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-rw-r--r--drivers/media/video/cx231xx/Kconfig35
-rw-r--r--drivers/media/video/cx231xx/Makefile14
-rw-r--r--drivers/media/video/cx231xx/cx231xx-audio.c586
-rw-r--r--drivers/media/video/cx231xx/cx231xx-avcore.c2581
-rw-r--r--drivers/media/video/cx231xx/cx231xx-cards.c914
-rw-r--r--drivers/media/video/cx231xx/cx231xx-conf-reg.h494
-rw-r--r--drivers/media/video/cx231xx/cx231xx-core.c1200
-rw-r--r--drivers/media/video/cx231xx/cx231xx-dvb.c559
-rw-r--r--drivers/media/video/cx231xx/cx231xx-i2c.c555
-rw-r--r--drivers/media/video/cx231xx/cx231xx-input.c246
-rw-r--r--drivers/media/video/cx231xx/cx231xx-pcb-cfg.c795
-rw-r--r--drivers/media/video/cx231xx/cx231xx-pcb-cfg.h231
-rw-r--r--drivers/media/video/cx231xx/cx231xx-reg.h1564
-rw-r--r--drivers/media/video/cx231xx/cx231xx-vbi.c701
-rw-r--r--drivers/media/video/cx231xx/cx231xx-vbi.h65
-rw-r--r--drivers/media/video/cx231xx/cx231xx-video.c2434
-rw-r--r--drivers/media/video/cx231xx/cx231xx.h779
17 files changed, 13753 insertions, 0 deletions
diff --git a/drivers/media/video/cx231xx/Kconfig b/drivers/media/video/cx231xx/Kconfig
new file mode 100644
index 000000000000..91156546a07a
--- /dev/null
+++ b/drivers/media/video/cx231xx/Kconfig
@@ -0,0 +1,35 @@
1config VIDEO_CX231XX
2 tristate "Conexant cx231xx USB video capture support"
3 depends on VIDEO_DEV && I2C && INPUT
4 select VIDEO_TUNER
5 select VIDEO_TVEEPROM
6 select VIDEO_IR
7 select VIDEOBUF_VMALLOC
8 select VIDEO_CX25840
9 select VIDEO_CX231XX_ALSA
10
11 ---help---
12 This is a video4linux driver for Conexant 231xx USB based TV cards.
13
14 To compile this driver as a module, choose M here: the
15 module will be called cx231xx
16
17config VIDEO_CX231XX_ALSA
18 tristate "Conexant Cx231xx ALSA audio module"
19 depends on VIDEO_CX231XX && SND
20 select SND_PCM
21
22 ---help---
23 This is an ALSA driver for Cx231xx USB based TV cards.
24
25 To compile this driver as a module, choose M here: the
26 module will be called cx231xx-alsa
27
28config VIDEO_CX231XX_DVB
29 tristate "DVB/ATSC Support for Cx231xx based TV cards"
30 depends on VIDEO_CX231XX && DVB_CORE
31 select VIDEOBUF_DVB
32 select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMISE
33 ---help---
34 This adds support for DVB cards based on the
35 Conexant cx231xx chips.
diff --git a/drivers/media/video/cx231xx/Makefile b/drivers/media/video/cx231xx/Makefile
new file mode 100644
index 000000000000..755dd0ce65ff
--- /dev/null
+++ b/drivers/media/video/cx231xx/Makefile
@@ -0,0 +1,14 @@
1cx231xx-objs := cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o \
2 cx231xx-avcore.o cx231xx-pcb-cfg.o cx231xx-vbi.o
3
4cx231xx-alsa-objs := cx231xx-audio.o
5
6obj-$(CONFIG_VIDEO_CX231XX) += cx231xx.o
7obj-$(CONFIG_VIDEO_CX231XX_ALSA) += cx231xx-alsa.o
8obj-$(CONFIG_VIDEO_CX231XX_DVB) += cx231xx-dvb.o
9
10EXTRA_CFLAGS += -Idrivers/media/video
11EXTRA_CFLAGS += -Idrivers/media/common/tuners
12EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
13EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
14
diff --git a/drivers/media/video/cx231xx/cx231xx-audio.c b/drivers/media/video/cx231xx/cx231xx-audio.c
new file mode 100644
index 000000000000..7793d60966db
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-audio.c
@@ -0,0 +1,586 @@
1/*
2 * Conexant Cx231xx audio extension
3 *
4 * Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5 * Based on em28xx driver
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/usb.h>
25#include <linux/init.h>
26#include <linux/sound.h>
27#include <linux/spinlock.h>
28#include <linux/soundcard.h>
29#include <linux/slab.h>
30#include <linux/vmalloc.h>
31#include <linux/proc_fs.h>
32#include <linux/module.h>
33#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/info.h>
37#include <sound/initval.h>
38#include <sound/control.h>
39#include <media/v4l2-common.h>
40#include "cx231xx.h"
41
42static int debug;
43module_param(debug, int, 0644);
44MODULE_PARM_DESC(debug, "activates debug info");
45
46#define dprintk(fmt, arg...) do { \
47 if (debug) \
48 printk(KERN_INFO "cx231xx-audio %s: " fmt, \
49 __func__, ##arg); \
50 } while (0)
51
52static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
53
54static int cx231xx_isoc_audio_deinit(struct cx231xx *dev)
55{
56 int i;
57
58 dprintk("Stopping isoc\n");
59
60 for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
61 if (dev->adev.urb[i]) {
62 if (!irqs_disabled())
63 usb_kill_urb(dev->adev.urb[i]);
64 else
65 usb_unlink_urb(dev->adev.urb[i]);
66
67 usb_free_urb(dev->adev.urb[i]);
68 dev->adev.urb[i] = NULL;
69
70 kfree(dev->adev.transfer_buffer[i]);
71 dev->adev.transfer_buffer[i] = NULL;
72 }
73 }
74
75 return 0;
76}
77
78static void cx231xx_audio_isocirq(struct urb *urb)
79{
80 struct cx231xx *dev = urb->context;
81 int i;
82 unsigned int oldptr;
83 int period_elapsed = 0;
84 int status;
85 unsigned char *cp;
86 unsigned int stride;
87 struct snd_pcm_substream *substream;
88 struct snd_pcm_runtime *runtime;
89
90 switch (urb->status) {
91 case 0: /* success */
92 case -ETIMEDOUT: /* NAK */
93 break;
94 case -ECONNRESET: /* kill */
95 case -ENOENT:
96 case -ESHUTDOWN:
97 return;
98 default: /* error */
99 dprintk("urb completition error %d.\n", urb->status);
100 break;
101 }
102
103 if (dev->adev.capture_pcm_substream) {
104 substream = dev->adev.capture_pcm_substream;
105 runtime = substream->runtime;
106 stride = runtime->frame_bits >> 3;
107
108 for (i = 0; i < urb->number_of_packets; i++) {
109 int length = urb->iso_frame_desc[i].actual_length /
110 stride;
111 cp = (unsigned char *)urb->transfer_buffer +
112 urb->iso_frame_desc[i].offset;
113
114 if (!length)
115 continue;
116
117 oldptr = dev->adev.hwptr_done_capture;
118 if (oldptr + length >= runtime->buffer_size) {
119 unsigned int cnt;
120
121 cnt = runtime->buffer_size - oldptr;
122 memcpy(runtime->dma_area + oldptr * stride, cp,
123 cnt * stride);
124 memcpy(runtime->dma_area, cp + cnt * stride,
125 length * stride - cnt * stride);
126 } else {
127 memcpy(runtime->dma_area + oldptr * stride, cp,
128 length * stride);
129 }
130
131 snd_pcm_stream_lock(substream);
132
133 dev->adev.hwptr_done_capture += length;
134 if (dev->adev.hwptr_done_capture >=
135 runtime->buffer_size)
136 dev->adev.hwptr_done_capture -=
137 runtime->buffer_size;
138
139 dev->adev.capture_transfer_done += length;
140 if (dev->adev.capture_transfer_done >=
141 runtime->period_size) {
142 dev->adev.capture_transfer_done -=
143 runtime->period_size;
144 period_elapsed = 1;
145 }
146 snd_pcm_stream_unlock(substream);
147 }
148 if (period_elapsed)
149 snd_pcm_period_elapsed(substream);
150 }
151 urb->status = 0;
152
153 status = usb_submit_urb(urb, GFP_ATOMIC);
154 if (status < 0) {
155 cx231xx_errdev("resubmit of audio urb failed (error=%i)\n",
156 status);
157 }
158 return;
159}
160
161static int cx231xx_init_audio_isoc(struct cx231xx *dev)
162{
163 int i, errCode;
164 int sb_size;
165
166 cx231xx_info("%s: Starting AUDIO transfers\n", __func__);
167
168 sb_size = CX231XX_NUM_AUDIO_PACKETS * dev->adev.max_pkt_size;
169
170 for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
171 struct urb *urb;
172 int j, k;
173
174 dev->adev.transfer_buffer[i] = kmalloc(sb_size, GFP_ATOMIC);
175 if (!dev->adev.transfer_buffer[i])
176 return -ENOMEM;
177
178 memset(dev->adev.transfer_buffer[i], 0x80, sb_size);
179 urb = usb_alloc_urb(CX231XX_NUM_AUDIO_PACKETS, GFP_ATOMIC);
180 if (!urb) {
181 cx231xx_errdev("usb_alloc_urb failed!\n");
182 for (j = 0; j < i; j++) {
183 usb_free_urb(dev->adev.urb[j]);
184 kfree(dev->adev.transfer_buffer[j]);
185 }
186 return -ENOMEM;
187 }
188
189 urb->dev = dev->udev;
190 urb->context = dev;
191 urb->pipe = usb_rcvisocpipe(dev->udev,
192 dev->adev.end_point_addr);
193 urb->transfer_flags = URB_ISO_ASAP;
194 urb->transfer_buffer = dev->adev.transfer_buffer[i];
195 urb->interval = 1;
196 urb->complete = cx231xx_audio_isocirq;
197 urb->number_of_packets = CX231XX_NUM_AUDIO_PACKETS;
198 urb->transfer_buffer_length = sb_size;
199
200 for (j = k = 0; j < CX231XX_NUM_AUDIO_PACKETS;
201 j++, k += dev->adev.max_pkt_size) {
202 urb->iso_frame_desc[j].offset = k;
203 urb->iso_frame_desc[j].length = dev->adev.max_pkt_size;
204 }
205 dev->adev.urb[i] = urb;
206 }
207
208 for (i = 0; i < CX231XX_AUDIO_BUFS; i++) {
209 errCode = usb_submit_urb(dev->adev.urb[i], GFP_ATOMIC);
210 if (errCode < 0) {
211 cx231xx_isoc_audio_deinit(dev);
212 return errCode;
213 }
214 }
215
216 return errCode;
217}
218
219static int cx231xx_cmd(struct cx231xx *dev, int cmd, int arg)
220{
221 dprintk("%s transfer\n", (dev->adev.capture_stream == STREAM_ON) ?
222 "stop" : "start");
223
224 switch (cmd) {
225 case CX231XX_CAPTURE_STREAM_EN:
226 if (dev->adev.capture_stream == STREAM_OFF && arg == 1) {
227 dev->adev.capture_stream = STREAM_ON;
228 cx231xx_init_audio_isoc(dev);
229 } else if (dev->adev.capture_stream == STREAM_ON && arg == 0) {
230 dev->adev.capture_stream = STREAM_OFF;
231 cx231xx_isoc_audio_deinit(dev);
232 } else {
233 cx231xx_errdev("An underrun very likely occurred. "
234 "Ignoring it.\n");
235 }
236 return 0;
237 default:
238 return -EINVAL;
239 }
240}
241
242static int snd_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs,
243 size_t size)
244{
245 struct snd_pcm_runtime *runtime = subs->runtime;
246
247 dprintk("Allocating vbuffer\n");
248 if (runtime->dma_area) {
249 if (runtime->dma_bytes > size)
250 return 0;
251
252 vfree(runtime->dma_area);
253 }
254 runtime->dma_area = vmalloc(size);
255 if (!runtime->dma_area)
256 return -ENOMEM;
257
258 runtime->dma_bytes = size;
259
260 return 0;
261}
262
263static struct snd_pcm_hardware snd_cx231xx_hw_capture = {
264 .info = SNDRV_PCM_INFO_BLOCK_TRANSFER |
265 SNDRV_PCM_INFO_MMAP |
266 SNDRV_PCM_INFO_INTERLEAVED |
267 SNDRV_PCM_INFO_MMAP_VALID,
268
269 .formats = SNDRV_PCM_FMTBIT_S16_LE,
270
271 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_KNOT,
272
273 .rate_min = 48000,
274 .rate_max = 48000,
275 .channels_min = 2,
276 .channels_max = 2,
277 .buffer_bytes_max = 62720 * 8, /* just about the value in usbaudio.c */
278 .period_bytes_min = 64, /* 12544/2, */
279 .period_bytes_max = 12544,
280 .periods_min = 2,
281 .periods_max = 98, /* 12544, */
282};
283
284static int snd_cx231xx_capture_open(struct snd_pcm_substream *substream)
285{
286 struct cx231xx *dev = snd_pcm_substream_chip(substream);
287 struct snd_pcm_runtime *runtime = substream->runtime;
288 int ret = 0;
289
290 dprintk("opening device and trying to acquire exclusive lock\n");
291
292 if (!dev) {
293 cx231xx_errdev("BUG: cx231xx can't find device struct."
294 " Can't proceed with open\n");
295 return -ENODEV;
296 }
297
298 /* Sets volume, mute, etc */
299 dev->mute = 0;
300
301 /* set alternate setting for audio interface */
302 /* 1 - 48000 samples per sec */
303 ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 1);
304 if (ret < 0) {
305 cx231xx_errdev("failed to set alternate setting !\n");
306
307 return ret;
308 }
309
310 /* inform hardware to start streaming */
311 ret = cx231xx_capture_start(dev, 1, Audio);
312
313 runtime->hw = snd_cx231xx_hw_capture;
314
315 mutex_lock(&dev->lock);
316 dev->adev.users++;
317 mutex_unlock(&dev->lock);
318
319 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
320 dev->adev.capture_pcm_substream = substream;
321 runtime->private_data = dev;
322
323 return 0;
324}
325
326static int snd_cx231xx_pcm_close(struct snd_pcm_substream *substream)
327{
328 int ret;
329 struct cx231xx *dev = snd_pcm_substream_chip(substream);
330
331 dprintk("closing device\n");
332
333 /* set alternate setting for audio interface */
334 /* 1 - 48000 samples per sec */
335 ret = cx231xx_set_alt_setting(dev, INDEX_AUDIO, 0);
336 if (ret < 0) {
337 cx231xx_errdev("failed to set alternate setting !\n");
338
339 return ret;
340 }
341
342 /* inform hardware to start streaming */
343 ret = cx231xx_capture_start(dev, 0, Audio);
344
345 dev->mute = 1;
346 mutex_lock(&dev->lock);
347 dev->adev.users--;
348 mutex_unlock(&dev->lock);
349
350 if (dev->adev.users == 0 && dev->adev.shutdown == 1) {
351 dprintk("audio users: %d\n", dev->adev.users);
352 dprintk("disabling audio stream!\n");
353 dev->adev.shutdown = 0;
354 dprintk("released lock\n");
355 cx231xx_cmd(dev, CX231XX_CAPTURE_STREAM_EN, 0);
356 }
357 return 0;
358}
359
360static int snd_cx231xx_hw_capture_params(struct snd_pcm_substream *substream,
361 struct snd_pcm_hw_params *hw_params)
362{
363 unsigned int channels, rate, format;
364 int ret;
365
366 dprintk("Setting capture parameters\n");
367
368 ret = snd_pcm_alloc_vmalloc_buffer(substream,
369 params_buffer_bytes(hw_params));
370 format = params_format(hw_params);
371 rate = params_rate(hw_params);
372 channels = params_channels(hw_params);
373
374 /* TODO: set up cx231xx audio chip to deliver the correct audio format,
375 current default is 48000hz multiplexed => 96000hz mono
376 which shouldn't matter since analogue TV only supports mono */
377 return 0;
378}
379
380static int snd_cx231xx_hw_capture_free(struct snd_pcm_substream *substream)
381{
382 struct cx231xx *dev = snd_pcm_substream_chip(substream);
383
384 dprintk("Stop capture, if needed\n");
385
386 if (dev->adev.capture_stream == STREAM_ON)
387 cx231xx_cmd(dev, CX231XX_CAPTURE_STREAM_EN, CX231XX_STOP_AUDIO);
388
389 return 0;
390}
391
392static int snd_cx231xx_prepare(struct snd_pcm_substream *substream)
393{
394 return 0;
395}
396
397static int snd_cx231xx_capture_trigger(struct snd_pcm_substream *substream,
398 int cmd)
399{
400 struct cx231xx *dev = snd_pcm_substream_chip(substream);
401 int retval;
402
403 dprintk("Should %s capture\n", (cmd == SNDRV_PCM_TRIGGER_START) ?
404 "start" : "stop");
405
406 spin_lock(&dev->adev.slock);
407 switch (cmd) {
408 case SNDRV_PCM_TRIGGER_START:
409 cx231xx_cmd(dev, CX231XX_CAPTURE_STREAM_EN,
410 CX231XX_START_AUDIO);
411 retval = 0;
412 break;
413 case SNDRV_PCM_TRIGGER_STOP:
414 cx231xx_cmd(dev, CX231XX_CAPTURE_STREAM_EN, CX231XX_STOP_AUDIO);
415 retval = 0;
416 break;
417 default:
418 retval = -EINVAL;
419 }
420
421 spin_unlock(&dev->adev.slock);
422 return retval;
423}
424
425static snd_pcm_uframes_t snd_cx231xx_capture_pointer(struct snd_pcm_substream
426 *substream)
427{
428 struct cx231xx *dev;
429 unsigned long flags;
430 snd_pcm_uframes_t hwptr_done;
431
432 dev = snd_pcm_substream_chip(substream);
433
434 spin_lock_irqsave(&dev->adev.slock, flags);
435 hwptr_done = dev->adev.hwptr_done_capture;
436 spin_unlock_irqrestore(&dev->adev.slock, flags);
437
438 return hwptr_done;
439}
440
441static struct page *snd_pcm_get_vmalloc_page(struct snd_pcm_substream *subs,
442 unsigned long offset)
443{
444 void *pageptr = subs->runtime->dma_area + offset;
445
446 return vmalloc_to_page(pageptr);
447}
448
449static struct snd_pcm_ops snd_cx231xx_pcm_capture = {
450 .open = snd_cx231xx_capture_open,
451 .close = snd_cx231xx_pcm_close,
452 .ioctl = snd_pcm_lib_ioctl,
453 .hw_params = snd_cx231xx_hw_capture_params,
454 .hw_free = snd_cx231xx_hw_capture_free,
455 .prepare = snd_cx231xx_prepare,
456 .trigger = snd_cx231xx_capture_trigger,
457 .pointer = snd_cx231xx_capture_pointer,
458 .page = snd_pcm_get_vmalloc_page,
459};
460
461static int cx231xx_audio_init(struct cx231xx *dev)
462{
463 struct cx231xx_audio *adev = &dev->adev;
464 struct snd_pcm *pcm;
465 struct snd_card *card;
466 static int devnr;
467 int err;
468 struct usb_interface *uif;
469 int i, isoc_pipe = 0;
470
471 if (dev->has_alsa_audio != 1) {
472 /* This device does not support the extension (in this case
473 the device is expecting the snd-usb-audio module or
474 doesn't have analog audio support at all) */
475 return 0;
476 }
477
478 cx231xx_info("cx231xx-audio.c: probing for cx231xx "
479 "non standard usbaudio\n");
480
481 err = snd_card_create(index[devnr], "Cx231xx Audio", THIS_MODULE,
482 0, &card);
483 if (err < 0)
484 return err;
485
486 spin_lock_init(&adev->slock);
487 err = snd_pcm_new(card, "Cx231xx Audio", 0, 0, 1, &pcm);
488 if (err < 0) {
489 snd_card_free(card);
490 return err;
491 }
492
493 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
494 &snd_cx231xx_pcm_capture);
495 pcm->info_flags = 0;
496 pcm->private_data = dev;
497 strcpy(pcm->name, "Conexant cx231xx Capture");
498 strcpy(card->driver, "Conexant cx231xx Audio");
499 strcpy(card->shortname, "Cx231xx Audio");
500 strcpy(card->longname, "Conexant cx231xx Audio");
501
502 err = snd_card_register(card);
503 if (err < 0) {
504 snd_card_free(card);
505 return err;
506 }
507 adev->sndcard = card;
508 adev->udev = dev->udev;
509
510 /* compute alternate max packet sizes for Audio */
511 uif =
512 dev->udev->actconfig->interface[dev->current_pcb_config.
513 hs_config_info[0].interface_info.
514 audio_index + 1];
515
516 adev->end_point_addr =
517 le16_to_cpu(uif->altsetting[0].endpoint[isoc_pipe].desc.
518 bEndpointAddress);
519
520 adev->num_alt = uif->num_altsetting;
521 cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
522 adev->end_point_addr, adev->num_alt);
523 adev->alt_max_pkt_size = kmalloc(32 * adev->num_alt, GFP_KERNEL);
524
525 if (adev->alt_max_pkt_size == NULL) {
526 cx231xx_errdev("out of memory!\n");
527 return -ENOMEM;
528 }
529
530 for (i = 0; i < adev->num_alt; i++) {
531 u16 tmp =
532 le16_to_cpu(uif->altsetting[i].endpoint[isoc_pipe].desc.
533 wMaxPacketSize);
534 adev->alt_max_pkt_size[i] =
535 (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
536 cx231xx_info("Alternate setting %i, max size= %i\n", i,
537 adev->alt_max_pkt_size[i]);
538 }
539
540 return 0;
541}
542
543static int cx231xx_audio_fini(struct cx231xx *dev)
544{
545 if (dev == NULL)
546 return 0;
547
548 if (dev->has_alsa_audio != 1) {
549 /* This device does not support the extension (in this case
550 the device is expecting the snd-usb-audio module or
551 doesn't have analog audio support at all) */
552 return 0;
553 }
554
555 if (dev->adev.sndcard) {
556 snd_card_free(dev->adev.sndcard);
557 kfree(dev->adev.alt_max_pkt_size);
558 dev->adev.sndcard = NULL;
559 }
560
561 return 0;
562}
563
564static struct cx231xx_ops audio_ops = {
565 .id = CX231XX_AUDIO,
566 .name = "Cx231xx Audio Extension",
567 .init = cx231xx_audio_init,
568 .fini = cx231xx_audio_fini,
569};
570
571static int __init cx231xx_alsa_register(void)
572{
573 return cx231xx_register_extension(&audio_ops);
574}
575
576static void __exit cx231xx_alsa_unregister(void)
577{
578 cx231xx_unregister_extension(&audio_ops);
579}
580
581MODULE_LICENSE("GPL");
582MODULE_AUTHOR("Srinivasa Deevi <srinivasa.deevi@conexant.com>");
583MODULE_DESCRIPTION("Cx231xx Audio driver");
584
585module_init(cx231xx_alsa_register);
586module_exit(cx231xx_alsa_unregister);
diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c
new file mode 100644
index 000000000000..1be3881be991
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-avcore.c
@@ -0,0 +1,2581 @@
1/*
2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#include <linux/init.h>
26#include <linux/list.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/bitmap.h>
30#include <linux/usb.h>
31#include <linux/i2c.h>
32#include <linux/version.h>
33#include <linux/mm.h>
34#include <linux/mutex.h>
35
36#include <media/v4l2-common.h>
37#include <media/v4l2-ioctl.h>
38#include <media/v4l2-chip-ident.h>
39
40#include "cx231xx.h"
41
42/******************************************************************************
43 -: BLOCK ARRANGEMENT :-
44 I2S block ----------------------|
45 [I2S audio] |
46 |
47 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
48 [video & audio] | [Audio]
49 |
50 |-> Cx25840 --> Video
51 [Video]
52
53*******************************************************************************/
54
55/******************************************************************************
56 * A F E - B L O C K C O N T R O L functions *
57 * [ANALOG FRONT END] *
58 ******************************************************************************/
59static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
60{
61 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
62 saddr, 2, data, 1);
63}
64
65static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
66{
67 int status;
68 u32 temp = 0;
69
70 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
71 saddr, 2, &temp, 1);
72 *data = (u8) temp;
73 return status;
74}
75
76int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
77{
78 int status = 0;
79 u8 temp = 0;
80 u8 afe_power_status = 0;
81 int i = 0;
82
83 /* super block initialize */
84 temp = (u8) (ref_count & 0xff);
85 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
86 if (status < 0)
87 return status;
88
89 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
90 if (status < 0)
91 return status;
92
93 temp = (u8) ((ref_count & 0x300) >> 8);
94 temp |= 0x40;
95 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
96 if (status < 0)
97 return status;
98
99 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
100 if (status < 0)
101 return status;
102
103 /* enable pll */
104 while (afe_power_status != 0x18) {
105 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
106 if (status < 0) {
107 cx231xx_info(
108 ": Init Super Block failed in send cmd\n");
109 break;
110 }
111
112 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
113 afe_power_status &= 0xff;
114 if (status < 0) {
115 cx231xx_info(
116 ": Init Super Block failed in receive cmd\n");
117 break;
118 }
119 i++;
120 if (i == 10) {
121 cx231xx_info(
122 ": Init Super Block force break in loop !!!!\n");
123 status = -1;
124 break;
125 }
126 }
127
128 if (status < 0)
129 return status;
130
131 /* start tuning filter */
132 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
133 if (status < 0)
134 return status;
135
136 msleep(5);
137
138 /* exit tuning */
139 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
140
141 return status;
142}
143
144int cx231xx_afe_init_channels(struct cx231xx *dev)
145{
146 int status = 0;
147
148 /* power up all 3 channels, clear pd_buffer */
149 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
150 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
151 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
152
153 /* Enable quantizer calibration */
154 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
155
156 /* channel initialize, force modulator (fb) reset */
157 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
158 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
159 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
160
161 /* start quantilizer calibration */
162 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
163 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
164 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
165 msleep(5);
166
167 /* exit modulator (fb) reset */
168 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
169 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
170 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
171
172 /* enable the pre_clamp in each channel for single-ended input */
173 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
174 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
175 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
176
177 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
178 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
179 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
180 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
181 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
182 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
183 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
184
185 /* dynamic element matching off */
186 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
187 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
188 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
189
190 return status;
191}
192
193int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
194{
195 u8 c_value = 0;
196 int status = 0;
197
198 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
199 c_value &= (~(0x50));
200 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
201
202 return status;
203}
204
205/*
206 The Analog Front End in Cx231xx has 3 channels. These
207 channels are used to share between different inputs
208 like tuner, s-video and composite inputs.
209
210 channel 1 ----- pin 1 to pin4(in reg is 1-4)
211 channel 2 ----- pin 5 to pin8(in reg is 5-8)
212 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
213*/
214int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
215{
216 u8 ch1_setting = (u8) input_mux;
217 u8 ch2_setting = (u8) (input_mux >> 8);
218 u8 ch3_setting = (u8) (input_mux >> 16);
219 int status = 0;
220 u8 value = 0;
221
222 if (ch1_setting != 0) {
223 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
224 value &= (!INPUT_SEL_MASK);
225 value |= (ch1_setting - 1) << 4;
226 value &= 0xff;
227 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
228 }
229
230 if (ch2_setting != 0) {
231 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
232 value &= (!INPUT_SEL_MASK);
233 value |= (ch2_setting - 1) << 4;
234 value &= 0xff;
235 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
236 }
237
238 /* For ch3_setting, the value to put in the register is
239 7 less than the input number */
240 if (ch3_setting != 0) {
241 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
242 value &= (!INPUT_SEL_MASK);
243 value |= (ch3_setting - 1) << 4;
244 value &= 0xff;
245 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
246 }
247
248 return status;
249}
250
251int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
252{
253 int status = 0;
254
255 /*
256 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
257 * Currently, only baseband works.
258 */
259
260 switch (mode) {
261 case AFE_MODE_LOW_IF:
262 /* SetupAFEforLowIF(); */
263 break;
264 case AFE_MODE_BASEBAND:
265 status = cx231xx_afe_setup_AFE_for_baseband(dev);
266 break;
267 case AFE_MODE_EU_HI_IF:
268 /* SetupAFEforEuHiIF(); */
269 break;
270 case AFE_MODE_US_HI_IF:
271 /* SetupAFEforUsHiIF(); */
272 break;
273 case AFE_MODE_JAPAN_HI_IF:
274 /* SetupAFEforJapanHiIF(); */
275 break;
276 }
277
278 if ((mode != dev->afe_mode) &&
279 (dev->video_input == CX231XX_VMUX_TELEVISION))
280 status = cx231xx_afe_adjust_ref_count(dev,
281 CX231XX_VMUX_TELEVISION);
282
283 dev->afe_mode = mode;
284
285 return status;
286}
287
288int cx231xx_afe_update_power_control(struct cx231xx *dev,
289 enum AV_MODE avmode)
290{
291 u8 afe_power_status = 0;
292 int status = 0;
293
294 switch (dev->model) {
295 case CX231XX_BOARD_CNXT_RDE_250:
296 case CX231XX_BOARD_CNXT_RDU_250:
297 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
298 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
299 FLD_PWRDN_ENABLE_PLL)) {
300 status = afe_write_byte(dev, SUP_BLK_PWRDN,
301 FLD_PWRDN_TUNING_BIAS |
302 FLD_PWRDN_ENABLE_PLL);
303 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
304 &afe_power_status);
305 if (status < 0)
306 break;
307 }
308
309 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
310 0x00);
311 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
312 0x00);
313 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
314 0x00);
315 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
316 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
317 0x70);
318 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
319 0x70);
320 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
321 0x70);
322
323 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
324 &afe_power_status);
325 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
326 FLD_PWRDN_PD_BIAS |
327 FLD_PWRDN_PD_TUNECK;
328 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
329 afe_power_status);
330 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
331 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
332 FLD_PWRDN_ENABLE_PLL)) {
333 status = afe_write_byte(dev, SUP_BLK_PWRDN,
334 FLD_PWRDN_TUNING_BIAS |
335 FLD_PWRDN_ENABLE_PLL);
336 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
337 &afe_power_status);
338 if (status < 0)
339 break;
340 }
341
342 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
343 0x00);
344 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
345 0x00);
346 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
347 0x00);
348 } else {
349 cx231xx_info("Invalid AV mode input\n");
350 status = -1;
351 }
352 break;
353 default:
354 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
355 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
356 FLD_PWRDN_ENABLE_PLL)) {
357 status = afe_write_byte(dev, SUP_BLK_PWRDN,
358 FLD_PWRDN_TUNING_BIAS |
359 FLD_PWRDN_ENABLE_PLL);
360 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
361 &afe_power_status);
362 if (status < 0)
363 break;
364 }
365
366 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
367 0x40);
368 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
369 0x40);
370 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
371 0x00);
372 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
373 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
374 0x70);
375 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
376 0x70);
377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
378 0x70);
379
380 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
381 &afe_power_status);
382 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
383 FLD_PWRDN_PD_BIAS |
384 FLD_PWRDN_PD_TUNECK;
385 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
386 afe_power_status);
387 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
388 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
389 FLD_PWRDN_ENABLE_PLL)) {
390 status = afe_write_byte(dev, SUP_BLK_PWRDN,
391 FLD_PWRDN_TUNING_BIAS |
392 FLD_PWRDN_ENABLE_PLL);
393 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
394 &afe_power_status);
395 if (status < 0)
396 break;
397 }
398
399 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
400 0x00);
401 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
402 0x00);
403 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
404 0x40);
405 } else {
406 cx231xx_info("Invalid AV mode input\n");
407 status = -1;
408 }
409 } /* switch */
410
411 return status;
412}
413
414int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
415{
416 u8 input_mode = 0;
417 u8 ntf_mode = 0;
418 int status = 0;
419
420 dev->video_input = video_input;
421
422 if (video_input == CX231XX_VMUX_TELEVISION) {
423 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
424 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
425 &ntf_mode);
426 } else {
427 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
428 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
429 &ntf_mode);
430 }
431
432 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
433
434 switch (input_mode) {
435 case SINGLE_ENDED:
436 dev->afe_ref_count = 0x23C;
437 break;
438 case LOW_IF:
439 dev->afe_ref_count = 0x24C;
440 break;
441 case EU_IF:
442 dev->afe_ref_count = 0x258;
443 break;
444 case US_IF:
445 dev->afe_ref_count = 0x260;
446 break;
447 default:
448 break;
449 }
450
451 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
452
453 return status;
454}
455
456/******************************************************************************
457 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
458 ******************************************************************************/
459static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
460{
461 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
462 saddr, 2, data, 1);
463}
464
465static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
466{
467 int status;
468 u32 temp = 0;
469
470 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
471 saddr, 2, &temp, 1);
472 *data = (u8) temp;
473 return status;
474}
475
476static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
477{
478 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
479 saddr, 2, data, 4);
480}
481
482static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
483{
484 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
485 saddr, 2, data, 4);
486}
487
488int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
489{
490 int status = 0;
491
492 switch (INPUT(input)->type) {
493 case CX231XX_VMUX_COMPOSITE1:
494 case CX231XX_VMUX_SVIDEO:
495 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
496 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
497 /* External AV */
498 status = cx231xx_set_power_mode(dev,
499 POLARIS_AVMODE_ENXTERNAL_AV);
500 if (status < 0) {
501 cx231xx_errdev("%s: set_power_mode : Failed to"
502 " set Power - errCode [%d]!\n",
503 __func__, status);
504 return status;
505 }
506 }
507 status = cx231xx_set_decoder_video_input(dev,
508 INPUT(input)->type,
509 INPUT(input)->vmux);
510 break;
511 case CX231XX_VMUX_TELEVISION:
512 case CX231XX_VMUX_CABLE:
513 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
514 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
515 /* Tuner */
516 status = cx231xx_set_power_mode(dev,
517 POLARIS_AVMODE_ANALOGT_TV);
518 if (status < 0) {
519 cx231xx_errdev("%s: set_power_mode:Failed"
520 " to set Power - errCode [%d]!\n",
521 __func__, status);
522 return status;
523 }
524 }
525 status = cx231xx_set_decoder_video_input(dev,
526 CX231XX_VMUX_COMPOSITE1,
527 INPUT(input)->vmux);
528 break;
529 default:
530 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
531 __func__, INPUT(input)->type);
532 break;
533 }
534
535 /* save the selection */
536 dev->video_input = input;
537
538 return status;
539}
540
541int cx231xx_set_decoder_video_input(struct cx231xx *dev,
542 u8 pin_type, u8 input)
543{
544 int status = 0;
545 u32 value = 0;
546
547 if (pin_type != dev->video_input) {
548 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
549 if (status < 0) {
550 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
551 "AFE input mux - errCode [%d]!\n",
552 __func__, status);
553 return status;
554 }
555 }
556
557 /* call afe block to set video inputs */
558 status = cx231xx_afe_set_input_mux(dev, input);
559 if (status < 0) {
560 cx231xx_errdev("%s: set_input_mux :Failed to set"
561 " AFE input mux - errCode [%d]!\n",
562 __func__, status);
563 return status;
564 }
565
566 switch (pin_type) {
567 case CX231XX_VMUX_COMPOSITE1:
568 status = vid_blk_read_word(dev, AFE_CTRL, &value);
569 value |= (0 << 13) | (1 << 4);
570 value &= ~(1 << 5);
571
572 /* set [24:23] [22:15] to 0 */
573 value &= (~(0x1ff8000));
574 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
575 value |= 0x1000000;
576 status = vid_blk_write_word(dev, AFE_CTRL, value);
577
578 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
579 value |= (1 << 7);
580 status = vid_blk_write_word(dev, OUT_CTRL1, value);
581
582 /* Set vip 1.1 output mode */
583 status = cx231xx_read_modify_write_i2c_dword(dev,
584 VID_BLK_I2C_ADDRESS,
585 OUT_CTRL1,
586 FLD_OUT_MODE,
587 OUT_MODE_VIP11);
588
589 /* Tell DIF object to go to baseband mode */
590 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
591 if (status < 0) {
592 cx231xx_errdev("%s: cx231xx_dif set to By pass"
593 " mode- errCode [%d]!\n",
594 __func__, status);
595 return status;
596 }
597
598 /* Read the DFE_CTRL1 register */
599 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
600
601 /* enable the VBI_GATE_EN */
602 value |= FLD_VBI_GATE_EN;
603
604 /* Enable the auto-VGA enable */
605 value |= FLD_VGA_AUTO_EN;
606
607 /* Write it back */
608 status = vid_blk_write_word(dev, DFE_CTRL1, value);
609
610 /* Disable auto config of registers */
611 status = cx231xx_read_modify_write_i2c_dword(dev,
612 VID_BLK_I2C_ADDRESS,
613 MODE_CTRL, FLD_ACFG_DIS,
614 cx231xx_set_field(FLD_ACFG_DIS, 1));
615
616 /* Set CVBS input mode */
617 status = cx231xx_read_modify_write_i2c_dword(dev,
618 VID_BLK_I2C_ADDRESS,
619 MODE_CTRL, FLD_INPUT_MODE,
620 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
621 break;
622 case CX231XX_VMUX_SVIDEO:
623 /* Disable the use of DIF */
624
625 status = vid_blk_read_word(dev, AFE_CTRL, &value);
626
627 /* set [24:23] [22:15] to 0 */
628 value &= (~(0x1ff8000));
629 /* set FUNC_MODE[24:23] = 2
630 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
631 value |= 0x1000010;
632 status = vid_blk_write_word(dev, AFE_CTRL, value);
633
634 /* Tell DIF object to go to baseband mode */
635 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
636 if (status < 0) {
637 cx231xx_errdev("%s: cx231xx_dif set to By pass"
638 " mode- errCode [%d]!\n",
639 __func__, status);
640 return status;
641 }
642
643 /* Read the DFE_CTRL1 register */
644 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
645
646 /* enable the VBI_GATE_EN */
647 value |= FLD_VBI_GATE_EN;
648
649 /* Enable the auto-VGA enable */
650 value |= FLD_VGA_AUTO_EN;
651
652 /* Write it back */
653 status = vid_blk_write_word(dev, DFE_CTRL1, value);
654
655 /* Disable auto config of registers */
656 status = cx231xx_read_modify_write_i2c_dword(dev,
657 VID_BLK_I2C_ADDRESS,
658 MODE_CTRL, FLD_ACFG_DIS,
659 cx231xx_set_field(FLD_ACFG_DIS, 1));
660
661 /* Set YC input mode */
662 status = cx231xx_read_modify_write_i2c_dword(dev,
663 VID_BLK_I2C_ADDRESS,
664 MODE_CTRL,
665 FLD_INPUT_MODE,
666 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
667
668 /* Chroma to ADC2 */
669 status = vid_blk_read_word(dev, AFE_CTRL, &value);
670 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
671
672 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
673 This sets them to use video
674 rather than audio. Only one of the two will be in use. */
675 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
676
677 status = vid_blk_write_word(dev, AFE_CTRL, value);
678
679 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
680 break;
681 case CX231XX_VMUX_TELEVISION:
682 case CX231XX_VMUX_CABLE:
683 default:
684 switch (dev->model) {
685 case CX231XX_BOARD_CNXT_RDE_250:
686 case CX231XX_BOARD_CNXT_RDU_250:
687 /* Disable the use of DIF */
688
689 status = vid_blk_read_word(dev, AFE_CTRL, &value);
690 value |= (0 << 13) | (1 << 4);
691 value &= ~(1 << 5);
692
693 /* set [24:23] [22:15] to 0 */
694 value &= (~(0x1FF8000));
695 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
696 value |= 0x1000000;
697 status = vid_blk_write_word(dev, AFE_CTRL, value);
698
699 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
700 value |= (1 << 7);
701 status = vid_blk_write_word(dev, OUT_CTRL1, value);
702
703 /* Set vip 1.1 output mode */
704 status = cx231xx_read_modify_write_i2c_dword(dev,
705 VID_BLK_I2C_ADDRESS,
706 OUT_CTRL1, FLD_OUT_MODE,
707 OUT_MODE_VIP11);
708
709 /* Tell DIF object to go to baseband mode */
710 status = cx231xx_dif_set_standard(dev,
711 DIF_USE_BASEBAND);
712 if (status < 0) {
713 cx231xx_errdev("%s: cx231xx_dif set to By pass"
714 " mode- errCode [%d]!\n",
715 __func__, status);
716 return status;
717 }
718
719 /* Read the DFE_CTRL1 register */
720 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
721
722 /* enable the VBI_GATE_EN */
723 value |= FLD_VBI_GATE_EN;
724
725 /* Enable the auto-VGA enable */
726 value |= FLD_VGA_AUTO_EN;
727
728 /* Write it back */
729 status = vid_blk_write_word(dev, DFE_CTRL1, value);
730
731 /* Disable auto config of registers */
732 status = cx231xx_read_modify_write_i2c_dword(dev,
733 VID_BLK_I2C_ADDRESS,
734 MODE_CTRL, FLD_ACFG_DIS,
735 cx231xx_set_field(FLD_ACFG_DIS, 1));
736
737 /* Set CVBS input mode */
738 status = cx231xx_read_modify_write_i2c_dword(dev,
739 VID_BLK_I2C_ADDRESS,
740 MODE_CTRL, FLD_INPUT_MODE,
741 cx231xx_set_field(FLD_INPUT_MODE,
742 INPUT_MODE_CVBS_0));
743 break;
744 default:
745 /* Enable the DIF for the tuner */
746
747 /* Reinitialize the DIF */
748 status = cx231xx_dif_set_standard(dev, dev->norm);
749 if (status < 0) {
750 cx231xx_errdev("%s: cx231xx_dif set to By pass"
751 " mode- errCode [%d]!\n",
752 __func__, status);
753 return status;
754 }
755
756 /* Make sure bypass is cleared */
757 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
758
759 /* Clear the bypass bit */
760 value &= ~FLD_DIF_DIF_BYPASS;
761
762 /* Enable the use of the DIF block */
763 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
764
765 /* Read the DFE_CTRL1 register */
766 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
767
768 /* Disable the VBI_GATE_EN */
769 value &= ~FLD_VBI_GATE_EN;
770
771 /* Enable the auto-VGA enable, AGC, and
772 set the skip count to 2 */
773 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
774
775 /* Write it back */
776 status = vid_blk_write_word(dev, DFE_CTRL1, value);
777
778 /* Wait until AGC locks up */
779 msleep(1);
780
781 /* Disable the auto-VGA enable AGC */
782 value &= ~(FLD_VGA_AUTO_EN);
783
784 /* Write it back */
785 status = vid_blk_write_word(dev, DFE_CTRL1, value);
786
787 /* Enable Polaris B0 AGC output */
788 status = vid_blk_read_word(dev, PIN_CTRL, &value);
789 value |= (FLD_OEF_AGC_RF) |
790 (FLD_OEF_AGC_IFVGA) |
791 (FLD_OEF_AGC_IF);
792 status = vid_blk_write_word(dev, PIN_CTRL, value);
793
794 /* Set vip 1.1 output mode */
795 status = cx231xx_read_modify_write_i2c_dword(dev,
796 VID_BLK_I2C_ADDRESS,
797 OUT_CTRL1, FLD_OUT_MODE,
798 OUT_MODE_VIP11);
799
800 /* Disable auto config of registers */
801 status = cx231xx_read_modify_write_i2c_dword(dev,
802 VID_BLK_I2C_ADDRESS,
803 MODE_CTRL, FLD_ACFG_DIS,
804 cx231xx_set_field(FLD_ACFG_DIS, 1));
805
806 /* Set CVBS input mode */
807 status = cx231xx_read_modify_write_i2c_dword(dev,
808 VID_BLK_I2C_ADDRESS,
809 MODE_CTRL, FLD_INPUT_MODE,
810 cx231xx_set_field(FLD_INPUT_MODE,
811 INPUT_MODE_CVBS_0));
812
813 /* Set some bits in AFE_CTRL so that channel 2 or 3
814 * is ready to receive audio */
815 /* Clear clamp for channels 2 and 3 (bit 16-17) */
816 /* Clear droop comp (bit 19-20) */
817 /* Set VGA_SEL (for audio control) (bit 7-8) */
818 status = vid_blk_read_word(dev, AFE_CTRL, &value);
819
820 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
821
822 status = vid_blk_write_word(dev, AFE_CTRL, value);
823 break;
824
825 }
826 break;
827 }
828
829 /* Set raw VBI mode */
830 status = cx231xx_read_modify_write_i2c_dword(dev,
831 VID_BLK_I2C_ADDRESS,
832 OUT_CTRL1, FLD_VBIHACTRAW_EN,
833 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
834
835 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
836 if (value & 0x02) {
837 value |= (1 << 19);
838 status = vid_blk_write_word(dev, OUT_CTRL1, value);
839 }
840
841 return status;
842}
843
844/*
845 * Handle any video-mode specific overrides that are different
846 * on a per video standards basis after touching the MODE_CTRL
847 * register which resets many values for autodetect
848 */
849int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
850{
851 int status = 0;
852
853 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
854 (unsigned int)dev->norm);
855
856 /* Change the DFE_CTRL3 bp_percent to fix flagging */
857 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
858
859 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
860 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
861
862 /* Move the close caption lines out of active video,
863 adjust the active video start point */
864 status = cx231xx_read_modify_write_i2c_dword(dev,
865 VID_BLK_I2C_ADDRESS,
866 VERT_TIM_CTRL,
867 FLD_VBLANK_CNT, 0x18);
868 status = cx231xx_read_modify_write_i2c_dword(dev,
869 VID_BLK_I2C_ADDRESS,
870 VERT_TIM_CTRL,
871 FLD_VACTIVE_CNT,
872 0x1E6000);
873 status = cx231xx_read_modify_write_i2c_dword(dev,
874 VID_BLK_I2C_ADDRESS,
875 VERT_TIM_CTRL,
876 FLD_V656BLANK_CNT,
877 0x1E000000);
878
879 status = cx231xx_read_modify_write_i2c_dword(dev,
880 VID_BLK_I2C_ADDRESS,
881 HORIZ_TIM_CTRL,
882 FLD_HBLANK_CNT,
883 cx231xx_set_field
884 (FLD_HBLANK_CNT, 0x79));
885 } else if (dev->norm & V4L2_STD_SECAM) {
886 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
887 status = cx231xx_read_modify_write_i2c_dword(dev,
888 VID_BLK_I2C_ADDRESS,
889 VERT_TIM_CTRL,
890 FLD_VBLANK_CNT, 0x24);
891 /* Adjust the active video horizontal start point */
892 status = cx231xx_read_modify_write_i2c_dword(dev,
893 VID_BLK_I2C_ADDRESS,
894 HORIZ_TIM_CTRL,
895 FLD_HBLANK_CNT,
896 cx231xx_set_field
897 (FLD_HBLANK_CNT, 0x85));
898 } else {
899 cx231xx_info("do_mode_ctrl_overrides PAL\n");
900 status = cx231xx_read_modify_write_i2c_dword(dev,
901 VID_BLK_I2C_ADDRESS,
902 VERT_TIM_CTRL,
903 FLD_VBLANK_CNT, 0x24);
904 /* Adjust the active video horizontal start point */
905 status = cx231xx_read_modify_write_i2c_dword(dev,
906 VID_BLK_I2C_ADDRESS,
907 HORIZ_TIM_CTRL,
908 FLD_HBLANK_CNT,
909 cx231xx_set_field
910 (FLD_HBLANK_CNT, 0x85));
911 }
912
913 return status;
914}
915
916int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
917{
918 int status = 0;
919 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
920
921 switch (INPUT(input)->amux) {
922 case CX231XX_AMUX_VIDEO:
923 ainput = AUDIO_INPUT_TUNER_TV;
924 break;
925 case CX231XX_AMUX_LINE_IN:
926 status = cx231xx_i2s_blk_set_audio_input(dev, input);
927 ainput = AUDIO_INPUT_LINE;
928 break;
929 default:
930 break;
931 }
932
933 status = cx231xx_set_audio_decoder_input(dev, ainput);
934
935 return status;
936}
937
938int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
939 enum AUDIO_INPUT audio_input)
940{
941 u32 dwval;
942 int status;
943 u8 gen_ctrl;
944 u32 value = 0;
945
946 /* Put it in soft reset */
947 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
948 gen_ctrl |= 1;
949 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
950
951 switch (audio_input) {
952 case AUDIO_INPUT_LINE:
953 /* setup AUD_IO control from Merlin paralle output */
954 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
955 AUD_CHAN_SRC_PARALLEL);
956 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
957
958 /* setup input to Merlin, SRC2 connect to AC97
959 bypass upsample-by-2, slave mode, sony mode, left justify
960 adr 091c, dat 01000000 */
961 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
962
963 status = vid_blk_write_word(dev, AC97_CTL,
964 (dwval | FLD_AC97_UP2X_BYPASS));
965
966 /* select the parallel1 and SRC3 */
967 status = vid_blk_write_word(dev, BAND_OUT_SEL,
968 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
969 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
970 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
971
972 /* unmute all, AC97 in, independence mode
973 adr 08d0, data 0x00063073 */
974 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
975
976 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
977 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
978 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
979 (dwval | FLD_PATH1_AVC_THRESHOLD));
980
981 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
982 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
983 status = vid_blk_write_word(dev, PATH1_SC_CTL,
984 (dwval | FLD_PATH1_SC_THRESHOLD));
985 break;
986
987 case AUDIO_INPUT_TUNER_TV:
988 default:
989
990 /* Setup SRC sources and clocks */
991 status = vid_blk_write_word(dev, BAND_OUT_SEL,
992 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
993 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
994 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
995 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
996 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
997 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
998 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
999 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1000 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1001 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1002 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1003 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1004 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1005
1006 /* Setup the AUD_IO control */
1007 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1008 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1009 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1010 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1011 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1012 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1013
1014 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1015
1016 /* setAudioStandard(_audio_standard); */
1017
1018 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1019 switch (dev->model) {
1020 case CX231XX_BOARD_CNXT_RDE_250:
1021 case CX231XX_BOARD_CNXT_RDU_250:
1022 status = cx231xx_read_modify_write_i2c_dword(dev,
1023 VID_BLK_I2C_ADDRESS,
1024 CHIP_CTRL,
1025 FLD_SIF_EN,
1026 cx231xx_set_field(FLD_SIF_EN, 1));
1027 break;
1028 default:
1029 break;
1030 }
1031 break;
1032
1033 case AUDIO_INPUT_TUNER_FM:
1034 /* use SIF for FM radio
1035 setupFM();
1036 setAudioStandard(_audio_standard);
1037 */
1038 break;
1039
1040 case AUDIO_INPUT_MUTE:
1041 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1042 break;
1043 }
1044
1045 /* Take it out of soft reset */
1046 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1047 gen_ctrl &= ~1;
1048 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1049
1050 return status;
1051}
1052
1053/* Set resolution of the video */
1054int cx231xx_resolution_set(struct cx231xx *dev)
1055{
1056 int width, height;
1057 u32 hscale, vscale;
1058 int status = 0;
1059
1060 width = dev->width;
1061 height = dev->height;
1062
1063 get_scale(dev, width, height, &hscale, &vscale);
1064
1065 /* set horzontal scale */
1066 status = vid_blk_write_word(dev, HSCALE_CTRL, hscale);
1067
1068 /* set vertical scale */
1069 status = vid_blk_write_word(dev, VSCALE_CTRL, vscale);
1070
1071 return status;
1072}
1073
1074/******************************************************************************
1075 * C H I P Specific C O N T R O L functions *
1076 ******************************************************************************/
1077int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1078{
1079 u32 value;
1080 int status = 0;
1081
1082 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1083 value |= (~dev->board.ctl_pin_status_mask);
1084 status = vid_blk_write_word(dev, PIN_CTRL, value);
1085
1086 return status;
1087}
1088
1089int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1090 u8 analog_or_digital)
1091{
1092 int status = 0;
1093
1094 /* first set the direction to output */
1095 status = cx231xx_set_gpio_direction(dev,
1096 dev->board.
1097 agc_analog_digital_select_gpio, 1);
1098
1099 /* 0 - demod ; 1 - Analog mode */
1100 status = cx231xx_set_gpio_value(dev,
1101 dev->board.agc_analog_digital_select_gpio,
1102 analog_or_digital);
1103
1104 return status;
1105}
1106
1107int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1108{
1109 u8 value[4] = { 0, 0, 0, 0 };
1110 int status = 0;
1111
1112 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1113
1114 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1115 PWR_CTL_EN, value, 4);
1116 if (status < 0)
1117 return status;
1118
1119 if (I2CIndex == I2C_1) {
1120 if (value[0] & I2C_DEMOD_EN) {
1121 value[0] &= ~I2C_DEMOD_EN;
1122 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1123 PWR_CTL_EN, value, 4);
1124 }
1125 } else {
1126 if (!(value[0] & I2C_DEMOD_EN)) {
1127 value[0] |= I2C_DEMOD_EN;
1128 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1129 PWR_CTL_EN, value, 4);
1130 }
1131 }
1132
1133 return status;
1134
1135}
1136
1137/******************************************************************************
1138 * D I F - B L O C K C O N T R O L functions *
1139 ******************************************************************************/
1140int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1141 u32 function_mode, u32 standard)
1142{
1143 int status = 0;
1144
1145 if (mode == V4L2_TUNER_RADIO) {
1146 /* C2HH */
1147 /* lo if big signal */
1148 status = cx231xx_reg_mask_write(dev,
1149 VID_BLK_I2C_ADDRESS, 32,
1150 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1151 /* FUNC_MODE = DIF */
1152 status = cx231xx_reg_mask_write(dev,
1153 VID_BLK_I2C_ADDRESS, 32,
1154 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1155 /* IF_MODE */
1156 status = cx231xx_reg_mask_write(dev,
1157 VID_BLK_I2C_ADDRESS, 32,
1158 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1159 /* no inv */
1160 status = cx231xx_reg_mask_write(dev,
1161 VID_BLK_I2C_ADDRESS, 32,
1162 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1163 } else if (standard != DIF_USE_BASEBAND) {
1164 if (standard & V4L2_STD_MN) {
1165 /* lo if big signal */
1166 status = cx231xx_reg_mask_write(dev,
1167 VID_BLK_I2C_ADDRESS, 32,
1168 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1169 /* FUNC_MODE = DIF */
1170 status = cx231xx_reg_mask_write(dev,
1171 VID_BLK_I2C_ADDRESS, 32,
1172 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1173 function_mode);
1174 /* IF_MODE */
1175 status = cx231xx_reg_mask_write(dev,
1176 VID_BLK_I2C_ADDRESS, 32,
1177 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1178 /* no inv */
1179 status = cx231xx_reg_mask_write(dev,
1180 VID_BLK_I2C_ADDRESS, 32,
1181 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1182 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1183 status = cx231xx_reg_mask_write(dev,
1184 VID_BLK_I2C_ADDRESS, 32,
1185 AUD_IO_CTRL, 0, 31, 0x00000003);
1186 } else if ((standard == V4L2_STD_PAL_I) |
1187 (standard & V4L2_STD_SECAM)) {
1188 /* C2HH setup */
1189 /* lo if big signal */
1190 status = cx231xx_reg_mask_write(dev,
1191 VID_BLK_I2C_ADDRESS, 32,
1192 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1193 /* FUNC_MODE = DIF */
1194 status = cx231xx_reg_mask_write(dev,
1195 VID_BLK_I2C_ADDRESS, 32,
1196 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1197 function_mode);
1198 /* IF_MODE */
1199 status = cx231xx_reg_mask_write(dev,
1200 VID_BLK_I2C_ADDRESS, 32,
1201 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1202 /* no inv */
1203 status = cx231xx_reg_mask_write(dev,
1204 VID_BLK_I2C_ADDRESS, 32,
1205 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1206 } else {
1207 /* default PAL BG */
1208 /* C2HH setup */
1209 /* lo if big signal */
1210 status = cx231xx_reg_mask_write(dev,
1211 VID_BLK_I2C_ADDRESS, 32,
1212 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1213 /* FUNC_MODE = DIF */
1214 status = cx231xx_reg_mask_write(dev,
1215 VID_BLK_I2C_ADDRESS, 32,
1216 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1217 function_mode);
1218 /* IF_MODE */
1219 status = cx231xx_reg_mask_write(dev,
1220 VID_BLK_I2C_ADDRESS, 32,
1221 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1222 /* no inv */
1223 status = cx231xx_reg_mask_write(dev,
1224 VID_BLK_I2C_ADDRESS, 32,
1225 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1226 }
1227 }
1228
1229 return status;
1230}
1231
1232int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1233{
1234 int status = 0;
1235 u32 dif_misc_ctrl_value = 0;
1236 u32 func_mode = 0;
1237
1238 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1239
1240 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1241 if (standard != DIF_USE_BASEBAND)
1242 dev->norm = standard;
1243
1244 switch (dev->model) {
1245 case CX231XX_BOARD_CNXT_RDE_250:
1246 case CX231XX_BOARD_CNXT_RDU_250:
1247 func_mode = 0x03;
1248 break;
1249 default:
1250 func_mode = 0x01;
1251 }
1252
1253 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1254 func_mode, standard);
1255
1256 if (standard == DIF_USE_BASEBAND) { /* base band */
1257 /* There is a different SRC_PHASE_INC value
1258 for baseband vs. DIF */
1259 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1260 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1261 &dif_misc_ctrl_value);
1262 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1263 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1264 dif_misc_ctrl_value);
1265 } else if (standard & V4L2_STD_PAL_D) {
1266 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1267 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1268 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1269 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1270 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1271 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1272 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1273 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1274 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1275 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1276 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1277 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1278 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1279 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1280 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1281 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1282 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1283 DIF_AGC_IF_INT_CURRENT, 0, 31,
1284 0x26001700);
1285 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1286 DIF_AGC_RF_CURRENT, 0, 31,
1287 0x00002660);
1288 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1289 DIF_VIDEO_AGC_CTRL, 0, 31,
1290 0x72500800);
1291 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1292 DIF_VID_AUD_OVERRIDE, 0, 31,
1293 0x27000100);
1294 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1295 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1296 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1297 DIF_COMP_FLT_CTRL, 0, 31,
1298 0x00000000);
1299 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1300 DIF_SRC_PHASE_INC, 0, 31,
1301 0x1befbf06);
1302 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1303 DIF_SRC_GAIN_CONTROL, 0, 31,
1304 0x000035e8);
1305 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1306 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1307 /* Save the Spec Inversion value */
1308 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1309 dif_misc_ctrl_value |= 0x3a023F11;
1310 } else if (standard & V4L2_STD_PAL_I) {
1311 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1312 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1313 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1314 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1315 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1316 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1317 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1318 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1319 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1320 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1321 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1322 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1323 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1324 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1325 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1326 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1327 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1328 DIF_AGC_IF_INT_CURRENT, 0, 31,
1329 0x26001700);
1330 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1331 DIF_AGC_RF_CURRENT, 0, 31,
1332 0x00002660);
1333 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1334 DIF_VIDEO_AGC_CTRL, 0, 31,
1335 0x72500800);
1336 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1337 DIF_VID_AUD_OVERRIDE, 0, 31,
1338 0x27000100);
1339 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1340 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1341 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1342 DIF_COMP_FLT_CTRL, 0, 31,
1343 0x00000000);
1344 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1345 DIF_SRC_PHASE_INC, 0, 31,
1346 0x1befbf06);
1347 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1348 DIF_SRC_GAIN_CONTROL, 0, 31,
1349 0x000035e8);
1350 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1351 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1352 /* Save the Spec Inversion value */
1353 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1354 dif_misc_ctrl_value |= 0x3a033F11;
1355 } else if (standard & V4L2_STD_PAL_M) {
1356 /* improved Low Frequency Phase Noise */
1357 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1358 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1359 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1360 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1361 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1362 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1363 0x26001700);
1364 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1365 0x00002660);
1366 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1367 0x72500800);
1368 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1369 0x27000100);
1370 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1371 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1372 0x009f50c1);
1373 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1374 0x1befbf06);
1375 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1376 0x000035e8);
1377 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1378 0x00000000);
1379 /* Save the Spec Inversion value */
1380 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1381 dif_misc_ctrl_value |= 0x3A0A3F10;
1382 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1383 /* improved Low Frequency Phase Noise */
1384 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1385 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1386 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1387 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1388 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1389 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1390 0x26001700);
1391 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1392 0x00002660);
1393 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1394 0x72500800);
1395 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1396 0x27000100);
1397 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1398 0x012c405d);
1399 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1400 0x009f50c1);
1401 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1402 0x1befbf06);
1403 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1404 0x000035e8);
1405 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1406 0x00000000);
1407 /* Save the Spec Inversion value */
1408 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1409 dif_misc_ctrl_value = 0x3A093F10;
1410 } else if (standard &
1411 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1412 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1413
1414 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1415 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1416 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1417 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1418 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1419 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1420 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1421 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1422 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1423 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1424 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1425 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1426 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1427 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1428 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1429 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1430 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1431 DIF_AGC_IF_INT_CURRENT, 0, 31,
1432 0x26001700);
1433 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1434 DIF_AGC_RF_CURRENT, 0, 31,
1435 0x00002660);
1436 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1437 DIF_VID_AUD_OVERRIDE, 0, 31,
1438 0x27000100);
1439 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1440 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1441 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1442 DIF_COMP_FLT_CTRL, 0, 31,
1443 0x00000000);
1444 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1445 DIF_SRC_PHASE_INC, 0, 31,
1446 0x1befbf06);
1447 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1448 DIF_SRC_GAIN_CONTROL, 0, 31,
1449 0x000035e8);
1450 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1451 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1452 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1453 DIF_VIDEO_AGC_CTRL, 0, 31,
1454 0xf4000000);
1455
1456 /* Save the Spec Inversion value */
1457 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1458 dif_misc_ctrl_value |= 0x3a023F11;
1459 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1460 /* Is it SECAM_L1? */
1461 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1462 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1463 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1464 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1465 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1466 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1467 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1468 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1469 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1470 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1471 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1472 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1473 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1474 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1475 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1476 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1477 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1478 DIF_AGC_IF_INT_CURRENT, 0, 31,
1479 0x26001700);
1480 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1481 DIF_AGC_RF_CURRENT, 0, 31,
1482 0x00002660);
1483 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1484 DIF_VID_AUD_OVERRIDE, 0, 31,
1485 0x27000100);
1486 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1487 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1488 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1489 DIF_COMP_FLT_CTRL, 0, 31,
1490 0x00000000);
1491 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1492 DIF_SRC_PHASE_INC, 0, 31,
1493 0x1befbf06);
1494 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1495 DIF_SRC_GAIN_CONTROL, 0, 31,
1496 0x000035e8);
1497 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1498 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1499 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1500 DIF_VIDEO_AGC_CTRL, 0, 31,
1501 0xf2560000);
1502
1503 /* Save the Spec Inversion value */
1504 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1505 dif_misc_ctrl_value |= 0x3a023F11;
1506
1507 } else if (standard & V4L2_STD_NTSC_M) {
1508 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1509 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
1510
1511 /* For NTSC the centre frequency of video coming out of
1512 sidewinder is around 7.1MHz or 3.6MHz depending on the
1513 spectral inversion. so for a non spectrally inverted channel
1514 the pll freq word is 0x03420c49
1515 */
1516
1517 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
1518 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
1519 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
1520 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1521 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
1522 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1523 0x26001700);
1524 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1525 0x00002660);
1526 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1527 0x04000800);
1528 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1529 0x27000100);
1530 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
1531
1532 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1533 0x009f50c1);
1534 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1535 0x1befbf06);
1536 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1537 0x000035e8);
1538
1539 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
1540 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
1541 0xC2262600);
1542 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
1543
1544 /* Save the Spec Inversion value */
1545 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1546 dif_misc_ctrl_value |= 0x3a003F10;
1547 } else {
1548 /* default PAL BG */
1549 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1550 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1551 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1552 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1553 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1554 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1555 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1556 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1557 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1558 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1559 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1560 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1561 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1562 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1563 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1564 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1565 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1566 DIF_AGC_IF_INT_CURRENT, 0, 31,
1567 0x26001700);
1568 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1569 DIF_AGC_RF_CURRENT, 0, 31,
1570 0x00002660);
1571 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1572 DIF_VIDEO_AGC_CTRL, 0, 31,
1573 0x72500800);
1574 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1575 DIF_VID_AUD_OVERRIDE, 0, 31,
1576 0x27000100);
1577 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1578 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1579 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1580 DIF_COMP_FLT_CTRL, 0, 31,
1581 0x00A653A8);
1582 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1583 DIF_SRC_PHASE_INC, 0, 31,
1584 0x1befbf06);
1585 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1586 DIF_SRC_GAIN_CONTROL, 0, 31,
1587 0x000035e8);
1588 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1589 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1590 /* Save the Spec Inversion value */
1591 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1592 dif_misc_ctrl_value |= 0x3a013F11;
1593 }
1594
1595 /* The AGC values should be the same for all standards,
1596 AUD_SRC_SEL[19] should always be disabled */
1597 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
1598
1599 /* It is still possible to get Set Standard calls even when we
1600 are in FM mode.
1601 This is done to override the value for FM. */
1602 if (dev->active_mode == V4L2_TUNER_RADIO)
1603 dif_misc_ctrl_value = 0x7a080000;
1604
1605 /* Write the calculated value for misc ontrol register */
1606 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
1607
1608 return status;
1609}
1610
1611int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
1612{
1613 int status = 0;
1614 u32 dwval;
1615
1616 /* Set the RF and IF k_agc values to 3 */
1617 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1618 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1619 dwval |= 0x33000000;
1620
1621 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1622
1623 return status;
1624}
1625
1626int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1627{
1628 int status = 0;
1629 u32 dwval;
1630
1631 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1632 * SECAM L/B/D standards */
1633 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1634 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1635
1636 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
1637 V4L2_STD_SECAM_D))
1638 dwval |= 0x88000000;
1639 else
1640 dwval |= 0x44000000;
1641
1642 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1643
1644 return status;
1645}
1646
1647/******************************************************************************
1648 * I 2 S - B L O C K C O N T R O L functions *
1649 ******************************************************************************/
1650int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
1651{
1652 int status = 0;
1653 u32 value;
1654
1655 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1656 CH_PWR_CTRL1, 1, &value, 1);
1657 /* enables clock to delta-sigma and decimation filter */
1658 value |= 0x80;
1659 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1660 CH_PWR_CTRL1, 1, value, 1);
1661 /* power up all channel */
1662 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1663 CH_PWR_CTRL2, 1, 0x00, 1);
1664
1665 return status;
1666}
1667
1668int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
1669 enum AV_MODE avmode)
1670{
1671 int status = 0;
1672 u32 value = 0;
1673
1674 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
1675 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1676 CH_PWR_CTRL2, 1, &value, 1);
1677 value |= 0xfe;
1678 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1679 CH_PWR_CTRL2, 1, value, 1);
1680 } else {
1681 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1682 CH_PWR_CTRL2, 1, 0x00, 1);
1683 }
1684
1685 return status;
1686}
1687
1688/* set i2s_blk for audio input types */
1689int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
1690{
1691 int status = 0;
1692
1693 switch (audio_input) {
1694 case CX231XX_AMUX_LINE_IN:
1695 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1696 CH_PWR_CTRL2, 1, 0x00, 1);
1697 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1698 CH_PWR_CTRL1, 1, 0x80, 1);
1699 break;
1700 case CX231XX_AMUX_VIDEO:
1701 default:
1702 break;
1703 }
1704
1705 dev->ctl_ainput = audio_input;
1706
1707 return status;
1708}
1709
1710/******************************************************************************
1711 * P O W E R C O N T R O L functions *
1712 ******************************************************************************/
1713int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1714{
1715 u8 value[4] = { 0, 0, 0, 0 };
1716 u32 tmp = 0;
1717 int status = 0;
1718
1719 if (dev->power_mode != mode)
1720 dev->power_mode = mode;
1721 else {
1722 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
1723 mode);
1724 return 0;
1725 }
1726
1727 cx231xx_info(" setPowerMode::mode = %d\n", mode);
1728
1729 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1730 4);
1731 if (status < 0)
1732 return status;
1733
1734 tmp = *((u32 *) value);
1735
1736 switch (mode) {
1737 case POLARIS_AVMODE_ENXTERNAL_AV:
1738
1739 tmp &= (~PWR_MODE_MASK);
1740
1741 tmp |= PWR_AV_EN;
1742 value[0] = (u8) tmp;
1743 value[1] = (u8) (tmp >> 8);
1744 value[2] = (u8) (tmp >> 16);
1745 value[3] = (u8) (tmp >> 24);
1746 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1747 PWR_CTL_EN, value, 4);
1748 msleep(PWR_SLEEP_INTERVAL);
1749
1750 tmp |= PWR_ISO_EN;
1751 value[0] = (u8) tmp;
1752 value[1] = (u8) (tmp >> 8);
1753 value[2] = (u8) (tmp >> 16);
1754 value[3] = (u8) (tmp >> 24);
1755 status =
1756 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1757 value, 4);
1758 msleep(PWR_SLEEP_INTERVAL);
1759
1760 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
1761 value[0] = (u8) tmp;
1762 value[1] = (u8) (tmp >> 8);
1763 value[2] = (u8) (tmp >> 16);
1764 value[3] = (u8) (tmp >> 24);
1765 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1766 PWR_CTL_EN, value, 4);
1767
1768 /* reset state of xceive tuner */
1769 dev->xc_fw_load_done = 0;
1770 break;
1771
1772 case POLARIS_AVMODE_ANALOGT_TV:
1773
1774 tmp &= (~PWR_DEMOD_EN);
1775 tmp |= (I2C_DEMOD_EN);
1776 value[0] = (u8) tmp;
1777 value[1] = (u8) (tmp >> 8);
1778 value[2] = (u8) (tmp >> 16);
1779 value[3] = (u8) (tmp >> 24);
1780 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1781 PWR_CTL_EN, value, 4);
1782 msleep(PWR_SLEEP_INTERVAL);
1783
1784 if (!(tmp & PWR_TUNER_EN)) {
1785 tmp |= (PWR_TUNER_EN);
1786 value[0] = (u8) tmp;
1787 value[1] = (u8) (tmp >> 8);
1788 value[2] = (u8) (tmp >> 16);
1789 value[3] = (u8) (tmp >> 24);
1790 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1791 PWR_CTL_EN, value, 4);
1792 msleep(PWR_SLEEP_INTERVAL);
1793 }
1794
1795 if (!(tmp & PWR_AV_EN)) {
1796 tmp |= PWR_AV_EN;
1797 value[0] = (u8) tmp;
1798 value[1] = (u8) (tmp >> 8);
1799 value[2] = (u8) (tmp >> 16);
1800 value[3] = (u8) (tmp >> 24);
1801 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1802 PWR_CTL_EN, value, 4);
1803 msleep(PWR_SLEEP_INTERVAL);
1804 }
1805 if (!(tmp & PWR_ISO_EN)) {
1806 tmp |= PWR_ISO_EN;
1807 value[0] = (u8) tmp;
1808 value[1] = (u8) (tmp >> 8);
1809 value[2] = (u8) (tmp >> 16);
1810 value[3] = (u8) (tmp >> 24);
1811 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1812 PWR_CTL_EN, value, 4);
1813 msleep(PWR_SLEEP_INTERVAL);
1814 }
1815
1816 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
1817 tmp |= POLARIS_AVMODE_ANALOGT_TV;
1818 value[0] = (u8) tmp;
1819 value[1] = (u8) (tmp >> 8);
1820 value[2] = (u8) (tmp >> 16);
1821 value[3] = (u8) (tmp >> 24);
1822 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1823 PWR_CTL_EN, value, 4);
1824 msleep(PWR_SLEEP_INTERVAL);
1825 }
1826
1827 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1828 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1829 /* tuner path to channel 1 from port 3 */
1830 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1831
1832 if (dev->cx231xx_reset_analog_tuner)
1833 dev->cx231xx_reset_analog_tuner(dev);
1834 }
1835 break;
1836
1837 case POLARIS_AVMODE_DIGITAL:
1838 if (!(tmp & PWR_TUNER_EN)) {
1839 tmp |= (PWR_TUNER_EN);
1840 value[0] = (u8) tmp;
1841 value[1] = (u8) (tmp >> 8);
1842 value[2] = (u8) (tmp >> 16);
1843 value[3] = (u8) (tmp >> 24);
1844 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1845 PWR_CTL_EN, value, 4);
1846 msleep(PWR_SLEEP_INTERVAL);
1847 }
1848 if (!(tmp & PWR_AV_EN)) {
1849 tmp |= PWR_AV_EN;
1850 value[0] = (u8) tmp;
1851 value[1] = (u8) (tmp >> 8);
1852 value[2] = (u8) (tmp >> 16);
1853 value[3] = (u8) (tmp >> 24);
1854 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1855 PWR_CTL_EN, value, 4);
1856 msleep(PWR_SLEEP_INTERVAL);
1857 }
1858 if (!(tmp & PWR_ISO_EN)) {
1859 tmp |= PWR_ISO_EN;
1860 value[0] = (u8) tmp;
1861 value[1] = (u8) (tmp >> 8);
1862 value[2] = (u8) (tmp >> 16);
1863 value[3] = (u8) (tmp >> 24);
1864 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1865 PWR_CTL_EN, value, 4);
1866 msleep(PWR_SLEEP_INTERVAL);
1867 }
1868
1869 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
1870 value[0] = (u8) tmp;
1871 value[1] = (u8) (tmp >> 8);
1872 value[2] = (u8) (tmp >> 16);
1873 value[3] = (u8) (tmp >> 24);
1874 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1875 PWR_CTL_EN, value, 4);
1876 msleep(PWR_SLEEP_INTERVAL);
1877
1878 if (!(tmp & PWR_DEMOD_EN)) {
1879 tmp |= PWR_DEMOD_EN;
1880 value[0] = (u8) tmp;
1881 value[1] = (u8) (tmp >> 8);
1882 value[2] = (u8) (tmp >> 16);
1883 value[3] = (u8) (tmp >> 24);
1884 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1885 PWR_CTL_EN, value, 4);
1886 msleep(PWR_SLEEP_INTERVAL);
1887 }
1888
1889 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1890 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1891 /* tuner path to channel 1 from port 3 */
1892 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1893
1894 if (dev->cx231xx_reset_analog_tuner)
1895 dev->cx231xx_reset_analog_tuner(dev);
1896 }
1897 break;
1898
1899 default:
1900 break;
1901 }
1902
1903 msleep(PWR_SLEEP_INTERVAL);
1904
1905 /* For power saving, only enable Pwr_resetout_n
1906 when digital TV is selected. */
1907 if (mode == POLARIS_AVMODE_DIGITAL) {
1908 tmp |= PWR_RESETOUT_EN;
1909 value[0] = (u8) tmp;
1910 value[1] = (u8) (tmp >> 8);
1911 value[2] = (u8) (tmp >> 16);
1912 value[3] = (u8) (tmp >> 24);
1913 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1914 PWR_CTL_EN, value, 4);
1915 msleep(PWR_SLEEP_INTERVAL);
1916 }
1917
1918 /* update power control for afe */
1919 status = cx231xx_afe_update_power_control(dev, mode);
1920
1921 /* update power control for i2s_blk */
1922 status = cx231xx_i2s_blk_update_power_control(dev, mode);
1923
1924 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1925 4);
1926 cx231xx_info(" The data of PWR_CTL_EN register 0x74"
1927 "=0x%0x,0x%0x,0x%0x,0x%0x\n",
1928 value[0], value[1], value[2], value[3]);
1929
1930 return status;
1931}
1932
1933int cx231xx_power_suspend(struct cx231xx *dev)
1934{
1935 u8 value[4] = { 0, 0, 0, 0 };
1936 u32 tmp = 0;
1937 int status = 0;
1938
1939 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1940 value, 4);
1941 if (status > 0)
1942 return status;
1943
1944 tmp = *((u32 *) value);
1945 tmp &= (~PWR_MODE_MASK);
1946
1947 value[0] = (u8) tmp;
1948 value[1] = (u8) (tmp >> 8);
1949 value[2] = (u8) (tmp >> 16);
1950 value[3] = (u8) (tmp >> 24);
1951 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1952 value, 4);
1953
1954 return status;
1955}
1956
1957/******************************************************************************
1958 * S T R E A M C O N T R O L functions *
1959 ******************************************************************************/
1960int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
1961{
1962 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1963 u32 tmp = 0;
1964 int status = 0;
1965
1966 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
1967 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1968 value, 4);
1969 if (status < 0)
1970 return status;
1971
1972 tmp = *((u32 *) value);
1973 tmp |= ep_mask;
1974 value[0] = (u8) tmp;
1975 value[1] = (u8) (tmp >> 8);
1976 value[2] = (u8) (tmp >> 16);
1977 value[3] = (u8) (tmp >> 24);
1978
1979 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1980 value, 4);
1981
1982 return status;
1983}
1984
1985int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
1986{
1987 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1988 u32 tmp = 0;
1989 int status = 0;
1990
1991 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
1992 status =
1993 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
1994 if (status < 0)
1995 return status;
1996
1997 tmp = *((u32 *) value);
1998 tmp &= (~ep_mask);
1999 value[0] = (u8) tmp;
2000 value[1] = (u8) (tmp >> 8);
2001 value[2] = (u8) (tmp >> 16);
2002 value[3] = (u8) (tmp >> 24);
2003
2004 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2005 value, 4);
2006
2007 return status;
2008}
2009
2010int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2011{
2012 int status = 0;
2013
2014 if (dev->udev->speed == USB_SPEED_HIGH) {
2015 switch (media_type) {
2016 case 81: /* audio */
2017 cx231xx_info("%s: Audio enter HANC\n", __func__);
2018 status =
2019 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2020 break;
2021
2022 case 2: /* vbi */
2023 cx231xx_info("%s: set vanc registers\n", __func__);
2024 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2025 break;
2026
2027 case 3: /* sliced cc */
2028 cx231xx_info("%s: set hanc registers\n", __func__);
2029 status =
2030 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2031 break;
2032
2033 case 0: /* video */
2034 cx231xx_info("%s: set video registers\n", __func__);
2035 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2036 break;
2037
2038 case 4: /* ts1 */
2039 cx231xx_info("%s: set ts1 registers\n", __func__);
2040 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2041 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2042 break;
2043 case 6: /* ts1 parallel mode */
2044 cx231xx_info("%s: set ts1 parrallel mode registers\n",
2045 __func__);
2046 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2047 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2048 break;
2049 }
2050 } else {
2051 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2052 }
2053
2054 return status;
2055}
2056
2057int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2058{
2059 int rc;
2060 u32 ep_mask = -1;
2061 struct pcb_config *pcb_config;
2062
2063 /* get EP for media type */
2064 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2065
2066 if (pcb_config->config_num == 1) {
2067 switch (media_type) {
2068 case 0: /* Video */
2069 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2070 break;
2071 case 1: /* Audio */
2072 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2073 break;
2074 case 2: /* Vbi */
2075 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2076 break;
2077 case 3: /* Sliced_cc */
2078 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2079 break;
2080 case 4: /* ts1 */
2081 case 6: /* ts1 parallel mode */
2082 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2083 break;
2084 case 5: /* ts2 */
2085 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2086 break;
2087 }
2088
2089 } else if (pcb_config->config_num > 1) {
2090 switch (media_type) {
2091 case 0: /* Video */
2092 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2093 break;
2094 case 1: /* Audio */
2095 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2096 break;
2097 case 2: /* Vbi */
2098 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2099 break;
2100 case 3: /* Sliced_cc */
2101 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2102 break;
2103 case 4: /* ts1 */
2104 case 6: /* ts1 parallel mode */
2105 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2106 break;
2107 case 5: /* ts2 */
2108 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2109 break;
2110 }
2111
2112 }
2113
2114 if (start) {
2115 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2116
2117 if (rc < 0)
2118 return rc;
2119
2120 /* enable video capture */
2121 if (ep_mask > 0)
2122 rc = cx231xx_start_stream(dev, ep_mask);
2123 } else {
2124 /* disable video capture */
2125 if (ep_mask > 0)
2126 rc = cx231xx_stop_stream(dev, ep_mask);
2127 }
2128
2129 if (dev->mode == CX231XX_ANALOG_MODE)
2130 ;/* do any in Analog mode */
2131 else
2132 ;/* do any in digital mode */
2133
2134 return rc;
2135}
2136EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2137
2138/*****************************************************************************
2139* G P I O B I T control functions *
2140******************************************************************************/
2141int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2142{
2143 int status = 0;
2144
2145 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2146
2147 return status;
2148}
2149
2150int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2151{
2152 int status = 0;
2153
2154 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2155
2156 return status;
2157}
2158
2159/*
2160* cx231xx_set_gpio_direction
2161* Sets the direction of the GPIO pin to input or output
2162*
2163* Parameters :
2164* pin_number : The GPIO Pin number to program the direction for
2165* from 0 to 31
2166* pin_value : The Direction of the GPIO Pin under reference.
2167* 0 = Input direction
2168* 1 = Output direction
2169*/
2170int cx231xx_set_gpio_direction(struct cx231xx *dev,
2171 int pin_number, int pin_value)
2172{
2173 int status = 0;
2174 u32 value = 0;
2175
2176 /* Check for valid pin_number - if 32 , bail out */
2177 if (pin_number >= 32)
2178 return -EINVAL;
2179
2180 /* input */
2181 if (pin_value == 0)
2182 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2183 else
2184 value = dev->gpio_dir | (1 << pin_number);
2185
2186 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2187
2188 /* cache the value for future */
2189 dev->gpio_dir = value;
2190
2191 return status;
2192}
2193
2194/*
2195* cx231xx_set_gpio_value
2196* Sets the value of the GPIO pin to Logic high or low. The Pin under
2197* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2198*
2199* Parameters :
2200* pin_number : The GPIO Pin number to program the direction for
2201* pin_value : The value of the GPIO Pin under reference.
2202* 0 = set it to 0
2203* 1 = set it to 1
2204*/
2205int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2206{
2207 int status = 0;
2208 u32 value = 0;
2209
2210 /* Check for valid pin_number - if 0xFF , bail out */
2211 if (pin_number >= 32)
2212 return -EINVAL;
2213
2214 /* first do a sanity check - if the Pin is not output, make it output */
2215 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2216 /* It was in input mode */
2217 value = dev->gpio_dir | (1 << pin_number);
2218 dev->gpio_dir = value;
2219 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2220 (u8 *) &dev->gpio_val);
2221 value = 0;
2222 }
2223
2224 if (pin_value == 0)
2225 value = dev->gpio_val & (~(1 << pin_number));
2226 else
2227 value = dev->gpio_val | (1 << pin_number);
2228
2229 /* store the value */
2230 dev->gpio_val = value;
2231
2232 /* toggle bit0 of GP_IO */
2233 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2234
2235 return status;
2236}
2237
2238/*****************************************************************************
2239* G P I O I2C related functions *
2240******************************************************************************/
2241int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2242{
2243 int status = 0;
2244
2245 /* set SCL to output 1 ; set SDA to output 1 */
2246 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2247 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2248 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2249 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2250
2251 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2252 if (status < 0)
2253 return -EINVAL;
2254
2255 /* set SCL to output 1; set SDA to output 0 */
2256 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2257 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2258
2259 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2260 if (status < 0)
2261 return -EINVAL;
2262
2263 /* set SCL to output 0; set SDA to output 0 */
2264 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2265 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2266
2267 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2268 if (status < 0)
2269 return -EINVAL;
2270
2271 return status;
2272}
2273
2274int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2275{
2276 int status = 0;
2277
2278 /* set SCL to output 0; set SDA to output 0 */
2279 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2280 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2281
2282 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2283 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2284
2285 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2286 if (status < 0)
2287 return -EINVAL;
2288
2289 /* set SCL to output 1; set SDA to output 0 */
2290 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2291 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2292
2293 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2294 if (status < 0)
2295 return -EINVAL;
2296
2297 /* set SCL to input ,release SCL cable control
2298 set SDA to input ,release SDA cable control */
2299 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2300 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2301
2302 status =
2303 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2304 if (status < 0)
2305 return -EINVAL;
2306
2307 return status;
2308}
2309
2310int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2311{
2312 int status = 0;
2313 u8 i;
2314
2315 /* set SCL to output ; set SDA to output */
2316 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2317 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2318
2319 for (i = 0; i < 8; i++) {
2320 if (((data << i) & 0x80) == 0) {
2321 /* set SCL to output 0; set SDA to output 0 */
2322 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2323 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2324 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2325 (u8 *)&dev->gpio_val);
2326
2327 /* set SCL to output 1; set SDA to output 0 */
2328 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2329 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2330 (u8 *)&dev->gpio_val);
2331
2332 /* set SCL to output 0; set SDA to output 0 */
2333 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2334 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2335 (u8 *)&dev->gpio_val);
2336 } else {
2337 /* set SCL to output 0; set SDA to output 1 */
2338 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2339 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2340 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2341 (u8 *)&dev->gpio_val);
2342
2343 /* set SCL to output 1; set SDA to output 1 */
2344 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2345 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2346 (u8 *)&dev->gpio_val);
2347
2348 /* set SCL to output 0; set SDA to output 1 */
2349 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2350 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2351 (u8 *)&dev->gpio_val);
2352 }
2353 }
2354 return status;
2355}
2356
2357int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf)
2358{
2359 u8 value = 0;
2360 int status = 0;
2361 u32 gpio_logic_value = 0;
2362 u8 i;
2363
2364 /* read byte */
2365 for (i = 0; i < 8; i++) { /* send write I2c addr */
2366
2367 /* set SCL to output 0; set SDA to input */
2368 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2369 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2370 (u8 *)&dev->gpio_val);
2371
2372 /* set SCL to output 1; set SDA to input */
2373 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2374 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2375 (u8 *)&dev->gpio_val);
2376
2377 /* get SDA data bit */
2378 gpio_logic_value = dev->gpio_val;
2379 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2380 (u8 *)&dev->gpio_val);
2381 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2382 value |= (1 << (8 - i - 1));
2383
2384 dev->gpio_val = gpio_logic_value;
2385 }
2386
2387 /* set SCL to output 0,finish the read latest SCL signal.
2388 !!!set SDA to input, never to modify SDA direction at
2389 the same times */
2390 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2391 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2392
2393 /* store the value */
2394 *buf = value & 0xff;
2395
2396 return status;
2397}
2398
2399int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2400{
2401 int status = 0;
2402 u32 gpio_logic_value = 0;
2403 int nCnt = 10;
2404 int nInit = nCnt;
2405
2406 /* clock stretch; set SCL to input; set SDA to input;
2407 get SCL value till SCL = 1 */
2408 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2409 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2410
2411 gpio_logic_value = dev->gpio_val;
2412 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2413
2414 do {
2415 msleep(2);
2416 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2417 (u8 *)&dev->gpio_val);
2418 nCnt--;
2419 } while (((dev->gpio_val &
2420 (1 << dev->board.tuner_scl_gpio)) == 0) &&
2421 (nCnt > 0));
2422
2423 if (nCnt == 0)
2424 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2425 nInit * 10);
2426
2427 /* readAck
2428 throuth clock stretch ,slave has given a SCL signal,
2429 so the SDA data can be directly read. */
2430 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2431
2432 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2433 dev->gpio_val = gpio_logic_value;
2434 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2435 status = 0;
2436 } else {
2437 dev->gpio_val = gpio_logic_value;
2438 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2439 }
2440
2441 /* read SDA end, set the SCL to output 0, after this operation,
2442 SDA direction can be changed. */
2443 dev->gpio_val = gpio_logic_value;
2444 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2445 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2446 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2447
2448 return status;
2449}
2450
2451int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2452{
2453 int status = 0;
2454
2455 /* set SDA to ouput */
2456 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2457 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2458
2459 /* set SCL = 0 (output); set SDA = 0 (output) */
2460 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2461 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2462 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2463
2464 /* set SCL = 1 (output); set SDA = 0 (output) */
2465 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2466 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2467
2468 /* set SCL = 0 (output); set SDA = 0 (output) */
2469 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2470 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2471
2472 /* set SDA to input,and then the slave will read data from SDA. */
2473 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2474 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2475
2476 return status;
2477}
2478
2479int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2480{
2481 int status = 0;
2482
2483 /* set scl to output ; set sda to input */
2484 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2485 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2486 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2487
2488 /* set scl to output 0; set sda to input */
2489 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2490 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2491
2492 /* set scl to output 1; set sda to input */
2493 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2494 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2495
2496 return status;
2497}
2498
2499/*****************************************************************************
2500* G P I O I2C related functions *
2501******************************************************************************/
2502/* cx231xx_gpio_i2c_read
2503 * Function to read data from gpio based I2C interface
2504 */
2505int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2506{
2507 int status = 0;
2508 int i = 0;
2509
2510 /* get the lock */
2511 mutex_lock(&dev->gpio_i2c_lock);
2512
2513 /* start */
2514 status = cx231xx_gpio_i2c_start(dev);
2515
2516 /* write dev_addr */
2517 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
2518
2519 /* readAck */
2520 status = cx231xx_gpio_i2c_read_ack(dev);
2521
2522 /* read data */
2523 for (i = 0; i < len; i++) {
2524 /* read data */
2525 buf[i] = 0;
2526 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
2527
2528 if ((i + 1) != len) {
2529 /* only do write ack if we more length */
2530 status = cx231xx_gpio_i2c_write_ack(dev);
2531 }
2532 }
2533
2534 /* write NAK - inform reads are complete */
2535 status = cx231xx_gpio_i2c_write_nak(dev);
2536
2537 /* write end */
2538 status = cx231xx_gpio_i2c_end(dev);
2539
2540 /* release the lock */
2541 mutex_unlock(&dev->gpio_i2c_lock);
2542
2543 return status;
2544}
2545
2546/* cx231xx_gpio_i2c_write
2547 * Function to write data to gpio based I2C interface
2548 */
2549int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2550{
2551 int status = 0;
2552 int i = 0;
2553
2554 /* get the lock */
2555 mutex_lock(&dev->gpio_i2c_lock);
2556
2557 /* start */
2558 status = cx231xx_gpio_i2c_start(dev);
2559
2560 /* write dev_addr */
2561 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
2562
2563 /* read Ack */
2564 status = cx231xx_gpio_i2c_read_ack(dev);
2565
2566 for (i = 0; i < len; i++) {
2567 /* Write data */
2568 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
2569
2570 /* read Ack */
2571 status = cx231xx_gpio_i2c_read_ack(dev);
2572 }
2573
2574 /* write End */
2575 status = cx231xx_gpio_i2c_end(dev);
2576
2577 /* release the lock */
2578 mutex_unlock(&dev->gpio_i2c_lock);
2579
2580 return 0;
2581}
diff --git a/drivers/media/video/cx231xx/cx231xx-cards.c b/drivers/media/video/cx231xx/cx231xx-cards.c
new file mode 100644
index 000000000000..c8a32b1b5381
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-cards.c
@@ -0,0 +1,914 @@
1/*
2 cx231xx-cards.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6 Based on em28xx driver
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/delay.h>
26#include <linux/i2c.h>
27#include <linux/usb.h>
28#include <media/tuner.h>
29#include <media/tveeprom.h>
30#include <media/v4l2-common.h>
31#include <media/v4l2-chip-ident.h>
32
33#include <media/cx25840.h>
34#include "xc5000.h"
35
36#include "cx231xx.h"
37
38static int tuner = -1;
39module_param(tuner, int, 0444);
40MODULE_PARM_DESC(tuner, "tuner type");
41
42static unsigned int disable_ir;
43module_param(disable_ir, int, 0444);
44MODULE_PARM_DESC(disable_ir, "disable infrared remote support");
45
46/* Bitmask marking allocated devices from 0 to CX231XX_MAXBOARDS */
47static unsigned long cx231xx_devused;
48
49/*
50 * Reset sequences for analog/digital modes
51 */
52
53static struct cx231xx_reg_seq RDE250_XCV_TUNER[] = {
54 {0x03, 0x01, 10},
55 {0x03, 0x00, 30},
56 {0x03, 0x01, 10},
57 {-1, -1, -1},
58};
59
60/*
61 * Board definitions
62 */
63struct cx231xx_board cx231xx_boards[] = {
64 [CX231XX_BOARD_UNKNOWN] = {
65 .name = "Unknown CX231xx video grabber",
66 .tuner_type = TUNER_ABSENT,
67 .input = {{
68 .type = CX231XX_VMUX_TELEVISION,
69 .vmux = CX231XX_VIN_3_1,
70 .amux = CX231XX_AMUX_VIDEO,
71 .gpio = 0,
72 }, {
73 .type = CX231XX_VMUX_COMPOSITE1,
74 .vmux = CX231XX_VIN_2_1,
75 .amux = CX231XX_AMUX_LINE_IN,
76 .gpio = 0,
77 }, {
78 .type = CX231XX_VMUX_SVIDEO,
79 .vmux = CX231XX_VIN_1_1 |
80 (CX231XX_VIN_1_2 << 8) |
81 CX25840_SVIDEO_ON,
82 .amux = CX231XX_AMUX_LINE_IN,
83 .gpio = 0,
84 }
85 },
86 },
87 [CX231XX_BOARD_CNXT_RDE_250] = {
88 .name = "Conexant Hybrid TV - RDE250",
89 .tuner_type = TUNER_XC5000,
90 .tuner_addr = 0x61,
91 .tuner_gpio = RDE250_XCV_TUNER,
92 .tuner_sif_gpio = 0x05,
93 .tuner_scl_gpio = 0x1a,
94 .tuner_sda_gpio = 0x1b,
95 .decoder = CX231XX_AVDECODER,
96 .demod_xfer_mode = 0,
97 .ctl_pin_status_mask = 0xFFFFFFC4,
98 .agc_analog_digital_select_gpio = 0x0c,
99 .gpio_pin_status_mask = 0x4001000,
100 .tuner_i2c_master = 1,
101 .demod_i2c_master = 2,
102 .has_dvb = 1,
103 .demod_addr = 0x02,
104 .norm = V4L2_STD_PAL,
105
106 .input = {{
107 .type = CX231XX_VMUX_TELEVISION,
108 .vmux = CX231XX_VIN_3_1,
109 .amux = CX231XX_AMUX_VIDEO,
110 .gpio = 0,
111 }, {
112 .type = CX231XX_VMUX_COMPOSITE1,
113 .vmux = CX231XX_VIN_2_1,
114 .amux = CX231XX_AMUX_LINE_IN,
115 .gpio = 0,
116 }, {
117 .type = CX231XX_VMUX_SVIDEO,
118 .vmux = CX231XX_VIN_1_1 |
119 (CX231XX_VIN_1_2 << 8) |
120 CX25840_SVIDEO_ON,
121 .amux = CX231XX_AMUX_LINE_IN,
122 .gpio = 0,
123 }
124 },
125 },
126
127 [CX231XX_BOARD_CNXT_RDU_250] = {
128 .name = "Conexant Hybrid TV - RDU250",
129 .tuner_type = TUNER_XC5000,
130 .tuner_addr = 0x61,
131 .tuner_gpio = RDE250_XCV_TUNER,
132 .tuner_sif_gpio = 0x05,
133 .tuner_scl_gpio = 0x1a,
134 .tuner_sda_gpio = 0x1b,
135 .decoder = CX231XX_AVDECODER,
136 .demod_xfer_mode = 0,
137 .ctl_pin_status_mask = 0xFFFFFFC4,
138 .agc_analog_digital_select_gpio = 0x0c,
139 .gpio_pin_status_mask = 0x4001000,
140 .tuner_i2c_master = 1,
141 .demod_i2c_master = 2,
142 .has_dvb = 1,
143 .demod_addr = 0x32,
144 .norm = V4L2_STD_NTSC,
145
146 .input = {{
147 .type = CX231XX_VMUX_TELEVISION,
148 .vmux = CX231XX_VIN_3_1,
149 .amux = CX231XX_AMUX_VIDEO,
150 .gpio = 0,
151 }, {
152 .type = CX231XX_VMUX_COMPOSITE1,
153 .vmux = CX231XX_VIN_2_1,
154 .amux = CX231XX_AMUX_LINE_IN,
155 .gpio = 0,
156 }, {
157 .type = CX231XX_VMUX_SVIDEO,
158 .vmux = CX231XX_VIN_1_1 |
159 (CX231XX_VIN_1_2 << 8) |
160 CX25840_SVIDEO_ON,
161 .amux = CX231XX_AMUX_LINE_IN,
162 .gpio = 0,
163 }
164 },
165 },
166};
167const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards);
168
169/* table of devices that work with this driver */
170struct usb_device_id cx231xx_id_table[] = {
171 {USB_DEVICE(0x0572, 0x5A3C),
172 .driver_info = CX231XX_BOARD_UNKNOWN},
173 {USB_DEVICE(0x0572, 0x58A2),
174 .driver_info = CX231XX_BOARD_CNXT_RDE_250},
175 {USB_DEVICE(0x0572, 0x58A1),
176 .driver_info = CX231XX_BOARD_CNXT_RDU_250},
177 {},
178};
179
180MODULE_DEVICE_TABLE(usb, cx231xx_id_table);
181
182/* cx231xx_tuner_callback
183 * will be used to reset XC5000 tuner using GPIO pin
184 */
185
186int cx231xx_tuner_callback(void *ptr, int component, int command, int arg)
187{
188 int rc = 0;
189 struct cx231xx *dev = ptr;
190
191 if (dev->tuner_type == TUNER_XC5000) {
192 if (command == XC5000_TUNER_RESET) {
193 cx231xx_info
194 ("Tuner CB: RESET: cmd %d : tuner type %d \n",
195 command, dev->tuner_type);
196 cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit,
197 1);
198 msleep(10);
199 cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit,
200 0);
201 msleep(330);
202 cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit,
203 1);
204 msleep(10);
205 }
206 }
207 return rc;
208}
209EXPORT_SYMBOL_GPL(cx231xx_tuner_callback);
210
211static inline void cx231xx_set_model(struct cx231xx *dev)
212{
213 memcpy(&dev->board, &cx231xx_boards[dev->model], sizeof(dev->board));
214}
215
216/* Since cx231xx_pre_card_setup() requires a proper dev->model,
217 * this won't work for boards with generic PCI IDs
218 */
219void cx231xx_pre_card_setup(struct cx231xx *dev)
220{
221
222 cx231xx_set_model(dev);
223
224 cx231xx_info("Identified as %s (card=%d)\n",
225 dev->board.name, dev->model);
226
227 /* set the direction for GPIO pins */
228 cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1);
229 cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1);
230 cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
231
232 /* request some modules if any required */
233
234 /* reset the Tuner */
235 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
236
237 /* set the mode to Analog mode initially */
238 cx231xx_set_mode(dev, CX231XX_ANALOG_MODE);
239
240 /* Unlock device */
241 /* cx231xx_set_mode(dev, CX231XX_SUSPEND); */
242
243}
244
245static void cx231xx_config_tuner(struct cx231xx *dev)
246{
247 struct tuner_setup tun_setup;
248 struct v4l2_frequency f;
249
250 if (dev->tuner_type == TUNER_ABSENT)
251 return;
252
253 tun_setup.mode_mask = T_ANALOG_TV | T_RADIO;
254 tun_setup.type = dev->tuner_type;
255 tun_setup.addr = dev->tuner_addr;
256 tun_setup.tuner_callback = cx231xx_tuner_callback;
257
258 tuner_call(dev, tuner, s_type_addr, &tun_setup);
259
260#if 0
261 if (tun_setup.type == TUNER_XC5000) {
262 static struct xc2028_ctrl ctrl = {
263 .fname = XC5000_DEFAULT_FIRMWARE,
264 .max_len = 64,
265 .demod = 0;
266 };
267 struct v4l2_priv_tun_config cfg = {
268 .tuner = dev->tuner_type,
269 .priv = &ctrl,
270 };
271 tuner_call(dev, tuner, s_config, &cfg);
272 }
273#endif
274 /* configure tuner */
275 f.tuner = 0;
276 f.type = V4L2_TUNER_ANALOG_TV;
277 f.frequency = 9076; /* just a magic number */
278 dev->ctl_freq = f.frequency;
279 call_all(dev, tuner, s_frequency, &f);
280
281}
282
283/* ----------------------------------------------------------------------- */
284void cx231xx_set_ir(struct cx231xx *dev, struct IR_i2c *ir)
285{
286 if (disable_ir) {
287 ir->get_key = NULL;
288 return;
289 }
290
291 /* detect & configure */
292 switch (dev->model) {
293
294 case CX231XX_BOARD_CNXT_RDE_250:
295 break;
296 case CX231XX_BOARD_CNXT_RDU_250:
297 break;
298 default:
299 break;
300 }
301}
302
303void cx231xx_card_setup(struct cx231xx *dev)
304{
305
306 cx231xx_set_model(dev);
307
308 dev->tuner_type = cx231xx_boards[dev->model].tuner_type;
309 if (cx231xx_boards[dev->model].tuner_addr)
310 dev->tuner_addr = cx231xx_boards[dev->model].tuner_addr;
311
312 /* request some modules */
313 if (dev->board.decoder == CX231XX_AVDECODER) {
314 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
315 &dev->i2c_bus[0].i2c_adap,
316 "cx25840", "cx25840", 0x88 >> 1);
317 if (dev->sd_cx25840 == NULL)
318 cx231xx_info("cx25840 subdev registration failure\n");
319 cx25840_call(dev, core, load_fw);
320
321 }
322
323 if (dev->board.tuner_type != TUNER_ABSENT) {
324 dev->sd_tuner = v4l2_i2c_new_subdev(&dev->v4l2_dev,
325 &dev->i2c_bus[1].i2c_adap,
326 "tuner", "tuner", 0xc2 >> 1);
327 if (dev->sd_tuner == NULL)
328 cx231xx_info("tuner subdev registration failure\n");
329
330 cx231xx_config_tuner(dev);
331 }
332
333 cx231xx_config_tuner(dev);
334
335#if 0
336 /* TBD IR will be added later */
337 cx231xx_ir_init(dev);
338#endif
339}
340
341/*
342 * cx231xx_config()
343 * inits registers with sane defaults
344 */
345int cx231xx_config(struct cx231xx *dev)
346{
347 /* TBD need to add cx231xx specific code */
348 dev->mute = 1; /* maybe not the right place... */
349 dev->volume = 0x1f;
350
351 return 0;
352}
353
354/*
355 * cx231xx_config_i2c()
356 * configure i2c attached devices
357 */
358void cx231xx_config_i2c(struct cx231xx *dev)
359{
360 /* u32 input = INPUT(dev->video_input)->vmux; */
361
362 call_all(dev, video, s_stream, 1);
363}
364
365/*
366 * cx231xx_realease_resources()
367 * unregisters the v4l2,i2c and usb devices
368 * called when the device gets disconected or at module unload
369*/
370void cx231xx_release_resources(struct cx231xx *dev)
371{
372
373#if 0 /* TBD IR related */
374 if (dev->ir)
375 cx231xx_ir_fini(dev);
376#endif
377
378 cx231xx_release_analog_resources(dev);
379
380 cx231xx_remove_from_devlist(dev);
381
382 cx231xx_dev_uninit(dev);
383
384 usb_put_dev(dev->udev);
385
386 /* Mark device as unused */
387 cx231xx_devused &= ~(1 << dev->devno);
388}
389
390/*
391 * cx231xx_init_dev()
392 * allocates and inits the device structs, registers i2c bus and v4l device
393 */
394static int cx231xx_init_dev(struct cx231xx **devhandle, struct usb_device *udev,
395 int minor)
396{
397 struct cx231xx *dev = *devhandle;
398 int retval = -ENOMEM;
399 int errCode;
400 unsigned int maxh, maxw;
401
402 dev->udev = udev;
403 mutex_init(&dev->lock);
404 mutex_init(&dev->ctrl_urb_lock);
405 mutex_init(&dev->gpio_i2c_lock);
406
407 spin_lock_init(&dev->video_mode.slock);
408 spin_lock_init(&dev->vbi_mode.slock);
409 spin_lock_init(&dev->sliced_cc_mode.slock);
410
411 init_waitqueue_head(&dev->open);
412 init_waitqueue_head(&dev->wait_frame);
413 init_waitqueue_head(&dev->wait_stream);
414
415 dev->cx231xx_read_ctrl_reg = cx231xx_read_ctrl_reg;
416 dev->cx231xx_write_ctrl_reg = cx231xx_write_ctrl_reg;
417 dev->cx231xx_send_usb_command = cx231xx_send_usb_command;
418 dev->cx231xx_gpio_i2c_read = cx231xx_gpio_i2c_read;
419 dev->cx231xx_gpio_i2c_write = cx231xx_gpio_i2c_write;
420
421 /* Query cx231xx to find what pcb config it is related to */
422 initialize_cx231xx(dev);
423
424 /* Cx231xx pre card setup */
425 cx231xx_pre_card_setup(dev);
426
427 errCode = cx231xx_config(dev);
428 if (errCode) {
429 cx231xx_errdev("error configuring device\n");
430 return -ENOMEM;
431 }
432
433 /* set default norm */
434 dev->norm = dev->board.norm;
435
436 /* register i2c bus */
437 errCode = cx231xx_dev_init(dev);
438 if (errCode < 0) {
439 cx231xx_errdev("%s: cx231xx_i2c_register - errCode [%d]!\n",
440 __func__, errCode);
441 return errCode;
442 }
443
444 /* Do board specific init */
445 cx231xx_card_setup(dev);
446
447 /* configure the device */
448 cx231xx_config_i2c(dev);
449
450 maxw = norm_maxw(dev);
451 maxh = norm_maxh(dev);
452
453 /* set default image size */
454 dev->width = maxw;
455 dev->height = maxh;
456 dev->interlaced = 0;
457 dev->hscale = 0;
458 dev->vscale = 0;
459 dev->video_input = 0;
460
461 errCode = cx231xx_config(dev);
462 if (errCode < 0) {
463 cx231xx_errdev("%s: cx231xx_config - errCode [%d]!\n",
464 __func__, errCode);
465 return errCode;
466 }
467
468 /* init video dma queues */
469 INIT_LIST_HEAD(&dev->video_mode.vidq.active);
470 INIT_LIST_HEAD(&dev->video_mode.vidq.queued);
471
472 /* init vbi dma queues */
473 INIT_LIST_HEAD(&dev->vbi_mode.vidq.active);
474 INIT_LIST_HEAD(&dev->vbi_mode.vidq.queued);
475
476 /* Reset other chips required if they are tied up with GPIO pins */
477
478 cx231xx_add_into_devlist(dev);
479
480 retval = cx231xx_register_analog_devices(dev);
481 if (retval < 0) {
482 cx231xx_release_resources(dev);
483 goto fail_reg_devices;
484 }
485
486 cx231xx_init_extension(dev);
487
488 return 0;
489
490fail_reg_devices:
491 mutex_unlock(&dev->lock);
492 return retval;
493}
494
495#if defined(CONFIG_MODULES) && defined(MODULE)
496static void request_module_async(struct work_struct *work)
497{
498 struct cx231xx *dev = container_of(work,
499 struct cx231xx, request_module_wk);
500
501 if (dev->has_alsa_audio)
502 request_module("cx231xx-alsa");
503
504 if (dev->board.has_dvb)
505 request_module("cx231xx-dvb");
506
507}
508
509static void request_modules(struct cx231xx *dev)
510{
511 INIT_WORK(&dev->request_module_wk, request_module_async);
512 schedule_work(&dev->request_module_wk);
513}
514#else
515#define request_modules(dev)
516#endif /* CONFIG_MODULES */
517
518/*
519 * cx231xx_usb_probe()
520 * checks for supported devices
521 */
522static int cx231xx_usb_probe(struct usb_interface *interface,
523 const struct usb_device_id *id)
524{
525 struct usb_device *udev;
526 struct usb_interface *uif;
527 struct cx231xx *dev = NULL;
528 int retval = -ENODEV;
529 int nr = 0, ifnum;
530 int i, isoc_pipe = 0;
531 char *speed;
532 char descr[255] = "";
533 struct usb_interface *lif = NULL;
534 int skip_interface = 0;
535 struct usb_interface_assoc_descriptor *assoc_desc;
536
537 udev = usb_get_dev(interface_to_usbdev(interface));
538 ifnum = interface->altsetting[0].desc.bInterfaceNumber;
539
540 if (!ifnum) {
541 /*
542 * Interface number 0 - IR interface
543 */
544 /* Check to see next free device and mark as used */
545 nr = find_first_zero_bit(&cx231xx_devused, CX231XX_MAXBOARDS);
546 cx231xx_devused |= 1 << nr;
547
548 if (nr >= CX231XX_MAXBOARDS) {
549 cx231xx_err(DRIVER_NAME ": Supports only %i cx231xx boards.\n",
550 CX231XX_MAXBOARDS);
551 cx231xx_devused &= ~(1 << nr);
552 return -ENOMEM;
553 }
554
555 /* allocate memory for our device state and initialize it */
556 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
557 if (dev == NULL) {
558 cx231xx_err(DRIVER_NAME ": out of memory!\n");
559 cx231xx_devused &= ~(1 << nr);
560 return -ENOMEM;
561 }
562
563 snprintf(dev->name, 29, "cx231xx #%d", nr);
564 dev->devno = nr;
565 dev->model = id->driver_info;
566 dev->video_mode.alt = -1;
567 dev->interface_count++;
568
569 /* reset gpio dir and value */
570 dev->gpio_dir = 0;
571 dev->gpio_val = 0;
572 dev->xc_fw_load_done = 0;
573 dev->has_alsa_audio = 1;
574 dev->power_mode = -1;
575
576 /* 0 - vbi ; 1 -sliced cc mode */
577 dev->vbi_or_sliced_cc_mode = 0;
578
579 /* get maximum no.of IAD interfaces */
580 assoc_desc = udev->actconfig->intf_assoc[0];
581 dev->max_iad_interface_count = assoc_desc->bInterfaceCount;
582
583 /* init CIR module TBD */
584
585 /* store the current interface */
586 lif = interface;
587
588 switch (udev->speed) {
589 case USB_SPEED_LOW:
590 speed = "1.5";
591 break;
592 case USB_SPEED_UNKNOWN:
593 case USB_SPEED_FULL:
594 speed = "12";
595 break;
596 case USB_SPEED_HIGH:
597 speed = "480";
598 break;
599 default:
600 speed = "unknown";
601 }
602
603 if (udev->manufacturer)
604 strlcpy(descr, udev->manufacturer, sizeof(descr));
605
606 if (udev->product) {
607 if (*descr)
608 strlcat(descr, " ", sizeof(descr));
609 strlcat(descr, udev->product, sizeof(descr));
610 }
611 if (*descr)
612 strlcat(descr, " ", sizeof(descr));
613
614 cx231xx_info("New device %s@ %s Mbps "
615 "(%04x:%04x) with %d interfaces\n",
616 descr,
617 speed,
618 le16_to_cpu(udev->descriptor.idVendor),
619 le16_to_cpu(udev->descriptor.idProduct),
620 dev->max_iad_interface_count);
621 } else {
622 /* Get dev structure first */
623 dev = usb_get_intfdata(udev->actconfig->interface[0]);
624 if (dev == NULL) {
625 cx231xx_err(DRIVER_NAME ": out of first interface!\n");
626 return -ENODEV;
627 }
628
629 /* store the interface 0 back */
630 lif = udev->actconfig->interface[0];
631
632 /* increment interface count */
633 dev->interface_count++;
634
635 /* get device number */
636 nr = dev->devno;
637
638 /*
639 * set skip interface, for all interfaces but
640 * interface 1 and the last one
641 */
642 if ((ifnum != 1) && ((dev->interface_count - 1)
643 != dev->max_iad_interface_count))
644 skip_interface = 1;
645
646 if (ifnum == 1) {
647 assoc_desc = udev->actconfig->intf_assoc[0];
648 if (assoc_desc->bFirstInterface != ifnum) {
649 cx231xx_err(DRIVER_NAME ": Not found "
650 "matching IAD interface\n");
651 return -ENODEV;
652 }
653 }
654 }
655
656 if (skip_interface)
657 return -ENODEV;
658
659 cx231xx_info("registering interface %d\n", ifnum);
660
661 /* save our data pointer in this interface device */
662 usb_set_intfdata(lif, dev);
663
664 if ((dev->interface_count - 1) != dev->max_iad_interface_count)
665 return 0;
666
667 /*
668 * AV device initialization - only done at the last interface
669 */
670
671 /* Create v4l2 device */
672 retval = v4l2_device_register(&interface->dev, &dev->v4l2_dev);
673 if (retval) {
674 cx231xx_errdev("v4l2_device_register failed\n");
675 cx231xx_devused &= ~(1 << nr);
676 kfree(dev);
677 return -EIO;
678 }
679
680 /* allocate device struct */
681 retval = cx231xx_init_dev(&dev, udev, nr);
682 if (retval) {
683 cx231xx_devused &= ~(1 << dev->devno);
684 v4l2_device_unregister(&dev->v4l2_dev);
685 kfree(dev);
686 return retval;
687 }
688
689 /* compute alternate max packet sizes for video */
690 uif = udev->actconfig->interface[dev->current_pcb_config.
691 hs_config_info[0].interface_info.video_index + 1];
692
693 dev->video_mode.end_point_addr = le16_to_cpu(uif->altsetting[0].
694 endpoint[isoc_pipe].desc.bEndpointAddress);
695
696 dev->video_mode.num_alt = uif->num_altsetting;
697 cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
698 dev->video_mode.end_point_addr,
699 dev->video_mode.num_alt);
700 dev->video_mode.alt_max_pkt_size =
701 kmalloc(32 * dev->video_mode.num_alt, GFP_KERNEL);
702
703 if (dev->video_mode.alt_max_pkt_size == NULL) {
704 cx231xx_errdev("out of memory!\n");
705 cx231xx_devused &= ~(1 << nr);
706 v4l2_device_unregister(&dev->v4l2_dev);
707 kfree(dev);
708 return -ENOMEM;
709 }
710
711 for (i = 0; i < dev->video_mode.num_alt; i++) {
712 u16 tmp = le16_to_cpu(uif->altsetting[i].endpoint[isoc_pipe].
713 desc.wMaxPacketSize);
714 dev->video_mode.alt_max_pkt_size[i] =
715 (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
716 cx231xx_info("Alternate setting %i, max size= %i\n", i,
717 dev->video_mode.alt_max_pkt_size[i]);
718 }
719
720 /* compute alternate max packet sizes for vbi */
721 uif = udev->actconfig->interface[dev->current_pcb_config.
722 hs_config_info[0].interface_info.
723 vanc_index + 1];
724
725 dev->vbi_mode.end_point_addr =
726 le16_to_cpu(uif->altsetting[0].endpoint[isoc_pipe].desc.
727 bEndpointAddress);
728
729 dev->vbi_mode.num_alt = uif->num_altsetting;
730 cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
731 dev->vbi_mode.end_point_addr,
732 dev->vbi_mode.num_alt);
733 dev->vbi_mode.alt_max_pkt_size =
734 kmalloc(32 * dev->vbi_mode.num_alt, GFP_KERNEL);
735
736 if (dev->vbi_mode.alt_max_pkt_size == NULL) {
737 cx231xx_errdev("out of memory!\n");
738 cx231xx_devused &= ~(1 << nr);
739 v4l2_device_unregister(&dev->v4l2_dev);
740 kfree(dev);
741 return -ENOMEM;
742 }
743
744 for (i = 0; i < dev->vbi_mode.num_alt; i++) {
745 u16 tmp =
746 le16_to_cpu(uif->altsetting[i].endpoint[isoc_pipe].
747 desc.wMaxPacketSize);
748 dev->vbi_mode.alt_max_pkt_size[i] =
749 (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
750 cx231xx_info("Alternate setting %i, max size= %i\n", i,
751 dev->vbi_mode.alt_max_pkt_size[i]);
752 }
753
754 /* compute alternate max packet sizes for sliced CC */
755 uif = udev->actconfig->interface[dev->current_pcb_config.
756 hs_config_info[0].interface_info.
757 hanc_index + 1];
758
759 dev->sliced_cc_mode.end_point_addr =
760 le16_to_cpu(uif->altsetting[0].endpoint[isoc_pipe].desc.
761 bEndpointAddress);
762
763 dev->sliced_cc_mode.num_alt = uif->num_altsetting;
764 cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
765 dev->sliced_cc_mode.end_point_addr,
766 dev->sliced_cc_mode.num_alt);
767 dev->sliced_cc_mode.alt_max_pkt_size =
768 kmalloc(32 * dev->sliced_cc_mode.num_alt, GFP_KERNEL);
769
770 if (dev->sliced_cc_mode.alt_max_pkt_size == NULL) {
771 cx231xx_errdev("out of memory!\n");
772 cx231xx_devused &= ~(1 << nr);
773 v4l2_device_unregister(&dev->v4l2_dev);
774 kfree(dev);
775 return -ENOMEM;
776 }
777
778 for (i = 0; i < dev->sliced_cc_mode.num_alt; i++) {
779 u16 tmp = le16_to_cpu(uif->altsetting[i].endpoint[isoc_pipe].
780 desc.wMaxPacketSize);
781 dev->sliced_cc_mode.alt_max_pkt_size[i] =
782 (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
783 cx231xx_info("Alternate setting %i, max size= %i\n", i,
784 dev->sliced_cc_mode.alt_max_pkt_size[i]);
785 }
786
787 if (dev->current_pcb_config.ts1_source != 0xff) {
788 /* compute alternate max packet sizes for TS1 */
789 uif = udev->actconfig->interface[dev->current_pcb_config.
790 hs_config_info[0].
791 interface_info.
792 ts1_index + 1];
793
794 dev->ts1_mode.end_point_addr =
795 le16_to_cpu(uif->altsetting[0].endpoint[isoc_pipe].
796 desc.bEndpointAddress);
797
798 dev->ts1_mode.num_alt = uif->num_altsetting;
799 cx231xx_info("EndPoint Addr 0x%x, Alternate settings: %i\n",
800 dev->ts1_mode.end_point_addr,
801 dev->ts1_mode.num_alt);
802 dev->ts1_mode.alt_max_pkt_size =
803 kmalloc(32 * dev->ts1_mode.num_alt, GFP_KERNEL);
804
805 if (dev->ts1_mode.alt_max_pkt_size == NULL) {
806 cx231xx_errdev("out of memory!\n");
807 cx231xx_devused &= ~(1 << nr);
808 v4l2_device_unregister(&dev->v4l2_dev);
809 kfree(dev);
810 return -ENOMEM;
811 }
812
813 for (i = 0; i < dev->ts1_mode.num_alt; i++) {
814 u16 tmp = le16_to_cpu(uif->altsetting[i].
815 endpoint[isoc_pipe].desc.
816 wMaxPacketSize);
817 dev->ts1_mode.alt_max_pkt_size[i] =
818 (tmp & 0x07ff) * (((tmp & 0x1800) >> 11) + 1);
819 cx231xx_info("Alternate setting %i, max size= %i\n", i,
820 dev->ts1_mode.alt_max_pkt_size[i]);
821 }
822 }
823
824 /* load other modules required */
825 request_modules(dev);
826
827 return 0;
828}
829
830/*
831 * cx231xx_usb_disconnect()
832 * called when the device gets diconencted
833 * video device will be unregistered on v4l2_close in case it is still open
834 */
835static void cx231xx_usb_disconnect(struct usb_interface *interface)
836{
837 struct cx231xx *dev;
838
839 dev = usb_get_intfdata(interface);
840 usb_set_intfdata(interface, NULL);
841
842 if (!dev)
843 return;
844
845 if (!dev->udev)
846 return;
847
848 /* delete v4l2 device */
849 v4l2_device_unregister(&dev->v4l2_dev);
850
851 /* wait until all current v4l2 io is finished then deallocate
852 resources */
853 mutex_lock(&dev->lock);
854
855 wake_up_interruptible_all(&dev->open);
856
857 if (dev->users) {
858 cx231xx_warn
859 ("device /dev/video%d is open! Deregistration and memory "
860 "deallocation are deferred on close.\n", dev->vdev->num);
861
862 dev->state |= DEV_MISCONFIGURED;
863 cx231xx_uninit_isoc(dev);
864 dev->state |= DEV_DISCONNECTED;
865 wake_up_interruptible(&dev->wait_frame);
866 wake_up_interruptible(&dev->wait_stream);
867 } else {
868 dev->state |= DEV_DISCONNECTED;
869 cx231xx_release_resources(dev);
870 }
871
872 cx231xx_close_extension(dev);
873
874 mutex_unlock(&dev->lock);
875
876 if (!dev->users) {
877 kfree(dev->video_mode.alt_max_pkt_size);
878 kfree(dev->vbi_mode.alt_max_pkt_size);
879 kfree(dev->sliced_cc_mode.alt_max_pkt_size);
880 kfree(dev->ts1_mode.alt_max_pkt_size);
881 kfree(dev);
882 }
883}
884
885static struct usb_driver cx231xx_usb_driver = {
886 .name = "cx231xx",
887 .probe = cx231xx_usb_probe,
888 .disconnect = cx231xx_usb_disconnect,
889 .id_table = cx231xx_id_table,
890};
891
892static int __init cx231xx_module_init(void)
893{
894 int result;
895
896 printk(KERN_INFO DRIVER_NAME " v4l2 driver loaded.\n");
897
898 /* register this driver with the USB subsystem */
899 result = usb_register(&cx231xx_usb_driver);
900 if (result)
901 cx231xx_err(DRIVER_NAME
902 " usb_register failed. Error number %d.\n", result);
903
904 return result;
905}
906
907static void __exit cx231xx_module_exit(void)
908{
909 /* deregister this driver with the USB subsystem */
910 usb_deregister(&cx231xx_usb_driver);
911}
912
913module_init(cx231xx_module_init);
914module_exit(cx231xx_module_exit);
diff --git a/drivers/media/video/cx231xx/cx231xx-conf-reg.h b/drivers/media/video/cx231xx/cx231xx-conf-reg.h
new file mode 100644
index 000000000000..a6f398a175c5
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-conf-reg.h
@@ -0,0 +1,494 @@
1/*
2 cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB
3 video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _POLARIS_REG_H_
23#define _POLARIS_REG_H_
24
25#define BOARD_CFG_STAT 0x0
26#define TS_MODE_REG 0x4
27#define TS1_CFG_REG 0x8
28#define TS1_LENGTH_REG 0xc
29#define TS2_CFG_REG 0x10
30#define TS2_LENGTH_REG 0x14
31#define EP_MODE_SET 0x18
32#define CIR_PWR_PTN1 0x1c
33#define CIR_PWR_PTN2 0x20
34#define CIR_PWR_PTN3 0x24
35#define CIR_PWR_MASK0 0x28
36#define CIR_PWR_MASK1 0x2c
37#define CIR_PWR_MASK2 0x30
38#define CIR_GAIN 0x34
39#define CIR_CAR_REG 0x38
40#define CIR_OT_CFG1 0x40
41#define CIR_OT_CFG2 0x44
42#define PWR_CTL_EN 0x74
43
44/* Polaris Endpoints capture mask for register EP_MODE_SET */
45#define ENABLE_EP1 0x01 /* Bit[0]=1 */
46#define ENABLE_EP2 0x02 /* Bit[1]=1 */
47#define ENABLE_EP3 0x04 /* Bit[2]=1 */
48#define ENABLE_EP4 0x08 /* Bit[3]=1 */
49#define ENABLE_EP5 0x10 /* Bit[4]=1 */
50#define ENABLE_EP6 0x20 /* Bit[5]=1 */
51
52/* Bit definition for register PWR_CTL_EN */
53#define PWR_MODE_MASK 0x17f
54#define PWR_AV_EN 0x08 /* bit3 */
55#define PWR_ISO_EN 0x40 /* bit6 */
56#define PWR_AV_MODE 0x30 /* bit4,5 */
57#define PWR_TUNER_EN 0x04 /* bit2 */
58#define PWR_DEMOD_EN 0x02 /* bit1 */
59#define I2C_DEMOD_EN 0x01 /* bit0 */
60#define PWR_RESETOUT_EN 0x100 /* bit8 */
61
62enum AV_MODE{
63 POLARIS_AVMODE_DEFAULT = 0,
64 POLARIS_AVMODE_DIGITAL = 0x10,
65 POLARIS_AVMODE_ANALOGT_TV = 0x20,
66 POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
67
68};
69
70/* Colibri Registers */
71
72#define SINGLE_ENDED 0x0
73#define LOW_IF 0x4
74#define EU_IF 0x9
75#define US_IF 0xa
76
77#define SUP_BLK_TUNE1 0x00
78#define SUP_BLK_TUNE2 0x01
79#define SUP_BLK_TUNE3 0x02
80#define SUP_BLK_XTAL 0x03
81#define SUP_BLK_PLL1 0x04
82#define SUP_BLK_PLL2 0x05
83#define SUP_BLK_PLL3 0x06
84#define SUP_BLK_REF 0x07
85#define SUP_BLK_PWRDN 0x08
86#define SUP_BLK_TESTPAD 0x09
87#define ADC_COM_INT5_STAB_REF 0x0a
88#define ADC_COM_QUANT 0x0b
89#define ADC_COM_BIAS1 0x0c
90#define ADC_COM_BIAS2 0x0d
91#define ADC_COM_BIAS3 0x0e
92#define TESTBUS_CTRL 0x12
93
94#define FLD_PWRDN_TUNING_BIAS 0x10
95#define FLD_PWRDN_ENABLE_PLL 0x08
96#define FLD_PWRDN_PD_BANDGAP 0x04
97#define FLD_PWRDN_PD_BIAS 0x02
98#define FLD_PWRDN_PD_TUNECK 0x01
99
100
101#define ADC_STATUS_CH1 0x20
102#define ADC_STATUS_CH2 0x40
103#define ADC_STATUS_CH3 0x60
104
105#define ADC_STATUS2_CH1 0x21
106#define ADC_STATUS2_CH2 0x41
107#define ADC_STATUS2_CH3 0x61
108
109#define ADC_CAL_ATEST_CH1 0x22
110#define ADC_CAL_ATEST_CH2 0x42
111#define ADC_CAL_ATEST_CH3 0x62
112
113#define ADC_PWRDN_CLAMP_CH1 0x23
114#define ADC_PWRDN_CLAMP_CH2 0x43
115#define ADC_PWRDN_CLAMP_CH3 0x63
116
117#define ADC_CTRL_DAC23_CH1 0x24
118#define ADC_CTRL_DAC23_CH2 0x44
119#define ADC_CTRL_DAC23_CH3 0x64
120
121#define ADC_CTRL_DAC1_CH1 0x25
122#define ADC_CTRL_DAC1_CH2 0x45
123#define ADC_CTRL_DAC1_CH3 0x65
124
125#define ADC_DCSERVO_DEM_CH1 0x26
126#define ADC_DCSERVO_DEM_CH2 0x46
127#define ADC_DCSERVO_DEM_CH3 0x66
128
129#define ADC_FB_FRCRST_CH1 0x27
130#define ADC_FB_FRCRST_CH2 0x47
131#define ADC_FB_FRCRST_CH3 0x67
132
133#define ADC_INPUT_CH1 0x28
134#define ADC_INPUT_CH2 0x48
135#define ADC_INPUT_CH3 0x68
136#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */
137
138#define ADC_NTF_PRECLMP_EN_CH1 0x29
139#define ADC_NTF_PRECLMP_EN_CH2 0x49
140#define ADC_NTF_PRECLMP_EN_CH3 0x69
141
142#define ADC_QGAIN_RES_TRM_CH1 0x2a
143#define ADC_QGAIN_RES_TRM_CH2 0x4a
144#define ADC_QGAIN_RES_TRM_CH3 0x6a
145
146#define ADC_SOC_PRECLMP_TERM_CH1 0x2b
147#define ADC_SOC_PRECLMP_TERM_CH2 0x4b
148#define ADC_SOC_PRECLMP_TERM_CH3 0x6b
149
150#define TESTBUS_CTRL_CH1 0x32
151#define TESTBUS_CTRL_CH2 0x52
152#define TESTBUS_CTRL_CH3 0x72
153
154/******************************************************************************
155 * DIF registers *
156 ******************************************************************************/
157#define DIRECT_IF_REVB_BASE 0x00300
158
159/*****************************************************************************/
160#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000)
161/*****************************************************************************/
162#define FLD_DIF_PLL_LOCK 0x80000000
163/* Reserved [30:29] */
164#define FLD_DIF_PLL_FREE_RUN 0x10000000
165#define FLD_DIF_PLL_FREQ 0x0fffffff
166
167/*****************************************************************************/
168#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004)
169/*****************************************************************************/
170#define FLD_DIF_KD_PD 0xff000000
171/* Reserved [23:20] */
172#define FLD_DIF_KDS_PD 0x000f0000
173#define FLD_DIF_KI_PD 0x0000ff00
174/* Reserved [7:4] */
175#define FLD_DIF_KIS_PD 0x0000000f
176
177/*****************************************************************************/
178#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008)
179/*****************************************************************************/
180#define FLD_DIF_KD_FD 0xff000000
181/* Reserved [23:20] */
182#define FLD_DIF_KDS_FD 0x000f0000
183#define FLD_DIF_KI_FD 0x0000ff00
184#define FLD_DIF_SIG_PROP_SZ 0x000000f0
185#define FLD_DIF_KIS_FD 0x0000000f
186
187/*****************************************************************************/
188#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c)
189/*****************************************************************************/
190#define FLD_DIF_PLL_AGC_REF 0xfff00000
191#define FLD_DIF_PLL_AGC_KI 0x000f0000
192/* Reserved [15] */
193#define FLD_DIF_FREQ_LIMIT 0x00007000
194#define FLD_DIF_K_FD 0x00000f00
195#define FLD_DIF_DOWNSMPL_FD 0x000000ff
196
197/*****************************************************************************/
198#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010)
199/*****************************************************************************/
200/* Reserved [31:16] */
201#define FLD_DIF_PLL_AGC_EN 0x00008000
202/* Reserved [14:12] */
203#define FLD_DIF_PLL_MAN_GAIN 0x00000fff
204
205/*****************************************************************************/
206#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014)
207/*****************************************************************************/
208#define FLD_DIF_K_AGC_RF 0xf0000000
209#define FLD_DIF_K_AGC_IF 0x0f000000
210#define FLD_DIF_K_AGC_INT 0x00f00000
211/* Reserved [19:12] */
212#define FLD_DIF_IF_REF 0x00000fff
213
214/*****************************************************************************/
215#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018)
216/*****************************************************************************/
217#define FLD_DIF_IF_MAX 0xff000000
218#define FLD_DIF_IF_MIN 0x00ff0000
219#define FLD_DIF_IF_AGC 0x0000ffff
220
221/*****************************************************************************/
222#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c)
223/*****************************************************************************/
224#define FLD_DIF_INT_MAX 0xff000000
225#define FLD_DIF_INT_MIN 0x00ff0000
226#define FLD_DIF_INT_AGC 0x0000ffff
227
228/*****************************************************************************/
229#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020)
230/*****************************************************************************/
231#define FLD_DIF_RF_MAX 0xff000000
232#define FLD_DIF_RF_MIN 0x00ff0000
233#define FLD_DIF_RF_AGC 0x0000ffff
234
235/*****************************************************************************/
236#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024)
237/*****************************************************************************/
238#define FLD_DIF_IF_AGC_IN 0xffff0000
239#define FLD_DIF_INT_AGC_IN 0x0000ffff
240
241/*****************************************************************************/
242#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028)
243/*****************************************************************************/
244/* Reserved [31:16] */
245#define FLD_DIF_RF_AGC_IN 0x0000ffff
246
247/*****************************************************************************/
248#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c)
249/*****************************************************************************/
250#define FLD_DIF_AFD 0xc0000000
251#define FLD_DIF_K_VID_AGC 0x30000000
252#define FLD_DIF_LINE_LENGTH 0x0fff0000
253#define FLD_DIF_AGC_GAIN 0x0000ffff
254
255/*****************************************************************************/
256#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030)
257/*****************************************************************************/
258#define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000
259/* Reserved [30:30] */
260#define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000
261/* Reserved [23:17] */
262#define FLD_DIF_VID_AGC_OVERRIDE 0x00010000
263#define FLD_DIF_VID_MAN_GAIN 0x0000ffff
264
265/*****************************************************************************/
266#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034)
267/*****************************************************************************/
268#define FLD_DIF_LPF_FREQ 0xc0000000
269#define FLD_DIF_AV_PHASE_INC 0x3f000000
270#define FLD_DIF_AUDIO_FREQ 0x00ffffff
271
272/*****************************************************************************/
273#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038)
274/*****************************************************************************/
275/* Reserved [31:24] */
276#define FLD_DIF_IIR23_R2 0x00ff0000
277#define FLD_DIF_IIR23_R1 0x0000ff00
278#define FLD_DIF_IIR1_R1 0x000000ff
279
280/*****************************************************************************/
281#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c)
282/*****************************************************************************/
283#define FLD_DIF_DIF_BYPASS 0x80000000
284#define FLD_DIF_FM_NYQ_GAIN 0x40000000
285#define FLD_DIF_RF_AGC_ENA 0x20000000
286#define FLD_DIF_INT_AGC_ENA 0x10000000
287#define FLD_DIF_IF_AGC_ENA 0x08000000
288#define FLD_DIF_FORCE_RF_IF_LOCK 0x04000000
289#define FLD_DIF_VIDEO_AGC_ENA 0x02000000
290#define FLD_DIF_RF_AGC_INV 0x01000000
291#define FLD_DIF_INT_AGC_INV 0x00800000
292#define FLD_DIF_IF_AGC_INV 0x00400000
293#define FLD_DIF_SPEC_INV 0x00200000
294#define FLD_DIF_AUD_FULL_BW 0x00100000
295#define FLD_DIF_AUD_SRC_SEL 0x00080000
296/* Reserved [18] */
297#define FLD_DIF_IF_FREQ 0x00030000
298/* Reserved [15:14] */
299#define FLD_DIF_TIP_OFFSET 0x00003f00
300/* Reserved [7:5] */
301#define FLD_DIF_DITHER_ENA 0x00000010
302/* Reserved [3:1] */
303#define FLD_DIF_RF_IF_LOCK 0x00000001
304
305/*****************************************************************************/
306#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040)
307/*****************************************************************************/
308/* Reserved [31:29] */
309#define FLD_DIF_PHASE_INC 0x1fffffff
310
311/*****************************************************************************/
312#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044)
313/*****************************************************************************/
314/* Reserved [31:16] */
315#define FLD_DIF_SRC_KI 0x0000ff00
316#define FLD_DIF_SRC_KD 0x000000ff
317
318/*****************************************************************************/
319#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048)
320/*****************************************************************************/
321/* Reserved [31:19] */
322#define FLD_DIF_BPF_COEFF_0 0x00070000
323/* Reserved [15:4] */
324#define FLD_DIF_BPF_COEFF_1 0x0000000f
325
326/*****************************************************************************/
327#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c)
328/*****************************************************************************/
329/* Reserved [31:22] */
330#define FLD_DIF_BPF_COEFF_2 0x003f0000
331/* Reserved [15:7] */
332#define FLD_DIF_BPF_COEFF_3 0x0000007f
333
334/*****************************************************************************/
335#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050)
336/*****************************************************************************/
337/* Reserved [31:24] */
338#define FLD_DIF_BPF_COEFF_4 0x00ff0000
339/* Reserved [15:8] */
340#define FLD_DIF_BPF_COEFF_5 0x000000ff
341
342/*****************************************************************************/
343#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054)
344/*****************************************************************************/
345/* Reserved [31:25] */
346#define FLD_DIF_BPF_COEFF_6 0x01ff0000
347/* Reserved [15:9] */
348#define FLD_DIF_BPF_COEFF_7 0x000001ff
349
350/*****************************************************************************/
351#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058)
352/*****************************************************************************/
353/* Reserved [31:26] */
354#define FLD_DIF_BPF_COEFF_8 0x03ff0000
355/* Reserved [15:10] */
356#define FLD_DIF_BPF_COEFF_9 0x000003ff
357
358/*****************************************************************************/
359#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c)
360/*****************************************************************************/
361/* Reserved [31:27] */
362#define FLD_DIF_BPF_COEFF_10 0x07ff0000
363/* Reserved [15:11] */
364#define FLD_DIF_BPF_COEFF_11 0x000007ff
365
366/*****************************************************************************/
367#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060)
368/*****************************************************************************/
369/* Reserved [31:27] */
370#define FLD_DIF_BPF_COEFF_12 0x07ff0000
371/* Reserved [15:12] */
372#define FLD_DIF_BPF_COEFF_13 0x00000fff
373
374/*****************************************************************************/
375#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064)
376/*****************************************************************************/
377/* Reserved [31:28] */
378#define FLD_DIF_BPF_COEFF_14 0x0fff0000
379/* Reserved [15:12] */
380#define FLD_DIF_BPF_COEFF_15 0x00000fff
381
382/*****************************************************************************/
383#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068)
384/*****************************************************************************/
385/* Reserved [31:29] */
386#define FLD_DIF_BPF_COEFF_16 0x1fff0000
387/* Reserved [15:13] */
388#define FLD_DIF_BPF_COEFF_17 0x00001fff
389
390/*****************************************************************************/
391#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c)
392/*****************************************************************************/
393/* Reserved [31:29] */
394#define FLD_DIF_BPF_COEFF_18 0x1fff0000
395/* Reserved [15:13] */
396#define FLD_DIF_BPF_COEFF_19 0x00001fff
397
398/*****************************************************************************/
399#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070)
400/*****************************************************************************/
401/* Reserved [31:29] */
402#define FLD_DIF_BPF_COEFF_20 0x1fff0000
403/* Reserved [15:14] */
404#define FLD_DIF_BPF_COEFF_21 0x00003fff
405
406/*****************************************************************************/
407#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074)
408/*****************************************************************************/
409/* Reserved [31:30] */
410#define FLD_DIF_BPF_COEFF_22 0x3fff0000
411/* Reserved [15:14] */
412#define FLD_DIF_BPF_COEFF_23 0x00003fff
413
414/*****************************************************************************/
415#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078)
416/*****************************************************************************/
417/* Reserved [31:30] */
418#define FLD_DIF_BPF_COEFF_24 0x3fff0000
419/* Reserved [15:14] */
420#define FLD_DIF_BPF_COEFF_25 0x00003fff
421
422/*****************************************************************************/
423#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c)
424/*****************************************************************************/
425/* Reserved [31:30] */
426#define FLD_DIF_BPF_COEFF_26 0x3fff0000
427/* Reserved [15:14] */
428#define FLD_DIF_BPF_COEFF_27 0x00003fff
429
430/*****************************************************************************/
431#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080)
432/*****************************************************************************/
433/* Reserved [31:30] */
434#define FLD_DIF_BPF_COEFF_28 0x3fff0000
435/* Reserved [15:14] */
436#define FLD_DIF_BPF_COEFF_29 0x00003fff
437
438/*****************************************************************************/
439#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084)
440/*****************************************************************************/
441/* Reserved [31:30] */
442#define FLD_DIF_BPF_COEFF_30 0x3fff0000
443/* Reserved [15:14] */
444#define FLD_DIF_BPF_COEFF_31 0x00003fff
445
446/*****************************************************************************/
447#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088)
448/*****************************************************************************/
449/* Reserved [31:30] */
450#define FLD_DIF_BPF_COEFF_32 0x3fff0000
451/* Reserved [15:14] */
452#define FLD_DIF_BPF_COEFF_33 0x00003fff
453
454/*****************************************************************************/
455#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c)
456/*****************************************************************************/
457/* Reserved [31:30] */
458#define FLD_DIF_BPF_COEFF_34 0x3fff0000
459/* Reserved [15:14] */
460#define FLD_DIF_BPF_COEFF_35 0x00003fff
461
462/*****************************************************************************/
463#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090)
464/*****************************************************************************/
465/* Reserved [31:30] */
466#define FLD_DIF_BPF_COEFF_36 0x3fff0000
467/* Reserved [15:0] */
468
469/*****************************************************************************/
470#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094)
471/*****************************************************************************/
472/* Reserved [31:20] */
473#define FLD_DIF_RPT_VARIANCE 0x000fffff
474
475/*****************************************************************************/
476#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098)
477/*****************************************************************************/
478/* Reserved [31:8] */
479#define FLD_DIF_DIF_SOFT_RST 0x00000080
480#define FLD_DIF_DIF_REG_RST_MSK 0x00000040
481#define FLD_DIF_AGC_RST_MSK 0x00000020
482#define FLD_DIF_CMP_RST_MSK 0x00000010
483#define FLD_DIF_AVS_RST_MSK 0x00000008
484#define FLD_DIF_NYQ_RST_MSK 0x00000004
485#define FLD_DIF_DIF_SRC_RST_MSK 0x00000002
486#define FLD_DIF_PLL_RST_MSK 0x00000001
487
488/*****************************************************************************/
489#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c)
490/*****************************************************************************/
491/* Reserved [31:25] */
492#define FLD_DIF_CTL_IP 0x01ffffff
493
494#endif
diff --git a/drivers/media/video/cx231xx/cx231xx-core.c b/drivers/media/video/cx231xx/cx231xx-core.c
new file mode 100644
index 000000000000..0d333e679f70
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-core.c
@@ -0,0 +1,1200 @@
1/*
2 cx231xx-core.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6 Based on em28xx driver
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/module.h>
26#include <linux/usb.h>
27#include <linux/vmalloc.h>
28#include <media/v4l2-common.h>
29
30#include "cx231xx.h"
31#include "cx231xx-reg.h"
32
33/* #define ENABLE_DEBUG_ISOC_FRAMES */
34
35static unsigned int core_debug;
36module_param(core_debug, int, 0644);
37MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
38
39#define cx231xx_coredbg(fmt, arg...) do {\
40 if (core_debug) \
41 printk(KERN_INFO "%s %s :"fmt, \
42 dev->name, __func__ , ##arg); } while (0)
43
44static unsigned int reg_debug;
45module_param(reg_debug, int, 0644);
46MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
47
48#define cx231xx_regdbg(fmt, arg...) do {\
49 if (reg_debug) \
50 printk(KERN_INFO "%s %s :"fmt, \
51 dev->name, __func__ , ##arg); } while (0)
52
53static int alt = CX231XX_PINOUT;
54module_param(alt, int, 0644);
55MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
56
57#define cx231xx_isocdbg(fmt, arg...) do {\
58 if (core_debug) \
59 printk(KERN_INFO "%s %s :"fmt, \
60 dev->name, __func__ , ##arg); } while (0)
61
62/*****************************************************************
63* Device control list functions *
64******************************************************************/
65
66static LIST_HEAD(cx231xx_devlist);
67static DEFINE_MUTEX(cx231xx_devlist_mutex);
68
69struct cx231xx *cx231xx_get_device(int minor,
70 enum v4l2_buf_type *fh_type, int *has_radio)
71{
72 struct cx231xx *h, *dev = NULL;
73
74 *fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
75 *has_radio = 0;
76
77 mutex_lock(&cx231xx_devlist_mutex);
78 list_for_each_entry(h, &cx231xx_devlist, devlist) {
79 if (h->vdev->minor == minor)
80 dev = h;
81 if (h->vbi_dev->minor == minor) {
82 dev = h;
83 *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE;
84 }
85 if (h->radio_dev && h->radio_dev->minor == minor) {
86 dev = h;
87 *has_radio = 1;
88 }
89 }
90 mutex_unlock(&cx231xx_devlist_mutex);
91
92 return dev;
93}
94
95/*
96 * cx231xx_realease_resources()
97 * unregisters the v4l2,i2c and usb devices
98 * called when the device gets disconected or at module unload
99*/
100void cx231xx_remove_from_devlist(struct cx231xx *dev)
101{
102 mutex_lock(&cx231xx_devlist_mutex);
103 list_del(&dev->devlist);
104 mutex_unlock(&cx231xx_devlist_mutex);
105};
106
107void cx231xx_add_into_devlist(struct cx231xx *dev)
108{
109 mutex_lock(&cx231xx_devlist_mutex);
110 list_add_tail(&dev->devlist, &cx231xx_devlist);
111 mutex_unlock(&cx231xx_devlist_mutex);
112};
113
114static LIST_HEAD(cx231xx_extension_devlist);
115static DEFINE_MUTEX(cx231xx_extension_devlist_lock);
116
117int cx231xx_register_extension(struct cx231xx_ops *ops)
118{
119 struct cx231xx *dev = NULL;
120
121 mutex_lock(&cx231xx_devlist_mutex);
122 mutex_lock(&cx231xx_extension_devlist_lock);
123 list_add_tail(&ops->next, &cx231xx_extension_devlist);
124 list_for_each_entry(dev, &cx231xx_devlist, devlist) {
125 if (dev)
126 ops->init(dev);
127 }
128 printk(KERN_INFO DRIVER_NAME ": %s initialized\n", ops->name);
129 mutex_unlock(&cx231xx_extension_devlist_lock);
130 mutex_unlock(&cx231xx_devlist_mutex);
131 return 0;
132}
133EXPORT_SYMBOL(cx231xx_register_extension);
134
135void cx231xx_unregister_extension(struct cx231xx_ops *ops)
136{
137 struct cx231xx *dev = NULL;
138
139 mutex_lock(&cx231xx_devlist_mutex);
140 list_for_each_entry(dev, &cx231xx_devlist, devlist) {
141 if (dev)
142 ops->fini(dev);
143 }
144
145 mutex_lock(&cx231xx_extension_devlist_lock);
146 printk(KERN_INFO DRIVER_NAME ": %s removed\n", ops->name);
147 list_del(&ops->next);
148 mutex_unlock(&cx231xx_extension_devlist_lock);
149 mutex_unlock(&cx231xx_devlist_mutex);
150}
151EXPORT_SYMBOL(cx231xx_unregister_extension);
152
153void cx231xx_init_extension(struct cx231xx *dev)
154{
155 struct cx231xx_ops *ops = NULL;
156
157 mutex_lock(&cx231xx_extension_devlist_lock);
158 if (!list_empty(&cx231xx_extension_devlist)) {
159 list_for_each_entry(ops, &cx231xx_extension_devlist, next) {
160 if (ops->init)
161 ops->init(dev);
162 }
163 }
164 mutex_unlock(&cx231xx_extension_devlist_lock);
165}
166
167void cx231xx_close_extension(struct cx231xx *dev)
168{
169 struct cx231xx_ops *ops = NULL;
170
171 mutex_lock(&cx231xx_extension_devlist_lock);
172 if (!list_empty(&cx231xx_extension_devlist)) {
173 list_for_each_entry(ops, &cx231xx_extension_devlist, next) {
174 if (ops->fini)
175 ops->fini(dev);
176 }
177 }
178 mutex_unlock(&cx231xx_extension_devlist_lock);
179}
180
181/****************************************************************
182* U S B related functions *
183*****************************************************************/
184int cx231xx_send_usb_command(struct cx231xx_i2c *i2c_bus,
185 struct cx231xx_i2c_xfer_data *req_data)
186{
187 int status = 0;
188 struct cx231xx *dev = i2c_bus->dev;
189 struct VENDOR_REQUEST_IN ven_req;
190
191 u8 saddr_len = 0;
192 u8 _i2c_period = 0;
193 u8 _i2c_nostop = 0;
194 u8 _i2c_reserve = 0;
195
196 /* Get the I2C period, nostop and reserve parameters */
197 _i2c_period = i2c_bus->i2c_period;
198 _i2c_nostop = i2c_bus->i2c_nostop;
199 _i2c_reserve = i2c_bus->i2c_reserve;
200
201 saddr_len = req_data->saddr_len;
202
203 /* Set wValue */
204 if (saddr_len == 1) /* need check saddr_len == 0 */
205 ven_req.wValue =
206 req_data->
207 dev_addr << 9 | _i2c_period << 4 | saddr_len << 2 |
208 _i2c_nostop << 1 | I2C_SYNC | _i2c_reserve << 6;
209 else
210 ven_req.wValue =
211 req_data->
212 dev_addr << 9 | _i2c_period << 4 | saddr_len << 2 |
213 _i2c_nostop << 1 | I2C_SYNC | _i2c_reserve << 6;
214
215 /* set channel number */
216 if (req_data->direction & I2C_M_RD) {
217 /* channel number, for read,spec required channel_num +4 */
218 ven_req.bRequest = i2c_bus->nr + 4;
219 } else
220 ven_req.bRequest = i2c_bus->nr; /* channel number, */
221
222 /* set index value */
223 switch (saddr_len) {
224 case 0:
225 ven_req.wIndex = 0; /* need check */
226 break;
227 case 1:
228 ven_req.wIndex = (req_data->saddr_dat & 0xff);
229 break;
230 case 2:
231 ven_req.wIndex = req_data->saddr_dat;
232 break;
233 }
234
235 /* set wLength value */
236 ven_req.wLength = req_data->buf_size;
237
238 /* set bData value */
239 ven_req.bData = 0;
240
241 /* set the direction */
242 if (req_data->direction) {
243 ven_req.direction = USB_DIR_IN;
244 memset(req_data->p_buffer, 0x00, ven_req.wLength);
245 } else
246 ven_req.direction = USB_DIR_OUT;
247
248 /* set the buffer for read / write */
249 ven_req.pBuff = req_data->p_buffer;
250
251
252 /* call common vendor command request */
253 status = cx231xx_send_vendor_cmd(dev, &ven_req);
254 if (status < 0) {
255 cx231xx_info
256 ("UsbInterface::sendCommand, failed with status -%d\n",
257 status);
258 }
259
260 return status;
261}
262EXPORT_SYMBOL_GPL(cx231xx_send_usb_command);
263
264/*
265 * cx231xx_read_ctrl_reg()
266 * reads data from the usb device specifying bRequest and wValue
267 */
268int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
269 char *buf, int len)
270{
271 u8 val = 0;
272 int ret;
273 int pipe = usb_rcvctrlpipe(dev->udev, 0);
274
275 if (dev->state & DEV_DISCONNECTED)
276 return -ENODEV;
277
278 if (len > URB_MAX_CTRL_SIZE)
279 return -EINVAL;
280
281 switch (len) {
282 case 1:
283 val = ENABLE_ONE_BYTE;
284 break;
285 case 2:
286 val = ENABLE_TWE_BYTE;
287 break;
288 case 3:
289 val = ENABLE_THREE_BYTE;
290 break;
291 case 4:
292 val = ENABLE_FOUR_BYTE;
293 break;
294 default:
295 val = 0xFF; /* invalid option */
296 }
297
298 if (val == 0xFF)
299 return -EINVAL;
300
301 if (reg_debug) {
302 cx231xx_isocdbg("(pipe 0x%08x): "
303 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
304 pipe,
305 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
306 req, 0, val,
307 reg & 0xff, reg >> 8, len & 0xff, len >> 8);
308 }
309
310 mutex_lock(&dev->ctrl_urb_lock);
311 ret = usb_control_msg(dev->udev, pipe, req,
312 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
313 val, reg, dev->urb_buf, len, HZ);
314 if (ret < 0) {
315 cx231xx_isocdbg(" failed!\n");
316 /* mutex_unlock(&dev->ctrl_urb_lock); */
317 return ret;
318 }
319
320 if (len)
321 memcpy(buf, dev->urb_buf, len);
322
323 mutex_unlock(&dev->ctrl_urb_lock);
324
325 if (reg_debug) {
326 int byte;
327
328 cx231xx_isocdbg("<<<");
329 for (byte = 0; byte < len; byte++)
330 cx231xx_isocdbg(" %02x", (unsigned char)buf[byte]);
331 cx231xx_isocdbg("\n");
332 }
333
334 return ret;
335}
336
337int cx231xx_send_vendor_cmd(struct cx231xx *dev,
338 struct VENDOR_REQUEST_IN *ven_req)
339{
340 int ret;
341 int pipe = 0;
342
343 if (dev->state & DEV_DISCONNECTED)
344 return -ENODEV;
345
346 if ((ven_req->wLength > URB_MAX_CTRL_SIZE))
347 return -EINVAL;
348
349 if (ven_req->direction)
350 pipe = usb_rcvctrlpipe(dev->udev, 0);
351 else
352 pipe = usb_sndctrlpipe(dev->udev, 0);
353
354 if (reg_debug) {
355 int byte;
356
357 cx231xx_isocdbg("(pipe 0x%08x): "
358 "OUT: %02x %02x %02x %04x %04x %04x >>>",
359 pipe,
360 ven_req->
361 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
362 ven_req->bRequest, 0, ven_req->wValue,
363 ven_req->wIndex, ven_req->wLength);
364
365 for (byte = 0; byte < ven_req->wLength; byte++)
366 cx231xx_isocdbg(" %02x",
367 (unsigned char)ven_req->pBuff[byte]);
368 cx231xx_isocdbg("\n");
369 }
370
371 mutex_lock(&dev->ctrl_urb_lock);
372 ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest,
373 ven_req->
374 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
375 ven_req->wValue, ven_req->wIndex, ven_req->pBuff,
376 ven_req->wLength, HZ);
377 mutex_unlock(&dev->ctrl_urb_lock);
378
379 return ret;
380}
381
382/*
383 * cx231xx_write_ctrl_reg()
384 * sends data to the usb device, specifying bRequest
385 */
386int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, char *buf,
387 int len)
388{
389 u8 val = 0;
390 int ret;
391 int pipe = usb_sndctrlpipe(dev->udev, 0);
392
393 if (dev->state & DEV_DISCONNECTED)
394 return -ENODEV;
395
396 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
397 return -EINVAL;
398
399 switch (len) {
400 case 1:
401 val = ENABLE_ONE_BYTE;
402 break;
403 case 2:
404 val = ENABLE_TWE_BYTE;
405 break;
406 case 3:
407 val = ENABLE_THREE_BYTE;
408 break;
409 case 4:
410 val = ENABLE_FOUR_BYTE;
411 break;
412 default:
413 val = 0xFF; /* invalid option */
414 }
415
416 if (val == 0xFF)
417 return -EINVAL;
418
419 if (reg_debug) {
420 int byte;
421
422 cx231xx_isocdbg("(pipe 0x%08x): "
423 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
424 pipe,
425 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
426 req, 0, val, reg & 0xff,
427 reg >> 8, len & 0xff, len >> 8);
428
429 for (byte = 0; byte < len; byte++)
430 cx231xx_isocdbg(" %02x", (unsigned char)buf[byte]);
431 cx231xx_isocdbg("\n");
432 }
433
434 mutex_lock(&dev->ctrl_urb_lock);
435 memcpy(dev->urb_buf, buf, len);
436 ret = usb_control_msg(dev->udev, pipe, req,
437 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
438 val, reg, dev->urb_buf, len, HZ);
439 mutex_unlock(&dev->ctrl_urb_lock);
440
441 return ret;
442}
443
444/****************************************************************
445* USB Alternate Setting functions *
446*****************************************************************/
447
448int cx231xx_set_video_alternate(struct cx231xx *dev)
449{
450 int errCode, prev_alt = dev->video_mode.alt;
451 unsigned int min_pkt_size = dev->width * 2 + 4;
452 u32 usb_interface_index = 0;
453
454 /* When image size is bigger than a certain value,
455 the frame size should be increased, otherwise, only
456 green screen will be received.
457 */
458 if (dev->width * 2 * dev->height > 720 * 240 * 2)
459 min_pkt_size *= 2;
460
461 if (dev->width > 360) {
462 /* resolutions: 720,704,640 */
463 dev->video_mode.alt = 3;
464 } else if (dev->width > 180) {
465 /* resolutions: 360,352,320,240 */
466 dev->video_mode.alt = 2;
467 } else if (dev->width > 0) {
468 /* resolutions: 180,176,160,128,88 */
469 dev->video_mode.alt = 1;
470 } else {
471 /* Change to alt0 BULK to release USB bandwidth */
472 dev->video_mode.alt = 0;
473 }
474
475 /* Get the correct video interface Index */
476 usb_interface_index =
477 dev->current_pcb_config.hs_config_info[0].interface_info.
478 video_index + 1;
479
480 if (dev->video_mode.alt != prev_alt) {
481 cx231xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
482 min_pkt_size, dev->video_mode.alt);
483 dev->video_mode.max_pkt_size =
484 dev->video_mode.alt_max_pkt_size[dev->video_mode.alt];
485 cx231xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
486 dev->video_mode.alt,
487 dev->video_mode.max_pkt_size);
488 cx231xx_info
489 (" setting alt %d with wMaxPktSize=%u , Interface = %d\n",
490 dev->video_mode.alt, dev->video_mode.max_pkt_size,
491 usb_interface_index);
492 errCode =
493 usb_set_interface(dev->udev, usb_interface_index,
494 dev->video_mode.alt);
495 if (errCode < 0) {
496 cx231xx_errdev
497 ("cannot change alt number to %d (error=%i)\n",
498 dev->video_mode.alt, errCode);
499 return errCode;
500 }
501 }
502 return 0;
503}
504
505int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt)
506{
507 int status = 0;
508 u32 usb_interface_index = 0;
509 u32 max_pkt_size = 0;
510
511 switch (index) {
512 case INDEX_TS1:
513 usb_interface_index =
514 dev->current_pcb_config.hs_config_info[0].interface_info.
515 ts1_index + 1;
516 dev->video_mode.alt = alt;
517 if (dev->ts1_mode.alt_max_pkt_size != NULL)
518 max_pkt_size = dev->ts1_mode.max_pkt_size =
519 dev->ts1_mode.alt_max_pkt_size[dev->ts1_mode.alt];
520 break;
521 case INDEX_TS2:
522 usb_interface_index =
523 dev->current_pcb_config.hs_config_info[0].interface_info.
524 ts2_index + 1;
525 break;
526 case INDEX_AUDIO:
527 usb_interface_index =
528 dev->current_pcb_config.hs_config_info[0].interface_info.
529 audio_index + 1;
530 dev->adev.alt = alt;
531 if (dev->adev.alt_max_pkt_size != NULL)
532 max_pkt_size = dev->adev.max_pkt_size =
533 dev->adev.alt_max_pkt_size[dev->adev.alt];
534 break;
535 case INDEX_VIDEO:
536 usb_interface_index =
537 dev->current_pcb_config.hs_config_info[0].interface_info.
538 video_index + 1;
539 dev->video_mode.alt = alt;
540 if (dev->video_mode.alt_max_pkt_size != NULL)
541 max_pkt_size = dev->video_mode.max_pkt_size =
542 dev->video_mode.alt_max_pkt_size[dev->video_mode.
543 alt];
544 break;
545 case INDEX_VANC:
546 usb_interface_index =
547 dev->current_pcb_config.hs_config_info[0].interface_info.
548 vanc_index + 1;
549 dev->vbi_mode.alt = alt;
550 if (dev->vbi_mode.alt_max_pkt_size != NULL)
551 max_pkt_size = dev->vbi_mode.max_pkt_size =
552 dev->vbi_mode.alt_max_pkt_size[dev->vbi_mode.alt];
553 break;
554 case INDEX_HANC:
555 usb_interface_index =
556 dev->current_pcb_config.hs_config_info[0].interface_info.
557 hanc_index + 1;
558 dev->sliced_cc_mode.alt = alt;
559 if (dev->sliced_cc_mode.alt_max_pkt_size != NULL)
560 max_pkt_size = dev->sliced_cc_mode.max_pkt_size =
561 dev->sliced_cc_mode.alt_max_pkt_size[dev->
562 sliced_cc_mode.
563 alt];
564 break;
565 default:
566 break;
567 }
568
569 if (alt > 0 && max_pkt_size == 0) {
570 cx231xx_errdev
571 ("can't change interface %d alt no. to %d: Max. Pkt size = 0\n",
572 usb_interface_index, alt);
573 return -1;
574 }
575
576 cx231xx_info
577 (" setting alternate %d with wMaxPacketSize=%u , Interface = %d\n",
578 alt, max_pkt_size, usb_interface_index);
579
580 if (usb_interface_index > 0) {
581 status = usb_set_interface(dev->udev, usb_interface_index, alt);
582 if (status < 0) {
583 cx231xx_errdev
584 ("can't change interface %d alt no. to %d (err=%i)\n",
585 usb_interface_index, alt, status);
586 return status;
587 }
588 }
589
590 return status;
591}
592EXPORT_SYMBOL_GPL(cx231xx_set_alt_setting);
593
594int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio)
595{
596 int rc = 0;
597
598 if (!gpio)
599 return rc;
600
601 /* Send GPIO reset sequences specified at board entry */
602 while (gpio->sleep >= 0) {
603 rc = cx231xx_set_gpio_value(dev, gpio->bit, gpio->val);
604 if (rc < 0)
605 return rc;
606
607 if (gpio->sleep > 0)
608 msleep(gpio->sleep);
609
610 gpio++;
611 }
612 return rc;
613}
614
615int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode)
616{
617 if (dev->mode == set_mode)
618 return 0;
619
620 if (set_mode == CX231XX_SUSPEND) {
621 /* Set the chip in power saving mode */
622 dev->mode = set_mode;
623 }
624
625 /* Resource is locked */
626 if (dev->mode != CX231XX_SUSPEND)
627 return -EINVAL;
628
629 dev->mode = set_mode;
630
631 if (dev->mode == CX231XX_DIGITAL_MODE)
632 ;/* Set Digital power mode */
633 else
634 ;/* Set Analog Power mode */
635
636 return 0;
637}
638EXPORT_SYMBOL_GPL(cx231xx_set_mode);
639
640/*****************************************************************
641* URB Streaming functions *
642******************************************************************/
643
644/*
645 * IRQ callback, called by URB callback
646 */
647static void cx231xx_irq_callback(struct urb *urb)
648{
649 struct cx231xx_dmaqueue *dma_q = urb->context;
650 struct cx231xx_video_mode *vmode =
651 container_of(dma_q, struct cx231xx_video_mode, vidq);
652 struct cx231xx *dev = container_of(vmode, struct cx231xx, video_mode);
653 int rc, i;
654
655 switch (urb->status) {
656 case 0: /* success */
657 case -ETIMEDOUT: /* NAK */
658 break;
659 case -ECONNRESET: /* kill */
660 case -ENOENT:
661 case -ESHUTDOWN:
662 return;
663 default: /* error */
664 cx231xx_isocdbg("urb completition error %d.\n", urb->status);
665 break;
666 }
667
668 /* Copy data from URB */
669 spin_lock(&dev->video_mode.slock);
670 rc = dev->video_mode.isoc_ctl.isoc_copy(dev, urb);
671 spin_unlock(&dev->video_mode.slock);
672
673 /* Reset urb buffers */
674 for (i = 0; i < urb->number_of_packets; i++) {
675 urb->iso_frame_desc[i].status = 0;
676 urb->iso_frame_desc[i].actual_length = 0;
677 }
678 urb->status = 0;
679
680 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
681 if (urb->status) {
682 cx231xx_isocdbg("urb resubmit failed (error=%i)\n",
683 urb->status);
684 }
685}
686
687/*
688 * Stop and Deallocate URBs
689 */
690void cx231xx_uninit_isoc(struct cx231xx *dev)
691{
692 struct urb *urb;
693 int i;
694
695 cx231xx_isocdbg("cx231xx: called cx231xx_uninit_isoc\n");
696
697 dev->video_mode.isoc_ctl.nfields = -1;
698 for (i = 0; i < dev->video_mode.isoc_ctl.num_bufs; i++) {
699 urb = dev->video_mode.isoc_ctl.urb[i];
700 if (urb) {
701 if (!irqs_disabled())
702 usb_kill_urb(urb);
703 else
704 usb_unlink_urb(urb);
705
706 if (dev->video_mode.isoc_ctl.transfer_buffer[i]) {
707 usb_buffer_free(dev->udev,
708 urb->transfer_buffer_length,
709 dev->video_mode.isoc_ctl.
710 transfer_buffer[i],
711 urb->transfer_dma);
712 }
713 usb_free_urb(urb);
714 dev->video_mode.isoc_ctl.urb[i] = NULL;
715 }
716 dev->video_mode.isoc_ctl.transfer_buffer[i] = NULL;
717 }
718
719 kfree(dev->video_mode.isoc_ctl.urb);
720 kfree(dev->video_mode.isoc_ctl.transfer_buffer);
721
722 dev->video_mode.isoc_ctl.urb = NULL;
723 dev->video_mode.isoc_ctl.transfer_buffer = NULL;
724 dev->video_mode.isoc_ctl.num_bufs = 0;
725
726 cx231xx_capture_start(dev, 0, Raw_Video);
727}
728EXPORT_SYMBOL_GPL(cx231xx_uninit_isoc);
729
730/*
731 * Allocate URBs and start IRQ
732 */
733int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
734 int num_bufs, int max_pkt_size,
735 int (*isoc_copy) (struct cx231xx *dev, struct urb *urb))
736{
737 struct cx231xx_dmaqueue *dma_q = &dev->video_mode.vidq;
738 int i;
739 int sb_size, pipe;
740 struct urb *urb;
741 int j, k;
742 int rc;
743
744 cx231xx_isocdbg("cx231xx: called cx231xx_prepare_isoc\n");
745
746 dev->video_input = dev->video_input > 2 ? 2 : dev->video_input;
747
748 cx231xx_info("Setting Video mux to %d\n", dev->video_input);
749 video_mux(dev, dev->video_input);
750
751 /* De-allocates all pending stuff */
752 cx231xx_uninit_isoc(dev);
753
754 dev->video_mode.isoc_ctl.isoc_copy = isoc_copy;
755 dev->video_mode.isoc_ctl.num_bufs = num_bufs;
756 dma_q->pos = 0;
757 dma_q->is_partial_line = 0;
758 dma_q->last_sav = 0;
759 dma_q->current_field = -1;
760 dma_q->field1_done = 0;
761 dma_q->lines_per_field = dev->height / 2;
762 dma_q->bytes_left_in_line = dev->width << 1;
763 dma_q->lines_completed = 0;
764 for (i = 0; i < 8; i++)
765 dma_q->partial_buf[i] = 0;
766
767 dev->video_mode.isoc_ctl.urb =
768 kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
769 if (!dev->video_mode.isoc_ctl.urb) {
770 cx231xx_errdev("cannot alloc memory for usb buffers\n");
771 return -ENOMEM;
772 }
773
774 dev->video_mode.isoc_ctl.transfer_buffer =
775 kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
776 if (!dev->video_mode.isoc_ctl.transfer_buffer) {
777 cx231xx_errdev("cannot allocate memory for usbtransfer\n");
778 kfree(dev->video_mode.isoc_ctl.urb);
779 return -ENOMEM;
780 }
781
782 dev->video_mode.isoc_ctl.max_pkt_size = max_pkt_size;
783 dev->video_mode.isoc_ctl.buf = NULL;
784
785 sb_size = max_packets * dev->video_mode.isoc_ctl.max_pkt_size;
786
787 /* allocate urbs and transfer buffers */
788 for (i = 0; i < dev->video_mode.isoc_ctl.num_bufs; i++) {
789 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
790 if (!urb) {
791 cx231xx_err("cannot alloc isoc_ctl.urb %i\n", i);
792 cx231xx_uninit_isoc(dev);
793 return -ENOMEM;
794 }
795 dev->video_mode.isoc_ctl.urb[i] = urb;
796
797 dev->video_mode.isoc_ctl.transfer_buffer[i] =
798 usb_buffer_alloc(dev->udev, sb_size, GFP_KERNEL,
799 &urb->transfer_dma);
800 if (!dev->video_mode.isoc_ctl.transfer_buffer[i]) {
801 cx231xx_err("unable to allocate %i bytes for transfer"
802 " buffer %i%s\n",
803 sb_size, i,
804 in_interrupt() ? " while in int" : "");
805 cx231xx_uninit_isoc(dev);
806 return -ENOMEM;
807 }
808 memset(dev->video_mode.isoc_ctl.transfer_buffer[i], 0, sb_size);
809
810 pipe =
811 usb_rcvisocpipe(dev->udev, dev->video_mode.end_point_addr);
812
813 usb_fill_int_urb(urb, dev->udev, pipe,
814 dev->video_mode.isoc_ctl.transfer_buffer[i],
815 sb_size, cx231xx_irq_callback, dma_q, 1);
816
817 urb->number_of_packets = max_packets;
818 urb->transfer_flags = URB_ISO_ASAP;
819
820 k = 0;
821 for (j = 0; j < max_packets; j++) {
822 urb->iso_frame_desc[j].offset = k;
823 urb->iso_frame_desc[j].length =
824 dev->video_mode.isoc_ctl.max_pkt_size;
825 k += dev->video_mode.isoc_ctl.max_pkt_size;
826 }
827 }
828
829 init_waitqueue_head(&dma_q->wq);
830
831 /* submit urbs and enables IRQ */
832 for (i = 0; i < dev->video_mode.isoc_ctl.num_bufs; i++) {
833 rc = usb_submit_urb(dev->video_mode.isoc_ctl.urb[i],
834 GFP_ATOMIC);
835 if (rc) {
836 cx231xx_err("submit of urb %i failed (error=%i)\n", i,
837 rc);
838 cx231xx_uninit_isoc(dev);
839 return rc;
840 }
841 }
842
843 cx231xx_capture_start(dev, 1, Raw_Video);
844
845 return 0;
846}
847EXPORT_SYMBOL_GPL(cx231xx_init_isoc);
848
849/*****************************************************************
850* Device Init/UnInit functions *
851******************************************************************/
852int cx231xx_dev_init(struct cx231xx *dev)
853{
854 int errCode = 0;
855
856 /* Initialize I2C bus */
857
858 /* External Master 1 Bus */
859 dev->i2c_bus[0].nr = 0;
860 dev->i2c_bus[0].dev = dev;
861 dev->i2c_bus[0].i2c_period = I2C_SPEED_1M; /* 1MHz */
862 dev->i2c_bus[0].i2c_nostop = 0;
863 dev->i2c_bus[0].i2c_reserve = 0;
864
865 /* External Master 2 Bus */
866 dev->i2c_bus[1].nr = 1;
867 dev->i2c_bus[1].dev = dev;
868 dev->i2c_bus[1].i2c_period = I2C_SPEED_1M; /* 1MHz */
869 dev->i2c_bus[1].i2c_nostop = 0;
870 dev->i2c_bus[1].i2c_reserve = 0;
871
872 /* Internal Master 3 Bus */
873 dev->i2c_bus[2].nr = 2;
874 dev->i2c_bus[2].dev = dev;
875 dev->i2c_bus[2].i2c_period = I2C_SPEED_400K; /* 400kHz */
876 dev->i2c_bus[2].i2c_nostop = 0;
877 dev->i2c_bus[2].i2c_reserve = 0;
878
879 /* register I2C buses */
880 cx231xx_i2c_register(&dev->i2c_bus[0]);
881 cx231xx_i2c_register(&dev->i2c_bus[1]);
882 cx231xx_i2c_register(&dev->i2c_bus[2]);
883
884 /* init hardware */
885 /* Note : with out calling set power mode function,
886 afe can not be set up correctly */
887 errCode = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV);
888 if (errCode < 0) {
889 cx231xx_errdev
890 ("%s: Failed to set Power - errCode [%d]!\n",
891 __func__, errCode);
892 return errCode;
893 }
894
895 /* initialize Colibri block */
896 errCode = cx231xx_afe_init_super_block(dev, 0x23c);
897 if (errCode < 0) {
898 cx231xx_errdev
899 ("%s: cx231xx_afe init super block - errCode [%d]!\n",
900 __func__, errCode);
901 return errCode;
902 }
903 errCode = cx231xx_afe_init_channels(dev);
904 if (errCode < 0) {
905 cx231xx_errdev
906 ("%s: cx231xx_afe init channels - errCode [%d]!\n",
907 __func__, errCode);
908 return errCode;
909 }
910
911 /* Set DIF in By pass mode */
912 errCode = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
913 if (errCode < 0) {
914 cx231xx_errdev
915 ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n",
916 __func__, errCode);
917 return errCode;
918 }
919
920 /* I2S block related functions */
921 errCode = cx231xx_i2s_blk_initialize(dev);
922 if (errCode < 0) {
923 cx231xx_errdev
924 ("%s: cx231xx_i2s block initialize - errCode [%d]!\n",
925 __func__, errCode);
926 return errCode;
927 }
928
929 /* init control pins */
930 errCode = cx231xx_init_ctrl_pin_status(dev);
931 if (errCode < 0) {
932 cx231xx_errdev("%s: cx231xx_init ctrl pins - errCode [%d]!\n",
933 __func__, errCode);
934 return errCode;
935 }
936
937 /* set AGC mode to Analog */
938 errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 1);
939 if (errCode < 0) {
940 cx231xx_errdev
941 ("%s: cx231xx_AGC mode to Analog - errCode [%d]!\n",
942 __func__, errCode);
943 return errCode;
944 }
945
946 /* set all alternate settings to zero initially */
947 cx231xx_set_alt_setting(dev, INDEX_VIDEO, 0);
948 cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
949 cx231xx_set_alt_setting(dev, INDEX_HANC, 0);
950 if (dev->board.has_dvb)
951 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
952
953 /* set the I2C master port to 3 on channel 1 */
954 errCode = cx231xx_enable_i2c_for_tuner(dev, I2C_3);
955
956 return errCode;
957}
958EXPORT_SYMBOL_GPL(cx231xx_dev_init);
959
960void cx231xx_dev_uninit(struct cx231xx *dev)
961{
962 /* Un Initialize I2C bus */
963 cx231xx_i2c_unregister(&dev->i2c_bus[2]);
964 cx231xx_i2c_unregister(&dev->i2c_bus[1]);
965 cx231xx_i2c_unregister(&dev->i2c_bus[0]);
966}
967EXPORT_SYMBOL_GPL(cx231xx_dev_uninit);
968
969/*****************************************************************
970* G P I O related functions *
971******************************************************************/
972int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val,
973 u8 len, u8 request, u8 direction)
974{
975 int status = 0;
976 struct VENDOR_REQUEST_IN ven_req;
977
978 /* Set wValue */
979 ven_req.wValue = (u16) (gpio_bit >> 16 & 0xffff);
980
981 /* set request */
982 if (!request) {
983 if (direction)
984 ven_req.bRequest = VRT_GET_GPIO; /* 0x8 gpio */
985 else
986 ven_req.bRequest = VRT_SET_GPIO; /* 0x9 gpio */
987 } else {
988 if (direction)
989 ven_req.bRequest = VRT_GET_GPIE; /* 0xa gpie */
990 else
991 ven_req.bRequest = VRT_SET_GPIE; /* 0xb gpie */
992 }
993
994 /* set index value */
995 ven_req.wIndex = (u16) (gpio_bit & 0xffff);
996
997 /* set wLength value */
998 ven_req.wLength = len;
999
1000 /* set bData value */
1001 ven_req.bData = 0;
1002
1003 /* set the buffer for read / write */
1004 ven_req.pBuff = gpio_val;
1005
1006 /* set the direction */
1007 if (direction) {
1008 ven_req.direction = USB_DIR_IN;
1009 memset(ven_req.pBuff, 0x00, ven_req.wLength);
1010 } else
1011 ven_req.direction = USB_DIR_OUT;
1012
1013
1014 /* call common vendor command request */
1015 status = cx231xx_send_vendor_cmd(dev, &ven_req);
1016 if (status < 0) {
1017 cx231xx_info
1018 ("UsbInterface::sendCommand, failed with status -%d\n",
1019 status);
1020 }
1021
1022 return status;
1023}
1024EXPORT_SYMBOL_GPL(cx231xx_send_gpio_cmd);
1025
1026/*****************************************************************
1027 * C O N T R O L - Register R E A D / W R I T E functions *
1028 *****************************************************************/
1029int cx231xx_mode_register(struct cx231xx *dev, u16 address, u32 mode)
1030{
1031 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1032 u32 tmp = 0;
1033 int status = 0;
1034
1035 status =
1036 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, address, value, 4);
1037 if (status < 0)
1038 return status;
1039
1040 tmp = *((u32 *) value);
1041 tmp |= mode;
1042
1043 value[0] = (u8) tmp;
1044 value[1] = (u8) (tmp >> 8);
1045 value[2] = (u8) (tmp >> 16);
1046 value[3] = (u8) (tmp >> 24);
1047
1048 status =
1049 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, address, value, 4);
1050
1051 return status;
1052}
1053
1054/*****************************************************************
1055 * I 2 C Internal C O N T R O L functions *
1056 *****************************************************************/
1057int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr, u16 saddr,
1058 u8 saddr_len, u32 *data, u8 data_len)
1059{
1060 int status = 0;
1061 struct cx231xx_i2c_xfer_data req_data;
1062 u8 value[4] = { 0, 0, 0, 0 };
1063
1064 if (saddr_len == 0)
1065 saddr = 0;
1066 else if (saddr_len == 0)
1067 saddr &= 0xff;
1068
1069 /* prepare xfer_data struct */
1070 req_data.dev_addr = dev_addr >> 1;
1071 req_data.direction = I2C_M_RD;
1072 req_data.saddr_len = saddr_len;
1073 req_data.saddr_dat = saddr;
1074 req_data.buf_size = data_len;
1075 req_data.p_buffer = (u8 *) value;
1076
1077 /* usb send command */
1078 status = dev->cx231xx_send_usb_command(&dev->i2c_bus[0], &req_data);
1079
1080 if (status >= 0) {
1081 /* Copy the data read back to main buffer */
1082 if (data_len == 1)
1083 *data = value[0];
1084 else
1085 *data =
1086 value[0] | value[1] << 8 | value[2] << 16 | value[3]
1087 << 24;
1088 }
1089
1090 return status;
1091}
1092
1093int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr, u16 saddr,
1094 u8 saddr_len, u32 data, u8 data_len)
1095{
1096 int status = 0;
1097 u8 value[4] = { 0, 0, 0, 0 };
1098 struct cx231xx_i2c_xfer_data req_data;
1099
1100 value[0] = (u8) data;
1101 value[1] = (u8) (data >> 8);
1102 value[2] = (u8) (data >> 16);
1103 value[3] = (u8) (data >> 24);
1104
1105 if (saddr_len == 0)
1106 saddr = 0;
1107 else if (saddr_len == 0)
1108 saddr &= 0xff;
1109
1110 /* prepare xfer_data struct */
1111 req_data.dev_addr = dev_addr >> 1;
1112 req_data.direction = 0;
1113 req_data.saddr_len = saddr_len;
1114 req_data.saddr_dat = saddr;
1115 req_data.buf_size = data_len;
1116 req_data.p_buffer = value;
1117
1118 /* usb send command */
1119 status = dev->cx231xx_send_usb_command(&dev->i2c_bus[0], &req_data);
1120
1121 return status;
1122}
1123
1124int cx231xx_reg_mask_write(struct cx231xx *dev, u8 dev_addr, u8 size,
1125 u16 register_address, u8 bit_start, u8 bit_end,
1126 u32 value)
1127{
1128 int status = 0;
1129 u32 tmp;
1130 u32 mask = 0;
1131 int i;
1132
1133 if (bit_start > (size - 1) || bit_end > (size - 1))
1134 return -1;
1135
1136 if (size == 8) {
1137 status =
1138 cx231xx_read_i2c_data(dev, dev_addr, register_address, 2,
1139 &tmp, 1);
1140 } else {
1141 status =
1142 cx231xx_read_i2c_data(dev, dev_addr, register_address, 2,
1143 &tmp, 4);
1144 }
1145
1146 if (status < 0)
1147 return status;
1148
1149 mask = 1 << bit_end;
1150 for (i = bit_end; i > bit_start && i > 0; i--)
1151 mask = mask + (1 << (i - 1));
1152
1153 value <<= bit_start;
1154
1155 if (size == 8) {
1156 tmp &= ~mask;
1157 tmp |= value;
1158 tmp &= 0xff;
1159 status =
1160 cx231xx_write_i2c_data(dev, dev_addr, register_address, 2,
1161 tmp, 1);
1162 } else {
1163 tmp &= ~mask;
1164 tmp |= value;
1165 status =
1166 cx231xx_write_i2c_data(dev, dev_addr, register_address, 2,
1167 tmp, 4);
1168 }
1169
1170 return status;
1171}
1172
1173int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr,
1174 u16 saddr, u32 mask, u32 value)
1175{
1176 u32 temp;
1177 int status = 0;
1178
1179 status = cx231xx_read_i2c_data(dev, dev_addr, saddr, 2, &temp, 4);
1180
1181 if (status < 0)
1182 return status;
1183
1184 temp &= ~mask;
1185 temp |= value;
1186
1187 status = cx231xx_write_i2c_data(dev, dev_addr, saddr, 2, temp, 4);
1188
1189 return status;
1190}
1191
1192u32 cx231xx_set_field(u32 field_mask, u32 data)
1193{
1194 u32 temp;
1195
1196 for (temp = field_mask; (temp & 1) == 0; temp >>= 1)
1197 data <<= 1;
1198
1199 return data;
1200}
diff --git a/drivers/media/video/cx231xx/cx231xx-dvb.c b/drivers/media/video/cx231xx/cx231xx-dvb.c
new file mode 100644
index 000000000000..c5082a4e8ced
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-dvb.c
@@ -0,0 +1,559 @@
1/*
2 DVB device driver for cx231xx
3
4 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5 Based on em28xx driver
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/usb.h>
24
25#include "cx231xx.h"
26#include <media/v4l2-common.h>
27#include <media/videobuf-vmalloc.h>
28
29#include "xc5000.h"
30#include "dvb_dummy_fe.h"
31
32MODULE_DESCRIPTION("driver for cx231xx based DVB cards");
33MODULE_AUTHOR("Srinivasa Deevi <srinivasa.deevi@conexant.com>");
34MODULE_LICENSE("GPL");
35
36static unsigned int debug;
37module_param(debug, int, 0644);
38MODULE_PARM_DESC(debug, "enable debug messages [dvb]");
39
40DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
41
42#define dprintk(level, fmt, arg...) do { \
43if (debug >= level) \
44 printk(KERN_DEBUG "%s/2-dvb: " fmt, dev->name, ## arg); \
45} while (0)
46
47#define CX231XX_DVB_NUM_BUFS 5
48#define CX231XX_DVB_MAX_PACKETSIZE 564
49#define CX231XX_DVB_MAX_PACKETS 64
50
51struct cx231xx_dvb {
52 struct dvb_frontend *frontend;
53
54 /* feed count management */
55 struct mutex lock;
56 int nfeeds;
57
58 /* general boilerplate stuff */
59 struct dvb_adapter adapter;
60 struct dvb_demux demux;
61 struct dmxdev dmxdev;
62 struct dmx_frontend fe_hw;
63 struct dmx_frontend fe_mem;
64 struct dvb_net net;
65};
66
67static inline void print_err_status(struct cx231xx *dev, int packet, int status)
68{
69 char *errmsg = "Unknown";
70
71 switch (status) {
72 case -ENOENT:
73 errmsg = "unlinked synchronuously";
74 break;
75 case -ECONNRESET:
76 errmsg = "unlinked asynchronuously";
77 break;
78 case -ENOSR:
79 errmsg = "Buffer error (overrun)";
80 break;
81 case -EPIPE:
82 errmsg = "Stalled (device not responding)";
83 break;
84 case -EOVERFLOW:
85 errmsg = "Babble (bad cable?)";
86 break;
87 case -EPROTO:
88 errmsg = "Bit-stuff error (bad cable?)";
89 break;
90 case -EILSEQ:
91 errmsg = "CRC/Timeout (could be anything)";
92 break;
93 case -ETIME:
94 errmsg = "Device does not respond";
95 break;
96 }
97 if (packet < 0) {
98 dprintk(1, "URB status %d [%s].\n", status, errmsg);
99 } else {
100 dprintk(1, "URB packet %d, status %d [%s].\n",
101 packet, status, errmsg);
102 }
103}
104
105static inline int dvb_isoc_copy(struct cx231xx *dev, struct urb *urb)
106{
107 int i;
108
109 if (!dev)
110 return 0;
111
112 if ((dev->state & DEV_DISCONNECTED) || (dev->state & DEV_MISCONFIGURED))
113 return 0;
114
115 if (urb->status < 0) {
116 print_err_status(dev, -1, urb->status);
117 if (urb->status == -ENOENT)
118 return 0;
119 }
120
121 for (i = 0; i < urb->number_of_packets; i++) {
122 int status = urb->iso_frame_desc[i].status;
123
124 if (status < 0) {
125 print_err_status(dev, i, status);
126 if (urb->iso_frame_desc[i].status != -EPROTO)
127 continue;
128 }
129
130 dvb_dmx_swfilter(&dev->dvb->demux, urb->transfer_buffer +
131 urb->iso_frame_desc[i].offset,
132 urb->iso_frame_desc[i].actual_length);
133 }
134
135 return 0;
136}
137
138static int start_streaming(struct cx231xx_dvb *dvb)
139{
140 int rc;
141 struct cx231xx *dev = dvb->adapter.priv;
142
143 usb_set_interface(dev->udev, 0, 1);
144 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
145 if (rc < 0)
146 return rc;
147
148 return cx231xx_init_isoc(dev, CX231XX_DVB_MAX_PACKETS,
149 CX231XX_DVB_NUM_BUFS,
150 CX231XX_DVB_MAX_PACKETSIZE, dvb_isoc_copy);
151}
152
153static int stop_streaming(struct cx231xx_dvb *dvb)
154{
155 struct cx231xx *dev = dvb->adapter.priv;
156
157 cx231xx_uninit_isoc(dev);
158
159 cx231xx_set_mode(dev, CX231XX_SUSPEND);
160
161 return 0;
162}
163
164static int start_feed(struct dvb_demux_feed *feed)
165{
166 struct dvb_demux *demux = feed->demux;
167 struct cx231xx_dvb *dvb = demux->priv;
168 int rc, ret;
169
170 if (!demux->dmx.frontend)
171 return -EINVAL;
172
173 mutex_lock(&dvb->lock);
174 dvb->nfeeds++;
175 rc = dvb->nfeeds;
176
177 if (dvb->nfeeds == 1) {
178 ret = start_streaming(dvb);
179 if (ret < 0)
180 rc = ret;
181 }
182
183 mutex_unlock(&dvb->lock);
184 return rc;
185}
186
187static int stop_feed(struct dvb_demux_feed *feed)
188{
189 struct dvb_demux *demux = feed->demux;
190 struct cx231xx_dvb *dvb = demux->priv;
191 int err = 0;
192
193 mutex_lock(&dvb->lock);
194 dvb->nfeeds--;
195
196 if (0 == dvb->nfeeds)
197 err = stop_streaming(dvb);
198
199 mutex_unlock(&dvb->lock);
200 return err;
201}
202
203/* ------------------------------------------------------------------ */
204static int cx231xx_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
205{
206 struct cx231xx *dev = fe->dvb->priv;
207
208 if (acquire)
209 return cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
210 else
211 return cx231xx_set_mode(dev, CX231XX_SUSPEND);
212}
213
214/* ------------------------------------------------------------------ */
215
216static struct xc5000_config cnxt_rde250_tunerconfig = {
217 .i2c_address = 0x61,
218 .if_khz = 5380,
219};
220
221/* ------------------------------------------------------------------ */
222#if 0
223static int attach_xc5000(u8 addr, struct cx231xx *dev)
224{
225
226 struct dvb_frontend *fe;
227 struct xc5000_config cfg;
228
229 memset(&cfg, 0, sizeof(cfg));
230 cfg.i2c_adap = &dev->i2c_bus[1].i2c_adap;
231 cfg.i2c_addr = addr;
232
233 if (!dev->dvb->frontend) {
234 printk(KERN_ERR "%s/2: dvb frontend not attached. "
235 "Can't attach xc5000\n", dev->name);
236 return -EINVAL;
237 }
238
239 fe = dvb_attach(xc5000_attach, dev->dvb->frontend, &cfg);
240 if (!fe) {
241 printk(KERN_ERR "%s/2: xc5000 attach failed\n", dev->name);
242 dvb_frontend_detach(dev->dvb->frontend);
243 dev->dvb->frontend = NULL;
244 return -EINVAL;
245 }
246
247 printk(KERN_INFO "%s/2: xc5000 attached\n", dev->name);
248
249 return 0;
250}
251#endif
252
253int cx231xx_set_analog_freq(struct cx231xx *dev, u32 freq)
254{
255 int status = 0;
256
257 if ((dev->dvb != NULL) && (dev->dvb->frontend != NULL)) {
258
259 struct dvb_tuner_ops *dops = &dev->dvb->frontend->ops.tuner_ops;
260
261 if (dops->set_analog_params != NULL) {
262 struct analog_parameters params;
263
264 params.frequency = freq;
265 params.std = dev->norm;
266 params.mode = 0; /* 0- Air; 1 - cable */
267 /*params.audmode = ; */
268
269 /* Set the analog parameters to set the frequency */
270 cx231xx_info("Setting Frequency for XC5000\n");
271 dops->set_analog_params(dev->dvb->frontend, &params);
272 }
273
274 }
275
276 return status;
277}
278
279int cx231xx_reset_analog_tuner(struct cx231xx *dev)
280{
281 int status = 0;
282
283 if ((dev->dvb != NULL) && (dev->dvb->frontend != NULL)) {
284
285 struct dvb_tuner_ops *dops = &dev->dvb->frontend->ops.tuner_ops;
286
287 if (dops->init != NULL && !dev->xc_fw_load_done) {
288
289 cx231xx_info("Reloading firmware for XC5000\n");
290 status = dops->init(dev->dvb->frontend);
291 if (status == 0) {
292 dev->xc_fw_load_done = 1;
293 cx231xx_info
294 ("XC5000 firmware download completed\n");
295 } else {
296 dev->xc_fw_load_done = 0;
297 cx231xx_info
298 ("XC5000 firmware download failed !!!\n");
299 }
300 }
301
302 }
303
304 return status;
305}
306
307/* ------------------------------------------------------------------ */
308
309static int register_dvb(struct cx231xx_dvb *dvb,
310 struct module *module,
311 struct cx231xx *dev, struct device *device)
312{
313 int result;
314
315 mutex_init(&dvb->lock);
316
317 /* register adapter */
318 result = dvb_register_adapter(&dvb->adapter, dev->name, module, device,
319 adapter_nr);
320 if (result < 0) {
321 printk(KERN_WARNING
322 "%s: dvb_register_adapter failed (errno = %d)\n",
323 dev->name, result);
324 goto fail_adapter;
325 }
326
327 /* Ensure all frontends negotiate bus access */
328 dvb->frontend->ops.ts_bus_ctrl = cx231xx_dvb_bus_ctrl;
329
330 dvb->adapter.priv = dev;
331
332 /* register frontend */
333 result = dvb_register_frontend(&dvb->adapter, dvb->frontend);
334 if (result < 0) {
335 printk(KERN_WARNING
336 "%s: dvb_register_frontend failed (errno = %d)\n",
337 dev->name, result);
338 goto fail_frontend;
339 }
340
341 /* register demux stuff */
342 dvb->demux.dmx.capabilities =
343 DMX_TS_FILTERING | DMX_SECTION_FILTERING |
344 DMX_MEMORY_BASED_FILTERING;
345 dvb->demux.priv = dvb;
346 dvb->demux.filternum = 256;
347 dvb->demux.feednum = 256;
348 dvb->demux.start_feed = start_feed;
349 dvb->demux.stop_feed = stop_feed;
350
351 result = dvb_dmx_init(&dvb->demux);
352 if (result < 0) {
353 printk(KERN_WARNING "%s: dvb_dmx_init failed (errno = %d)\n",
354 dev->name, result);
355 goto fail_dmx;
356 }
357
358 dvb->dmxdev.filternum = 256;
359 dvb->dmxdev.demux = &dvb->demux.dmx;
360 dvb->dmxdev.capabilities = 0;
361 result = dvb_dmxdev_init(&dvb->dmxdev, &dvb->adapter);
362 if (result < 0) {
363 printk(KERN_WARNING "%s: dvb_dmxdev_init failed (errno = %d)\n",
364 dev->name, result);
365 goto fail_dmxdev;
366 }
367
368 dvb->fe_hw.source = DMX_FRONTEND_0;
369 result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_hw);
370 if (result < 0) {
371 printk(KERN_WARNING
372 "%s: add_frontend failed (DMX_FRONTEND_0, errno = %d)\n",
373 dev->name, result);
374 goto fail_fe_hw;
375 }
376
377 dvb->fe_mem.source = DMX_MEMORY_FE;
378 result = dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->fe_mem);
379 if (result < 0) {
380 printk(KERN_WARNING
381 "%s: add_frontend failed (DMX_MEMORY_FE, errno = %d)\n",
382 dev->name, result);
383 goto fail_fe_mem;
384 }
385
386 result = dvb->demux.dmx.connect_frontend(&dvb->demux.dmx, &dvb->fe_hw);
387 if (result < 0) {
388 printk(KERN_WARNING
389 "%s: connect_frontend failed (errno = %d)\n", dev->name,
390 result);
391 goto fail_fe_conn;
392 }
393
394 /* register network adapter */
395 dvb_net_init(&dvb->adapter, &dvb->net, &dvb->demux.dmx);
396 return 0;
397
398fail_fe_conn:
399 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
400fail_fe_mem:
401 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
402fail_fe_hw:
403 dvb_dmxdev_release(&dvb->dmxdev);
404fail_dmxdev:
405 dvb_dmx_release(&dvb->demux);
406fail_dmx:
407 dvb_unregister_frontend(dvb->frontend);
408fail_frontend:
409 dvb_frontend_detach(dvb->frontend);
410 dvb_unregister_adapter(&dvb->adapter);
411fail_adapter:
412 return result;
413}
414
415static void unregister_dvb(struct cx231xx_dvb *dvb)
416{
417 dvb_net_release(&dvb->net);
418 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_mem);
419 dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
420 dvb_dmxdev_release(&dvb->dmxdev);
421 dvb_dmx_release(&dvb->demux);
422 dvb_unregister_frontend(dvb->frontend);
423 dvb_frontend_detach(dvb->frontend);
424 dvb_unregister_adapter(&dvb->adapter);
425}
426
427static int dvb_init(struct cx231xx *dev)
428{
429 int result = 0;
430 struct cx231xx_dvb *dvb;
431
432 if (!dev->board.has_dvb) {
433 /* This device does not support the extension */
434 return 0;
435 }
436
437 dvb = kzalloc(sizeof(struct cx231xx_dvb), GFP_KERNEL);
438
439 if (dvb == NULL) {
440 printk(KERN_INFO "cx231xx_dvb: memory allocation failed\n");
441 return -ENOMEM;
442 }
443 dev->dvb = dvb;
444 dev->cx231xx_set_analog_freq = cx231xx_set_analog_freq;
445 dev->cx231xx_reset_analog_tuner = cx231xx_reset_analog_tuner;
446
447 cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
448 /* init frontend */
449 switch (dev->model) {
450 case CX231XX_BOARD_CNXT_RDE_250:
451
452 /* dev->dvb->frontend = dvb_attach(s5h1411_attach,
453 &dvico_s5h1411_config,
454 &dev->i2c_bus[1].i2c_adap); */
455 dev->dvb->frontend = dvb_attach(dvb_dummy_fe_ofdm_attach);
456
457 if (dev->dvb->frontend == NULL) {
458 printk(DRIVER_NAME
459 ": Failed to attach dummy front end\n");
460 result = -EINVAL;
461 goto out_free;
462 }
463
464 /* define general-purpose callback pointer */
465 dvb->frontend->callback = cx231xx_tuner_callback;
466
467 if (dvb_attach(xc5000_attach, dev->dvb->frontend,
468 &dev->i2c_bus[1].i2c_adap,
469 &cnxt_rde250_tunerconfig) < 0) {
470 result = -EINVAL;
471 goto out_free;
472 }
473
474 break;
475 case CX231XX_BOARD_CNXT_RDU_250:
476
477 dev->dvb->frontend = dvb_attach(dvb_dummy_fe_ofdm_attach);
478
479 if (dev->dvb->frontend == NULL) {
480 printk(DRIVER_NAME
481 ": Failed to attach dummy front end\n");
482 result = -EINVAL;
483 goto out_free;
484 }
485
486 /* define general-purpose callback pointer */
487 dvb->frontend->callback = cx231xx_tuner_callback;
488
489 if (dvb_attach(xc5000_attach, dev->dvb->frontend,
490 &dev->i2c_bus[1].i2c_adap,
491 &cnxt_rde250_tunerconfig) < 0) {
492 result = -EINVAL;
493 goto out_free;
494 }
495 break;
496
497 default:
498 printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card"
499 " isn't supported yet\n", dev->name);
500 break;
501 }
502 if (NULL == dvb->frontend) {
503 printk(KERN_ERR
504 "%s/2: frontend initialization failed\n", dev->name);
505 result = -EINVAL;
506 goto out_free;
507 }
508
509 /* register everything */
510 result = register_dvb(dvb, THIS_MODULE, dev, &dev->udev->dev);
511
512 if (result < 0)
513 goto out_free;
514
515 cx231xx_set_mode(dev, CX231XX_SUSPEND);
516 printk(KERN_INFO "Successfully loaded cx231xx-dvb\n");
517 return 0;
518
519out_free:
520 cx231xx_set_mode(dev, CX231XX_SUSPEND);
521 kfree(dvb);
522 dev->dvb = NULL;
523 return result;
524}
525
526static int dvb_fini(struct cx231xx *dev)
527{
528 if (!dev->board.has_dvb) {
529 /* This device does not support the extension */
530 return 0;
531 }
532
533 if (dev->dvb) {
534 unregister_dvb(dev->dvb);
535 dev->dvb = NULL;
536 }
537
538 return 0;
539}
540
541static struct cx231xx_ops dvb_ops = {
542 .id = CX231XX_DVB,
543 .name = "Cx231xx dvb Extension",
544 .init = dvb_init,
545 .fini = dvb_fini,
546};
547
548static int __init cx231xx_dvb_register(void)
549{
550 return cx231xx_register_extension(&dvb_ops);
551}
552
553static void __exit cx231xx_dvb_unregister(void)
554{
555 cx231xx_unregister_extension(&dvb_ops);
556}
557
558module_init(cx231xx_dvb_register);
559module_exit(cx231xx_dvb_unregister);
diff --git a/drivers/media/video/cx231xx/cx231xx-i2c.c b/drivers/media/video/cx231xx/cx231xx-i2c.c
new file mode 100644
index 000000000000..b4a03d813e00
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-i2c.c
@@ -0,0 +1,555 @@
1/*
2 cx231xx-i2c.c - driver for Conexant Cx23100/101/102 USB video capture devices
3
4 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5 Based on em28xx driver
6 Based on Cx23885 driver
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/usb.h>
26#include <linux/i2c.h>
27#include <media/v4l2-common.h>
28#include <media/tuner.h>
29
30#include "cx231xx.h"
31
32/* ----------------------------------------------------------- */
33
34static unsigned int i2c_scan;
35module_param(i2c_scan, int, 0444);
36MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
37
38static unsigned int i2c_debug;
39module_param(i2c_debug, int, 0644);
40MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
41
42#define dprintk1(lvl, fmt, args...) \
43do { \
44 if (i2c_debug >= lvl) { \
45 printk(fmt, ##args); \
46 } \
47} while (0)
48
49#define dprintk2(lvl, fmt, args...) \
50do { \
51 if (i2c_debug >= lvl) { \
52 printk(KERN_DEBUG "%s at %s: " fmt, \
53 dev->name, __func__ , ##args); \
54 } \
55} while (0)
56
57/*
58 * cx231xx_i2c_send_bytes()
59 */
60int cx231xx_i2c_send_bytes(struct i2c_adapter *i2c_adap,
61 const struct i2c_msg *msg)
62{
63 struct cx231xx_i2c *bus = i2c_adap->algo_data;
64 struct cx231xx *dev = bus->dev;
65 struct cx231xx_i2c_xfer_data req_data;
66 int status = 0;
67 u16 size = 0;
68 u8 loop = 0;
69 u8 saddr_len = 1;
70 u8 *buf_ptr = NULL;
71 u16 saddr = 0;
72 u8 need_gpio = 0;
73
74 if ((bus->nr == 1) && (msg->addr == 0x61)
75 && (dev->tuner_type == TUNER_XC5000)) {
76
77 size = msg->len;
78
79 if (size == 2) { /* register write sub addr */
80 /* Just writing sub address will cause problem
81 * to XC5000. So ignore the request */
82 return 0;
83 } else if (size == 4) { /* register write with sub addr */
84 if (msg->len >= 2)
85 saddr = msg->buf[0] << 8 | msg->buf[1];
86 else if (msg->len == 1)
87 saddr = msg->buf[0];
88
89 switch (saddr) {
90 case 0x0000: /* start tuner calibration mode */
91 need_gpio = 1;
92 /* FW Loading is done */
93 dev->xc_fw_load_done = 1;
94 break;
95 case 0x000D: /* Set signal source */
96 case 0x0001: /* Set TV standard - Video */
97 case 0x0002: /* Set TV standard - Audio */
98 case 0x0003: /* Set RF Frequency */
99 need_gpio = 1;
100 break;
101 default:
102 if (dev->xc_fw_load_done)
103 need_gpio = 1;
104 break;
105 }
106
107 if (need_gpio) {
108 dprintk1(1,
109 "GPIO WRITE: addr 0x%x, len %d, saddr 0x%x\n",
110 msg->addr, msg->len, saddr);
111
112 return dev->cx231xx_gpio_i2c_write(dev,
113 msg->addr,
114 msg->buf,
115 msg->len);
116 }
117 }
118
119 /* special case for Xc5000 tuner case */
120 saddr_len = 1;
121
122 /* adjust the length to correct length */
123 size -= saddr_len;
124 buf_ptr = (u8 *) (msg->buf + 1);
125
126 do {
127 /* prepare xfer_data struct */
128 req_data.dev_addr = msg->addr;
129 req_data.direction = msg->flags;
130 req_data.saddr_len = saddr_len;
131 req_data.saddr_dat = msg->buf[0];
132 req_data.buf_size = size > 16 ? 16 : size;
133 req_data.p_buffer = (u8 *) (buf_ptr + loop * 16);
134
135 bus->i2c_nostop = (size > 16) ? 1 : 0;
136 bus->i2c_reserve = (loop == 0) ? 0 : 1;
137
138 /* usb send command */
139 status = dev->cx231xx_send_usb_command(bus, &req_data);
140 loop++;
141
142 if (size >= 16)
143 size -= 16;
144 else
145 size = 0;
146
147 } while (size > 0);
148
149 bus->i2c_nostop = 0;
150 bus->i2c_reserve = 0;
151
152 } else { /* regular case */
153
154 /* prepare xfer_data struct */
155 req_data.dev_addr = msg->addr;
156 req_data.direction = msg->flags;
157 req_data.saddr_len = 0;
158 req_data.saddr_dat = 0;
159 req_data.buf_size = msg->len;
160 req_data.p_buffer = msg->buf;
161
162 /* usb send command */
163 status = dev->cx231xx_send_usb_command(bus, &req_data);
164 }
165
166 return status < 0 ? status : 0;
167}
168
169/*
170 * cx231xx_i2c_recv_bytes()
171 * read a byte from the i2c device
172 */
173static int cx231xx_i2c_recv_bytes(struct i2c_adapter *i2c_adap,
174 const struct i2c_msg *msg)
175{
176 struct cx231xx_i2c *bus = i2c_adap->algo_data;
177 struct cx231xx *dev = bus->dev;
178 struct cx231xx_i2c_xfer_data req_data;
179 int status = 0;
180 u16 saddr = 0;
181 u8 need_gpio = 0;
182
183 if ((bus->nr == 1) && (msg->addr == 0x61)
184 && dev->tuner_type == TUNER_XC5000) {
185
186 if (msg->len == 2)
187 saddr = msg->buf[0] << 8 | msg->buf[1];
188 else if (msg->len == 1)
189 saddr = msg->buf[0];
190
191 if (dev->xc_fw_load_done) {
192
193 switch (saddr) {
194 case 0x0009: /* BUSY check */
195 dprintk1(1,
196 "GPIO R E A D: Special case BUSY check \n");
197 /*Try read BUSY register, just set it to zero*/
198 msg->buf[0] = 0;
199 if (msg->len == 2)
200 msg->buf[1] = 0;
201 return 0;
202 case 0x0004: /* read Lock status */
203 need_gpio = 1;
204 break;
205
206 }
207
208 if (need_gpio) {
209 /* this is a special case to handle Xceive tuner
210 clock stretch issue with gpio based I2C */
211
212 dprintk1(1,
213 "GPIO R E A D: addr 0x%x, len %d, saddr 0x%x\n",
214 msg->addr, msg->len,
215 msg->buf[0] << 8 | msg->buf[1]);
216
217 status =
218 dev->cx231xx_gpio_i2c_write(dev, msg->addr,
219 msg->buf,
220 msg->len);
221 status =
222 dev->cx231xx_gpio_i2c_read(dev, msg->addr,
223 msg->buf,
224 msg->len);
225 return status;
226 }
227 }
228
229 /* prepare xfer_data struct */
230 req_data.dev_addr = msg->addr;
231 req_data.direction = msg->flags;
232 req_data.saddr_len = msg->len;
233 req_data.saddr_dat = msg->buf[0] << 8 | msg->buf[1];
234 req_data.buf_size = msg->len;
235 req_data.p_buffer = msg->buf;
236
237 /* usb send command */
238 status = dev->cx231xx_send_usb_command(bus, &req_data);
239
240 } else {
241
242 /* prepare xfer_data struct */
243 req_data.dev_addr = msg->addr;
244 req_data.direction = msg->flags;
245 req_data.saddr_len = 0;
246 req_data.saddr_dat = 0;
247 req_data.buf_size = msg->len;
248 req_data.p_buffer = msg->buf;
249
250 /* usb send command */
251 status = dev->cx231xx_send_usb_command(bus, &req_data);
252 }
253
254 return status < 0 ? status : 0;
255}
256
257/*
258 * cx231xx_i2c_recv_bytes_with_saddr()
259 * read a byte from the i2c device
260 */
261static int cx231xx_i2c_recv_bytes_with_saddr(struct i2c_adapter *i2c_adap,
262 const struct i2c_msg *msg1,
263 const struct i2c_msg *msg2)
264{
265 struct cx231xx_i2c *bus = i2c_adap->algo_data;
266 struct cx231xx *dev = bus->dev;
267 struct cx231xx_i2c_xfer_data req_data;
268 int status = 0;
269 u16 saddr = 0;
270 u8 need_gpio = 0;
271
272 if (msg1->len == 2)
273 saddr = msg1->buf[0] << 8 | msg1->buf[1];
274 else if (msg1->len == 1)
275 saddr = msg1->buf[0];
276
277 if ((bus->nr == 1) && (msg2->addr == 0x61)
278 && dev->tuner_type == TUNER_XC5000) {
279
280 if ((msg2->len < 16)) {
281
282 dprintk1(1,
283 "i2c_read: addr 0x%x, len %d, saddr 0x%x, len %d\n",
284 msg2->addr, msg2->len, saddr, msg1->len);
285
286 switch (saddr) {
287 case 0x0008: /* read FW load status */
288 need_gpio = 1;
289 break;
290 case 0x0004: /* read Lock status */
291 need_gpio = 1;
292 break;
293 }
294
295 if (need_gpio) {
296 status =
297 dev->cx231xx_gpio_i2c_write(dev, msg1->addr,
298 msg1->buf,
299 msg1->len);
300 status =
301 dev->cx231xx_gpio_i2c_read(dev, msg2->addr,
302 msg2->buf,
303 msg2->len);
304 return status;
305 }
306 }
307 }
308
309 /* prepare xfer_data struct */
310 req_data.dev_addr = msg2->addr;
311 req_data.direction = msg2->flags;
312 req_data.saddr_len = msg1->len;
313 req_data.saddr_dat = saddr;
314 req_data.buf_size = msg2->len;
315 req_data.p_buffer = msg2->buf;
316
317 /* usb send command */
318 status = dev->cx231xx_send_usb_command(bus, &req_data);
319
320 return status < 0 ? status : 0;
321}
322
323/*
324 * cx231xx_i2c_check_for_device()
325 * check if there is a i2c_device at the supplied address
326 */
327static int cx231xx_i2c_check_for_device(struct i2c_adapter *i2c_adap,
328 const struct i2c_msg *msg)
329{
330 struct cx231xx_i2c *bus = i2c_adap->algo_data;
331 struct cx231xx *dev = bus->dev;
332 struct cx231xx_i2c_xfer_data req_data;
333 int status = 0;
334
335 /* prepare xfer_data struct */
336 req_data.dev_addr = msg->addr;
337 req_data.direction = msg->flags;
338 req_data.saddr_len = 0;
339 req_data.saddr_dat = 0;
340 req_data.buf_size = 0;
341 req_data.p_buffer = NULL;
342
343 /* usb send command */
344 status = dev->cx231xx_send_usb_command(bus, &req_data);
345
346 return status < 0 ? status : 0;
347}
348
349/*
350 * cx231xx_i2c_xfer()
351 * the main i2c transfer function
352 */
353static int cx231xx_i2c_xfer(struct i2c_adapter *i2c_adap,
354 struct i2c_msg msgs[], int num)
355{
356 struct cx231xx_i2c *bus = i2c_adap->algo_data;
357 struct cx231xx *dev = bus->dev;
358 int addr, rc, i, byte;
359
360 if (num <= 0)
361 return 0;
362
363 for (i = 0; i < num; i++) {
364
365 addr = msgs[i].addr >> 1;
366
367 dprintk2(2, "%s %s addr=%x len=%d:",
368 (msgs[i].flags & I2C_M_RD) ? "read" : "write",
369 i == num - 1 ? "stop" : "nonstop", addr, msgs[i].len);
370 if (!msgs[i].len) {
371 /* no len: check only for device presence */
372 rc = cx231xx_i2c_check_for_device(i2c_adap, &msgs[i]);
373 if (rc < 0) {
374 dprintk2(2, " no device\n");
375 return rc;
376 }
377
378 } else if (msgs[i].flags & I2C_M_RD) {
379 /* read bytes */
380 rc = cx231xx_i2c_recv_bytes(i2c_adap, &msgs[i]);
381 if (i2c_debug >= 2) {
382 for (byte = 0; byte < msgs[i].len; byte++)
383 printk(" %02x", msgs[i].buf[byte]);
384 }
385 } else if (i + 1 < num && (msgs[i + 1].flags & I2C_M_RD) &&
386 msgs[i].addr == msgs[i + 1].addr
387 && (msgs[i].len <= 2) && (bus->nr < 2)) {
388 /* read bytes */
389 rc = cx231xx_i2c_recv_bytes_with_saddr(i2c_adap,
390 &msgs[i],
391 &msgs[i + 1]);
392 if (i2c_debug >= 2) {
393 for (byte = 0; byte < msgs[i].len; byte++)
394 printk(" %02x", msgs[i].buf[byte]);
395 }
396 i++;
397 } else {
398 /* write bytes */
399 if (i2c_debug >= 2) {
400 for (byte = 0; byte < msgs[i].len; byte++)
401 printk(" %02x", msgs[i].buf[byte]);
402 }
403 rc = cx231xx_i2c_send_bytes(i2c_adap, &msgs[i]);
404 }
405 if (rc < 0)
406 goto err;
407 if (i2c_debug >= 2)
408 printk("\n");
409 }
410
411 return num;
412err:
413 dprintk2(2, " ERROR: %i\n", rc);
414 return rc;
415}
416
417/* ----------------------------------------------------------- */
418
419/*
420 * functionality()
421 */
422static u32 functionality(struct i2c_adapter *adap)
423{
424 return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
425}
426
427/*
428 * attach_inform()
429 * gets called when a device attaches to the i2c bus
430 * does some basic configuration
431 */
432static int attach_inform(struct i2c_client *client)
433{
434 struct cx231xx_i2c *bus = i2c_get_adapdata(client->adapter);
435 struct cx231xx *dev = bus->dev;
436
437 switch (client->addr << 1) {
438 case 0x8e:
439 {
440 struct IR_i2c *ir = i2c_get_clientdata(client);
441 dprintk1(1, "attach_inform: IR detected (%s).\n",
442 ir->phys);
443 cx231xx_set_ir(dev, ir);
444 break;
445 }
446 break;
447
448 default:
449 break;
450 }
451
452 return 0;
453}
454
455static struct i2c_algorithm cx231xx_algo = {
456 .master_xfer = cx231xx_i2c_xfer,
457 .functionality = functionality,
458};
459
460static struct i2c_adapter cx231xx_adap_template = {
461 .owner = THIS_MODULE,
462 .name = "cx231xx",
463 .id = I2C_HW_B_CX231XX,
464 .algo = &cx231xx_algo,
465 .client_register = attach_inform,
466};
467
468static struct i2c_client cx231xx_client_template = {
469 .name = "cx231xx internal",
470};
471
472/* ----------------------------------------------------------- */
473
474/*
475 * i2c_devs
476 * incomplete list of known devices
477 */
478static char *i2c_devs[128] = {
479 [0x60 >> 1] = "colibri",
480 [0x88 >> 1] = "hammerhead",
481 [0x8e >> 1] = "CIR",
482 [0x32 >> 1] = "GeminiIII",
483 [0x02 >> 1] = "Aquarius",
484 [0xa0 >> 1] = "eeprom",
485 [0xc0 >> 1] = "tuner/XC3028",
486 [0xc2 >> 1] = "tuner/XC5000",
487};
488
489/*
490 * cx231xx_do_i2c_scan()
491 * check i2c address range for devices
492 */
493void cx231xx_do_i2c_scan(struct cx231xx *dev, struct i2c_client *c)
494{
495 unsigned char buf;
496 int i, rc;
497
498 cx231xx_info(": Checking for I2C devices ..\n");
499 for (i = 0; i < 128; i++) {
500 c->addr = i;
501 rc = i2c_master_recv(c, &buf, 0);
502 if (rc < 0)
503 continue;
504 cx231xx_info("%s: i2c scan: found device @ 0x%x [%s]\n",
505 dev->name, i << 1,
506 i2c_devs[i] ? i2c_devs[i] : "???");
507 }
508 cx231xx_info(": Completed Checking for I2C devices.\n");
509}
510
511/*
512 * cx231xx_i2c_register()
513 * register i2c bus
514 */
515int cx231xx_i2c_register(struct cx231xx_i2c *bus)
516{
517 struct cx231xx *dev = bus->dev;
518
519 BUG_ON(!dev->cx231xx_send_usb_command);
520
521 memcpy(&bus->i2c_adap, &cx231xx_adap_template, sizeof(bus->i2c_adap));
522 memcpy(&bus->i2c_algo, &cx231xx_algo, sizeof(bus->i2c_algo));
523 memcpy(&bus->i2c_client, &cx231xx_client_template,
524 sizeof(bus->i2c_client));
525
526 bus->i2c_adap.dev.parent = &dev->udev->dev;
527
528 strlcpy(bus->i2c_adap.name, bus->dev->name, sizeof(bus->i2c_adap.name));
529
530 bus->i2c_algo.data = bus;
531 bus->i2c_adap.algo_data = bus;
532 i2c_set_adapdata(&bus->i2c_adap, &dev->v4l2_dev);
533 i2c_add_adapter(&bus->i2c_adap);
534
535 bus->i2c_client.adapter = &bus->i2c_adap;
536
537 if (0 == bus->i2c_rc) {
538 if (i2c_scan)
539 cx231xx_do_i2c_scan(dev, &bus->i2c_client);
540 } else
541 cx231xx_warn("%s: i2c bus %d register FAILED\n",
542 dev->name, bus->nr);
543
544 return bus->i2c_rc;
545}
546
547/*
548 * cx231xx_i2c_unregister()
549 * unregister i2c_bus
550 */
551int cx231xx_i2c_unregister(struct cx231xx_i2c *bus)
552{
553 i2c_del_adapter(&bus->i2c_adap);
554 return 0;
555}
diff --git a/drivers/media/video/cx231xx/cx231xx-input.c b/drivers/media/video/cx231xx/cx231xx-input.c
new file mode 100644
index 000000000000..97e304c3c799
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-input.c
@@ -0,0 +1,246 @@
1/*
2 handle cx231xx IR remotes via linux kernel input layer.
3
4 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5 Based on em28xx driver
6
7 < This is a place holder for IR now.>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/interrupt.h>
28#include <linux/input.h>
29#include <linux/usb.h>
30
31#include "cx231xx.h"
32
33static unsigned int ir_debug;
34module_param(ir_debug, int, 0644);
35MODULE_PARM_DESC(ir_debug, "enable debug messages [IR]");
36
37#define i2cdprintk(fmt, arg...) \
38 if (ir_debug) { \
39 printk(KERN_DEBUG "%s/ir: " fmt, ir->c.name , ## arg); \
40 }
41
42#define dprintk(fmt, arg...) \
43 if (ir_debug) { \
44 printk(KERN_DEBUG "%s/ir: " fmt, ir->name , ## arg); \
45 }
46
47/**********************************************************
48 Polling structure used by cx231xx IR's
49 **********************************************************/
50
51struct cx231xx_ir_poll_result {
52 unsigned int toggle_bit:1;
53 unsigned int read_count:7;
54 u8 rc_address;
55 u8 rc_data[4];
56};
57
58struct cx231xx_IR {
59 struct cx231xx *dev;
60 struct input_dev *input;
61 struct ir_input_state ir;
62 char name[32];
63 char phys[32];
64
65 /* poll external decoder */
66 int polling;
67 struct work_struct work;
68 struct timer_list timer;
69 unsigned int last_toggle:1;
70 unsigned int last_readcount;
71 unsigned int repeat_interval;
72
73 int (*get_key) (struct cx231xx_IR *, struct cx231xx_ir_poll_result *);
74};
75
76/**********************************************************
77 Polling code for cx231xx
78 **********************************************************/
79
80static void cx231xx_ir_handle_key(struct cx231xx_IR *ir)
81{
82 int result;
83 int do_sendkey = 0;
84 struct cx231xx_ir_poll_result poll_result;
85
86 /* read the registers containing the IR status */
87 result = ir->get_key(ir, &poll_result);
88 if (result < 0) {
89 dprintk("ir->get_key() failed %d\n", result);
90 return;
91 }
92
93 dprintk("ir->get_key result tb=%02x rc=%02x lr=%02x data=%02x\n",
94 poll_result.toggle_bit, poll_result.read_count,
95 ir->last_readcount, poll_result.rc_data[0]);
96
97 if (ir->dev->chip_id == CHIP_ID_EM2874) {
98 /* The em2874 clears the readcount field every time the
99 register is read. The em2860/2880 datasheet says that it
100 is supposed to clear the readcount, but it doesn't. So with
101 the em2874, we are looking for a non-zero read count as
102 opposed to a readcount that is incrementing */
103 ir->last_readcount = 0;
104 }
105
106 if (poll_result.read_count == 0) {
107 /* The button has not been pressed since the last read */
108 } else if (ir->last_toggle != poll_result.toggle_bit) {
109 /* A button has been pressed */
110 dprintk("button has been pressed\n");
111 ir->last_toggle = poll_result.toggle_bit;
112 ir->repeat_interval = 0;
113 do_sendkey = 1;
114 } else if (poll_result.toggle_bit == ir->last_toggle &&
115 poll_result.read_count > 0 &&
116 poll_result.read_count != ir->last_readcount) {
117 /* The button is still being held down */
118 dprintk("button being held down\n");
119
120 /* Debouncer for first keypress */
121 if (ir->repeat_interval++ > 9) {
122 /* Start repeating after 1 second */
123 do_sendkey = 1;
124 }
125 }
126
127 if (do_sendkey) {
128 dprintk("sending keypress\n");
129 ir_input_keydown(ir->input, &ir->ir, poll_result.rc_data[0],
130 poll_result.rc_data[0]);
131 ir_input_nokey(ir->input, &ir->ir);
132 }
133
134 ir->last_readcount = poll_result.read_count;
135 return;
136}
137
138static void ir_timer(unsigned long data)
139{
140 struct cx231xx_IR *ir = (struct cx231xx_IR *)data;
141
142 schedule_work(&ir->work);
143}
144
145static void cx231xx_ir_work(struct work_struct *work)
146{
147 struct cx231xx_IR *ir = container_of(work, struct cx231xx_IR, work);
148
149 cx231xx_ir_handle_key(ir);
150 mod_timer(&ir->timer, jiffies + msecs_to_jiffies(ir->polling));
151}
152
153void cx231xx_ir_start(struct cx231xx_IR *ir)
154{
155 setup_timer(&ir->timer, ir_timer, (unsigned long)ir);
156 INIT_WORK(&ir->work, cx231xx_ir_work);
157 schedule_work(&ir->work);
158}
159
160static void cx231xx_ir_stop(struct cx231xx_IR *ir)
161{
162 del_timer_sync(&ir->timer);
163 flush_scheduled_work();
164}
165
166int cx231xx_ir_init(struct cx231xx *dev)
167{
168 struct cx231xx_IR *ir;
169 struct input_dev *input_dev;
170 u8 ir_config;
171 int err = -ENOMEM;
172
173 if (dev->board.ir_codes == NULL) {
174 /* No remote control support */
175 return 0;
176 }
177
178 ir = kzalloc(sizeof(*ir), GFP_KERNEL);
179 input_dev = input_allocate_device();
180 if (!ir || !input_dev)
181 goto err_out_free;
182
183 ir->input = input_dev;
184
185 /* Setup the proper handler based on the chip */
186 switch (dev->chip_id) {
187 default:
188 printk("Unrecognized cx231xx chip id: IR not supported\n");
189 goto err_out_free;
190 }
191
192 /* This is how often we ask the chip for IR information */
193 ir->polling = 100; /* ms */
194
195 /* init input device */
196 snprintf(ir->name, sizeof(ir->name), "cx231xx IR (%s)", dev->name);
197
198 usb_make_path(dev->udev, ir->phys, sizeof(ir->phys));
199 strlcat(ir->phys, "/input0", sizeof(ir->phys));
200
201 ir_input_init(input_dev, &ir->ir, IR_TYPE_OTHER, dev->board.ir_codes);
202 input_dev->name = ir->name;
203 input_dev->phys = ir->phys;
204 input_dev->id.bustype = BUS_USB;
205 input_dev->id.version = 1;
206 input_dev->id.vendor = le16_to_cpu(dev->udev->descriptor.idVendor);
207 input_dev->id.product = le16_to_cpu(dev->udev->descriptor.idProduct);
208
209 input_dev->dev.parent = &dev->udev->dev;
210 /* record handles to ourself */
211 ir->dev = dev;
212 dev->ir = ir;
213
214 cx231xx_ir_start(ir);
215
216 /* all done */
217 err = input_register_device(ir->input);
218 if (err)
219 goto err_out_stop;
220
221 return 0;
222err_out_stop:
223 cx231xx_ir_stop(ir);
224 dev->ir = NULL;
225err_out_free:
226 input_free_device(input_dev);
227 kfree(ir);
228 return err;
229}
230
231int cx231xx_ir_fini(struct cx231xx *dev)
232{
233 struct cx231xx_IR *ir = dev->ir;
234
235 /* skip detach on non attached boards */
236 if (!ir)
237 return 0;
238
239 cx231xx_ir_stop(ir);
240 input_unregister_device(ir->input);
241 kfree(ir);
242
243 /* done */
244 dev->ir = NULL;
245 return 0;
246}
diff --git a/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c
new file mode 100644
index 000000000000..7473c33e823e
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c
@@ -0,0 +1,795 @@
1/*
2 cx231xx-pcb-config.c - driver for Conexant
3 Cx23100/101/102 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include "cx231xx.h"
23#include "cx231xx-conf-reg.h"
24
25static unsigned int pcb_debug;
26module_param(pcb_debug, int, 0644);
27MODULE_PARM_DESC(pcb_debug, "enable pcb config debug messages [video]");
28
29/******************************************************************************/
30
31struct pcb_config cx231xx_Scenario[] = {
32 {
33 INDEX_SELFPOWER_DIGITAL_ONLY, /* index */
34 USB_SELF_POWER, /* power_type */
35 0, /* speed , not decide yet */
36 MOD_DIGITAL, /* mode */
37 SOURCE_TS_BDA, /* ts1_source, digital tv only */
38 NOT_SUPPORTED, /* ts2_source */
39 NOT_SUPPORTED, /* analog source */
40
41 0, /* digital_index */
42 0, /* analog index */
43 0, /* dif_index */
44 0, /* external_index */
45
46 1, /* only one configuration */
47 {
48 {
49 0, /* config index */
50 {
51 0, /* interrupt ep index */
52 1, /* ts1 index */
53 NOT_SUPPORTED, /* TS2 index */
54 NOT_SUPPORTED, /* AUDIO */
55 NOT_SUPPORTED, /* VIDEO */
56 NOT_SUPPORTED, /* VANC */
57 NOT_SUPPORTED, /* HANC */
58 NOT_SUPPORTED /* ir_index */
59 }
60 ,
61 }
62 ,
63 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
64 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
65 NOT_SUPPORTED}
66 }
67 ,
68 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
69 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
70 NOT_SUPPORTED}
71 }
72 }
73 ,
74 /* full-speed config */
75 {
76 {
77 0, /* config index */
78 {
79 0, /* interrupt ep index */
80 1, /* ts1 index */
81 NOT_SUPPORTED, /* TS2 index */
82 NOT_SUPPORTED, /* AUDIO */
83 NOT_SUPPORTED, /* VIDEO */
84 NOT_SUPPORTED, /* VANC */
85 NOT_SUPPORTED, /* HANC */
86 NOT_SUPPORTED /* ir_index */
87 }
88 }
89 ,
90 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
91 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
92 NOT_SUPPORTED}
93 }
94 ,
95 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
96 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
97 NOT_SUPPORTED}
98 }
99 }
100 }
101 ,
102
103 {
104 INDEX_SELFPOWER_DUAL_DIGITAL, /* index */
105 USB_SELF_POWER, /* power_type */
106 0, /* speed , not decide yet */
107 MOD_DIGITAL, /* mode */
108 SOURCE_TS_BDA, /* ts1_source, digital tv only */
109 0, /* ts2_source,need update from register */
110 NOT_SUPPORTED, /* analog source */
111 0, /* digital_index */
112 0, /* analog index */
113 0, /* dif_index */
114 0, /* external_index */
115
116 1, /* only one configuration */
117 {
118 {
119 0, /* config index */
120 {
121 0, /* interrupt ep index */
122 1, /* ts1 index */
123 2, /* TS2 index */
124 NOT_SUPPORTED, /* AUDIO */
125 NOT_SUPPORTED, /* VIDEO */
126 NOT_SUPPORTED, /* VANC */
127 NOT_SUPPORTED, /* HANC */
128 NOT_SUPPORTED /* ir_index */
129 }
130 }
131 ,
132 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
133 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
134 NOT_SUPPORTED}
135 }
136 ,
137 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
138 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
139 NOT_SUPPORTED}
140 }
141 }
142 ,
143 /* full-speed */
144 {
145 {
146 0, /* config index */
147 {
148 0, /* interrupt ep index */
149 1, /* ts1 index */
150 2, /* TS2 index */
151 NOT_SUPPORTED, /* AUDIO */
152 NOT_SUPPORTED, /* VIDEO */
153 NOT_SUPPORTED, /* VANC */
154 NOT_SUPPORTED, /* HANC */
155 NOT_SUPPORTED /* ir_index */
156 }
157 }
158 ,
159 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
160 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
161 NOT_SUPPORTED}
162 }
163 ,
164 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
165 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
166 NOT_SUPPORTED}
167 }
168 }
169 }
170 ,
171
172 {
173 INDEX_SELFPOWER_ANALOG_ONLY, /* index */
174 USB_SELF_POWER, /* power_type */
175 0, /* speed , not decide yet */
176 MOD_ANALOG | MOD_DIF | MOD_EXTERNAL, /* mode ,analog tv only */
177 NOT_SUPPORTED, /* ts1_source, NOT SUPPORT */
178 NOT_SUPPORTED, /* ts2_source,NOT SUPPORT */
179 0, /* analog source, need update */
180
181 0, /* digital_index */
182 0, /* analog index */
183 0, /* dif_index */
184 0, /* external_index */
185
186 1, /* only one configuration */
187 {
188 {
189 0, /* config index */
190 {
191 0, /* interrupt ep index */
192 NOT_SUPPORTED, /* ts1 index */
193 NOT_SUPPORTED, /* TS2 index */
194 1, /* AUDIO */
195 2, /* VIDEO */
196 3, /* VANC */
197 4, /* HANC */
198 NOT_SUPPORTED /* ir_index */
199 }
200 }
201 ,
202 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
203 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
204 NOT_SUPPORTED}
205 }
206 ,
207 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
208 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
209 NOT_SUPPORTED}
210 }
211 }
212 ,
213 /* full-speed */
214 {
215 {
216 0, /* config index */
217 {
218 0, /* interrupt ep index */
219 NOT_SUPPORTED, /* ts1 index */
220 NOT_SUPPORTED, /* TS2 index */
221 1, /* AUDIO */
222 2, /* VIDEO */
223 NOT_SUPPORTED, /* VANC */
224 NOT_SUPPORTED, /* HANC */
225 NOT_SUPPORTED /* ir_index */
226 }
227 }
228 ,
229 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
230 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
231 NOT_SUPPORTED}
232 }
233 ,
234 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
235 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
236 NOT_SUPPORTED}
237 }
238 }
239 }
240 ,
241
242 {
243 INDEX_SELFPOWER_DUAL, /* index */
244 USB_SELF_POWER, /* power_type */
245 0, /* speed , not decide yet */
246 /* mode ,analog tv and digital path */
247 MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
248 0, /* ts1_source,will update in register */
249 NOT_SUPPORTED, /* ts2_source,NOT SUPPORT */
250 0, /* analog source need update */
251 0, /* digital_index */
252 0, /* analog index */
253 0, /* dif_index */
254 0, /* external_index */
255 1, /* only one configuration */
256 {
257 {
258 0, /* config index */
259 {
260 0, /* interrupt ep index */
261 1, /* ts1 index */
262 NOT_SUPPORTED, /* TS2 index */
263 2, /* AUDIO */
264 3, /* VIDEO */
265 4, /* VANC */
266 5, /* HANC */
267 NOT_SUPPORTED /* ir_index */
268 }
269 }
270 ,
271 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
272 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
273 NOT_SUPPORTED}
274 }
275 ,
276 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
277 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
278 NOT_SUPPORTED}
279 }
280 }
281 ,
282 /* full-speed */
283 {
284 {
285 0, /* config index */
286 {
287 0, /* interrupt ep index */
288 1, /* ts1 index */
289 NOT_SUPPORTED, /* TS2 index */
290 2, /* AUDIO */
291 3, /* VIDEO */
292 NOT_SUPPORTED, /* VANC */
293 NOT_SUPPORTED, /* HANC */
294 NOT_SUPPORTED /* ir_index */
295 }
296 }
297 ,
298 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
299 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
300 NOT_SUPPORTED}
301 }
302 ,
303 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
304 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
305 NOT_SUPPORTED}
306 }
307 }
308 }
309 ,
310
311 {
312 INDEX_SELFPOWER_TRIPLE, /* index */
313 USB_SELF_POWER, /* power_type */
314 0, /* speed , not decide yet */
315 /* mode ,analog tv and digital path */
316 MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
317 0, /* ts1_source, update in register */
318 0, /* ts2_source,update in register */
319 0, /* analog source, need update */
320
321 0, /* digital_index */
322 0, /* analog index */
323 0, /* dif_index */
324 0, /* external_index */
325 1, /* only one configuration */
326 {
327 {
328 0, /* config index */
329 {
330 0, /* interrupt ep index */
331 1, /* ts1 index */
332 2, /* TS2 index */
333 3, /* AUDIO */
334 4, /* VIDEO */
335 5, /* VANC */
336 6, /* HANC */
337 NOT_SUPPORTED /* ir_index */
338 }
339 }
340 ,
341 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
342 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
343 NOT_SUPPORTED}
344 }
345 ,
346 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
347 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
348 NOT_SUPPORTED}
349 }
350 }
351 ,
352 /* full-speed */
353 {
354 {
355 0, /* config index */
356 {
357 0, /* interrupt ep index */
358 1, /* ts1 index */
359 2, /* TS2 index */
360 3, /* AUDIO */
361 4, /* VIDEO */
362 NOT_SUPPORTED, /* VANC */
363 NOT_SUPPORTED, /* HANC */
364 NOT_SUPPORTED /* ir_index */
365 }
366 }
367 ,
368 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
369 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
370 NOT_SUPPORTED}
371 }
372 ,
373 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
374 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
375 NOT_SUPPORTED}
376 }
377 }
378 }
379 ,
380
381 {
382 INDEX_SELFPOWER_COMPRESSOR, /* index */
383 USB_SELF_POWER, /* power_type */
384 0, /* speed , not decide yet */
385 /* mode ,analog tv AND DIGITAL path */
386 MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
387 NOT_SUPPORTED, /* ts1_source, disable */
388 SOURCE_TS_BDA, /* ts2_source */
389 0, /* analog source,need update */
390 0, /* digital_index */
391 0, /* analog index */
392 0, /* dif_index */
393 0, /* external_index */
394 1, /* only one configuration */
395 {
396 {
397 0, /* config index */
398 {
399 0, /* interrupt ep index */
400 NOT_SUPPORTED, /* ts1 index */
401 1, /* TS2 index */
402 2, /* AUDIO */
403 3, /* VIDEO */
404 4, /* VANC */
405 5, /* HANC */
406 NOT_SUPPORTED /* ir_index */
407 }
408 }
409 ,
410 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
411 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
412 NOT_SUPPORTED}
413 }
414 ,
415 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
416 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
417 NOT_SUPPORTED}
418 }
419 }
420 ,
421 /* full-speed */
422 {
423 {
424 0, /* config index */
425 {
426 0, /* interrupt ep index */
427 NOT_SUPPORTED, /* ts1 index */
428 1, /* TS2 index */
429 2, /* AUDIO */
430 3, /* VIDEO */
431 NOT_SUPPORTED, /* VANC */
432 NOT_SUPPORTED, /* HANC */
433 NOT_SUPPORTED /* ir_index */
434 }
435 }
436 ,
437 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
438 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
439 NOT_SUPPORTED}
440 }
441 ,
442 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
443 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
444 NOT_SUPPORTED}
445 }
446 }
447 }
448 ,
449
450 {
451 INDEX_BUSPOWER_DIGITAL_ONLY, /* index */
452 USB_BUS_POWER, /* power_type */
453 0, /* speed , not decide yet */
454 MOD_DIGITAL, /* mode ,analog tv AND DIGITAL path */
455 SOURCE_TS_BDA, /* ts1_source, disable */
456 NOT_SUPPORTED, /* ts2_source */
457 NOT_SUPPORTED, /* analog source */
458
459 0, /* digital_index */
460 0, /* analog index */
461 0, /* dif_index */
462 0, /* external_index */
463
464 1, /* only one configuration */
465 {
466 {
467 0, /* config index */
468 {
469 0, /* interrupt ep index = 2 */
470 1, /* ts1 index */
471 NOT_SUPPORTED, /* TS2 index */
472 NOT_SUPPORTED, /* AUDIO */
473 NOT_SUPPORTED, /* VIDEO */
474 NOT_SUPPORTED, /* VANC */
475 NOT_SUPPORTED, /* HANC */
476 NOT_SUPPORTED /* ir_index */
477 }
478 }
479 ,
480 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
481 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
482 NOT_SUPPORTED}
483 }
484 ,
485 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
486 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
487 NOT_SUPPORTED}
488 }
489 }
490 ,
491 /* full-speed */
492 {
493 {
494 0, /* config index */
495 {
496 0, /* interrupt ep index = 2 */
497 1, /* ts1 index */
498 NOT_SUPPORTED, /* TS2 index */
499 NOT_SUPPORTED, /* AUDIO */
500 NOT_SUPPORTED, /* VIDEO */
501 NOT_SUPPORTED, /* VANC */
502 NOT_SUPPORTED, /* HANC */
503 NOT_SUPPORTED /* ir_index */
504 }
505 }
506 ,
507 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
508 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
509 NOT_SUPPORTED}
510 }
511 ,
512 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
513 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
514 NOT_SUPPORTED}
515 }
516 }
517 }
518 ,
519 {
520 INDEX_BUSPOWER_ANALOG_ONLY, /* index */
521 USB_BUS_POWER, /* power_type */
522 0, /* speed , not decide yet */
523 MOD_ANALOG, /* mode ,analog tv AND DIGITAL path */
524 NOT_SUPPORTED, /* ts1_source, disable */
525 NOT_SUPPORTED, /* ts2_source */
526 SOURCE_ANALOG, /* analog source--analog */
527 0, /* digital_index */
528 0, /* analog index */
529 0, /* dif_index */
530 0, /* external_index */
531 1, /* only one configuration */
532 {
533 {
534 0, /* config index */
535 {
536 0, /* interrupt ep index */
537 NOT_SUPPORTED, /* ts1 index */
538 NOT_SUPPORTED, /* TS2 index */
539 1, /* AUDIO */
540 2, /* VIDEO */
541 3, /* VANC */
542 4, /* HANC */
543 NOT_SUPPORTED /* ir_index */
544 }
545 }
546 ,
547 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
548 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
549 NOT_SUPPORTED}
550 }
551 ,
552 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
553 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
554 NOT_SUPPORTED}
555 }
556 }
557 ,
558 { /* full-speed */
559 {
560 0, /* config index */
561 {
562 0, /* interrupt ep index */
563 NOT_SUPPORTED, /* ts1 index */
564 NOT_SUPPORTED, /* TS2 index */
565 1, /* AUDIO */
566 2, /* VIDEO */
567 NOT_SUPPORTED, /* VANC */
568 NOT_SUPPORTED, /* HANC */
569 NOT_SUPPORTED /* ir_index */
570 }
571 }
572 ,
573 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
574 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
575 NOT_SUPPORTED}
576 }
577 ,
578 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
579 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
580 NOT_SUPPORTED}
581 }
582 }
583 }
584 ,
585 {
586 INDEX_BUSPOWER_DIF_ONLY, /* index */
587 USB_BUS_POWER, /* power_type */
588 0, /* speed , not decide yet */
589 /* mode ,analog tv AND DIGITAL path */
590 MOD_DIF | MOD_ANALOG | MOD_DIGITAL | MOD_EXTERNAL,
591 SOURCE_TS_BDA, /* ts1_source, disable */
592 NOT_SUPPORTED, /* ts2_source */
593 SOURCE_DIF | SOURCE_ANALOG | SOURCE_EXTERNAL, /* analog source, dif */
594 0, /* digital_index */
595 0, /* analog index */
596 0, /* dif_index */
597 0, /* external_index */
598 1, /* only one configuration */
599 {
600 {
601 0, /* config index */
602 {
603 0, /* interrupt ep index */
604 1, /* ts1 index */
605 NOT_SUPPORTED, /* TS2 index */
606 2, /* AUDIO */
607 3, /* VIDEO */
608 4, /* VANC */
609 5, /* HANC */
610 NOT_SUPPORTED /* ir_index */
611 }
612 }
613 ,
614 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
615 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
616 NOT_SUPPORTED}
617 }
618 ,
619 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
620 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
621 NOT_SUPPORTED}
622 }
623 }
624 ,
625 { /* full speed */
626 {
627 0, /* config index */
628 {
629 0, /* interrupt ep index */
630 1, /* ts1 index */
631 NOT_SUPPORTED, /* TS2 index */
632 2, /* AUDIO */
633 3, /* VIDEO */
634 NOT_SUPPORTED, /* VANC */
635 NOT_SUPPORTED, /* HANC */
636 NOT_SUPPORTED /* ir_index */
637 }
638 }
639 ,
640 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
641 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
642 NOT_SUPPORTED}
643 }
644 ,
645 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
646 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
647 NOT_SUPPORTED}
648 }
649 }
650 }
651 ,
652
653};
654
655/*****************************************************************/
656
657u32 initialize_cx231xx(struct cx231xx *dev)
658{
659 u32 config_info = 0;
660 struct pcb_config *p_pcb_info;
661 u8 usb_speed = 1; /* from register,1--HS, 0--FS */
662 u8 data[4] = { 0, 0, 0, 0 };
663 u32 ts1_source = 0;
664 u32 ts2_source = 0;
665 u32 analog_source = 0;
666 u8 _current_scenario_idx = 0xff;
667
668 ts1_source = SOURCE_TS_BDA;
669 ts2_source = SOURCE_TS_BDA;
670
671 /* read board config register to find out which
672 pcb config it is related to */
673 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, data, 4);
674
675 config_info = *((u32 *) data);
676 usb_speed = (u8) (config_info & 0x1);
677
678 /* Verify this device belongs to Bus power or Self power device */
679 if (config_info & BUS_POWER) { /* bus-power */
680 switch (config_info & BUSPOWER_MASK) {
681 case TS1_PORT | BUS_POWER:
682 cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY].speed =
683 usb_speed;
684 p_pcb_info =
685 &cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY];
686 _current_scenario_idx = INDEX_BUSPOWER_DIGITAL_ONLY;
687 break;
688 case AVDEC_ENABLE | BUS_POWER:
689 cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY].speed =
690 usb_speed;
691 p_pcb_info =
692 &cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY];
693 _current_scenario_idx = INDEX_BUSPOWER_ANALOG_ONLY;
694 break;
695 case AVDEC_ENABLE | BUS_POWER | TS1_PORT:
696 cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY].speed =
697 usb_speed;
698 p_pcb_info = &cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY];
699 _current_scenario_idx = INDEX_BUSPOWER_DIF_ONLY;
700 break;
701 default:
702 cx231xx_info("bad config in buspower!!!!\n");
703 cx231xx_info("config_info=%x\n",
704 (config_info & BUSPOWER_MASK));
705 return 1;
706 }
707 } else { /* self-power */
708
709 switch (config_info & SELFPOWER_MASK) {
710 case TS1_PORT | SELF_POWER:
711 cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY].speed =
712 usb_speed;
713 p_pcb_info =
714 &cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY];
715 _current_scenario_idx = INDEX_SELFPOWER_DIGITAL_ONLY;
716 break;
717 case TS1_TS2_PORT | SELF_POWER:
718 cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].speed =
719 usb_speed;
720 cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].
721 ts2_source = ts2_source;
722 p_pcb_info =
723 &cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL];
724 _current_scenario_idx = INDEX_SELFPOWER_DUAL_DIGITAL;
725 break;
726 case AVDEC_ENABLE | SELF_POWER:
727 cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].speed =
728 usb_speed;
729 cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].
730 analog_source = analog_source;
731 p_pcb_info =
732 &cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY];
733 _current_scenario_idx = INDEX_SELFPOWER_ANALOG_ONLY;
734 break;
735 case AVDEC_ENABLE | TS1_PORT | SELF_POWER:
736 cx231xx_Scenario[INDEX_SELFPOWER_DUAL].speed =
737 usb_speed;
738 cx231xx_Scenario[INDEX_SELFPOWER_DUAL].ts1_source =
739 ts1_source;
740 cx231xx_Scenario[INDEX_SELFPOWER_DUAL].analog_source =
741 analog_source;
742 p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_DUAL];
743 _current_scenario_idx = INDEX_SELFPOWER_DUAL;
744 break;
745 case AVDEC_ENABLE | TS1_TS2_PORT | SELF_POWER:
746 cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].speed =
747 usb_speed;
748 cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts1_source =
749 ts1_source;
750 cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts2_source =
751 ts2_source;
752 cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].analog_source =
753 analog_source;
754 p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE];
755 _current_scenario_idx = INDEX_SELFPOWER_TRIPLE;
756 break;
757 case AVDEC_ENABLE | TS1VIP_TS2_PORT | SELF_POWER:
758 cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].speed =
759 usb_speed;
760 cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].
761 analog_source = analog_source;
762 p_pcb_info =
763 &cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR];
764 _current_scenario_idx = INDEX_SELFPOWER_COMPRESSOR;
765 break;
766 default:
767 cx231xx_info("bad senario!!!!!\n");
768 cx231xx_info("config_info=%x\n",
769 (config_info & SELFPOWER_MASK));
770 return 1;
771 }
772 }
773
774 dev->current_scenario_idx = _current_scenario_idx;
775
776 memcpy(&dev->current_pcb_config, p_pcb_info,
777 sizeof(struct pcb_config));
778
779 if (pcb_debug) {
780 cx231xx_info("SC(0x00) register = 0x%x\n", config_info);
781 cx231xx_info("scenario %d\n",
782 (dev->current_pcb_config.index) + 1);
783 cx231xx_info("type=%x\n", dev->current_pcb_config.type);
784 cx231xx_info("mode=%x\n", dev->current_pcb_config.mode);
785 cx231xx_info("speed=%x\n", dev->current_pcb_config.speed);
786 cx231xx_info("ts1_source=%x\n",
787 dev->current_pcb_config.ts1_source);
788 cx231xx_info("ts2_source=%x\n",
789 dev->current_pcb_config.ts2_source);
790 cx231xx_info("analog_source=%x\n",
791 dev->current_pcb_config.analog_source);
792 }
793
794 return 0;
795}
diff --git a/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h
new file mode 100644
index 000000000000..f5e46e89f3ab
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h
@@ -0,0 +1,231 @@
1/*
2 cx231xx-pcb-cfg.h - driver for Conexant
3 Cx23100/101/102 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _PCB_CONFIG_H_
23#define _PCB_CONFIG_H_
24
25#include <linux/init.h>
26#include <linux/module.h>
27
28/***************************************************************************
29 * Class Information *
30***************************************************************************/
31#define CLASS_DEFAULT 0xFF
32
33enum VENDOR_REQUEST_TYPE {
34 /* Set/Get I2C */
35 VRT_SET_I2C0 = 0x0,
36 VRT_SET_I2C1 = 0x1,
37 VRT_SET_I2C2 = 0x2,
38 VRT_GET_I2C0 = 0x4,
39 VRT_GET_I2C1 = 0x5,
40 VRT_GET_I2C2 = 0x6,
41
42 /* Set/Get GPIO */
43 VRT_SET_GPIO = 0x8,
44 VRT_GET_GPIO = 0x9,
45
46 /* Set/Get GPIE */
47 VRT_SET_GPIE = 0xA,
48 VRT_GET_GPIE = 0xB,
49
50 /* Set/Get Register Control/Status */
51 VRT_SET_REGISTER = 0xC,
52 VRT_GET_REGISTER = 0xD,
53
54 /* Get Extended Compat ID Descriptor */
55 VRT_GET_EXTCID_DESC = 0xFF,
56};
57
58enum BYTE_ENABLE_MASK {
59 ENABLE_ONE_BYTE = 0x1,
60 ENABLE_TWE_BYTE = 0x3,
61 ENABLE_THREE_BYTE = 0x7,
62 ENABLE_FOUR_BYTE = 0xF,
63};
64
65#define SPEED_MASK 0x1
66enum USB_SPEED{
67 FULL_SPEED = 0x0, /* 0: full speed */
68 HIGH_SPEED = 0x1 /* 1: high speed */
69};
70
71enum _true_false{
72 FALSE = 0,
73 TRUE = 1
74};
75
76#define TS_MASK 0x6
77enum TS_PORT{
78 NO_TS_PORT = 0x0, /* 2'b00: Neither port used. PCB not a Hybrid,
79 only offers Analog TV or Video */
80 TS1_PORT = 0x4, /* 2'b10: TS1 Input (Hybrid mode :
81 Digital or External Analog/Compressed source) */
82 TS1_TS2_PORT = 0x6, /* 2'b11: TS1 & TS2 Inputs
83 (Dual inputs from Digital and/or
84 External Analog/Compressed sources) */
85 TS1_EXT_CLOCK = 0x6, /* 2'b11: TS1 & TS2 as selector
86 to external clock */
87 TS1VIP_TS2_PORT = 0x2 /* 2'b01: TS1 used as 656/VIP Output,
88 TS2 Input (from Compressor) */
89};
90
91#define EAVP_MASK 0x8
92enum EAV_PRESENT{
93 NO_EXTERNAL_AV = 0x0, /* 0: No External A/V inputs
94 (no need for i2s blcok),
95 Analog Tuner must be present */
96 EXTERNAL_AV = 0x8 /* 1: External A/V inputs
97 present (requires i2s blk) */
98};
99
100#define ATM_MASK 0x30
101enum AT_MODE{
102 DIF_TUNER = 0x30, /* 2'b11: IF Tuner (requires use of DIF) */
103 BASEBAND_SOUND = 0x20, /* 2'b10: Baseband Composite &
104 Sound-IF Signals present */
105 NO_TUNER = 0x10 /* 2'b0x: No Analog Tuner present */
106};
107
108#define PWR_SEL_MASK 0x40
109enum POWE_TYPE{
110 SELF_POWER = 0x0, /* 0: self power */
111 BUS_POWER = 0x40 /* 1: bus power */
112};
113
114enum USB_POWE_TYPE{
115 USB_SELF_POWER = 0,
116 USB_BUS_POWER
117};
118
119#define BO_0_MASK 0x80
120enum AVDEC_STATUS{
121 AVDEC_DISABLE = 0x0, /* 0: A/V Decoder Disabled */
122 AVDEC_ENABLE = 0x80 /* 1: A/V Decoder Enabled */
123};
124
125#define BO_1_MASK 0x100
126
127#define BUSPOWER_MASK 0xC4 /* for Polaris spec 0.8 */
128#define SELFPOWER_MASK 0x86
129
130/***************************************************************************/
131#define NOT_DECIDE_YET 0xFE
132#define NOT_SUPPORTED 0xFF
133
134/***************************************************************************
135 * for mod field use *
136***************************************************************************/
137#define MOD_DIGITAL 0x1
138#define MOD_ANALOG 0x2
139#define MOD_DIF 0x4
140#define MOD_EXTERNAL 0x8
141#define CAP_ALL_MOD 0x0f
142
143/***************************************************************************
144 * source define *
145***************************************************************************/
146#define SOURCE_DIGITAL 0x1
147#define SOURCE_ANALOG 0x2
148#define SOURCE_DIF 0x4
149#define SOURCE_EXTERNAL 0x8
150#define SOURCE_TS_BDA 0x10
151#define SOURCE_TS_ENCODE 0x20
152#define SOURCE_TS_EXTERNAL 0x40
153
154/***************************************************************************
155 * interface information define *
156***************************************************************************/
157struct INTERFACE_INFO {
158 u8 interrupt_index;
159 u8 ts1_index;
160 u8 ts2_index;
161 u8 audio_index;
162 u8 video_index;
163 u8 vanc_index; /* VBI */
164 u8 hanc_index; /* Sliced CC */
165 u8 ir_index;
166};
167
168enum INDEX_INTERFACE_INFO{
169 INDEX_INTERRUPT = 0x0,
170 INDEX_TS1,
171 INDEX_TS2,
172 INDEX_AUDIO,
173 INDEX_VIDEO,
174 INDEX_VANC,
175 INDEX_HANC,
176 INDEX_IR,
177};
178
179/***************************************************************************
180 * configuration information define *
181***************************************************************************/
182struct CONFIG_INFO {
183 u8 config_index;
184 struct INTERFACE_INFO interface_info;
185};
186
187struct pcb_config {
188 u8 index;
189 u8 type; /* bus power or self power,
190 self power--0, bus_power--1 */
191 u8 speed; /* usb speed, 2.0--1, 1.1--0 */
192 u8 mode; /* digital , anlog, dif or external A/V */
193 u32 ts1_source; /* three source -- BDA,External,encode */
194 u32 ts2_source;
195 u32 analog_source;
196 u8 digital_index; /* bus-power used */
197 u8 analog_index; /* bus-power used */
198 u8 dif_index; /* bus-power used */
199 u8 external_index; /* bus-power used */
200 u8 config_num; /* current config num, 0,1,2,
201 for self-power, always 0 */
202 struct CONFIG_INFO hs_config_info[3];
203 struct CONFIG_INFO fs_config_info[3];
204};
205
206enum INDEX_PCB_CONFIG{
207 INDEX_SELFPOWER_DIGITAL_ONLY = 0x0,
208 INDEX_SELFPOWER_DUAL_DIGITAL,
209 INDEX_SELFPOWER_ANALOG_ONLY,
210 INDEX_SELFPOWER_DUAL,
211 INDEX_SELFPOWER_TRIPLE,
212 INDEX_SELFPOWER_COMPRESSOR,
213 INDEX_BUSPOWER_DIGITAL_ONLY,
214 INDEX_BUSPOWER_ANALOG_ONLY,
215 INDEX_BUSPOWER_DIF_ONLY,
216 INDEX_BUSPOWER_EXTERNAL_ONLY,
217 INDEX_BUSPOWER_EXTERNAL_ANALOG,
218 INDEX_BUSPOWER_EXTERNAL_DIF,
219 INDEX_BUSPOWER_EXTERNAL_DIGITAL,
220 INDEX_BUSPOWER_DIGITAL_ANALOG,
221 INDEX_BUSPOWER_DIGITAL_DIF,
222 INDEX_BUSPOWER_DIGITAL_ANALOG_EXTERNAL,
223 INDEX_BUSPOWER_DIGITAL_DIF_EXTERNAL,
224};
225
226/***************************************************************************/
227struct cx231xx;
228
229u32 initialize_cx231xx(struct cx231xx *p_dev);
230
231#endif
diff --git a/drivers/media/video/cx231xx/cx231xx-reg.h b/drivers/media/video/cx231xx/cx231xx-reg.h
new file mode 100644
index 000000000000..750c5d37d569
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-reg.h
@@ -0,0 +1,1564 @@
1/*
2 cx231xx-reg.h - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _CX231XX_REG_H
23#define _CX231XX_REG_H
24
25/*****************************************************************************
26 * VBI codes *
27*****************************************************************************/
28
29#define SAV_ACTIVE_VIDEO_FIELD1 0x80
30#define EAV_ACTIVE_VIDEO_FIELD1 0x90
31
32#define SAV_ACTIVE_VIDEO_FIELD2 0xc0
33#define EAV_ACTIVE_VIDEO_FIELD2 0xd0
34
35#define SAV_VBLANK_FIELD1 0xa0
36#define EAV_VBLANK_FIELD1 0xb0
37
38#define SAV_VBLANK_FIELD2 0xe0
39#define EAV_VBLANK_FIELD2 0xf0
40
41#define SAV_VBI_FIELD1 0x20
42#define EAV_VBI_FIELD1 0x30
43
44#define SAV_VBI_FIELD2 0x60
45#define EAV_VBI_FIELD2 0x70
46
47/*****************************************************************************/
48/* Audio ADC Registers */
49#define CH_PWR_CTRL1 0x0000000e
50#define CH_PWR_CTRL2 0x0000000f
51/*****************************************************************************/
52
53#define HOST_REG1 0x000
54#define FLD_FORCE_CHIP_SEL 0x80
55#define FLD_AUTO_INC_DIS 0x20
56#define FLD_PREFETCH_EN 0x10
57/* Reserved [2:3] */
58#define FLD_DIGITAL_PWR_DN 0x02
59#define FLD_SLEEP 0x01
60
61/*****************************************************************************/
62#define HOST_REG2 0x001
63
64/*****************************************************************************/
65#define HOST_REG3 0x002
66
67/*****************************************************************************/
68/* added for polaris */
69#define GPIO_PIN_CTL0 0x3
70#define GPIO_PIN_CTL1 0x4
71#define GPIO_PIN_CTL2 0x5
72#define GPIO_PIN_CTL3 0x6
73#define TS1_PIN_CTL0 0x7
74#define TS1_PIN_CTL1 0x8
75/*****************************************************************************/
76
77#define FLD_CLK_IN_EN 0x80
78#define FLD_XTAL_CTRL 0x70
79#define FLD_BB_CLK_MODE 0x0C
80#define FLD_REF_DIV_PLL 0x02
81#define FLD_REF_SEL_PLL1 0x01
82
83/*****************************************************************************/
84#define CHIP_CTRL 0x100
85/* Reserved [27] */
86/* Reserved [31:21] */
87#define FLD_CHIP_ACFG_DIS 0x00100000
88/* Reserved [19] */
89#define FLD_DUAL_MODE_ADC2 0x00040000
90#define FLD_SIF_EN 0x00020000
91#define FLD_SOFT_RST 0x00010000
92#define FLD_DEVICE_ID 0x0000ffff
93
94/*****************************************************************************/
95#define AFE_CTRL 0x104
96#define AFE_CTRL_C2HH_SRC_CTRL 0x104
97#define FLD_DIF_OUT_SEL 0xc0000000
98#define FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000
99#define FLD_UV_ORDER_MODE 0x02000000
100#define FLD_FUNC_MODE 0x01800000
101#define FLD_ROT1_PHASE_CTL 0x007f8000
102#define FLD_AUD_IN_SEL 0x00004000
103#define FLD_LUMA_IN_SEL 0x00002000
104#define FLD_CHROMA_IN_SEL 0x00001000
105/* reserve [11:10] */
106#define FLD_INV_SPEC_DIS 0x00000200
107#define FLD_VGA_SEL_CH3 0x00000100
108#define FLD_VGA_SEL_CH2 0x00000080
109#define FLD_VGA_SEL_CH1 0x00000040
110#define FLD_DCR_BYP_CH1 0x00000020
111#define FLD_DCR_BYP_CH2 0x00000010
112#define FLD_DCR_BYP_CH3 0x00000008
113#define FLD_EN_12DB_CH3 0x00000004
114#define FLD_EN_12DB_CH2 0x00000002
115#define FLD_EN_12DB_CH1 0x00000001
116
117/* redefine in Cx231xx */
118/*****************************************************************************/
119#define DC_CTRL1 0x108
120/* reserve [31:30] */
121#define FLD_CLAMP_LVL_CH1 0x3fff8000
122#define FLD_CLAMP_LVL_CH2 0x00007fff
123/*****************************************************************************/
124
125/*****************************************************************************/
126#define DC_CTRL2 0x10c
127/* reserve [31:28] */
128#define FLD_CLAMP_LVL_CH3 0x00fffe00
129#define FLD_CLAMP_WIND_LENTH 0x000001e0
130#define FLD_C2HH_SAT_MIN 0x0000001e
131#define FLD_FLT_BYP_SEL 0x00000001
132/*****************************************************************************/
133
134/*****************************************************************************/
135#define DC_CTRL3 0x110
136/* reserve [31:16] */
137#define FLD_ERR_GAIN_CTL 0x00070000
138#define FLD_LPF_MIN 0x0000ffff
139/*****************************************************************************/
140
141/*****************************************************************************/
142#define DC_CTRL4 0x114
143/* reserve [31:31] */
144#define FLD_INTG_CH1 0x7fffffff
145/*****************************************************************************/
146
147/*****************************************************************************/
148#define DC_CTRL5 0x118
149/* reserve [31:31] */
150#define FLD_INTG_CH2 0x7fffffff
151/*****************************************************************************/
152
153/*****************************************************************************/
154#define DC_CTRL6 0x11c
155/* reserve [31:31] */
156#define FLD_INTG_CH3 0x7fffffff
157/*****************************************************************************/
158
159/*****************************************************************************/
160#define PIN_CTRL 0x120
161#define FLD_OEF_AGC_RF 0x00000001
162#define FLD_OEF_AGC_IFVGA 0x00000002
163#define FLD_OEF_AGC_IF 0x00000004
164#define FLD_REG_BO_PUD 0x80000000
165#define FLD_IR_IRQ_STAT 0x40000000
166#define FLD_AUD_IRQ_STAT 0x20000000
167#define FLD_VID_IRQ_STAT 0x10000000
168/* Reserved [27:26] */
169#define FLD_IRQ_N_OUT_EN 0x02000000
170#define FLD_IRQ_N_POLAR 0x01000000
171/* Reserved [23:6] */
172#define FLD_OE_AUX_PLL_CLK 0x00000020
173#define FLD_OE_I2S_BCLK 0x00000010
174#define FLD_OE_I2S_WCLK 0x00000008
175#define FLD_OE_AGC_IF 0x00000004
176#define FLD_OE_AGC_IFVGA 0x00000002
177#define FLD_OE_AGC_RF 0x00000001
178
179/*****************************************************************************/
180#define AUD_IO_CTRL 0x124
181/* Reserved [31:8] */
182#define FLD_I2S_PORT_DIR 0x00000080
183#define FLD_I2S_OUT_SRC 0x00000040
184#define FLD_AUD_CHAN3_SRC 0x00000030
185#define FLD_AUD_CHAN2_SRC 0x0000000c
186#define FLD_AUD_CHAN1_SRC 0x00000003
187
188/*****************************************************************************/
189#define AUD_LOCK1 0x128
190#define FLD_AUD_LOCK_KI_SHIFT 0xc0000000
191#define FLD_AUD_LOCK_KD_SHIFT 0x30000000
192/* Reserved [27:25] */
193#define FLD_EN_AV_LOCK 0x01000000
194#define FLD_VID_COUNT 0x00ffffff
195
196/*****************************************************************************/
197#define AUD_LOCK2 0x12c
198#define FLD_AUD_LOCK_KI_MULT 0xf0000000
199#define FLD_AUD_LOCK_KD_MULT 0x0F000000
200/* Reserved [23:22] */
201#define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000
202#define FLD_AUD_COUNT 0x000fffff
203
204/*****************************************************************************/
205#define AFE_DIAG_CTRL1 0x134
206/* Reserved [31:16] */
207#define FLD_CUV_DLY_LENGTH 0x0000ff00
208#define FLD_YC_DLY_LENGTH 0x000000ff
209
210/*****************************************************************************/
211/* Poalris redefine */
212#define AFE_DIAG_CTRL3 0x138
213/* Reserved [31:26] */
214#define FLD_AUD_DUAL_FLAG_POL 0x02000000
215#define FLD_VID_DUAL_FLAG_POL 0x01000000
216/* Reserved [23:23] */
217#define FLD_COL_CLAMP_DIS_CH1 0x00400000
218#define FLD_COL_CLAMP_DIS_CH2 0x00200000
219#define FLD_COL_CLAMP_DIS_CH3 0x00100000
220
221#define TEST_CTRL1 0x144
222/* Reserved [31:29] */
223#define FLD_LBIST_EN 0x10000000
224/* Reserved [27:10] */
225#define FLD_FI_BIST_INTR_R 0x0000200
226#define FLD_FI_BIST_INTR_L 0x0000100
227#define FLD_BIST_FAIL_AUD_PLL 0x0000080
228#define FLD_BIST_INTR_AUD_PLL 0x0000040
229#define FLD_BIST_FAIL_VID_PLL 0x0000020
230#define FLD_BIST_INTR_VID_PLL 0x0000010
231/* Reserved [3:1] */
232#define FLD_CIR_TEST_DIS 0x00000001
233
234/*****************************************************************************/
235#define TEST_CTRL2 0x148
236#define FLD_TSXCLK_POL_CTL 0x80000000
237#define FLD_ISO_CTL_SEL 0x40000000
238#define FLD_ISO_CTL_EN 0x20000000
239#define FLD_BIST_DEBUGZ 0x10000000
240#define FLD_AUD_BIST_TEST_H 0x0f000000
241/* Reserved [23:22] */
242#define FLD_FLTRN_BIST_TEST_H 0x00020000
243#define FLD_VID_BIST_TEST_H 0x00010000
244/* Reserved [19:17] */
245#define FLD_BIST_TEST_H 0x00010000
246/* Reserved [15:13] */
247#define FLD_TAB_EN 0x00001000
248/* Reserved [11:0] */
249
250/*****************************************************************************/
251#define BIST_STAT 0x14c
252#define FLD_AUD_BIST_FAIL_H 0xfff00000
253#define FLD_FLTRN_BIST_FAIL_H 0x00180000
254#define FLD_VID_BIST_FAIL_H 0x00070000
255#define FLD_AUD_BIST_TST_DONE 0x0000fff0
256#define FLD_FLTRN_BIST_TST_DONE 0x00000008
257#define FLD_VID_BIST_TST_DONE 0x00000007
258
259/*****************************************************************************/
260/* DirectIF registers definition have been moved to DIF_reg.h */
261/*****************************************************************************/
262#define MODE_CTRL 0x400
263#define FLD_AFD_PAL60_DIS 0x20000000
264#define FLD_AFD_FORCE_SECAM 0x10000000
265#define FLD_AFD_FORCE_PALNC 0x08000000
266#define FLD_AFD_FORCE_PAL 0x04000000
267#define FLD_AFD_PALM_SEL 0x03000000
268#define FLD_CKILL_MODE 0x00300000
269#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */
270#define FLD_CLR_LOCK_STAT 0x00020000
271#define FLD_FAST_LOCK_MD 0x00010000
272#define FLD_WCEN 0x00008000
273#define FLD_CAGCEN 0x00004000
274#define FLD_CKILLEN 0x00002000
275#define FLD_AUTO_SC_LOCK 0x00001000
276#define FLD_MAN_SC_FAST_LOCK 0x00000800
277#define FLD_INPUT_MODE 0x00000600
278#define FLD_AFD_ACQUIRE 0x00000100
279#define FLD_AFD_NTSC_SEL 0x00000080
280#define FLD_AFD_PAL_SEL 0x00000040
281#define FLD_ACFG_DIS 0x00000020
282#define FLD_SQ_PIXEL 0x00000010
283#define FLD_VID_FMT_SEL 0x0000000f
284
285/*****************************************************************************/
286#define OUT_CTRL1 0x404
287#define FLD_POLAR 0x7f000000
288/* Reserved [23] */
289#define FLD_RND_MODE 0x00600000
290#define FLD_VIPCLAMP_EN 0x00100000
291#define FLD_VIPBLANK_EN 0x00080000
292#define FLD_VIP_OPT_AL 0x00040000
293#define FLD_IDID0_SOURCE 0x00020000
294#define FLD_DCMODE 0x00010000
295#define FLD_CLK_GATING 0x0000c000
296#define FLD_CLK_INVERT 0x00002000
297#define FLD_HSFMT 0x00001000
298#define FLD_VALIDFMT 0x00000800
299#define FLD_ACTFMT 0x00000400
300#define FLD_SWAPRAW 0x00000200
301#define FLD_CLAMPRAW_EN 0x00000100
302#define FLD_BLUE_FIELD_EN 0x00000080
303#define FLD_BLUE_FIELD_ACT 0x00000040
304#define FLD_TASKBIT_VAL 0x00000020
305#define FLD_ANC_DATA_EN 0x00000010
306#define FLD_VBIHACTRAW_EN 0x00000008
307#define FLD_MODE10B 0x00000004
308#define FLD_OUT_MODE 0x00000003
309
310/*****************************************************************************/
311#define OUT_CTRL2 0x408
312#define FLD_AUD_GRP 0xc0000000
313#define FLD_SAMPLE_RATE 0x30000000
314#define FLD_AUD_ANC_EN 0x08000000
315#define FLD_EN_C 0x04000000
316#define FLD_EN_B 0x02000000
317#define FLD_EN_A 0x01000000
318/* Reserved [23:20] */
319#define FLD_IDID1_LSB 0x000c0000
320#define FLD_IDID0_LSB 0x00030000
321#define FLD_IDID1_MSB 0x0000ff00
322#define FLD_IDID0_MSB 0x000000ff
323
324/*****************************************************************************/
325#define GEN_STAT 0x40c
326#define FLD_VCR_DETECT 0x00800000
327#define FLD_SPECIAL_PLAY_N 0x00400000
328#define FLD_VPRES 0x00200000
329#define FLD_AGC_LOCK 0x00100000
330#define FLD_CSC_LOCK 0x00080000
331#define FLD_VLOCK 0x00040000
332#define FLD_SRC_LOCK 0x00020000
333#define FLD_HLOCK 0x00010000
334#define FLD_VSYNC_N 0x00008000
335#define FLD_SRC_FIFO_UFLOW 0x00004000
336#define FLD_SRC_FIFO_OFLOW 0x00002000
337#define FLD_FIELD 0x00001000
338#define FLD_AFD_FMT_STAT 0x00000f00
339#define FLD_MV_TYPE2_PAIR 0x00000080
340#define FLD_MV_T3CS 0x00000040
341#define FLD_MV_CS 0x00000020
342#define FLD_MV_PSP 0x00000010
343/* Reserved [3] */
344#define FLD_MV_CDAT 0x00000003
345
346/*****************************************************************************/
347#define INT_STAT_MASK 0x410
348#define FLD_COMB_3D_FIFO_MSK 0x80000000
349#define FLD_WSS_DAT_AVAIL_MSK 0x40000000
350#define FLD_GS2_DAT_AVAIL_MSK 0x20000000
351#define FLD_GS1_DAT_AVAIL_MSK 0x10000000
352#define FLD_CC_DAT_AVAIL_MSK 0x08000000
353#define FLD_VPRES_CHANGE_MSK 0x04000000
354#define FLD_MV_CHANGE_MSK 0x02000000
355#define FLD_END_VBI_EVEN_MSK 0x01000000
356#define FLD_END_VBI_ODD_MSK 0x00800000
357#define FLD_FMT_CHANGE_MSK 0x00400000
358#define FLD_VSYNC_TRAIL_MSK 0x00200000
359#define FLD_HLOCK_CHANGE_MSK 0x00100000
360#define FLD_VLOCK_CHANGE_MSK 0x00080000
361#define FLD_CSC_LOCK_CHANGE_MSK 0x00040000
362#define FLD_SRC_FIFO_UFLOW_MSK 0x00020000
363#define FLD_SRC_FIFO_OFLOW_MSK 0x00010000
364#define FLD_COMB_3D_FIFO_STAT 0x00008000
365#define FLD_WSS_DAT_AVAIL_STAT 0x00004000
366#define FLD_GS2_DAT_AVAIL_STAT 0x00002000
367#define FLD_GS1_DAT_AVAIL_STAT 0x00001000
368#define FLD_CC_DAT_AVAIL_STAT 0x00000800
369#define FLD_VPRES_CHANGE_STAT 0x00000400
370#define FLD_MV_CHANGE_STAT 0x00000200
371#define FLD_END_VBI_EVEN_STAT 0x00000100
372#define FLD_END_VBI_ODD_STAT 0x00000080
373#define FLD_FMT_CHANGE_STAT 0x00000040
374#define FLD_VSYNC_TRAIL_STAT 0x00000020
375#define FLD_HLOCK_CHANGE_STAT 0x00000010
376#define FLD_VLOCK_CHANGE_STAT 0x00000008
377#define FLD_CSC_LOCK_CHANGE_STAT 0x00000004
378#define FLD_SRC_FIFO_UFLOW_STAT 0x00000002
379#define FLD_SRC_FIFO_OFLOW_STAT 0x00000001
380
381/*****************************************************************************/
382#define LUMA_CTRL 0x414
383#define BRIGHTNESS_CTRL_BYTE 0x414
384#define CONTRAST_CTRL_BYTE 0x415
385#define LUMA_CTRL_BYTE_3 0x416
386#define FLD_LUMA_CORE_SEL 0x00c00000
387#define FLD_RANGE 0x00300000
388/* Reserved [19] */
389#define FLD_PEAK_EN 0x00040000
390#define FLD_PEAK_SEL 0x00030000
391#define FLD_CNTRST 0x0000ff00
392#define FLD_BRITE 0x000000ff
393
394/*****************************************************************************/
395#define HSCALE_CTRL 0x418
396#define FLD_HFILT 0x03000000
397#define FLD_HSCALE 0x00ffffff
398
399/*****************************************************************************/
400#define VSCALE_CTRL 0x41c
401#define FLD_LINE_AVG_DIS 0x01000000
402/* Reserved [23:20] */
403#define FLD_VS_INTRLACE 0x00080000
404#define FLD_VFILT 0x00070000
405/* Reserved [15:13] */
406#define FLD_VSCALE 0x00001fff
407
408/*****************************************************************************/
409#define CHROMA_CTRL 0x420
410#define USAT_CTRL_BYTE 0x420
411#define VSAT_CTRL_BYTE 0x421
412#define HUE_CTRL_BYTE 0x422
413#define FLD_C_LPF_EN 0x20000000
414#define FLD_CHR_DELAY 0x1c000000
415#define FLD_C_CORE_SEL 0x03000000
416#define FLD_HUE 0x00ff0000
417#define FLD_VSAT 0x0000ff00
418#define FLD_USAT 0x000000ff
419
420/*****************************************************************************/
421#define VBI_LINE_CTRL1 0x424
422#define FLD_VBI_MD_LINE4 0xff000000
423#define FLD_VBI_MD_LINE3 0x00ff0000
424#define FLD_VBI_MD_LINE2 0x0000ff00
425#define FLD_VBI_MD_LINE1 0x000000ff
426
427/*****************************************************************************/
428#define VBI_LINE_CTRL2 0x428
429#define FLD_VBI_MD_LINE8 0xff000000
430#define FLD_VBI_MD_LINE7 0x00ff0000
431#define FLD_VBI_MD_LINE6 0x0000ff00
432#define FLD_VBI_MD_LINE5 0x000000ff
433
434/*****************************************************************************/
435#define VBI_LINE_CTRL3 0x42c
436#define FLD_VBI_MD_LINE12 0xff000000
437#define FLD_VBI_MD_LINE11 0x00ff0000
438#define FLD_VBI_MD_LINE10 0x0000ff00
439#define FLD_VBI_MD_LINE9 0x000000ff
440
441/*****************************************************************************/
442#define VBI_LINE_CTRL4 0x430
443#define FLD_VBI_MD_LINE16 0xff000000
444#define FLD_VBI_MD_LINE15 0x00ff0000
445#define FLD_VBI_MD_LINE14 0x0000ff00
446#define FLD_VBI_MD_LINE13 0x000000ff
447
448/*****************************************************************************/
449#define VBI_LINE_CTRL5 0x434
450#define FLD_VBI_MD_LINE17 0x000000ff
451
452/*****************************************************************************/
453#define VBI_FC_CFG 0x438
454#define FLD_FC_ALT2 0xff000000
455#define FLD_FC_ALT1 0x00ff0000
456#define FLD_FC_ALT2_TYPE 0x0000f000
457#define FLD_FC_ALT1_TYPE 0x00000f00
458/* Reserved [7:1] */
459#define FLD_FC_SEARCH_MODE 0x00000001
460
461/*****************************************************************************/
462#define VBI_MISC_CFG1 0x43c
463#define FLD_TTX_PKTADRU 0xfff00000
464#define FLD_TTX_PKTADRL 0x000fff00
465/* Reserved [7:6] */
466#define FLD_MOJI_PACK_DIS 0x00000020
467#define FLD_VPS_DEC_DIS 0x00000010
468#define FLD_CRI_MARG_SCALE 0x0000000c
469#define FLD_EDGE_RESYNC_EN 0x00000002
470#define FLD_ADAPT_SLICE_DIS 0x00000001
471
472/*****************************************************************************/
473#define VBI_MISC_CFG2 0x440
474#define FLD_HAMMING_TYPE 0x0f000000
475/* Reserved [23:20] */
476#define FLD_WSS_FIFO_RST 0x00080000
477#define FLD_GS2_FIFO_RST 0x00040000
478#define FLD_GS1_FIFO_RST 0x00020000
479#define FLD_CC_FIFO_RST 0x00010000
480/* Reserved [15:12] */
481#define FLD_VBI3_SDID 0x00000f00
482#define FLD_VBI2_SDID 0x000000f0
483#define FLD_VBI1_SDID 0x0000000f
484
485/*****************************************************************************/
486#define VBI_PAY1 0x444
487#define FLD_GS1_FIFO_DAT 0xFF000000
488#define FLD_GS1_STAT 0x00FF0000
489#define FLD_CC_FIFO_DAT 0x0000FF00
490#define FLD_CC_STAT 0x000000FF
491
492/*****************************************************************************/
493#define VBI_PAY2 0x448
494#define FLD_WSS_FIFO_DAT 0xff000000
495#define FLD_WSS_STAT 0x00ff0000
496#define FLD_GS2_FIFO_DAT 0x0000ff00
497#define FLD_GS2_STAT 0x000000ff
498
499/*****************************************************************************/
500#define VBI_CUST1_CFG1 0x44c
501/* Reserved [31] */
502#define FLD_VBI1_CRIWIN 0x7f000000
503#define FLD_VBI1_SLICE_DIST 0x00f00000
504#define FLD_VBI1_BITINC 0x000fff00
505#define FLD_VBI1_HDELAY 0x000000ff
506
507/*****************************************************************************/
508#define VBI_CUST1_CFG2 0x450
509#define FLD_VBI1_FC_LENGTH 0x1f000000
510#define FLD_VBI1_FRAME_CODE 0x00ffffff
511
512/*****************************************************************************/
513#define VBI_CUST1_CFG3 0x454
514#define FLD_VBI1_HAM_EN 0x80000000
515#define FLD_VBI1_FIFO_MODE 0x70000000
516#define FLD_VBI1_FORMAT_TYPE 0x0f000000
517#define FLD_VBI1_PAYLD_LENGTH 0x00ff0000
518#define FLD_VBI1_CRI_LENGTH 0x0000f000
519#define FLD_VBI1_CRI_MARGIN 0x00000f00
520#define FLD_VBI1_CRI_TIME 0x000000ff
521
522/*****************************************************************************/
523#define VBI_CUST2_CFG1 0x458
524/* Reserved [31] */
525#define FLD_VBI2_CRIWIN 0x7f000000
526#define FLD_VBI2_SLICE_DIST 0x00f00000
527#define FLD_VBI2_BITINC 0x000fff00
528#define FLD_VBI2_HDELAY 0x000000ff
529
530/*****************************************************************************/
531#define VBI_CUST2_CFG2 0x45c
532#define FLD_VBI2_FC_LENGTH 0x1f000000
533#define FLD_VBI2_FRAME_CODE 0x00ffffff
534
535/*****************************************************************************/
536#define VBI_CUST2_CFG3 0x460
537#define FLD_VBI2_HAM_EN 0x80000000
538#define FLD_VBI2_FIFO_MODE 0x70000000
539#define FLD_VBI2_FORMAT_TYPE 0x0f000000
540#define FLD_VBI2_PAYLD_LENGTH 0x00ff0000
541#define FLD_VBI2_CRI_LENGTH 0x0000f000
542#define FLD_VBI2_CRI_MARGIN 0x00000f00
543#define FLD_VBI2_CRI_TIME 0x000000ff
544
545/*****************************************************************************/
546#define VBI_CUST3_CFG1 0x464
547/* Reserved [31] */
548#define FLD_VBI3_CRIWIN 0x7f000000
549#define FLD_VBI3_SLICE_DIST 0x00f00000
550#define FLD_VBI3_BITINC 0x000fff00
551#define FLD_VBI3_HDELAY 0x000000ff
552
553/*****************************************************************************/
554#define VBI_CUST3_CFG2 0x468
555#define FLD_VBI3_FC_LENGTH 0x1f000000
556#define FLD_VBI3_FRAME_CODE 0x00ffffff
557
558/*****************************************************************************/
559#define VBI_CUST3_CFG3 0x46c
560#define FLD_VBI3_HAM_EN 0x80000000
561#define FLD_VBI3_FIFO_MODE 0x70000000
562#define FLD_VBI3_FORMAT_TYPE 0x0f000000
563#define FLD_VBI3_PAYLD_LENGTH 0x00ff0000
564#define FLD_VBI3_CRI_LENGTH 0x0000f000
565#define FLD_VBI3_CRI_MARGIN 0x00000f00
566#define FLD_VBI3_CRI_TIME 0x000000ff
567
568/*****************************************************************************/
569#define HORIZ_TIM_CTRL 0x470
570#define FLD_BGDEL_CNT 0xff000000
571/* Reserved [23:22] */
572#define FLD_HACTIVE_CNT 0x003ff000
573/* Reserved [11:10] */
574#define FLD_HBLANK_CNT 0x000003ff
575
576/*****************************************************************************/
577#define VERT_TIM_CTRL 0x474
578#define FLD_V656BLANK_CNT 0xff000000
579/* Reserved [23:22] */
580#define FLD_VACTIVE_CNT 0x003ff000
581/* Reserved [11:10] */
582#define FLD_VBLANK_CNT 0x000003ff
583
584/*****************************************************************************/
585#define SRC_COMB_CFG 0x478
586#define FLD_CCOMB_2LN_CHECK 0x80000000
587#define FLD_CCOMB_3LN_EN 0x40000000
588#define FLD_CCOMB_2LN_EN 0x20000000
589#define FLD_CCOMB_3D_EN 0x10000000
590/* Reserved [27] */
591#define FLD_LCOMB_3LN_EN 0x04000000
592#define FLD_LCOMB_2LN_EN 0x02000000
593#define FLD_LCOMB_3D_EN 0x01000000
594#define FLD_LUMA_LPF_SEL 0x00c00000
595#define FLD_UV_LPF_SEL 0x00300000
596#define FLD_BLEND_SLOPE 0x000f0000
597#define FLD_CCOMB_REDUCE_EN 0x00008000
598/* Reserved [14:10] */
599#define FLD_SRC_DECIM_RATIO 0x000003ff
600
601/*****************************************************************************/
602#define CHROMA_VBIOFF_CFG 0x47c
603#define FLD_VBI_VOFFSET 0x1f000000
604/* Reserved [23:20] */
605#define FLD_SC_STEP 0x000fffff
606
607/*****************************************************************************/
608#define FIELD_COUNT 0x480
609#define FLD_FIELD_COUNT_FLD 0x000003ff
610
611/*****************************************************************************/
612#define MISC_TIM_CTRL 0x484
613#define FLD_DEBOUNCE_COUNT 0xc0000000
614#define FLD_VT_LINE_CNT_HYST 0x30000000
615/* Reserved [27] */
616#define FLD_AFD_STAT 0x07ff0000
617#define FLD_VPRES_VERT_EN 0x00008000
618/* Reserved [14:12] */
619#define FLD_HR32 0x00000800
620#define FLD_TDALGN 0x00000400
621#define FLD_TDFIELD 0x00000200
622/* Reserved [8:6] */
623#define FLD_TEMPDEC 0x0000003f
624
625/*****************************************************************************/
626#define DFE_CTRL1 0x488
627#define FLD_CLAMP_AUTO_EN 0x80000000
628#define FLD_AGC_AUTO_EN 0x40000000
629#define FLD_VGA_CRUSH_EN 0x20000000
630#define FLD_VGA_AUTO_EN 0x10000000
631#define FLD_VBI_GATE_EN 0x08000000
632#define FLD_CLAMP_LEVEL 0x07000000
633/* Reserved [23:22] */
634#define FLD_CLAMP_SKIP_CNT 0x00300000
635#define FLD_AGC_GAIN 0x000fff00
636/* Reserved [7:6] */
637#define FLD_VGA_GAIN 0x0000003f
638
639/*****************************************************************************/
640#define DFE_CTRL2 0x48c
641#define FLD_VGA_ACQUIRE_RANGE 0x00ff0000
642#define FLD_VGA_TRACK_RANGE 0x0000ff00
643#define FLD_VGA_SYNC 0x000000ff
644
645/*****************************************************************************/
646#define DFE_CTRL3 0x490
647#define FLD_BP_PERCENT 0xff000000
648#define FLD_DFT_THRESHOLD 0x00ff0000
649/* Reserved [15:12] */
650#define FLD_SYNC_WIDTH_SEL 0x00000600
651#define FLD_BP_LOOP_GAIN 0x00000300
652#define FLD_SYNC_LOOP_GAIN 0x000000c0
653/* Reserved [5:4] */
654#define FLD_AGC_LOOP_GAIN 0x0000000c
655#define FLD_DCC_LOOP_GAIN 0x00000003
656
657/*****************************************************************************/
658#define PLL_CTRL 0x494
659#define FLD_PLL_KD 0xff000000
660#define FLD_PLL_KI 0x00ff0000
661#define FLD_PLL_MAX_OFFSET 0x0000ffff
662
663/*****************************************************************************/
664#define HTL_CTRL 0x498
665/* Reserved [31:24] */
666#define FLD_AUTO_LOCK_SPD 0x00080000
667#define FLD_MAN_FAST_LOCK 0x00040000
668#define FLD_HTL_15K_EN 0x00020000
669#define FLD_HTL_500K_EN 0x00010000
670#define FLD_HTL_KD 0x0000ff00
671#define FLD_HTL_KI 0x000000ff
672
673/*****************************************************************************/
674#define COMB_CTRL 0x49c
675#define FLD_COMB_PHASE_LIMIT 0xff000000
676#define FLD_CCOMB_ERR_LIMIT 0x00ff0000
677#define FLD_LUMA_THRESHOLD 0x0000ff00
678#define FLD_LCOMB_ERR_LIMIT 0x000000ff
679
680/*****************************************************************************/
681#define CRUSH_CTRL 0x4a0
682#define FLD_WTW_EN 0x00400000
683#define FLD_CRUSH_FREQ 0x00200000
684#define FLD_MAJ_SEL_EN 0x00100000
685#define FLD_MAJ_SEL 0x000c0000
686/* Reserved [17:15] */
687#define FLD_SYNC_TIP_REDUCE 0x00007e00
688/* Reserved [8:6] */
689#define FLD_SYNC_TIP_INC 0x0000003f
690
691/*****************************************************************************/
692#define SOFT_RST_CTRL 0x4a4
693#define FLD_VD_SOFT_RST 0x00008000
694/* Reserved [14:12] */
695#define FLD_REG_RST_MSK 0x00000800
696#define FLD_VOF_RST_MSK 0x00000400
697#define FLD_MVDET_RST_MSK 0x00000200
698#define FLD_VBI_RST_MSK 0x00000100
699#define FLD_SCALE_RST_MSK 0x00000080
700#define FLD_CHROMA_RST_MSK 0x00000040
701#define FLD_LUMA_RST_MSK 0x00000020
702#define FLD_VTG_RST_MSK 0x00000010
703#define FLD_YCSEP_RST_MSK 0x00000008
704#define FLD_SRC_RST_MSK 0x00000004
705#define FLD_DFE_RST_MSK 0x00000002
706/* Reserved [0] */
707
708/*****************************************************************************/
709#define MV_DT_CTRL1 0x4a8
710/* Reserved [31:29] */
711#define FLD_PSP_STOP_LINE 0x1f000000
712/* Reserved [23:21] */
713#define FLD_PSP_STRT_LINE 0x001f0000
714/* Reserved [15] */
715#define FLD_PSP_LLIMW 0x00007f00
716/* Reserved [7] */
717#define FLD_PSP_ULIMW 0x0000007f
718
719/*****************************************************************************/
720#define MV_DT_CTRL2 0x4aC
721#define FLD_CS_STOPWIN 0xff000000
722#define FLD_CS_STRTWIN 0x00ff0000
723#define FLD_CS_WIDTH 0x0000ff00
724#define FLD_PSP_SPEC_VAL 0x000000ff
725
726/*****************************************************************************/
727#define MV_DT_CTRL3 0x4B0
728#define FLD_AUTO_RATE_DIS 0x80000000
729#define FLD_HLOCK_DIS 0x40000000
730#define FLD_SEL_FIELD_CNT 0x20000000
731#define FLD_CS_TYPE2_SEL 0x10000000
732#define FLD_CS_LINE_THRSH_SEL 0x08000000
733#define FLD_CS_ATHRESH_SEL 0x04000000
734#define FLD_PSP_SPEC_SEL 0x02000000
735#define FLD_PSP_LINES_SEL 0x01000000
736#define FLD_FIELD_CNT 0x00f00000
737#define FLD_CS_TYPE2_CNT 0x000fc000
738#define FLD_CS_LINE_CNT 0x00003f00
739#define FLD_CS_ATHRESH_LEV 0x000000ff
740
741/*****************************************************************************/
742#define CHIP_VERSION 0x4b4
743/* Cx231xx redefine */
744#define VERSION 0x4b4
745#define FLD_REV_ID 0x000000ff
746
747/*****************************************************************************/
748#define MISC_DIAG_CTRL 0x4b8
749/* Reserved [31:24] */
750#define FLD_SC_CONVERGE_THRESH 0x00ff0000
751#define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00
752#define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff
753
754/*****************************************************************************/
755#define VBI_PASS_CTRL 0x4bc
756#define FLD_VBI_PASS_MD 0x00200000
757#define FLD_VBI_SETUP_DIS 0x00100000
758#define FLD_PASS_LINE_CTRL 0x000fffff
759
760/*****************************************************************************/
761/* Cx231xx redefine */
762#define VCR_DET_CTRL 0x4c0
763#define FLD_EN_FIELD_PHASE_DET 0x80000000
764#define FLD_EN_HEAD_SW_DET 0x40000000
765#define FLD_FIELD_PHASE_LENGTH 0x01ff0000
766/* Reserved [29:25] */
767#define FLD_FIELD_PHASE_DELAY 0x0000ff00
768#define FLD_FIELD_PHASE_LIMIT 0x000000f0
769#define FLD_HEAD_SW_DET_LIMIT 0x0000000f
770
771/*****************************************************************************/
772#define DL_CTL 0x800
773#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */
774#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */
775#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */
776#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */
777/* Reserved [31:5] */
778#define FLD_START_8051 0x10000000
779#define FLD_DL_ENABLE 0x08000000
780#define FLD_DL_AUTO_INC 0x04000000
781#define FLD_DL_MAP 0x03000000
782
783/*****************************************************************************/
784#define STD_DET_STATUS 0x804
785#define FLD_SPARE_STATUS1 0xff000000
786#define FLD_SPARE_STATUS0 0x00ff0000
787#define FLD_MOD_DET_STATUS1 0x0000ff00
788#define FLD_MOD_DET_STATUS0 0x000000ff
789
790/*****************************************************************************/
791#define AUD_BUILD_NUM 0x806
792#define AUD_VER_NUM 0x807
793#define STD_DET_CTL 0x808
794#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */
795#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
796#define FLD_SPARE_CTL0 0xff000000
797#define FLD_DIS_DBX 0x00800000
798#define FLD_DIS_BTSC 0x00400000
799#define FLD_DIS_NICAM_A2 0x00200000
800#define FLD_VIDEO_PRESENT 0x00100000
801#define FLD_DW8051_VIDEO_FORMAT 0x000f0000
802#define FLD_PREF_DEC_MODE 0x0000ff00
803#define FLD_AUD_CONFIG 0x000000ff
804
805/*****************************************************************************/
806#define DW8051_INT 0x80c
807#define FLD_VIDEO_PRESENT_CHANGE 0x80000000
808#define FLD_VIDEO_CHANGE 0x40000000
809#define FLD_RDS_READY 0x20000000
810#define FLD_AC97_INT 0x10000000
811#define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000
812#define FLD_NICAM_LOCK 0x04000000
813#define FLD_NICAM_UNLOCK 0x02000000
814#define FLD_DFT4_TH_CMP 0x01000000
815/* Reserved [23:22] */
816#define FLD_LOCK_IND_INT 0x00200000
817#define FLD_DFT3_TH_CMP 0x00100000
818#define FLD_DFT2_TH_CMP 0x00080000
819#define FLD_DFT1_TH_CMP 0x00040000
820#define FLD_FM2_DFT_TH_CMP 0x00020000
821#define FLD_FM1_DFT_TH_CMP 0x00010000
822#define FLD_VIDEO_PRESENT_EN 0x00008000
823#define FLD_VIDEO_CHANGE_EN 0x00004000
824#define FLD_RDS_READY_EN 0x00002000
825#define FLD_AC97_INT_EN 0x00001000
826#define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800
827#define FLD_NICAM_LOCK_EN 0x00000400
828#define FLD_NICAM_UNLOCK_EN 0x00000200
829#define FLD_DFT4_TH_CMP_EN 0x00000100
830/* Reserved [7] */
831#define FLD_DW8051_INT6_CTL1 0x00000040
832#define FLD_DW8051_INT5_CTL1 0x00000020
833#define FLD_DW8051_INT4_CTL1 0x00000010
834#define FLD_DW8051_INT3_CTL1 0x00000008
835#define FLD_DW8051_INT2_CTL1 0x00000004
836#define FLD_DW8051_INT1_CTL1 0x00000002
837#define FLD_DW8051_INT0_CTL1 0x00000001
838
839/*****************************************************************************/
840#define GENERAL_CTL 0x810
841#define FLD_RDS_INT 0x80000000
842#define FLD_NBER_INT 0x40000000
843#define FLD_NLL_INT 0x20000000
844#define FLD_IFL_INT 0x10000000
845#define FLD_FDL_INT 0x08000000
846#define FLD_AFC_INT 0x04000000
847#define FLD_AMC_INT 0x02000000
848#define FLD_AC97_INT_CTL 0x01000000
849#define FLD_RDS_INT_DIS 0x00800000
850#define FLD_NBER_INT_DIS 0x00400000
851#define FLD_NLL_INT_DIS 0x00200000
852#define FLD_IFL_INT_DIS 0x00100000
853#define FLD_FDL_INT_DIS 0x00080000
854#define FLD_FC_INT_DIS 0x00040000
855#define FLD_AMC_INT_DIS 0x00020000
856#define FLD_AC97_INT_DIS 0x00010000
857#define FLD_REV_NUM 0x0000ff00
858/* Reserved [7:5] */
859#define FLD_DBX_SOFT_RESET_REG 0x00000010
860#define FLD_AD_SOFT_RESET_REG 0x00000008
861#define FLD_SRC_SOFT_RESET_REG 0x00000004
862#define FLD_CDMOD_SOFT_RESET 0x00000002
863#define FLD_8051_SOFT_RESET 0x00000001
864
865/*****************************************************************************/
866#define AAGC_CTL 0x814
867#define FLD_AFE_12DB_EN 0x80000000
868#define FLD_AAGC_DEFAULT_EN 0x40000000
869#define FLD_AAGC_DEFAULT 0x3f000000
870/* Reserved [23] */
871#define FLD_AAGC_GAIN 0x00600000
872#define FLD_AAGC_TH 0x001f0000
873/* Reserved [15:14] */
874#define FLD_AAGC_HYST2 0x00003f00
875/* Reserved [7:6] */
876#define FLD_AAGC_HYST1 0x0000003f
877
878/*****************************************************************************/
879#define IF_SRC_CTL 0x818
880#define FLD_DBX_BYPASS 0x80000000
881/* Reserved [30:25] */
882#define FLD_IF_SRC_MODE 0x01000000
883/* Reserved [23:18] */
884#define FLD_IF_SRC_PHASE_INC 0x0001ffff
885
886/*****************************************************************************/
887#define ANALOG_DEMOD_CTL 0x81c
888#define FLD_ROT1_PHACC_PROG 0xffff0000
889/* Reserved [15] */
890#define FLD_FM1_DELAY_FIX 0x00007000
891#define FLD_PDF4_SHIFT 0x00000c00
892#define FLD_PDF3_SHIFT 0x00000300
893#define FLD_PDF2_SHIFT 0x000000c0
894#define FLD_PDF1_SHIFT 0x00000030
895#define FLD_FMBYPASS_MODE2 0x00000008
896#define FLD_FMBYPASS_MODE1 0x00000004
897#define FLD_NICAM_MODE 0x00000002
898#define FLD_BTSC_FMRADIO_MODE 0x00000001
899
900/*****************************************************************************/
901#define ROT_FREQ_CTL 0x820
902#define FLD_ROT3_PHACC_PROG 0xffff0000
903#define FLD_ROT2_PHACC_PROG 0x0000ffff
904
905/*****************************************************************************/
906#define FM_CTL 0x824
907#define FLD_FM2_DC_FB_SHIFT 0xf0000000
908#define FLD_FM2_DC_INT_SHIFT 0x0f000000
909#define FLD_FM2_AFC_RESET 0x00800000
910#define FLD_FM2_DC_PASS_IN 0x00400000
911#define FLD_FM2_DAGC_SHIFT 0x00380000
912#define FLD_FM2_CORDIC_SHIFT 0x00070000
913#define FLD_FM1_DC_FB_SHIFT 0x0000f000
914#define FLD_FM1_DC_INT_SHIFT 0x00000f00
915#define FLD_FM1_AFC_RESET 0x00000080
916#define FLD_FM1_DC_PASS_IN 0x00000040
917#define FLD_FM1_DAGC_SHIFT 0x00000038
918#define FLD_FM1_CORDIC_SHIFT 0x00000007
919
920/*****************************************************************************/
921#define LPF_PDF_CTL 0x828
922/* Reserved [31:30] */
923#define FLD_LPF32_SHIFT1 0x30000000
924#define FLD_LPF32_SHIFT2 0x0c000000
925#define FLD_LPF160_SHIFTA 0x03000000
926#define FLD_LPF160_SHIFTB 0x00c00000
927#define FLD_LPF160_SHIFTC 0x00300000
928#define FLD_LPF32_COEF_SEL2 0x000c0000
929#define FLD_LPF32_COEF_SEL1 0x00030000
930#define FLD_LPF160_COEF_SELC 0x0000c000
931#define FLD_LPF160_COEF_SELB 0x00003000
932#define FLD_LPF160_COEF_SELA 0x00000c00
933#define FLD_LPF160_IN_EN_REG 0x00000300
934#define FLD_PDF4_PDF_SEL 0x000000c0
935#define FLD_PDF3_PDF_SEL 0x00000030
936#define FLD_PDF2_PDF_SEL 0x0000000c
937#define FLD_PDF1_PDF_SEL 0x00000003
938
939/*****************************************************************************/
940#define DFT1_CTL1 0x82c
941#define FLD_DFT1_DWELL 0xffff0000
942#define FLD_DFT1_FREQ 0x0000ffff
943
944/*****************************************************************************/
945#define DFT1_CTL2 0x830
946#define FLD_DFT1_THRESHOLD 0xffffff00
947#define FLD_DFT1_CMP_CTL 0x00000080
948#define FLD_DFT1_AVG 0x00000070
949/* Reserved [3:1] */
950#define FLD_DFT1_START 0x00000001
951
952/*****************************************************************************/
953#define DFT1_STATUS 0x834
954#define FLD_DFT1_DONE 0x80000000
955#define FLD_DFT1_TH_CMP_STAT 0x40000000
956#define FLD_DFT1_RESULT 0x3fffffff
957
958/*****************************************************************************/
959#define DFT2_CTL1 0x838
960#define FLD_DFT2_DWELL 0xffff0000
961#define FLD_DFT2_FREQ 0x0000ffff
962
963/*****************************************************************************/
964#define DFT2_CTL2 0x83C
965#define FLD_DFT2_THRESHOLD 0xffffff00
966#define FLD_DFT2_CMP_CTL 0x00000080
967#define FLD_DFT2_AVG 0x00000070
968/* Reserved [3:1] */
969#define FLD_DFT2_START 0x00000001
970
971/*****************************************************************************/
972#define DFT2_STATUS 0x840
973#define FLD_DFT2_DONE 0x80000000
974#define FLD_DFT2_TH_CMP_STAT 0x40000000
975#define FLD_DFT2_RESULT 0x3fffffff
976
977/*****************************************************************************/
978#define DFT3_CTL1 0x844
979#define FLD_DFT3_DWELL 0xffff0000
980#define FLD_DFT3_FREQ 0x0000ffff
981
982/*****************************************************************************/
983#define DFT3_CTL2 0x848
984#define FLD_DFT3_THRESHOLD 0xffffff00
985#define FLD_DFT3_CMP_CTL 0x00000080
986#define FLD_DFT3_AVG 0x00000070
987/* Reserved [3:1] */
988#define FLD_DFT3_START 0x00000001
989
990/*****************************************************************************/
991#define DFT3_STATUS 0x84c
992#define FLD_DFT3_DONE 0x80000000
993#define FLD_DFT3_TH_CMP_STAT 0x40000000
994#define FLD_DFT3_RESULT 0x3fffffff
995
996/*****************************************************************************/
997#define DFT4_CTL1 0x850
998#define FLD_DFT4_DWELL 0xffff0000
999#define FLD_DFT4_FREQ 0x0000ffff
1000
1001/*****************************************************************************/
1002#define DFT4_CTL2 0x854
1003#define FLD_DFT4_THRESHOLD 0xffffff00
1004#define FLD_DFT4_CMP_CTL 0x00000080
1005#define FLD_DFT4_AVG 0x00000070
1006/* Reserved [3:1] */
1007#define FLD_DFT4_START 0x00000001
1008
1009/*****************************************************************************/
1010#define DFT4_STATUS 0x858
1011#define FLD_DFT4_DONE 0x80000000
1012#define FLD_DFT4_TH_CMP_STAT 0x40000000
1013#define FLD_DFT4_RESULT 0x3fffffff
1014
1015/*****************************************************************************/
1016#define AM_MTS_DET 0x85c
1017#define FLD_AM_MTS_MODE 0x80000000
1018/* Reserved [30:26] */
1019#define FLD_AM_SUB 0x02000000
1020#define FLD_AM_GAIN_EN 0x01000000
1021/* Reserved [23:16] */
1022#define FLD_AMMTS_GAIN_SCALE 0x0000e000
1023#define FLD_MTS_PDF_SHIFT 0x00001800
1024#define FLD_AM_REG_GAIN 0x00000700
1025#define FLD_AGC_REF 0x000000ff
1026
1027/*****************************************************************************/
1028#define ANALOG_MUX_CTL 0x860
1029/* Reserved [31:29] */
1030#define FLD_MUX21_SEL 0x10000000
1031#define FLD_MUX20_SEL 0x08000000
1032#define FLD_MUX19_SEL 0x04000000
1033#define FLD_MUX18_SEL 0x02000000
1034#define FLD_MUX17_SEL 0x01000000
1035#define FLD_MUX16_SEL 0x00800000
1036#define FLD_MUX15_SEL 0x00400000
1037#define FLD_MUX14_SEL 0x00300000
1038#define FLD_MUX13_SEL 0x000C0000
1039#define FLD_MUX12_SEL 0x00020000
1040#define FLD_MUX11_SEL 0x00018000
1041#define FLD_MUX10_SEL 0x00004000
1042#define FLD_MUX9_SEL 0x00002000
1043#define FLD_MUX8_SEL 0x00001000
1044#define FLD_MUX7_SEL 0x00000800
1045#define FLD_MUX6_SEL 0x00000600
1046#define FLD_MUX5_SEL 0x00000100
1047#define FLD_MUX4_SEL 0x000000c0
1048#define FLD_MUX3_SEL 0x00000030
1049#define FLD_MUX2_SEL 0x0000000c
1050#define FLD_MUX1_SEL 0x00000003
1051
1052/*****************************************************************************/
1053/* Cx231xx redefine */
1054#define DPLL_CTRL1 0x864
1055#define DIG_PLL_CTL1 0x864
1056
1057#define FLD_PLL_STATUS 0x07000000
1058#define FLD_BANDWIDTH_SELECT 0x00030000
1059#define FLD_PLL_SHIFT_REG 0x00007000
1060#define FLD_PHASE_SHIFT 0x000007ff
1061
1062/*****************************************************************************/
1063/* Cx231xx redefine */
1064#define DPLL_CTRL2 0x868
1065#define DIG_PLL_CTL2 0x868
1066#define FLD_PLL_UNLOCK_THR 0xff000000
1067#define FLD_PLL_LOCK_THR 0x00ff0000
1068/* Reserved [15:8] */
1069#define FLD_AM_PDF_SEL2 0x000000c0
1070#define FLD_AM_PDF_SEL1 0x00000030
1071#define FLD_DPLL_FSM_CTRL 0x0000000c
1072/* Reserved [1] */
1073#define FLD_PLL_PILOT_DET 0x00000001
1074
1075/*****************************************************************************/
1076/* Cx231xx redefine */
1077#define DPLL_CTRL3 0x86c
1078#define DIG_PLL_CTL3 0x86c
1079#define FLD_DISABLE_LOOP 0x01000000
1080#define FLD_A1_DS1_SEL 0x000c0000
1081#define FLD_A1_DS2_SEL 0x00030000
1082#define FLD_A1_KI 0x0000ff00
1083#define FLD_A1_KD 0x000000ff
1084
1085/*****************************************************************************/
1086/* Cx231xx redefine */
1087#define DPLL_CTRL4 0x870
1088#define DIG_PLL_CTL4 0x870
1089#define FLD_A2_DS1_SEL 0x000c0000
1090#define FLD_A2_DS2_SEL 0x00030000
1091#define FLD_A2_KI 0x0000ff00
1092#define FLD_A2_KD 0x000000ff
1093
1094/*****************************************************************************/
1095/* Cx231xx redefine */
1096#define DPLL_CTRL5 0x874
1097#define DIG_PLL_CTL5 0x874
1098#define FLD_TRK_DS1_SEL 0x000c0000
1099#define FLD_TRK_DS2_SEL 0x00030000
1100#define FLD_TRK_KI 0x0000ff00
1101#define FLD_TRK_KD 0x000000ff
1102
1103/*****************************************************************************/
1104#define DEEMPH_GAIN_CTL 0x878
1105#define FLD_DEEMPH2_GAIN 0xFFFF0000
1106#define FLD_DEEMPH1_GAIN 0x0000FFFF
1107
1108/*****************************************************************************/
1109/* Cx231xx redefine */
1110#define DEEMPH_COEFF1 0x87c
1111#define DEEMPH_COEF1 0x87c
1112#define FLD_DEEMPH_B0 0xffff0000
1113#define FLD_DEEMPH_A0 0x0000ffff
1114
1115/*****************************************************************************/
1116/* Cx231xx redefine */
1117#define DEEMPH_COEFF2 0x880
1118#define DEEMPH_COEF2 0x880
1119#define FLD_DEEMPH_B1 0xFFFF0000
1120#define FLD_DEEMPH_A1 0x0000FFFF
1121
1122/*****************************************************************************/
1123#define DBX1_CTL1 0x884
1124#define FLD_DBX1_WBE_GAIN 0xffff0000
1125#define FLD_DBX1_IN_GAIN 0x0000ffff
1126
1127/*****************************************************************************/
1128#define DBX1_CTL2 0x888
1129#define FLD_DBX1_SE_BYPASS 0xffff0000
1130#define FLD_DBX1_SE_GAIN 0x0000ffff
1131
1132/*****************************************************************************/
1133#define DBX1_RMS_SE 0x88C
1134#define FLD_DBX1_RMS_WBE 0xffff0000
1135#define FLD_DBX1_RMS_SE_FLD 0x0000ffff
1136
1137/*****************************************************************************/
1138#define DBX2_CTL1 0x890
1139#define FLD_DBX2_WBE_GAIN 0xffff0000
1140#define FLD_DBX2_IN_GAIN 0x0000ffff
1141
1142/*****************************************************************************/
1143#define DBX2_CTL2 0x894
1144#define FLD_DBX2_SE_BYPASS 0xffff0000
1145#define FLD_DBX2_SE_GAIN 0x0000ffff
1146
1147/*****************************************************************************/
1148#define DBX2_RMS_SE 0x898
1149#define FLD_DBX2_RMS_WBE 0xffff0000
1150#define FLD_DBX2_RMS_SE_FLD 0x0000ffff
1151
1152/*****************************************************************************/
1153#define AM_FM_DIFF 0x89c
1154/* Reserved [31] */
1155#define FLD_FM_DIFF_OUT 0x7fff0000
1156/* Reserved [15] */
1157#define FLD_AM_DIFF_OUT 0x00007fff
1158
1159/*****************************************************************************/
1160#define NICAM_FAW 0x8a0
1161#define FLD_FAWDETWINEND 0xFc000000
1162#define FLD_FAWDETWINSTR 0x03ff0000
1163/* Reserved [15:12] */
1164#define FLD_FAWDETTHRSHLD3 0x00000f00
1165#define FLD_FAWDETTHRSHLD2 0x000000f0
1166#define FLD_FAWDETTHRSHLD1 0x0000000f
1167
1168/*****************************************************************************/
1169/* Cx231xx redefine */
1170#define DEEMPH_GAIN 0x8a4
1171#define NICAM_DEEMPHGAIN 0x8a4
1172/* Reserved [31:18] */
1173#define FLD_DEEMPHGAIN 0x0003ffff
1174
1175/*****************************************************************************/
1176/* Cx231xx redefine */
1177#define DEEMPH_NUMER1 0x8a8
1178#define NICAM_DEEMPHNUMER1 0x8a8
1179/* Reserved [31:18] */
1180#define FLD_DEEMPHNUMER1 0x0003ffff
1181
1182/*****************************************************************************/
1183/* Cx231xx redefine */
1184#define DEEMPH_NUMER2 0x8ac
1185#define NICAM_DEEMPHNUMER2 0x8ac
1186/* Reserved [31:18] */
1187#define FLD_DEEMPHNUMER2 0x0003ffff
1188
1189/*****************************************************************************/
1190/* Cx231xx redefine */
1191#define DEEMPH_DENOM1 0x8b0
1192#define NICAM_DEEMPHDENOM1 0x8b0
1193/* Reserved [31:18] */
1194#define FLD_DEEMPHDENOM1 0x0003ffff
1195
1196/*****************************************************************************/
1197/* Cx231xx redefine */
1198#define DEEMPH_DENOM2 0x8b4
1199#define NICAM_DEEMPHDENOM2 0x8b4
1200/* Reserved [31:18] */
1201#define FLD_DEEMPHDENOM2 0x0003ffff
1202
1203/*****************************************************************************/
1204#define NICAM_ERRLOG_CTL1 0x8B8
1205/* Reserved [31:28] */
1206#define FLD_ERRINTRPTTHSHLD1 0x0fff0000
1207/* Reserved [15:12] */
1208#define FLD_ERRLOGPERIOD 0x00000fff
1209
1210/*****************************************************************************/
1211#define NICAM_ERRLOG_CTL2 0x8bc
1212/* Reserved [31:28] */
1213#define FLD_ERRINTRPTTHSHLD3 0x0fff0000
1214/* Reserved [15:12] */
1215#define FLD_ERRINTRPTTHSHLD2 0x00000fff
1216
1217/*****************************************************************************/
1218#define NICAM_ERRLOG_STS1 0x8c0
1219/* Reserved [31:28] */
1220#define FLD_ERRLOG2 0x0fff0000
1221/* Reserved [15:12] */
1222#define FLD_ERRLOG1 0x00000fff
1223
1224/*****************************************************************************/
1225#define NICAM_ERRLOG_STS2 0x8c4
1226/* Reserved [31:12] */
1227#define FLD_ERRLOG3 0x00000fff
1228
1229/*****************************************************************************/
1230#define NICAM_STATUS 0x8c8
1231/* Reserved [31:20] */
1232#define FLD_NICAM_CIB 0x000c0000
1233#define FLD_NICAM_LOCK_STAT 0x00020000
1234#define FLD_NICAM_MUTE 0x00010000
1235#define FLD_NICAMADDIT_DATA 0x0000ffe0
1236#define FLD_NICAMCNTRL 0x0000001f
1237
1238/*****************************************************************************/
1239#define DEMATRIX_CTL 0x8cc
1240#define FLD_AC97_IN_SHIFT 0xf0000000
1241#define FLD_I2S_IN_SHIFT 0x0f000000
1242#define FLD_DEMATRIX_SEL_CTL 0x00ff0000
1243/* Reserved [15:11] */
1244#define FLD_DMTRX_BYPASS 0x00000400
1245#define FLD_DEMATRIX_MODE 0x00000300
1246/* Reserved [7:6] */
1247#define FLD_PH_DBX_SEL 0x00000020
1248#define FLD_PH_CH_SEL 0x00000010
1249#define FLD_PHASE_FIX 0x0000000f
1250
1251/*****************************************************************************/
1252#define PATH1_CTL1 0x8d0
1253/* Reserved [31:29] */
1254#define FLD_PATH1_MUTE_CTL 0x1f000000
1255/* Reserved [23:22] */
1256#define FLD_PATH1_AVC_CG 0x00300000
1257#define FLD_PATH1_AVC_RT 0x000f0000
1258#define FLD_PATH1_AVC_AT 0x0000f000
1259#define FLD_PATH1_AVC_STEREO 0x00000800
1260#define FLD_PATH1_AVC_CR 0x00000700
1261#define FLD_PATH1_AVC_RMS_CON 0x000000f0
1262#define FLD_PATH1_SEL_CTL 0x0000000f
1263
1264/*****************************************************************************/
1265#define PATH1_VOL_CTL 0x8d4
1266#define FLD_PATH1_AVC_THRESHOLD 0x7fff0000
1267#define FLD_PATH1_BAL_LEFT 0x00008000
1268#define FLD_PATH1_BAL_LEVEL 0x00007f00
1269#define FLD_PATH1_VOLUME 0x000000ff
1270
1271/*****************************************************************************/
1272#define PATH1_EQ_CTL 0x8d8
1273/* Reserved [31:30] */
1274#define FLD_PATH1_EQ_TREBLE_VOL 0x3f000000
1275/* Reserved [23:22] */
1276#define FLD_PATH1_EQ_MID_VOL 0x003f0000
1277/* Reserved [15:14] */
1278#define FLD_PATH1_EQ_BASS_VOL 0x00003f00
1279/* Reserved [7:1] */
1280#define FLD_PATH1_EQ_BAND_SEL 0x00000001
1281
1282/*****************************************************************************/
1283#define PATH1_SC_CTL 0x8dc
1284#define FLD_PATH1_SC_THRESHOLD 0x7fff0000
1285#define FLD_PATH1_SC_RT 0x0000f000
1286#define FLD_PATH1_SC_AT 0x00000f00
1287#define FLD_PATH1_SC_STEREO 0x00000080
1288#define FLD_PATH1_SC_CR 0x00000070
1289#define FLD_PATH1_SC_RMS_CON 0x0000000f
1290
1291/*****************************************************************************/
1292#define PATH2_CTL1 0x8e0
1293/* Reserved [31:26] */
1294#define FLD_PATH2_MUTE_CTL 0x03000000
1295/* Reserved [23:22] */
1296#define FLD_PATH2_AVC_CG 0x00300000
1297#define FLD_PATH2_AVC_RT 0x000f0000
1298#define FLD_PATH2_AVC_AT 0x0000f000
1299#define FLD_PATH2_AVC_STEREO 0x00000800
1300#define FLD_PATH2_AVC_CR 0x00000700
1301#define FLD_PATH2_AVC_RMS_CON 0x000000f0
1302#define FLD_PATH2_SEL_CTL 0x0000000f
1303
1304/*****************************************************************************/
1305#define PATH2_VOL_CTL 0x8e4
1306#define FLD_PATH2_AVC_THRESHOLD 0xffff0000
1307#define FLD_PATH2_BAL_LEFT 0x00008000
1308#define FLD_PATH2_BAL_LEVEL 0x00007f00
1309#define FLD_PATH2_VOLUME 0x000000ff
1310
1311/*****************************************************************************/
1312#define PATH2_EQ_CTL 0x8e8
1313/* Reserved [31:30] */
1314#define FLD_PATH2_EQ_TREBLE_VOL 0x3f000000
1315/* Reserved [23:22] */
1316#define FLD_PATH2_EQ_MID_VOL 0x003f0000
1317/* Reserved [15:14] */
1318#define FLD_PATH2_EQ_BASS_VOL 0x00003f00
1319/* Reserved [7:1] */
1320#define FLD_PATH2_EQ_BAND_SEL 0x00000001
1321
1322/*****************************************************************************/
1323#define PATH2_SC_CTL 0x8eC
1324#define FLD_PATH2_SC_THRESHOLD 0xffff0000
1325#define FLD_PATH2_SC_RT 0x0000f000
1326#define FLD_PATH2_SC_AT 0x00000f00
1327#define FLD_PATH2_SC_STEREO 0x00000080
1328#define FLD_PATH2_SC_CR 0x00000070
1329#define FLD_PATH2_SC_RMS_CON 0x0000000f
1330
1331/*****************************************************************************/
1332#define SRC_CTL 0x8f0
1333#define FLD_SRC_STATUS 0xffffff00
1334#define FLD_FIFO_LF_EN 0x000000fc
1335#define FLD_BYPASS_LI 0x00000002
1336#define FLD_BYPASS_PF 0x00000001
1337
1338/*****************************************************************************/
1339#define SRC_LF_COEF 0x8f4
1340#define FLD_LOOP_FILTER_COEF2 0xffff0000
1341#define FLD_LOOP_FILTER_COEF1 0x0000ffff
1342
1343/*****************************************************************************/
1344#define SRC1_CTL 0x8f8
1345/* Reserved [31:28] */
1346#define FLD_SRC1_FIFO_RD_TH 0x0f000000
1347/* Reserved [23:18] */
1348#define FLD_SRC1_PHASE_INC 0x0003ffff
1349
1350/*****************************************************************************/
1351#define SRC2_CTL 0x8fc
1352/* Reserved [31:28] */
1353#define FLD_SRC2_FIFO_RD_TH 0x0f000000
1354/* Reserved [23:18] */
1355#define FLD_SRC2_PHASE_INC 0x0003ffff
1356
1357/*****************************************************************************/
1358#define SRC3_CTL 0x900
1359/* Reserved [31:28] */
1360#define FLD_SRC3_FIFO_RD_TH 0x0f000000
1361/* Reserved [23:18] */
1362#define FLD_SRC3_PHASE_INC 0x0003ffff
1363
1364/*****************************************************************************/
1365#define SRC4_CTL 0x904
1366/* Reserved [31:28] */
1367#define FLD_SRC4_FIFO_RD_TH 0x0f000000
1368/* Reserved [23:18] */
1369#define FLD_SRC4_PHASE_INC 0x0003ffff
1370
1371/*****************************************************************************/
1372#define SRC5_CTL 0x908
1373/* Reserved [31:28] */
1374#define FLD_SRC5_FIFO_RD_TH 0x0f000000
1375/* Reserved [23:18] */
1376#define FLD_SRC5_PHASE_INC 0x0003ffff
1377
1378/*****************************************************************************/
1379#define SRC6_CTL 0x90c
1380/* Reserved [31:28] */
1381#define FLD_SRC6_FIFO_RD_TH 0x0f000000
1382/* Reserved [23:18] */
1383#define FLD_SRC6_PHASE_INC 0x0003ffff
1384
1385/*****************************************************************************/
1386#define BAND_OUT_SEL 0x910
1387#define FLD_SRC6_IN_SEL 0xc0000000
1388#define FLD_SRC6_CLK_SEL 0x30000000
1389#define FLD_SRC5_IN_SEL 0x0c000000
1390#define FLD_SRC5_CLK_SEL 0x03000000
1391#define FLD_SRC4_IN_SEL 0x00c00000
1392#define FLD_SRC4_CLK_SEL 0x00300000
1393#define FLD_SRC3_IN_SEL 0x000c0000
1394#define FLD_SRC3_CLK_SEL 0x00030000
1395#define FLD_BASEBAND_BYPASS_CTL 0x0000ff00
1396#define FLD_AC97_SRC_SEL 0x000000c0
1397#define FLD_I2S_SRC_SEL 0x00000030
1398#define FLD_PARALLEL2_SRC_SEL 0x0000000c
1399#define FLD_PARALLEL1_SRC_SEL 0x00000003
1400
1401/*****************************************************************************/
1402#define I2S_IN_CTL 0x914
1403/* Reserved [31:11] */
1404#define FLD_I2S_UP2X_BW20K 0x00000400
1405#define FLD_I2S_UP2X_BYPASS 0x00000200
1406#define FLD_I2S_IN_MASTER_MODE 0x00000100
1407#define FLD_I2S_IN_SONY_MODE 0x00000080
1408#define FLD_I2S_IN_RIGHT_JUST 0x00000040
1409#define FLD_I2S_IN_WS_SEL 0x00000020
1410#define FLD_I2S_IN_BCN_DEL 0x0000001f
1411
1412/*****************************************************************************/
1413#define I2S_OUT_CTL 0x918
1414/* Reserved [31:17] */
1415#define FLD_I2S_OUT_SOFT_RESET_EN 0x00010000
1416/* Reserved [15:9] */
1417#define FLD_I2S_OUT_MASTER_MODE 0x00000100
1418#define FLD_I2S_OUT_SONY_MODE 0x00000080
1419#define FLD_I2S_OUT_RIGHT_JUST 0x00000040
1420#define FLD_I2S_OUT_WS_SEL 0x00000020
1421#define FLD_I2S_OUT_BCN_DEL 0x0000001f
1422
1423/*****************************************************************************/
1424#define AC97_CTL 0x91c
1425/* Reserved [31:26] */
1426#define FLD_AC97_UP2X_BW20K 0x02000000
1427#define FLD_AC97_UP2X_BYPASS 0x01000000
1428/* Reserved [23:17] */
1429#define FLD_AC97_RST_ACL 0x00010000
1430/* Reserved [15:9] */
1431#define FLD_AC97_WAKE_UP_SYNC 0x00000100
1432/* Reserved [7:1] */
1433#define FLD_AC97_SHUTDOWN 0x00000001
1434
1435/* Cx231xx redefine */
1436#define QPSK_IAGC_CTL1 0x94c
1437#define QPSK_IAGC_CTL2 0x950
1438#define QPSK_FEPR_FREQ 0x954
1439#define QPSK_BTL_CTL1 0x958
1440#define QPSK_BTL_CTL2 0x95c
1441#define QPSK_CTL_CTL1 0x960
1442#define QPSK_CTL_CTL2 0x964
1443#define QPSK_MF_FAGC_CTL 0x968
1444#define QPSK_EQ_CTL 0x96c
1445#define QPSK_LOCK_CTL 0x970
1446
1447/*****************************************************************************/
1448#define FM1_DFT_CTL 0x9a8
1449#define FLD_FM1_DFT_THRESHOLD 0xffff0000
1450/* Reserved [15:8] */
1451#define FLD_FM1_DFT_CMP_CTL 0x00000080
1452#define FLD_FM1_DFT_AVG 0x00000070
1453/* Reserved [3:1] */
1454#define FLD_FM1_DFT_START 0x00000001
1455
1456/*****************************************************************************/
1457#define FM1_DFT_STATUS 0x9ac
1458#define FLD_FM1_DFT_DONE 0x80000000
1459/* Reserved [30:19] */
1460#define FLD_FM_DFT_TH_CMP 0x00040000
1461#define FLD_FM1_DFT 0x0003ffff
1462
1463/*****************************************************************************/
1464#define FM2_DFT_CTL 0x9b0
1465#define FLD_FM2_DFT_THRESHOLD 0xffff0000
1466/* Reserved [15:8] */
1467#define FLD_FM2_DFT_CMP_CTL 0x00000080
1468#define FLD_FM2_DFT_AVG 0x00000070
1469/* Reserved [3:1] */
1470#define FLD_FM2_DFT_START 0x00000001
1471
1472/*****************************************************************************/
1473#define FM2_DFT_STATUS 0x9b4
1474#define FLD_FM2_DFT_DONE 0x80000000
1475/* Reserved [30:19] */
1476#define FLD_FM2_DFT_TH_CMP_STAT 0x00040000
1477#define FLD_FM2_DFT 0x0003ffff
1478
1479/*****************************************************************************/
1480/* Cx231xx redefine */
1481#define AAGC_STATUS_REG 0x9b8
1482#define AAGC_STATUS 0x9b8
1483/* Reserved [31:27] */
1484#define FLD_FM2_DAGC_OUT 0x07000000
1485/* Reserved [23:19] */
1486#define FLD_FM1_DAGC_OUT 0x00070000
1487/* Reserved [15:6] */
1488#define FLD_AFE_VGA_OUT 0x0000003f
1489
1490/*****************************************************************************/
1491#define MTS_GAIN_STATUS 0x9bc
1492/* Reserved [31:14] */
1493#define FLD_MTS_GAIN 0x00003fff
1494
1495#define RDS_OUT 0x9c0
1496#define FLD_RDS_Q 0xffff0000
1497#define FLD_RDS_I 0x0000ffff
1498
1499/*****************************************************************************/
1500#define AUTOCONFIG_REG 0x9c4
1501/* Reserved [31:4] */
1502#define FLD_AUTOCONFIG_MODE 0x0000000f
1503
1504#define FM_AFC 0x9c8
1505#define FLD_FM2_AFC 0xffff0000
1506#define FLD_FM1_AFC 0x0000ffff
1507
1508/*****************************************************************************/
1509/* Cx231xx redefine */
1510#define NEW_SPARE 0x9cc
1511#define NEW_SPARE_REG 0x9cc
1512
1513/*****************************************************************************/
1514#define DBX_ADJ 0x9d0
1515/* Reserved [31:28] */
1516#define FLD_DBX2_ADJ 0x0fff0000
1517/* Reserved [15:12] */
1518#define FLD_DBX1_ADJ 0x00000fff
1519
1520#define VID_FMT_AUTO 0
1521#define VID_FMT_NTSC_M 1
1522#define VID_FMT_NTSC_J 2
1523#define VID_FMT_NTSC_443 3
1524#define VID_FMT_PAL_BDGHI 4
1525#define VID_FMT_PAL_M 5
1526#define VID_FMT_PAL_N 6
1527#define VID_FMT_PAL_NC 7
1528#define VID_FMT_PAL_60 8
1529#define VID_FMT_SECAM 12
1530#define VID_FMT_SECAM_60 13
1531
1532#define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */
1533#define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */
1534#define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */
1535#define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */
1536
1537#define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */
1538#define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */
1539#define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */
1540
1541#define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */
1542#define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */
1543#define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */
1544
1545#define TWO_TAP_FILT 0
1546#define THREE_TAP_FILT 1
1547#define FOUR_TAP_FILT 2
1548#define FIVE_TAP_FILT 3
1549
1550#define AUD_CHAN_SRC_PARALLEL 0
1551#define AUD_CHAN_SRC_I2S_INPUT 1
1552#define AUD_CHAN_SRC_FLATIRON 2
1553#define AUD_CHAN_SRC_PARALLEL3 3
1554
1555#define OUT_MODE_601 0
1556#define OUT_MODE_656 1
1557#define OUT_MODE_VIP11 2
1558#define OUT_MODE_VIP20 3
1559
1560#define PHASE_INC_49MHZ 0x0df22
1561#define PHASE_INC_56MHZ 0x0fa5b
1562#define PHASE_INC_28MHZ 0x010000
1563
1564#endif
diff --git a/drivers/media/video/cx231xx/cx231xx-vbi.c b/drivers/media/video/cx231xx/cx231xx-vbi.c
new file mode 100644
index 000000000000..94180526909c
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-vbi.c
@@ -0,0 +1,701 @@
1/*
2 cx231xx_vbi.c - driver for Conexant Cx23100/101/102 USB video capture devices
3
4 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5 Based on cx88 driver
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/bitmap.h>
27#include <linux/usb.h>
28#include <linux/i2c.h>
29#include <linux/version.h>
30#include <linux/mm.h>
31#include <linux/mutex.h>
32
33#include <media/v4l2-common.h>
34#include <media/v4l2-ioctl.h>
35#include <media/v4l2-chip-ident.h>
36#include <media/msp3400.h>
37#include <media/tuner.h>
38
39#include "cx231xx.h"
40#include "cx231xx-vbi.h"
41
42static inline void print_err_status(struct cx231xx *dev, int packet, int status)
43{
44 char *errmsg = "Unknown";
45
46 switch (status) {
47 case -ENOENT:
48 errmsg = "unlinked synchronuously";
49 break;
50 case -ECONNRESET:
51 errmsg = "unlinked asynchronuously";
52 break;
53 case -ENOSR:
54 errmsg = "Buffer error (overrun)";
55 break;
56 case -EPIPE:
57 errmsg = "Stalled (device not responding)";
58 break;
59 case -EOVERFLOW:
60 errmsg = "Babble (bad cable?)";
61 break;
62 case -EPROTO:
63 errmsg = "Bit-stuff error (bad cable?)";
64 break;
65 case -EILSEQ:
66 errmsg = "CRC/Timeout (could be anything)";
67 break;
68 case -ETIME:
69 errmsg = "Device does not respond";
70 break;
71 }
72 if (packet < 0) {
73 cx231xx_err(DRIVER_NAME "URB status %d [%s].\n", status,
74 errmsg);
75 } else {
76 cx231xx_err(DRIVER_NAME "URB packet %d, status %d [%s].\n",
77 packet, status, errmsg);
78 }
79}
80
81/*
82 * Controls the isoc copy of each urb packet
83 */
84static inline int cx231xx_isoc_vbi_copy(struct cx231xx *dev, struct urb *urb)
85{
86 struct cx231xx_buffer *buf;
87 struct cx231xx_dmaqueue *dma_q = urb->context;
88 int rc = 1;
89 unsigned char *p_buffer;
90 u32 bytes_parsed = 0, buffer_size = 0;
91 u8 sav_eav = 0;
92
93 if (!dev)
94 return 0;
95
96 if ((dev->state & DEV_DISCONNECTED) || (dev->state & DEV_MISCONFIGURED))
97 return 0;
98
99 if (urb->status < 0) {
100 print_err_status(dev, -1, urb->status);
101 if (urb->status == -ENOENT)
102 return 0;
103 }
104
105 buf = dev->vbi_mode.isoc_ctl.buf;
106
107 /* get buffer pointer and length */
108 p_buffer = urb->transfer_buffer;
109 buffer_size = urb->actual_length;
110
111 if (buffer_size > 0) {
112 bytes_parsed = 0;
113
114 if (dma_q->is_partial_line) {
115 /* Handle the case where we were working on a partial
116 line */
117 sav_eav = dma_q->last_sav;
118 } else {
119 /* Check for a SAV/EAV overlapping the
120 buffer boundary */
121
122 sav_eav = cx231xx_find_boundary_SAV_EAV(p_buffer,
123 dma_q->partial_buf,
124 &bytes_parsed);
125 }
126
127 sav_eav &= 0xF0;
128 /* Get the first line if we have some portion of an SAV/EAV from
129 the last buffer or a partial line */
130 if (sav_eav) {
131 bytes_parsed += cx231xx_get_vbi_line(dev, dma_q,
132 sav_eav, /* SAV/EAV */
133 p_buffer + bytes_parsed, /* p_buffer */
134 buffer_size - bytes_parsed); /* buffer size */
135 }
136
137 /* Now parse data that is completely in this buffer */
138 dma_q->is_partial_line = 0;
139
140 while (bytes_parsed < buffer_size) {
141 u32 bytes_used = 0;
142
143 sav_eav = cx231xx_find_next_SAV_EAV(
144 p_buffer + bytes_parsed, /* p_buffer */
145 buffer_size - bytes_parsed, /* buffer size */
146 &bytes_used); /* bytes used to get SAV/EAV */
147
148 bytes_parsed += bytes_used;
149
150 sav_eav &= 0xF0;
151 if (sav_eav && (bytes_parsed < buffer_size)) {
152 bytes_parsed += cx231xx_get_vbi_line(dev,
153 dma_q, sav_eav, /* SAV/EAV */
154 p_buffer+bytes_parsed, /* p_buffer */
155 buffer_size-bytes_parsed);/*buf size*/
156 }
157 }
158
159 /* Save the last four bytes of the buffer so we can
160 check the buffer boundary condition next time */
161 memcpy(dma_q->partial_buf, p_buffer + buffer_size - 4, 4);
162 bytes_parsed = 0;
163 }
164
165 return rc;
166}
167
168/* ------------------------------------------------------------------
169 Vbi buf operations
170 ------------------------------------------------------------------*/
171
172static int
173vbi_buffer_setup(struct videobuf_queue *vq, unsigned int *count,
174 unsigned int *size)
175{
176 struct cx231xx_fh *fh = vq->priv_data;
177 struct cx231xx *dev = fh->dev;
178 u32 height = 0;
179
180 height = ((dev->norm & V4L2_STD_625_50) ?
181 PAL_VBI_LINES : NTSC_VBI_LINES);
182
183 *size = (dev->width * height * 2);
184 if (0 == *count)
185 *count = CX231XX_DEF_VBI_BUF;
186
187 if (*count < CX231XX_MIN_BUF)
188 *count = CX231XX_MIN_BUF;
189
190 return 0;
191}
192
193/* This is called *without* dev->slock held; please keep it that way */
194static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
195{
196 struct cx231xx_fh *fh = vq->priv_data;
197 struct cx231xx *dev = fh->dev;
198 unsigned long flags = 0;
199 if (in_interrupt())
200 BUG();
201
202 /* We used to wait for the buffer to finish here, but this didn't work
203 because, as we were keeping the state as VIDEOBUF_QUEUED,
204 videobuf_queue_cancel marked it as finished for us.
205 (Also, it could wedge forever if the hardware was misconfigured.)
206
207 This should be safe; by the time we get here, the buffer isn't
208 queued anymore. If we ever start marking the buffers as
209 VIDEOBUF_ACTIVE, it won't be, though.
210 */
211 spin_lock_irqsave(&dev->vbi_mode.slock, flags);
212 if (dev->vbi_mode.isoc_ctl.buf == buf)
213 dev->vbi_mode.isoc_ctl.buf = NULL;
214 spin_unlock_irqrestore(&dev->vbi_mode.slock, flags);
215
216 videobuf_vmalloc_free(&buf->vb);
217 buf->vb.state = VIDEOBUF_NEEDS_INIT;
218}
219
220static int
221vbi_buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb,
222 enum v4l2_field field)
223{
224 struct cx231xx_fh *fh = vq->priv_data;
225 struct cx231xx_buffer *buf =
226 container_of(vb, struct cx231xx_buffer, vb);
227 struct cx231xx *dev = fh->dev;
228 int rc = 0, urb_init = 0;
229 u32 height = 0;
230
231 height = ((dev->norm & V4L2_STD_625_50) ?
232 PAL_VBI_LINES : NTSC_VBI_LINES);
233 buf->vb.size = ((dev->width << 1) * height);
234
235 if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size)
236 return -EINVAL;
237
238 buf->vb.width = dev->width;
239 buf->vb.height = height;
240 buf->vb.field = field;
241 buf->vb.field = V4L2_FIELD_SEQ_TB;
242
243 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
244 rc = videobuf_iolock(vq, &buf->vb, NULL);
245 if (rc < 0)
246 goto fail;
247 }
248
249 if (!dev->vbi_mode.isoc_ctl.num_bufs)
250 urb_init = 1;
251
252 if (urb_init) {
253 rc = cx231xx_init_vbi_isoc(dev, CX231XX_NUM_VBI_PACKETS,
254 CX231XX_NUM_VBI_BUFS,
255 dev->vbi_mode.alt_max_pkt_size[0],
256 cx231xx_isoc_vbi_copy);
257 if (rc < 0)
258 goto fail;
259 }
260
261 buf->vb.state = VIDEOBUF_PREPARED;
262 return 0;
263
264fail:
265 free_buffer(vq, buf);
266 return rc;
267}
268
269static void
270vbi_buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
271{
272 struct cx231xx_buffer *buf =
273 container_of(vb, struct cx231xx_buffer, vb);
274 struct cx231xx_fh *fh = vq->priv_data;
275 struct cx231xx *dev = fh->dev;
276 struct cx231xx_dmaqueue *vidq = &dev->vbi_mode.vidq;
277
278 buf->vb.state = VIDEOBUF_QUEUED;
279 list_add_tail(&buf->vb.queue, &vidq->active);
280
281}
282
283static void vbi_buffer_release(struct videobuf_queue *vq,
284 struct videobuf_buffer *vb)
285{
286 struct cx231xx_buffer *buf =
287 container_of(vb, struct cx231xx_buffer, vb);
288
289
290 free_buffer(vq, buf);
291}
292
293struct videobuf_queue_ops cx231xx_vbi_qops = {
294 .buf_setup = vbi_buffer_setup,
295 .buf_prepare = vbi_buffer_prepare,
296 .buf_queue = vbi_buffer_queue,
297 .buf_release = vbi_buffer_release,
298};
299
300/* ------------------------------------------------------------------
301 URB control
302 ------------------------------------------------------------------*/
303
304/*
305 * IRQ callback, called by URB callback
306 */
307static void cx231xx_irq_vbi_callback(struct urb *urb)
308{
309 struct cx231xx_dmaqueue *dma_q = urb->context;
310 struct cx231xx_video_mode *vmode =
311 container_of(dma_q, struct cx231xx_video_mode, vidq);
312 struct cx231xx *dev = container_of(vmode, struct cx231xx, vbi_mode);
313 int rc;
314
315 switch (urb->status) {
316 case 0: /* success */
317 case -ETIMEDOUT: /* NAK */
318 break;
319 case -ECONNRESET: /* kill */
320 case -ENOENT:
321 case -ESHUTDOWN:
322 return;
323 default: /* error */
324 cx231xx_err(DRIVER_NAME "urb completition error %d.\n",
325 urb->status);
326 break;
327 }
328
329 /* Copy data from URB */
330 spin_lock(&dev->vbi_mode.slock);
331 rc = dev->vbi_mode.isoc_ctl.isoc_copy(dev, urb);
332 spin_unlock(&dev->vbi_mode.slock);
333
334 /* Reset status */
335 urb->status = 0;
336
337 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
338 if (urb->status) {
339 cx231xx_err(DRIVER_NAME "urb resubmit failed (error=%i)\n",
340 urb->status);
341 }
342}
343
344/*
345 * Stop and Deallocate URBs
346 */
347void cx231xx_uninit_vbi_isoc(struct cx231xx *dev)
348{
349 struct urb *urb;
350 int i;
351
352 cx231xx_info(DRIVER_NAME "cx231xx: called cx231xx_uninit_vbi_isoc\n");
353
354 dev->vbi_mode.isoc_ctl.nfields = -1;
355 for (i = 0; i < dev->vbi_mode.isoc_ctl.num_bufs; i++) {
356 urb = dev->vbi_mode.isoc_ctl.urb[i];
357 if (urb) {
358 if (!irqs_disabled())
359 usb_kill_urb(urb);
360 else
361 usb_unlink_urb(urb);
362
363 if (dev->vbi_mode.isoc_ctl.transfer_buffer[i]) {
364
365 kfree(dev->vbi_mode.isoc_ctl.
366 transfer_buffer[i]);
367 dev->vbi_mode.isoc_ctl.transfer_buffer[i] =
368 NULL;
369 }
370 usb_free_urb(urb);
371 dev->vbi_mode.isoc_ctl.urb[i] = NULL;
372 }
373 dev->vbi_mode.isoc_ctl.transfer_buffer[i] = NULL;
374 }
375
376 kfree(dev->vbi_mode.isoc_ctl.urb);
377 kfree(dev->vbi_mode.isoc_ctl.transfer_buffer);
378
379 dev->vbi_mode.isoc_ctl.urb = NULL;
380 dev->vbi_mode.isoc_ctl.transfer_buffer = NULL;
381 dev->vbi_mode.isoc_ctl.num_bufs = 0;
382
383 cx231xx_capture_start(dev, 0, Vbi);
384}
385EXPORT_SYMBOL_GPL(cx231xx_uninit_vbi_isoc);
386
387/*
388 * Allocate URBs and start IRQ
389 */
390int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
391 int num_bufs, int max_pkt_size,
392 int (*isoc_copy) (struct cx231xx *dev,
393 struct urb *urb))
394{
395 struct cx231xx_dmaqueue *dma_q = &dev->vbi_mode.vidq;
396 int i;
397 int sb_size, pipe;
398 struct urb *urb;
399 int rc;
400
401 cx231xx_info(DRIVER_NAME "cx231xx: called cx231xx_prepare_isoc\n");
402
403 /* De-allocates all pending stuff */
404 cx231xx_uninit_vbi_isoc(dev);
405
406 /* clear if any halt */
407 usb_clear_halt(dev->udev,
408 usb_rcvbulkpipe(dev->udev,
409 dev->vbi_mode.end_point_addr));
410
411 dev->vbi_mode.isoc_ctl.isoc_copy = isoc_copy;
412 dev->vbi_mode.isoc_ctl.num_bufs = num_bufs;
413 dma_q->pos = 0;
414 dma_q->is_partial_line = 0;
415 dma_q->last_sav = 0;
416 dma_q->current_field = -1;
417 dma_q->bytes_left_in_line = dev->width << 1;
418 dma_q->lines_per_field = ((dev->norm & V4L2_STD_625_50) ?
419 PAL_VBI_LINES : NTSC_VBI_LINES);
420 dma_q->lines_completed = 0;
421 for (i = 0; i < 8; i++)
422 dma_q->partial_buf[i] = 0;
423
424 dev->vbi_mode.isoc_ctl.urb = kzalloc(sizeof(void *) * num_bufs,
425 GFP_KERNEL);
426 if (!dev->vbi_mode.isoc_ctl.urb) {
427 cx231xx_errdev("cannot alloc memory for usb buffers\n");
428 return -ENOMEM;
429 }
430
431 dev->vbi_mode.isoc_ctl.transfer_buffer =
432 kzalloc(sizeof(void *) * num_bufs, GFP_KERNEL);
433 if (!dev->vbi_mode.isoc_ctl.transfer_buffer) {
434 cx231xx_errdev("cannot allocate memory for usbtransfer\n");
435 kfree(dev->vbi_mode.isoc_ctl.urb);
436 return -ENOMEM;
437 }
438
439 dev->vbi_mode.isoc_ctl.max_pkt_size = max_pkt_size;
440 dev->vbi_mode.isoc_ctl.buf = NULL;
441
442 sb_size = max_packets * dev->vbi_mode.isoc_ctl.max_pkt_size;
443
444 /* allocate urbs and transfer buffers */
445 for (i = 0; i < dev->vbi_mode.isoc_ctl.num_bufs; i++) {
446
447 urb = usb_alloc_urb(0, GFP_KERNEL);
448 if (!urb) {
449 cx231xx_err(DRIVER_NAME
450 ": cannot alloc isoc_ctl.urb %i\n", i);
451 cx231xx_uninit_vbi_isoc(dev);
452 return -ENOMEM;
453 }
454 dev->vbi_mode.isoc_ctl.urb[i] = urb;
455 urb->transfer_flags = 0;
456
457 dev->vbi_mode.isoc_ctl.transfer_buffer[i] =
458 kzalloc(sb_size, GFP_KERNEL);
459 if (!dev->vbi_mode.isoc_ctl.transfer_buffer[i]) {
460 cx231xx_err(DRIVER_NAME
461 ": unable to allocate %i bytes for transfer"
462 " buffer %i%s\n", sb_size, i,
463 in_interrupt() ? " while in int" : "");
464 cx231xx_uninit_vbi_isoc(dev);
465 return -ENOMEM;
466 }
467
468 pipe = usb_rcvbulkpipe(dev->udev, dev->vbi_mode.end_point_addr);
469 usb_fill_bulk_urb(urb, dev->udev, pipe,
470 dev->vbi_mode.isoc_ctl.transfer_buffer[i],
471 sb_size, cx231xx_irq_vbi_callback, dma_q);
472 }
473
474 init_waitqueue_head(&dma_q->wq);
475
476 /* submit urbs and enables IRQ */
477 for (i = 0; i < dev->vbi_mode.isoc_ctl.num_bufs; i++) {
478 rc = usb_submit_urb(dev->vbi_mode.isoc_ctl.urb[i], GFP_ATOMIC);
479 if (rc) {
480 cx231xx_err(DRIVER_NAME
481 ": submit of urb %i failed (error=%i)\n", i,
482 rc);
483 cx231xx_uninit_vbi_isoc(dev);
484 return rc;
485 }
486 }
487
488 cx231xx_capture_start(dev, 1, Vbi);
489
490 return 0;
491}
492EXPORT_SYMBOL_GPL(cx231xx_init_vbi_isoc);
493
494u32 cx231xx_get_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
495 u8 sav_eav, u8 *p_buffer, u32 buffer_size)
496{
497 u32 bytes_copied = 0;
498 int current_field = -1;
499
500 switch (sav_eav) {
501
502 case SAV_VBI_FIELD1:
503 current_field = 1;
504 break;
505
506 case SAV_VBI_FIELD2:
507 current_field = 2;
508 break;
509 default:
510 break;
511 }
512
513 if (current_field < 0)
514 return bytes_copied;
515
516 dma_q->last_sav = sav_eav;
517
518 bytes_copied =
519 cx231xx_copy_vbi_line(dev, dma_q, p_buffer, buffer_size,
520 current_field);
521
522 return bytes_copied;
523}
524
525/*
526 * Announces that a buffer were filled and request the next
527 */
528static inline void vbi_buffer_filled(struct cx231xx *dev,
529 struct cx231xx_dmaqueue *dma_q,
530 struct cx231xx_buffer *buf)
531{
532 /* Advice that buffer was filled */
533 /* cx231xx_info(DRIVER_NAME "[%p/%d] wakeup\n", buf, buf->vb.i); */
534
535 buf->vb.state = VIDEOBUF_DONE;
536 buf->vb.field_count++;
537 do_gettimeofday(&buf->vb.ts);
538
539 dev->vbi_mode.isoc_ctl.buf = NULL;
540
541 list_del(&buf->vb.queue);
542 wake_up(&buf->vb.done);
543}
544
545u32 cx231xx_copy_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
546 u8 *p_line, u32 length, int field_number)
547{
548 u32 bytes_to_copy;
549 struct cx231xx_buffer *buf;
550 u32 _line_size = dev->width * 2;
551
552 if (dma_q->current_field != field_number)
553 cx231xx_reset_vbi_buffer(dev, dma_q);
554
555 /* get the buffer pointer */
556 buf = dev->vbi_mode.isoc_ctl.buf;
557
558 /* Remember the field number for next time */
559 dma_q->current_field = field_number;
560
561 bytes_to_copy = dma_q->bytes_left_in_line;
562 if (bytes_to_copy > length)
563 bytes_to_copy = length;
564
565 if (dma_q->lines_completed >= dma_q->lines_per_field) {
566 dma_q->bytes_left_in_line -= bytes_to_copy;
567 dma_q->is_partial_line =
568 (dma_q->bytes_left_in_line == 0) ? 0 : 1;
569 return 0;
570 }
571
572 dma_q->is_partial_line = 1;
573
574 /* If we don't have a buffer, just return the number of bytes we would
575 have copied if we had a buffer. */
576 if (!buf) {
577 dma_q->bytes_left_in_line -= bytes_to_copy;
578 dma_q->is_partial_line =
579 (dma_q->bytes_left_in_line == 0) ? 0 : 1;
580 return bytes_to_copy;
581 }
582
583 /* copy the data to video buffer */
584 cx231xx_do_vbi_copy(dev, dma_q, p_line, bytes_to_copy);
585
586 dma_q->pos += bytes_to_copy;
587 dma_q->bytes_left_in_line -= bytes_to_copy;
588
589 if (dma_q->bytes_left_in_line == 0) {
590
591 dma_q->bytes_left_in_line = _line_size;
592 dma_q->lines_completed++;
593 dma_q->is_partial_line = 0;
594
595 if (cx231xx_is_vbi_buffer_done(dev, dma_q) && buf) {
596
597 vbi_buffer_filled(dev, dma_q, buf);
598
599 dma_q->pos = 0;
600 buf = NULL;
601 dma_q->lines_completed = 0;
602 }
603 }
604
605 return bytes_to_copy;
606}
607
608/*
609 * video-buf generic routine to get the next available buffer
610 */
611static inline void get_next_vbi_buf(struct cx231xx_dmaqueue *dma_q,
612 struct cx231xx_buffer **buf)
613{
614 struct cx231xx_video_mode *vmode =
615 container_of(dma_q, struct cx231xx_video_mode, vidq);
616 struct cx231xx *dev = container_of(vmode, struct cx231xx, vbi_mode);
617 char *outp;
618
619 if (list_empty(&dma_q->active)) {
620 cx231xx_err(DRIVER_NAME ": No active queue to serve\n");
621 dev->vbi_mode.isoc_ctl.buf = NULL;
622 *buf = NULL;
623 return;
624 }
625
626 /* Get the next buffer */
627 *buf = list_entry(dma_q->active.next, struct cx231xx_buffer, vb.queue);
628
629 /* Cleans up buffer - Usefull for testing for frame/URB loss */
630 outp = videobuf_to_vmalloc(&(*buf)->vb);
631 memset(outp, 0, (*buf)->vb.size);
632
633 dev->vbi_mode.isoc_ctl.buf = *buf;
634
635 return;
636}
637
638void cx231xx_reset_vbi_buffer(struct cx231xx *dev,
639 struct cx231xx_dmaqueue *dma_q)
640{
641 struct cx231xx_buffer *buf;
642
643 buf = dev->vbi_mode.isoc_ctl.buf;
644
645 if (buf == NULL) {
646 /* first try to get the buffer */
647 get_next_vbi_buf(dma_q, &buf);
648
649 dma_q->pos = 0;
650 dma_q->current_field = -1;
651 }
652
653 dma_q->bytes_left_in_line = dev->width << 1;
654 dma_q->lines_completed = 0;
655}
656
657int cx231xx_do_vbi_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
658 u8 *p_buffer, u32 bytes_to_copy)
659{
660 u8 *p_out_buffer = NULL;
661 u32 current_line_bytes_copied = 0;
662 struct cx231xx_buffer *buf;
663 u32 _line_size = dev->width << 1;
664 void *startwrite;
665 int offset, lencopy;
666
667 buf = dev->vbi_mode.isoc_ctl.buf;
668
669 if (buf == NULL)
670 return -EINVAL;
671
672 p_out_buffer = videobuf_to_vmalloc(&buf->vb);
673
674 if (dma_q->bytes_left_in_line != _line_size) {
675 current_line_bytes_copied =
676 _line_size - dma_q->bytes_left_in_line;
677 }
678
679 offset = (dma_q->lines_completed * _line_size) +
680 current_line_bytes_copied;
681
682 /* prepare destination address */
683 startwrite = p_out_buffer + offset;
684
685 lencopy = dma_q->bytes_left_in_line > bytes_to_copy ?
686 bytes_to_copy : dma_q->bytes_left_in_line;
687
688 memcpy(startwrite, p_buffer, lencopy);
689
690 return 0;
691}
692
693u8 cx231xx_is_vbi_buffer_done(struct cx231xx *dev,
694 struct cx231xx_dmaqueue *dma_q)
695{
696 u32 height = 0;
697
698 height = ((dev->norm & V4L2_STD_625_50) ?
699 PAL_VBI_LINES : NTSC_VBI_LINES);
700 return (dma_q->lines_completed == height) ? 1 : 0;
701}
diff --git a/drivers/media/video/cx231xx/cx231xx-vbi.h b/drivers/media/video/cx231xx/cx231xx-vbi.h
new file mode 100644
index 000000000000..89c7fe80b261
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-vbi.h
@@ -0,0 +1,65 @@
1/*
2 cx231xx_vbi.h - driver for Conexant Cx23100/101/102 USB video capture devices
3
4 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5 Based on cx88 driver
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _CX231XX_VBI_H
23#define _CX231XX_VBI_H
24
25extern struct videobuf_queue_ops cx231xx_vbi_qops;
26
27#define NTSC_VBI_START_LINE 10 /* line 10 - 21 */
28#define NTSC_VBI_END_LINE 21
29#define NTSC_VBI_LINES (NTSC_VBI_END_LINE-NTSC_VBI_START_LINE+1)
30
31#define PAL_VBI_START_LINE 6
32#define PAL_VBI_END_LINE 23
33#define PAL_VBI_LINES (PAL_VBI_END_LINE-PAL_VBI_START_LINE+1)
34
35#define VBI_STRIDE 1440
36#define VBI_SAMPLES_PER_LINE 1440
37
38#define CX231XX_NUM_VBI_PACKETS 4
39#define CX231XX_NUM_VBI_BUFS 5
40
41/* stream functions */
42int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
43 int num_bufs, int max_pkt_size,
44 int (*isoc_copy) (struct cx231xx *dev,
45 struct urb *urb));
46
47void cx231xx_uninit_vbi_isoc(struct cx231xx *dev);
48
49/* vbi data copy functions */
50u32 cx231xx_get_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
51 u8 sav_eav, u8 *p_buffer, u32 buffer_size);
52
53u32 cx231xx_copy_vbi_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
54 u8 *p_line, u32 length, int field_number);
55
56void cx231xx_reset_vbi_buffer(struct cx231xx *dev,
57 struct cx231xx_dmaqueue *dma_q);
58
59int cx231xx_do_vbi_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
60 u8 *p_buffer, u32 bytes_to_copy);
61
62u8 cx231xx_is_vbi_buffer_done(struct cx231xx *dev,
63 struct cx231xx_dmaqueue *dma_q);
64
65#endif
diff --git a/drivers/media/video/cx231xx/cx231xx-video.c b/drivers/media/video/cx231xx/cx231xx-video.c
new file mode 100644
index 000000000000..a23ae73fe634
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-video.c
@@ -0,0 +1,2434 @@
1/*
2 cx231xx-video.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6 Based on em28xx driver
7 Based on cx23885 driver
8 Based on cx88 driver
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#include <linux/init.h>
26#include <linux/list.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/bitmap.h>
30#include <linux/usb.h>
31#include <linux/i2c.h>
32#include <linux/version.h>
33#include <linux/mm.h>
34#include <linux/mutex.h>
35
36#include <media/v4l2-common.h>
37#include <media/v4l2-ioctl.h>
38#include <media/v4l2-chip-ident.h>
39#include <media/msp3400.h>
40#include <media/tuner.h>
41
42#include "dvb_frontend.h"
43
44#include "cx231xx.h"
45#include "cx231xx-vbi.h"
46
47#define CX231XX_VERSION_CODE KERNEL_VERSION(0, 0, 1)
48
49#define DRIVER_AUTHOR "Srinivasa Deevi <srinivasa.deevi@conexant.com>"
50#define DRIVER_DESC "Conexant cx231xx based USB video device driver"
51
52#define cx231xx_videodbg(fmt, arg...) do {\
53 if (video_debug) \
54 printk(KERN_INFO "%s %s :"fmt, \
55 dev->name, __func__ , ##arg); } while (0)
56
57static unsigned int isoc_debug;
58module_param(isoc_debug, int, 0644);
59MODULE_PARM_DESC(isoc_debug, "enable debug messages [isoc transfers]");
60
61#define cx231xx_isocdbg(fmt, arg...) \
62do {\
63 if (isoc_debug) { \
64 printk(KERN_INFO "%s %s :"fmt, \
65 dev->name, __func__ , ##arg); \
66 } \
67 } while (0)
68
69MODULE_AUTHOR(DRIVER_AUTHOR);
70MODULE_DESCRIPTION(DRIVER_DESC);
71MODULE_LICENSE("GPL");
72
73static unsigned int card[] = {[0 ... (CX231XX_MAXBOARDS - 1)] = UNSET };
74static unsigned int video_nr[] = {[0 ... (CX231XX_MAXBOARDS - 1)] = UNSET };
75static unsigned int vbi_nr[] = {[0 ... (CX231XX_MAXBOARDS - 1)] = UNSET };
76static unsigned int radio_nr[] = {[0 ... (CX231XX_MAXBOARDS - 1)] = UNSET };
77
78module_param_array(card, int, NULL, 0444);
79module_param_array(video_nr, int, NULL, 0444);
80module_param_array(vbi_nr, int, NULL, 0444);
81module_param_array(radio_nr, int, NULL, 0444);
82
83MODULE_PARM_DESC(card, "card type");
84MODULE_PARM_DESC(video_nr, "video device numbers");
85MODULE_PARM_DESC(vbi_nr, "vbi device numbers");
86MODULE_PARM_DESC(radio_nr, "radio device numbers");
87
88static unsigned int video_debug;
89module_param(video_debug, int, 0644);
90MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
91
92/* supported video standards */
93static struct cx231xx_fmt format[] = {
94 {
95 .name = "16bpp YUY2, 4:2:2, packed",
96 .fourcc = V4L2_PIX_FMT_YUYV,
97 .depth = 16,
98 .reg = 0,
99 },
100};
101
102/* supported controls */
103/* Common to all boards */
104
105/* ------------------------------------------------------------------- */
106
107static const struct v4l2_queryctrl no_ctl = {
108 .name = "42",
109 .flags = V4L2_CTRL_FLAG_DISABLED,
110};
111
112static struct cx231xx_ctrl cx231xx_ctls[] = {
113 /* --- video --- */
114 {
115 .v = {
116 .id = V4L2_CID_BRIGHTNESS,
117 .name = "Brightness",
118 .minimum = 0x00,
119 .maximum = 0xff,
120 .step = 1,
121 .default_value = 0x7f,
122 .type = V4L2_CTRL_TYPE_INTEGER,
123 },
124 .off = 128,
125 .reg = LUMA_CTRL,
126 .mask = 0x00ff,
127 .shift = 0,
128 }, {
129 .v = {
130 .id = V4L2_CID_CONTRAST,
131 .name = "Contrast",
132 .minimum = 0,
133 .maximum = 0xff,
134 .step = 1,
135 .default_value = 0x3f,
136 .type = V4L2_CTRL_TYPE_INTEGER,
137 },
138 .off = 0,
139 .reg = LUMA_CTRL,
140 .mask = 0xff00,
141 .shift = 8,
142 }, {
143 .v = {
144 .id = V4L2_CID_HUE,
145 .name = "Hue",
146 .minimum = 0,
147 .maximum = 0xff,
148 .step = 1,
149 .default_value = 0x7f,
150 .type = V4L2_CTRL_TYPE_INTEGER,
151 },
152 .off = 128,
153 .reg = CHROMA_CTRL,
154 .mask = 0xff0000,
155 .shift = 16,
156 }, {
157 /* strictly, this only describes only U saturation.
158 * V saturation is handled specially through code.
159 */
160 .v = {
161 .id = V4L2_CID_SATURATION,
162 .name = "Saturation",
163 .minimum = 0,
164 .maximum = 0xff,
165 .step = 1,
166 .default_value = 0x7f,
167 .type = V4L2_CTRL_TYPE_INTEGER,
168 },
169 .off = 0,
170 .reg = CHROMA_CTRL,
171 .mask = 0x00ff,
172 .shift = 0,
173 }, {
174 /* --- audio --- */
175 .v = {
176 .id = V4L2_CID_AUDIO_MUTE,
177 .name = "Mute",
178 .minimum = 0,
179 .maximum = 1,
180 .default_value = 1,
181 .type = V4L2_CTRL_TYPE_BOOLEAN,
182 },
183 .reg = PATH1_CTL1,
184 .mask = (0x1f << 24),
185 .shift = 24,
186 }, {
187 .v = {
188 .id = V4L2_CID_AUDIO_VOLUME,
189 .name = "Volume",
190 .minimum = 0,
191 .maximum = 0x3f,
192 .step = 1,
193 .default_value = 0x3f,
194 .type = V4L2_CTRL_TYPE_INTEGER,
195 },
196 .reg = PATH1_VOL_CTL,
197 .mask = 0xff,
198 .shift = 0,
199 }
200};
201static const int CX231XX_CTLS = ARRAY_SIZE(cx231xx_ctls);
202
203static const u32 cx231xx_user_ctrls[] = {
204 V4L2_CID_USER_CLASS,
205 V4L2_CID_BRIGHTNESS,
206 V4L2_CID_CONTRAST,
207 V4L2_CID_SATURATION,
208 V4L2_CID_HUE,
209 V4L2_CID_AUDIO_VOLUME,
210#if 0
211 V4L2_CID_AUDIO_BALANCE,
212#endif
213 V4L2_CID_AUDIO_MUTE,
214 0
215};
216
217static const u32 *ctrl_classes[] = {
218 cx231xx_user_ctrls,
219 NULL
220};
221
222/* ------------------------------------------------------------------
223 Video buffer and parser functions
224 ------------------------------------------------------------------*/
225
226/*
227 * Announces that a buffer were filled and request the next
228 */
229static inline void buffer_filled(struct cx231xx *dev,
230 struct cx231xx_dmaqueue *dma_q,
231 struct cx231xx_buffer *buf)
232{
233 /* Advice that buffer was filled */
234 cx231xx_isocdbg("[%p/%d] wakeup\n", buf, buf->vb.i);
235 buf->vb.state = VIDEOBUF_DONE;
236 buf->vb.field_count++;
237 do_gettimeofday(&buf->vb.ts);
238
239 dev->video_mode.isoc_ctl.buf = NULL;
240
241 list_del(&buf->vb.queue);
242 wake_up(&buf->vb.done);
243}
244
245static inline void print_err_status(struct cx231xx *dev, int packet, int status)
246{
247 char *errmsg = "Unknown";
248
249 switch (status) {
250 case -ENOENT:
251 errmsg = "unlinked synchronuously";
252 break;
253 case -ECONNRESET:
254 errmsg = "unlinked asynchronuously";
255 break;
256 case -ENOSR:
257 errmsg = "Buffer error (overrun)";
258 break;
259 case -EPIPE:
260 errmsg = "Stalled (device not responding)";
261 break;
262 case -EOVERFLOW:
263 errmsg = "Babble (bad cable?)";
264 break;
265 case -EPROTO:
266 errmsg = "Bit-stuff error (bad cable?)";
267 break;
268 case -EILSEQ:
269 errmsg = "CRC/Timeout (could be anything)";
270 break;
271 case -ETIME:
272 errmsg = "Device does not respond";
273 break;
274 }
275 if (packet < 0) {
276 cx231xx_isocdbg("URB status %d [%s].\n", status, errmsg);
277 } else {
278 cx231xx_isocdbg("URB packet %d, status %d [%s].\n",
279 packet, status, errmsg);
280 }
281}
282
283/*
284 * video-buf generic routine to get the next available buffer
285 */
286static inline void get_next_buf(struct cx231xx_dmaqueue *dma_q,
287 struct cx231xx_buffer **buf)
288{
289 struct cx231xx_video_mode *vmode =
290 container_of(dma_q, struct cx231xx_video_mode, vidq);
291 struct cx231xx *dev = container_of(vmode, struct cx231xx, video_mode);
292
293 char *outp;
294
295 if (list_empty(&dma_q->active)) {
296 cx231xx_isocdbg("No active queue to serve\n");
297 dev->video_mode.isoc_ctl.buf = NULL;
298 *buf = NULL;
299 return;
300 }
301
302 /* Get the next buffer */
303 *buf = list_entry(dma_q->active.next, struct cx231xx_buffer, vb.queue);
304
305 /* Cleans up buffer - Usefull for testing for frame/URB loss */
306 outp = videobuf_to_vmalloc(&(*buf)->vb);
307 memset(outp, 0, (*buf)->vb.size);
308
309 dev->video_mode.isoc_ctl.buf = *buf;
310
311 return;
312}
313
314/*
315 * Controls the isoc copy of each urb packet
316 */
317static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
318{
319 struct cx231xx_buffer *buf;
320 struct cx231xx_dmaqueue *dma_q = urb->context;
321 unsigned char *outp = NULL;
322 int i, rc = 1;
323 unsigned char *p_buffer;
324 u32 bytes_parsed = 0, buffer_size = 0;
325 u8 sav_eav = 0;
326
327 if (!dev)
328 return 0;
329
330 if ((dev->state & DEV_DISCONNECTED) || (dev->state & DEV_MISCONFIGURED))
331 return 0;
332
333 if (urb->status < 0) {
334 print_err_status(dev, -1, urb->status);
335 if (urb->status == -ENOENT)
336 return 0;
337 }
338
339 buf = dev->video_mode.isoc_ctl.buf;
340 if (buf != NULL)
341 outp = videobuf_to_vmalloc(&buf->vb);
342
343 for (i = 0; i < urb->number_of_packets; i++) {
344 int status = urb->iso_frame_desc[i].status;
345
346 if (status < 0) {
347 print_err_status(dev, i, status);
348 if (urb->iso_frame_desc[i].status != -EPROTO)
349 continue;
350 }
351
352 if (urb->iso_frame_desc[i].actual_length <= 0) {
353 /* cx231xx_isocdbg("packet %d is empty",i); - spammy */
354 continue;
355 }
356 if (urb->iso_frame_desc[i].actual_length >
357 dev->video_mode.max_pkt_size) {
358 cx231xx_isocdbg("packet bigger than packet size");
359 continue;
360 }
361
362 /* get buffer pointer and length */
363 p_buffer = urb->transfer_buffer + urb->iso_frame_desc[i].offset;
364 buffer_size = urb->iso_frame_desc[i].actual_length;
365 bytes_parsed = 0;
366
367 if (dma_q->is_partial_line) {
368 /* Handle the case of a partial line */
369 sav_eav = dma_q->last_sav;
370 } else {
371 /* Check for a SAV/EAV overlapping
372 the buffer boundary */
373 sav_eav =
374 cx231xx_find_boundary_SAV_EAV(p_buffer,
375 dma_q->partial_buf,
376 &bytes_parsed);
377 }
378
379 sav_eav &= 0xF0;
380 /* Get the first line if we have some portion of an SAV/EAV from
381 the last buffer or a partial line */
382 if (sav_eav) {
383 bytes_parsed += cx231xx_get_video_line(dev, dma_q,
384 sav_eav, /* SAV/EAV */
385 p_buffer + bytes_parsed, /* p_buffer */
386 buffer_size - bytes_parsed);/* buf size */
387 }
388
389 /* Now parse data that is completely in this buffer */
390 /* dma_q->is_partial_line = 0; */
391
392 while (bytes_parsed < buffer_size) {
393 u32 bytes_used = 0;
394
395 sav_eav = cx231xx_find_next_SAV_EAV(
396 p_buffer + bytes_parsed, /* p_buffer */
397 buffer_size - bytes_parsed, /* buf size */
398 &bytes_used);/* bytes used to get SAV/EAV */
399
400 bytes_parsed += bytes_used;
401
402 sav_eav &= 0xF0;
403 if (sav_eav && (bytes_parsed < buffer_size)) {
404 bytes_parsed += cx231xx_get_video_line(dev,
405 dma_q, sav_eav, /* SAV/EAV */
406 p_buffer + bytes_parsed,/* p_buffer */
407 buffer_size - bytes_parsed);/*buf size*/
408 }
409 }
410
411 /* Save the last four bytes of the buffer so we can check the
412 buffer boundary condition next time */
413 memcpy(dma_q->partial_buf, p_buffer + buffer_size - 4, 4);
414 bytes_parsed = 0;
415
416 }
417 return rc;
418}
419
420u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf,
421 u32 *p_bytes_used)
422{
423 u32 bytes_used;
424 u8 boundary_bytes[8];
425 u8 sav_eav = 0;
426
427 *p_bytes_used = 0;
428
429 /* Create an array of the last 4 bytes of the last buffer and the first
430 4 bytes of the current buffer. */
431
432 memcpy(boundary_bytes, partial_buf, 4);
433 memcpy(boundary_bytes + 4, p_buffer, 4);
434
435 /* Check for the SAV/EAV in the boundary buffer */
436 sav_eav = cx231xx_find_next_SAV_EAV((u8 *)&boundary_bytes, 8,
437 &bytes_used);
438
439 if (sav_eav) {
440 /* found a boundary SAV/EAV. Updates the bytes used to reflect
441 only those used in the new buffer */
442 *p_bytes_used = bytes_used - 4;
443 }
444
445 return sav_eav;
446}
447
448u8 cx231xx_find_next_SAV_EAV(u8 *p_buffer, u32 buffer_size, u32 *p_bytes_used)
449{
450 u32 i;
451 u8 sav_eav = 0;
452
453 /*
454 * Don't search if the buffer size is less than 4. It causes a page
455 * fault since buffer_size - 4 evaluates to a large number in that
456 * case.
457 */
458 if (buffer_size < 4) {
459 *p_bytes_used = buffer_size;
460 return 0;
461 }
462
463 for (i = 0; i < (buffer_size - 3); i++) {
464
465 if ((p_buffer[i] == 0xFF) &&
466 (p_buffer[i + 1] == 0x00) && (p_buffer[i + 2] == 0x00)) {
467
468 *p_bytes_used = i + 4;
469 sav_eav = p_buffer[i + 3];
470 return sav_eav;
471 }
472 }
473
474 *p_bytes_used = buffer_size;
475 return 0;
476}
477
478u32 cx231xx_get_video_line(struct cx231xx *dev,
479 struct cx231xx_dmaqueue *dma_q, u8 sav_eav,
480 u8 *p_buffer, u32 buffer_size)
481{
482 u32 bytes_copied = 0;
483 int current_field = -1;
484
485 switch (sav_eav) {
486 case SAV_ACTIVE_VIDEO_FIELD1:
487 /* looking for skipped line which occurred in PAL 720x480 mode.
488 In this case, there will be no active data contained
489 between the SAV and EAV */
490 if ((buffer_size > 3) && (p_buffer[0] == 0xFF) &&
491 (p_buffer[1] == 0x00) && (p_buffer[2] == 0x00) &&
492 ((p_buffer[3] == EAV_ACTIVE_VIDEO_FIELD1) ||
493 (p_buffer[3] == EAV_ACTIVE_VIDEO_FIELD2) ||
494 (p_buffer[3] == EAV_VBLANK_FIELD1) ||
495 (p_buffer[3] == EAV_VBLANK_FIELD2)))
496 return bytes_copied;
497 current_field = 1;
498 break;
499
500 case SAV_ACTIVE_VIDEO_FIELD2:
501 /* looking for skipped line which occurred in PAL 720x480 mode.
502 In this case, there will be no active data contained between
503 the SAV and EAV */
504 if ((buffer_size > 3) && (p_buffer[0] == 0xFF) &&
505 (p_buffer[1] == 0x00) && (p_buffer[2] == 0x00) &&
506 ((p_buffer[3] == EAV_ACTIVE_VIDEO_FIELD1) ||
507 (p_buffer[3] == EAV_ACTIVE_VIDEO_FIELD2) ||
508 (p_buffer[3] == EAV_VBLANK_FIELD1) ||
509 (p_buffer[3] == EAV_VBLANK_FIELD2)))
510 return bytes_copied;
511 current_field = 2;
512 break;
513 }
514
515 dma_q->last_sav = sav_eav;
516
517 bytes_copied = cx231xx_copy_video_line(dev, dma_q, p_buffer,
518 buffer_size, current_field);
519
520 return bytes_copied;
521}
522
523u32 cx231xx_copy_video_line(struct cx231xx *dev,
524 struct cx231xx_dmaqueue *dma_q, u8 *p_line,
525 u32 length, int field_number)
526{
527 u32 bytes_to_copy;
528 struct cx231xx_buffer *buf;
529 u32 _line_size = dev->width * 2;
530
531 if (dma_q->current_field != field_number)
532 cx231xx_reset_video_buffer(dev, dma_q);
533
534 /* get the buffer pointer */
535 buf = dev->video_mode.isoc_ctl.buf;
536
537 /* Remember the field number for next time */
538 dma_q->current_field = field_number;
539
540 bytes_to_copy = dma_q->bytes_left_in_line;
541 if (bytes_to_copy > length)
542 bytes_to_copy = length;
543
544 if (dma_q->lines_completed >= dma_q->lines_per_field) {
545 dma_q->bytes_left_in_line -= bytes_to_copy;
546 dma_q->is_partial_line = (dma_q->bytes_left_in_line == 0) ?
547 0 : 1;
548 return 0;
549 }
550
551 dma_q->is_partial_line = 1;
552
553 /* If we don't have a buffer, just return the number of bytes we would
554 have copied if we had a buffer. */
555 if (!buf) {
556 dma_q->bytes_left_in_line -= bytes_to_copy;
557 dma_q->is_partial_line = (dma_q->bytes_left_in_line == 0)
558 ? 0 : 1;
559 return bytes_to_copy;
560 }
561
562 /* copy the data to video buffer */
563 cx231xx_do_copy(dev, dma_q, p_line, bytes_to_copy);
564
565 dma_q->pos += bytes_to_copy;
566 dma_q->bytes_left_in_line -= bytes_to_copy;
567
568 if (dma_q->bytes_left_in_line == 0) {
569 dma_q->bytes_left_in_line = _line_size;
570 dma_q->lines_completed++;
571 dma_q->is_partial_line = 0;
572
573 if (cx231xx_is_buffer_done(dev, dma_q) && buf) {
574 buffer_filled(dev, dma_q, buf);
575
576 dma_q->pos = 0;
577 buf = NULL;
578 dma_q->lines_completed = 0;
579 }
580 }
581
582 return bytes_to_copy;
583}
584
585void cx231xx_reset_video_buffer(struct cx231xx *dev,
586 struct cx231xx_dmaqueue *dma_q)
587{
588 struct cx231xx_buffer *buf;
589
590 /* handle the switch from field 1 to field 2 */
591 if (dma_q->current_field == 1) {
592 if (dma_q->lines_completed >= dma_q->lines_per_field)
593 dma_q->field1_done = 1;
594 else
595 dma_q->field1_done = 0;
596 }
597
598 buf = dev->video_mode.isoc_ctl.buf;
599
600 if (buf == NULL) {
601 u8 *outp = NULL;
602 /* first try to get the buffer */
603 get_next_buf(dma_q, &buf);
604
605 if (buf)
606 outp = videobuf_to_vmalloc(&buf->vb);
607
608 dma_q->pos = 0;
609 dma_q->field1_done = 0;
610 dma_q->current_field = -1;
611 }
612
613 /* reset the counters */
614 dma_q->bytes_left_in_line = dev->width << 1;
615 dma_q->lines_completed = 0;
616}
617
618int cx231xx_do_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
619 u8 *p_buffer, u32 bytes_to_copy)
620{
621 u8 *p_out_buffer = NULL;
622 u32 current_line_bytes_copied = 0;
623 struct cx231xx_buffer *buf;
624 u32 _line_size = dev->width << 1;
625 void *startwrite;
626 int offset, lencopy;
627
628 buf = dev->video_mode.isoc_ctl.buf;
629
630 if (buf == NULL)
631 return -1;
632
633 p_out_buffer = videobuf_to_vmalloc(&buf->vb);
634
635 current_line_bytes_copied = _line_size - dma_q->bytes_left_in_line;
636
637 /* Offset field 2 one line from the top of the buffer */
638 offset = (dma_q->current_field == 1) ? 0 : _line_size;
639
640 /* Offset for field 2 */
641 startwrite = p_out_buffer + offset;
642
643 /* lines already completed in the current field */
644 startwrite += (dma_q->lines_completed * _line_size * 2);
645
646 /* bytes already completed in the current line */
647 startwrite += current_line_bytes_copied;
648
649 lencopy = dma_q->bytes_left_in_line > bytes_to_copy ?
650 bytes_to_copy : dma_q->bytes_left_in_line;
651
652 if ((u8 *)(startwrite + lencopy) > (u8 *)(p_out_buffer + buf->vb.size))
653 return 0;
654
655 /* The below copies the UYVY data straight into video buffer */
656 cx231xx_swab((u16 *) p_buffer, (u16 *) startwrite, (u16) lencopy);
657
658 return 0;
659}
660
661void cx231xx_swab(u16 *from, u16 *to, u16 len)
662{
663 u16 i;
664
665 if (len <= 0)
666 return;
667
668 for (i = 0; i < len / 2; i++)
669 to[i] = (from[i] << 8) | (from[i] >> 8);
670}
671
672u8 cx231xx_is_buffer_done(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q)
673{
674 u8 buffer_complete = 0;
675
676 /* Dual field stream */
677 buffer_complete = ((dma_q->current_field == 2) &&
678 (dma_q->lines_completed >= dma_q->lines_per_field) &&
679 dma_q->field1_done);
680
681 return buffer_complete;
682}
683
684/* ------------------------------------------------------------------
685 Videobuf operations
686 ------------------------------------------------------------------*/
687
688static int
689buffer_setup(struct videobuf_queue *vq, unsigned int *count, unsigned int *size)
690{
691 struct cx231xx_fh *fh = vq->priv_data;
692 struct cx231xx *dev = fh->dev;
693 struct v4l2_frequency f;
694
695 *size = (fh->dev->width * fh->dev->height * dev->format->depth + 7)>>3;
696 if (0 == *count)
697 *count = CX231XX_DEF_BUF;
698
699 if (*count < CX231XX_MIN_BUF)
700 *count = CX231XX_MIN_BUF;
701
702 /* Ask tuner to go to analog mode */
703 memset(&f, 0, sizeof(f));
704 f.frequency = dev->ctl_freq;
705 f.type = fh->radio ? V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
706
707 call_all(dev, tuner, s_frequency, &f);
708
709 return 0;
710}
711
712/* This is called *without* dev->slock held; please keep it that way */
713static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
714{
715 struct cx231xx_fh *fh = vq->priv_data;
716 struct cx231xx *dev = fh->dev;
717 unsigned long flags = 0;
718
719 if (in_interrupt())
720 BUG();
721
722 /* We used to wait for the buffer to finish here, but this didn't work
723 because, as we were keeping the state as VIDEOBUF_QUEUED,
724 videobuf_queue_cancel marked it as finished for us.
725 (Also, it could wedge forever if the hardware was misconfigured.)
726
727 This should be safe; by the time we get here, the buffer isn't
728 queued anymore. If we ever start marking the buffers as
729 VIDEOBUF_ACTIVE, it won't be, though.
730 */
731 spin_lock_irqsave(&dev->video_mode.slock, flags);
732 if (dev->video_mode.isoc_ctl.buf == buf)
733 dev->video_mode.isoc_ctl.buf = NULL;
734 spin_unlock_irqrestore(&dev->video_mode.slock, flags);
735
736 videobuf_vmalloc_free(&buf->vb);
737 buf->vb.state = VIDEOBUF_NEEDS_INIT;
738}
739
740static int
741buffer_prepare(struct videobuf_queue *vq, struct videobuf_buffer *vb,
742 enum v4l2_field field)
743{
744 struct cx231xx_fh *fh = vq->priv_data;
745 struct cx231xx_buffer *buf =
746 container_of(vb, struct cx231xx_buffer, vb);
747 struct cx231xx *dev = fh->dev;
748 int rc = 0, urb_init = 0;
749
750 /* The only currently supported format is 16 bits/pixel */
751 buf->vb.size = (fh->dev->width * fh->dev->height * dev->format->depth
752 + 7) >> 3;
753 if (0 != buf->vb.baddr && buf->vb.bsize < buf->vb.size)
754 return -EINVAL;
755
756 buf->vb.width = dev->width;
757 buf->vb.height = dev->height;
758 buf->vb.field = field;
759
760 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
761 rc = videobuf_iolock(vq, &buf->vb, NULL);
762 if (rc < 0)
763 goto fail;
764 }
765
766 if (!dev->video_mode.isoc_ctl.num_bufs)
767 urb_init = 1;
768
769 if (urb_init) {
770 rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
771 CX231XX_NUM_BUFS,
772 dev->video_mode.max_pkt_size,
773 cx231xx_isoc_copy);
774 if (rc < 0)
775 goto fail;
776 }
777
778 buf->vb.state = VIDEOBUF_PREPARED;
779 return 0;
780
781fail:
782 free_buffer(vq, buf);
783 return rc;
784}
785
786static void buffer_queue(struct videobuf_queue *vq, struct videobuf_buffer *vb)
787{
788 struct cx231xx_buffer *buf =
789 container_of(vb, struct cx231xx_buffer, vb);
790 struct cx231xx_fh *fh = vq->priv_data;
791 struct cx231xx *dev = fh->dev;
792 struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
793
794 buf->vb.state = VIDEOBUF_QUEUED;
795 list_add_tail(&buf->vb.queue, &vidq->active);
796
797}
798
799static void buffer_release(struct videobuf_queue *vq,
800 struct videobuf_buffer *vb)
801{
802 struct cx231xx_buffer *buf =
803 container_of(vb, struct cx231xx_buffer, vb);
804 struct cx231xx_fh *fh = vq->priv_data;
805 struct cx231xx *dev = (struct cx231xx *)fh->dev;
806
807 cx231xx_isocdbg("cx231xx: called buffer_release\n");
808
809 free_buffer(vq, buf);
810}
811
812static struct videobuf_queue_ops cx231xx_video_qops = {
813 .buf_setup = buffer_setup,
814 .buf_prepare = buffer_prepare,
815 .buf_queue = buffer_queue,
816 .buf_release = buffer_release,
817};
818
819/********************* v4l2 interface **************************************/
820
821void video_mux(struct cx231xx *dev, int index)
822{
823 dev->video_input = index;
824 dev->ctl_ainput = INPUT(index)->amux;
825
826 cx231xx_set_video_input_mux(dev, index);
827
828 cx25840_call(dev, video, s_routing, INPUT(index)->vmux, 0, 0);
829
830 cx231xx_set_audio_input(dev, dev->ctl_ainput);
831
832 cx231xx_info("video_mux : %d\n", index);
833
834 /* do mode control overrides if required */
835 cx231xx_do_mode_ctrl_overrides(dev);
836}
837
838/* Usage lock check functions */
839static int res_get(struct cx231xx_fh *fh)
840{
841 struct cx231xx *dev = fh->dev;
842 int rc = 0;
843
844 /* This instance already has stream_on */
845 if (fh->stream_on)
846 return rc;
847
848 if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
849 if (dev->stream_on)
850 return -EBUSY;
851 dev->stream_on = 1;
852 } else if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
853 if (dev->vbi_stream_on)
854 return -EBUSY;
855 dev->vbi_stream_on = 1;
856 } else
857 return -EINVAL;
858
859 fh->stream_on = 1;
860
861 return rc;
862}
863
864static int res_check(struct cx231xx_fh *fh)
865{
866 return fh->stream_on;
867}
868
869static void res_free(struct cx231xx_fh *fh)
870{
871 struct cx231xx *dev = fh->dev;
872
873 fh->stream_on = 0;
874
875 if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
876 dev->stream_on = 0;
877 if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE)
878 dev->vbi_stream_on = 0;
879}
880
881static int check_dev(struct cx231xx *dev)
882{
883 if (dev->state & DEV_DISCONNECTED) {
884 cx231xx_errdev("v4l2 ioctl: device not present\n");
885 return -ENODEV;
886 }
887
888 if (dev->state & DEV_MISCONFIGURED) {
889 cx231xx_errdev("v4l2 ioctl: device is misconfigured; "
890 "close and open it again\n");
891 return -EIO;
892 }
893 return 0;
894}
895
896void get_scale(struct cx231xx *dev,
897 unsigned int width, unsigned int height,
898 unsigned int *hscale, unsigned int *vscale)
899{
900 unsigned int maxw = norm_maxw(dev);
901 unsigned int maxh = norm_maxh(dev);
902
903 *hscale = (((unsigned long)maxw) << 12) / width - 4096L;
904 if (*hscale >= 0x4000)
905 *hscale = 0x3fff;
906
907 *vscale = (((unsigned long)maxh) << 12) / height - 4096L;
908 if (*vscale >= 0x4000)
909 *vscale = 0x3fff;
910
911 dev->hscale = *hscale;
912 dev->vscale = *vscale;
913
914}
915
916/* ------------------------------------------------------------------
917 IOCTL vidioc handling
918 ------------------------------------------------------------------*/
919
920static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
921 struct v4l2_format *f)
922{
923 struct cx231xx_fh *fh = priv;
924 struct cx231xx *dev = fh->dev;
925
926 mutex_lock(&dev->lock);
927
928 f->fmt.pix.width = dev->width;
929 f->fmt.pix.height = dev->height;
930 f->fmt.pix.pixelformat = dev->format->fourcc;;
931 f->fmt.pix.bytesperline = (dev->width * dev->format->depth + 7) >> 3;;
932 f->fmt.pix.sizeimage = f->fmt.pix.bytesperline * dev->height;
933 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
934
935 f->fmt.pix.field = V4L2_FIELD_INTERLACED;
936
937 mutex_unlock(&dev->lock);
938
939 return 0;
940}
941
942static struct cx231xx_fmt *format_by_fourcc(unsigned int fourcc)
943{
944 unsigned int i;
945
946 for (i = 0; i < ARRAY_SIZE(format); i++)
947 if (format[i].fourcc == fourcc)
948 return &format[i];
949
950 return NULL;
951}
952
953static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
954 struct v4l2_format *f)
955{
956 struct cx231xx_fh *fh = priv;
957 struct cx231xx *dev = fh->dev;
958 int width = f->fmt.pix.width;
959 int height = f->fmt.pix.height;
960 unsigned int maxw = norm_maxw(dev);
961 unsigned int maxh = norm_maxh(dev);
962 unsigned int hscale, vscale;
963 struct cx231xx_fmt *fmt;
964
965 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
966 if (!fmt) {
967 cx231xx_videodbg("Fourcc format (%08x) invalid.\n",
968 f->fmt.pix.pixelformat);
969 return -EINVAL;
970 }
971
972 /* width must even because of the YUYV format
973 height must be even because of interlacing */
974 height &= 0xfffe;
975 width &= 0xfffe;
976
977 if (unlikely(height < 32))
978 height = 32;
979 if (unlikely(height > maxh))
980 height = maxh;
981 if (unlikely(width < 48))
982 width = 48;
983 if (unlikely(width > maxw))
984 width = maxw;
985
986 get_scale(dev, width, height, &hscale, &vscale);
987
988 width = (((unsigned long)maxw) << 12) / (hscale + 4096L);
989 height = (((unsigned long)maxh) << 12) / (vscale + 4096L);
990
991 f->fmt.pix.width = width;
992 f->fmt.pix.height = height;
993 f->fmt.pix.pixelformat = fmt->fourcc;
994 f->fmt.pix.bytesperline = (dev->width * fmt->depth + 7) >> 3;
995 f->fmt.pix.sizeimage = f->fmt.pix.bytesperline * height;
996 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
997 f->fmt.pix.field = V4L2_FIELD_INTERLACED;
998
999 return 0;
1000}
1001
1002static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1003 struct v4l2_format *f)
1004{
1005 struct cx231xx_fh *fh = priv;
1006 struct cx231xx *dev = fh->dev;
1007 int rc;
1008 struct cx231xx_fmt *fmt;
1009
1010 rc = check_dev(dev);
1011 if (rc < 0)
1012 return rc;
1013
1014 mutex_lock(&dev->lock);
1015
1016 vidioc_try_fmt_vid_cap(file, priv, f);
1017
1018 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
1019 if (!fmt) {
1020 rc = -EINVAL;
1021 goto out;
1022 }
1023
1024 if (videobuf_queue_is_busy(&fh->vb_vidq)) {
1025 cx231xx_errdev("%s queue busy\n", __func__);
1026 rc = -EBUSY;
1027 goto out;
1028 }
1029
1030 if (dev->stream_on && !fh->stream_on) {
1031 cx231xx_errdev("%s device in use by another fh\n", __func__);
1032 rc = -EBUSY;
1033 goto out;
1034 }
1035
1036 /* set new image size */
1037 dev->width = f->fmt.pix.width;
1038 dev->height = f->fmt.pix.height;
1039 dev->format = fmt;
1040 get_scale(dev, dev->width, dev->height, &dev->hscale, &dev->vscale);
1041
1042 call_all(dev, video, s_fmt, f);
1043
1044 /* Set the correct alternate setting for this resolution */
1045 cx231xx_resolution_set(dev);
1046
1047out:
1048 mutex_unlock(&dev->lock);
1049 return rc;
1050}
1051
1052static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id * id)
1053{
1054 struct cx231xx_fh *fh = priv;
1055 struct cx231xx *dev = fh->dev;
1056
1057 *id = dev->norm;
1058 return 0;
1059}
1060
1061static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *norm)
1062{
1063 struct cx231xx_fh *fh = priv;
1064 struct cx231xx *dev = fh->dev;
1065 struct v4l2_format f;
1066 int rc;
1067
1068 rc = check_dev(dev);
1069 if (rc < 0)
1070 return rc;
1071
1072 cx231xx_info("vidioc_s_std : 0x%x\n", (unsigned int)*norm);
1073
1074 mutex_lock(&dev->lock);
1075 dev->norm = *norm;
1076
1077 /* Adjusts width/height, if needed */
1078 f.fmt.pix.width = dev->width;
1079 f.fmt.pix.height = dev->height;
1080 vidioc_try_fmt_vid_cap(file, priv, &f);
1081
1082 /* set new image size */
1083 dev->width = f.fmt.pix.width;
1084 dev->height = f.fmt.pix.height;
1085 get_scale(dev, dev->width, dev->height, &dev->hscale, &dev->vscale);
1086
1087 call_all(dev, core, s_std, dev->norm);
1088
1089 mutex_unlock(&dev->lock);
1090
1091 cx231xx_resolution_set(dev);
1092
1093 /* do mode control overrides */
1094 cx231xx_do_mode_ctrl_overrides(dev);
1095
1096 return 0;
1097}
1098
1099static const char *iname[] = {
1100 [CX231XX_VMUX_COMPOSITE1] = "Composite1",
1101 [CX231XX_VMUX_SVIDEO] = "S-Video",
1102 [CX231XX_VMUX_TELEVISION] = "Television",
1103 [CX231XX_VMUX_CABLE] = "Cable TV",
1104 [CX231XX_VMUX_DVB] = "DVB",
1105 [CX231XX_VMUX_DEBUG] = "for debug only",
1106};
1107
1108static int vidioc_enum_input(struct file *file, void *priv,
1109 struct v4l2_input *i)
1110{
1111 struct cx231xx_fh *fh = priv;
1112 struct cx231xx *dev = fh->dev;
1113 unsigned int n;
1114
1115 n = i->index;
1116 if (n >= MAX_CX231XX_INPUT)
1117 return -EINVAL;
1118 if (0 == INPUT(n)->type)
1119 return -EINVAL;
1120
1121 i->index = n;
1122 i->type = V4L2_INPUT_TYPE_CAMERA;
1123
1124 strcpy(i->name, iname[INPUT(n)->type]);
1125
1126 if ((CX231XX_VMUX_TELEVISION == INPUT(n)->type) ||
1127 (CX231XX_VMUX_CABLE == INPUT(n)->type))
1128 i->type = V4L2_INPUT_TYPE_TUNER;
1129
1130 i->std = dev->vdev->tvnorms;
1131
1132 return 0;
1133}
1134
1135static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1136{
1137 struct cx231xx_fh *fh = priv;
1138 struct cx231xx *dev = fh->dev;
1139
1140 *i = dev->video_input;
1141
1142 return 0;
1143}
1144
1145static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1146{
1147 struct cx231xx_fh *fh = priv;
1148 struct cx231xx *dev = fh->dev;
1149 int rc;
1150
1151 rc = check_dev(dev);
1152 if (rc < 0)
1153 return rc;
1154
1155 if (i >= MAX_CX231XX_INPUT)
1156 return -EINVAL;
1157 if (0 == INPUT(i)->type)
1158 return -EINVAL;
1159
1160 mutex_lock(&dev->lock);
1161
1162 video_mux(dev, i);
1163
1164 mutex_unlock(&dev->lock);
1165 return 0;
1166}
1167
1168static int vidioc_g_audio(struct file *file, void *priv, struct v4l2_audio *a)
1169{
1170 struct cx231xx_fh *fh = priv;
1171 struct cx231xx *dev = fh->dev;
1172
1173 switch (a->index) {
1174 case CX231XX_AMUX_VIDEO:
1175 strcpy(a->name, "Television");
1176 break;
1177 case CX231XX_AMUX_LINE_IN:
1178 strcpy(a->name, "Line In");
1179 break;
1180 default:
1181 return -EINVAL;
1182 }
1183
1184 a->index = dev->ctl_ainput;
1185 a->capability = V4L2_AUDCAP_STEREO;
1186
1187 return 0;
1188}
1189
1190static int vidioc_s_audio(struct file *file, void *priv, struct v4l2_audio *a)
1191{
1192 struct cx231xx_fh *fh = priv;
1193 struct cx231xx *dev = fh->dev;
1194 int status = 0;
1195
1196 /* Doesn't allow manual routing */
1197 if (a->index != dev->ctl_ainput)
1198 return -EINVAL;
1199
1200 dev->ctl_ainput = INPUT(a->index)->amux;
1201 status = cx231xx_set_audio_input(dev, dev->ctl_ainput);
1202
1203 return status;
1204}
1205
1206static int vidioc_queryctrl(struct file *file, void *priv,
1207 struct v4l2_queryctrl *qc)
1208{
1209 struct cx231xx_fh *fh = priv;
1210 struct cx231xx *dev = fh->dev;
1211 int id = qc->id;
1212 int i;
1213 int rc;
1214
1215 rc = check_dev(dev);
1216 if (rc < 0)
1217 return rc;
1218
1219 qc->id = v4l2_ctrl_next(ctrl_classes, qc->id);
1220 if (unlikely(qc->id == 0))
1221 return -EINVAL;
1222
1223 memset(qc, 0, sizeof(*qc));
1224
1225 qc->id = id;
1226
1227 if (qc->id < V4L2_CID_BASE || qc->id >= V4L2_CID_LASTP1)
1228 return -EINVAL;
1229
1230 for (i = 0; i < CX231XX_CTLS; i++)
1231 if (cx231xx_ctls[i].v.id == qc->id)
1232 break;
1233
1234 if (i == CX231XX_CTLS) {
1235 *qc = no_ctl;
1236 return 0;
1237 }
1238 *qc = cx231xx_ctls[i].v;
1239
1240 mutex_lock(&dev->lock);
1241 call_all(dev, core, queryctrl, qc);
1242 mutex_unlock(&dev->lock);
1243
1244 if (qc->type)
1245 return 0;
1246 else
1247 return -EINVAL;
1248}
1249
1250static int vidioc_g_ctrl(struct file *file, void *priv,
1251 struct v4l2_control *ctrl)
1252{
1253 struct cx231xx_fh *fh = priv;
1254 struct cx231xx *dev = fh->dev;
1255 int rc;
1256
1257 rc = check_dev(dev);
1258 if (rc < 0)
1259 return rc;
1260
1261 mutex_lock(&dev->lock);
1262 call_all(dev, core, g_ctrl, ctrl);
1263 mutex_unlock(&dev->lock);
1264 return rc;
1265}
1266
1267static int vidioc_s_ctrl(struct file *file, void *priv,
1268 struct v4l2_control *ctrl)
1269{
1270 struct cx231xx_fh *fh = priv;
1271 struct cx231xx *dev = fh->dev;
1272 int rc;
1273
1274 rc = check_dev(dev);
1275 if (rc < 0)
1276 return rc;
1277
1278 mutex_lock(&dev->lock);
1279 call_all(dev, core, s_ctrl, ctrl);
1280 mutex_unlock(&dev->lock);
1281 return rc;
1282}
1283
1284static int vidioc_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
1285{
1286 struct cx231xx_fh *fh = priv;
1287 struct cx231xx *dev = fh->dev;
1288 int rc;
1289
1290 rc = check_dev(dev);
1291 if (rc < 0)
1292 return rc;
1293
1294 if (0 != t->index)
1295 return -EINVAL;
1296
1297 strcpy(t->name, "Tuner");
1298
1299 t->type = V4L2_TUNER_ANALOG_TV;
1300 t->capability = V4L2_TUNER_CAP_NORM;
1301 t->rangehigh = 0xffffffffUL;
1302 t->signal = 0xffff; /* LOCKED */
1303
1304 return 0;
1305}
1306
1307static int vidioc_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
1308{
1309 struct cx231xx_fh *fh = priv;
1310 struct cx231xx *dev = fh->dev;
1311 int rc;
1312
1313 rc = check_dev(dev);
1314 if (rc < 0)
1315 return rc;
1316
1317 if (0 != t->index)
1318 return -EINVAL;
1319#if 0
1320 mutex_lock(&dev->lock);
1321 call_all(dev, tuner, s_tuner, t);
1322 mutex_unlock(&dev->lock);
1323#endif
1324 return 0;
1325}
1326
1327static int vidioc_g_frequency(struct file *file, void *priv,
1328 struct v4l2_frequency *f)
1329{
1330 struct cx231xx_fh *fh = priv;
1331 struct cx231xx *dev = fh->dev;
1332
1333 mutex_lock(&dev->lock);
1334 f->type = fh->radio ? V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
1335 f->frequency = dev->ctl_freq;
1336
1337 call_all(dev, tuner, g_frequency, f);
1338
1339 mutex_unlock(&dev->lock);
1340
1341 return 0;
1342}
1343
1344static int vidioc_s_frequency(struct file *file, void *priv,
1345 struct v4l2_frequency *f)
1346{
1347 struct cx231xx_fh *fh = priv;
1348 struct cx231xx *dev = fh->dev;
1349 int rc;
1350
1351 rc = check_dev(dev);
1352 if (rc < 0)
1353 return rc;
1354
1355 if (0 != f->tuner)
1356 return -EINVAL;
1357
1358 if (unlikely(0 == fh->radio && f->type != V4L2_TUNER_ANALOG_TV))
1359 return -EINVAL;
1360 if (unlikely(1 == fh->radio && f->type != V4L2_TUNER_RADIO))
1361 return -EINVAL;
1362
1363 /* set pre channel change settings in DIF first */
1364 rc = cx231xx_tuner_pre_channel_change(dev);
1365
1366 mutex_lock(&dev->lock);
1367
1368 dev->ctl_freq = f->frequency;
1369
1370 if (dev->tuner_type == TUNER_XC5000) {
1371 if (dev->cx231xx_set_analog_freq != NULL)
1372 dev->cx231xx_set_analog_freq(dev, f->frequency);
1373 } else
1374 call_all(dev, tuner, s_frequency, f);
1375
1376 mutex_unlock(&dev->lock);
1377
1378 /* set post channel change settings in DIF first */
1379 rc = cx231xx_tuner_post_channel_change(dev);
1380
1381 cx231xx_info("Set New FREQUENCY to %d\n", f->frequency);
1382
1383 return rc;
1384}
1385
1386#ifdef CONFIG_VIDEO_ADV_DEBUG
1387
1388/*
1389 -R, --list-registers=type=<host/i2cdrv/i2caddr>,
1390 chip=<chip>[,min=<addr>,max=<addr>]
1391 dump registers from <min> to <max> [VIDIOC_DBG_G_REGISTER]
1392 -r, --set-register=type=<host/i2cdrv/i2caddr>,
1393 chip=<chip>,reg=<addr>,val=<val>
1394 set the register [VIDIOC_DBG_S_REGISTER]
1395
1396 if type == host, then <chip> is the hosts chip ID (default 0)
1397 if type == i2cdrv (default), then <chip> is the I2C driver name or ID
1398 if type == i2caddr, then <chip> is the 7-bit I2C address
1399*/
1400
1401static int vidioc_g_register(struct file *file, void *priv,
1402 struct v4l2_dbg_register *reg)
1403{
1404 struct cx231xx_fh *fh = priv;
1405 struct cx231xx *dev = fh->dev;
1406 int ret = 0;
1407 u8 value[4] = { 0, 0, 0, 0 };
1408 u32 data = 0;
1409
1410 switch (reg->match.type) {
1411 case V4L2_CHIP_MATCH_HOST:
1412 switch (reg->match.addr) {
1413 case 0: /* Cx231xx - internal registers */
1414 ret = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1415 (u16)reg->reg, value, 4);
1416 reg->val = value[0] | value[1] << 8 |
1417 value[2] << 16 | value[3] << 24;
1418 break;
1419 case 1: /* AFE - read byte */
1420 ret = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
1421 (u16)reg->reg, 2, &data, 1);
1422 reg->val = le32_to_cpu(data & 0xff);
1423 break;
1424 case 14: /* AFE - read dword */
1425 ret = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
1426 (u16)reg->reg, 2, &data, 4);
1427 reg->val = le32_to_cpu(data);
1428 break;
1429 case 2: /* Video Block - read byte */
1430 ret = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
1431 (u16)reg->reg, 2, &data, 1);
1432 reg->val = le32_to_cpu(data & 0xff);
1433 break;
1434 case 24: /* Video Block - read dword */
1435 ret = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
1436 (u16)reg->reg, 2, &data, 4);
1437 reg->val = le32_to_cpu(data);
1438 break;
1439 case 3: /* I2S block - read byte */
1440 ret = cx231xx_read_i2c_data(dev,
1441 I2S_BLK_DEVICE_ADDRESS,
1442 (u16)reg->reg, 1,
1443 &data, 1);
1444 reg->val = le32_to_cpu(data & 0xff);
1445 break;
1446 case 34: /* I2S Block - read dword */
1447 ret =
1448 cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1449 (u16)reg->reg, 1, &data, 4);
1450 reg->val = le32_to_cpu(data);
1451 break;
1452 }
1453 return ret < 0 ? ret : 0;
1454
1455 case V4L2_CHIP_MATCH_I2C_DRIVER:
1456 call_all(dev, core, g_register, reg);
1457 return 0;
1458 case V4L2_CHIP_MATCH_I2C_ADDR:
1459 /* Not supported yet */
1460 return -EINVAL;
1461 default:
1462 if (!v4l2_chip_match_host(&reg->match))
1463 return -EINVAL;
1464 }
1465
1466 mutex_lock(&dev->lock);
1467 call_all(dev, core, g_register, reg);
1468 mutex_unlock(&dev->lock);
1469
1470 return ret;
1471}
1472
1473static int vidioc_s_register(struct file *file, void *priv,
1474 struct v4l2_dbg_register *reg)
1475{
1476 struct cx231xx_fh *fh = priv;
1477 struct cx231xx *dev = fh->dev;
1478 int ret = 0;
1479 __le64 buf;
1480 u32 value;
1481 u8 data[4] = { 0, 0, 0, 0 };
1482
1483 buf = cpu_to_le64(reg->val);
1484
1485 switch (reg->match.type) {
1486 case V4L2_CHIP_MATCH_HOST:
1487 {
1488 value = (u32) buf & 0xffffffff;
1489
1490 switch (reg->match.addr) {
1491 case 0: /* cx231xx internal registers */
1492 data[0] = (u8) value;
1493 data[1] = (u8) (value >> 8);
1494 data[2] = (u8) (value >> 16);
1495 data[3] = (u8) (value >> 24);
1496 ret = cx231xx_write_ctrl_reg(dev,
1497 VRT_SET_REGISTER,
1498 (u16)reg->reg, data,
1499 4);
1500 break;
1501 case 1: /* AFE - read byte */
1502 ret = cx231xx_write_i2c_data(dev,
1503 AFE_DEVICE_ADDRESS,
1504 (u16)reg->reg, 2,
1505 value, 1);
1506 break;
1507 case 14: /* AFE - read dword */
1508 ret = cx231xx_write_i2c_data(dev,
1509 AFE_DEVICE_ADDRESS,
1510 (u16)reg->reg, 2,
1511 value, 4);
1512 break;
1513 case 2: /* Video Block - read byte */
1514 ret =
1515 cx231xx_write_i2c_data(dev,
1516 VID_BLK_I2C_ADDRESS,
1517 (u16)reg->reg, 2,
1518 value, 1);
1519 break;
1520 case 24: /* Video Block - read dword */
1521 ret =
1522 cx231xx_write_i2c_data(dev,
1523 VID_BLK_I2C_ADDRESS,
1524 (u16)reg->reg, 2,
1525 value, 4);
1526 break;
1527 case 3: /* I2S block - read byte */
1528 ret =
1529 cx231xx_write_i2c_data(dev,
1530 I2S_BLK_DEVICE_ADDRESS,
1531 (u16)reg->reg, 1,
1532 value, 1);
1533 break;
1534 case 34: /* I2S block - read dword */
1535 ret =
1536 cx231xx_write_i2c_data(dev,
1537 I2S_BLK_DEVICE_ADDRESS,
1538 (u16)reg->reg, 1,
1539 value, 4);
1540 break;
1541 }
1542 }
1543 return ret < 0 ? ret : 0;
1544
1545 default:
1546 break;
1547 }
1548
1549 mutex_lock(&dev->lock);
1550 call_all(dev, core, s_register, reg);
1551 mutex_unlock(&dev->lock);
1552
1553 return ret;
1554}
1555#endif
1556
1557static int vidioc_cropcap(struct file *file, void *priv,
1558 struct v4l2_cropcap *cc)
1559{
1560 struct cx231xx_fh *fh = priv;
1561 struct cx231xx *dev = fh->dev;
1562
1563 if (cc->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1564 return -EINVAL;
1565
1566 cc->bounds.left = 0;
1567 cc->bounds.top = 0;
1568 cc->bounds.width = dev->width;
1569 cc->bounds.height = dev->height;
1570 cc->defrect = cc->bounds;
1571 cc->pixelaspect.numerator = 54; /* 4:3 FIXME: remove magic numbers */
1572 cc->pixelaspect.denominator = 59;
1573
1574 return 0;
1575}
1576
1577static int vidioc_streamon(struct file *file, void *priv,
1578 enum v4l2_buf_type type)
1579{
1580 struct cx231xx_fh *fh = priv;
1581 struct cx231xx *dev = fh->dev;
1582 int rc;
1583
1584 rc = check_dev(dev);
1585 if (rc < 0)
1586 return rc;
1587
1588 mutex_lock(&dev->lock);
1589 rc = res_get(fh);
1590
1591 if (likely(rc >= 0))
1592 rc = videobuf_streamon(&fh->vb_vidq);
1593
1594 call_all(dev, video, s_stream, 1);
1595
1596 mutex_unlock(&dev->lock);
1597
1598 return rc;
1599}
1600
1601static int vidioc_streamoff(struct file *file, void *priv,
1602 enum v4l2_buf_type type)
1603{
1604 struct cx231xx_fh *fh = priv;
1605 struct cx231xx *dev = fh->dev;
1606 int rc;
1607
1608 rc = check_dev(dev);
1609 if (rc < 0)
1610 return rc;
1611
1612 if ((fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1613 (fh->type != V4L2_BUF_TYPE_VBI_CAPTURE))
1614 return -EINVAL;
1615 if (type != fh->type)
1616 return -EINVAL;
1617
1618 mutex_lock(&dev->lock);
1619
1620 cx25840_call(dev, video, s_stream, 0);
1621
1622 videobuf_streamoff(&fh->vb_vidq);
1623 res_free(fh);
1624
1625 mutex_unlock(&dev->lock);
1626
1627 return 0;
1628}
1629
1630static int vidioc_querycap(struct file *file, void *priv,
1631 struct v4l2_capability *cap)
1632{
1633 struct cx231xx_fh *fh = priv;
1634 struct cx231xx *dev = fh->dev;
1635
1636 strlcpy(cap->driver, "cx231xx", sizeof(cap->driver));
1637 strlcpy(cap->card, cx231xx_boards[dev->model].name, sizeof(cap->card));
1638 usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info));
1639
1640 cap->version = CX231XX_VERSION_CODE;
1641
1642 cap->capabilities = V4L2_CAP_VBI_CAPTURE |
1643#if 0
1644 V4L2_CAP_SLICED_VBI_CAPTURE |
1645#endif
1646 V4L2_CAP_VIDEO_CAPTURE |
1647 V4L2_CAP_AUDIO |
1648 V4L2_CAP_READWRITE |
1649 V4L2_CAP_STREAMING;
1650
1651 if (dev->tuner_type != TUNER_ABSENT)
1652 cap->capabilities |= V4L2_CAP_TUNER;
1653
1654 return 0;
1655}
1656
1657static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1658 struct v4l2_fmtdesc *f)
1659{
1660 if (unlikely(f->index >= ARRAY_SIZE(format)))
1661 return -EINVAL;
1662
1663 strlcpy(f->description, format[f->index].name, sizeof(f->description));
1664 f->pixelformat = format[f->index].fourcc;
1665
1666 return 0;
1667}
1668
1669/* Sliced VBI ioctls */
1670static int vidioc_g_fmt_sliced_vbi_cap(struct file *file, void *priv,
1671 struct v4l2_format *f)
1672{
1673 struct cx231xx_fh *fh = priv;
1674 struct cx231xx *dev = fh->dev;
1675 int rc;
1676
1677 rc = check_dev(dev);
1678 if (rc < 0)
1679 return rc;
1680
1681 mutex_lock(&dev->lock);
1682
1683 f->fmt.sliced.service_set = 0;
1684
1685 call_all(dev, video, g_fmt, f);
1686
1687 if (f->fmt.sliced.service_set == 0)
1688 rc = -EINVAL;
1689
1690 mutex_unlock(&dev->lock);
1691 return rc;
1692}
1693
1694static int vidioc_try_set_sliced_vbi_cap(struct file *file, void *priv,
1695 struct v4l2_format *f)
1696{
1697 struct cx231xx_fh *fh = priv;
1698 struct cx231xx *dev = fh->dev;
1699 int rc;
1700
1701 rc = check_dev(dev);
1702 if (rc < 0)
1703 return rc;
1704
1705 mutex_lock(&dev->lock);
1706 call_all(dev, video, g_fmt, f);
1707 mutex_unlock(&dev->lock);
1708
1709 if (f->fmt.sliced.service_set == 0)
1710 return -EINVAL;
1711
1712 return 0;
1713}
1714
1715/* RAW VBI ioctls */
1716
1717static int vidioc_g_fmt_vbi_cap(struct file *file, void *priv,
1718 struct v4l2_format *f)
1719{
1720 struct cx231xx_fh *fh = priv;
1721 struct cx231xx *dev = fh->dev;
1722
1723 f->fmt.vbi.sampling_rate = (dev->norm & V4L2_STD_625_50) ?
1724 35468950 : 28636363;
1725 f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
1726 f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
1727 f->fmt.vbi.offset = 64 * 4;
1728 f->fmt.vbi.start[0] = (dev->norm & V4L2_STD_625_50) ?
1729 PAL_VBI_START_LINE : NTSC_VBI_START_LINE;
1730 f->fmt.vbi.count[0] = (dev->norm & V4L2_STD_625_50) ?
1731 PAL_VBI_LINES : NTSC_VBI_LINES;
1732 f->fmt.vbi.start[1] = (dev->norm & V4L2_STD_625_50) ?
1733 PAL_VBI_START_LINE + 312 : NTSC_VBI_START_LINE + 263;
1734 f->fmt.vbi.count[1] = f->fmt.vbi.count[0];
1735
1736 return 0;
1737
1738}
1739
1740static int vidioc_try_fmt_vbi_cap(struct file *file, void *priv,
1741 struct v4l2_format *f)
1742{
1743 struct cx231xx_fh *fh = priv;
1744 struct cx231xx *dev = fh->dev;
1745
1746 if (dev->vbi_stream_on && !fh->stream_on) {
1747 cx231xx_errdev("%s device in use by another fh\n", __func__);
1748 return -EBUSY;
1749 }
1750
1751 f->type = V4L2_BUF_TYPE_VBI_CAPTURE;
1752 f->fmt.vbi.sampling_rate = (dev->norm & V4L2_STD_625_50) ?
1753 35468950 : 28636363;
1754 f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
1755 f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
1756 f->fmt.vbi.offset = 244;
1757 f->fmt.vbi.flags = 0;
1758 f->fmt.vbi.start[0] = (dev->norm & V4L2_STD_625_50) ?
1759 PAL_VBI_START_LINE : NTSC_VBI_START_LINE;
1760 f->fmt.vbi.count[0] = (dev->norm & V4L2_STD_625_50) ?
1761 PAL_VBI_LINES : NTSC_VBI_LINES;
1762 f->fmt.vbi.start[1] = (dev->norm & V4L2_STD_625_50) ?
1763 PAL_VBI_START_LINE + 312 : NTSC_VBI_START_LINE + 263;
1764 f->fmt.vbi.count[1] = f->fmt.vbi.count[0];
1765
1766 return 0;
1767
1768}
1769
1770static int vidioc_reqbufs(struct file *file, void *priv,
1771 struct v4l2_requestbuffers *rb)
1772{
1773 struct cx231xx_fh *fh = priv;
1774 struct cx231xx *dev = fh->dev;
1775 int rc;
1776
1777 rc = check_dev(dev);
1778 if (rc < 0)
1779 return rc;
1780
1781 return videobuf_reqbufs(&fh->vb_vidq, rb);
1782}
1783
1784static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *b)
1785{
1786 struct cx231xx_fh *fh = priv;
1787 struct cx231xx *dev = fh->dev;
1788 int rc;
1789
1790 rc = check_dev(dev);
1791 if (rc < 0)
1792 return rc;
1793
1794 return videobuf_querybuf(&fh->vb_vidq, b);
1795}
1796
1797static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1798{
1799 struct cx231xx_fh *fh = priv;
1800 struct cx231xx *dev = fh->dev;
1801 int rc;
1802
1803 rc = check_dev(dev);
1804 if (rc < 0)
1805 return rc;
1806
1807 return videobuf_qbuf(&fh->vb_vidq, b);
1808}
1809
1810static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1811{
1812 struct cx231xx_fh *fh = priv;
1813 struct cx231xx *dev = fh->dev;
1814 int rc;
1815
1816 rc = check_dev(dev);
1817 if (rc < 0)
1818 return rc;
1819
1820 return videobuf_dqbuf(&fh->vb_vidq, b, file->f_flags & O_NONBLOCK);
1821}
1822
1823#ifdef CONFIG_VIDEO_V4L1_COMPAT
1824static int vidiocgmbuf(struct file *file, void *priv, struct video_mbuf *mbuf)
1825{
1826 struct cx231xx_fh *fh = priv;
1827
1828 return videobuf_cgmbuf(&fh->vb_vidq, mbuf, 8);
1829}
1830#endif
1831
1832/* ----------------------------------------------------------- */
1833/* RADIO ESPECIFIC IOCTLS */
1834/* ----------------------------------------------------------- */
1835
1836static int radio_querycap(struct file *file, void *priv,
1837 struct v4l2_capability *cap)
1838{
1839 struct cx231xx *dev = ((struct cx231xx_fh *)priv)->dev;
1840
1841 strlcpy(cap->driver, "cx231xx", sizeof(cap->driver));
1842 strlcpy(cap->card, cx231xx_boards[dev->model].name, sizeof(cap->card));
1843 usb_make_path(dev->udev, cap->bus_info, sizeof(cap->bus_info));
1844
1845 cap->version = CX231XX_VERSION_CODE;
1846 cap->capabilities = V4L2_CAP_TUNER;
1847 return 0;
1848}
1849
1850static int radio_g_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
1851{
1852 struct cx231xx *dev = ((struct cx231xx_fh *)priv)->dev;
1853
1854 if (unlikely(t->index > 0))
1855 return -EINVAL;
1856
1857 strcpy(t->name, "Radio");
1858 t->type = V4L2_TUNER_RADIO;
1859
1860 mutex_lock(&dev->lock);
1861 call_all(dev, tuner, s_tuner, t);
1862 mutex_unlock(&dev->lock);
1863
1864 return 0;
1865}
1866
1867static int radio_enum_input(struct file *file, void *priv, struct v4l2_input *i)
1868{
1869 if (i->index != 0)
1870 return -EINVAL;
1871 strcpy(i->name, "Radio");
1872 i->type = V4L2_INPUT_TYPE_TUNER;
1873
1874 return 0;
1875}
1876
1877static int radio_g_audio(struct file *file, void *priv, struct v4l2_audio *a)
1878{
1879 if (unlikely(a->index))
1880 return -EINVAL;
1881
1882 strcpy(a->name, "Radio");
1883 return 0;
1884}
1885
1886static int radio_s_tuner(struct file *file, void *priv, struct v4l2_tuner *t)
1887{
1888 struct cx231xx *dev = ((struct cx231xx_fh *)priv)->dev;
1889
1890 if (0 != t->index)
1891 return -EINVAL;
1892
1893 mutex_lock(&dev->lock);
1894 call_all(dev, tuner, s_tuner, t);
1895 mutex_unlock(&dev->lock);
1896
1897 return 0;
1898}
1899
1900static int radio_s_audio(struct file *file, void *fh, struct v4l2_audio *a)
1901{
1902 return 0;
1903}
1904
1905static int radio_s_input(struct file *file, void *fh, unsigned int i)
1906{
1907 return 0;
1908}
1909
1910static int radio_queryctrl(struct file *file, void *priv,
1911 struct v4l2_queryctrl *c)
1912{
1913 int i;
1914
1915 if (c->id < V4L2_CID_BASE || c->id >= V4L2_CID_LASTP1)
1916 return -EINVAL;
1917 if (c->id == V4L2_CID_AUDIO_MUTE) {
1918 for (i = 0; i < CX231XX_CTLS; i++)
1919 if (cx231xx_ctls[i].v.id == c->id)
1920 break;
1921 *c = cx231xx_ctls[i].v;
1922 } else
1923 *c = no_ctl;
1924 return 0;
1925}
1926
1927/*
1928 * cx231xx_v4l2_open()
1929 * inits the device and starts isoc transfer
1930 */
1931static int cx231xx_v4l2_open(struct file *filp)
1932{
1933 int minor = video_devdata(filp)->minor;
1934 int errCode = 0, radio = 0;
1935 struct cx231xx *dev = NULL;
1936 struct cx231xx_fh *fh;
1937 enum v4l2_buf_type fh_type = 0;
1938
1939 dev = cx231xx_get_device(minor, &fh_type, &radio);
1940 if (NULL == dev)
1941 return -ENODEV;
1942
1943 mutex_lock(&dev->lock);
1944
1945 cx231xx_videodbg("open minor=%d type=%s users=%d\n",
1946 minor, v4l2_type_names[fh_type], dev->users);
1947
1948#if 0
1949 errCode = cx231xx_set_mode(dev, CX231XX_ANALOG_MODE);
1950 if (errCode < 0) {
1951 cx231xx_errdev
1952 ("Device locked on digital mode. Can't open analog\n");
1953 mutex_unlock(&dev->lock);
1954 return -EBUSY;
1955 }
1956#endif
1957
1958 fh = kzalloc(sizeof(struct cx231xx_fh), GFP_KERNEL);
1959 if (!fh) {
1960 cx231xx_errdev("cx231xx-video.c: Out of memory?!\n");
1961 mutex_unlock(&dev->lock);
1962 return -ENOMEM;
1963 }
1964 fh->dev = dev;
1965 fh->radio = radio;
1966 fh->type = fh_type;
1967 filp->private_data = fh;
1968
1969 if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE && dev->users == 0) {
1970 dev->width = norm_maxw(dev);
1971 dev->height = norm_maxh(dev);
1972 dev->hscale = 0;
1973 dev->vscale = 0;
1974
1975 /* Power up in Analog TV mode */
1976 cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV);
1977
1978#if 0
1979 cx231xx_set_mode(dev, CX231XX_ANALOG_MODE);
1980#endif
1981 cx231xx_resolution_set(dev);
1982
1983 /* set video alternate setting */
1984 cx231xx_set_video_alternate(dev);
1985
1986 /* Needed, since GPIO might have disabled power of
1987 some i2c device */
1988 cx231xx_config_i2c(dev);
1989
1990 /* device needs to be initialized before isoc transfer */
1991 dev->video_input = dev->video_input > 2 ? 2 : dev->video_input;
1992 video_mux(dev, dev->video_input);
1993
1994 }
1995 if (fh->radio) {
1996 cx231xx_videodbg("video_open: setting radio device\n");
1997
1998 /* cx231xx_start_radio(dev); */
1999
2000 call_all(dev, tuner, s_radio);
2001 }
2002
2003 dev->users++;
2004
2005 if (fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
2006 videobuf_queue_vmalloc_init(&fh->vb_vidq, &cx231xx_video_qops,
2007 NULL, &dev->video_mode.slock,
2008 fh->type, V4L2_FIELD_INTERLACED,
2009 sizeof(struct cx231xx_buffer), fh);
2010 if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
2011 /* Set the required alternate setting VBI interface works in
2012 Bulk mode only */
2013 cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
2014
2015 videobuf_queue_vmalloc_init(&fh->vb_vidq, &cx231xx_vbi_qops,
2016 NULL, &dev->vbi_mode.slock,
2017 fh->type, V4L2_FIELD_SEQ_TB,
2018 sizeof(struct cx231xx_buffer), fh);
2019 }
2020
2021 mutex_unlock(&dev->lock);
2022
2023 return errCode;
2024}
2025
2026/*
2027 * cx231xx_realease_resources()
2028 * unregisters the v4l2,i2c and usb devices
2029 * called when the device gets disconected or at module unload
2030*/
2031void cx231xx_release_analog_resources(struct cx231xx *dev)
2032{
2033
2034 /*FIXME: I2C IR should be disconnected */
2035
2036 if (dev->radio_dev) {
2037 if (-1 != dev->radio_dev->minor)
2038 video_unregister_device(dev->radio_dev);
2039 else
2040 video_device_release(dev->radio_dev);
2041 dev->radio_dev = NULL;
2042 }
2043 if (dev->vbi_dev) {
2044 cx231xx_info("V4L2 device /dev/vbi%d deregistered\n",
2045 dev->vbi_dev->num);
2046 if (-1 != dev->vbi_dev->minor)
2047 video_unregister_device(dev->vbi_dev);
2048 else
2049 video_device_release(dev->vbi_dev);
2050 dev->vbi_dev = NULL;
2051 }
2052 if (dev->vdev) {
2053 cx231xx_info("V4L2 device /dev/video%d deregistered\n",
2054 dev->vdev->num);
2055 if (-1 != dev->vdev->minor)
2056 video_unregister_device(dev->vdev);
2057 else
2058 video_device_release(dev->vdev);
2059 dev->vdev = NULL;
2060 }
2061}
2062
2063/*
2064 * cx231xx_v4l2_close()
2065 * stops streaming and deallocates all resources allocated by the v4l2
2066 * calls and ioctls
2067 */
2068static int cx231xx_v4l2_close(struct file *filp)
2069{
2070 struct cx231xx_fh *fh = filp->private_data;
2071 struct cx231xx *dev = fh->dev;
2072
2073 cx231xx_videodbg("users=%d\n", dev->users);
2074
2075 mutex_lock(&dev->lock);
2076
2077 if (res_check(fh))
2078 res_free(fh);
2079
2080 if (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE) {
2081 videobuf_stop(&fh->vb_vidq);
2082 videobuf_mmap_free(&fh->vb_vidq);
2083
2084 /* the device is already disconnect,
2085 free the remaining resources */
2086 if (dev->state & DEV_DISCONNECTED) {
2087 cx231xx_release_resources(dev);
2088 mutex_unlock(&dev->lock);
2089 kfree(dev);
2090 return 0;
2091 }
2092
2093 /* do this before setting alternate! */
2094 cx231xx_uninit_vbi_isoc(dev);
2095
2096 /* set alternate 0 */
2097 if (!dev->vbi_or_sliced_cc_mode)
2098 cx231xx_set_alt_setting(dev, INDEX_VANC, 0);
2099 else
2100 cx231xx_set_alt_setting(dev, INDEX_HANC, 0);
2101
2102 kfree(fh);
2103 dev->users--;
2104 wake_up_interruptible_nr(&dev->open, 1);
2105 mutex_unlock(&dev->lock);
2106 return 0;
2107 }
2108
2109 if (dev->users == 1) {
2110 videobuf_stop(&fh->vb_vidq);
2111 videobuf_mmap_free(&fh->vb_vidq);
2112
2113 /* the device is already disconnect,
2114 free the remaining resources */
2115 if (dev->state & DEV_DISCONNECTED) {
2116 cx231xx_release_resources(dev);
2117 mutex_unlock(&dev->lock);
2118 kfree(dev);
2119 return 0;
2120 }
2121
2122 /* Save some power by putting tuner to sleep */
2123 call_all(dev, tuner, s_standby);
2124
2125 /* do this before setting alternate! */
2126 cx231xx_uninit_isoc(dev);
2127 cx231xx_set_mode(dev, CX231XX_SUSPEND);
2128
2129 /* set alternate 0 */
2130 cx231xx_set_alt_setting(dev, INDEX_VIDEO, 0);
2131 }
2132 kfree(fh);
2133 dev->users--;
2134 wake_up_interruptible_nr(&dev->open, 1);
2135 mutex_unlock(&dev->lock);
2136 return 0;
2137}
2138
2139/*
2140 * cx231xx_v4l2_read()
2141 * will allocate buffers when called for the first time
2142 */
2143static ssize_t
2144cx231xx_v4l2_read(struct file *filp, char __user *buf, size_t count,
2145 loff_t *pos)
2146{
2147 struct cx231xx_fh *fh = filp->private_data;
2148 struct cx231xx *dev = fh->dev;
2149 int rc;
2150
2151 rc = check_dev(dev);
2152 if (rc < 0)
2153 return rc;
2154
2155 if ((fh->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) ||
2156 (fh->type == V4L2_BUF_TYPE_VBI_CAPTURE)) {
2157 mutex_lock(&dev->lock);
2158 rc = res_get(fh);
2159 mutex_unlock(&dev->lock);
2160
2161 if (unlikely(rc < 0))
2162 return rc;
2163
2164 return videobuf_read_stream(&fh->vb_vidq, buf, count, pos, 0,
2165 filp->f_flags & O_NONBLOCK);
2166 }
2167 return 0;
2168}
2169
2170/*
2171 * cx231xx_v4l2_poll()
2172 * will allocate buffers when called for the first time
2173 */
2174static unsigned int cx231xx_v4l2_poll(struct file *filp, poll_table * wait)
2175{
2176 struct cx231xx_fh *fh = filp->private_data;
2177 struct cx231xx *dev = fh->dev;
2178 int rc;
2179
2180 rc = check_dev(dev);
2181 if (rc < 0)
2182 return rc;
2183
2184 mutex_lock(&dev->lock);
2185 rc = res_get(fh);
2186 mutex_unlock(&dev->lock);
2187
2188 if (unlikely(rc < 0))
2189 return POLLERR;
2190
2191 if ((V4L2_BUF_TYPE_VIDEO_CAPTURE == fh->type) ||
2192 (V4L2_BUF_TYPE_VBI_CAPTURE == fh->type))
2193 return videobuf_poll_stream(filp, &fh->vb_vidq, wait);
2194 else
2195 return POLLERR;
2196}
2197
2198/*
2199 * cx231xx_v4l2_mmap()
2200 */
2201static int cx231xx_v4l2_mmap(struct file *filp, struct vm_area_struct *vma)
2202{
2203 struct cx231xx_fh *fh = filp->private_data;
2204 struct cx231xx *dev = fh->dev;
2205 int rc;
2206
2207 rc = check_dev(dev);
2208 if (rc < 0)
2209 return rc;
2210
2211 mutex_lock(&dev->lock);
2212 rc = res_get(fh);
2213 mutex_unlock(&dev->lock);
2214
2215 if (unlikely(rc < 0))
2216 return rc;
2217
2218 rc = videobuf_mmap_mapper(&fh->vb_vidq, vma);
2219
2220 cx231xx_videodbg("vma start=0x%08lx, size=%ld, ret=%d\n",
2221 (unsigned long)vma->vm_start,
2222 (unsigned long)vma->vm_end -
2223 (unsigned long)vma->vm_start, rc);
2224
2225 return rc;
2226}
2227
2228static const struct v4l2_file_operations cx231xx_v4l_fops = {
2229 .owner = THIS_MODULE,
2230 .open = cx231xx_v4l2_open,
2231 .release = cx231xx_v4l2_close,
2232 .read = cx231xx_v4l2_read,
2233 .poll = cx231xx_v4l2_poll,
2234 .mmap = cx231xx_v4l2_mmap,
2235 .ioctl = video_ioctl2,
2236};
2237
2238static const struct v4l2_ioctl_ops video_ioctl_ops = {
2239 .vidioc_querycap = vidioc_querycap,
2240 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
2241 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
2242 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
2243 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
2244 .vidioc_g_fmt_vbi_cap = vidioc_g_fmt_vbi_cap,
2245 .vidioc_try_fmt_vbi_cap = vidioc_try_fmt_vbi_cap,
2246 .vidioc_s_fmt_vbi_cap = vidioc_try_fmt_vbi_cap,
2247 .vidioc_g_audio = vidioc_g_audio,
2248 .vidioc_s_audio = vidioc_s_audio,
2249 .vidioc_cropcap = vidioc_cropcap,
2250 .vidioc_g_fmt_sliced_vbi_cap = vidioc_g_fmt_sliced_vbi_cap,
2251 .vidioc_try_fmt_sliced_vbi_cap = vidioc_try_set_sliced_vbi_cap,
2252 .vidioc_reqbufs = vidioc_reqbufs,
2253 .vidioc_querybuf = vidioc_querybuf,
2254 .vidioc_qbuf = vidioc_qbuf,
2255 .vidioc_dqbuf = vidioc_dqbuf,
2256 .vidioc_s_std = vidioc_s_std,
2257 .vidioc_g_std = vidioc_g_std,
2258 .vidioc_enum_input = vidioc_enum_input,
2259 .vidioc_g_input = vidioc_g_input,
2260 .vidioc_s_input = vidioc_s_input,
2261 .vidioc_queryctrl = vidioc_queryctrl,
2262 .vidioc_g_ctrl = vidioc_g_ctrl,
2263 .vidioc_s_ctrl = vidioc_s_ctrl,
2264 .vidioc_streamon = vidioc_streamon,
2265 .vidioc_streamoff = vidioc_streamoff,
2266 .vidioc_g_tuner = vidioc_g_tuner,
2267 .vidioc_s_tuner = vidioc_s_tuner,
2268 .vidioc_g_frequency = vidioc_g_frequency,
2269 .vidioc_s_frequency = vidioc_s_frequency,
2270#ifdef CONFIG_VIDEO_ADV_DEBUG
2271 .vidioc_g_register = vidioc_g_register,
2272 .vidioc_s_register = vidioc_s_register,
2273#endif
2274#ifdef CONFIG_VIDEO_V4L1_COMPAT
2275 .vidiocgmbuf = vidiocgmbuf,
2276#endif
2277};
2278
2279static struct video_device cx231xx_vbi_template;
2280
2281static const struct video_device cx231xx_video_template = {
2282 .fops = &cx231xx_v4l_fops,
2283 .release = video_device_release,
2284 .ioctl_ops = &video_ioctl_ops,
2285 .minor = -1,
2286 .tvnorms = V4L2_STD_ALL,
2287 .current_norm = V4L2_STD_PAL,
2288};
2289
2290static const struct v4l2_file_operations radio_fops = {
2291 .owner = THIS_MODULE,
2292 .open = cx231xx_v4l2_open,
2293 .release = cx231xx_v4l2_close,
2294 .ioctl = video_ioctl2,
2295};
2296
2297static const struct v4l2_ioctl_ops radio_ioctl_ops = {
2298 .vidioc_querycap = radio_querycap,
2299 .vidioc_g_tuner = radio_g_tuner,
2300 .vidioc_enum_input = radio_enum_input,
2301 .vidioc_g_audio = radio_g_audio,
2302 .vidioc_s_tuner = radio_s_tuner,
2303 .vidioc_s_audio = radio_s_audio,
2304 .vidioc_s_input = radio_s_input,
2305 .vidioc_queryctrl = radio_queryctrl,
2306 .vidioc_g_ctrl = vidioc_g_ctrl,
2307 .vidioc_s_ctrl = vidioc_s_ctrl,
2308 .vidioc_g_frequency = vidioc_g_frequency,
2309 .vidioc_s_frequency = vidioc_s_frequency,
2310#ifdef CONFIG_VIDEO_ADV_DEBUG
2311 .vidioc_g_register = vidioc_g_register,
2312 .vidioc_s_register = vidioc_s_register,
2313#endif
2314};
2315
2316static struct video_device cx231xx_radio_template = {
2317 .name = "cx231xx-radio",
2318 .fops = &radio_fops,
2319 .ioctl_ops = &radio_ioctl_ops,
2320 .minor = -1,
2321};
2322
2323/******************************** usb interface ******************************/
2324
2325static struct video_device *cx231xx_vdev_init(struct cx231xx *dev,
2326 const struct video_device
2327 *template, const char *type_name)
2328{
2329 struct video_device *vfd;
2330
2331 vfd = video_device_alloc();
2332 if (NULL == vfd)
2333 return NULL;
2334
2335 *vfd = *template;
2336 vfd->minor = -1;
2337 vfd->v4l2_dev = &dev->v4l2_dev;
2338 vfd->release = video_device_release;
2339 vfd->debug = video_debug;
2340
2341 snprintf(vfd->name, sizeof(vfd->name), "%s %s", dev->name, type_name);
2342
2343 return vfd;
2344}
2345
2346int cx231xx_register_analog_devices(struct cx231xx *dev)
2347{
2348 int ret;
2349
2350 cx231xx_info("%s: v4l2 driver version %d.%d.%d\n",
2351 dev->name,
2352 (CX231XX_VERSION_CODE >> 16) & 0xff,
2353 (CX231XX_VERSION_CODE >> 8) & 0xff,
2354 CX231XX_VERSION_CODE & 0xff);
2355
2356 /* set default norm */
2357 /*dev->norm = cx231xx_video_template.current_norm; */
2358 dev->width = norm_maxw(dev);
2359 dev->height = norm_maxh(dev);
2360 dev->interlaced = 0;
2361 dev->hscale = 0;
2362 dev->vscale = 0;
2363
2364 /* Analog specific initialization */
2365 dev->format = &format[0];
2366 /* video_mux(dev, dev->video_input); */
2367
2368 /* Audio defaults */
2369 dev->mute = 1;
2370 dev->volume = 0x1f;
2371
2372 /* enable vbi capturing */
2373 /* write code here... */
2374
2375 /* allocate and fill video video_device struct */
2376 dev->vdev = cx231xx_vdev_init(dev, &cx231xx_video_template, "video");
2377 if (!dev->vdev) {
2378 cx231xx_errdev("cannot allocate video_device.\n");
2379 return -ENODEV;
2380 }
2381
2382 /* register v4l2 video video_device */
2383 ret = video_register_device(dev->vdev, VFL_TYPE_GRABBER,
2384 video_nr[dev->devno]);
2385 if (ret) {
2386 cx231xx_errdev("unable to register video device (error=%i).\n",
2387 ret);
2388 return ret;
2389 }
2390
2391 cx231xx_info("%s/0: registered device video%d [v4l2]\n",
2392 dev->name, dev->vdev->num);
2393
2394 /* Initialize VBI template */
2395 memcpy(&cx231xx_vbi_template, &cx231xx_video_template,
2396 sizeof(cx231xx_vbi_template));
2397 strcpy(cx231xx_vbi_template.name, "cx231xx-vbi");
2398
2399 /* Allocate and fill vbi video_device struct */
2400 dev->vbi_dev = cx231xx_vdev_init(dev, &cx231xx_vbi_template, "vbi");
2401
2402 /* register v4l2 vbi video_device */
2403 ret = video_register_device(dev->vbi_dev, VFL_TYPE_VBI,
2404 vbi_nr[dev->devno]);
2405 if (ret < 0) {
2406 cx231xx_errdev("unable to register vbi device\n");
2407 return ret;
2408 }
2409
2410 cx231xx_info("%s/0: registered device vbi%d\n",
2411 dev->name, dev->vbi_dev->num);
2412
2413 if (cx231xx_boards[dev->model].radio.type == CX231XX_RADIO) {
2414 dev->radio_dev = cx231xx_vdev_init(dev, &cx231xx_radio_template,
2415 "radio");
2416 if (!dev->radio_dev) {
2417 cx231xx_errdev("cannot allocate video_device.\n");
2418 return -ENODEV;
2419 }
2420 ret = video_register_device(dev->radio_dev, VFL_TYPE_RADIO,
2421 radio_nr[dev->devno]);
2422 if (ret < 0) {
2423 cx231xx_errdev("can't register radio device\n");
2424 return ret;
2425 }
2426 cx231xx_info("Registered radio device as /dev/radio%d\n",
2427 dev->radio_dev->num);
2428 }
2429
2430 cx231xx_info("V4L2 device registered as /dev/video%d and /dev/vbi%d\n",
2431 dev->vdev->num, dev->vbi_dev->num);
2432
2433 return 0;
2434}
diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h
new file mode 100644
index 000000000000..aa4a23ef491a
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx.h
@@ -0,0 +1,779 @@
1/*
2 cx231xx.h - driver for Conexant Cx23100/101/102 USB video capture devices
3
4 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
5 Based on em28xx driver
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _CX231XX_H
23#define _CX231XX_H
24
25#include <linux/videodev2.h>
26#include <linux/types.h>
27#include <linux/ioctl.h>
28#include <linux/i2c.h>
29#include <linux/i2c-algo-bit.h>
30#include <linux/mutex.h>
31
32
33#include <media/videobuf-vmalloc.h>
34#include <media/v4l2-device.h>
35#include <media/ir-kbd-i2c.h>
36#if defined(CONFIG_VIDEO_CX231XX_DVB) || \
37 defined(CONFIG_VIDEO_CX231XX_DVB_MODULE)
38#include <media/videobuf-dvb.h>
39#endif
40
41#include "cx231xx-reg.h"
42#include "cx231xx-pcb-cfg.h"
43#include "cx231xx-conf-reg.h"
44
45#define DRIVER_NAME "cx231xx"
46#define PWR_SLEEP_INTERVAL 5
47
48/* I2C addresses for control block in Cx231xx */
49#define AFE_DEVICE_ADDRESS 0x60
50#define I2S_BLK_DEVICE_ADDRESS 0x98
51#define VID_BLK_I2C_ADDRESS 0x88
52#define DIF_USE_BASEBAND 0xFFFFFFFF
53
54/* Boards supported by driver */
55#define CX231XX_BOARD_UNKNOWN 0
56#define CX231XX_BOARD_CNXT_RDE_250 1
57#define CX231XX_BOARD_CNXT_RDU_250 2
58
59/* Limits minimum and default number of buffers */
60#define CX231XX_MIN_BUF 4
61#define CX231XX_DEF_BUF 12
62#define CX231XX_DEF_VBI_BUF 6
63
64#define VBI_LINE_COUNT 17
65#define VBI_LINE_LENGTH 1440
66
67/*Limits the max URB message size */
68#define URB_MAX_CTRL_SIZE 80
69
70/* Params for validated field */
71#define CX231XX_BOARD_NOT_VALIDATED 1
72#define CX231XX_BOARD_VALIDATED 0
73
74/* maximum number of cx231xx boards */
75#define CX231XX_MAXBOARDS 8
76
77/* maximum number of frames that can be queued */
78#define CX231XX_NUM_FRAMES 5
79
80/* number of buffers for isoc transfers */
81#define CX231XX_NUM_BUFS 8
82
83/* number of packets for each buffer
84 windows requests only 40 packets .. so we better do the same
85 this is what I found out for all alternate numbers there!
86 */
87#define CX231XX_NUM_PACKETS 40
88
89/* default alternate; 0 means choose the best */
90#define CX231XX_PINOUT 0
91
92#define CX231XX_INTERLACED_DEFAULT 1
93
94/* time to wait when stopping the isoc transfer */
95#define CX231XX_URB_TIMEOUT \
96 msecs_to_jiffies(CX231XX_NUM_BUFS * CX231XX_NUM_PACKETS)
97
98enum cx231xx_mode {
99 CX231XX_SUSPEND,
100 CX231XX_ANALOG_MODE,
101 CX231XX_DIGITAL_MODE,
102};
103
104enum cx231xx_std_mode {
105 CX231XX_TV_AIR = 0,
106 CX231XX_TV_CABLE
107};
108
109enum cx231xx_stream_state {
110 STREAM_OFF,
111 STREAM_INTERRUPT,
112 STREAM_ON,
113};
114
115struct cx231xx;
116
117struct cx231xx_usb_isoc_ctl {
118 /* max packet size of isoc transaction */
119 int max_pkt_size;
120
121 /* number of allocated urbs */
122 int num_bufs;
123
124 /* urb for isoc transfers */
125 struct urb **urb;
126
127 /* transfer buffers for isoc transfer */
128 char **transfer_buffer;
129
130 /* Last buffer command and region */
131 u8 cmd;
132 int pos, size, pktsize;
133
134 /* Last field: ODD or EVEN? */
135 int field;
136
137 /* Stores incomplete commands */
138 u32 tmp_buf;
139 int tmp_buf_len;
140
141 /* Stores already requested buffers */
142 struct cx231xx_buffer *buf;
143
144 /* Stores the number of received fields */
145 int nfields;
146
147 /* isoc urb callback */
148 int (*isoc_copy) (struct cx231xx *dev, struct urb *urb);
149};
150
151struct cx231xx_fmt {
152 char *name;
153 u32 fourcc; /* v4l2 format id */
154 int depth;
155 int reg;
156};
157
158/* buffer for one video frame */
159struct cx231xx_buffer {
160 /* common v4l buffer stuff -- must be first */
161 struct videobuf_buffer vb;
162
163 struct list_head frame;
164 int top_field;
165 int receiving;
166};
167
168struct cx231xx_dmaqueue {
169 struct list_head active;
170 struct list_head queued;
171
172 wait_queue_head_t wq;
173
174 /* Counters to control buffer fill */
175 int pos;
176 u8 is_partial_line;
177 u8 partial_buf[8];
178 u8 last_sav;
179 int current_field;
180 u32 bytes_left_in_line;
181 u32 lines_completed;
182 u8 field1_done;
183 u32 lines_per_field;
184};
185
186/* inputs */
187
188#define MAX_CX231XX_INPUT 4
189
190enum cx231xx_itype {
191 CX231XX_VMUX_COMPOSITE1 = 1,
192 CX231XX_VMUX_SVIDEO,
193 CX231XX_VMUX_TELEVISION,
194 CX231XX_VMUX_CABLE,
195 CX231XX_RADIO,
196 CX231XX_VMUX_DVB,
197 CX231XX_VMUX_DEBUG
198};
199
200enum cx231xx_v_input {
201 CX231XX_VIN_1_1 = 0x1,
202 CX231XX_VIN_2_1,
203 CX231XX_VIN_3_1,
204 CX231XX_VIN_4_1,
205 CX231XX_VIN_1_2 = 0x01,
206 CX231XX_VIN_2_2,
207 CX231XX_VIN_3_2,
208 CX231XX_VIN_1_3 = 0x1,
209 CX231XX_VIN_2_3,
210 CX231XX_VIN_3_3,
211};
212
213/* cx231xx has two audio inputs: tuner and line in */
214enum cx231xx_amux {
215 /* This is the only entry for cx231xx tuner input */
216 CX231XX_AMUX_VIDEO, /* cx231xx tuner */
217 CX231XX_AMUX_LINE_IN, /* Line In */
218};
219
220struct cx231xx_reg_seq {
221 unsigned char bit;
222 unsigned char val;
223 int sleep;
224};
225
226struct cx231xx_input {
227 enum cx231xx_itype type;
228 unsigned int vmux;
229 enum cx231xx_amux amux;
230 struct cx231xx_reg_seq *gpio;
231};
232
233#define INPUT(nr) (&cx231xx_boards[dev->model].input[nr])
234
235enum cx231xx_decoder {
236 CX231XX_NODECODER,
237 CX231XX_AVDECODER
238};
239
240enum CX231XX_I2C_MASTER_PORT {
241 I2C_0 = 0,
242 I2C_1 = 1,
243 I2C_2 = 2,
244 I2C_3 = 3
245};
246
247struct cx231xx_board {
248 char *name;
249 int vchannels;
250 int tuner_type;
251 int tuner_addr;
252 v4l2_std_id norm; /* tv norm */
253
254 /* demod related */
255 int demod_addr;
256 u8 demod_xfer_mode; /* 0 - Serial; 1 - parallel */
257
258 /* GPIO Pins */
259 struct cx231xx_reg_seq *dvb_gpio;
260 struct cx231xx_reg_seq *suspend_gpio;
261 struct cx231xx_reg_seq *tuner_gpio;
262 u8 tuner_sif_gpio;
263 u8 tuner_scl_gpio;
264 u8 tuner_sda_gpio;
265
266 /* PIN ctrl */
267 u32 ctl_pin_status_mask;
268 u8 agc_analog_digital_select_gpio;
269 u32 gpio_pin_status_mask;
270
271 /* i2c masters */
272 u8 tuner_i2c_master;
273 u8 demod_i2c_master;
274
275 unsigned int max_range_640_480:1;
276 unsigned int has_dvb:1;
277 unsigned int valid:1;
278
279 unsigned char xclk, i2c_speed;
280
281 enum cx231xx_decoder decoder;
282
283 struct cx231xx_input input[MAX_CX231XX_INPUT];
284 struct cx231xx_input radio;
285 IR_KEYTAB_TYPE *ir_codes;
286};
287
288/* device states */
289enum cx231xx_dev_state {
290 DEV_INITIALIZED = 0x01,
291 DEV_DISCONNECTED = 0x02,
292 DEV_MISCONFIGURED = 0x04,
293};
294
295enum AFE_MODE {
296 AFE_MODE_LOW_IF,
297 AFE_MODE_BASEBAND,
298 AFE_MODE_EU_HI_IF,
299 AFE_MODE_US_HI_IF,
300 AFE_MODE_JAPAN_HI_IF
301};
302
303enum AUDIO_INPUT {
304 AUDIO_INPUT_MUTE,
305 AUDIO_INPUT_LINE,
306 AUDIO_INPUT_TUNER_TV,
307 AUDIO_INPUT_SPDIF,
308 AUDIO_INPUT_TUNER_FM
309};
310
311#define CX231XX_AUDIO_BUFS 5
312#define CX231XX_NUM_AUDIO_PACKETS 64
313#define CX231XX_CAPTURE_STREAM_EN 1
314#define CX231XX_STOP_AUDIO 0
315#define CX231XX_START_AUDIO 1
316
317/* cx231xx extensions */
318#define CX231XX_AUDIO 0x10
319#define CX231XX_DVB 0x20
320
321struct cx231xx_audio {
322 char name[50];
323 char *transfer_buffer[CX231XX_AUDIO_BUFS];
324 struct urb *urb[CX231XX_AUDIO_BUFS];
325 struct usb_device *udev;
326 unsigned int capture_transfer_done;
327 struct snd_pcm_substream *capture_pcm_substream;
328
329 unsigned int hwptr_done_capture;
330 struct snd_card *sndcard;
331
332 int users, shutdown;
333 enum cx231xx_stream_state capture_stream;
334 spinlock_t slock;
335
336 int alt; /* alternate */
337 int max_pkt_size; /* max packet size of isoc transaction */
338 int num_alt; /* Number of alternative settings */
339 unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
340 u16 end_point_addr;
341};
342
343struct cx231xx;
344
345struct cx231xx_fh {
346 struct cx231xx *dev;
347 unsigned int stream_on:1; /* Locks streams */
348 int radio;
349
350 struct videobuf_queue vb_vidq;
351
352 enum v4l2_buf_type type;
353};
354
355/*****************************************************************/
356/* set/get i2c */
357/* 00--1Mb/s, 01-400kb/s, 10--100kb/s, 11--5Mb/s */
358#define I2C_SPEED_1M 0x0
359#define I2C_SPEED_400K 0x1
360#define I2C_SPEED_100K 0x2
361#define I2C_SPEED_5M 0x3
362
363/* 0-- STOP transaction */
364#define I2C_STOP 0x0
365/* 1-- do not transmit STOP at end of transaction */
366#define I2C_NOSTOP 0x1
367/* 1--alllow slave to insert clock wait states */
368#define I2C_SYNC 0x1
369
370struct cx231xx_i2c {
371 struct cx231xx *dev;
372
373 int nr;
374
375 /* i2c i/o */
376 struct i2c_adapter i2c_adap;
377 struct i2c_algo_bit_data i2c_algo;
378 struct i2c_client i2c_client;
379 u32 i2c_rc;
380
381 /* different settings for each bus */
382 u8 i2c_period;
383 u8 i2c_nostop;
384 u8 i2c_reserve;
385};
386
387struct cx231xx_i2c_xfer_data {
388 u8 dev_addr;
389 u8 direction; /* 1 - IN, 0 - OUT */
390 u8 saddr_len; /* sub address len */
391 u16 saddr_dat; /* sub addr data */
392 u8 buf_size; /* buffer size */
393 u8 *p_buffer; /* pointer to the buffer */
394};
395
396struct VENDOR_REQUEST_IN {
397 u8 bRequest;
398 u16 wValue;
399 u16 wIndex;
400 u16 wLength;
401 u8 direction;
402 u8 bData;
403 u8 *pBuff;
404};
405
406struct cx231xx_ctrl {
407 struct v4l2_queryctrl v;
408 u32 off;
409 u32 reg;
410 u32 mask;
411 u32 shift;
412};
413
414enum TRANSFER_TYPE {
415 Raw_Video = 0,
416 Audio,
417 Vbi, /* VANC */
418 Sliced_cc, /* HANC */
419 TS1_serial_mode,
420 TS2,
421 TS1_parallel_mode
422} ;
423
424struct cx231xx_video_mode {
425 /* Isoc control struct */
426 struct cx231xx_dmaqueue vidq;
427 struct cx231xx_usb_isoc_ctl isoc_ctl;
428 spinlock_t slock;
429
430 /* usb transfer */
431 int alt; /* alternate */
432 int max_pkt_size; /* max packet size of isoc transaction */
433 int num_alt; /* Number of alternative settings */
434 unsigned int *alt_max_pkt_size; /* array of wMaxPacketSize */
435 u16 end_point_addr;
436};
437
438/* main device struct */
439struct cx231xx {
440 /* generic device properties */
441 char name[30]; /* name (including minor) of the device */
442 int model; /* index in the device_data struct */
443 int devno; /* marks the number of this device */
444
445 struct cx231xx_board board;
446
447 unsigned int stream_on:1; /* Locks streams */
448 unsigned int vbi_stream_on:1; /* Locks streams for VBI */
449 unsigned int has_audio_class:1;
450 unsigned int has_alsa_audio:1;
451
452 struct cx231xx_fmt *format;
453
454 struct v4l2_device v4l2_dev;
455 struct v4l2_subdev *sd_cx25840;
456 struct v4l2_subdev *sd_tuner;
457
458 struct cx231xx_IR *ir;
459
460 struct list_head devlist;
461
462 int tuner_type; /* type of the tuner */
463 int tuner_addr; /* tuner address */
464
465 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
466 struct cx231xx_i2c i2c_bus[3];
467 unsigned int xc_fw_load_done:1;
468 struct mutex gpio_i2c_lock;
469
470 /* video for linux */
471 int users; /* user count for exclusive use */
472 struct video_device *vdev; /* video for linux device struct */
473 v4l2_std_id norm; /* selected tv norm */
474 int ctl_freq; /* selected frequency */
475 unsigned int ctl_ainput; /* selected audio input */
476 int mute;
477 int volume;
478
479 /* frame properties */
480 int width; /* current frame width */
481 int height; /* current frame height */
482 unsigned hscale; /* horizontal scale factor (see datasheet) */
483 unsigned vscale; /* vertical scale factor (see datasheet) */
484 int interlaced; /* 1=interlace fileds, 0=just top fileds */
485
486 struct cx231xx_audio adev;
487
488 /* states */
489 enum cx231xx_dev_state state;
490
491 struct work_struct request_module_wk;
492
493 /* locks */
494 struct mutex lock;
495 struct mutex ctrl_urb_lock; /* protects urb_buf */
496 struct list_head inqueue, outqueue;
497 wait_queue_head_t open, wait_frame, wait_stream;
498 struct video_device *vbi_dev;
499 struct video_device *radio_dev;
500
501 unsigned char eedata[256];
502
503 struct cx231xx_video_mode video_mode;
504 struct cx231xx_video_mode vbi_mode;
505 struct cx231xx_video_mode sliced_cc_mode;
506 struct cx231xx_video_mode ts1_mode;
507
508 struct usb_device *udev; /* the usb device */
509 char urb_buf[URB_MAX_CTRL_SIZE]; /* urb control msg buffer */
510
511 /* helper funcs that call usb_control_msg */
512 int (*cx231xx_read_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg,
513 char *buf, int len);
514 int (*cx231xx_write_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg,
515 char *buf, int len);
516 int (*cx231xx_send_usb_command) (struct cx231xx_i2c *i2c_bus,
517 struct cx231xx_i2c_xfer_data *req_data);
518 int (*cx231xx_gpio_i2c_read) (struct cx231xx *dev, u8 dev_addr,
519 u8 *buf, u8 len);
520 int (*cx231xx_gpio_i2c_write) (struct cx231xx *dev, u8 dev_addr,
521 u8 *buf, u8 len);
522
523 int (*cx231xx_set_analog_freq) (struct cx231xx *dev, u32 freq);
524 int (*cx231xx_reset_analog_tuner) (struct cx231xx *dev);
525
526 enum cx231xx_mode mode;
527
528 struct cx231xx_dvb *dvb;
529
530 /* Cx231xx supported PCB config's */
531 struct pcb_config current_pcb_config;
532 u8 current_scenario_idx;
533 u8 interface_count;
534 u8 max_iad_interface_count;
535
536 /* GPIO related register direction and values */
537 u32 gpio_dir;
538 u32 gpio_val;
539
540 /* Power Modes */
541 int power_mode;
542
543 /* afe parameters */
544 enum AFE_MODE afe_mode;
545 u32 afe_ref_count;
546
547 /* video related parameters */
548 u32 video_input;
549 u32 active_mode;
550 u8 vbi_or_sliced_cc_mode; /* 0 - vbi ; 1 - sliced cc mode */
551 enum cx231xx_std_mode std_mode; /* 0 - Air; 1 - cable */
552
553};
554
555#define cx25840_call(cx231xx, o, f, args...) \
556 v4l2_subdev_call(cx231xx->sd_cx25840, o, f, ##args)
557#define tuner_call(cx231xx, o, f, args...) \
558 v4l2_subdev_call(cx231xx->sd_tuner, o, f, ##args)
559#define call_all(dev, o, f, args...) \
560 v4l2_device_call_until_err(&dev->v4l2_dev, 0, o, f, ##args)
561
562struct cx231xx_ops {
563 struct list_head next;
564 char *name;
565 int id;
566 int (*init) (struct cx231xx *);
567 int (*fini) (struct cx231xx *);
568};
569
570/* call back functions in dvb module */
571int cx231xx_set_analog_freq(struct cx231xx *dev, u32 freq);
572int cx231xx_reset_analog_tuner(struct cx231xx *dev);
573
574/* Provided by cx231xx-i2c.c */
575void cx231xx_do_i2c_scan(struct cx231xx *dev, struct i2c_client *c);
576int cx231xx_i2c_register(struct cx231xx_i2c *bus);
577int cx231xx_i2c_unregister(struct cx231xx_i2c *bus);
578
579/* Internal block control functions */
580int cx231xx_read_i2c_data(struct cx231xx *dev, u8 dev_addr,
581 u16 saddr, u8 saddr_len, u32 *data, u8 data_len);
582int cx231xx_write_i2c_data(struct cx231xx *dev, u8 dev_addr,
583 u16 saddr, u8 saddr_len, u32 data, u8 data_len);
584int cx231xx_reg_mask_write(struct cx231xx *dev, u8 dev_addr, u8 size,
585 u16 register_address, u8 bit_start, u8 bit_end,
586 u32 value);
587int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr,
588 u16 saddr, u32 mask, u32 value);
589u32 cx231xx_set_field(u32 field_mask, u32 data);
590
591/* afe related functions */
592int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count);
593int cx231xx_afe_init_channels(struct cx231xx *dev);
594int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev);
595int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux);
596int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode);
597int cx231xx_afe_update_power_control(struct cx231xx *dev,
598 enum AV_MODE avmode);
599int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input);
600
601/* i2s block related functions */
602int cx231xx_i2s_blk_initialize(struct cx231xx *dev);
603int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
604 enum AV_MODE avmode);
605int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input);
606
607/* DIF related functions */
608int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
609 u32 function_mode, u32 standard);
610int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard);
611int cx231xx_tuner_pre_channel_change(struct cx231xx *dev);
612int cx231xx_tuner_post_channel_change(struct cx231xx *dev);
613
614/* video parser functions */
615u8 cx231xx_find_next_SAV_EAV(u8 *p_buffer, u32 buffer_size,
616 u32 *p_bytes_used);
617u8 cx231xx_find_boundary_SAV_EAV(u8 *p_buffer, u8 *partial_buf,
618 u32 *p_bytes_used);
619int cx231xx_do_copy(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
620 u8 *p_buffer, u32 bytes_to_copy);
621void cx231xx_reset_video_buffer(struct cx231xx *dev,
622 struct cx231xx_dmaqueue *dma_q);
623u8 cx231xx_is_buffer_done(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q);
624u32 cx231xx_copy_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
625 u8 *p_line, u32 length, int field_number);
626u32 cx231xx_get_video_line(struct cx231xx *dev, struct cx231xx_dmaqueue *dma_q,
627 u8 sav_eav, u8 *p_buffer, u32 buffer_size);
628void cx231xx_swab(u16 *from, u16 *to, u16 len);
629
630/* Provided by cx231xx-core.c */
631
632u32 cx231xx_request_buffers(struct cx231xx *dev, u32 count);
633void cx231xx_queue_unusedframes(struct cx231xx *dev);
634void cx231xx_release_buffers(struct cx231xx *dev);
635
636/* read from control pipe */
637int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
638 char *buf, int len);
639
640/* write to control pipe */
641int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
642 char *buf, int len);
643int cx231xx_mode_register(struct cx231xx *dev, u16 address, u32 mode);
644
645int cx231xx_send_vendor_cmd(struct cx231xx *dev,
646 struct VENDOR_REQUEST_IN *ven_req);
647int cx231xx_send_usb_command(struct cx231xx_i2c *i2c_bus,
648 struct cx231xx_i2c_xfer_data *req_data);
649
650/* Gpio related functions */
651int cx231xx_send_gpio_cmd(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val,
652 u8 len, u8 request, u8 direction);
653int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val);
654int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val);
655int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value);
656int cx231xx_set_gpio_direction(struct cx231xx *dev, int pin_number,
657 int pin_value);
658
659int cx231xx_gpio_i2c_start(struct cx231xx *dev);
660int cx231xx_gpio_i2c_end(struct cx231xx *dev);
661int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data);
662int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf);
663int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev);
664int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev);
665int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev);
666
667int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len);
668int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len);
669
670/* audio related functions */
671int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
672 enum AUDIO_INPUT audio_input);
673
674int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type);
675int cx231xx_resolution_set(struct cx231xx *dev);
676int cx231xx_set_video_alternate(struct cx231xx *dev);
677int cx231xx_set_alt_setting(struct cx231xx *dev, u8 index, u8 alt);
678int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
679 int num_bufs, int max_pkt_size,
680 int (*isoc_copy) (struct cx231xx *dev,
681 struct urb *urb));
682void cx231xx_uninit_isoc(struct cx231xx *dev);
683int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode);
684int cx231xx_gpio_set(struct cx231xx *dev, struct cx231xx_reg_seq *gpio);
685
686/* Device list functions */
687void cx231xx_release_resources(struct cx231xx *dev);
688void cx231xx_release_analog_resources(struct cx231xx *dev);
689int cx231xx_register_analog_devices(struct cx231xx *dev);
690void cx231xx_remove_from_devlist(struct cx231xx *dev);
691void cx231xx_add_into_devlist(struct cx231xx *dev);
692struct cx231xx *cx231xx_get_device(int minor,
693 enum v4l2_buf_type *fh_type, int *has_radio);
694void cx231xx_init_extension(struct cx231xx *dev);
695void cx231xx_close_extension(struct cx231xx *dev);
696
697/* hardware init functions */
698int cx231xx_dev_init(struct cx231xx *dev);
699void cx231xx_dev_uninit(struct cx231xx *dev);
700void cx231xx_config_i2c(struct cx231xx *dev);
701int cx231xx_config(struct cx231xx *dev);
702
703/* Stream control functions */
704int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask);
705int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask);
706
707int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type);
708
709/* Power control functions */
710int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode);
711int cx231xx_power_suspend(struct cx231xx *dev);
712
713/* chip specific control functions */
714int cx231xx_init_ctrl_pin_status(struct cx231xx *dev);
715int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
716 u8 analog_or_digital);
717int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex);
718
719/* video audio decoder related functions */
720void video_mux(struct cx231xx *dev, int index);
721int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input);
722int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input);
723int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev);
724int cx231xx_set_audio_input(struct cx231xx *dev, u8 input);
725void get_scale(struct cx231xx *dev,
726 unsigned int width, unsigned int height,
727 unsigned int *hscale, unsigned int *vscale);
728
729/* Provided by cx231xx-video.c */
730int cx231xx_register_extension(struct cx231xx_ops *dev);
731void cx231xx_unregister_extension(struct cx231xx_ops *dev);
732void cx231xx_init_extension(struct cx231xx *dev);
733void cx231xx_close_extension(struct cx231xx *dev);
734
735/* Provided by cx231xx-cards.c */
736extern void cx231xx_pre_card_setup(struct cx231xx *dev);
737extern void cx231xx_card_setup(struct cx231xx *dev);
738extern struct cx231xx_board cx231xx_boards[];
739extern struct usb_device_id cx231xx_id_table[];
740extern const unsigned int cx231xx_bcount;
741void cx231xx_set_ir(struct cx231xx *dev, struct IR_i2c *ir);
742int cx231xx_tuner_callback(void *ptr, int component, int command, int arg);
743
744/* Provided by cx231xx-input.c */
745int cx231xx_ir_init(struct cx231xx *dev);
746int cx231xx_ir_fini(struct cx231xx *dev);
747
748/* printk macros */
749
750#define cx231xx_err(fmt, arg...) do {\
751 printk(KERN_ERR fmt , ##arg); } while (0)
752
753#define cx231xx_errdev(fmt, arg...) do {\
754 printk(KERN_ERR "%s: "fmt,\
755 dev->name , ##arg); } while (0)
756
757#define cx231xx_info(fmt, arg...) do {\
758 printk(KERN_INFO "%s: "fmt,\
759 dev->name , ##arg); } while (0)
760#define cx231xx_warn(fmt, arg...) do {\
761 printk(KERN_WARNING "%s: "fmt,\
762 dev->name , ##arg); } while (0)
763
764static inline unsigned int norm_maxw(struct cx231xx *dev)
765{
766 if (dev->board.max_range_640_480)
767 return 640;
768 else
769 return 720;
770}
771
772static inline unsigned int norm_maxh(struct cx231xx *dev)
773{
774 if (dev->board.max_range_640_480)
775 return 480;
776 else
777 return (dev->norm & V4L2_STD_625_50) ? 576 : 480;
778}
779#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 16:01:11 -0500