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path: root/drivers/media/video/cx18/cx18-mailbox.c
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Diffstat (limited to 'drivers/media/video/cx18/cx18-mailbox.c')
-rw-r--r--drivers/media/video/cx18/cx18-mailbox.c46
1 files changed, 25 insertions, 21 deletions
diff --git a/drivers/media/video/cx18/cx18-mailbox.c b/drivers/media/video/cx18/cx18-mailbox.c
index 2a5ccef9185b..9d18dd22de76 100644
--- a/drivers/media/video/cx18/cx18-mailbox.c
+++ b/drivers/media/video/cx18/cx18-mailbox.c
@@ -22,6 +22,7 @@
22#include <stdarg.h> 22#include <stdarg.h>
23 23
24#include "cx18-driver.h" 24#include "cx18-driver.h"
25#include "cx18-io.h"
25#include "cx18-scb.h" 26#include "cx18-scb.h"
26#include "cx18-irq.h" 27#include "cx18-irq.h"
27#include "cx18-mailbox.h" 28#include "cx18-mailbox.h"
@@ -81,6 +82,8 @@ static const struct cx18_api_info api_info[] = {
81 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0), 82 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
82 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0), 83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
83 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST), 84 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
85 API_ENTRY(CPU, CX18_APU_RESETAI, API_FAST),
86 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, 0),
84 API_ENTRY(0, 0, 0), 87 API_ENTRY(0, 0, 0),
85}; 88};
86 89
@@ -104,20 +107,20 @@ static struct cx18_mailbox __iomem *cx18_mb_is_complete(struct cx18 *cx, int rpu
104 switch (rpu) { 107 switch (rpu) {
105 case APU: 108 case APU:
106 mb = &cx->scb->epu2apu_mb; 109 mb = &cx->scb->epu2apu_mb;
107 *state = readl(&cx->scb->apu_state); 110 *state = cx18_readl(cx, &cx->scb->apu_state);
108 *irq = readl(&cx->scb->epu2apu_irq); 111 *irq = cx18_readl(cx, &cx->scb->epu2apu_irq);
109 break; 112 break;
110 113
111 case CPU: 114 case CPU:
112 mb = &cx->scb->epu2cpu_mb; 115 mb = &cx->scb->epu2cpu_mb;
113 *state = readl(&cx->scb->cpu_state); 116 *state = cx18_readl(cx, &cx->scb->cpu_state);
114 *irq = readl(&cx->scb->epu2cpu_irq); 117 *irq = cx18_readl(cx, &cx->scb->epu2cpu_irq);
115 break; 118 break;
116 119
117 case HPU: 120 case HPU:
118 mb = &cx->scb->epu2hpu_mb; 121 mb = &cx->scb->epu2hpu_mb;
119 *state = readl(&cx->scb->hpu_state); 122 *state = cx18_readl(cx, &cx->scb->hpu_state);
120 *irq = readl(&cx->scb->epu2hpu_irq); 123 *irq = cx18_readl(cx, &cx->scb->epu2hpu_irq);
121 break; 124 break;
122 } 125 }
123 126
@@ -125,8 +128,8 @@ static struct cx18_mailbox __iomem *cx18_mb_is_complete(struct cx18 *cx, int rpu
125 return mb; 128 return mb;
126 129
127 do { 130 do {
128 *req = readl(&mb->request); 131 *req = cx18_readl(cx, &mb->request);
129 ack = readl(&mb->ack); 132 ack = cx18_readl(cx, &mb->ack);
130 wait_count++; 133 wait_count++;
131 } while (*req != ack && wait_count < 600); 134 } while (*req != ack && wait_count < 600);
132 135
@@ -171,9 +174,9 @@ long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb)
171 return -EINVAL; 174 return -EINVAL;
172 } 175 }
173 176
174 setup_page(SCB_OFFSET); 177 cx18_setup_page(cx, SCB_OFFSET);
175 write_sync(mb->request, &ack_mb->ack); 178 cx18_write_sync(cx, mb->request, &ack_mb->ack);
176 write_reg(ack_irq, SW2_INT_SET); 179 cx18_write_reg(cx, ack_irq, SW2_INT_SET);
177 return 0; 180 return 0;
178} 181}
179 182
@@ -198,7 +201,7 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
198 CX18_DEBUG_HI_API("%s\n", info->name); 201 CX18_DEBUG_HI_API("%s\n", info->name);
199 else 202 else
200 CX18_DEBUG_API("%s\n", info->name); 203 CX18_DEBUG_API("%s\n", info->name);
201 setup_page(SCB_OFFSET); 204 cx18_setup_page(cx, SCB_OFFSET);
202 mb = cx18_mb_is_complete(cx, info->rpu, &state, &irq, &req); 205 mb = cx18_mb_is_complete(cx, info->rpu, &state, &irq, &req);
203 206
204 if (mb == NULL) { 207 if (mb == NULL) {
@@ -207,11 +210,11 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
207 } 210 }
208 211
209 oldreq = req - 1; 212 oldreq = req - 1;
210 writel(cmd, &mb->cmd); 213 cx18_writel(cx, cmd, &mb->cmd);
211 for (i = 0; i < args; i++) 214 for (i = 0; i < args; i++)
212 writel(data[i], &mb->args[i]); 215 cx18_writel(cx, data[i], &mb->args[i]);
213 writel(0, &mb->error); 216 cx18_writel(cx, 0, &mb->error);
214 writel(req, &mb->request); 217 cx18_writel(cx, req, &mb->request);
215 218
216 switch (info->rpu) { 219 switch (info->rpu) {
217 case APU: waitq = &cx->mb_apu_waitq; break; 220 case APU: waitq = &cx->mb_apu_waitq; break;
@@ -222,9 +225,10 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
222 } 225 }
223 if (info->flags & API_FAST) 226 if (info->flags & API_FAST)
224 timeout /= 2; 227 timeout /= 2;
225 write_reg(irq, SW1_INT_SET); 228 cx18_write_reg(cx, irq, SW1_INT_SET);
226 229
227 while (!sig && readl(&mb->ack) != readl(&mb->request) && cnt < 660) { 230 while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request)
231 && cnt < 660) {
228 if (cnt > 200 && !in_atomic()) 232 if (cnt > 200 && !in_atomic())
229 sig = cx18_msleep_timeout(10, 1); 233 sig = cx18_msleep_timeout(10, 1);
230 cnt++; 234 cnt++;
@@ -232,13 +236,13 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
232 if (sig) 236 if (sig)
233 return -EINTR; 237 return -EINTR;
234 if (cnt == 660) { 238 if (cnt == 660) {
235 writel(oldreq, &mb->request); 239 cx18_writel(cx, oldreq, &mb->request);
236 CX18_ERR("mb %s failed\n", info->name); 240 CX18_ERR("mb %s failed\n", info->name);
237 return -EINVAL; 241 return -EINVAL;
238 } 242 }
239 for (i = 0; i < MAX_MB_ARGUMENTS; i++) 243 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
240 data[i] = readl(&mb->args[i]); 244 data[i] = cx18_readl(cx, &mb->args[i]);
241 err = readl(&mb->error); 245 err = cx18_readl(cx, &mb->error);
242 if (!in_atomic() && (info->flags & API_SLOW)) 246 if (!in_atomic() && (info->flags & API_SLOW))
243 cx18_msleep_timeout(300, 0); 247 cx18_msleep_timeout(300, 0);
244 if (err) 248 if (err)