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path: root/drivers/media/video/cx18/cx18-mailbox.c
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Diffstat (limited to 'drivers/media/video/cx18/cx18-mailbox.c')
-rw-r--r--drivers/media/video/cx18/cx18-mailbox.c44
1 files changed, 23 insertions, 21 deletions
diff --git a/drivers/media/video/cx18/cx18-mailbox.c b/drivers/media/video/cx18/cx18-mailbox.c
index 1b9fbf9a6bc5..9d18dd22de76 100644
--- a/drivers/media/video/cx18/cx18-mailbox.c
+++ b/drivers/media/video/cx18/cx18-mailbox.c
@@ -22,6 +22,7 @@
22#include <stdarg.h> 22#include <stdarg.h>
23 23
24#include "cx18-driver.h" 24#include "cx18-driver.h"
25#include "cx18-io.h"
25#include "cx18-scb.h" 26#include "cx18-scb.h"
26#include "cx18-irq.h" 27#include "cx18-irq.h"
27#include "cx18-mailbox.h" 28#include "cx18-mailbox.h"
@@ -106,20 +107,20 @@ static struct cx18_mailbox __iomem *cx18_mb_is_complete(struct cx18 *cx, int rpu
106 switch (rpu) { 107 switch (rpu) {
107 case APU: 108 case APU:
108 mb = &cx->scb->epu2apu_mb; 109 mb = &cx->scb->epu2apu_mb;
109 *state = readl(&cx->scb->apu_state); 110 *state = cx18_readl(cx, &cx->scb->apu_state);
110 *irq = readl(&cx->scb->epu2apu_irq); 111 *irq = cx18_readl(cx, &cx->scb->epu2apu_irq);
111 break; 112 break;
112 113
113 case CPU: 114 case CPU:
114 mb = &cx->scb->epu2cpu_mb; 115 mb = &cx->scb->epu2cpu_mb;
115 *state = readl(&cx->scb->cpu_state); 116 *state = cx18_readl(cx, &cx->scb->cpu_state);
116 *irq = readl(&cx->scb->epu2cpu_irq); 117 *irq = cx18_readl(cx, &cx->scb->epu2cpu_irq);
117 break; 118 break;
118 119
119 case HPU: 120 case HPU:
120 mb = &cx->scb->epu2hpu_mb; 121 mb = &cx->scb->epu2hpu_mb;
121 *state = readl(&cx->scb->hpu_state); 122 *state = cx18_readl(cx, &cx->scb->hpu_state);
122 *irq = readl(&cx->scb->epu2hpu_irq); 123 *irq = cx18_readl(cx, &cx->scb->epu2hpu_irq);
123 break; 124 break;
124 } 125 }
125 126
@@ -127,8 +128,8 @@ static struct cx18_mailbox __iomem *cx18_mb_is_complete(struct cx18 *cx, int rpu
127 return mb; 128 return mb;
128 129
129 do { 130 do {
130 *req = readl(&mb->request); 131 *req = cx18_readl(cx, &mb->request);
131 ack = readl(&mb->ack); 132 ack = cx18_readl(cx, &mb->ack);
132 wait_count++; 133 wait_count++;
133 } while (*req != ack && wait_count < 600); 134 } while (*req != ack && wait_count < 600);
134 135
@@ -173,9 +174,9 @@ long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb)
173 return -EINVAL; 174 return -EINVAL;
174 } 175 }
175 176
176 setup_page(SCB_OFFSET); 177 cx18_setup_page(cx, SCB_OFFSET);
177 write_sync(mb->request, &ack_mb->ack); 178 cx18_write_sync(cx, mb->request, &ack_mb->ack);
178 write_reg(ack_irq, SW2_INT_SET); 179 cx18_write_reg(cx, ack_irq, SW2_INT_SET);
179 return 0; 180 return 0;
180} 181}
181 182
@@ -200,7 +201,7 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
200 CX18_DEBUG_HI_API("%s\n", info->name); 201 CX18_DEBUG_HI_API("%s\n", info->name);
201 else 202 else
202 CX18_DEBUG_API("%s\n", info->name); 203 CX18_DEBUG_API("%s\n", info->name);
203 setup_page(SCB_OFFSET); 204 cx18_setup_page(cx, SCB_OFFSET);
204 mb = cx18_mb_is_complete(cx, info->rpu, &state, &irq, &req); 205 mb = cx18_mb_is_complete(cx, info->rpu, &state, &irq, &req);
205 206
206 if (mb == NULL) { 207 if (mb == NULL) {
@@ -209,11 +210,11 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
209 } 210 }
210 211
211 oldreq = req - 1; 212 oldreq = req - 1;
212 writel(cmd, &mb->cmd); 213 cx18_writel(cx, cmd, &mb->cmd);
213 for (i = 0; i < args; i++) 214 for (i = 0; i < args; i++)
214 writel(data[i], &mb->args[i]); 215 cx18_writel(cx, data[i], &mb->args[i]);
215 writel(0, &mb->error); 216 cx18_writel(cx, 0, &mb->error);
216 writel(req, &mb->request); 217 cx18_writel(cx, req, &mb->request);
217 218
218 switch (info->rpu) { 219 switch (info->rpu) {
219 case APU: waitq = &cx->mb_apu_waitq; break; 220 case APU: waitq = &cx->mb_apu_waitq; break;
@@ -224,9 +225,10 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
224 } 225 }
225 if (info->flags & API_FAST) 226 if (info->flags & API_FAST)
226 timeout /= 2; 227 timeout /= 2;
227 write_reg(irq, SW1_INT_SET); 228 cx18_write_reg(cx, irq, SW1_INT_SET);
228 229
229 while (!sig && readl(&mb->ack) != readl(&mb->request) && cnt < 660) { 230 while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request)
231 && cnt < 660) {
230 if (cnt > 200 && !in_atomic()) 232 if (cnt > 200 && !in_atomic())
231 sig = cx18_msleep_timeout(10, 1); 233 sig = cx18_msleep_timeout(10, 1);
232 cnt++; 234 cnt++;
@@ -234,13 +236,13 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
234 if (sig) 236 if (sig)
235 return -EINTR; 237 return -EINTR;
236 if (cnt == 660) { 238 if (cnt == 660) {
237 writel(oldreq, &mb->request); 239 cx18_writel(cx, oldreq, &mb->request);
238 CX18_ERR("mb %s failed\n", info->name); 240 CX18_ERR("mb %s failed\n", info->name);
239 return -EINVAL; 241 return -EINVAL;
240 } 242 }
241 for (i = 0; i < MAX_MB_ARGUMENTS; i++) 243 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
242 data[i] = readl(&mb->args[i]); 244 data[i] = cx18_readl(cx, &mb->args[i]);
243 err = readl(&mb->error); 245 err = cx18_readl(cx, &mb->error);
244 if (!in_atomic() && (info->flags & API_SLOW)) 246 if (!in_atomic() && (info->flags & API_SLOW))
245 cx18_msleep_timeout(300, 0); 247 cx18_msleep_timeout(300, 0);
246 if (err) 248 if (err)