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path: root/drivers/media/video/cx18/cx18-irq.c
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Diffstat (limited to 'drivers/media/video/cx18/cx18-irq.c')
-rw-r--r--drivers/media/video/cx18/cx18-irq.c163
1 files changed, 22 insertions, 141 deletions
diff --git a/drivers/media/video/cx18/cx18-irq.c b/drivers/media/video/cx18/cx18-irq.c
index 5fbfbd0f1493..af2f504eda2b 100644
--- a/drivers/media/video/cx18/cx18-irq.c
+++ b/drivers/media/video/cx18/cx18-irq.c
@@ -2,6 +2,7 @@
2 * cx18 interrupt handling 2 * cx18 interrupt handling
3 * 3 *
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
5 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 8 * it under the terms of the GNU General Public License as published by
@@ -21,132 +22,9 @@
21 22
22#include "cx18-driver.h" 23#include "cx18-driver.h"
23#include "cx18-io.h" 24#include "cx18-io.h"
24#include "cx18-firmware.h"
25#include "cx18-fileops.h"
26#include "cx18-queue.h"
27#include "cx18-irq.h" 25#include "cx18-irq.h"
28#include "cx18-ioctl.h"
29#include "cx18-mailbox.h" 26#include "cx18-mailbox.h"
30#include "cx18-vbi.h"
31#include "cx18-scb.h" 27#include "cx18-scb.h"
32#include "cx18-dvb.h"
33
34void cx18_work_handler(struct work_struct *work)
35{
36 struct cx18 *cx = container_of(work, struct cx18, work);
37 if (test_and_clear_bit(CX18_F_I_WORK_INITED, &cx->i_flags)) {
38 struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 };
39 /* This thread must use the FIFO scheduler as it
40 * is realtime sensitive. */
41 sched_setscheduler(current, SCHED_FIFO, &param);
42 }
43 if (test_and_clear_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags))
44 cx18_dvb_work_handler(cx);
45}
46
47static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb)
48{
49 u32 handle = mb->args[0];
50 struct cx18_stream *s = NULL;
51 struct cx18_buffer *buf;
52 u32 off;
53 int i;
54 int id;
55
56 for (i = 0; i < CX18_MAX_STREAMS; i++) {
57 s = &cx->streams[i];
58 if ((handle == s->handle) && (s->dvb.enabled))
59 break;
60 if (s->v4l2dev && handle == s->handle)
61 break;
62 }
63 if (i == CX18_MAX_STREAMS) {
64 CX18_WARN("Got DMA done notification for unknown/inactive"
65 " handle %d\n", handle);
66 mb->error = CXERR_NOT_OPEN;
67 mb->cmd = 0;
68 cx18_mb_ack(cx, mb);
69 return;
70 }
71
72 off = mb->args[1];
73 if (mb->args[2] != 1)
74 CX18_WARN("Ack struct = %d for %s\n",
75 mb->args[2], s->name);
76 id = cx18_read_enc(cx, off);
77 buf = cx18_queue_get_buf_irq(s, id, cx18_read_enc(cx, off + 4));
78 CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
79 if (buf) {
80 cx18_buf_sync_for_cpu(s, buf);
81 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
82 CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
83 buf->bytesused);
84
85 set_bit(CX18_F_I_WORK_HANDLER_DVB, &cx->i_flags);
86 set_bit(CX18_F_I_HAVE_WORK, &cx->i_flags);
87 } else
88 set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
89 } else {
90 CX18_WARN("Could not find buf %d for stream %s\n",
91 cx18_read_enc(cx, off), s->name);
92 }
93 mb->error = 0;
94 mb->cmd = 0;
95 cx18_mb_ack(cx, mb);
96 wake_up(&cx->dma_waitq);
97 if (s->id != -1)
98 wake_up(&s->waitq);
99}
100
101static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb)
102{
103 char str[256] = { 0 };
104 char *p;
105
106 if (mb->args[1]) {
107 cx18_setup_page(cx, mb->args[1]);
108 cx18_memcpy_fromio(cx, str, cx->enc_mem + mb->args[1], 252);
109 str[252] = 0;
110 }
111 cx18_mb_ack(cx, mb);
112 CX18_DEBUG_INFO("%x %s\n", mb->args[0], str);
113 p = strchr(str, '.');
114 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
115 CX18_INFO("FW version: %s\n", p - 1);
116}
117
118static void epu_cmd(struct cx18 *cx, u32 sw1)
119{
120 struct cx18_mailbox mb;
121
122 if (sw1 & IRQ_CPU_TO_EPU) {
123 cx18_memcpy_fromio(cx, &mb, &cx->scb->cpu2epu_mb, sizeof(mb));
124 mb.error = 0;
125
126 switch (mb.cmd) {
127 case CX18_EPU_DMA_DONE:
128 epu_dma_done(cx, &mb);
129 break;
130 case CX18_EPU_DEBUG:
131 epu_debug(cx, &mb);
132 break;
133 default:
134 CX18_WARN("Unknown CPU_TO_EPU mailbox command %#08x\n",
135 mb.cmd);
136 break;
137 }
138 }
139
140 if (sw1 & IRQ_APU_TO_EPU) {
141 cx18_memcpy_fromio(cx, &mb, &cx->scb->apu2epu_mb, sizeof(mb));
142 CX18_WARN("Unknown APU_TO_EPU mailbox command %#08x\n", mb.cmd);
143 }
144
145 if (sw1 & IRQ_HPU_TO_EPU) {
146 cx18_memcpy_fromio(cx, &mb, &cx->scb->hpu2epu_mb, sizeof(mb));
147 CX18_WARN("Unknown HPU_TO_EPU mailbox command %#08x\n", mb.cmd);
148 }
149}
150 28
151static void xpu_ack(struct cx18 *cx, u32 sw2) 29static void xpu_ack(struct cx18 *cx, u32 sw2)
152{ 30{
@@ -154,23 +32,24 @@ static void xpu_ack(struct cx18 *cx, u32 sw2)
154 wake_up(&cx->mb_cpu_waitq); 32 wake_up(&cx->mb_cpu_waitq);
155 if (sw2 & IRQ_APU_TO_EPU_ACK) 33 if (sw2 & IRQ_APU_TO_EPU_ACK)
156 wake_up(&cx->mb_apu_waitq); 34 wake_up(&cx->mb_apu_waitq);
157 if (sw2 & IRQ_HPU_TO_EPU_ACK) 35}
158 wake_up(&cx->mb_hpu_waitq); 36
37static void epu_cmd(struct cx18 *cx, u32 sw1)
38{
39 if (sw1 & IRQ_CPU_TO_EPU)
40 cx18_api_epu_cmd_irq(cx, CPU);
41 if (sw1 & IRQ_APU_TO_EPU)
42 cx18_api_epu_cmd_irq(cx, APU);
159} 43}
160 44
161irqreturn_t cx18_irq_handler(int irq, void *dev_id) 45irqreturn_t cx18_irq_handler(int irq, void *dev_id)
162{ 46{
163 struct cx18 *cx = (struct cx18 *)dev_id; 47 struct cx18 *cx = (struct cx18 *)dev_id;
164 u32 sw1, sw1_mask; 48 u32 sw1, sw2, hw2;
165 u32 sw2, sw2_mask;
166 u32 hw2, hw2_mask;
167 49
168 sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); 50 sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask;
169 sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; 51 sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & cx->sw2_irq_mask;
170 sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); 52 hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & cx->hw2_irq_mask;
171 sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
172 hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI);
173 hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask;
174 53
175 if (sw1) 54 if (sw1)
176 cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1); 55 cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
@@ -180,7 +59,15 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
180 cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2); 59 cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
181 60
182 if (sw1 || sw2 || hw2) 61 if (sw1 || sw2 || hw2)
183 CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); 62 CX18_DEBUG_HI_IRQ("received interrupts "
63 "SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);
64
65 /*
66 * SW1 responses have to happen first. The sending XPU times out the
67 * incoming mailboxes on us rather rapidly.
68 */
69 if (sw1)
70 epu_cmd(cx, sw1);
184 71
185 /* To do: interrupt-based I2C handling 72 /* To do: interrupt-based I2C handling
186 if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) { 73 if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {
@@ -190,11 +77,5 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
190 if (sw2) 77 if (sw2)
191 xpu_ack(cx, sw2); 78 xpu_ack(cx, sw2);
192 79
193 if (sw1)
194 epu_cmd(cx, sw1);
195
196 if (test_and_clear_bit(CX18_F_I_HAVE_WORK, &cx->i_flags))
197 queue_work(cx->work_queue, &cx->work);
198
199 return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE; 80 return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
200} 81}