diff options
Diffstat (limited to 'drivers/media/video/cx18/cx18-irq.c')
-rw-r--r-- | drivers/media/video/cx18/cx18-irq.c | 47 |
1 files changed, 24 insertions, 23 deletions
diff --git a/drivers/media/video/cx18/cx18-irq.c b/drivers/media/video/cx18/cx18-irq.c index ab218315c84b..360330f5463f 100644 --- a/drivers/media/video/cx18/cx18-irq.c +++ b/drivers/media/video/cx18/cx18-irq.c | |||
@@ -20,6 +20,7 @@ | |||
20 | */ | 20 | */ |
21 | 21 | ||
22 | #include "cx18-driver.h" | 22 | #include "cx18-driver.h" |
23 | #include "cx18-io.h" | ||
23 | #include "cx18-firmware.h" | 24 | #include "cx18-firmware.h" |
24 | #include "cx18-fileops.h" | 25 | #include "cx18-fileops.h" |
25 | #include "cx18-queue.h" | 26 | #include "cx18-queue.h" |
@@ -48,8 +49,8 @@ static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb) | |||
48 | break; | 49 | break; |
49 | } | 50 | } |
50 | if (i == CX18_MAX_STREAMS) { | 51 | if (i == CX18_MAX_STREAMS) { |
51 | CX18_WARN("DMA done for unknown handle %d for stream %s\n", | 52 | CX18_WARN("Got DMA done notification for unknown/inactive" |
52 | handle, s->name); | 53 | " handle %d\n", handle); |
53 | mb->error = CXERR_NOT_OPEN; | 54 | mb->error = CXERR_NOT_OPEN; |
54 | mb->cmd = 0; | 55 | mb->cmd = 0; |
55 | cx18_mb_ack(cx, mb); | 56 | cx18_mb_ack(cx, mb); |
@@ -60,8 +61,8 @@ static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb) | |||
60 | if (mb->args[2] != 1) | 61 | if (mb->args[2] != 1) |
61 | CX18_WARN("Ack struct = %d for %s\n", | 62 | CX18_WARN("Ack struct = %d for %s\n", |
62 | mb->args[2], s->name); | 63 | mb->args[2], s->name); |
63 | id = read_enc(off); | 64 | id = cx18_read_enc(cx, off); |
64 | buf = cx18_queue_get_buf_irq(s, id, read_enc(off + 4)); | 65 | buf = cx18_queue_get_buf_irq(s, id, cx18_read_enc(cx, off + 4)); |
65 | CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id); | 66 | CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id); |
66 | if (buf) { | 67 | if (buf) { |
67 | cx18_buf_sync_for_cpu(s, buf); | 68 | cx18_buf_sync_for_cpu(s, buf); |
@@ -81,7 +82,7 @@ static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb) | |||
81 | set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags); | 82 | set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags); |
82 | } else { | 83 | } else { |
83 | CX18_WARN("Could not find buf %d for stream %s\n", | 84 | CX18_WARN("Could not find buf %d for stream %s\n", |
84 | read_enc(off), s->name); | 85 | cx18_read_enc(cx, off), s->name); |
85 | } | 86 | } |
86 | mb->error = 0; | 87 | mb->error = 0; |
87 | mb->cmd = 0; | 88 | mb->cmd = 0; |
@@ -97,8 +98,8 @@ static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb) | |||
97 | char *p; | 98 | char *p; |
98 | 99 | ||
99 | if (mb->args[1]) { | 100 | if (mb->args[1]) { |
100 | setup_page(mb->args[1]); | 101 | cx18_setup_page(cx, mb->args[1]); |
101 | memcpy_fromio(str, cx->enc_mem + mb->args[1], 252); | 102 | cx18_memcpy_fromio(cx, str, cx->enc_mem + mb->args[1], 252); |
102 | str[252] = 0; | 103 | str[252] = 0; |
103 | } | 104 | } |
104 | cx18_mb_ack(cx, mb); | 105 | cx18_mb_ack(cx, mb); |
@@ -113,7 +114,7 @@ static void hpu_cmd(struct cx18 *cx, u32 sw1) | |||
113 | struct cx18_mailbox mb; | 114 | struct cx18_mailbox mb; |
114 | 115 | ||
115 | if (sw1 & IRQ_CPU_TO_EPU) { | 116 | if (sw1 & IRQ_CPU_TO_EPU) { |
116 | memcpy_fromio(&mb, &cx->scb->cpu2epu_mb, sizeof(mb)); | 117 | cx18_memcpy_fromio(cx, &mb, &cx->scb->cpu2epu_mb, sizeof(mb)); |
117 | mb.error = 0; | 118 | mb.error = 0; |
118 | 119 | ||
119 | switch (mb.cmd) { | 120 | switch (mb.cmd) { |
@@ -141,16 +142,16 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id) | |||
141 | 142 | ||
142 | spin_lock(&cx->dma_reg_lock); | 143 | spin_lock(&cx->dma_reg_lock); |
143 | 144 | ||
144 | hw2_mask = read_reg(HW2_INT_MASK5_PCI); | 145 | hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI); |
145 | hw2 = read_reg(HW2_INT_CLR_STATUS) & hw2_mask; | 146 | hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask; |
146 | sw2_mask = read_reg(SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK; | 147 | sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK; |
147 | sw2 = read_reg(SW2_INT_STATUS) & sw2_mask; | 148 | sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask; |
148 | sw1_mask = read_reg(SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU; | 149 | sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU; |
149 | sw1 = read_reg(SW1_INT_STATUS) & sw1_mask; | 150 | sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask; |
150 | 151 | ||
151 | write_reg(sw2&sw2_mask, SW2_INT_STATUS); | 152 | cx18_write_reg(cx, sw2&sw2_mask, SW2_INT_STATUS); |
152 | write_reg(sw1&sw1_mask, SW1_INT_STATUS); | 153 | cx18_write_reg(cx, sw1&sw1_mask, SW1_INT_STATUS); |
153 | write_reg(hw2&hw2_mask, HW2_INT_CLR_STATUS); | 154 | cx18_write_reg(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS); |
154 | 155 | ||
155 | if (sw1 || sw2 || hw2) | 156 | if (sw1 || sw2 || hw2) |
156 | CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); | 157 | CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2); |
@@ -161,15 +162,15 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id) | |||
161 | */ | 162 | */ |
162 | 163 | ||
163 | if (sw2) { | 164 | if (sw2) { |
164 | if (sw2 & (readl(&cx->scb->cpu2hpu_irq_ack) | | 165 | if (sw2 & (cx18_readl(cx, &cx->scb->cpu2hpu_irq_ack) | |
165 | readl(&cx->scb->cpu2epu_irq_ack))) | 166 | cx18_readl(cx, &cx->scb->cpu2epu_irq_ack))) |
166 | wake_up(&cx->mb_cpu_waitq); | 167 | wake_up(&cx->mb_cpu_waitq); |
167 | if (sw2 & (readl(&cx->scb->apu2hpu_irq_ack) | | 168 | if (sw2 & (cx18_readl(cx, &cx->scb->apu2hpu_irq_ack) | |
168 | readl(&cx->scb->apu2epu_irq_ack))) | 169 | cx18_readl(cx, &cx->scb->apu2epu_irq_ack))) |
169 | wake_up(&cx->mb_apu_waitq); | 170 | wake_up(&cx->mb_apu_waitq); |
170 | if (sw2 & readl(&cx->scb->epu2hpu_irq_ack)) | 171 | if (sw2 & cx18_readl(cx, &cx->scb->epu2hpu_irq_ack)) |
171 | wake_up(&cx->mb_epu_waitq); | 172 | wake_up(&cx->mb_epu_waitq); |
172 | if (sw2 & readl(&cx->scb->hpu2epu_irq_ack)) | 173 | if (sw2 & cx18_readl(cx, &cx->scb->hpu2epu_irq_ack)) |
173 | wake_up(&cx->mb_hpu_waitq); | 174 | wake_up(&cx->mb_hpu_waitq); |
174 | } | 175 | } |
175 | 176 | ||