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path: root/drivers/media/video/cx18/cx18-io.c
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Diffstat (limited to 'drivers/media/video/cx18/cx18-io.c')
-rw-r--r--drivers/media/video/cx18/cx18-io.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/media/video/cx18/cx18-io.c b/drivers/media/video/cx18/cx18-io.c
index 220fae8d4ad7..0ad8dea3e600 100644
--- a/drivers/media/video/cx18/cx18-io.c
+++ b/drivers/media/video/cx18/cx18-io.c
@@ -31,10 +31,10 @@ void cx18_log_statistics(struct cx18 *cx)
31 if (!(cx18_debug & CX18_DBGFLG_INFO)) 31 if (!(cx18_debug & CX18_DBGFLG_INFO))
32 return; 32 return;
33 33
34 for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++) 34 for (i = 0; i <= CX18_MAX_MMIO_WR_RETRIES; i++)
35 CX18_DEBUG_INFO("retried_write[%d] = %d\n", i, 35 CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
36 atomic_read(&cx->mmio_stats.retried_write[i])); 36 atomic_read(&cx->mmio_stats.retried_write[i]));
37 for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++) 37 for (i = 0; i <= CX18_MAX_MMIO_RD_RETRIES; i++)
38 CX18_DEBUG_INFO("retried_read[%d] = %d\n", i, 38 CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
39 atomic_read(&cx->mmio_stats.retried_read[i])); 39 atomic_read(&cx->mmio_stats.retried_read[i]));
40 return; 40 return;
@@ -43,7 +43,7 @@ void cx18_log_statistics(struct cx18 *cx)
43void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) 43void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
44{ 44{
45 int i; 45 int i;
46 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 46 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
47 cx18_raw_writel_noretry(cx, val, addr); 47 cx18_raw_writel_noretry(cx, val, addr);
48 if (val == cx18_raw_readl_noretry(cx, addr)) 48 if (val == cx18_raw_readl_noretry(cx, addr))
49 break; 49 break;
@@ -55,7 +55,7 @@ u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr)
55{ 55{
56 int i; 56 int i;
57 u32 val; 57 u32 val;
58 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 58 for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
59 val = cx18_raw_readl_noretry(cx, addr); 59 val = cx18_raw_readl_noretry(cx, addr);
60 if (val != 0xffffffff) /* PCI bus read error */ 60 if (val != 0xffffffff) /* PCI bus read error */
61 break; 61 break;
@@ -68,7 +68,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
68{ 68{
69 int i; 69 int i;
70 u16 val; 70 u16 val;
71 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 71 for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
72 val = cx18_raw_readw_noretry(cx, addr); 72 val = cx18_raw_readw_noretry(cx, addr);
73 if (val != 0xffff) /* PCI bus read error */ 73 if (val != 0xffff) /* PCI bus read error */
74 break; 74 break;
@@ -80,7 +80,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
80void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) 80void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
81{ 81{
82 int i; 82 int i;
83 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 83 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
84 cx18_writel_noretry(cx, val, addr); 84 cx18_writel_noretry(cx, val, addr);
85 if (val == cx18_readl_noretry(cx, addr)) 85 if (val == cx18_readl_noretry(cx, addr))
86 break; 86 break;
@@ -93,7 +93,7 @@ void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
93{ 93{
94 int i; 94 int i;
95 eval &= mask; 95 eval &= mask;
96 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 96 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
97 cx18_writel_noretry(cx, val, addr); 97 cx18_writel_noretry(cx, val, addr);
98 if (eval == (cx18_readl_noretry(cx, addr) & mask)) 98 if (eval == (cx18_readl_noretry(cx, addr) & mask))
99 break; 99 break;
@@ -104,7 +104,7 @@ void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
104void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr) 104void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
105{ 105{
106 int i; 106 int i;
107 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 107 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
108 cx18_writew_noretry(cx, val, addr); 108 cx18_writew_noretry(cx, val, addr);
109 if (val == cx18_readw_noretry(cx, addr)) 109 if (val == cx18_readw_noretry(cx, addr))
110 break; 110 break;
@@ -115,7 +115,7 @@ void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
115void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr) 115void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
116{ 116{
117 int i; 117 int i;
118 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 118 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
119 cx18_writeb_noretry(cx, val, addr); 119 cx18_writeb_noretry(cx, val, addr);
120 if (val == cx18_readb_noretry(cx, addr)) 120 if (val == cx18_readb_noretry(cx, addr))
121 break; 121 break;
@@ -127,7 +127,7 @@ u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr)
127{ 127{
128 int i; 128 int i;
129 u32 val; 129 u32 val;
130 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 130 for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
131 val = cx18_readl_noretry(cx, addr); 131 val = cx18_readl_noretry(cx, addr);
132 if (val != 0xffffffff) /* PCI bus read error */ 132 if (val != 0xffffffff) /* PCI bus read error */
133 break; 133 break;
@@ -140,7 +140,7 @@ u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr)
140{ 140{
141 int i; 141 int i;
142 u16 val; 142 u16 val;
143 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 143 for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
144 val = cx18_readw_noretry(cx, addr); 144 val = cx18_readw_noretry(cx, addr);
145 if (val != 0xffff) /* PCI bus read error */ 145 if (val != 0xffff) /* PCI bus read error */
146 break; 146 break;
@@ -153,7 +153,7 @@ u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr)
153{ 153{
154 int i; 154 int i;
155 u8 val; 155 u8 val;
156 for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { 156 for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
157 val = cx18_readb_noretry(cx, addr); 157 val = cx18_readb_noretry(cx, addr);
158 if (val != 0xff) /* PCI bus read error */ 158 if (val != 0xff) /* PCI bus read error */
159 break; 159 break;