diff options
Diffstat (limited to 'drivers/media/video/cx18/cx18-i2c.c')
-rw-r--r-- | drivers/media/video/cx18/cx18-i2c.c | 49 |
1 files changed, 27 insertions, 22 deletions
diff --git a/drivers/media/video/cx18/cx18-i2c.c b/drivers/media/video/cx18/cx18-i2c.c index 6023ba3bd3a6..aa09e557b195 100644 --- a/drivers/media/video/cx18/cx18-i2c.c +++ b/drivers/media/video/cx18/cx18-i2c.c | |||
@@ -22,13 +22,12 @@ | |||
22 | */ | 22 | */ |
23 | 23 | ||
24 | #include "cx18-driver.h" | 24 | #include "cx18-driver.h" |
25 | #include "cx18-io.h" | ||
25 | #include "cx18-cards.h" | 26 | #include "cx18-cards.h" |
26 | #include "cx18-gpio.h" | 27 | #include "cx18-gpio.h" |
27 | #include "cx18-av-core.h" | 28 | #include "cx18-av-core.h" |
28 | #include "cx18-i2c.h" | 29 | #include "cx18-i2c.h" |
29 | 30 | ||
30 | #include <media/ir-kbd-i2c.h> | ||
31 | |||
32 | #define CX18_REG_I2C_1_WR 0xf15000 | 31 | #define CX18_REG_I2C_1_WR 0xf15000 |
33 | #define CX18_REG_I2C_1_RD 0xf15008 | 32 | #define CX18_REG_I2C_1_RD 0xf15008 |
34 | #define CX18_REG_I2C_2_WR 0xf25100 | 33 | #define CX18_REG_I2C_2_WR 0xf25100 |
@@ -158,12 +157,12 @@ static void cx18_setscl(void *data, int state) | |||
158 | struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx; | 157 | struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx; |
159 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; | 158 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; |
160 | u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR; | 159 | u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR; |
161 | u32 r = read_reg(addr); | 160 | u32 r = cx18_read_reg(cx, addr); |
162 | 161 | ||
163 | if (state) | 162 | if (state) |
164 | write_reg_sync(r | SETSCL_BIT, addr); | 163 | cx18_write_reg_sync(cx, r | SETSCL_BIT, addr); |
165 | else | 164 | else |
166 | write_reg_sync(r & ~SETSCL_BIT, addr); | 165 | cx18_write_reg_sync(cx, r & ~SETSCL_BIT, addr); |
167 | } | 166 | } |
168 | 167 | ||
169 | static void cx18_setsda(void *data, int state) | 168 | static void cx18_setsda(void *data, int state) |
@@ -171,12 +170,12 @@ static void cx18_setsda(void *data, int state) | |||
171 | struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx; | 170 | struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx; |
172 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; | 171 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; |
173 | u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR; | 172 | u32 addr = bus_index ? CX18_REG_I2C_2_WR : CX18_REG_I2C_1_WR; |
174 | u32 r = read_reg(addr); | 173 | u32 r = cx18_read_reg(cx, addr); |
175 | 174 | ||
176 | if (state) | 175 | if (state) |
177 | write_reg_sync(r | SETSDL_BIT, addr); | 176 | cx18_write_reg_sync(cx, r | SETSDL_BIT, addr); |
178 | else | 177 | else |
179 | write_reg_sync(r & ~SETSDL_BIT, addr); | 178 | cx18_write_reg_sync(cx, r & ~SETSDL_BIT, addr); |
180 | } | 179 | } |
181 | 180 | ||
182 | static int cx18_getscl(void *data) | 181 | static int cx18_getscl(void *data) |
@@ -185,7 +184,7 @@ static int cx18_getscl(void *data) | |||
185 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; | 184 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; |
186 | u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD; | 185 | u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD; |
187 | 186 | ||
188 | return read_reg(addr) & GETSCL_BIT; | 187 | return cx18_read_reg(cx, addr) & GETSCL_BIT; |
189 | } | 188 | } |
190 | 189 | ||
191 | static int cx18_getsda(void *data) | 190 | static int cx18_getsda(void *data) |
@@ -194,7 +193,7 @@ static int cx18_getsda(void *data) | |||
194 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; | 193 | int bus_index = ((struct cx18_i2c_algo_callback_data *)data)->bus_index; |
195 | u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD; | 194 | u32 addr = bus_index ? CX18_REG_I2C_2_RD : CX18_REG_I2C_1_RD; |
196 | 195 | ||
197 | return read_reg(addr) & GETSDL_BIT; | 196 | return cx18_read_reg(cx, addr) & GETSDL_BIT; |
198 | } | 197 | } |
199 | 198 | ||
200 | /* template for i2c-bit-algo */ | 199 | /* template for i2c-bit-algo */ |
@@ -394,29 +393,33 @@ int init_cx18_i2c(struct cx18 *cx) | |||
394 | cx->i2c_adap[i].dev.parent = &cx->dev->dev; | 393 | cx->i2c_adap[i].dev.parent = &cx->dev->dev; |
395 | } | 394 | } |
396 | 395 | ||
397 | if (read_reg(CX18_REG_I2C_2_WR) != 0x0003c02f) { | 396 | if (cx18_read_reg(cx, CX18_REG_I2C_2_WR) != 0x0003c02f) { |
398 | /* Reset/Unreset I2C hardware block */ | 397 | /* Reset/Unreset I2C hardware block */ |
399 | write_reg(0x10000000, 0xc71004); /* Clock select 220MHz */ | 398 | /* Clock select 220MHz */ |
400 | write_reg_sync(0x10001000, 0xc71024); /* Clock Enable */ | 399 | cx18_write_reg(cx, 0x10000000, 0xc71004); |
400 | /* Clock Enable */ | ||
401 | cx18_write_reg_sync(cx, 0x10001000, 0xc71024); | ||
401 | } | 402 | } |
402 | /* courtesy of Steven Toth <stoth@hauppauge.com> */ | 403 | /* courtesy of Steven Toth <stoth@hauppauge.com> */ |
403 | write_reg_sync(0x00c00000, 0xc7001c); | 404 | cx18_write_reg_sync(cx, 0x00c00000, 0xc7001c); |
404 | mdelay(10); | 405 | mdelay(10); |
405 | write_reg_sync(0x00c000c0, 0xc7001c); | 406 | cx18_write_reg_sync(cx, 0x00c000c0, 0xc7001c); |
406 | mdelay(10); | 407 | mdelay(10); |
407 | write_reg_sync(0x00c00000, 0xc7001c); | 408 | cx18_write_reg_sync(cx, 0x00c00000, 0xc7001c); |
408 | mdelay(10); | 409 | mdelay(10); |
409 | 410 | ||
410 | write_reg_sync(0x00c00000, 0xc730c8); /* Set to edge-triggered intrs. */ | 411 | /* Set to edge-triggered intrs. */ |
411 | write_reg_sync(0x00c00000, 0xc730c4); /* Clear any stale intrs */ | 412 | cx18_write_reg_sync(cx, 0x00c00000, 0xc730c8); |
413 | /* Clear any stale intrs */ | ||
414 | cx18_write_reg_sync(cx, 0x00c00000, 0xc730c4); | ||
412 | 415 | ||
413 | /* Hw I2C1 Clock Freq ~100kHz */ | 416 | /* Hw I2C1 Clock Freq ~100kHz */ |
414 | write_reg_sync(0x00021c0f & ~4, CX18_REG_I2C_1_WR); | 417 | cx18_write_reg_sync(cx, 0x00021c0f & ~4, CX18_REG_I2C_1_WR); |
415 | cx18_setscl(&cx->i2c_algo_cb_data[0], 1); | 418 | cx18_setscl(&cx->i2c_algo_cb_data[0], 1); |
416 | cx18_setsda(&cx->i2c_algo_cb_data[0], 1); | 419 | cx18_setsda(&cx->i2c_algo_cb_data[0], 1); |
417 | 420 | ||
418 | /* Hw I2C2 Clock Freq ~100kHz */ | 421 | /* Hw I2C2 Clock Freq ~100kHz */ |
419 | write_reg_sync(0x00021c0f & ~4, CX18_REG_I2C_2_WR); | 422 | cx18_write_reg_sync(cx, 0x00021c0f & ~4, CX18_REG_I2C_2_WR); |
420 | cx18_setscl(&cx->i2c_algo_cb_data[1], 1); | 423 | cx18_setscl(&cx->i2c_algo_cb_data[1], 1); |
421 | cx18_setsda(&cx->i2c_algo_cb_data[1], 1); | 424 | cx18_setsda(&cx->i2c_algo_cb_data[1], 1); |
422 | 425 | ||
@@ -430,8 +433,10 @@ void exit_cx18_i2c(struct cx18 *cx) | |||
430 | { | 433 | { |
431 | int i; | 434 | int i; |
432 | CX18_DEBUG_I2C("i2c exit\n"); | 435 | CX18_DEBUG_I2C("i2c exit\n"); |
433 | write_reg(read_reg(CX18_REG_I2C_1_WR) | 4, CX18_REG_I2C_1_WR); | 436 | cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_1_WR) | 4, |
434 | write_reg(read_reg(CX18_REG_I2C_2_WR) | 4, CX18_REG_I2C_2_WR); | 437 | CX18_REG_I2C_1_WR); |
438 | cx18_write_reg(cx, cx18_read_reg(cx, CX18_REG_I2C_2_WR) | 4, | ||
439 | CX18_REG_I2C_2_WR); | ||
435 | 440 | ||
436 | for (i = 0; i < 2; i++) { | 441 | for (i = 0; i < 2; i++) { |
437 | i2c_del_adapter(&cx->i2c_adap[i]); | 442 | i2c_del_adapter(&cx->i2c_adap[i]); |