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path: root/drivers/media/video/cx18/cx18-av-firmware.c
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Diffstat (limited to 'drivers/media/video/cx18/cx18-av-firmware.c')
-rw-r--r--drivers/media/video/cx18/cx18-av-firmware.c85
1 files changed, 55 insertions, 30 deletions
diff --git a/drivers/media/video/cx18/cx18-av-firmware.c b/drivers/media/video/cx18/cx18-av-firmware.c
index a1a6af6c1c8f..522a035b2e8f 100644
--- a/drivers/media/video/cx18/cx18-av-firmware.c
+++ b/drivers/media/video/cx18/cx18-av-firmware.c
@@ -20,8 +20,10 @@
20 */ 20 */
21 21
22#include "cx18-driver.h" 22#include "cx18-driver.h"
23#include "cx18-io.h"
23#include <linux/firmware.h> 24#include <linux/firmware.h>
24 25
26#define CX18_AUDIO_ENABLE 0xc72014
25#define FWFILE "v4l-cx23418-dig.fw" 27#define FWFILE "v4l-cx23418-dig.fw"
26 28
27int cx18_av_loadfw(struct cx18 *cx) 29int cx18_av_loadfw(struct cx18 *cx)
@@ -31,40 +33,64 @@ int cx18_av_loadfw(struct cx18 *cx)
31 u32 v; 33 u32 v;
32 const u8 *ptr; 34 const u8 *ptr;
33 int i; 35 int i;
36 int retries1 = 0;
34 37
35 if (request_firmware(&fw, FWFILE, &cx->dev->dev) != 0) { 38 if (request_firmware(&fw, FWFILE, &cx->dev->dev) != 0) {
36 CX18_ERR("unable to open firmware %s\n", FWFILE); 39 CX18_ERR("unable to open firmware %s\n", FWFILE);
37 return -EINVAL; 40 return -EINVAL;
38 } 41 }
39 42
40 cx18_av_write4(cx, CXADEC_CHIP_CTRL, 0x00010000); 43 /* The firmware load often has byte errors, so allow for several
41 cx18_av_write(cx, CXADEC_STD_DET_CTL, 0xf6); /* Byte 0 */ 44 retries, both at byte level and at the firmware load level. */
42 45 while (retries1 < 5) {
43 /* Reset the Mako core (Register is undocumented.) */ 46 cx18_av_write4(cx, CXADEC_CHIP_CTRL, 0x00010000);
44 cx18_av_write4(cx, 0x8100, 0x00010000); 47 cx18_av_write(cx, CXADEC_STD_DET_CTL, 0xf6);
45 48
46 /* Put the 8051 in reset and enable firmware upload */ 49 /* Reset the Mako core (Register is undocumented.) */
47 cx18_av_write4(cx, CXADEC_DL_CTL, 0x0F000000); 50 cx18_av_write4(cx, 0x8100, 0x00010000);
48 51
49 ptr = fw->data; 52 /* Put the 8051 in reset and enable firmware upload */
50 size = fw->size; 53 cx18_av_write4_noretry(cx, CXADEC_DL_CTL, 0x0F000000);
51 54
52 for (i = 0; i < size; i++) { 55 ptr = fw->data;
53 u32 dl_control = 0x0F000000 | ((u32)ptr[i] << 16); 56 size = fw->size;
54 u32 value = 0; 57
55 int retries; 58 for (i = 0; i < size; i++) {
56 59 u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
57 for (retries = 0; retries < 5; retries++) { 60 u32 value = 0;
58 cx18_av_write4(cx, CXADEC_DL_CTL, dl_control); 61 int retries2;
59 value = cx18_av_read4(cx, CXADEC_DL_CTL); 62 int unrec_err = 0;
60 if ((value & 0x3F00) == (dl_control & 0x3F00)) 63
64 for (retries2 = 0; retries2 < CX18_MAX_MMIO_RETRIES;
65 retries2++) {
66 cx18_av_write4_noretry(cx, CXADEC_DL_CTL,
67 dl_control);
68 udelay(10);
69 value = cx18_av_read4_noretry(cx,
70 CXADEC_DL_CTL);
71 if (value == dl_control)
72 break;
73 /* Check if we can correct the byte by changing
74 the address. We can only write the lower
75 address byte of the address. */
76 if ((value & 0x3F00) != (dl_control & 0x3F00)) {
77 unrec_err = 1;
78 break;
79 }
80 }
81 cx18_log_write_retries(cx, retries2,
82 cx->reg_mem + 0xc40000 + CXADEC_DL_CTL);
83 if (unrec_err || retries2 >= CX18_MAX_MMIO_RETRIES)
61 break; 84 break;
62 } 85 }
63 if (retries >= 5) { 86 if (i == size)
64 CX18_ERR("unable to load firmware %s\n", FWFILE); 87 break;
65 release_firmware(fw); 88 retries1++;
66 return -EIO; 89 }
67 } 90 if (retries1 >= 5) {
91 CX18_ERR("unable to load firmware %s\n", FWFILE);
92 release_firmware(fw);
93 return -EIO;
68 } 94 }
69 95
70 cx18_av_write4(cx, CXADEC_DL_CTL, 0x13000000 | fw->size); 96 cx18_av_write4(cx, CXADEC_DL_CTL, 0x13000000 | fw->size);
@@ -100,11 +126,10 @@ int cx18_av_loadfw(struct cx18 *cx)
100 have a name in the spec. */ 126 have a name in the spec. */
101 cx18_av_write4(cx, 0x09CC, 1); 127 cx18_av_write4(cx, 0x09CC, 1);
102 128
103#define CX18_AUDIO_ENABLE 0xc72014 129 v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
104 v = read_reg(CX18_AUDIO_ENABLE); 130 /* If bit 11 is 1, clear bit 10 */
105 /* If bit 11 is 1 */
106 if (v & 0x800) 131 if (v & 0x800)
107 write_reg(v & 0xFFFFFBFF, CX18_AUDIO_ENABLE); /* Clear bit 10 */ 132 cx18_write_reg(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE);
108 133
109 /* Enable WW auto audio standard detection */ 134 /* Enable WW auto audio standard detection */
110 v = cx18_av_read4(cx, CXADEC_STD_DET_CTL); 135 v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);