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-rw-r--r--drivers/media/video/arv.c916
1 files changed, 916 insertions, 0 deletions
diff --git a/drivers/media/video/arv.c b/drivers/media/video/arv.c
new file mode 100644
index 000000000000..87fd3a7bb392
--- /dev/null
+++ b/drivers/media/video/arv.c
@@ -0,0 +1,916 @@
1/*
2 * Colour AR M64278(VGA) driver for Video4Linux
3 *
4 * Copyright (C) 2003 Takeo Takahashi <takahashi.takeo@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Some code is taken from AR driver sample program for M3T-M32700UT.
12 *
13 * AR driver sample (M32R SDK):
14 * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION
15 * AND RENESAS SOLUTIONS CORPORATION
16 * All Rights Reserved.
17 *
18 * 2003-09-01: Support w3cam by Takeo Takahashi
19 */
20
21#include <linux/config.h>
22#include <linux/init.h>
23#include <linux/devfs_fs_kernel.h>
24#include <linux/module.h>
25#include <linux/version.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/fs.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/slab.h>
32#include <linux/mm.h>
33#include <linux/sched.h>
34#include <linux/videodev.h>
35
36#include <asm/semaphore.h>
37#include <asm/uaccess.h>
38#include <asm/m32r.h>
39#include <asm/io.h>
40#include <asm/dma.h>
41#include <asm/byteorder.h>
42
43#if 0
44#define DEBUG(n, args...) printk(args)
45#define CHECK_LOST 1
46#else
47#define DEBUG(n, args...)
48#define CHECK_LOST 0
49#endif
50
51/*
52 * USE_INT is always 0, interrupt mode is not available
53 * on linux due to lack of speed
54 */
55#define USE_INT 0 /* Don't modify */
56
57#define VERSION "0.03"
58
59#define ar_inl(addr) inl((unsigned long)(addr))
60#define ar_outl(val, addr) outl((unsigned long)(val),(unsigned long)(addr))
61
62extern struct cpuinfo_m32r boot_cpu_data;
63
64/*
65 * CCD pixel size
66 * Note that M32700UT does not support CIF mode, but QVGA is
67 * supported by M32700UT hardware using VGA mode of AR LSI.
68 *
69 * Supported: VGA (Normal mode, Interlace mode)
70 * QVGA (Always Interlace mode of VGA)
71 *
72 */
73#define AR_WIDTH_VGA 640
74#define AR_HEIGHT_VGA 480
75#define AR_WIDTH_QVGA 320
76#define AR_HEIGHT_QVGA 240
77#define MIN_AR_WIDTH AR_WIDTH_QVGA
78#define MIN_AR_HEIGHT AR_HEIGHT_QVGA
79#define MAX_AR_WIDTH AR_WIDTH_VGA
80#define MAX_AR_HEIGHT AR_HEIGHT_VGA
81
82/* bits & bytes per pixel */
83#define AR_BITS_PER_PIXEL 16
84#define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL/8)
85
86/* line buffer size */
87#define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL)
88#define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL)
89#define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA
90
91/* frame size & type */
92#define AR_FRAME_BYTES_VGA \
93 (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYTES_PER_PIXEL)
94#define AR_FRAME_BYTES_QVGA \
95 (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_BYTES_PER_PIXEL)
96#define MAX_AR_FRAME_BYTES \
97 (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYTES_PER_PIXEL)
98
99#define AR_MAX_FRAME 15
100
101/* capture size */
102#define AR_SIZE_VGA 0
103#define AR_SIZE_QVGA 1
104
105/* capture mode */
106#define AR_MODE_INTERLACE 0
107#define AR_MODE_NORMAL 1
108
109struct ar_device {
110 struct video_device *vdev;
111 unsigned int start_capture; /* duaring capture in INT. mode. */
112#if USE_INT
113 unsigned char *line_buff; /* DMA line buffer */
114#endif
115 unsigned char *frame[MAX_AR_HEIGHT]; /* frame data */
116 short size; /* capture size */
117 short mode; /* capture mode */
118 int width, height;
119 int frame_bytes, line_bytes;
120 wait_queue_head_t wait;
121 struct semaphore lock;
122};
123
124static int video_nr = -1; /* video device number (first free) */
125static unsigned char yuv[MAX_AR_FRAME_BYTES];
126
127/* module parameters */
128/* default frequency */
129#define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */
130static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */
131static int vga = 0; /* default mode(0:QVGA mode, other:VGA mode) */
132static int vga_interlace = 0; /* 0 is normal mode for, else interlace mode */
133MODULE_PARM(freq, "i");
134MODULE_PARM(vga, "i");
135MODULE_PARM(vga_interlace, "i");
136
137static int ar_initialize(struct video_device *dev);
138
139static inline void wait_for_vsync(void)
140{
141 while (ar_inl(ARVCR0) & ARVCR0_VDS) /* wait for VSYNC */
142 cpu_relax();
143 while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) /* wait for VSYNC */
144 cpu_relax();
145}
146
147static inline void wait_acknowledge(void)
148{
149 int i;
150
151 for (i = 0; i < 1000; i++)
152 cpu_relax();
153 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK)
154 cpu_relax();
155}
156
157/*******************************************************************
158 * I2C functions
159 *******************************************************************/
160void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2,
161 unsigned long data3)
162{
163 int i;
164
165 /* Slave Address */
166 ar_outl(addr, PLDI2CDATA);
167 wait_for_vsync();
168
169 /* Start */
170 ar_outl(1, PLDI2CCND);
171 wait_acknowledge();
172
173 /* Transfer data 1 */
174 ar_outl(data1, PLDI2CDATA);
175 wait_for_vsync();
176 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
177 wait_acknowledge();
178
179 /* Transfer data 2 */
180 ar_outl(data2, PLDI2CDATA);
181 wait_for_vsync();
182 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
183 wait_acknowledge();
184
185 if (n == 3) {
186 /* Transfer data 3 */
187 ar_outl(data3, PLDI2CDATA);
188 wait_for_vsync();
189 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
190 wait_acknowledge();
191 }
192
193 /* Stop */
194 for (i = 0; i < 100; i++)
195 cpu_relax();
196 ar_outl(2, PLDI2CCND);
197 ar_outl(2, PLDI2CCND);
198
199 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_BB)
200 cpu_relax();
201}
202
203
204void init_iic(void)
205{
206 DEBUG(1, "init_iic:\n");
207
208 /*
209 * ICU Setting (iic)
210 */
211 /* I2C Setting */
212 ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */
213 ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */
214 ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */
215
216 /* I2C CLK */
217 /* 50MH-100k */
218 if (freq == 75) {
219 ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */
220 } else if (freq == 50) {
221 ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */
222 } else {
223 ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */
224 }
225 ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */
226}
227
228/**************************************************************************
229 *
230 * Video4Linux Interface functions
231 *
232 **************************************************************************/
233
234static inline void disable_dma(void)
235{
236 ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */
237}
238
239static inline void enable_dma(void)
240{
241 ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */
242}
243
244static inline void clear_dma_status(void)
245{
246 ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */
247}
248
249static inline void wait_for_vertical_sync(int exp_line)
250{
251#if CHECK_LOST
252 int tmout = 10000; /* FIXME */
253 int l;
254
255 /*
256 * check HCOUNT because we cannot check vertical sync.
257 */
258 for (; tmout >= 0; tmout--) {
259 l = ar_inl(ARVHCOUNT);
260 if (l == exp_line)
261 break;
262 }
263 if (tmout < 0)
264 printk("arv: lost %d -> %d\n", exp_line, l);
265#else
266 while (ar_inl(ARVHCOUNT) != exp_line)
267 cpu_relax();
268#endif
269}
270
271static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos)
272{
273 struct video_device *v = video_devdata(file);
274 struct ar_device *ar = v->priv;
275 long ret = ar->frame_bytes; /* return read bytes */
276 unsigned long arvcr1 = 0;
277 unsigned long flags;
278 unsigned char *p;
279 int h, w;
280 unsigned char *py, *pu, *pv;
281#if ! USE_INT
282 int l;
283#endif
284
285 DEBUG(1, "ar_read()\n");
286
287 if (ar->size == AR_SIZE_QVGA)
288 arvcr1 |= ARVCR1_QVGA;
289 if (ar->mode == AR_MODE_NORMAL)
290 arvcr1 |= ARVCR1_NORMAL;
291
292 down(&ar->lock);
293
294#if USE_INT
295 local_irq_save(flags);
296 disable_dma();
297 ar_outl(0xa1871300, M32R_DMA0CR0_PORTL);
298 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
299
300 /* set AR FIFO address as source(BSEL5) */
301 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
302 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
303 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */
304 ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */
305 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */
306 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */
307
308 /*
309 * Okey , kicks AR LSI to invoke an interrupt
310 */
311 ar->start_capture = 0;
312 ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1);
313 local_irq_restore(flags);
314 /* .... AR interrupts .... */
315 interruptible_sleep_on(&ar->wait);
316 if (signal_pending(current)) {
317 printk("arv: interrupted while get frame data.\n");
318 ret = -EINTR;
319 goto out_up;
320 }
321#else /* ! USE_INT */
322 /* polling */
323 ar_outl(arvcr1, ARVCR1);
324 disable_dma();
325 ar_outl(0x8000, M32R_DMAEDET_PORTL);
326 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
327 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
328 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
329 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
330 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL);
331 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL);
332
333 local_irq_save(flags);
334 while (ar_inl(ARVHCOUNT) != 0) /* wait for 0 */
335 cpu_relax();
336 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
337 for (h = 0; h < ar->height; h++) {
338 wait_for_vertical_sync(h);
339 if (h < (AR_HEIGHT_VGA/2))
340 l = h << 1;
341 else
342 l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1);
343 ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL);
344 enable_dma();
345 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
346 cpu_relax();
347 disable_dma();
348 clear_dma_status();
349 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
350 }
351 } else {
352 for (h = 0; h < ar->height; h++) {
353 wait_for_vertical_sync(h);
354 ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL);
355 enable_dma();
356 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
357 cpu_relax();
358 disable_dma();
359 clear_dma_status();
360 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
361 }
362 }
363 local_irq_restore(flags);
364#endif /* ! USE_INT */
365
366 /*
367 * convert YUV422 to YUV422P
368 * +--------------------+
369 * | Y0,Y1,... |
370 * | ..............Yn |
371 * +--------------------+
372 * | U0,U1,........Un |
373 * +--------------------+
374 * | V0,V1,........Vn |
375 * +--------------------+
376 */
377 py = yuv;
378 pu = py + (ar->frame_bytes / 2);
379 pv = pu + (ar->frame_bytes / 4);
380 for (h = 0; h < ar->height; h++) {
381 p = ar->frame[h];
382 for (w = 0; w < ar->line_bytes; w += 4) {
383 *py++ = *p++;
384 *pu++ = *p++;
385 *py++ = *p++;
386 *pv++ = *p++;
387 }
388 }
389 if (copy_to_user(buf, yuv, ar->frame_bytes)) {
390 printk("arv: failed while copy_to_user yuv.\n");
391 ret = -EFAULT;
392 goto out_up;
393 }
394 DEBUG(1, "ret = %d\n", ret);
395out_up:
396 up(&ar->lock);
397 return ret;
398}
399
400static int ar_do_ioctl(struct inode *inode, struct file *file,
401 unsigned int cmd, void *arg)
402{
403 struct video_device *dev = video_devdata(file);
404 struct ar_device *ar = dev->priv;
405
406 DEBUG(1, "ar_ioctl()\n");
407 switch(cmd) {
408 case VIDIOCGCAP:
409 {
410 struct video_capability *b = arg;
411 DEBUG(1, "VIDIOCGCAP:\n");
412 strcpy(b->name, ar->vdev->name);
413 b->type = VID_TYPE_CAPTURE;
414 b->channels = 0;
415 b->audios = 0;
416 b->maxwidth = MAX_AR_WIDTH;
417 b->maxheight = MAX_AR_HEIGHT;
418 b->minwidth = MIN_AR_WIDTH;
419 b->minheight = MIN_AR_HEIGHT;
420 return 0;
421 }
422 case VIDIOCGCHAN:
423 DEBUG(1, "VIDIOCGCHAN:\n");
424 return 0;
425 case VIDIOCSCHAN:
426 DEBUG(1, "VIDIOCSCHAN:\n");
427 return 0;
428 case VIDIOCGTUNER:
429 DEBUG(1, "VIDIOCGTUNER:\n");
430 return 0;
431 case VIDIOCSTUNER:
432 DEBUG(1, "VIDIOCSTUNER:\n");
433 return 0;
434 case VIDIOCGPICT:
435 DEBUG(1, "VIDIOCGPICT:\n");
436 return 0;
437 case VIDIOCSPICT:
438 DEBUG(1, "VIDIOCSPICT:\n");
439 return 0;
440 case VIDIOCCAPTURE:
441 DEBUG(1, "VIDIOCCAPTURE:\n");
442 return -EINVAL;
443 case VIDIOCGWIN:
444 {
445 struct video_window *w = arg;
446 DEBUG(1, "VIDIOCGWIN:\n");
447 memset(w, 0, sizeof(w));
448 w->width = ar->width;
449 w->height = ar->height;
450 return 0;
451 }
452 case VIDIOCSWIN:
453 {
454 struct video_window *w = arg;
455 DEBUG(1, "VIDIOCSWIN:\n");
456 if ((w->width != AR_WIDTH_VGA || w->height != AR_HEIGHT_VGA) &&
457 (w->width != AR_WIDTH_QVGA || w->height != AR_HEIGHT_QVGA))
458 return -EINVAL;
459
460 down(&ar->lock);
461 ar->width = w->width;
462 ar->height = w->height;
463 if (ar->width == AR_WIDTH_VGA) {
464 ar->size = AR_SIZE_VGA;
465 ar->frame_bytes = AR_FRAME_BYTES_VGA;
466 ar->line_bytes = AR_LINE_BYTES_VGA;
467 if (vga_interlace)
468 ar->mode = AR_MODE_INTERLACE;
469 else
470 ar->mode = AR_MODE_NORMAL;
471 } else {
472 ar->size = AR_SIZE_QVGA;
473 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
474 ar->line_bytes = AR_LINE_BYTES_QVGA;
475 ar->mode = AR_MODE_INTERLACE;
476 }
477 up(&ar->lock);
478 return 0;
479 }
480 case VIDIOCGFBUF:
481 DEBUG(1, "VIDIOCGFBUF:\n");
482 return -EINVAL;
483 case VIDIOCSFBUF:
484 DEBUG(1, "VIDIOCSFBUF:\n");
485 return -EINVAL;
486 case VIDIOCKEY:
487 DEBUG(1, "VIDIOCKEY:\n");
488 return 0;
489 case VIDIOCGFREQ:
490 DEBUG(1, "VIDIOCGFREQ:\n");
491 return -EINVAL;
492 case VIDIOCSFREQ:
493 DEBUG(1, "VIDIOCSFREQ:\n");
494 return -EINVAL;
495 case VIDIOCGAUDIO:
496 DEBUG(1, "VIDIOCGAUDIO:\n");
497 return -EINVAL;
498 case VIDIOCSAUDIO:
499 DEBUG(1, "VIDIOCSAUDIO:\n");
500 return -EINVAL;
501 case VIDIOCSYNC:
502 DEBUG(1, "VIDIOCSYNC:\n");
503 return -EINVAL;
504 case VIDIOCMCAPTURE:
505 DEBUG(1, "VIDIOCMCAPTURE:\n");
506 return -EINVAL;
507 case VIDIOCGMBUF:
508 DEBUG(1, "VIDIOCGMBUF:\n");
509 return -EINVAL;
510 case VIDIOCGUNIT:
511 DEBUG(1, "VIDIOCGUNIT:\n");
512 return -EINVAL;
513 case VIDIOCGCAPTURE:
514 DEBUG(1, "VIDIOCGCAPTURE:\n");
515 return -EINVAL;
516 case VIDIOCSCAPTURE:
517 DEBUG(1, "VIDIOCSCAPTURE:\n");
518 return -EINVAL;
519 case VIDIOCSPLAYMODE:
520 DEBUG(1, "VIDIOCSPLAYMODE:\n");
521 return -EINVAL;
522 case VIDIOCSWRITEMODE:
523 DEBUG(1, "VIDIOCSWRITEMODE:\n");
524 return -EINVAL;
525 case VIDIOCGPLAYINFO:
526 DEBUG(1, "VIDIOCGPLAYINFO:\n");
527 return -EINVAL;
528 case VIDIOCSMICROCODE:
529 DEBUG(1, "VIDIOCSMICROCODE:\n");
530 return -EINVAL;
531 case VIDIOCGVBIFMT:
532 DEBUG(1, "VIDIOCGVBIFMT:\n");
533 return -EINVAL;
534 case VIDIOCSVBIFMT:
535 DEBUG(1, "VIDIOCSVBIFMT:\n");
536 return -EINVAL;
537 default:
538 DEBUG(1, "Unknown ioctl(0x%08x)\n", cmd);
539 return -ENOIOCTLCMD;
540 }
541 return 0;
542}
543
544static int ar_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
545 unsigned long arg)
546{
547 return video_usercopy(inode, file, cmd, arg, ar_do_ioctl);
548}
549
550#if USE_INT
551/*
552 * Interrupt handler
553 */
554static void ar_interrupt(int irq, void *dev, struct pt_regs *regs)
555{
556 struct ar_device *ar = dev;
557 unsigned int line_count;
558 unsigned int line_number;
559 unsigned int arvcr1;
560
561 line_count = ar_inl(ARVHCOUNT); /* line number */
562 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
563 /* operations for interlace mode */
564 if ( line_count < (AR_HEIGHT_VGA/2) ) /* even line */
565 line_number = (line_count << 1);
566 else /* odd line */
567 line_number =
568 (((line_count - (AR_HEIGHT_VGA/2)) << 1) + 1);
569 } else {
570 line_number = line_count;
571 }
572
573 if (line_number == 0) {
574 /*
575 * It is an interrupt for line 0.
576 * we have to start capture.
577 */
578 disable_dma();
579#if 0
580 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* needless? */
581#endif
582 memcpy(ar->frame[0], ar->line_buff, ar->line_bytes);
583#if 0
584 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
585#endif
586 enable_dma();
587 ar->start_capture = 1; /* during capture */
588 return;
589 }
590
591 if (ar->start_capture == 1 && line_number <= (ar->height - 1)) {
592 disable_dma();
593 memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes);
594
595 /*
596 * if captured all line of a frame, disable AR interrupt
597 * and wake a process up.
598 */
599 if (line_number == (ar->height - 1)) { /* end of line */
600
601 ar->start_capture = 0;
602
603 /* disable AR interrupt request */
604 arvcr1 = ar_inl(ARVCR1);
605 arvcr1 &= ~ARVCR1_HIEN; /* clear int. flag */
606 ar_outl(arvcr1, ARVCR1); /* disable */
607 wake_up_interruptible(&ar->wait);
608 } else {
609#if 0
610 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL);
611 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
612#endif
613 enable_dma();
614 }
615 }
616}
617#endif
618
619/*
620 * ar_initialize()
621 * ar_initialize() is called by video_register_device() and
622 * initializes AR LSI and peripherals.
623 *
624 * -1 is returned in all failures.
625 * 0 is returned in success.
626 *
627 */
628static int ar_initialize(struct video_device *dev)
629{
630 struct ar_device *ar = dev->priv;
631 unsigned long cr = 0;
632 int i,found=0;
633
634 DEBUG(1, "ar_initialize:\n");
635
636 /*
637 * initialize AR LSI
638 */
639 ar_outl(0, ARVCR0); /* assert reset of AR LSI */
640 for (i = 0; i < 0x18; i++) /* wait for over 10 cycles @ 27MHz */
641 cpu_relax();
642 ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */
643 for (i = 0; i < 0x40d; i++) /* wait for over 420 cycles @ 27MHz */
644 cpu_relax();
645
646 /* AR uses INT3 of CPU as interrupt pin. */
647 ar_outl(ARINTSEL_INT3, ARINTSEL);
648
649 if (ar->size == AR_SIZE_QVGA)
650 cr |= ARVCR1_QVGA;
651 if (ar->mode == AR_MODE_NORMAL)
652 cr |= ARVCR1_NORMAL;
653 ar_outl(cr, ARVCR1);
654
655 /*
656 * Initialize IIC so that CPU can communicate with AR LSI,
657 * and send boot commands to AR LSI.
658 */
659 init_iic();
660
661 for (i = 0; i < 0x100000; i++) { /* > 0xa1d10, 56ms */
662 if ((ar_inl(ARVCR0) & ARVCR0_VDS)) { /* VSYNC */
663 found = 1;
664 break;
665 }
666 }
667
668 if (found == 0)
669 return -ENODEV;
670
671 printk("arv: Initializing ");
672
673 iic(2,0x78,0x11,0x01,0x00); /* start */
674 iic(3,0x78,0x12,0x00,0x06);
675 iic(3,0x78,0x12,0x12,0x30);
676 iic(3,0x78,0x12,0x15,0x58);
677 iic(3,0x78,0x12,0x17,0x30);
678 printk(".");
679 iic(3,0x78,0x12,0x1a,0x97);
680 iic(3,0x78,0x12,0x1b,0xff);
681 iic(3,0x78,0x12,0x1c,0xff);
682 iic(3,0x78,0x12,0x26,0x10);
683 iic(3,0x78,0x12,0x27,0x00);
684 printk(".");
685 iic(2,0x78,0x34,0x02,0x00);
686 iic(2,0x78,0x7a,0x10,0x00);
687 iic(2,0x78,0x80,0x39,0x00);
688 iic(2,0x78,0x81,0xe6,0x00);
689 iic(2,0x78,0x8d,0x00,0x00);
690 printk(".");
691 iic(2,0x78,0x8e,0x0c,0x00);
692 iic(2,0x78,0x8f,0x00,0x00);
693#if 0
694 iic(2,0x78,0x90,0x00,0x00); /* AWB on=1 off=0 */
695#endif
696 iic(2,0x78,0x93,0x01,0x00);
697 iic(2,0x78,0x94,0xcd,0x00);
698 iic(2,0x78,0x95,0x00,0x00);
699 printk(".");
700 iic(2,0x78,0x96,0xa0,0x00);
701 iic(2,0x78,0x97,0x00,0x00);
702 iic(2,0x78,0x98,0x60,0x00);
703 iic(2,0x78,0x99,0x01,0x00);
704 iic(2,0x78,0x9a,0x19,0x00);
705 printk(".");
706 iic(2,0x78,0x9b,0x02,0x00);
707 iic(2,0x78,0x9c,0xe8,0x00);
708 iic(2,0x78,0x9d,0x02,0x00);
709 iic(2,0x78,0x9e,0x2e,0x00);
710 iic(2,0x78,0xb8,0x78,0x00);
711 iic(2,0x78,0xba,0x05,0x00);
712#if 0
713 iic(2,0x78,0x83,0x8c,0x00); /* brightness */
714#endif
715 printk(".");
716
717 /* color correction */
718 iic(3,0x78,0x49,0x00,0x95); /* a */
719 iic(3,0x78,0x49,0x01,0x96); /* b */
720 iic(3,0x78,0x49,0x03,0x85); /* c */
721 iic(3,0x78,0x49,0x04,0x97); /* d */
722 iic(3,0x78,0x49,0x02,0x7e); /* e(Lo) */
723 iic(3,0x78,0x49,0x05,0xa4); /* f(Lo) */
724 iic(3,0x78,0x49,0x06,0x04); /* e(Hi) */
725 iic(3,0x78,0x49,0x07,0x04); /* e(Hi) */
726 iic(2,0x78,0x48,0x01,0x00); /* on=1 off=0 */
727
728 printk(".");
729 iic(2,0x78,0x11,0x00,0x00); /* end */
730 printk(" done\n");
731 return 0;
732}
733
734
735void ar_release(struct video_device *vfd)
736{
737 struct ar_device *ar = vfd->priv;
738 down(&ar->lock);
739 video_device_release(vfd);
740}
741
742/****************************************************************************
743 *
744 * Video4Linux Module functions
745 *
746 ****************************************************************************/
747static struct file_operations ar_fops = {
748 .owner = THIS_MODULE,
749 .open = video_exclusive_open,
750 .release = video_exclusive_release,
751 .read = ar_read,
752 .ioctl = ar_ioctl,
753 .llseek = no_llseek,
754};
755
756static struct video_device ar_template = {
757 .owner = THIS_MODULE,
758 .name = "Colour AR VGA",
759 .type = VID_TYPE_CAPTURE,
760 .hardware = VID_HARDWARE_ARV,
761 .fops = &ar_fops,
762 .release = ar_release,
763 .minor = -1,
764};
765
766#define ALIGN4(x) ((((int)(x)) & 0x3) == 0)
767static struct ar_device ardev;
768
769static int __init ar_init(void)
770{
771 struct ar_device *ar;
772 int ret;
773 int i;
774
775 DEBUG(1, "ar_init:\n");
776 ret = -EIO;
777 printk(KERN_INFO "arv: Colour AR VGA driver %s\n", VERSION);
778
779 ar = &ardev;
780 memset(ar, 0, sizeof(struct ar_device));
781
782#if USE_INT
783 /* allocate a DMA buffer for 1 line. */
784 ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA);
785 if (ar->line_buff == NULL || ! ALIGN4(ar->line_buff)) {
786 printk("arv: buffer allocation failed for DMA.\n");
787 ret = -ENOMEM;
788 goto out_end;
789 }
790#endif
791 /* allocate buffers for a frame */
792 for (i = 0; i < MAX_AR_HEIGHT; i++) {
793 ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL);
794 if (ar->frame[i] == NULL || ! ALIGN4(ar->frame[i])) {
795 printk("arv: buffer allocation failed for frame.\n");
796 ret = -ENOMEM;
797 goto out_line_buff;
798 }
799 }
800
801 ar->vdev = video_device_alloc();
802 if (!ar->vdev) {
803 printk(KERN_ERR "arv: video_device_alloc() failed\n");
804 return -ENOMEM;
805 }
806 memcpy(ar->vdev, &ar_template, sizeof(ar_template));
807 ar->vdev->priv = ar;
808
809 if (vga) {
810 ar->width = AR_WIDTH_VGA;
811 ar->height = AR_HEIGHT_VGA;
812 ar->size = AR_SIZE_VGA;
813 ar->frame_bytes = AR_FRAME_BYTES_VGA;
814 ar->line_bytes = AR_LINE_BYTES_VGA;
815 if (vga_interlace)
816 ar->mode = AR_MODE_INTERLACE;
817 else
818 ar->mode = AR_MODE_NORMAL;
819 } else {
820 ar->width = AR_WIDTH_QVGA;
821 ar->height = AR_HEIGHT_QVGA;
822 ar->size = AR_SIZE_QVGA;
823 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
824 ar->line_bytes = AR_LINE_BYTES_QVGA;
825 ar->mode = AR_MODE_INTERLACE;
826 }
827 init_MUTEX(&ar->lock);
828 init_waitqueue_head(&ar->wait);
829
830#if USE_INT
831 if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)) {
832 printk("arv: request_irq(%d) failed.\n", M32R_IRQ_INT3);
833 ret = -EIO;
834 goto out_irq;
835 }
836#endif
837
838 if (ar_initialize(ar->vdev) != 0) {
839 printk("arv: M64278 not found.\n");
840 ret = -ENODEV;
841 goto out_dev;
842 }
843
844 /*
845 * ok, we can initialize h/w according to parameters,
846 * so register video device as a frame grabber type.
847 * device is named "video[0-64]".
848 * video_register_device() initializes h/w using ar_initialize().
849 */
850 if (video_register_device(ar->vdev, VFL_TYPE_GRABBER, video_nr) != 0) {
851 /* return -1, -ENFILE(full) or others */
852 printk("arv: register video (Colour AR) failed.\n");
853 ret = -ENODEV;
854 goto out_dev;
855 }
856
857 printk("video%d: Found M64278 VGA (IRQ %d, Freq %dMHz).\n",
858 ar->vdev->minor, M32R_IRQ_INT3, freq);
859
860 return 0;
861
862out_dev:
863#if USE_INT
864 free_irq(M32R_IRQ_INT3, ar);
865
866out_irq:
867#endif
868 for (i = 0; i < MAX_AR_HEIGHT; i++) {
869 if (ar->frame[i])
870 kfree(ar->frame[i]);
871 }
872
873out_line_buff:
874#if USE_INT
875 kfree(ar->line_buff);
876
877out_end:
878#endif
879 return ret;
880}
881
882
883static int __init ar_init_module(void)
884{
885 freq = (boot_cpu_data.bus_clock / 1000000);
886 printk("arv: Bus clock %d\n", freq);
887 if (freq != 50 && freq != 75)
888 freq = DEFAULT_FREQ;
889 return ar_init();
890}
891
892static void __exit ar_cleanup_module(void)
893{
894 struct ar_device *ar;
895 int i;
896
897 ar = &ardev;
898 video_unregister_device(ar->vdev);
899#if USE_INT
900 free_irq(M32R_IRQ_INT3, ar);
901#endif
902 for (i = 0; i < MAX_AR_HEIGHT; i++) {
903 if (ar->frame[i])
904 kfree(ar->frame[i]);
905 }
906#if USE_INT
907 kfree(ar->line_buff);
908#endif
909}
910
911module_init(ar_init_module);
912module_exit(ar_cleanup_module);
913
914MODULE_AUTHOR("Takeo Takahashi <takahashi.takeo@renesas.com>");
915MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux");
916MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 17:37:21 -0500