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path: root/drivers/media/rc/nuvoton-cir.h
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Diffstat (limited to 'drivers/media/rc/nuvoton-cir.h')
-rw-r--r--drivers/media/rc/nuvoton-cir.h17
1 files changed, 14 insertions, 3 deletions
diff --git a/drivers/media/rc/nuvoton-cir.h b/drivers/media/rc/nuvoton-cir.h
index 048135eea702..379795d61ea7 100644
--- a/drivers/media/rc/nuvoton-cir.h
+++ b/drivers/media/rc/nuvoton-cir.h
@@ -330,9 +330,13 @@ struct nvt_dev {
330#define EFER_EFM_DISABLE 0xaa 330#define EFER_EFM_DISABLE 0xaa
331 331
332/* Chip IDs found in CR_CHIP_ID_{HI,LO} */ 332/* Chip IDs found in CR_CHIP_ID_{HI,LO} */
333#define CHIP_ID_HIGH 0xb4 333#define CHIP_ID_HIGH_667 0xa5
334#define CHIP_ID_LOW 0x72 334#define CHIP_ID_HIGH_677B 0xb4
335#define CHIP_ID_LOW2 0x73 335#define CHIP_ID_HIGH_677C 0xc3
336#define CHIP_ID_LOW_667 0x13
337#define CHIP_ID_LOW_677B2 0x72
338#define CHIP_ID_LOW_677B3 0x73
339#define CHIP_ID_LOW_677C 0x33
336 340
337/* Config regs we need to care about */ 341/* Config regs we need to care about */
338#define CR_SOFTWARE_RESET 0x02 342#define CR_SOFTWARE_RESET 0x02
@@ -341,6 +345,7 @@ struct nvt_dev {
341#define CR_CHIP_ID_LO 0x21 345#define CR_CHIP_ID_LO 0x21
342#define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */ 346#define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
343#define CR_OUTPUT_PIN_SEL 0x27 347#define CR_OUTPUT_PIN_SEL 0x27
348#define CR_MULTIFUNC_PIN_SEL 0x2c
344#define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */ 349#define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
345/* next three regs valid for both the CIR and CIR_WAKE logical devices */ 350/* next three regs valid for both the CIR and CIR_WAKE logical devices */
346#define CR_CIR_BASE_ADDR_HI 0x60 351#define CR_CIR_BASE_ADDR_HI 0x60
@@ -364,10 +369,16 @@ struct nvt_dev {
364#define CIR_INTR_MOUSE_IRQ_BIT 0x80 369#define CIR_INTR_MOUSE_IRQ_BIT 0x80
365#define PME_INTR_CIR_PASS_BIT 0x08 370#define PME_INTR_CIR_PASS_BIT 0x08
366 371
372/* w83677hg CIR pin config */
367#define OUTPUT_PIN_SEL_MASK 0xbc 373#define OUTPUT_PIN_SEL_MASK 0xbc
368#define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */ 374#define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
369#define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */ 375#define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
370 376
377/* w83667hg CIR pin config */
378#define MULTIFUNC_PIN_SEL_MASK 0x1f
379#define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
380#define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
381
371/* MCE CIR signal length, related on sample period */ 382/* MCE CIR signal length, related on sample period */
372 383
373/* MCE CIR controller signal length: about 43ms 384/* MCE CIR controller signal length: about 43ms