diff options
Diffstat (limited to 'drivers/media/platform/omap3isp/isphist.c')
-rw-r--r-- | drivers/media/platform/omap3isp/isphist.c | 127 |
1 files changed, 76 insertions, 51 deletions
diff --git a/drivers/media/platform/omap3isp/isphist.c b/drivers/media/platform/omap3isp/isphist.c index ce822c34c843..7138b043a4aa 100644 --- a/drivers/media/platform/omap3isp/isphist.c +++ b/drivers/media/platform/omap3isp/isphist.c | |||
@@ -16,20 +16,18 @@ | |||
16 | */ | 16 | */ |
17 | 17 | ||
18 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
19 | #include <linux/device.h> | ||
20 | #include <linux/dmaengine.h> | ||
21 | #include <linux/omap-dmaengine.h> | ||
19 | #include <linux/slab.h> | 22 | #include <linux/slab.h> |
20 | #include <linux/uaccess.h> | 23 | #include <linux/uaccess.h> |
21 | #include <linux/device.h> | ||
22 | 24 | ||
23 | #include "isp.h" | 25 | #include "isp.h" |
24 | #include "ispreg.h" | 26 | #include "ispreg.h" |
25 | #include "isphist.h" | 27 | #include "isphist.h" |
26 | 28 | ||
27 | #define OMAP24XX_DMA_NO_DEVICE 0 | ||
28 | |||
29 | #define HIST_CONFIG_DMA 1 | 29 | #define HIST_CONFIG_DMA 1 |
30 | 30 | ||
31 | #define HIST_USING_DMA(hist) ((hist)->dma_ch >= 0) | ||
32 | |||
33 | /* | 31 | /* |
34 | * hist_reset_mem - clear Histogram memory before start stats engine. | 32 | * hist_reset_mem - clear Histogram memory before start stats engine. |
35 | */ | 33 | */ |
@@ -62,20 +60,6 @@ static void hist_reset_mem(struct ispstat *hist) | |||
62 | hist->wait_acc_frames = conf->num_acc_frames; | 60 | hist->wait_acc_frames = conf->num_acc_frames; |
63 | } | 61 | } |
64 | 62 | ||
65 | static void hist_dma_config(struct ispstat *hist) | ||
66 | { | ||
67 | struct isp_device *isp = hist->isp; | ||
68 | |||
69 | hist->dma_config.data_type = OMAP_DMA_DATA_TYPE_S32; | ||
70 | hist->dma_config.sync_mode = OMAP_DMA_SYNC_ELEMENT; | ||
71 | hist->dma_config.frame_count = 1; | ||
72 | hist->dma_config.src_amode = OMAP_DMA_AMODE_CONSTANT; | ||
73 | hist->dma_config.src_start = isp->mmio_base_phys[OMAP3_ISP_IOMEM_HIST] | ||
74 | + ISPHIST_DATA; | ||
75 | hist->dma_config.dst_amode = OMAP_DMA_AMODE_POST_INC; | ||
76 | hist->dma_config.src_or_dst_synch = OMAP_DMA_SRC_SYNC; | ||
77 | } | ||
78 | |||
79 | /* | 63 | /* |
80 | * hist_setup_regs - Helper function to update Histogram registers. | 64 | * hist_setup_regs - Helper function to update Histogram registers. |
81 | */ | 65 | */ |
@@ -176,17 +160,12 @@ static int hist_busy(struct ispstat *hist) | |||
176 | & ISPHIST_PCR_BUSY; | 160 | & ISPHIST_PCR_BUSY; |
177 | } | 161 | } |
178 | 162 | ||
179 | static void hist_dma_cb(int lch, u16 ch_status, void *data) | 163 | static void hist_dma_cb(void *data) |
180 | { | 164 | { |
181 | struct ispstat *hist = data; | 165 | struct ispstat *hist = data; |
182 | 166 | ||
183 | if (ch_status & ~OMAP_DMA_BLOCK_IRQ) { | 167 | /* FIXME: The DMA engine API can't report transfer errors :-/ */ |
184 | dev_dbg(hist->isp->dev, "hist: DMA error. status = 0x%04x\n", | 168 | |
185 | ch_status); | ||
186 | omap_stop_dma(lch); | ||
187 | hist_reset_mem(hist); | ||
188 | atomic_set(&hist->buf_err, 1); | ||
189 | } | ||
190 | isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, | 169 | isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, |
191 | ISPHIST_CNT_CLEAR); | 170 | ISPHIST_CNT_CLEAR); |
192 | 171 | ||
@@ -198,24 +177,57 @@ static void hist_dma_cb(int lch, u16 ch_status, void *data) | |||
198 | static int hist_buf_dma(struct ispstat *hist) | 177 | static int hist_buf_dma(struct ispstat *hist) |
199 | { | 178 | { |
200 | dma_addr_t dma_addr = hist->active_buf->dma_addr; | 179 | dma_addr_t dma_addr = hist->active_buf->dma_addr; |
180 | struct dma_async_tx_descriptor *tx; | ||
181 | struct dma_slave_config cfg; | ||
182 | dma_cookie_t cookie; | ||
183 | int ret; | ||
201 | 184 | ||
202 | if (unlikely(!dma_addr)) { | 185 | if (unlikely(!dma_addr)) { |
203 | dev_dbg(hist->isp->dev, "hist: invalid DMA buffer address\n"); | 186 | dev_dbg(hist->isp->dev, "hist: invalid DMA buffer address\n"); |
204 | hist_reset_mem(hist); | 187 | goto error; |
205 | return STAT_NO_BUF; | ||
206 | } | 188 | } |
207 | 189 | ||
208 | isp_reg_writel(hist->isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR); | 190 | isp_reg_writel(hist->isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR); |
209 | isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, | 191 | isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, |
210 | ISPHIST_CNT_CLEAR); | 192 | ISPHIST_CNT_CLEAR); |
211 | omap3isp_flush(hist->isp); | 193 | omap3isp_flush(hist->isp); |
212 | hist->dma_config.dst_start = dma_addr; | ||
213 | hist->dma_config.elem_count = hist->buf_size / sizeof(u32); | ||
214 | omap_set_dma_params(hist->dma_ch, &hist->dma_config); | ||
215 | 194 | ||
216 | omap_start_dma(hist->dma_ch); | 195 | memset(&cfg, 0, sizeof(cfg)); |
196 | cfg.src_addr = hist->isp->mmio_hist_base_phys + ISPHIST_DATA; | ||
197 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
198 | cfg.src_maxburst = hist->buf_size / 4; | ||
199 | |||
200 | ret = dmaengine_slave_config(hist->dma_ch, &cfg); | ||
201 | if (ret < 0) { | ||
202 | dev_dbg(hist->isp->dev, | ||
203 | "hist: DMA slave configuration failed\n"); | ||
204 | goto error; | ||
205 | } | ||
206 | |||
207 | tx = dmaengine_prep_slave_single(hist->dma_ch, dma_addr, | ||
208 | hist->buf_size, DMA_DEV_TO_MEM, | ||
209 | DMA_CTRL_ACK); | ||
210 | if (tx == NULL) { | ||
211 | dev_dbg(hist->isp->dev, | ||
212 | "hist: DMA slave preparation failed\n"); | ||
213 | goto error; | ||
214 | } | ||
215 | |||
216 | tx->callback = hist_dma_cb; | ||
217 | tx->callback_param = hist; | ||
218 | cookie = tx->tx_submit(tx); | ||
219 | if (dma_submit_error(cookie)) { | ||
220 | dev_dbg(hist->isp->dev, "hist: DMA submission failed\n"); | ||
221 | goto error; | ||
222 | } | ||
223 | |||
224 | dma_async_issue_pending(hist->dma_ch); | ||
217 | 225 | ||
218 | return STAT_BUF_WAITING_DMA; | 226 | return STAT_BUF_WAITING_DMA; |
227 | |||
228 | error: | ||
229 | hist_reset_mem(hist); | ||
230 | return STAT_NO_BUF; | ||
219 | } | 231 | } |
220 | 232 | ||
221 | static int hist_buf_pio(struct ispstat *hist) | 233 | static int hist_buf_pio(struct ispstat *hist) |
@@ -272,7 +284,7 @@ static int hist_buf_process(struct ispstat *hist) | |||
272 | if (--(hist->wait_acc_frames)) | 284 | if (--(hist->wait_acc_frames)) |
273 | return STAT_NO_BUF; | 285 | return STAT_NO_BUF; |
274 | 286 | ||
275 | if (HIST_USING_DMA(hist)) | 287 | if (hist->dma_ch) |
276 | ret = hist_buf_dma(hist); | 288 | ret = hist_buf_dma(hist); |
277 | else | 289 | else |
278 | ret = hist_buf_pio(hist); | 290 | ret = hist_buf_pio(hist); |
@@ -473,18 +485,28 @@ int omap3isp_hist_init(struct isp_device *isp) | |||
473 | 485 | ||
474 | hist->isp = isp; | 486 | hist->isp = isp; |
475 | 487 | ||
476 | if (HIST_CONFIG_DMA) | 488 | if (HIST_CONFIG_DMA) { |
477 | ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE, "DMA_ISP_HIST", | 489 | struct platform_device *pdev = to_platform_device(isp->dev); |
478 | hist_dma_cb, hist, &hist->dma_ch); | 490 | struct resource *res; |
479 | if (ret) { | 491 | unsigned int sig = 0; |
480 | if (HIST_CONFIG_DMA) | 492 | dma_cap_mask_t mask; |
481 | dev_warn(isp->dev, "hist: DMA request channel failed. " | 493 | |
482 | "Using PIO only.\n"); | 494 | dma_cap_zero(mask); |
483 | hist->dma_ch = -1; | 495 | dma_cap_set(DMA_SLAVE, mask); |
484 | } else { | 496 | |
485 | dev_dbg(isp->dev, "hist: DMA channel = %d\n", hist->dma_ch); | 497 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
486 | hist_dma_config(hist); | 498 | "hist"); |
487 | omap_enable_dma_irq(hist->dma_ch, OMAP_DMA_BLOCK_IRQ); | 499 | if (res) |
500 | sig = res->start; | ||
501 | |||
502 | hist->dma_ch = dma_request_slave_channel_compat(mask, | ||
503 | omap_dma_filter_fn, &sig, isp->dev, "hist"); | ||
504 | if (!hist->dma_ch) | ||
505 | dev_warn(isp->dev, | ||
506 | "hist: DMA channel request failed, using PIO\n"); | ||
507 | else | ||
508 | dev_dbg(isp->dev, "hist: using DMA channel %s\n", | ||
509 | dma_chan_name(hist->dma_ch)); | ||
488 | } | 510 | } |
489 | 511 | ||
490 | hist->ops = &hist_ops; | 512 | hist->ops = &hist_ops; |
@@ -493,8 +515,8 @@ int omap3isp_hist_init(struct isp_device *isp) | |||
493 | 515 | ||
494 | ret = omap3isp_stat_init(hist, "histogram", &hist_subdev_ops); | 516 | ret = omap3isp_stat_init(hist, "histogram", &hist_subdev_ops); |
495 | if (ret) { | 517 | if (ret) { |
496 | if (HIST_USING_DMA(hist)) | 518 | if (hist->dma_ch) |
497 | omap_free_dma(hist->dma_ch); | 519 | dma_release_channel(hist->dma_ch); |
498 | } | 520 | } |
499 | 521 | ||
500 | return ret; | 522 | return ret; |
@@ -505,7 +527,10 @@ int omap3isp_hist_init(struct isp_device *isp) | |||
505 | */ | 527 | */ |
506 | void omap3isp_hist_cleanup(struct isp_device *isp) | 528 | void omap3isp_hist_cleanup(struct isp_device *isp) |
507 | { | 529 | { |
508 | if (HIST_USING_DMA(&isp->isp_hist)) | 530 | struct ispstat *hist = &isp->isp_hist; |
509 | omap_free_dma(isp->isp_hist.dma_ch); | 531 | |
510 | omap3isp_stat_cleanup(&isp->isp_hist); | 532 | if (hist->dma_ch) |
533 | dma_release_channel(hist->dma_ch); | ||
534 | |||
535 | omap3isp_stat_cleanup(hist); | ||
511 | } | 536 | } |