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path: root/drivers/media/i2c/adv7604.c
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Diffstat (limited to 'drivers/media/i2c/adv7604.c')
-rw-r--r--drivers/media/i2c/adv7604.c945
1 files changed, 476 insertions, 469 deletions
diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c
index d228b7c82310..60ffcf098bef 100644
--- a/drivers/media/i2c/adv7604.c
+++ b/drivers/media/i2c/adv7604.c
@@ -53,41 +53,41 @@ MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53MODULE_LICENSE("GPL"); 53MODULE_LICENSE("GPL");
54 54
55/* ADV7604 system clock frequency */ 55/* ADV7604 system clock frequency */
56#define ADV7604_fsc (28636360) 56#define ADV76XX_FSC (28636360)
57 57
58#define ADV7604_RGB_OUT (1 << 1) 58#define ADV76XX_RGB_OUT (1 << 1)
59 59
60#define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0) 60#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
61#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0) 61#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
62#define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0) 62#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
63 63
64#define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5) 64#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
65#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5) 65#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
66#define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5) 66#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
67#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5) 67#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
68#define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5) 68#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
69#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5) 69#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
70 70
71#define ADV7604_OP_CH_SEL_GBR (0 << 5) 71#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
72#define ADV7604_OP_CH_SEL_GRB (1 << 5) 72#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
73#define ADV7604_OP_CH_SEL_BGR (2 << 5) 73#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
74#define ADV7604_OP_CH_SEL_RGB (3 << 5) 74#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
75#define ADV7604_OP_CH_SEL_BRG (4 << 5) 75#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
76#define ADV7604_OP_CH_SEL_RBG (5 << 5) 76#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
77 77
78#define ADV7604_OP_SWAP_CB_CR (1 << 0) 78#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
79 79
80enum adv7604_type { 80enum adv76xx_type {
81 ADV7604, 81 ADV7604,
82 ADV7611, 82 ADV7611,
83}; 83};
84 84
85struct adv7604_reg_seq { 85struct adv76xx_reg_seq {
86 unsigned int reg; 86 unsigned int reg;
87 u8 val; 87 u8 val;
88}; 88};
89 89
90struct adv7604_format_info { 90struct adv76xx_format_info {
91 u32 code; 91 u32 code;
92 u8 op_ch_sel; 92 u8 op_ch_sel;
93 bool rgb_out; 93 bool rgb_out;
@@ -95,8 +95,8 @@ struct adv7604_format_info {
95 u8 op_format_sel; 95 u8 op_format_sel;
96}; 96};
97 97
98struct adv7604_chip_info { 98struct adv76xx_chip_info {
99 enum adv7604_type type; 99 enum adv76xx_type type;
100 100
101 bool has_afe; 101 bool has_afe;
102 unsigned int max_port; 102 unsigned int max_port;
@@ -109,8 +109,9 @@ struct adv7604_chip_info {
109 unsigned int cable_det_mask; 109 unsigned int cable_det_mask;
110 unsigned int tdms_lock_mask; 110 unsigned int tdms_lock_mask;
111 unsigned int fmt_change_digital_mask; 111 unsigned int fmt_change_digital_mask;
112 unsigned int cp_csc;
112 113
113 const struct adv7604_format_info *formats; 114 const struct adv76xx_format_info *formats;
114 unsigned int nformats; 115 unsigned int nformats;
115 116
116 void (*set_termination)(struct v4l2_subdev *sd, bool enable); 117 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
@@ -119,7 +120,7 @@ struct adv7604_chip_info {
119 unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 120 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
120 121
121 /* 0 = AFE, 1 = HDMI */ 122 /* 0 = AFE, 1 = HDMI */
122 const struct adv7604_reg_seq *recommended_settings[2]; 123 const struct adv76xx_reg_seq *recommended_settings[2];
123 unsigned int num_recommended_settings[2]; 124 unsigned int num_recommended_settings[2];
124 125
125 unsigned long page_mask; 126 unsigned long page_mask;
@@ -133,22 +134,22 @@ struct adv7604_chip_info {
133 ********************************************************************** 134 **********************************************************************
134 */ 135 */
135 136
136struct adv7604_state { 137struct adv76xx_state {
137 const struct adv7604_chip_info *info; 138 const struct adv76xx_chip_info *info;
138 struct adv7604_platform_data pdata; 139 struct adv76xx_platform_data pdata;
139 140
140 struct gpio_desc *hpd_gpio[4]; 141 struct gpio_desc *hpd_gpio[4];
141 142
142 struct v4l2_subdev sd; 143 struct v4l2_subdev sd;
143 struct media_pad pads[ADV7604_PAD_MAX]; 144 struct media_pad pads[ADV76XX_PAD_MAX];
144 unsigned int source_pad; 145 unsigned int source_pad;
145 146
146 struct v4l2_ctrl_handler hdl; 147 struct v4l2_ctrl_handler hdl;
147 148
148 enum adv7604_pad selected_input; 149 enum adv76xx_pad selected_input;
149 150
150 struct v4l2_dv_timings timings; 151 struct v4l2_dv_timings timings;
151 const struct adv7604_format_info *format; 152 const struct adv76xx_format_info *format;
152 153
153 struct { 154 struct {
154 u8 edid[256]; 155 u8 edid[256];
@@ -163,7 +164,7 @@ struct adv7604_state {
163 bool restart_stdi_once; 164 bool restart_stdi_once;
164 165
165 /* i2c clients */ 166 /* i2c clients */
166 struct i2c_client *i2c_clients[ADV7604_PAGE_MAX]; 167 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
167 168
168 /* controls */ 169 /* controls */
169 struct v4l2_ctrl *detect_tx_5v_ctrl; 170 struct v4l2_ctrl *detect_tx_5v_ctrl;
@@ -173,13 +174,13 @@ struct adv7604_state {
173 struct v4l2_ctrl *rgb_quantization_range_ctrl; 174 struct v4l2_ctrl *rgb_quantization_range_ctrl;
174}; 175};
175 176
176static bool adv7604_has_afe(struct adv7604_state *state) 177static bool adv76xx_has_afe(struct adv76xx_state *state)
177{ 178{
178 return state->info->has_afe; 179 return state->info->has_afe;
179} 180}
180 181
181/* Supported CEA and DMT timings */ 182/* Supported CEA and DMT timings */
182static const struct v4l2_dv_timings adv7604_timings[] = { 183static const struct v4l2_dv_timings adv76xx_timings[] = {
183 V4L2_DV_BT_CEA_720X480P59_94, 184 V4L2_DV_BT_CEA_720X480P59_94,
184 V4L2_DV_BT_CEA_720X576P50, 185 V4L2_DV_BT_CEA_720X576P50,
185 V4L2_DV_BT_CEA_1280X720P24, 186 V4L2_DV_BT_CEA_1280X720P24,
@@ -243,14 +244,14 @@ static const struct v4l2_dv_timings adv7604_timings[] = {
243 { }, 244 { },
244}; 245};
245 246
246struct adv7604_video_standards { 247struct adv76xx_video_standards {
247 struct v4l2_dv_timings timings; 248 struct v4l2_dv_timings timings;
248 u8 vid_std; 249 u8 vid_std;
249 u8 v_freq; 250 u8 v_freq;
250}; 251};
251 252
252/* sorted by number of lines */ 253/* sorted by number of lines */
253static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { 254static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
254 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 255 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
255 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 256 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
256 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 257 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
@@ -265,7 +266,7 @@ static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
265}; 266};
266 267
267/* sorted by number of lines */ 268/* sorted by number of lines */
268static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { 269static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
269 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 270 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
270 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 271 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
271 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 272 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
@@ -293,7 +294,7 @@ static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
293}; 294};
294 295
295/* sorted by number of lines */ 296/* sorted by number of lines */
296static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { 297static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
297 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 298 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
298 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 299 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
299 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 300 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
@@ -307,7 +308,7 @@ static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
307}; 308};
308 309
309/* sorted by number of lines */ 310/* sorted by number of lines */
310static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { 311static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
311 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 312 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
312 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 313 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
313 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 314 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
@@ -328,9 +329,9 @@ static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
328 329
329/* ----------------------------------------------------------------------- */ 330/* ----------------------------------------------------------------------- */
330 331
331static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) 332static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
332{ 333{
333 return container_of(sd, struct adv7604_state, sd); 334 return container_of(sd, struct adv76xx_state, sd);
334} 335}
335 336
336static inline unsigned htotal(const struct v4l2_bt_timings *t) 337static inline unsigned htotal(const struct v4l2_bt_timings *t)
@@ -360,15 +361,15 @@ static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
360 return -EIO; 361 return -EIO;
361} 362}
362 363
363static s32 adv_smbus_read_byte_data(struct adv7604_state *state, 364static s32 adv_smbus_read_byte_data(struct adv76xx_state *state,
364 enum adv7604_page page, u8 command) 365 enum adv76xx_page page, u8 command)
365{ 366{
366 return adv_smbus_read_byte_data_check(state->i2c_clients[page], 367 return adv_smbus_read_byte_data_check(state->i2c_clients[page],
367 command, true); 368 command, true);
368} 369}
369 370
370static s32 adv_smbus_write_byte_data(struct adv7604_state *state, 371static s32 adv_smbus_write_byte_data(struct adv76xx_state *state,
371 enum adv7604_page page, u8 command, 372 enum adv76xx_page page, u8 command,
372 u8 value) 373 u8 value)
373{ 374{
374 struct i2c_client *client = state->i2c_clients[page]; 375 struct i2c_client *client = state->i2c_clients[page];
@@ -391,8 +392,8 @@ static s32 adv_smbus_write_byte_data(struct adv7604_state *state,
391 return err; 392 return err;
392} 393}
393 394
394static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state, 395static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state,
395 enum adv7604_page page, u8 command, 396 enum adv76xx_page page, u8 command,
396 unsigned length, const u8 *values) 397 unsigned length, const u8 *values)
397{ 398{
398 struct i2c_client *client = state->i2c_clients[page]; 399 struct i2c_client *client = state->i2c_clients[page];
@@ -411,16 +412,16 @@ static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state,
411 412
412static inline int io_read(struct v4l2_subdev *sd, u8 reg) 413static inline int io_read(struct v4l2_subdev *sd, u8 reg)
413{ 414{
414 struct adv7604_state *state = to_state(sd); 415 struct adv76xx_state *state = to_state(sd);
415 416
416 return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg); 417 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg);
417} 418}
418 419
419static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 420static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
420{ 421{
421 struct adv7604_state *state = to_state(sd); 422 struct adv76xx_state *state = to_state(sd);
422 423
423 return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val); 424 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val);
424} 425}
425 426
426static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 427static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
@@ -430,73 +431,73 @@ static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 v
430 431
431static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 432static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
432{ 433{
433 struct adv7604_state *state = to_state(sd); 434 struct adv76xx_state *state = to_state(sd);
434 435
435 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg); 436 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
436} 437}
437 438
438static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 439static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
439{ 440{
440 struct adv7604_state *state = to_state(sd); 441 struct adv76xx_state *state = to_state(sd);
441 442
442 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val); 443 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
443} 444}
444 445
445static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 446static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
446{ 447{
447 struct adv7604_state *state = to_state(sd); 448 struct adv76xx_state *state = to_state(sd);
448 449
449 return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg); 450 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg);
450} 451}
451 452
452static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 453static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
453{ 454{
454 struct adv7604_state *state = to_state(sd); 455 struct adv76xx_state *state = to_state(sd);
455 456
456 return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val); 457 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val);
457} 458}
458 459
459static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 460static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
460{ 461{
461 struct adv7604_state *state = to_state(sd); 462 struct adv76xx_state *state = to_state(sd);
462 463
463 return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg); 464 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg);
464} 465}
465 466
466static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 467static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
467{ 468{
468 struct adv7604_state *state = to_state(sd); 469 struct adv76xx_state *state = to_state(sd);
469 470
470 return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME, 471 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME,
471 reg, val); 472 reg, val);
472} 473}
473 474
474static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 475static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
475{ 476{
476 struct adv7604_state *state = to_state(sd); 477 struct adv76xx_state *state = to_state(sd);
477 478
478 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg); 479 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg);
479} 480}
480 481
481static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 482static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
482{ 483{
483 struct adv7604_state *state = to_state(sd); 484 struct adv76xx_state *state = to_state(sd);
484 485
485 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val); 486 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val);
486} 487}
487 488
488static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 489static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
489{ 490{
490 struct adv7604_state *state = to_state(sd); 491 struct adv76xx_state *state = to_state(sd);
491 492
492 return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg); 493 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg);
493} 494}
494 495
495static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 496static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
496{ 497{
497 struct adv7604_state *state = to_state(sd); 498 struct adv76xx_state *state = to_state(sd);
498 499
499 return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val); 500 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val);
500} 501}
501 502
502static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 503static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
@@ -506,64 +507,60 @@ static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8
506 507
507static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 508static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
508{ 509{
509 struct adv7604_state *state = to_state(sd); 510 struct adv76xx_state *state = to_state(sd);
510 511
511 return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg); 512 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg);
512} 513}
513 514
514static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 515static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
515{ 516{
516 struct adv7604_state *state = to_state(sd); 517 struct adv76xx_state *state = to_state(sd);
517 518
518 return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val); 519 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val);
519} 520}
520 521
521static inline int edid_write_block(struct v4l2_subdev *sd, 522static inline int edid_write_block(struct v4l2_subdev *sd,
522 unsigned len, const u8 *val) 523 unsigned len, const u8 *val)
523{ 524{
524 struct adv7604_state *state = to_state(sd); 525 struct adv76xx_state *state = to_state(sd);
525 int err = 0; 526 int err = 0;
526 int i; 527 int i;
527 528
528 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); 529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
529 530
530 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) 531 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
531 err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID, 532 err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID,
532 i, I2C_SMBUS_BLOCK_MAX, val + i); 533 i, I2C_SMBUS_BLOCK_MAX, val + i);
533 return err; 534 return err;
534} 535}
535 536
536static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd) 537static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
537{ 538{
538 unsigned int i; 539 unsigned int i;
539 540
540 for (i = 0; i < state->info->num_dv_ports; ++i) { 541 for (i = 0; i < state->info->num_dv_ports; ++i)
541 if (IS_ERR(state->hpd_gpio[i]))
542 continue;
543
544 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); 542 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
545 }
546 543
547 v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd); 544 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
548} 545}
549 546
550static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) 547static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
551{ 548{
552 struct delayed_work *dwork = to_delayed_work(work); 549 struct delayed_work *dwork = to_delayed_work(work);
553 struct adv7604_state *state = container_of(dwork, struct adv7604_state, 550 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
554 delayed_work_enable_hotplug); 551 delayed_work_enable_hotplug);
555 struct v4l2_subdev *sd = &state->sd; 552 struct v4l2_subdev *sd = &state->sd;
556 553
557 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 554 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
558 555
559 adv7604_set_hpd(state, state->edid.present); 556 adv76xx_set_hpd(state, state->edid.present);
560} 557}
561 558
562static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 559static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
563{ 560{
564 struct adv7604_state *state = to_state(sd); 561 struct adv76xx_state *state = to_state(sd);
565 562
566 return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg); 563 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg);
567} 564}
568 565
569static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 566static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
@@ -573,9 +570,9 @@ static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
573 570
574static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 571static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
575{ 572{
576 struct adv7604_state *state = to_state(sd); 573 struct adv76xx_state *state = to_state(sd);
577 574
578 return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val); 575 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val);
579} 576}
580 577
581static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 578static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
@@ -585,16 +582,16 @@ static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8
585 582
586static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 583static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
587{ 584{
588 struct adv7604_state *state = to_state(sd); 585 struct adv76xx_state *state = to_state(sd);
589 586
590 return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val); 587 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val);
591} 588}
592 589
593static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 590static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
594{ 591{
595 struct adv7604_state *state = to_state(sd); 592 struct adv76xx_state *state = to_state(sd);
596 593
597 return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg); 594 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg);
598} 595}
599 596
600static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 597static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
@@ -604,9 +601,9 @@ static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
604 601
605static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 602static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
606{ 603{
607 struct adv7604_state *state = to_state(sd); 604 struct adv76xx_state *state = to_state(sd);
608 605
609 return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val); 606 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val);
610} 607}
611 608
612static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 609static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
@@ -616,25 +613,25 @@ static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 v
616 613
617static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 614static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
618{ 615{
619 struct adv7604_state *state = to_state(sd); 616 struct adv76xx_state *state = to_state(sd);
620 617
621 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg); 618 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
622} 619}
623 620
624static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 621static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
625{ 622{
626 struct adv7604_state *state = to_state(sd); 623 struct adv76xx_state *state = to_state(sd);
627 624
628 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val); 625 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
629} 626}
630 627
631#define ADV7604_REG(page, offset) (((page) << 8) | (offset)) 628#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
632#define ADV7604_REG_SEQ_TERM 0xffff 629#define ADV76XX_REG_SEQ_TERM 0xffff
633 630
634#ifdef CONFIG_VIDEO_ADV_DEBUG 631#ifdef CONFIG_VIDEO_ADV_DEBUG
635static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg) 632static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
636{ 633{
637 struct adv7604_state *state = to_state(sd); 634 struct adv76xx_state *state = to_state(sd);
638 unsigned int page = reg >> 8; 635 unsigned int page = reg >> 8;
639 636
640 if (!(BIT(page) & state->info->page_mask)) 637 if (!(BIT(page) & state->info->page_mask))
@@ -646,9 +643,9 @@ static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg)
646} 643}
647#endif 644#endif
648 645
649static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 646static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
650{ 647{
651 struct adv7604_state *state = to_state(sd); 648 struct adv76xx_state *state = to_state(sd);
652 unsigned int page = reg >> 8; 649 unsigned int page = reg >> 8;
653 650
654 if (!(BIT(page) & state->info->page_mask)) 651 if (!(BIT(page) & state->info->page_mask))
@@ -659,91 +656,91 @@ static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
659 return adv_smbus_write_byte_data(state, page, reg, val); 656 return adv_smbus_write_byte_data(state, page, reg, val);
660} 657}
661 658
662static void adv7604_write_reg_seq(struct v4l2_subdev *sd, 659static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
663 const struct adv7604_reg_seq *reg_seq) 660 const struct adv76xx_reg_seq *reg_seq)
664{ 661{
665 unsigned int i; 662 unsigned int i;
666 663
667 for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++) 664 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
668 adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 665 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
669} 666}
670 667
671/* ----------------------------------------------------------------------------- 668/* -----------------------------------------------------------------------------
672 * Format helpers 669 * Format helpers
673 */ 670 */
674 671
675static const struct adv7604_format_info adv7604_formats[] = { 672static const struct adv76xx_format_info adv7604_formats[] = {
676 { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, 673 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
677 ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, 674 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
678 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, 675 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
679 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 676 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
680 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, 677 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
681 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 678 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
682 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false, 679 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
683 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 680 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
684 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true, 681 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
685 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT }, 682 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
686 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, 683 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
687 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 684 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
688 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, 685 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
689 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 686 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
690 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, 687 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
691 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 688 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
692 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, 689 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
693 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 690 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
694 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, 691 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
695 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
696 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, 693 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
697 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
698 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false, 695 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
699 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
700 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true, 697 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
701 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
702 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false, 699 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
703 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
704 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true, 701 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
705 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT }, 702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
706 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, 703 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
707 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
708 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, 705 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
709 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
710 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, 707 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
711 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 708 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
712 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, 709 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
713 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 710 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
714}; 711};
715 712
716static const struct adv7604_format_info adv7611_formats[] = { 713static const struct adv76xx_format_info adv7611_formats[] = {
717 { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false, 714 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
718 ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT }, 715 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
719 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false, 716 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
720 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 717 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
721 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true, 718 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
722 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT }, 719 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
723 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false, 720 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
724 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 721 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
725 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true, 722 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
726 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT }, 723 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
727 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false, 724 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
728 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
729 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true, 726 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
730 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 727 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
731 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false, 728 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
732 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 729 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
733 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true, 730 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
734 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT }, 731 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
735 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false, 732 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
736 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 733 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
737 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true, 734 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
738 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 735 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
739 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false, 736 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
740 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 737 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
741 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true, 738 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
742 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT }, 739 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
743}; 740};
744 741
745static const struct adv7604_format_info * 742static const struct adv76xx_format_info *
746adv7604_format_info(struct adv7604_state *state, u32 code) 743adv76xx_format_info(struct adv76xx_state *state, u32 code)
747{ 744{
748 unsigned int i; 745 unsigned int i;
749 746
@@ -759,7 +756,7 @@ adv7604_format_info(struct adv7604_state *state, u32 code)
759 756
760static inline bool is_analog_input(struct v4l2_subdev *sd) 757static inline bool is_analog_input(struct v4l2_subdev *sd)
761{ 758{
762 struct adv7604_state *state = to_state(sd); 759 struct adv76xx_state *state = to_state(sd);
763 760
764 return state->selected_input == ADV7604_PAD_VGA_RGB || 761 return state->selected_input == ADV7604_PAD_VGA_RGB ||
765 state->selected_input == ADV7604_PAD_VGA_COMP; 762 state->selected_input == ADV7604_PAD_VGA_COMP;
@@ -767,9 +764,9 @@ static inline bool is_analog_input(struct v4l2_subdev *sd)
767 764
768static inline bool is_digital_input(struct v4l2_subdev *sd) 765static inline bool is_digital_input(struct v4l2_subdev *sd)
769{ 766{
770 struct adv7604_state *state = to_state(sd); 767 struct adv76xx_state *state = to_state(sd);
771 768
772 return state->selected_input == ADV7604_PAD_HDMI_PORT_A || 769 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
773 state->selected_input == ADV7604_PAD_HDMI_PORT_B || 770 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
774 state->selected_input == ADV7604_PAD_HDMI_PORT_C || 771 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
775 state->selected_input == ADV7604_PAD_HDMI_PORT_D; 772 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
@@ -778,7 +775,7 @@ static inline bool is_digital_input(struct v4l2_subdev *sd)
778/* ----------------------------------------------------------------------- */ 775/* ----------------------------------------------------------------------- */
779 776
780#ifdef CONFIG_VIDEO_ADV_DEBUG 777#ifdef CONFIG_VIDEO_ADV_DEBUG
781static void adv7604_inv_register(struct v4l2_subdev *sd) 778static void adv76xx_inv_register(struct v4l2_subdev *sd)
782{ 779{
783 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 780 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
784 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 781 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
@@ -795,15 +792,15 @@ static void adv7604_inv_register(struct v4l2_subdev *sd)
795 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 792 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
796} 793}
797 794
798static int adv7604_g_register(struct v4l2_subdev *sd, 795static int adv76xx_g_register(struct v4l2_subdev *sd,
799 struct v4l2_dbg_register *reg) 796 struct v4l2_dbg_register *reg)
800{ 797{
801 int ret; 798 int ret;
802 799
803 ret = adv7604_read_reg(sd, reg->reg); 800 ret = adv76xx_read_reg(sd, reg->reg);
804 if (ret < 0) { 801 if (ret < 0) {
805 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 802 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
806 adv7604_inv_register(sd); 803 adv76xx_inv_register(sd);
807 return ret; 804 return ret;
808 } 805 }
809 806
@@ -813,15 +810,15 @@ static int adv7604_g_register(struct v4l2_subdev *sd,
813 return 0; 810 return 0;
814} 811}
815 812
816static int adv7604_s_register(struct v4l2_subdev *sd, 813static int adv76xx_s_register(struct v4l2_subdev *sd,
817 const struct v4l2_dbg_register *reg) 814 const struct v4l2_dbg_register *reg)
818{ 815{
819 int ret; 816 int ret;
820 817
821 ret = adv7604_write_reg(sd, reg->reg, reg->val); 818 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
822 if (ret < 0) { 819 if (ret < 0) {
823 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 820 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
824 adv7604_inv_register(sd); 821 adv76xx_inv_register(sd);
825 return ret; 822 return ret;
826 } 823 }
827 824
@@ -846,10 +843,10 @@ static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
846 return value & 1; 843 return value & 1;
847} 844}
848 845
849static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 846static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
850{ 847{
851 struct adv7604_state *state = to_state(sd); 848 struct adv76xx_state *state = to_state(sd);
852 const struct adv7604_chip_info *info = state->info; 849 const struct adv76xx_chip_info *info = state->info;
853 850
854 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 851 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
855 info->read_cable_det(sd)); 852 info->read_cable_det(sd));
@@ -857,7 +854,7 @@ static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
857 854
858static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 855static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
859 u8 prim_mode, 856 u8 prim_mode,
860 const struct adv7604_video_standards *predef_vid_timings, 857 const struct adv76xx_video_standards *predef_vid_timings,
861 const struct v4l2_dv_timings *timings) 858 const struct v4l2_dv_timings *timings)
862{ 859{
863 int i; 860 int i;
@@ -878,12 +875,12 @@ static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
878static int configure_predefined_video_timings(struct v4l2_subdev *sd, 875static int configure_predefined_video_timings(struct v4l2_subdev *sd,
879 struct v4l2_dv_timings *timings) 876 struct v4l2_dv_timings *timings)
880{ 877{
881 struct adv7604_state *state = to_state(sd); 878 struct adv76xx_state *state = to_state(sd);
882 int err; 879 int err;
883 880
884 v4l2_dbg(1, debug, sd, "%s", __func__); 881 v4l2_dbg(1, debug, sd, "%s", __func__);
885 882
886 if (adv7604_has_afe(state)) { 883 if (adv76xx_has_afe(state)) {
887 /* reset to default values */ 884 /* reset to default values */
888 io_write(sd, 0x16, 0x43); 885 io_write(sd, 0x16, 0x43);
889 io_write(sd, 0x17, 0x5a); 886 io_write(sd, 0x17, 0x5a);
@@ -909,10 +906,10 @@ static int configure_predefined_video_timings(struct v4l2_subdev *sd,
909 0x02, adv7604_prim_mode_gr, timings); 906 0x02, adv7604_prim_mode_gr, timings);
910 } else if (is_digital_input(sd)) { 907 } else if (is_digital_input(sd)) {
911 err = find_and_set_predefined_video_timings(sd, 908 err = find_and_set_predefined_video_timings(sd,
912 0x05, adv7604_prim_mode_hdmi_comp, timings); 909 0x05, adv76xx_prim_mode_hdmi_comp, timings);
913 if (err) 910 if (err)
914 err = find_and_set_predefined_video_timings(sd, 911 err = find_and_set_predefined_video_timings(sd,
915 0x06, adv7604_prim_mode_hdmi_gr, timings); 912 0x06, adv76xx_prim_mode_hdmi_gr, timings);
916 } else { 913 } else {
917 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 914 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
918 __func__, state->selected_input); 915 __func__, state->selected_input);
@@ -926,7 +923,7 @@ static int configure_predefined_video_timings(struct v4l2_subdev *sd,
926static void configure_custom_video_timings(struct v4l2_subdev *sd, 923static void configure_custom_video_timings(struct v4l2_subdev *sd,
927 const struct v4l2_bt_timings *bt) 924 const struct v4l2_bt_timings *bt)
928{ 925{
929 struct adv7604_state *state = to_state(sd); 926 struct adv76xx_state *state = to_state(sd);
930 u32 width = htotal(bt); 927 u32 width = htotal(bt);
931 u32 height = vtotal(bt); 928 u32 height = vtotal(bt);
932 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 929 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
@@ -934,7 +931,7 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
934 u16 cp_start_vbi = height - bt->vfrontporch; 931 u16 cp_start_vbi = height - bt->vfrontporch;
935 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 932 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
936 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 933 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
937 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 934 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
938 const u8 pll[2] = { 935 const u8 pll[2] = {
939 0xc0 | ((width >> 8) & 0x1f), 936 0xc0 | ((width >> 8) & 0x1f),
940 width & 0xff 937 width & 0xff
@@ -952,7 +949,7 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
952 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 949 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
953 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 950 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
954 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 951 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
955 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO, 952 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO,
956 0x16, 2, pll)) 953 0x16, 2, pll))
957 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 954 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
958 955
@@ -983,9 +980,9 @@ static void configure_custom_video_timings(struct v4l2_subdev *sd,
983 cp_write(sd, 0xac, (height & 0x0f) << 4); 980 cp_write(sd, 0xac, (height & 0x0f) << 4);
984} 981}
985 982
986static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 983static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
987{ 984{
988 struct adv7604_state *state = to_state(sd); 985 struct adv76xx_state *state = to_state(sd);
989 u8 offset_buf[4]; 986 u8 offset_buf[4];
990 987
991 if (auto_offset) { 988 if (auto_offset) {
@@ -1004,14 +1001,14 @@ static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 off
1004 offset_buf[3] = offset_c & 0x0ff; 1001 offset_buf[3] = offset_c & 0x0ff;
1005 1002
1006 /* Registers must be written in this order with no i2c access in between */ 1003 /* Registers must be written in this order with no i2c access in between */
1007 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, 1004 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
1008 0x77, 4, offset_buf)) 1005 0x77, 4, offset_buf))
1009 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1006 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1010} 1007}
1011 1008
1012static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1009static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1013{ 1010{
1014 struct adv7604_state *state = to_state(sd); 1011 struct adv76xx_state *state = to_state(sd);
1015 u8 gain_buf[4]; 1012 u8 gain_buf[4];
1016 u8 gain_man = 1; 1013 u8 gain_man = 1;
1017 u8 agc_mode_man = 1; 1014 u8 agc_mode_man = 1;
@@ -1034,14 +1031,14 @@ static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a,
1034 gain_buf[3] = ((gain_c & 0x0ff)); 1031 gain_buf[3] = ((gain_c & 0x0ff));
1035 1032
1036 /* Registers must be written in this order with no i2c access in between */ 1033 /* Registers must be written in this order with no i2c access in between */
1037 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP, 1034 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
1038 0x73, 4, gain_buf)) 1035 0x73, 4, gain_buf))
1039 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1036 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1040} 1037}
1041 1038
1042static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1039static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1043{ 1040{
1044 struct adv7604_state *state = to_state(sd); 1041 struct adv76xx_state *state = to_state(sd);
1045 bool rgb_output = io_read(sd, 0x02) & 0x02; 1042 bool rgb_output = io_read(sd, 0x02) & 0x02;
1046 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1043 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1047 1044
@@ -1049,8 +1046,8 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1049 __func__, state->rgb_quantization_range, 1046 __func__, state->rgb_quantization_range,
1050 rgb_output, hdmi_signal); 1047 rgb_output, hdmi_signal);
1051 1048
1052 adv7604_set_gain(sd, true, 0x0, 0x0, 0x0); 1049 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1053 adv7604_set_offset(sd, true, 0x0, 0x0, 0x0); 1050 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1054 1051
1055 switch (state->rgb_quantization_range) { 1052 switch (state->rgb_quantization_range) {
1056 case V4L2_DV_RGB_RANGE_AUTO: 1053 case V4L2_DV_RGB_RANGE_AUTO:
@@ -1078,7 +1075,7 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1078 /* Receiving DVI-D signal 1075 /* Receiving DVI-D signal
1079 * ADV7604 selects RGB limited range regardless of 1076 * ADV7604 selects RGB limited range regardless of
1080 * input format (CE/IT) in automatic mode */ 1077 * input format (CE/IT) in automatic mode */
1081 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 1078 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1082 /* RGB limited range (16-235) */ 1079 /* RGB limited range (16-235) */
1083 io_write_clr_set(sd, 0x02, 0xf0, 0x00); 1080 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1084 } else { 1081 } else {
@@ -1086,10 +1083,10 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1086 io_write_clr_set(sd, 0x02, 0xf0, 0x10); 1083 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1087 1084
1088 if (is_digital_input(sd) && rgb_output) { 1085 if (is_digital_input(sd) && rgb_output) {
1089 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 1086 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1090 } else { 1087 } else {
1091 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1088 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1092 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 1089 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1093 } 1090 }
1094 } 1091 }
1095 break; 1092 break;
@@ -1119,21 +1116,21 @@ static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1119 1116
1120 /* Adjust gain/offset for DVI-D signals only */ 1117 /* Adjust gain/offset for DVI-D signals only */
1121 if (rgb_output) { 1118 if (rgb_output) {
1122 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 1119 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1123 } else { 1120 } else {
1124 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1121 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1125 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 1122 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1126 } 1123 }
1127 break; 1124 break;
1128 } 1125 }
1129} 1126}
1130 1127
1131static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) 1128static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1132{ 1129{
1133 struct v4l2_subdev *sd = 1130 struct v4l2_subdev *sd =
1134 &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; 1131 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1135 1132
1136 struct adv7604_state *state = to_state(sd); 1133 struct adv76xx_state *state = to_state(sd);
1137 1134
1138 switch (ctrl->id) { 1135 switch (ctrl->id) {
1139 case V4L2_CID_BRIGHTNESS: 1136 case V4L2_CID_BRIGHTNESS:
@@ -1153,7 +1150,7 @@ static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1153 set_rgb_quantization_range(sd); 1150 set_rgb_quantization_range(sd);
1154 return 0; 1151 return 0;
1155 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1152 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1156 if (!adv7604_has_afe(state)) 1153 if (!adv76xx_has_afe(state))
1157 return -EINVAL; 1154 return -EINVAL;
1158 /* Set the analog sampling phase. This is needed to find the 1155 /* Set the analog sampling phase. This is needed to find the
1159 best sampling phase for analog video: an application or 1156 best sampling phase for analog video: an application or
@@ -1185,15 +1182,15 @@ static inline bool no_power(struct v4l2_subdev *sd)
1185 1182
1186static inline bool no_signal_tmds(struct v4l2_subdev *sd) 1183static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1187{ 1184{
1188 struct adv7604_state *state = to_state(sd); 1185 struct adv76xx_state *state = to_state(sd);
1189 1186
1190 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1187 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1191} 1188}
1192 1189
1193static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1190static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1194{ 1191{
1195 struct adv7604_state *state = to_state(sd); 1192 struct adv76xx_state *state = to_state(sd);
1196 const struct adv7604_chip_info *info = state->info; 1193 const struct adv76xx_chip_info *info = state->info;
1197 1194
1198 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 1195 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1199} 1196}
@@ -1205,13 +1202,13 @@ static inline bool is_hdmi(struct v4l2_subdev *sd)
1205 1202
1206static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1203static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1207{ 1204{
1208 struct adv7604_state *state = to_state(sd); 1205 struct adv76xx_state *state = to_state(sd);
1209 1206
1210 /* 1207 /*
1211 * Chips without a AFE don't expose registers for the SSPD, so just assume 1208 * Chips without a AFE don't expose registers for the SSPD, so just assume
1212 * that we have a lock. 1209 * that we have a lock.
1213 */ 1210 */
1214 if (adv7604_has_afe(state)) 1211 if (adv76xx_has_afe(state))
1215 return false; 1212 return false;
1216 1213
1217 /* TODO channel 2 */ 1214 /* TODO channel 2 */
@@ -1243,9 +1240,9 @@ static inline bool no_signal(struct v4l2_subdev *sd)
1243 1240
1244static inline bool no_lock_cp(struct v4l2_subdev *sd) 1241static inline bool no_lock_cp(struct v4l2_subdev *sd)
1245{ 1242{
1246 struct adv7604_state *state = to_state(sd); 1243 struct adv76xx_state *state = to_state(sd);
1247 1244
1248 if (!adv7604_has_afe(state)) 1245 if (!adv76xx_has_afe(state))
1249 return false; 1246 return false;
1250 1247
1251 /* CP has detected a non standard number of lines on the incoming 1248 /* CP has detected a non standard number of lines on the incoming
@@ -1253,13 +1250,19 @@ static inline bool no_lock_cp(struct v4l2_subdev *sd)
1253 return io_read(sd, 0x12) & 0x01; 1250 return io_read(sd, 0x12) & 0x01;
1254} 1251}
1255 1252
1256static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) 1253static inline bool in_free_run(struct v4l2_subdev *sd)
1254{
1255 return cp_read(sd, 0xff) & 0x10;
1256}
1257
1258static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1257{ 1259{
1258 *status = 0; 1260 *status = 0;
1259 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1261 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1260 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1262 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1261 if (no_lock_cp(sd)) 1263 if (!in_free_run(sd) && no_lock_cp(sd))
1262 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 1264 *status |= is_digital_input(sd) ?
1265 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1263 1266
1264 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1267 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1265 1268
@@ -1278,22 +1281,22 @@ static int stdi2dv_timings(struct v4l2_subdev *sd,
1278 struct stdi_readback *stdi, 1281 struct stdi_readback *stdi,
1279 struct v4l2_dv_timings *timings) 1282 struct v4l2_dv_timings *timings)
1280{ 1283{
1281 struct adv7604_state *state = to_state(sd); 1284 struct adv76xx_state *state = to_state(sd);
1282 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; 1285 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1283 u32 pix_clk; 1286 u32 pix_clk;
1284 int i; 1287 int i;
1285 1288
1286 for (i = 0; adv7604_timings[i].bt.height; i++) { 1289 for (i = 0; adv76xx_timings[i].bt.height; i++) {
1287 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) 1290 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
1288 continue; 1291 continue;
1289 if (adv7604_timings[i].bt.vsync != stdi->lcvs) 1292 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
1290 continue; 1293 continue;
1291 1294
1292 pix_clk = hfreq * htotal(&adv7604_timings[i].bt); 1295 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
1293 1296
1294 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && 1297 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1295 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { 1298 (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1296 *timings = adv7604_timings[i]; 1299 *timings = adv76xx_timings[i];
1297 return 0; 1300 return 0;
1298 } 1301 }
1299 } 1302 }
@@ -1319,8 +1322,8 @@ static int stdi2dv_timings(struct v4l2_subdev *sd,
1319 1322
1320static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1323static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1321{ 1324{
1322 struct adv7604_state *state = to_state(sd); 1325 struct adv76xx_state *state = to_state(sd);
1323 const struct adv7604_chip_info *info = state->info; 1326 const struct adv76xx_chip_info *info = state->info;
1324 u8 polarity; 1327 u8 polarity;
1325 1328
1326 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1329 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
@@ -1334,7 +1337,7 @@ static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1334 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1337 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1335 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1338 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1336 1339
1337 if (adv7604_has_afe(state)) { 1340 if (adv76xx_has_afe(state)) {
1338 /* read SSPD */ 1341 /* read SSPD */
1339 polarity = cp_read(sd, 0xb5); 1342 polarity = cp_read(sd, 0xb5);
1340 if ((polarity & 0x03) == 0x01) { 1343 if ((polarity & 0x03) == 0x01) {
@@ -1373,26 +1376,26 @@ static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1373 return 0; 1376 return 0;
1374} 1377}
1375 1378
1376static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, 1379static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1377 struct v4l2_enum_dv_timings *timings) 1380 struct v4l2_enum_dv_timings *timings)
1378{ 1381{
1379 struct adv7604_state *state = to_state(sd); 1382 struct adv76xx_state *state = to_state(sd);
1380 1383
1381 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) 1384 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
1382 return -EINVAL; 1385 return -EINVAL;
1383 1386
1384 if (timings->pad >= state->source_pad) 1387 if (timings->pad >= state->source_pad)
1385 return -EINVAL; 1388 return -EINVAL;
1386 1389
1387 memset(timings->reserved, 0, sizeof(timings->reserved)); 1390 memset(timings->reserved, 0, sizeof(timings->reserved));
1388 timings->timings = adv7604_timings[timings->index]; 1391 timings->timings = adv76xx_timings[timings->index];
1389 return 0; 1392 return 0;
1390} 1393}
1391 1394
1392static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, 1395static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1393 struct v4l2_dv_timings_cap *cap) 1396 struct v4l2_dv_timings_cap *cap)
1394{ 1397{
1395 struct adv7604_state *state = to_state(sd); 1398 struct adv76xx_state *state = to_state(sd);
1396 1399
1397 if (cap->pad >= state->source_pad) 1400 if (cap->pad >= state->source_pad)
1398 return -EINVAL; 1401 return -EINVAL;
@@ -1403,7 +1406,7 @@ static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1403 cap->bt.min_pixelclock = 25000000; 1406 cap->bt.min_pixelclock = 25000000;
1404 1407
1405 switch (cap->pad) { 1408 switch (cap->pad) {
1406 case ADV7604_PAD_HDMI_PORT_A: 1409 case ADV76XX_PAD_HDMI_PORT_A:
1407 case ADV7604_PAD_HDMI_PORT_B: 1410 case ADV7604_PAD_HDMI_PORT_B:
1408 case ADV7604_PAD_HDMI_PORT_C: 1411 case ADV7604_PAD_HDMI_PORT_C:
1409 case ADV7604_PAD_HDMI_PORT_D: 1412 case ADV7604_PAD_HDMI_PORT_D:
@@ -1424,16 +1427,16 @@ static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1424} 1427}
1425 1428
1426/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1429/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1427 if the format is listed in adv7604_timings[] */ 1430 if the format is listed in adv76xx_timings[] */
1428static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1431static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1429 struct v4l2_dv_timings *timings) 1432 struct v4l2_dv_timings *timings)
1430{ 1433{
1431 int i; 1434 int i;
1432 1435
1433 for (i = 0; adv7604_timings[i].bt.width; i++) { 1436 for (i = 0; adv76xx_timings[i].bt.width; i++) {
1434 if (v4l2_match_dv_timings(timings, &adv7604_timings[i], 1437 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
1435 is_digital_input(sd) ? 250000 : 1000000)) { 1438 is_digital_input(sd) ? 250000 : 1000000)) {
1436 *timings = adv7604_timings[i]; 1439 *timings = adv76xx_timings[i];
1437 break; 1440 break;
1438 } 1441 }
1439 } 1442 }
@@ -1471,11 +1474,11 @@ static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1471 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1474 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1472} 1475}
1473 1476
1474static int adv7604_query_dv_timings(struct v4l2_subdev *sd, 1477static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1475 struct v4l2_dv_timings *timings) 1478 struct v4l2_dv_timings *timings)
1476{ 1479{
1477 struct adv7604_state *state = to_state(sd); 1480 struct adv76xx_state *state = to_state(sd);
1478 const struct adv7604_chip_info *info = state->info; 1481 const struct adv76xx_chip_info *info = state->info;
1479 struct v4l2_bt_timings *bt = &timings->bt; 1482 struct v4l2_bt_timings *bt = &timings->bt;
1480 struct stdi_readback stdi; 1483 struct stdi_readback stdi;
1481 1484
@@ -1519,7 +1522,7 @@ static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1519 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2; 1522 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
1520 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2; 1523 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
1521 } 1524 }
1522 adv7604_fill_optional_dv_timings_fields(sd, timings); 1525 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1523 } else { 1526 } else {
1524 /* find format 1527 /* find format
1525 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1528 * Since LCVS values are inaccurate [REF_03, p. 275-276],
@@ -1576,16 +1579,16 @@ found:
1576 } 1579 }
1577 1580
1578 if (debug > 1) 1581 if (debug > 1)
1579 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", 1582 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1580 timings, true); 1583 timings, true);
1581 1584
1582 return 0; 1585 return 0;
1583} 1586}
1584 1587
1585static int adv7604_s_dv_timings(struct v4l2_subdev *sd, 1588static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1586 struct v4l2_dv_timings *timings) 1589 struct v4l2_dv_timings *timings)
1587{ 1590{
1588 struct adv7604_state *state = to_state(sd); 1591 struct adv76xx_state *state = to_state(sd);
1589 struct v4l2_bt_timings *bt; 1592 struct v4l2_bt_timings *bt;
1590 int err; 1593 int err;
1591 1594
@@ -1606,7 +1609,7 @@ static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1606 return -ERANGE; 1609 return -ERANGE;
1607 } 1610 }
1608 1611
1609 adv7604_fill_optional_dv_timings_fields(sd, timings); 1612 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1610 1613
1611 state->timings = *timings; 1614 state->timings = *timings;
1612 1615
@@ -1623,15 +1626,15 @@ static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1623 set_rgb_quantization_range(sd); 1626 set_rgb_quantization_range(sd);
1624 1627
1625 if (debug > 1) 1628 if (debug > 1)
1626 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", 1629 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1627 timings, true); 1630 timings, true);
1628 return 0; 1631 return 0;
1629} 1632}
1630 1633
1631static int adv7604_g_dv_timings(struct v4l2_subdev *sd, 1634static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1632 struct v4l2_dv_timings *timings) 1635 struct v4l2_dv_timings *timings)
1633{ 1636{
1634 struct adv7604_state *state = to_state(sd); 1637 struct adv76xx_state *state = to_state(sd);
1635 1638
1636 *timings = state->timings; 1639 *timings = state->timings;
1637 return 0; 1640 return 0;
@@ -1649,7 +1652,7 @@ static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1649 1652
1650static void enable_input(struct v4l2_subdev *sd) 1653static void enable_input(struct v4l2_subdev *sd)
1651{ 1654{
1652 struct adv7604_state *state = to_state(sd); 1655 struct adv76xx_state *state = to_state(sd);
1653 1656
1654 if (is_analog_input(sd)) { 1657 if (is_analog_input(sd)) {
1655 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1658 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
@@ -1666,7 +1669,7 @@ static void enable_input(struct v4l2_subdev *sd)
1666 1669
1667static void disable_input(struct v4l2_subdev *sd) 1670static void disable_input(struct v4l2_subdev *sd)
1668{ 1671{
1669 struct adv7604_state *state = to_state(sd); 1672 struct adv76xx_state *state = to_state(sd);
1670 1673
1671 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ 1674 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1672 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 1675 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
@@ -1676,11 +1679,11 @@ static void disable_input(struct v4l2_subdev *sd)
1676 1679
1677static void select_input(struct v4l2_subdev *sd) 1680static void select_input(struct v4l2_subdev *sd)
1678{ 1681{
1679 struct adv7604_state *state = to_state(sd); 1682 struct adv76xx_state *state = to_state(sd);
1680 const struct adv7604_chip_info *info = state->info; 1683 const struct adv76xx_chip_info *info = state->info;
1681 1684
1682 if (is_analog_input(sd)) { 1685 if (is_analog_input(sd)) {
1683 adv7604_write_reg_seq(sd, info->recommended_settings[0]); 1686 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1684 1687
1685 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1688 afe_write(sd, 0x00, 0x08); /* power up ADC */
1686 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1689 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
@@ -1688,9 +1691,9 @@ static void select_input(struct v4l2_subdev *sd)
1688 } else if (is_digital_input(sd)) { 1691 } else if (is_digital_input(sd)) {
1689 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1692 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1690 1693
1691 adv7604_write_reg_seq(sd, info->recommended_settings[1]); 1694 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1692 1695
1693 if (adv7604_has_afe(state)) { 1696 if (adv76xx_has_afe(state)) {
1694 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1697 afe_write(sd, 0x00, 0xff); /* power down ADC */
1695 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1698 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1696 afe_write(sd, 0xc8, 0x40); /* phase control */ 1699 afe_write(sd, 0xc8, 0x40); /* phase control */
@@ -1705,10 +1708,10 @@ static void select_input(struct v4l2_subdev *sd)
1705 } 1708 }
1706} 1709}
1707 1710
1708static int adv7604_s_routing(struct v4l2_subdev *sd, 1711static int adv76xx_s_routing(struct v4l2_subdev *sd,
1709 u32 input, u32 output, u32 config) 1712 u32 input, u32 output, u32 config)
1710{ 1713{
1711 struct adv7604_state *state = to_state(sd); 1714 struct adv76xx_state *state = to_state(sd);
1712 1715
1713 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1716 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1714 __func__, input, state->selected_input); 1717 __func__, input, state->selected_input);
@@ -1730,11 +1733,11 @@ static int adv7604_s_routing(struct v4l2_subdev *sd,
1730 return 0; 1733 return 0;
1731} 1734}
1732 1735
1733static int adv7604_enum_mbus_code(struct v4l2_subdev *sd, 1736static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1734 struct v4l2_subdev_fh *fh, 1737 struct v4l2_subdev_pad_config *cfg,
1735 struct v4l2_subdev_mbus_code_enum *code) 1738 struct v4l2_subdev_mbus_code_enum *code)
1736{ 1739{
1737 struct adv7604_state *state = to_state(sd); 1740 struct adv76xx_state *state = to_state(sd);
1738 1741
1739 if (code->index >= state->info->nformats) 1742 if (code->index >= state->info->nformats)
1740 return -EINVAL; 1743 return -EINVAL;
@@ -1744,7 +1747,7 @@ static int adv7604_enum_mbus_code(struct v4l2_subdev *sd,
1744 return 0; 1747 return 0;
1745} 1748}
1746 1749
1747static void adv7604_fill_format(struct adv7604_state *state, 1750static void adv76xx_fill_format(struct adv76xx_state *state,
1748 struct v4l2_mbus_framefmt *format) 1751 struct v4l2_mbus_framefmt *format)
1749{ 1752{
1750 memset(format, 0, sizeof(*format)); 1753 memset(format, 0, sizeof(*format));
@@ -1752,8 +1755,9 @@ static void adv7604_fill_format(struct adv7604_state *state,
1752 format->width = state->timings.bt.width; 1755 format->width = state->timings.bt.width;
1753 format->height = state->timings.bt.height; 1756 format->height = state->timings.bt.height;
1754 format->field = V4L2_FIELD_NONE; 1757 format->field = V4L2_FIELD_NONE;
1758 format->colorspace = V4L2_COLORSPACE_SRGB;
1755 1759
1756 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) 1760 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1757 format->colorspace = (state->timings.bt.height <= 576) ? 1761 format->colorspace = (state->timings.bt.height <= 576) ?
1758 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1762 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1759} 1763}
@@ -1765,7 +1769,7 @@ static void adv7604_fill_format(struct adv7604_state *state,
1765 * 1769 *
1766 * The following table gives the op_ch_value from the format component order 1770 * The following table gives the op_ch_value from the format component order
1767 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as 1771 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1768 * adv7604_bus_order value in row). 1772 * adv76xx_bus_order value in row).
1769 * 1773 *
1770 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5) 1774 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1771 * ----------+------------------------------------------------- 1775 * ----------+-------------------------------------------------
@@ -1776,11 +1780,11 @@ static void adv7604_fill_format(struct adv7604_state *state,
1776 * BRG (ROR) | BRG RBG GRB GBR RGB BGR 1780 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1777 * GBR (ROL) | RGB BGR RBG BRG GBR GRB 1781 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1778 */ 1782 */
1779static unsigned int adv7604_op_ch_sel(struct adv7604_state *state) 1783static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1780{ 1784{
1781#define _SEL(a,b,c,d,e,f) { \ 1785#define _SEL(a,b,c,d,e,f) { \
1782 ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \ 1786 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1783 ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f } 1787 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1784#define _BUS(x) [ADV7604_BUS_ORDER_##x] 1788#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1785 1789
1786 static const unsigned int op_ch_sel[6][6] = { 1790 static const unsigned int op_ch_sel[6][6] = {
@@ -1795,33 +1799,34 @@ static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
1795 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; 1799 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1796} 1800}
1797 1801
1798static void adv7604_setup_format(struct adv7604_state *state) 1802static void adv76xx_setup_format(struct adv76xx_state *state)
1799{ 1803{
1800 struct v4l2_subdev *sd = &state->sd; 1804 struct v4l2_subdev *sd = &state->sd;
1801 1805
1802 io_write_clr_set(sd, 0x02, 0x02, 1806 io_write_clr_set(sd, 0x02, 0x02,
1803 state->format->rgb_out ? ADV7604_RGB_OUT : 0); 1807 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1804 io_write(sd, 0x03, state->format->op_format_sel | 1808 io_write(sd, 0x03, state->format->op_format_sel |
1805 state->pdata.op_format_mode_sel); 1809 state->pdata.op_format_mode_sel);
1806 io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state)); 1810 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1807 io_write_clr_set(sd, 0x05, 0x01, 1811 io_write_clr_set(sd, 0x05, 0x01,
1808 state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0); 1812 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1809} 1813}
1810 1814
1811static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 1815static int adv76xx_get_format(struct v4l2_subdev *sd,
1816 struct v4l2_subdev_pad_config *cfg,
1812 struct v4l2_subdev_format *format) 1817 struct v4l2_subdev_format *format)
1813{ 1818{
1814 struct adv7604_state *state = to_state(sd); 1819 struct adv76xx_state *state = to_state(sd);
1815 1820
1816 if (format->pad != state->source_pad) 1821 if (format->pad != state->source_pad)
1817 return -EINVAL; 1822 return -EINVAL;
1818 1823
1819 adv7604_fill_format(state, &format->format); 1824 adv76xx_fill_format(state, &format->format);
1820 1825
1821 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1826 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1822 struct v4l2_mbus_framefmt *fmt; 1827 struct v4l2_mbus_framefmt *fmt;
1823 1828
1824 fmt = v4l2_subdev_get_try_format(fh, format->pad); 1829 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1825 format->format.code = fmt->code; 1830 format->format.code = fmt->code;
1826 } else { 1831 } else {
1827 format->format.code = state->format->code; 1832 format->format.code = state->format->code;
@@ -1830,39 +1835,40 @@ static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1830 return 0; 1835 return 0;
1831} 1836}
1832 1837
1833static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, 1838static int adv76xx_set_format(struct v4l2_subdev *sd,
1839 struct v4l2_subdev_pad_config *cfg,
1834 struct v4l2_subdev_format *format) 1840 struct v4l2_subdev_format *format)
1835{ 1841{
1836 struct adv7604_state *state = to_state(sd); 1842 struct adv76xx_state *state = to_state(sd);
1837 const struct adv7604_format_info *info; 1843 const struct adv76xx_format_info *info;
1838 1844
1839 if (format->pad != state->source_pad) 1845 if (format->pad != state->source_pad)
1840 return -EINVAL; 1846 return -EINVAL;
1841 1847
1842 info = adv7604_format_info(state, format->format.code); 1848 info = adv76xx_format_info(state, format->format.code);
1843 if (info == NULL) 1849 if (info == NULL)
1844 info = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 1850 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1845 1851
1846 adv7604_fill_format(state, &format->format); 1852 adv76xx_fill_format(state, &format->format);
1847 format->format.code = info->code; 1853 format->format.code = info->code;
1848 1854
1849 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 1855 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1850 struct v4l2_mbus_framefmt *fmt; 1856 struct v4l2_mbus_framefmt *fmt;
1851 1857
1852 fmt = v4l2_subdev_get_try_format(fh, format->pad); 1858 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1853 fmt->code = format->format.code; 1859 fmt->code = format->format.code;
1854 } else { 1860 } else {
1855 state->format = info; 1861 state->format = info;
1856 adv7604_setup_format(state); 1862 adv76xx_setup_format(state);
1857 } 1863 }
1858 1864
1859 return 0; 1865 return 0;
1860} 1866}
1861 1867
1862static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1868static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1863{ 1869{
1864 struct adv7604_state *state = to_state(sd); 1870 struct adv76xx_state *state = to_state(sd);
1865 const struct adv7604_chip_info *info = state->info; 1871 const struct adv76xx_chip_info *info = state->info;
1866 const u8 irq_reg_0x43 = io_read(sd, 0x43); 1872 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1867 const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1873 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1868 const u8 irq_reg_0x70 = io_read(sd, 0x70); 1874 const u8 irq_reg_0x70 = io_read(sd, 0x70);
@@ -1890,7 +1896,7 @@ static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1890 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 1896 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1891 __func__, fmt_change, fmt_change_digital); 1897 __func__, fmt_change, fmt_change_digital);
1892 1898
1893 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); 1899 v4l2_subdev_notify(sd, ADV76XX_FMT_CHANGE, NULL);
1894 1900
1895 if (handled) 1901 if (handled)
1896 *handled = true; 1902 *handled = true;
@@ -1909,22 +1915,22 @@ static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1909 if (tx_5v) { 1915 if (tx_5v) {
1910 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 1916 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1911 io_write(sd, 0x71, tx_5v); 1917 io_write(sd, 0x71, tx_5v);
1912 adv7604_s_detect_tx_5v_ctrl(sd); 1918 adv76xx_s_detect_tx_5v_ctrl(sd);
1913 if (handled) 1919 if (handled)
1914 *handled = true; 1920 *handled = true;
1915 } 1921 }
1916 return 0; 1922 return 0;
1917} 1923}
1918 1924
1919static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 1925static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1920{ 1926{
1921 struct adv7604_state *state = to_state(sd); 1927 struct adv76xx_state *state = to_state(sd);
1922 u8 *data = NULL; 1928 u8 *data = NULL;
1923 1929
1924 memset(edid->reserved, 0, sizeof(edid->reserved)); 1930 memset(edid->reserved, 0, sizeof(edid->reserved));
1925 1931
1926 switch (edid->pad) { 1932 switch (edid->pad) {
1927 case ADV7604_PAD_HDMI_PORT_A: 1933 case ADV76XX_PAD_HDMI_PORT_A:
1928 case ADV7604_PAD_HDMI_PORT_B: 1934 case ADV7604_PAD_HDMI_PORT_B:
1929 case ADV7604_PAD_HDMI_PORT_C: 1935 case ADV7604_PAD_HDMI_PORT_C:
1930 case ADV7604_PAD_HDMI_PORT_D: 1936 case ADV7604_PAD_HDMI_PORT_D:
@@ -1982,10 +1988,10 @@ static int get_edid_spa_location(const u8 *edid)
1982 return -1; 1988 return -1;
1983} 1989}
1984 1990
1985static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 1991static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1986{ 1992{
1987 struct adv7604_state *state = to_state(sd); 1993 struct adv76xx_state *state = to_state(sd);
1988 const struct adv7604_chip_info *info = state->info; 1994 const struct adv76xx_chip_info *info = state->info;
1989 int spa_loc; 1995 int spa_loc;
1990 int err; 1996 int err;
1991 int i; 1997 int i;
@@ -1999,7 +2005,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1999 if (edid->blocks == 0) { 2005 if (edid->blocks == 0) {
2000 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2006 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2001 state->edid.present &= ~(1 << edid->pad); 2007 state->edid.present &= ~(1 << edid->pad);
2002 adv7604_set_hpd(state, state->edid.present); 2008 adv76xx_set_hpd(state, state->edid.present);
2003 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2009 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2004 2010
2005 /* Fall back to a 16:9 aspect ratio */ 2011 /* Fall back to a 16:9 aspect ratio */
@@ -2023,7 +2029,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2023 2029
2024 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 2030 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2025 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 2031 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2026 adv7604_set_hpd(state, 0); 2032 adv76xx_set_hpd(state, 0);
2027 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); 2033 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2028 2034
2029 spa_loc = get_edid_spa_location(edid->edid); 2035 spa_loc = get_edid_spa_location(edid->edid);
@@ -2031,7 +2037,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2031 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 2037 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2032 2038
2033 switch (edid->pad) { 2039 switch (edid->pad) {
2034 case ADV7604_PAD_HDMI_PORT_A: 2040 case ADV76XX_PAD_HDMI_PORT_A:
2035 state->spa_port_a[0] = edid->edid[spa_loc]; 2041 state->spa_port_a[0] = edid->edid[spa_loc];
2036 state->spa_port_a[1] = edid->edid[spa_loc + 1]; 2042 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2037 break; 2043 break;
@@ -2074,7 +2080,7 @@ static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2074 return err; 2080 return err;
2075 } 2081 }
2076 2082
2077 /* adv7604 calculates the checksums and enables I2C access to internal 2083 /* adv76xx calculates the checksums and enables I2C access to internal
2078 EDID RAM from DDC port. */ 2084 EDID RAM from DDC port. */
2079 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); 2085 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2080 2086
@@ -2138,10 +2144,10 @@ static void print_avi_infoframe(struct v4l2_subdev *sd)
2138 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 2144 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2139} 2145}
2140 2146
2141static int adv7604_log_status(struct v4l2_subdev *sd) 2147static int adv76xx_log_status(struct v4l2_subdev *sd)
2142{ 2148{
2143 struct adv7604_state *state = to_state(sd); 2149 struct adv76xx_state *state = to_state(sd);
2144 const struct adv7604_chip_info *info = state->info; 2150 const struct adv76xx_chip_info *info = state->info;
2145 struct v4l2_dv_timings timings; 2151 struct v4l2_dv_timings timings;
2146 struct stdi_readback stdi; 2152 struct stdi_readback stdi;
2147 u8 reg_io_0x02 = io_read(sd, 0x02); 2153 u8 reg_io_0x02 = io_read(sd, 0x02);
@@ -2200,7 +2206,7 @@ static int adv7604_log_status(struct v4l2_subdev *sd)
2200 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 2206 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2201 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 2207 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2202 v4l2_info(sd, "CP free run: %s\n", 2208 v4l2_info(sd, "CP free run: %s\n",
2203 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2209 (in_free_run(sd)) ? "on" : "off");
2204 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2210 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2205 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2211 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2206 (io_read(sd, 0x01) & 0x70) >> 4); 2212 (io_read(sd, 0x01) & 0x70) >> 4);
@@ -2213,7 +2219,7 @@ static int adv7604_log_status(struct v4l2_subdev *sd)
2213 stdi.lcf, stdi.bl, stdi.lcvs, 2219 stdi.lcf, stdi.bl, stdi.lcvs,
2214 stdi.interlaced ? "interlaced" : "progressive", 2220 stdi.interlaced ? "interlaced" : "progressive",
2215 stdi.hs_pol, stdi.vs_pol); 2221 stdi.hs_pol, stdi.vs_pol);
2216 if (adv7604_query_dv_timings(sd, &timings)) 2222 if (adv76xx_query_dv_timings(sd, &timings))
2217 v4l2_info(sd, "No video detected\n"); 2223 v4l2_info(sd, "No video detected\n");
2218 else 2224 else
2219 v4l2_print_dv_timings(sd->name, "Detected format: ", 2225 v4l2_print_dv_timings(sd->name, "Detected format: ",
@@ -2235,7 +2241,7 @@ static int adv7604_log_status(struct v4l2_subdev *sd)
2235 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 2241 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2236 "enabled" : "disabled"); 2242 "enabled" : "disabled");
2237 v4l2_info(sd, "Color space conversion: %s\n", 2243 v4l2_info(sd, "Color space conversion: %s\n",
2238 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); 2244 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2239 2245
2240 if (!is_digital_input(sd)) 2246 if (!is_digital_input(sd))
2241 return 0; 2247 return 0;
@@ -2279,47 +2285,47 @@ static int adv7604_log_status(struct v4l2_subdev *sd)
2279 2285
2280/* ----------------------------------------------------------------------- */ 2286/* ----------------------------------------------------------------------- */
2281 2287
2282static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { 2288static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2283 .s_ctrl = adv7604_s_ctrl, 2289 .s_ctrl = adv76xx_s_ctrl,
2284}; 2290};
2285 2291
2286static const struct v4l2_subdev_core_ops adv7604_core_ops = { 2292static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2287 .log_status = adv7604_log_status, 2293 .log_status = adv76xx_log_status,
2288 .interrupt_service_routine = adv7604_isr, 2294 .interrupt_service_routine = adv76xx_isr,
2289#ifdef CONFIG_VIDEO_ADV_DEBUG 2295#ifdef CONFIG_VIDEO_ADV_DEBUG
2290 .g_register = adv7604_g_register, 2296 .g_register = adv76xx_g_register,
2291 .s_register = adv7604_s_register, 2297 .s_register = adv76xx_s_register,
2292#endif 2298#endif
2293}; 2299};
2294 2300
2295static const struct v4l2_subdev_video_ops adv7604_video_ops = { 2301static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2296 .s_routing = adv7604_s_routing, 2302 .s_routing = adv76xx_s_routing,
2297 .g_input_status = adv7604_g_input_status, 2303 .g_input_status = adv76xx_g_input_status,
2298 .s_dv_timings = adv7604_s_dv_timings, 2304 .s_dv_timings = adv76xx_s_dv_timings,
2299 .g_dv_timings = adv7604_g_dv_timings, 2305 .g_dv_timings = adv76xx_g_dv_timings,
2300 .query_dv_timings = adv7604_query_dv_timings, 2306 .query_dv_timings = adv76xx_query_dv_timings,
2301}; 2307};
2302 2308
2303static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { 2309static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2304 .enum_mbus_code = adv7604_enum_mbus_code, 2310 .enum_mbus_code = adv76xx_enum_mbus_code,
2305 .get_fmt = adv7604_get_format, 2311 .get_fmt = adv76xx_get_format,
2306 .set_fmt = adv7604_set_format, 2312 .set_fmt = adv76xx_set_format,
2307 .get_edid = adv7604_get_edid, 2313 .get_edid = adv76xx_get_edid,
2308 .set_edid = adv7604_set_edid, 2314 .set_edid = adv76xx_set_edid,
2309 .dv_timings_cap = adv7604_dv_timings_cap, 2315 .dv_timings_cap = adv76xx_dv_timings_cap,
2310 .enum_dv_timings = adv7604_enum_dv_timings, 2316 .enum_dv_timings = adv76xx_enum_dv_timings,
2311}; 2317};
2312 2318
2313static const struct v4l2_subdev_ops adv7604_ops = { 2319static const struct v4l2_subdev_ops adv76xx_ops = {
2314 .core = &adv7604_core_ops, 2320 .core = &adv76xx_core_ops,
2315 .video = &adv7604_video_ops, 2321 .video = &adv76xx_video_ops,
2316 .pad = &adv7604_pad_ops, 2322 .pad = &adv76xx_pad_ops,
2317}; 2323};
2318 2324
2319/* -------------------------- custom ctrls ---------------------------------- */ 2325/* -------------------------- custom ctrls ---------------------------------- */
2320 2326
2321static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2327static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2322 .ops = &adv7604_ctrl_ops, 2328 .ops = &adv76xx_ctrl_ops,
2323 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2329 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2324 .name = "Analog Sampling Phase", 2330 .name = "Analog Sampling Phase",
2325 .type = V4L2_CTRL_TYPE_INTEGER, 2331 .type = V4L2_CTRL_TYPE_INTEGER,
@@ -2329,8 +2335,8 @@ static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2329 .def = 0, 2335 .def = 0,
2330}; 2336};
2331 2337
2332static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { 2338static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2333 .ops = &adv7604_ctrl_ops, 2339 .ops = &adv76xx_ctrl_ops,
2334 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2340 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2335 .name = "Free Running Color, Manual", 2341 .name = "Free Running Color, Manual",
2336 .type = V4L2_CTRL_TYPE_BOOLEAN, 2342 .type = V4L2_CTRL_TYPE_BOOLEAN,
@@ -2340,8 +2346,8 @@ static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2340 .def = false, 2346 .def = false,
2341}; 2347};
2342 2348
2343static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { 2349static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2344 .ops = &adv7604_ctrl_ops, 2350 .ops = &adv76xx_ctrl_ops,
2345 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2351 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2346 .name = "Free Running Color", 2352 .name = "Free Running Color",
2347 .type = V4L2_CTRL_TYPE_INTEGER, 2353 .type = V4L2_CTRL_TYPE_INTEGER,
@@ -2353,11 +2359,11 @@ static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2353 2359
2354/* ----------------------------------------------------------------------- */ 2360/* ----------------------------------------------------------------------- */
2355 2361
2356static int adv7604_core_init(struct v4l2_subdev *sd) 2362static int adv76xx_core_init(struct v4l2_subdev *sd)
2357{ 2363{
2358 struct adv7604_state *state = to_state(sd); 2364 struct adv76xx_state *state = to_state(sd);
2359 const struct adv7604_chip_info *info = state->info; 2365 const struct adv76xx_chip_info *info = state->info;
2360 struct adv7604_platform_data *pdata = &state->pdata; 2366 struct adv76xx_platform_data *pdata = &state->pdata;
2361 2367
2362 hdmi_write(sd, 0x48, 2368 hdmi_write(sd, 0x48,
2363 (pdata->disable_pwrdnb ? 0x80 : 0) | 2369 (pdata->disable_pwrdnb ? 0x80 : 0) |
@@ -2385,7 +2391,7 @@ static int adv7604_core_init(struct v4l2_subdev *sd)
2385 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | 2391 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2386 pdata->insert_av_codes << 2 | 2392 pdata->insert_av_codes << 2 |
2387 pdata->replicate_av_codes << 1); 2393 pdata->replicate_av_codes << 1);
2388 adv7604_setup_format(state); 2394 adv76xx_setup_format(state);
2389 2395
2390 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 2396 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2391 2397
@@ -2415,7 +2421,7 @@ static int adv7604_core_init(struct v4l2_subdev *sd)
2415 /* TODO from platform data */ 2421 /* TODO from platform data */
2416 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2422 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2417 2423
2418 if (adv7604_has_afe(state)) { 2424 if (adv76xx_has_afe(state)) {
2419 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2425 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2420 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); 2426 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2421 } 2427 }
@@ -2440,7 +2446,7 @@ static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2440 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2446 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2441} 2447}
2442 2448
2443static void adv7604_unregister_clients(struct adv7604_state *state) 2449static void adv76xx_unregister_clients(struct adv76xx_state *state)
2444{ 2450{
2445 unsigned int i; 2451 unsigned int i;
2446 2452
@@ -2450,7 +2456,7 @@ static void adv7604_unregister_clients(struct adv7604_state *state)
2450 } 2456 }
2451} 2457}
2452 2458
2453static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, 2459static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2454 u8 addr, u8 io_reg) 2460 u8 addr, u8 io_reg)
2455{ 2461{
2456 struct i2c_client *client = v4l2_get_subdevdata(sd); 2462 struct i2c_client *client = v4l2_get_subdevdata(sd);
@@ -2460,74 +2466,74 @@ static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2460 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 2466 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2461} 2467}
2462 2468
2463static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = { 2469static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2464 /* reset ADI recommended settings for HDMI: */ 2470 /* reset ADI recommended settings for HDMI: */
2465 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2471 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2466 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2472 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2467 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2473 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2468 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2474 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2469 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2475 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2470 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2476 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2471 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2477 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2472 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2478 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2473 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2479 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2474 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2480 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2475 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2481 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2476 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2482 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2477 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2483 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2478 2484
2479 /* set ADI recommended settings for digitizer */ 2485 /* set ADI recommended settings for digitizer */
2480 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2486 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2481 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2487 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2482 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2488 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2483 { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2489 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2484 { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2490 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2485 { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2491 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2486 2492
2487 { ADV7604_REG_SEQ_TERM, 0 }, 2493 { ADV76XX_REG_SEQ_TERM, 0 },
2488}; 2494};
2489 2495
2490static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = { 2496static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2491 /* set ADI recommended settings for HDMI: */ 2497 /* set ADI recommended settings for HDMI: */
2492 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2498 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2493 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2499 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2494 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2500 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2495 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2501 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2496 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2502 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2497 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2503 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2498 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2504 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2499 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2505 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2500 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2506 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2501 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2507 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2502 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2508 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2503 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2509 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2504 2510
2505 /* reset ADI recommended settings for digitizer */ 2511 /* reset ADI recommended settings for digitizer */
2506 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2512 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2507 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2513 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2508 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2514 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2509 2515
2510 { ADV7604_REG_SEQ_TERM, 0 }, 2516 { ADV76XX_REG_SEQ_TERM, 0 },
2511}; 2517};
2512 2518
2513static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = { 2519static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2514 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */ 2520 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2515 { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 }, 2521 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2516 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x9b), 0x03 }, 2522 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2517 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x08 }, 2523 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2518 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x85), 0x1f }, 2524 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2519 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 }, 2525 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2520 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda }, 2526 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2521 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 }, 2527 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2522 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 }, 2528 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2523 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 }, 2529 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2524 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 }, 2530 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2525 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e }, 2531 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2526 2532
2527 { ADV7604_REG_SEQ_TERM, 0 }, 2533 { ADV76XX_REG_SEQ_TERM, 0 },
2528}; 2534};
2529 2535
2530static const struct adv7604_chip_info adv7604_chip_info[] = { 2536static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2531 [ADV7604] = { 2537 [ADV7604] = {
2532 .type = ADV7604, 2538 .type = ADV7604,
2533 .has_afe = true, 2539 .has_afe = true,
@@ -2539,6 +2545,7 @@ static const struct adv7604_chip_info adv7604_chip_info[] = {
2539 .tdms_lock_mask = 0xe0, 2545 .tdms_lock_mask = 0xe0,
2540 .cable_det_mask = 0x1e, 2546 .cable_det_mask = 0x1e,
2541 .fmt_change_digital_mask = 0xc1, 2547 .fmt_change_digital_mask = 0xc1,
2548 .cp_csc = 0xfc,
2542 .formats = adv7604_formats, 2549 .formats = adv7604_formats,
2543 .nformats = ARRAY_SIZE(adv7604_formats), 2550 .nformats = ARRAY_SIZE(adv7604_formats),
2544 .set_termination = adv7604_set_termination, 2551 .set_termination = adv7604_set_termination,
@@ -2553,18 +2560,18 @@ static const struct adv7604_chip_info adv7604_chip_info[] = {
2553 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2560 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2554 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2561 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2555 }, 2562 },
2556 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2563 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2557 BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) | 2564 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2558 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2565 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2559 BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) | 2566 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2560 BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) | 2567 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2561 BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) | 2568 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2562 BIT(ADV7604_PAGE_VDP), 2569 BIT(ADV7604_PAGE_VDP),
2563 }, 2570 },
2564 [ADV7611] = { 2571 [ADV7611] = {
2565 .type = ADV7611, 2572 .type = ADV7611,
2566 .has_afe = false, 2573 .has_afe = false,
2567 .max_port = ADV7604_PAD_HDMI_PORT_A, 2574 .max_port = ADV76XX_PAD_HDMI_PORT_A,
2568 .num_dv_ports = 1, 2575 .num_dv_ports = 1,
2569 .edid_enable_reg = 0x74, 2576 .edid_enable_reg = 0x74,
2570 .edid_status_reg = 0x76, 2577 .edid_status_reg = 0x76,
@@ -2572,6 +2579,7 @@ static const struct adv7604_chip_info adv7604_chip_info[] = {
2572 .tdms_lock_mask = 0x43, 2579 .tdms_lock_mask = 0x43,
2573 .cable_det_mask = 0x01, 2580 .cable_det_mask = 0x01,
2574 .fmt_change_digital_mask = 0x03, 2581 .fmt_change_digital_mask = 0x03,
2582 .cp_csc = 0xf4,
2575 .formats = adv7611_formats, 2583 .formats = adv7611_formats,
2576 .nformats = ARRAY_SIZE(adv7611_formats), 2584 .nformats = ARRAY_SIZE(adv7611_formats),
2577 .set_termination = adv7611_set_termination, 2585 .set_termination = adv7611_set_termination,
@@ -2584,34 +2592,34 @@ static const struct adv7604_chip_info adv7604_chip_info[] = {
2584 .num_recommended_settings = { 2592 .num_recommended_settings = {
2585 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2593 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2586 }, 2594 },
2587 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) | 2595 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2588 BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) | 2596 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2589 BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) | 2597 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2590 BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP), 2598 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2591 }, 2599 },
2592}; 2600};
2593 2601
2594static struct i2c_device_id adv7604_i2c_id[] = { 2602static struct i2c_device_id adv76xx_i2c_id[] = {
2595 { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] }, 2603 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2596 { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] }, 2604 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
2597 { } 2605 { }
2598}; 2606};
2599MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id); 2607MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
2600 2608
2601static struct of_device_id adv7604_of_id[] __maybe_unused = { 2609static struct of_device_id adv76xx_of_id[] __maybe_unused = {
2602 { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] }, 2610 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
2603 { } 2611 { }
2604}; 2612};
2605MODULE_DEVICE_TABLE(of, adv7604_of_id); 2613MODULE_DEVICE_TABLE(of, adv76xx_of_id);
2606 2614
2607static int adv7604_parse_dt(struct adv7604_state *state) 2615static int adv76xx_parse_dt(struct adv76xx_state *state)
2608{ 2616{
2609 struct v4l2_of_endpoint bus_cfg; 2617 struct v4l2_of_endpoint bus_cfg;
2610 struct device_node *endpoint; 2618 struct device_node *endpoint;
2611 struct device_node *np; 2619 struct device_node *np;
2612 unsigned int flags; 2620 unsigned int flags;
2613 2621
2614 np = state->i2c_clients[ADV7604_PAGE_IO]->dev.of_node; 2622 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
2615 2623
2616 /* Parse the endpoint. */ 2624 /* Parse the endpoint. */
2617 endpoint = of_graph_get_next_endpoint(np, NULL); 2625 endpoint = of_graph_get_next_endpoint(np, NULL);
@@ -2638,20 +2646,20 @@ static int adv7604_parse_dt(struct adv7604_state *state)
2638 } 2646 }
2639 2647
2640 /* Disable the interrupt for now as no DT-based board uses it. */ 2648 /* Disable the interrupt for now as no DT-based board uses it. */
2641 state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED; 2649 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
2642 2650
2643 /* Use the default I2C addresses. */ 2651 /* Use the default I2C addresses. */
2644 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42; 2652 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2645 state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40; 2653 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2646 state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e; 2654 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
2647 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38; 2655 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2648 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c; 2656 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2649 state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26; 2657 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2650 state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32; 2658 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2651 state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36; 2659 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2652 state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34; 2660 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2653 state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30; 2661 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2654 state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22; 2662 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
2655 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24; 2663 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2656 2664
2657 /* Hardcode the remaining platform data fields. */ 2665 /* Hardcode the remaining platform data fields. */
@@ -2666,12 +2674,12 @@ static int adv7604_parse_dt(struct adv7604_state *state)
2666 return 0; 2674 return 0;
2667} 2675}
2668 2676
2669static int adv7604_probe(struct i2c_client *client, 2677static int adv76xx_probe(struct i2c_client *client,
2670 const struct i2c_device_id *id) 2678 const struct i2c_device_id *id)
2671{ 2679{
2672 static const struct v4l2_dv_timings cea640x480 = 2680 static const struct v4l2_dv_timings cea640x480 =
2673 V4L2_DV_BT_CEA_640X480P59_94; 2681 V4L2_DV_BT_CEA_640X480P59_94;
2674 struct adv7604_state *state; 2682 struct adv76xx_state *state;
2675 struct v4l2_ctrl_handler *hdl; 2683 struct v4l2_ctrl_handler *hdl;
2676 struct v4l2_subdev *sd; 2684 struct v4l2_subdev *sd;
2677 unsigned int i; 2685 unsigned int i;
@@ -2681,16 +2689,16 @@ static int adv7604_probe(struct i2c_client *client,
2681 /* Check if the adapter supports the needed features */ 2689 /* Check if the adapter supports the needed features */
2682 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2690 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2683 return -EIO; 2691 return -EIO;
2684 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", 2692 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
2685 client->addr << 1); 2693 client->addr << 1);
2686 2694
2687 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 2695 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2688 if (!state) { 2696 if (!state) {
2689 v4l_err(client, "Could not allocate adv7604_state memory!\n"); 2697 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
2690 return -ENOMEM; 2698 return -ENOMEM;
2691 } 2699 }
2692 2700
2693 state->i2c_clients[ADV7604_PAGE_IO] = client; 2701 state->i2c_clients[ADV76XX_PAGE_IO] = client;
2694 2702
2695 /* initialize variables */ 2703 /* initialize variables */
2696 state->restart_stdi_once = true; 2704 state->restart_stdi_once = true;
@@ -2699,18 +2707,18 @@ static int adv7604_probe(struct i2c_client *client,
2699 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { 2707 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2700 const struct of_device_id *oid; 2708 const struct of_device_id *oid;
2701 2709
2702 oid = of_match_node(adv7604_of_id, client->dev.of_node); 2710 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
2703 state->info = oid->data; 2711 state->info = oid->data;
2704 2712
2705 err = adv7604_parse_dt(state); 2713 err = adv76xx_parse_dt(state);
2706 if (err < 0) { 2714 if (err < 0) {
2707 v4l_err(client, "DT parsing error\n"); 2715 v4l_err(client, "DT parsing error\n");
2708 return err; 2716 return err;
2709 } 2717 }
2710 } else if (client->dev.platform_data) { 2718 } else if (client->dev.platform_data) {
2711 struct adv7604_platform_data *pdata = client->dev.platform_data; 2719 struct adv76xx_platform_data *pdata = client->dev.platform_data;
2712 2720
2713 state->info = (const struct adv7604_chip_info *)id->driver_data; 2721 state->info = (const struct adv76xx_chip_info *)id->driver_data;
2714 state->pdata = *pdata; 2722 state->pdata = *pdata;
2715 } else { 2723 } else {
2716 v4l_err(client, "No platform data!\n"); 2724 v4l_err(client, "No platform data!\n");
@@ -2720,20 +2728,20 @@ static int adv7604_probe(struct i2c_client *client,
2720 /* Request GPIOs. */ 2728 /* Request GPIOs. */
2721 for (i = 0; i < state->info->num_dv_ports; ++i) { 2729 for (i = 0; i < state->info->num_dv_ports; ++i) {
2722 state->hpd_gpio[i] = 2730 state->hpd_gpio[i] =
2723 devm_gpiod_get_index(&client->dev, "hpd", i); 2731 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
2732 GPIOD_OUT_LOW);
2724 if (IS_ERR(state->hpd_gpio[i])) 2733 if (IS_ERR(state->hpd_gpio[i]))
2725 continue; 2734 return PTR_ERR(state->hpd_gpio[i]);
2726
2727 gpiod_direction_output(state->hpd_gpio[i], 0);
2728 2735
2729 v4l_info(client, "Handling HPD %u GPIO\n", i); 2736 if (state->hpd_gpio[i])
2737 v4l_info(client, "Handling HPD %u GPIO\n", i);
2730 } 2738 }
2731 2739
2732 state->timings = cea640x480; 2740 state->timings = cea640x480;
2733 state->format = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); 2741 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2734 2742
2735 sd = &state->sd; 2743 sd = &state->sd;
2736 v4l2_i2c_subdev_init(sd, client, &adv7604_ops); 2744 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
2737 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 2745 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2738 id->name, i2c_adapter_id(client->adapter), 2746 id->name, i2c_adapter_id(client->adapter),
2739 client->addr); 2747 client->addr);
@@ -2763,15 +2771,15 @@ static int adv7604_probe(struct i2c_client *client,
2763 2771
2764 /* control handlers */ 2772 /* control handlers */
2765 hdl = &state->hdl; 2773 hdl = &state->hdl;
2766 v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8); 2774 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
2767 2775
2768 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2776 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2769 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 2777 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2770 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2778 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2771 V4L2_CID_CONTRAST, 0, 255, 1, 128); 2779 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2772 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2780 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2773 V4L2_CID_SATURATION, 0, 255, 1, 128); 2781 V4L2_CID_SATURATION, 0, 255, 1, 128);
2774 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2782 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
2775 V4L2_CID_HUE, 0, 128, 1, 0); 2783 V4L2_CID_HUE, 0, 128, 1, 0);
2776 2784
2777 /* private controls */ 2785 /* private controls */
@@ -2779,18 +2787,18 @@ static int adv7604_probe(struct i2c_client *client,
2779 V4L2_CID_DV_RX_POWER_PRESENT, 0, 2787 V4L2_CID_DV_RX_POWER_PRESENT, 0,
2780 (1 << state->info->num_dv_ports) - 1, 0, 0); 2788 (1 << state->info->num_dv_ports) - 1, 0, 0);
2781 state->rgb_quantization_range_ctrl = 2789 state->rgb_quantization_range_ctrl =
2782 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, 2790 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
2783 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 2791 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2784 0, V4L2_DV_RGB_RANGE_AUTO); 2792 0, V4L2_DV_RGB_RANGE_AUTO);
2785 2793
2786 /* custom controls */ 2794 /* custom controls */
2787 if (adv7604_has_afe(state)) 2795 if (adv76xx_has_afe(state))
2788 state->analog_sampling_phase_ctrl = 2796 state->analog_sampling_phase_ctrl =
2789 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 2797 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2790 state->free_run_color_manual_ctrl = 2798 state->free_run_color_manual_ctrl =
2791 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); 2799 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
2792 state->free_run_color_ctrl = 2800 state->free_run_color_ctrl =
2793 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); 2801 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
2794 2802
2795 sd->ctrl_handler = hdl; 2803 sd->ctrl_handler = hdl;
2796 if (hdl->error) { 2804 if (hdl->error) {
@@ -2799,22 +2807,22 @@ static int adv7604_probe(struct i2c_client *client,
2799 } 2807 }
2800 state->detect_tx_5v_ctrl->is_private = true; 2808 state->detect_tx_5v_ctrl->is_private = true;
2801 state->rgb_quantization_range_ctrl->is_private = true; 2809 state->rgb_quantization_range_ctrl->is_private = true;
2802 if (adv7604_has_afe(state)) 2810 if (adv76xx_has_afe(state))
2803 state->analog_sampling_phase_ctrl->is_private = true; 2811 state->analog_sampling_phase_ctrl->is_private = true;
2804 state->free_run_color_manual_ctrl->is_private = true; 2812 state->free_run_color_manual_ctrl->is_private = true;
2805 state->free_run_color_ctrl->is_private = true; 2813 state->free_run_color_ctrl->is_private = true;
2806 2814
2807 if (adv7604_s_detect_tx_5v_ctrl(sd)) { 2815 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
2808 err = -ENODEV; 2816 err = -ENODEV;
2809 goto err_hdl; 2817 goto err_hdl;
2810 } 2818 }
2811 2819
2812 for (i = 1; i < ADV7604_PAGE_MAX; ++i) { 2820 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
2813 if (!(BIT(i) & state->info->page_mask)) 2821 if (!(BIT(i) & state->info->page_mask))
2814 continue; 2822 continue;
2815 2823
2816 state->i2c_clients[i] = 2824 state->i2c_clients[i] =
2817 adv7604_dummy_client(sd, state->pdata.i2c_addresses[i], 2825 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
2818 0xf2 + i); 2826 0xf2 + i);
2819 if (state->i2c_clients[i] == NULL) { 2827 if (state->i2c_clients[i] == NULL) {
2820 err = -ENOMEM; 2828 err = -ENOMEM;
@@ -2832,7 +2840,7 @@ static int adv7604_probe(struct i2c_client *client,
2832 } 2840 }
2833 2841
2834 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2842 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2835 adv7604_delayed_work_enable_hotplug); 2843 adv76xx_delayed_work_enable_hotplug);
2836 2844
2837 state->source_pad = state->info->num_dv_ports 2845 state->source_pad = state->info->num_dv_ports
2838 + (state->info->has_afe ? 2 : 0); 2846 + (state->info->has_afe ? 2 : 0);
@@ -2845,7 +2853,7 @@ static int adv7604_probe(struct i2c_client *client,
2845 if (err) 2853 if (err)
2846 goto err_work_queues; 2854 goto err_work_queues;
2847 2855
2848 err = adv7604_core_init(sd); 2856 err = adv76xx_core_init(sd);
2849 if (err) 2857 if (err)
2850 goto err_entity; 2858 goto err_entity;
2851 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2859 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
@@ -2863,7 +2871,7 @@ err_work_queues:
2863 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2871 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2864 destroy_workqueue(state->work_queues); 2872 destroy_workqueue(state->work_queues);
2865err_i2c: 2873err_i2c:
2866 adv7604_unregister_clients(state); 2874 adv76xx_unregister_clients(state);
2867err_hdl: 2875err_hdl:
2868 v4l2_ctrl_handler_free(hdl); 2876 v4l2_ctrl_handler_free(hdl);
2869 return err; 2877 return err;
@@ -2871,32 +2879,31 @@ err_hdl:
2871 2879
2872/* ----------------------------------------------------------------------- */ 2880/* ----------------------------------------------------------------------- */
2873 2881
2874static int adv7604_remove(struct i2c_client *client) 2882static int adv76xx_remove(struct i2c_client *client)
2875{ 2883{
2876 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2884 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2877 struct adv7604_state *state = to_state(sd); 2885 struct adv76xx_state *state = to_state(sd);
2878 2886
2879 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2887 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2880 destroy_workqueue(state->work_queues); 2888 destroy_workqueue(state->work_queues);
2881 v4l2_async_unregister_subdev(sd); 2889 v4l2_async_unregister_subdev(sd);
2882 v4l2_device_unregister_subdev(sd);
2883 media_entity_cleanup(&sd->entity); 2890 media_entity_cleanup(&sd->entity);
2884 adv7604_unregister_clients(to_state(sd)); 2891 adv76xx_unregister_clients(to_state(sd));
2885 v4l2_ctrl_handler_free(sd->ctrl_handler); 2892 v4l2_ctrl_handler_free(sd->ctrl_handler);
2886 return 0; 2893 return 0;
2887} 2894}
2888 2895
2889/* ----------------------------------------------------------------------- */ 2896/* ----------------------------------------------------------------------- */
2890 2897
2891static struct i2c_driver adv7604_driver = { 2898static struct i2c_driver adv76xx_driver = {
2892 .driver = { 2899 .driver = {
2893 .owner = THIS_MODULE, 2900 .owner = THIS_MODULE,
2894 .name = "adv7604", 2901 .name = "adv7604",
2895 .of_match_table = of_match_ptr(adv7604_of_id), 2902 .of_match_table = of_match_ptr(adv76xx_of_id),
2896 }, 2903 },
2897 .probe = adv7604_probe, 2904 .probe = adv76xx_probe,
2898 .remove = adv7604_remove, 2905 .remove = adv76xx_remove,
2899 .id_table = adv7604_i2c_id, 2906 .id_table = adv76xx_i2c_id,
2900}; 2907};
2901 2908
2902module_i2c_driver(adv7604_driver); 2909module_i2c_driver(adv76xx_driver);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-10 02:39:53 -0400