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-rw-r--r--drivers/media/dvb/Kconfig2
-rw-r--r--drivers/media/dvb/dvb-core/dvb_frontend.h1
-rw-r--r--drivers/media/dvb/dvb-usb/Kconfig8
-rw-r--r--drivers/media/dvb/dvb-usb/Makefile3
-rw-r--r--drivers/media/dvb/dvb-usb/a800.c8
-rw-r--r--drivers/media/dvb/dvb-usb/af9015.c67
-rw-r--r--drivers/media/dvb/dvb-usb/af9015.h1
-rw-r--r--drivers/media/dvb/dvb-usb/dib0700.h2
-rw-r--r--drivers/media/dvb/dvb-usb/dib0700_core.c47
-rw-r--r--drivers/media/dvb/dvb-usb/dib0700_devices.c1381
-rw-r--r--drivers/media/dvb/dvb-usb/digitv.c2
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb-ids.h7
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb-remote.c111
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb.h2
-rw-r--r--drivers/media/dvb/dvb-usb/dw2102.c590
-rw-r--r--drivers/media/dvb/dvb-usb/lmedm04.c235
-rw-r--r--drivers/media/dvb/dvb-usb/opera1.c33
-rw-r--r--drivers/media/dvb/dvb-usb/technisat-usb2.c807
-rw-r--r--drivers/media/dvb/firewire/Kconfig8
-rw-r--r--drivers/media/dvb/firewire/Makefile5
-rw-r--r--drivers/media/dvb/firewire/firedtv-1394.c300
-rw-r--r--drivers/media/dvb/firewire/firedtv-avc.c15
-rw-r--r--drivers/media/dvb/firewire/firedtv-dvb.c135
-rw-r--r--drivers/media/dvb/firewire/firedtv-fe.c8
-rw-r--r--drivers/media/dvb/firewire/firedtv-fw.c146
-rw-r--r--drivers/media/dvb/firewire/firedtv.h45
-rw-r--r--drivers/media/dvb/frontends/Kconfig15
-rw-r--r--drivers/media/dvb/frontends/Makefile2
-rw-r--r--drivers/media/dvb/frontends/af9013.c55
-rw-r--r--drivers/media/dvb/frontends/dib0090.c1583
-rw-r--r--drivers/media/dvb/frontends/dib0090.h31
-rw-r--r--drivers/media/dvb/frontends/dib7000p.c1945
-rw-r--r--drivers/media/dvb/frontends/dib7000p.h96
-rw-r--r--drivers/media/dvb/frontends/dib8000.c821
-rw-r--r--drivers/media/dvb/frontends/dib8000.h20
-rw-r--r--drivers/media/dvb/frontends/dib9000.c2351
-rw-r--r--drivers/media/dvb/frontends/dib9000.h131
-rw-r--r--drivers/media/dvb/frontends/dibx000_common.c279
-rw-r--r--drivers/media/dvb/frontends/dibx000_common.h152
-rw-r--r--drivers/media/dvb/frontends/ds3000.c645
-rw-r--r--drivers/media/dvb/frontends/ds3000.h3
-rw-r--r--drivers/media/dvb/frontends/dvb-pll.c79
-rw-r--r--drivers/media/dvb/frontends/stv0288.c7
-rw-r--r--drivers/media/dvb/frontends/stv0367.c3459
-rw-r--r--drivers/media/dvb/frontends/stv0367.h66
-rw-r--r--drivers/media/dvb/frontends/stv0367_priv.h212
-rw-r--r--drivers/media/dvb/frontends/stv0367_regs.h3614
-rw-r--r--drivers/media/dvb/frontends/stv0900.h2
-rw-r--r--drivers/media/dvb/frontends/stv0900_core.c27
-rw-r--r--drivers/media/dvb/frontends/stv090x.c295
-rw-r--r--drivers/media/dvb/frontends/stv090x.h16
-rw-r--r--drivers/media/dvb/frontends/stv090x_reg.h16
-rw-r--r--drivers/media/dvb/frontends/zl10036.c10
-rw-r--r--drivers/media/dvb/ngene/Makefile3
-rw-r--r--drivers/media/dvb/ngene/ngene-cards.c179
-rw-r--r--drivers/media/dvb/ngene/ngene-core.c236
-rw-r--r--drivers/media/dvb/ngene/ngene-dvb.c71
-rw-r--r--drivers/media/dvb/ngene/ngene.h24
-rw-r--r--drivers/media/dvb/siano/sms-cards.c2
-rw-r--r--drivers/media/dvb/ttpci/budget-ci.c15
-rw-r--r--drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c1
61 files changed, 17769 insertions, 2663 deletions
diff --git a/drivers/media/dvb/Kconfig b/drivers/media/dvb/Kconfig
index 161ccfd471cb..ee214c3b63d7 100644
--- a/drivers/media/dvb/Kconfig
+++ b/drivers/media/dvb/Kconfig
@@ -65,7 +65,7 @@ comment "Supported SDMC DM1105 Adapters"
65source "drivers/media/dvb/dm1105/Kconfig" 65source "drivers/media/dvb/dm1105/Kconfig"
66 66
67comment "Supported FireWire (IEEE 1394) Adapters" 67comment "Supported FireWire (IEEE 1394) Adapters"
68 depends on DVB_CORE && IEEE1394 68 depends on DVB_CORE && FIREWIRE
69source "drivers/media/dvb/firewire/Kconfig" 69source "drivers/media/dvb/firewire/Kconfig"
70 70
71comment "Supported Earthsoft PT1 Adapters" 71comment "Supported Earthsoft PT1 Adapters"
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.h b/drivers/media/dvb/dvb-core/dvb_frontend.h
index f9f19be77181..3b860504bf04 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.h
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.h
@@ -239,7 +239,6 @@ struct analog_demod_ops {
239 void (*set_params)(struct dvb_frontend *fe, 239 void (*set_params)(struct dvb_frontend *fe,
240 struct analog_parameters *params); 240 struct analog_parameters *params);
241 int (*has_signal)(struct dvb_frontend *fe); 241 int (*has_signal)(struct dvb_frontend *fe);
242 int (*is_stereo)(struct dvb_frontend *fe);
243 int (*get_afc)(struct dvb_frontend *fe); 242 int (*get_afc)(struct dvb_frontend *fe);
244 void (*tuner_status)(struct dvb_frontend *fe); 243 void (*tuner_status)(struct dvb_frontend *fe);
245 void (*standby)(struct dvb_frontend *fe); 244 void (*standby)(struct dvb_frontend *fe);
diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
index 3d48ba019342..fe4f894183ff 100644
--- a/drivers/media/dvb/dvb-usb/Kconfig
+++ b/drivers/media/dvb/dvb-usb/Kconfig
@@ -358,3 +358,11 @@ config DVB_USB_LME2510
358 select DVB_IX2505V if !DVB_FE_CUSTOMISE 358 select DVB_IX2505V if !DVB_FE_CUSTOMISE
359 help 359 help
360 Say Y here to support the LME DM04/QQBOX DVB-S USB2.0 . 360 Say Y here to support the LME DM04/QQBOX DVB-S USB2.0 .
361
362config DVB_USB_TECHNISAT_USB2
363 tristate "Technisat DVB-S/S2 USB2.0 support"
364 depends on DVB_USB
365 select DVB_STB0899 if !DVB_FE_CUSTOMISE
366 select DVB_STB6100 if !DVB_FE_CUSTOMISE
367 help
368 Say Y here to support the Technisat USB2 DVB-S/S2 device
diff --git a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Makefile
index 5b1d12f2d591..4bac13da0c39 100644
--- a/drivers/media/dvb/dvb-usb/Makefile
+++ b/drivers/media/dvb/dvb-usb/Makefile
@@ -91,6 +91,9 @@ obj-$(CONFIG_DVB_USB_AZ6027) += dvb-usb-az6027.o
91dvb-usb-lmedm04-objs = lmedm04.o 91dvb-usb-lmedm04-objs = lmedm04.o
92obj-$(CONFIG_DVB_USB_LME2510) += dvb-usb-lmedm04.o 92obj-$(CONFIG_DVB_USB_LME2510) += dvb-usb-lmedm04.o
93 93
94dvb-usb-technisat-usb2-objs = technisat-usb2.o
95obj-$(CONFIG_DVB_USB_TECHNISAT_USB2) += dvb-usb-technisat-usb2.o
96
94EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/ 97EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/
95# due to tuner-xc3028 98# due to tuner-xc3028
96EXTRA_CFLAGS += -Idrivers/media/common/tuners 99EXTRA_CFLAGS += -Idrivers/media/common/tuners
diff --git a/drivers/media/dvb/dvb-usb/a800.c b/drivers/media/dvb/dvb-usb/a800.c
index 53b93a4b6f8a..f8e9bf116f21 100644
--- a/drivers/media/dvb/dvb-usb/a800.c
+++ b/drivers/media/dvb/dvb-usb/a800.c
@@ -38,8 +38,8 @@ static int a800_identify_state(struct usb_device *udev, struct dvb_usb_device_pr
38} 38}
39 39
40static struct rc_map_table rc_map_a800_table[] = { 40static struct rc_map_table rc_map_a800_table[] = {
41 { 0x0201, KEY_PROG1 }, /* SOURCE */ 41 { 0x0201, KEY_MODE }, /* SOURCE */
42 { 0x0200, KEY_POWER }, /* POWER */ 42 { 0x0200, KEY_POWER2 }, /* POWER */
43 { 0x0205, KEY_1 }, /* 1 */ 43 { 0x0205, KEY_1 }, /* 1 */
44 { 0x0206, KEY_2 }, /* 2 */ 44 { 0x0206, KEY_2 }, /* 2 */
45 { 0x0207, KEY_3 }, /* 3 */ 45 { 0x0207, KEY_3 }, /* 3 */
@@ -52,8 +52,8 @@ static struct rc_map_table rc_map_a800_table[] = {
52 { 0x0212, KEY_LEFT }, /* L / DISPLAY */ 52 { 0x0212, KEY_LEFT }, /* L / DISPLAY */
53 { 0x0211, KEY_0 }, /* 0 */ 53 { 0x0211, KEY_0 }, /* 0 */
54 { 0x0213, KEY_RIGHT }, /* R / CH RTN */ 54 { 0x0213, KEY_RIGHT }, /* R / CH RTN */
55 { 0x0217, KEY_PROG2 }, /* SNAP SHOT */ 55 { 0x0217, KEY_CAMERA }, /* SNAP SHOT */
56 { 0x0210, KEY_PROG3 }, /* 16-CH PREV */ 56 { 0x0210, KEY_LAST }, /* 16-CH PREV */
57 { 0x021e, KEY_VOLUMEDOWN }, /* VOL DOWN */ 57 { 0x021e, KEY_VOLUMEDOWN }, /* VOL DOWN */
58 { 0x020c, KEY_ZOOM }, /* FULL SCREEN */ 58 { 0x020c, KEY_ZOOM }, /* FULL SCREEN */
59 { 0x021f, KEY_VOLUMEUP }, /* VOL UP */ 59 { 0x021f, KEY_VOLUMEUP }, /* VOL UP */
diff --git a/drivers/media/dvb/dvb-usb/af9015.c b/drivers/media/dvb/dvb-usb/af9015.c
index 8671ca362c81..100ebc37e99e 100644
--- a/drivers/media/dvb/dvb-usb/af9015.c
+++ b/drivers/media/dvb/dvb-usb/af9015.c
@@ -479,6 +479,7 @@ static int af9015_init_endpoint(struct dvb_usb_device *d)
479 ret = af9015_set_reg_bit(d, 0xd50b, 0); 479 ret = af9015_set_reg_bit(d, 0xd50b, 0);
480 else 480 else
481 ret = af9015_clear_reg_bit(d, 0xd50b, 0); 481 ret = af9015_clear_reg_bit(d, 0xd50b, 0);
482
482error: 483error:
483 if (ret) 484 if (ret)
484 err("endpoint init failed:%d", ret); 485 err("endpoint init failed:%d", ret);
@@ -611,6 +612,11 @@ static int af9015_init(struct dvb_usb_device *d)
611 int ret; 612 int ret;
612 deb_info("%s:\n", __func__); 613 deb_info("%s:\n", __func__);
613 614
615 /* init RC canary */
616 ret = af9015_write_reg(d, 0x98e9, 0xff);
617 if (ret)
618 goto error;
619
614 ret = af9015_init_endpoint(d); 620 ret = af9015_init_endpoint(d);
615 if (ret) 621 if (ret)
616 goto error; 622 goto error;
@@ -659,9 +665,8 @@ error:
659static int af9015_download_firmware(struct usb_device *udev, 665static int af9015_download_firmware(struct usb_device *udev,
660 const struct firmware *fw) 666 const struct firmware *fw)
661{ 667{
662 int i, len, packets, remainder, ret; 668 int i, len, remaining, ret;
663 struct req_t req = {DOWNLOAD_FIRMWARE, 0, 0, 0, 0, 0, NULL}; 669 struct req_t req = {DOWNLOAD_FIRMWARE, 0, 0, 0, 0, 0, NULL};
664 u16 addr = 0x5100; /* firmware start address */
665 u16 checksum = 0; 670 u16 checksum = 0;
666 671
667 deb_info("%s:\n", __func__); 672 deb_info("%s:\n", __func__);
@@ -673,24 +678,20 @@ static int af9015_download_firmware(struct usb_device *udev,
673 af9015_config.firmware_size = fw->size; 678 af9015_config.firmware_size = fw->size;
674 af9015_config.firmware_checksum = checksum; 679 af9015_config.firmware_checksum = checksum;
675 680
676 #define FW_PACKET_MAX_DATA 55 681 #define FW_ADDR 0x5100 /* firmware start address */
677 682 #define LEN_MAX 55 /* max packet size */
678 packets = fw->size / FW_PACKET_MAX_DATA; 683 for (remaining = fw->size; remaining > 0; remaining -= LEN_MAX) {
679 remainder = fw->size % FW_PACKET_MAX_DATA; 684 len = remaining;
680 len = FW_PACKET_MAX_DATA; 685 if (len > LEN_MAX)
681 for (i = 0; i <= packets; i++) { 686 len = LEN_MAX;
682 if (i == packets) /* set size of the last packet */
683 len = remainder;
684 687
685 req.data_len = len; 688 req.data_len = len;
686 req.data = (u8 *)(fw->data + i * FW_PACKET_MAX_DATA); 689 req.data = (u8 *) &fw->data[fw->size - remaining];
687 req.addr = addr; 690 req.addr = FW_ADDR + fw->size - remaining;
688 addr += FW_PACKET_MAX_DATA;
689 691
690 ret = af9015_rw_udev(udev, &req); 692 ret = af9015_rw_udev(udev, &req);
691 if (ret) { 693 if (ret) {
692 err("firmware download failed at packet %d with " \ 694 err("firmware download failed:%d", ret);
693 "code %d", i, ret);
694 goto error; 695 goto error;
695 } 696 }
696 } 697 }
@@ -738,6 +739,8 @@ static const struct af9015_rc_setup af9015_rc_setup_hashes[] = {
738}; 739};
739 740
740static const struct af9015_rc_setup af9015_rc_setup_usbids[] = { 741static const struct af9015_rc_setup af9015_rc_setup_usbids[] = {
742 { (USB_VID_TERRATEC << 16) + USB_PID_TERRATEC_CINERGY_T_STICK_RC,
743 RC_MAP_TERRATEC_SLIM_2 },
741 { (USB_VID_TERRATEC << 16) + USB_PID_TERRATEC_CINERGY_T_STICK_DUAL_RC, 744 { (USB_VID_TERRATEC << 16) + USB_PID_TERRATEC_CINERGY_T_STICK_DUAL_RC,
742 RC_MAP_TERRATEC_SLIM }, 745 RC_MAP_TERRATEC_SLIM },
743 { (USB_VID_VISIONPLUS << 16) + USB_PID_AZUREWAVE_AD_TU700, 746 { (USB_VID_VISIONPLUS << 16) + USB_PID_AZUREWAVE_AD_TU700,
@@ -1016,22 +1019,38 @@ static int af9015_rc_query(struct dvb_usb_device *d)
1016{ 1019{
1017 struct af9015_state *priv = d->priv; 1020 struct af9015_state *priv = d->priv;
1018 int ret; 1021 int ret;
1019 u8 buf[16]; 1022 u8 buf[17];
1020 1023
1021 /* read registers needed to detect remote controller code */ 1024 /* read registers needed to detect remote controller code */
1022 ret = af9015_read_regs(d, 0x98d9, buf, sizeof(buf)); 1025 ret = af9015_read_regs(d, 0x98d9, buf, sizeof(buf));
1023 if (ret) 1026 if (ret)
1024 goto error; 1027 goto error;
1025 1028
1026 if (buf[14] || buf[15]) { 1029 /* If any of these are non-zero, assume invalid data */
1030 if (buf[1] || buf[2] || buf[3])
1031 return ret;
1032
1033 /* Check for repeat of previous code */
1034 if ((priv->rc_repeat != buf[6] || buf[0]) &&
1035 !memcmp(&buf[12], priv->rc_last, 4)) {
1036 deb_rc("%s: key repeated\n", __func__);
1037 rc_keydown(d->rc_dev, priv->rc_keycode, 0);
1038 priv->rc_repeat = buf[6];
1039 return ret;
1040 }
1041
1042 /* Only process key if canary killed */
1043 if (buf[16] != 0xff && buf[0] != 0x01) {
1027 deb_rc("%s: key pressed %02x %02x %02x %02x\n", __func__, 1044 deb_rc("%s: key pressed %02x %02x %02x %02x\n", __func__,
1028 buf[12], buf[13], buf[14], buf[15]); 1045 buf[12], buf[13], buf[14], buf[15]);
1029 1046
1030 /* clean IR code from mem */ 1047 /* Reset the canary */
1031 ret = af9015_write_regs(d, 0x98e5, "\x00\x00\x00\x00", 4); 1048 ret = af9015_write_reg(d, 0x98e9, 0xff);
1032 if (ret) 1049 if (ret)
1033 goto error; 1050 goto error;
1034 1051
1052 /* Remember this key */
1053 memcpy(priv->rc_last, &buf[12], 4);
1035 if (buf[14] == (u8) ~buf[15]) { 1054 if (buf[14] == (u8) ~buf[15]) {
1036 if (buf[12] == (u8) ~buf[13]) { 1055 if (buf[12] == (u8) ~buf[13]) {
1037 /* NEC */ 1056 /* NEC */
@@ -1041,15 +1060,17 @@ static int af9015_rc_query(struct dvb_usb_device *d)
1041 priv->rc_keycode = buf[12] << 16 | 1060 priv->rc_keycode = buf[12] << 16 |
1042 buf[13] << 8 | buf[14]; 1061 buf[13] << 8 | buf[14];
1043 } 1062 }
1044 rc_keydown(d->rc_dev, priv->rc_keycode, 0);
1045 } else { 1063 } else {
1046 priv->rc_keycode = 0; /* clear just for sure */ 1064 /* 32 bit NEC */
1065 priv->rc_keycode = buf[12] << 24 | buf[13] << 16 |
1066 buf[14] << 8 | buf[15];
1047 } 1067 }
1048 } else if (priv->rc_repeat != buf[6] || buf[0]) {
1049 deb_rc("%s: key repeated\n", __func__);
1050 rc_keydown(d->rc_dev, priv->rc_keycode, 0); 1068 rc_keydown(d->rc_dev, priv->rc_keycode, 0);
1051 } else { 1069 } else {
1052 deb_rc("%s: no key press\n", __func__); 1070 deb_rc("%s: no key press\n", __func__);
1071 /* Invalidate last keypress */
1072 /* Not really needed, but helps with debug */
1073 priv->rc_last[2] = priv->rc_last[3];
1053 } 1074 }
1054 1075
1055 priv->rc_repeat = buf[6]; 1076 priv->rc_repeat = buf[6];
diff --git a/drivers/media/dvb/dvb-usb/af9015.h b/drivers/media/dvb/dvb-usb/af9015.h
index f20cfa6ed690..beb3004f00ba 100644
--- a/drivers/media/dvb/dvb-usb/af9015.h
+++ b/drivers/media/dvb/dvb-usb/af9015.h
@@ -102,6 +102,7 @@ struct af9015_state {
102 struct i2c_adapter i2c_adap; /* I2C adapter for 2nd FE */ 102 struct i2c_adapter i2c_adap; /* I2C adapter for 2nd FE */
103 u8 rc_repeat; 103 u8 rc_repeat;
104 u32 rc_keycode; 104 u32 rc_keycode;
105 u8 rc_last[4];
105}; 106};
106 107
107struct af9015_config { 108struct af9015_config {
diff --git a/drivers/media/dvb/dvb-usb/dib0700.h b/drivers/media/dvb/dvb-usb/dib0700.h
index 3537d65c04bc..b2a87f2c2c3e 100644
--- a/drivers/media/dvb/dvb-usb/dib0700.h
+++ b/drivers/media/dvb/dvb-usb/dib0700.h
@@ -32,6 +32,7 @@ extern int dvb_usb_dib0700_debug;
32 // 1 Byte: 4MSB(1 = enable streaming, 0 = disable streaming) 4LSB(Video Mode: 0 = MPEG2 188Bytes, 1 = Analog) 32 // 1 Byte: 4MSB(1 = enable streaming, 0 = disable streaming) 4LSB(Video Mode: 0 = MPEG2 188Bytes, 1 = Analog)
33 // 2 Byte: MPEG2 mode: 4MSB(1 = Master Mode, 0 = Slave Mode) 4LSB(Channel 1 = bit0, Channel 2 = bit1) 33 // 2 Byte: MPEG2 mode: 4MSB(1 = Master Mode, 0 = Slave Mode) 4LSB(Channel 1 = bit0, Channel 2 = bit1)
34 // 2 Byte: Analog mode: 4MSB(0 = 625 lines, 1 = 525 lines) 4LSB( " " ) 34 // 2 Byte: Analog mode: 4MSB(0 = 625 lines, 1 = 525 lines) 4LSB( " " )
35#define REQUEST_SET_I2C_PARAM 0x10
35#define REQUEST_SET_RC 0x11 36#define REQUEST_SET_RC 0x11
36#define REQUEST_NEW_I2C_READ 0x12 37#define REQUEST_NEW_I2C_READ 0x12
37#define REQUEST_NEW_I2C_WRITE 0x13 38#define REQUEST_NEW_I2C_WRITE 0x13
@@ -61,6 +62,7 @@ extern struct i2c_algorithm dib0700_i2c_algo;
61extern int dib0700_identify_state(struct usb_device *udev, struct dvb_usb_device_properties *props, 62extern int dib0700_identify_state(struct usb_device *udev, struct dvb_usb_device_properties *props,
62 struct dvb_usb_device_description **desc, int *cold); 63 struct dvb_usb_device_description **desc, int *cold);
63extern int dib0700_change_protocol(struct rc_dev *dev, u64 rc_type); 64extern int dib0700_change_protocol(struct rc_dev *dev, u64 rc_type);
65extern int dib0700_set_i2c_speed(struct dvb_usb_device *d, u16 scl_kHz);
64 66
65extern int dib0700_device_count; 67extern int dib0700_device_count;
66extern int dvb_usb_dib0700_ir_proto; 68extern int dvb_usb_dib0700_ir_proto;
diff --git a/drivers/media/dvb/dvb-usb/dib0700_core.c b/drivers/media/dvb/dvb-usb/dib0700_core.c
index 98ffb40728e3..b79af68c54ae 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_core.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_core.c
@@ -186,7 +186,7 @@ static int dib0700_i2c_xfer_new(struct i2c_adapter *adap, struct i2c_msg *msg,
186 msg[i].len, 186 msg[i].len,
187 USB_CTRL_GET_TIMEOUT); 187 USB_CTRL_GET_TIMEOUT);
188 if (result < 0) { 188 if (result < 0) {
189 err("i2c read error (status = %d)\n", result); 189 deb_info("i2c read error (status = %d)\n", result);
190 break; 190 break;
191 } 191 }
192 192
@@ -215,7 +215,7 @@ static int dib0700_i2c_xfer_new(struct i2c_adapter *adap, struct i2c_msg *msg,
215 0, 0, buf, msg[i].len + 4, 215 0, 0, buf, msg[i].len + 4,
216 USB_CTRL_GET_TIMEOUT); 216 USB_CTRL_GET_TIMEOUT);
217 if (result < 0) { 217 if (result < 0) {
218 err("i2c write error (status = %d)\n", result); 218 deb_info("i2c write error (status = %d)\n", result);
219 break; 219 break;
220 } 220 }
221 } 221 }
@@ -328,6 +328,31 @@ static int dib0700_set_clock(struct dvb_usb_device *d, u8 en_pll,
328 return dib0700_ctrl_wr(d, b, 10); 328 return dib0700_ctrl_wr(d, b, 10);
329} 329}
330 330
331int dib0700_set_i2c_speed(struct dvb_usb_device *d, u16 scl_kHz)
332{
333 u16 divider;
334 u8 b[8];
335
336 if (scl_kHz == 0)
337 return -EINVAL;
338
339 b[0] = REQUEST_SET_I2C_PARAM;
340 divider = (u16) (30000 / scl_kHz);
341 b[2] = (u8) (divider >> 8);
342 b[3] = (u8) (divider & 0xff);
343 divider = (u16) (72000 / scl_kHz);
344 b[4] = (u8) (divider >> 8);
345 b[5] = (u8) (divider & 0xff);
346 divider = (u16) (72000 / scl_kHz); /* clock: 72MHz */
347 b[6] = (u8) (divider >> 8);
348 b[7] = (u8) (divider & 0xff);
349
350 deb_info("setting I2C speed: %04x %04x %04x (%d kHz).",
351 (b[2] << 8) | (b[3]), (b[4] << 8) | b[5], (b[6] << 8) | b[7], scl_kHz);
352 return dib0700_ctrl_wr(d, b, 8);
353}
354
355
331int dib0700_ctrl_clock(struct dvb_usb_device *d, u32 clk_MHz, u8 clock_out_gp3) 356int dib0700_ctrl_clock(struct dvb_usb_device *d, u32 clk_MHz, u8 clock_out_gp3)
332{ 357{
333 switch (clk_MHz) { 358 switch (clk_MHz) {
@@ -459,10 +484,20 @@ int dib0700_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff)
459 484
460 deb_info("modifying (%d) streaming state for %d\n", onoff, adap->id); 485 deb_info("modifying (%d) streaming state for %d\n", onoff, adap->id);
461 486
462 if (onoff) 487 st->channel_state &= ~0x3;
463 st->channel_state |= 1 << adap->id; 488 if ((adap->stream.props.endpoint != 2)
464 else 489 && (adap->stream.props.endpoint != 3)) {
465 st->channel_state &= ~(1 << adap->id); 490 deb_info("the endpoint number (%i) is not correct, use the adapter id instead", adap->stream.props.endpoint);
491 if (onoff)
492 st->channel_state |= 1 << (adap->id);
493 else
494 st->channel_state |= 1 << ~(adap->id);
495 } else {
496 if (onoff)
497 st->channel_state |= 1 << (adap->stream.props.endpoint-2);
498 else
499 st->channel_state |= 1 << (3-adap->stream.props.endpoint);
500 }
466 501
467 b[2] |= st->channel_state; 502 b[2] |= st->channel_state;
468 503
diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c
index 193cdb77b76a..97af266d7f1d 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c
@@ -12,6 +12,7 @@
12#include "dib7000m.h" 12#include "dib7000m.h"
13#include "dib7000p.h" 13#include "dib7000p.h"
14#include "dib8000.h" 14#include "dib8000.h"
15#include "dib9000.h"
15#include "mt2060.h" 16#include "mt2060.h"
16#include "mt2266.h" 17#include "mt2266.h"
17#include "tuner-xc2028.h" 18#include "tuner-xc2028.h"
@@ -29,6 +30,7 @@ MODULE_PARM_DESC(force_lna_activation, "force the activation of Low-Noise-Amplif
29 30
30struct dib0700_adapter_state { 31struct dib0700_adapter_state {
31 int (*set_param_save) (struct dvb_frontend *, struct dvb_frontend_parameters *); 32 int (*set_param_save) (struct dvb_frontend *, struct dvb_frontend_parameters *);
33 const struct firmware *frontend_firmware;
32}; 34};
33 35
34/* Hauppauge Nova-T 500 (aka Bristol) 36/* Hauppauge Nova-T 500 (aka Bristol)
@@ -1243,13 +1245,13 @@ static int dib807x_tuner_attach(struct dvb_usb_adapter *adap)
1243static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index, 1245static int stk80xx_pid_filter(struct dvb_usb_adapter *adapter, int index,
1244 u16 pid, int onoff) 1246 u16 pid, int onoff)
1245{ 1247{
1246 return dib8000_pid_filter(adapter->fe, index, pid, onoff); 1248 return dib8000_pid_filter(adapter->fe, index, pid, onoff);
1247} 1249}
1248 1250
1249static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter, 1251static int stk80xx_pid_filter_ctrl(struct dvb_usb_adapter *adapter,
1250 int onoff) 1252 int onoff)
1251{ 1253{
1252 return dib8000_pid_filter_ctrl(adapter->fe, onoff); 1254 return dib8000_pid_filter_ctrl(adapter->fe, onoff);
1253} 1255}
1254 1256
1255/* STK807x */ 1257/* STK807x */
@@ -1321,11 +1323,11 @@ static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap)
1321 1323
1322/* STK8096GP */ 1324/* STK8096GP */
1323struct dibx000_agc_config dib8090_agc_config[2] = { 1325struct dibx000_agc_config dib8090_agc_config[2] = {
1324 { 1326 {
1325 BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, 1327 BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
1326 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, 1328 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
1327 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0, 1329 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1328 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ 1330 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
1329 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) 1331 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
1330 | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), 1332 | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1331 1333
@@ -1362,12 +1364,12 @@ struct dibx000_agc_config dib8090_agc_config[2] = {
1362 51, 1364 51,
1363 1365
1364 0, 1366 0,
1365 }, 1367 },
1366 { 1368 {
1367 BAND_CBAND, 1369 BAND_CBAND,
1368 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, 1370 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1,
1369 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0, 1371 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
1370 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ 1372 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
1371 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) 1373 (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8)
1372 | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), 1374 | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
1373 1375
@@ -1404,135 +1406,153 @@ struct dibx000_agc_config dib8090_agc_config[2] = {
1404 51, 1406 51,
1405 1407
1406 0, 1408 0,
1407 } 1409 }
1408}; 1410};
1409 1411
1410static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = { 1412static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = {
1411 54000, 13500, 1413 54000, 13500,
1412 1, 18, 3, 1, 0, 1414 1, 18, 3, 1, 0,
1413 0, 0, 1, 1, 2, 1415 0, 0, 1, 1, 2,
1414 (3 << 14) | (1 << 12) | (599 << 0), 1416 (3 << 14) | (1 << 12) | (599 << 0),
1415 (0 << 25) | 0, 1417 (0 << 25) | 0,
1416 20199727, 1418 20199727,
1417 12000000, 1419 12000000,
1418}; 1420};
1419 1421
1420static int dib8090_get_adc_power(struct dvb_frontend *fe) 1422static int dib8090_get_adc_power(struct dvb_frontend *fe)
1421{ 1423{
1422 return dib8000_get_adc_power(fe, 1); 1424 return dib8000_get_adc_power(fe, 1);
1423} 1425}
1424 1426
1425static struct dib8000_config dib809x_dib8000_config = { 1427static struct dib8000_config dib809x_dib8000_config[2] = {
1426 .output_mpeg2_in_188_bytes = 1, 1428 {
1427 1429 .output_mpeg2_in_188_bytes = 1,
1428 .agc_config_count = 2, 1430
1429 .agc = dib8090_agc_config, 1431 .agc_config_count = 2,
1430 .agc_control = dib0090_dcc_freq, 1432 .agc = dib8090_agc_config,
1431 .pll = &dib8090_pll_config_12mhz, 1433 .agc_control = dib0090_dcc_freq,
1432 .tuner_is_baseband = 1, 1434 .pll = &dib8090_pll_config_12mhz,
1433 1435 .tuner_is_baseband = 1,
1434 .gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS, 1436
1435 .gpio_val = DIB8000_GPIO_DEFAULT_VALUES, 1437 .gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS,
1436 .gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS, 1438 .gpio_val = DIB8000_GPIO_DEFAULT_VALUES,
1437 1439 .gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS,
1438 .hostbus_diversity = 1, 1440
1439 .div_cfg = 0x31, 1441 .hostbus_diversity = 1,
1440 .output_mode = OUTMODE_MPEG2_FIFO, 1442 .div_cfg = 0x31,
1441 .drives = 0x2d98, 1443 .output_mode = OUTMODE_MPEG2_FIFO,
1442 .diversity_delay = 144, 1444 .drives = 0x2d98,
1443 .refclksel = 3, 1445 .diversity_delay = 48,
1446 .refclksel = 3,
1447 }, {
1448 .output_mpeg2_in_188_bytes = 1,
1449
1450 .agc_config_count = 2,
1451 .agc = dib8090_agc_config,
1452 .agc_control = dib0090_dcc_freq,
1453 .pll = &dib8090_pll_config_12mhz,
1454 .tuner_is_baseband = 1,
1455
1456 .gpio_dir = DIB8000_GPIO_DEFAULT_DIRECTIONS,
1457 .gpio_val = DIB8000_GPIO_DEFAULT_VALUES,
1458 .gpio_pwm_pos = DIB8000_GPIO_DEFAULT_PWM_POS,
1459
1460 .hostbus_diversity = 1,
1461 .div_cfg = 0x31,
1462 .output_mode = OUTMODE_DIVERSITY,
1463 .drives = 0x2d08,
1464 .diversity_delay = 1,
1465 .refclksel = 3,
1466 }
1467};
1468
1469static struct dib0090_wbd_slope dib8090_wbd_table[] = {
1470 /* max freq ; cold slope ; cold offset ; warm slope ; warm offset ; wbd gain */
1471 { 120, 0, 500, 0, 500, 4 }, /* CBAND */
1472 { 170, 0, 450, 0, 450, 4 }, /* CBAND */
1473 { 380, 48, 373, 28, 259, 6 }, /* VHF */
1474 { 860, 34, 700, 36, 616, 6 }, /* high UHF */
1475 { 0xFFFF, 34, 700, 36, 616, 6 }, /* default */
1444}; 1476};
1445 1477
1446static struct dib0090_config dib809x_dib0090_config = { 1478static struct dib0090_config dib809x_dib0090_config = {
1447 .io.pll_bypass = 1, 1479 .io.pll_bypass = 1,
1448 .io.pll_range = 1, 1480 .io.pll_range = 1,
1449 .io.pll_prediv = 1, 1481 .io.pll_prediv = 1,
1450 .io.pll_loopdiv = 20, 1482 .io.pll_loopdiv = 20,
1451 .io.adc_clock_ratio = 8, 1483 .io.adc_clock_ratio = 8,
1452 .io.pll_int_loop_filt = 0, 1484 .io.pll_int_loop_filt = 0,
1453 .io.clock_khz = 12000, 1485 .io.clock_khz = 12000,
1454 .reset = dib80xx_tuner_reset, 1486 .reset = dib80xx_tuner_reset,
1455 .sleep = dib80xx_tuner_sleep, 1487 .sleep = dib80xx_tuner_sleep,
1456 .clkouttobamse = 1, 1488 .clkouttobamse = 1,
1457 .analog_output = 1, 1489 .analog_output = 1,
1458 .i2c_address = DEFAULT_DIB0090_I2C_ADDRESS, 1490 .i2c_address = DEFAULT_DIB0090_I2C_ADDRESS,
1459 .wbd_vhf_offset = 100, 1491 .use_pwm_agc = 1,
1460 .wbd_cband_offset = 450, 1492 .clkoutdrive = 1,
1461 .use_pwm_agc = 1, 1493 .get_adc_power = dib8090_get_adc_power,
1462 .clkoutdrive = 1, 1494 .freq_offset_khz_uhf = -63,
1463 .get_adc_power = dib8090_get_adc_power,
1464 .freq_offset_khz_uhf = 0,
1465 .freq_offset_khz_vhf = -143, 1495 .freq_offset_khz_vhf = -143,
1496 .wbd = dib8090_wbd_table,
1497 .fref_clock_ratio = 6,
1466}; 1498};
1467 1499
1468static int dib8096_set_param_override(struct dvb_frontend *fe, 1500static int dib8096_set_param_override(struct dvb_frontend *fe,
1469 struct dvb_frontend_parameters *fep) 1501 struct dvb_frontend_parameters *fep)
1470{ 1502{
1471 struct dvb_usb_adapter *adap = fe->dvb->priv; 1503 struct dvb_usb_adapter *adap = fe->dvb->priv;
1472 struct dib0700_adapter_state *state = adap->priv; 1504 struct dib0700_adapter_state *state = adap->priv;
1473 u8 band = BAND_OF_FREQUENCY(fep->frequency/1000); 1505 u8 band = BAND_OF_FREQUENCY(fep->frequency/1000);
1474 u16 offset; 1506 u16 target;
1475 int ret = 0; 1507 int ret = 0;
1476 enum frontend_tune_state tune_state = CT_SHUTDOWN; 1508 enum frontend_tune_state tune_state = CT_SHUTDOWN;
1477 u16 ltgain, rf_gain_limit; 1509 u16 ltgain, rf_gain_limit;
1478 1510
1479 ret = state->set_param_save(fe, fep); 1511 ret = state->set_param_save(fe, fep);
1480 if (ret < 0) 1512 if (ret < 0)
1481 return ret; 1513 return ret;
1482 1514
1483 switch (band) { 1515 target = (dib0090_get_wbd_offset(fe) * 8 * 18 / 33 + 1) / 2;
1484 case BAND_VHF: 1516 dib8000_set_wbd_ref(fe, target);
1485 offset = 100; 1517
1486 break; 1518
1487 case BAND_UHF: 1519 if (band == BAND_CBAND) {
1488 offset = 550; 1520 deb_info("tuning in CBAND - soft-AGC startup\n");
1489 break; 1521 dib0090_set_tune_state(fe, CT_AGC_START);
1490 default: 1522 do {
1491 offset = 0; 1523 ret = dib0090_gain_control(fe);
1492 break; 1524 msleep(ret);
1493 } 1525 tune_state = dib0090_get_tune_state(fe);
1494 offset += (dib0090_get_wbd_offset(fe) * 8 * 18 / 33 + 1) / 2; 1526 if (tune_state == CT_AGC_STEP_0)
1495 dib8000_set_wbd_ref(fe, offset); 1527 dib8000_set_gpio(fe, 6, 0, 1);
1496 1528 else if (tune_state == CT_AGC_STEP_1) {
1497 1529 dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
1498 if (band == BAND_CBAND) { 1530 if (rf_gain_limit == 0)
1499 deb_info("tuning in CBAND - soft-AGC startup\n"); 1531 dib8000_set_gpio(fe, 6, 0, 0);
1500 /* TODO specific wbd target for dib0090 - needed for startup ? */ 1532 }
1501 dib0090_set_tune_state(fe, CT_AGC_START); 1533 } while (tune_state < CT_AGC_STOP);
1502 do { 1534 dib0090_pwm_gain_reset(fe);
1503 ret = dib0090_gain_control(fe); 1535 dib8000_pwm_agc_reset(fe);
1504 msleep(ret); 1536 dib8000_set_tune_state(fe, CT_DEMOD_START);
1505 tune_state = dib0090_get_tune_state(fe); 1537 } else {
1506 if (tune_state == CT_AGC_STEP_0) 1538 deb_info("not tuning in CBAND - standard AGC startup\n");
1507 dib8000_set_gpio(fe, 6, 0, 1); 1539 dib0090_pwm_gain_reset(fe);
1508 else if (tune_state == CT_AGC_STEP_1) { 1540 }
1509 dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, &ltgain);
1510 if (rf_gain_limit == 0)
1511 dib8000_set_gpio(fe, 6, 0, 0);
1512 }
1513 } while (tune_state < CT_AGC_STOP);
1514 dib0090_pwm_gain_reset(fe);
1515 dib8000_pwm_agc_reset(fe);
1516 dib8000_set_tune_state(fe, CT_DEMOD_START);
1517 } else {
1518 deb_info("not tuning in CBAND - standard AGC startup\n");
1519 dib0090_pwm_gain_reset(fe);
1520 }
1521 1541
1522 return 0; 1542 return 0;
1523} 1543}
1524 1544
1525static int dib809x_tuner_attach(struct dvb_usb_adapter *adap) 1545static int dib809x_tuner_attach(struct dvb_usb_adapter *adap)
1526{ 1546{
1527 struct dib0700_adapter_state *st = adap->priv; 1547 struct dib0700_adapter_state *st = adap->priv;
1528 struct i2c_adapter *tun_i2c = dib8000_get_i2c_master(adap->fe, DIBX000_I2C_INTERFACE_TUNER, 1); 1548 struct i2c_adapter *tun_i2c = dib8000_get_i2c_master(adap->fe, DIBX000_I2C_INTERFACE_TUNER, 1);
1529 1549
1530 if (dvb_attach(dib0090_register, adap->fe, tun_i2c, &dib809x_dib0090_config) == NULL) 1550 if (dvb_attach(dib0090_register, adap->fe, tun_i2c, &dib809x_dib0090_config) == NULL)
1531 return -ENODEV; 1551 return -ENODEV;
1532 1552
1533 st->set_param_save = adap->fe->ops.tuner_ops.set_params; 1553 st->set_param_save = adap->fe->ops.tuner_ops.set_params;
1534 adap->fe->ops.tuner_ops.set_params = dib8096_set_param_override; 1554 adap->fe->ops.tuner_ops.set_params = dib8096_set_param_override;
1535 return 0; 1555 return 0;
1536} 1556}
1537 1557
1538static int stk809x_frontend_attach(struct dvb_usb_adapter *adap) 1558static int stk809x_frontend_attach(struct dvb_usb_adapter *adap)
@@ -1554,11 +1574,931 @@ static int stk809x_frontend_attach(struct dvb_usb_adapter *adap)
1554 1574
1555 dib8000_i2c_enumeration(&adap->dev->i2c_adap, 1, 18, 0x80); 1575 dib8000_i2c_enumeration(&adap->dev->i2c_adap, 1, 18, 0x80);
1556 1576
1557 adap->fe = dvb_attach(dib8000_attach, &adap->dev->i2c_adap, 0x80, &dib809x_dib8000_config); 1577 adap->fe = dvb_attach(dib8000_attach, &adap->dev->i2c_adap, 0x80, &dib809x_dib8000_config[0]);
1578
1579 return adap->fe == NULL ? -ENODEV : 0;
1580}
1581
1582static int nim8096md_tuner_attach(struct dvb_usb_adapter *adap)
1583{
1584 struct dib0700_adapter_state *st = adap->priv;
1585 struct i2c_adapter *tun_i2c;
1586 struct dvb_frontend *fe_slave = dib8000_get_slave_frontend(adap->fe, 1);
1587
1588 if (fe_slave) {
1589 tun_i2c = dib8000_get_i2c_master(fe_slave, DIBX000_I2C_INTERFACE_TUNER, 1);
1590 if (dvb_attach(dib0090_register, fe_slave, tun_i2c, &dib809x_dib0090_config) == NULL)
1591 return -ENODEV;
1592 fe_slave->dvb = adap->fe->dvb;
1593 fe_slave->ops.tuner_ops.set_params = dib8096_set_param_override;
1594 }
1595 tun_i2c = dib8000_get_i2c_master(adap->fe, DIBX000_I2C_INTERFACE_TUNER, 1);
1596 if (dvb_attach(dib0090_register, adap->fe, tun_i2c, &dib809x_dib0090_config) == NULL)
1597 return -ENODEV;
1598
1599 st->set_param_save = adap->fe->ops.tuner_ops.set_params;
1600 adap->fe->ops.tuner_ops.set_params = dib8096_set_param_override;
1601
1602 return 0;
1603}
1604
1605static int nim8096md_frontend_attach(struct dvb_usb_adapter *adap)
1606{
1607 struct dvb_frontend *fe_slave;
1608
1609 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 0);
1610 msleep(20);
1611 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1612 msleep(1000);
1613 dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
1614 dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1615 dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1616
1617 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1618
1619 dib0700_ctrl_clock(adap->dev, 72, 1);
1620
1621 msleep(20);
1622 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1623 msleep(20);
1624 dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1625
1626 dib8000_i2c_enumeration(&adap->dev->i2c_adap, 2, 18, 0x80);
1627
1628 adap->fe = dvb_attach(dib8000_attach, &adap->dev->i2c_adap, 0x80, &dib809x_dib8000_config[0]);
1629 if (adap->fe == NULL)
1630 return -ENODEV;
1631
1632 fe_slave = dvb_attach(dib8000_attach, &adap->dev->i2c_adap, 0x82, &dib809x_dib8000_config[1]);
1633 dib8000_set_slave_frontend(adap->fe, fe_slave);
1634
1635 return fe_slave == NULL ? -ENODEV : 0;
1636}
1637
1638/* STK9090M */
1639static int dib90x0_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff)
1640{
1641 return dib9000_fw_pid_filter(adapter->fe, index, pid, onoff);
1642}
1643
1644static int dib90x0_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
1645{
1646 return dib9000_fw_pid_filter_ctrl(adapter->fe, onoff);
1647}
1648
1649static int dib90x0_tuner_reset(struct dvb_frontend *fe, int onoff)
1650{
1651 return dib9000_set_gpio(fe, 5, 0, !onoff);
1652}
1653
1654static int dib90x0_tuner_sleep(struct dvb_frontend *fe, int onoff)
1655{
1656 return dib9000_set_gpio(fe, 0, 0, onoff);
1657}
1658
1659static int dib01x0_pmu_update(struct i2c_adapter *i2c, u16 *data, u8 len)
1660{
1661 u8 wb[4] = { 0xc >> 8, 0xc & 0xff, 0, 0 };
1662 u8 rb[2];
1663 struct i2c_msg msg[2] = {
1664 {.addr = 0x1e >> 1, .flags = 0, .buf = wb, .len = 2},
1665 {.addr = 0x1e >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
1666 };
1667 u8 index_data;
1668
1669 dibx000_i2c_set_speed(i2c, 250);
1670
1671 if (i2c_transfer(i2c, msg, 2) != 2)
1672 return -EIO;
1673
1674 switch (rb[0] << 8 | rb[1]) {
1675 case 0:
1676 deb_info("Found DiB0170 rev1: This version of DiB0170 is not supported any longer.\n");
1677 return -EIO;
1678 case 1:
1679 deb_info("Found DiB0170 rev2");
1680 break;
1681 case 2:
1682 deb_info("Found DiB0190 rev2");
1683 break;
1684 default:
1685 deb_info("DiB01x0 not found");
1686 return -EIO;
1687 }
1688
1689 for (index_data = 0; index_data < len; index_data += 2) {
1690 wb[2] = (data[index_data + 1] >> 8) & 0xff;
1691 wb[3] = (data[index_data + 1]) & 0xff;
1692
1693 if (data[index_data] == 0) {
1694 wb[0] = (data[index_data] >> 8) & 0xff;
1695 wb[1] = (data[index_data]) & 0xff;
1696 msg[0].len = 2;
1697 if (i2c_transfer(i2c, msg, 2) != 2)
1698 return -EIO;
1699 wb[2] |= rb[0];
1700 wb[3] |= rb[1] & ~(3 << 4);
1701 }
1702
1703 wb[0] = (data[index_data] >> 8)&0xff;
1704 wb[1] = (data[index_data])&0xff;
1705 msg[0].len = 4;
1706 if (i2c_transfer(i2c, &msg[0], 1) != 1)
1707 return -EIO;
1708 }
1709 return 0;
1710}
1711
1712static struct dib9000_config stk9090m_config = {
1713 .output_mpeg2_in_188_bytes = 1,
1714 .output_mode = OUTMODE_MPEG2_FIFO,
1715 .vcxo_timer = 279620,
1716 .timing_frequency = 20452225,
1717 .demod_clock_khz = 60000,
1718 .xtal_clock_khz = 30000,
1719 .if_drives = (0 << 15) | (1 << 13) | (0 << 12) | (3 << 10) | (0 << 9) | (1 << 7) | (0 << 6) | (0 << 4) | (1 << 3) | (1 << 1) | (0),
1720 .subband = {
1721 2,
1722 {
1723 { 240, { BOARD_GPIO_COMPONENT_DEMOD, BOARD_GPIO_FUNCTION_SUBBAND_GPIO, 0x0008, 0x0000, 0x0008 } }, /* GPIO 3 to 1 for VHF */
1724 { 890, { BOARD_GPIO_COMPONENT_DEMOD, BOARD_GPIO_FUNCTION_SUBBAND_GPIO, 0x0008, 0x0000, 0x0000 } }, /* GPIO 3 to 0 for UHF */
1725 { 0 },
1726 },
1727 },
1728 .gpio_function = {
1729 { .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_ON, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = (0x10 & ~0x1) | 0x20 },
1730 { .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_OFF, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = 0 | 0x21 },
1731 },
1732};
1733
1734static struct dib9000_config nim9090md_config[2] = {
1735 {
1736 .output_mpeg2_in_188_bytes = 1,
1737 .output_mode = OUTMODE_MPEG2_FIFO,
1738 .vcxo_timer = 279620,
1739 .timing_frequency = 20452225,
1740 .demod_clock_khz = 60000,
1741 .xtal_clock_khz = 30000,
1742 .if_drives = (0 << 15) | (1 << 13) | (0 << 12) | (3 << 10) | (0 << 9) | (1 << 7) | (0 << 6) | (0 << 4) | (1 << 3) | (1 << 1) | (0),
1743 }, {
1744 .output_mpeg2_in_188_bytes = 1,
1745 .output_mode = OUTMODE_DIVERSITY,
1746 .vcxo_timer = 279620,
1747 .timing_frequency = 20452225,
1748 .demod_clock_khz = 60000,
1749 .xtal_clock_khz = 30000,
1750 .if_drives = (0 << 15) | (1 << 13) | (0 << 12) | (3 << 10) | (0 << 9) | (1 << 7) | (0 << 6) | (0 << 4) | (1 << 3) | (1 << 1) | (0),
1751 .subband = {
1752 2,
1753 {
1754 { 240, { BOARD_GPIO_COMPONENT_DEMOD, BOARD_GPIO_FUNCTION_SUBBAND_GPIO, 0x0006, 0x0000, 0x0006 } }, /* GPIO 1 and 2 to 1 for VHF */
1755 { 890, { BOARD_GPIO_COMPONENT_DEMOD, BOARD_GPIO_FUNCTION_SUBBAND_GPIO, 0x0006, 0x0000, 0x0000 } }, /* GPIO 1 and 2 to 0 for UHF */
1756 { 0 },
1757 },
1758 },
1759 .gpio_function = {
1760 { .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_ON, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = (0x10 & ~0x1) | 0x20 },
1761 { .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_OFF, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = 0 | 0x21 },
1762 },
1763 }
1764};
1765
1766static struct dib0090_config dib9090_dib0090_config = {
1767 .io.pll_bypass = 0,
1768 .io.pll_range = 1,
1769 .io.pll_prediv = 1,
1770 .io.pll_loopdiv = 8,
1771 .io.adc_clock_ratio = 8,
1772 .io.pll_int_loop_filt = 0,
1773 .io.clock_khz = 30000,
1774 .reset = dib90x0_tuner_reset,
1775 .sleep = dib90x0_tuner_sleep,
1776 .clkouttobamse = 0,
1777 .analog_output = 0,
1778 .use_pwm_agc = 0,
1779 .clkoutdrive = 0,
1780 .freq_offset_khz_uhf = 0,
1781 .freq_offset_khz_vhf = 0,
1782};
1783
1784static struct dib0090_config nim9090md_dib0090_config[2] = {
1785 {
1786 .io.pll_bypass = 0,
1787 .io.pll_range = 1,
1788 .io.pll_prediv = 1,
1789 .io.pll_loopdiv = 8,
1790 .io.adc_clock_ratio = 8,
1791 .io.pll_int_loop_filt = 0,
1792 .io.clock_khz = 30000,
1793 .reset = dib90x0_tuner_reset,
1794 .sleep = dib90x0_tuner_sleep,
1795 .clkouttobamse = 1,
1796 .analog_output = 0,
1797 .use_pwm_agc = 0,
1798 .clkoutdrive = 0,
1799 .freq_offset_khz_uhf = 0,
1800 .freq_offset_khz_vhf = 0,
1801 }, {
1802 .io.pll_bypass = 0,
1803 .io.pll_range = 1,
1804 .io.pll_prediv = 1,
1805 .io.pll_loopdiv = 8,
1806 .io.adc_clock_ratio = 8,
1807 .io.pll_int_loop_filt = 0,
1808 .io.clock_khz = 30000,
1809 .reset = dib90x0_tuner_reset,
1810 .sleep = dib90x0_tuner_sleep,
1811 .clkouttobamse = 0,
1812 .analog_output = 0,
1813 .use_pwm_agc = 0,
1814 .clkoutdrive = 0,
1815 .freq_offset_khz_uhf = 0,
1816 .freq_offset_khz_vhf = 0,
1817 }
1818};
1819
1820
1821static int stk9090m_frontend_attach(struct dvb_usb_adapter *adap)
1822{
1823 struct dib0700_adapter_state *state = adap->priv;
1824 struct dib0700_state *st = adap->dev->priv;
1825 u32 fw_version;
1826
1827 /* Make use of the new i2c functions from FW 1.20 */
1828 dib0700_get_version(adap->dev, NULL, NULL, &fw_version, NULL);
1829 if (fw_version >= 0x10200)
1830 st->fw_use_new_i2c_api = 1;
1831 dib0700_set_i2c_speed(adap->dev, 340);
1832
1833 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1834 msleep(20);
1835 dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
1836 dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1837 dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1838 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1839
1840 dib0700_ctrl_clock(adap->dev, 72, 1);
1841
1842 msleep(20);
1843 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1844 msleep(20);
1845 dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1846
1847 dib9000_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, 0x80);
1848
1849 if (request_firmware(&state->frontend_firmware, "dib9090.fw", &adap->dev->udev->dev)) {
1850 deb_info("%s: Upload failed. (file not found?)\n", __func__);
1851 return -ENODEV;
1852 } else {
1853 deb_info("%s: firmware read %Zu bytes.\n", __func__, state->frontend_firmware->size);
1854 }
1855 stk9090m_config.microcode_B_fe_size = state->frontend_firmware->size;
1856 stk9090m_config.microcode_B_fe_buffer = state->frontend_firmware->data;
1857
1858 adap->fe = dvb_attach(dib9000_attach, &adap->dev->i2c_adap, 0x80, &stk9090m_config);
1859
1860 return adap->fe == NULL ? -ENODEV : 0;
1861}
1862
1863static int dib9090_tuner_attach(struct dvb_usb_adapter *adap)
1864{
1865 struct dib0700_adapter_state *state = adap->priv;
1866 struct i2c_adapter *i2c = dib9000_get_tuner_interface(adap->fe);
1867 u16 data_dib190[10] = {
1868 1, 0x1374,
1869 2, 0x01a2,
1870 7, 0x0020,
1871 0, 0x00ef,
1872 8, 0x0486,
1873 };
1874
1875 if (dvb_attach(dib0090_fw_register, adap->fe, i2c, &dib9090_dib0090_config) == NULL)
1876 return -ENODEV;
1877 i2c = dib9000_get_i2c_master(adap->fe, DIBX000_I2C_INTERFACE_GPIO_1_2, 0);
1878 if (dib01x0_pmu_update(i2c, data_dib190, 10) != 0)
1879 return -ENODEV;
1880 dib0700_set_i2c_speed(adap->dev, 2000);
1881 if (dib9000_firmware_post_pll_init(adap->fe) < 0)
1882 return -ENODEV;
1883 release_firmware(state->frontend_firmware);
1884 return 0;
1885}
1886
1887static int nim9090md_frontend_attach(struct dvb_usb_adapter *adap)
1888{
1889 struct dib0700_adapter_state *state = adap->priv;
1890 struct dib0700_state *st = adap->dev->priv;
1891 struct i2c_adapter *i2c;
1892 struct dvb_frontend *fe_slave;
1893 u32 fw_version;
1894
1895 /* Make use of the new i2c functions from FW 1.20 */
1896 dib0700_get_version(adap->dev, NULL, NULL, &fw_version, NULL);
1897 if (fw_version >= 0x10200)
1898 st->fw_use_new_i2c_api = 1;
1899 dib0700_set_i2c_speed(adap->dev, 340);
1900
1901 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
1902 msleep(20);
1903 dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
1904 dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
1905 dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
1906 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
1907
1908 dib0700_ctrl_clock(adap->dev, 72, 1);
1909
1910 msleep(20);
1911 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
1912 msleep(20);
1913 dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
1914
1915 if (request_firmware(&state->frontend_firmware, "dib9090.fw", &adap->dev->udev->dev)) {
1916 deb_info("%s: Upload failed. (file not found?)\n", __func__);
1917 return -EIO;
1918 } else {
1919 deb_info("%s: firmware read %Zu bytes.\n", __func__, state->frontend_firmware->size);
1920 }
1921 nim9090md_config[0].microcode_B_fe_size = state->frontend_firmware->size;
1922 nim9090md_config[0].microcode_B_fe_buffer = state->frontend_firmware->data;
1923 nim9090md_config[1].microcode_B_fe_size = state->frontend_firmware->size;
1924 nim9090md_config[1].microcode_B_fe_buffer = state->frontend_firmware->data;
1925
1926 dib9000_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x20, 0x80);
1927 adap->fe = dvb_attach(dib9000_attach, &adap->dev->i2c_adap, 0x80, &nim9090md_config[0]);
1928
1929 if (adap->fe == NULL)
1930 return -ENODEV;
1931
1932 i2c = dib9000_get_i2c_master(adap->fe, DIBX000_I2C_INTERFACE_GPIO_3_4, 0);
1933 dib9000_i2c_enumeration(i2c, 1, 0x12, 0x82);
1934
1935 fe_slave = dvb_attach(dib9000_attach, i2c, 0x82, &nim9090md_config[1]);
1936 dib9000_set_slave_frontend(adap->fe, fe_slave);
1937
1938 return fe_slave == NULL ? -ENODEV : 0;
1939}
1940
1941static int nim9090md_tuner_attach(struct dvb_usb_adapter *adap)
1942{
1943 struct dib0700_adapter_state *state = adap->priv;
1944 struct i2c_adapter *i2c;
1945 struct dvb_frontend *fe_slave;
1946 u16 data_dib190[10] = {
1947 1, 0x5374,
1948 2, 0x01ae,
1949 7, 0x0020,
1950 0, 0x00ef,
1951 8, 0x0406,
1952 };
1953 i2c = dib9000_get_tuner_interface(adap->fe);
1954 if (dvb_attach(dib0090_fw_register, adap->fe, i2c, &nim9090md_dib0090_config[0]) == NULL)
1955 return -ENODEV;
1956 i2c = dib9000_get_i2c_master(adap->fe, DIBX000_I2C_INTERFACE_GPIO_1_2, 0);
1957 if (dib01x0_pmu_update(i2c, data_dib190, 10) < 0)
1958 return -ENODEV;
1959 dib0700_set_i2c_speed(adap->dev, 2000);
1960 if (dib9000_firmware_post_pll_init(adap->fe) < 0)
1961 return -ENODEV;
1962
1963 fe_slave = dib9000_get_slave_frontend(adap->fe, 1);
1964 if (fe_slave != NULL) {
1965 i2c = dib9000_get_component_bus_interface(adap->fe);
1966 dib9000_set_i2c_adapter(fe_slave, i2c);
1967
1968 i2c = dib9000_get_tuner_interface(fe_slave);
1969 if (dvb_attach(dib0090_fw_register, fe_slave, i2c, &nim9090md_dib0090_config[1]) == NULL)
1970 return -ENODEV;
1971 fe_slave->dvb = adap->fe->dvb;
1972 dib9000_fw_set_component_bus_speed(adap->fe, 2000);
1973 if (dib9000_firmware_post_pll_init(fe_slave) < 0)
1974 return -ENODEV;
1975 }
1976 release_firmware(state->frontend_firmware);
1977
1978 return 0;
1979}
1980
1981/* NIM7090 */
1982struct dib7090p_best_adc {
1983 u32 timf;
1984 u32 pll_loopdiv;
1985 u32 pll_prediv;
1986};
1987
1988static int dib7090p_get_best_sampling(struct dvb_frontend *fe , struct dib7090p_best_adc *adc)
1989{
1990 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;
1991
1992 u16 xtal = 12000;
1993 u32 fcp_min = 1900; /* PLL Minimum Frequency comparator KHz */
1994 u32 fcp_max = 20000; /* PLL Maximum Frequency comparator KHz */
1995 u32 fdem_max = 76000;
1996 u32 fdem_min = 69500;
1997 u32 fcp = 0, fs = 0, fdem = 0;
1998 u32 harmonic_id = 0;
1999
2000 adc->pll_loopdiv = loopdiv;
2001 adc->pll_prediv = prediv;
2002 adc->timf = 0;
2003
2004 deb_info("bandwidth = %d fdem_min =%d", fe->dtv_property_cache.bandwidth_hz, fdem_min);
2005
2006 /* Find Min and Max prediv */
2007 while ((xtal/max_prediv) >= fcp_min)
2008 max_prediv++;
2009
2010 max_prediv--;
2011 min_prediv = max_prediv;
2012 while ((xtal/min_prediv) <= fcp_max) {
2013 min_prediv--;
2014 if (min_prediv == 1)
2015 break;
2016 }
2017 deb_info("MIN prediv = %d : MAX prediv = %d", min_prediv, max_prediv);
2018
2019 min_prediv = 2;
2020
2021 for (prediv = min_prediv ; prediv < max_prediv; prediv++) {
2022 fcp = xtal / prediv;
2023 if (fcp > fcp_min && fcp < fcp_max) {
2024 for (loopdiv = 1 ; loopdiv < 64 ; loopdiv++) {
2025 fdem = ((xtal/prediv) * loopdiv);
2026 fs = fdem / 4;
2027 /* test min/max system restrictions */
2028
2029 if ((fdem >= fdem_min) && (fdem <= fdem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz/1000)) {
2030 spur = 0;
2031 /* test fs harmonics positions */
2032 for (harmonic_id = (fe->dtv_property_cache.frequency / (1000*fs)) ; harmonic_id <= ((fe->dtv_property_cache.frequency / (1000*fs))+1) ; harmonic_id++) {
2033 if (((fs*harmonic_id) >= ((fe->dtv_property_cache.frequency/1000) - (fe->dtv_property_cache.bandwidth_hz/2000))) && ((fs*harmonic_id) <= ((fe->dtv_property_cache.frequency/1000) + (fe->dtv_property_cache.bandwidth_hz/2000)))) {
2034 spur = 1;
2035 break;
2036 }
2037 }
2038
2039 if (!spur) {
2040 adc->pll_loopdiv = loopdiv;
2041 adc->pll_prediv = prediv;
2042 adc->timf = 2396745143UL/fdem*(1 << 9);
2043 adc->timf += ((2396745143UL%fdem) << 9)/fdem;
2044 deb_info("loopdiv=%i prediv=%i timf=%i", loopdiv, prediv, adc->timf);
2045 break;
2046 }
2047 }
2048 }
2049 }
2050 if (!spur)
2051 break;
2052 }
2053
2054
2055 if (adc->pll_loopdiv == 0 && adc->pll_prediv == 0)
2056 return -EINVAL;
2057 else
2058 return 0;
2059}
2060
2061static int dib7090_agc_startup(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
2062{
2063 struct dvb_usb_adapter *adap = fe->dvb->priv;
2064 struct dib0700_adapter_state *state = adap->priv;
2065 struct dibx000_bandwidth_config pll;
2066 u16 target;
2067 struct dib7090p_best_adc adc;
2068 int ret;
2069
2070 ret = state->set_param_save(fe, fep);
2071 if (ret < 0)
2072 return ret;
2073
2074 memset(&pll, 0, sizeof(struct dibx000_bandwidth_config));
2075 dib0090_pwm_gain_reset(fe);
2076 target = (dib0090_get_wbd_offset(fe) * 8 + 1) / 2;
2077 dib7000p_set_wbd_ref(fe, target);
2078
2079 if (dib7090p_get_best_sampling(fe, &adc) == 0) {
2080 pll.pll_ratio = adc.pll_loopdiv;
2081 pll.pll_prediv = adc.pll_prediv;
2082
2083 dib7000p_update_pll(fe, &pll);
2084 dib7000p_ctrl_timf(fe, DEMOD_TIMF_SET, adc.timf);
2085 }
2086 return 0;
2087}
2088
2089static struct dib0090_wbd_slope dib7090_wbd_table[] = {
2090 { 380, 81, 850, 64, 540, 4},
2091 { 860, 51, 866, 21, 375, 4},
2092 {1700, 0, 250, 0, 100, 6},
2093 {2600, 0, 250, 0, 100, 6},
2094 { 0xFFFF, 0, 0, 0, 0, 0},
2095};
2096
2097struct dibx000_agc_config dib7090_agc_config[2] = {
2098 {
2099 .band_caps = BAND_UHF,
2100 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
2101 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
2102 .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
2103
2104 .inv_gain = 687,
2105 .time_stabiliz = 10,
2106
2107 .alpha_level = 0,
2108 .thlock = 118,
2109
2110 .wbd_inv = 0,
2111 .wbd_ref = 1200,
2112 .wbd_sel = 3,
2113 .wbd_alpha = 5,
2114
2115 .agc1_max = 65535,
2116 .agc1_min = 0,
2117
2118 .agc2_max = 65535,
2119 .agc2_min = 0,
2120
2121 .agc1_pt1 = 0,
2122 .agc1_pt2 = 32,
2123 .agc1_pt3 = 114,
2124 .agc1_slope1 = 143,
2125 .agc1_slope2 = 144,
2126 .agc2_pt1 = 114,
2127 .agc2_pt2 = 227,
2128 .agc2_slope1 = 116,
2129 .agc2_slope2 = 117,
2130
2131 .alpha_mant = 18,
2132 .alpha_exp = 0,
2133 .beta_mant = 20,
2134 .beta_exp = 59,
2135
2136 .perform_agc_softsplit = 0,
2137 } , {
2138 .band_caps = BAND_FM | BAND_VHF | BAND_CBAND,
2139 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
2140 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */
2141 .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
2142
2143 .inv_gain = 732,
2144 .time_stabiliz = 10,
2145
2146 .alpha_level = 0,
2147 .thlock = 118,
2148
2149 .wbd_inv = 0,
2150 .wbd_ref = 1200,
2151 .wbd_sel = 3,
2152 .wbd_alpha = 5,
2153
2154 .agc1_max = 65535,
2155 .agc1_min = 0,
2156
2157 .agc2_max = 65535,
2158 .agc2_min = 0,
2159
2160 .agc1_pt1 = 0,
2161 .agc1_pt2 = 0,
2162 .agc1_pt3 = 98,
2163 .agc1_slope1 = 0,
2164 .agc1_slope2 = 167,
2165 .agc1_pt1 = 98,
2166 .agc2_pt2 = 255,
2167 .agc2_slope1 = 104,
2168 .agc2_slope2 = 0,
2169
2170 .alpha_mant = 18,
2171 .alpha_exp = 0,
2172 .beta_mant = 20,
2173 .beta_exp = 59,
2174
2175 .perform_agc_softsplit = 0,
2176 }
2177};
2178
2179static struct dibx000_bandwidth_config dib7090_clock_config_12_mhz = {
2180 60000, 15000,
2181 1, 5, 0, 0, 0,
2182 0, 0, 1, 1, 2,
2183 (3 << 14) | (1 << 12) | (524 << 0),
2184 (0 << 25) | 0,
2185 20452225,
2186 15000000,
2187};
2188
2189static struct dib7000p_config nim7090_dib7000p_config = {
2190 .output_mpeg2_in_188_bytes = 1,
2191 .hostbus_diversity = 1,
2192 .tuner_is_baseband = 1,
2193 .update_lna = NULL,
2194
2195 .agc_config_count = 2,
2196 .agc = dib7090_agc_config,
2197
2198 .bw = &dib7090_clock_config_12_mhz,
2199
2200 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
2201 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
2202 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
2203
2204 .pwm_freq_div = 0,
2205
2206 .agc_control = dib7090_agc_restart,
2207
2208 .spur_protect = 0,
2209 .disable_sample_and_hold = 0,
2210 .enable_current_mirror = 0,
2211 .diversity_delay = 0,
2212
2213 .output_mode = OUTMODE_MPEG2_FIFO,
2214 .enMpegOutput = 1,
2215};
2216
2217static struct dib7000p_config tfe7090pvr_dib7000p_config[2] = {
2218 {
2219 .output_mpeg2_in_188_bytes = 1,
2220 .hostbus_diversity = 1,
2221 .tuner_is_baseband = 1,
2222 .update_lna = NULL,
2223
2224 .agc_config_count = 2,
2225 .agc = dib7090_agc_config,
2226
2227 .bw = &dib7090_clock_config_12_mhz,
2228
2229 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
2230 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
2231 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
2232
2233 .pwm_freq_div = 0,
2234
2235 .agc_control = dib7090_agc_restart,
2236
2237 .spur_protect = 0,
2238 .disable_sample_and_hold = 0,
2239 .enable_current_mirror = 0,
2240 .diversity_delay = 0,
2241
2242 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,
2243 .default_i2c_addr = 0x90,
2244 .enMpegOutput = 1,
2245 }, {
2246 .output_mpeg2_in_188_bytes = 1,
2247 .hostbus_diversity = 1,
2248 .tuner_is_baseband = 1,
2249 .update_lna = NULL,
2250
2251 .agc_config_count = 2,
2252 .agc = dib7090_agc_config,
2253
2254 .bw = &dib7090_clock_config_12_mhz,
2255
2256 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
2257 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
2258 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
2259
2260 .pwm_freq_div = 0,
2261
2262 .agc_control = dib7090_agc_restart,
2263
2264 .spur_protect = 0,
2265 .disable_sample_and_hold = 0,
2266 .enable_current_mirror = 0,
2267 .diversity_delay = 0,
2268
2269 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,
2270 .default_i2c_addr = 0x92,
2271 .enMpegOutput = 0,
2272 }
2273};
2274
2275static const struct dib0090_config nim7090_dib0090_config = {
2276 .io.clock_khz = 12000,
2277 .io.pll_bypass = 0,
2278 .io.pll_range = 0,
2279 .io.pll_prediv = 3,
2280 .io.pll_loopdiv = 6,
2281 .io.adc_clock_ratio = 0,
2282 .io.pll_int_loop_filt = 0,
2283 .reset = dib7090_tuner_sleep,
2284 .sleep = dib7090_tuner_sleep,
2285
2286 .freq_offset_khz_uhf = 0,
2287 .freq_offset_khz_vhf = 0,
2288
2289 .get_adc_power = dib7090_get_adc_power,
2290
2291 .clkouttobamse = 1,
2292 .analog_output = 0,
2293
2294 .wbd_vhf_offset = 0,
2295 .wbd_cband_offset = 0,
2296 .use_pwm_agc = 1,
2297 .clkoutdrive = 0,
2298
2299 .fref_clock_ratio = 0,
2300
2301 .wbd = dib7090_wbd_table,
2302
2303 .ls_cfg_pad_drv = 0,
2304 .data_tx_drv = 0,
2305 .low_if = NULL,
2306 .in_soc = 1,
2307};
2308
2309static const struct dib0090_config tfe7090pvr_dib0090_config[2] = {
2310 {
2311 .io.clock_khz = 12000,
2312 .io.pll_bypass = 0,
2313 .io.pll_range = 0,
2314 .io.pll_prediv = 3,
2315 .io.pll_loopdiv = 6,
2316 .io.adc_clock_ratio = 0,
2317 .io.pll_int_loop_filt = 0,
2318 .reset = dib7090_tuner_sleep,
2319 .sleep = dib7090_tuner_sleep,
2320
2321 .freq_offset_khz_uhf = 50,
2322 .freq_offset_khz_vhf = 70,
2323
2324 .get_adc_power = dib7090_get_adc_power,
2325
2326 .clkouttobamse = 1,
2327 .analog_output = 0,
2328
2329 .wbd_vhf_offset = 0,
2330 .wbd_cband_offset = 0,
2331 .use_pwm_agc = 1,
2332 .clkoutdrive = 0,
2333
2334 .fref_clock_ratio = 0,
2335
2336 .wbd = dib7090_wbd_table,
2337
2338 .ls_cfg_pad_drv = 0,
2339 .data_tx_drv = 0,
2340 .low_if = NULL,
2341 .in_soc = 1,
2342 }, {
2343 .io.clock_khz = 12000,
2344 .io.pll_bypass = 0,
2345 .io.pll_range = 0,
2346 .io.pll_prediv = 3,
2347 .io.pll_loopdiv = 6,
2348 .io.adc_clock_ratio = 0,
2349 .io.pll_int_loop_filt = 0,
2350 .reset = dib7090_tuner_sleep,
2351 .sleep = dib7090_tuner_sleep,
2352
2353 .freq_offset_khz_uhf = -50,
2354 .freq_offset_khz_vhf = -70,
2355
2356 .get_adc_power = dib7090_get_adc_power,
2357
2358 .clkouttobamse = 1,
2359 .analog_output = 0,
2360
2361 .wbd_vhf_offset = 0,
2362 .wbd_cband_offset = 0,
2363 .use_pwm_agc = 1,
2364 .clkoutdrive = 0,
2365
2366 .fref_clock_ratio = 0,
2367
2368 .wbd = dib7090_wbd_table,
2369
2370 .ls_cfg_pad_drv = 0,
2371 .data_tx_drv = 0,
2372 .low_if = NULL,
2373 .in_soc = 1,
2374 }
2375};
2376
2377static int nim7090_frontend_attach(struct dvb_usb_adapter *adap)
2378{
2379 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
2380 msleep(20);
2381 dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
2382 dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
2383 dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
2384 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
2385
2386 msleep(20);
2387 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
2388 msleep(20);
2389 dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
2390
2391 if (dib7000p_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, &nim7090_dib7000p_config) != 0) {
2392 err("%s: dib7000p_i2c_enumeration failed. Cannot continue\n", __func__);
2393 return -ENODEV;
2394 }
2395 adap->fe = dvb_attach(dib7000p_attach, &adap->dev->i2c_adap, 0x80, &nim7090_dib7000p_config);
1558 2396
1559 return adap->fe == NULL ? -ENODEV : 0; 2397 return adap->fe == NULL ? -ENODEV : 0;
1560} 2398}
1561 2399
2400static int nim7090_tuner_attach(struct dvb_usb_adapter *adap)
2401{
2402 struct dib0700_adapter_state *st = adap->priv;
2403 struct i2c_adapter *tun_i2c = dib7090_get_i2c_tuner(adap->fe);
2404
2405 if (dvb_attach(dib0090_register, adap->fe, tun_i2c, &nim7090_dib0090_config) == NULL)
2406 return -ENODEV;
2407
2408 dib7000p_set_gpio(adap->fe, 8, 0, 1);
2409
2410 st->set_param_save = adap->fe->ops.tuner_ops.set_params;
2411 adap->fe->ops.tuner_ops.set_params = dib7090_agc_startup;
2412 return 0;
2413}
2414
2415static int tfe7090pvr_frontend0_attach(struct dvb_usb_adapter *adap)
2416{
2417 struct dib0700_state *st = adap->dev->priv;
2418
2419 /* The TFE7090 requires the dib0700 to not be in master mode */
2420 st->disable_streaming_master_mode = 1;
2421
2422 dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
2423 msleep(20);
2424 dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
2425 dib0700_set_gpio(adap->dev, GPIO4, GPIO_OUT, 1);
2426 dib0700_set_gpio(adap->dev, GPIO7, GPIO_OUT, 1);
2427 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 0);
2428
2429 msleep(20);
2430 dib0700_set_gpio(adap->dev, GPIO10, GPIO_OUT, 1);
2431 msleep(20);
2432 dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1);
2433
2434 /* initialize IC 0 */
2435 if (dib7000p_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x20, &tfe7090pvr_dib7000p_config[0]) != 0) {
2436 err("%s: dib7000p_i2c_enumeration failed. Cannot continue\n", __func__);
2437 return -ENODEV;
2438 }
2439
2440 dib0700_set_i2c_speed(adap->dev, 340);
2441 adap->fe = dvb_attach(dib7000p_attach, &adap->dev->i2c_adap, 0x90, &tfe7090pvr_dib7000p_config[0]);
2442
2443 dib7090_slave_reset(adap->fe);
2444
2445 if (adap->fe == NULL)
2446 return -ENODEV;
2447
2448 return 0;
2449}
2450
2451static int tfe7090pvr_frontend1_attach(struct dvb_usb_adapter *adap)
2452{
2453 struct i2c_adapter *i2c;
2454
2455 if (adap->dev->adapter[0].fe == NULL) {
2456 err("the master dib7090 has to be initialized first");
2457 return -ENODEV; /* the master device has not been initialized */
2458 }
2459
2460 i2c = dib7000p_get_i2c_master(adap->dev->adapter[0].fe, DIBX000_I2C_INTERFACE_GPIO_6_7, 1);
2461 if (dib7000p_i2c_enumeration(i2c, 1, 0x10, &tfe7090pvr_dib7000p_config[1]) != 0) {
2462 err("%s: dib7000p_i2c_enumeration failed. Cannot continue\n", __func__);
2463 return -ENODEV;
2464 }
2465
2466 adap->fe = dvb_attach(dib7000p_attach, i2c, 0x92, &tfe7090pvr_dib7000p_config[1]);
2467 dib0700_set_i2c_speed(adap->dev, 200);
2468
2469 return adap->fe == NULL ? -ENODEV : 0;
2470}
2471
2472static int tfe7090pvr_tuner0_attach(struct dvb_usb_adapter *adap)
2473{
2474 struct dib0700_adapter_state *st = adap->priv;
2475 struct i2c_adapter *tun_i2c = dib7090_get_i2c_tuner(adap->fe);
2476
2477 if (dvb_attach(dib0090_register, adap->fe, tun_i2c, &tfe7090pvr_dib0090_config[0]) == NULL)
2478 return -ENODEV;
2479
2480 dib7000p_set_gpio(adap->fe, 8, 0, 1);
2481
2482 st->set_param_save = adap->fe->ops.tuner_ops.set_params;
2483 adap->fe->ops.tuner_ops.set_params = dib7090_agc_startup;
2484 return 0;
2485}
2486
2487static int tfe7090pvr_tuner1_attach(struct dvb_usb_adapter *adap)
2488{
2489 struct dib0700_adapter_state *st = adap->priv;
2490 struct i2c_adapter *tun_i2c = dib7090_get_i2c_tuner(adap->fe);
2491
2492 if (dvb_attach(dib0090_register, adap->fe, tun_i2c, &tfe7090pvr_dib0090_config[1]) == NULL)
2493 return -ENODEV;
2494
2495 dib7000p_set_gpio(adap->fe, 8, 0, 1);
2496
2497 st->set_param_save = adap->fe->ops.tuner_ops.set_params;
2498 adap->fe->ops.tuner_ops.set_params = dib7090_agc_startup;
2499 return 0;
2500}
2501
1562/* STK7070PD */ 2502/* STK7070PD */
1563static struct dib7000p_config stk7070pd_dib7000p_config[2] = { 2503static struct dib7000p_config stk7070pd_dib7000p_config[2] = {
1564 { 2504 {
@@ -1856,6 +2796,12 @@ struct usb_device_id dib0700_usb_id_table[] = {
1856 { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV282E) }, 2796 { USB_DEVICE(USB_VID_PINNACLE, USB_PID_PINNACLE_PCTV282E) },
1857 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK8096GP) }, 2797 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK8096GP) },
1858 { USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_DIVERSITY) }, 2798 { USB_DEVICE(USB_VID_ELGATO, USB_PID_ELGATO_EYETV_DIVERSITY) },
2799 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM9090M) },
2800/* 70 */{ USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM8096MD) },
2801 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM9090MD) },
2802 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM7090) },
2803 { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE7090PVR) },
2804 { USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2) },
1859 { 0 } /* Terminating entry */ 2805 { 0 } /* Terminating entry */
1860}; 2806};
1861MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table); 2807MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
@@ -2465,7 +3411,7 @@ struct dvb_usb_device_properties dib0700_devices[] = {
2465 }, 3411 },
2466 }, 3412 },
2467 3413
2468 .num_device_descs = 2, 3414 .num_device_descs = 3,
2469 .devices = { 3415 .devices = {
2470 { "DiBcom STK7770P reference design", 3416 { "DiBcom STK7770P reference design",
2471 { &dib0700_usb_id_table[59], NULL }, 3417 { &dib0700_usb_id_table[59], NULL },
@@ -2477,6 +3423,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
2477 &dib0700_usb_id_table[60], NULL}, 3423 &dib0700_usb_id_table[60], NULL},
2478 { NULL }, 3424 { NULL },
2479 }, 3425 },
3426 { "TechniSat AirStar TeleStick 2",
3427 { &dib0700_usb_id_table[74], NULL },
3428 { NULL },
3429 },
2480 }, 3430 },
2481 3431
2482 .rc.core = { 3432 .rc.core = {
@@ -2619,6 +3569,205 @@ struct dvb_usb_device_properties dib0700_devices[] = {
2619 RC_TYPE_NEC, 3569 RC_TYPE_NEC,
2620 .change_protocol = dib0700_change_protocol, 3570 .change_protocol = dib0700_change_protocol,
2621 }, 3571 },
3572 }, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
3573 .num_adapters = 1,
3574 .adapter = {
3575 {
3576 .caps = DVB_USB_ADAP_HAS_PID_FILTER |
3577 DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
3578 .pid_filter_count = 32,
3579 .pid_filter = dib90x0_pid_filter,
3580 .pid_filter_ctrl = dib90x0_pid_filter_ctrl,
3581 .frontend_attach = stk9090m_frontend_attach,
3582 .tuner_attach = dib9090_tuner_attach,
3583
3584 DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
3585
3586 .size_of_priv =
3587 sizeof(struct dib0700_adapter_state),
3588 },
3589 },
3590
3591 .num_device_descs = 1,
3592 .devices = {
3593 { "DiBcom STK9090M reference design",
3594 { &dib0700_usb_id_table[69], NULL },
3595 { NULL },
3596 },
3597 },
3598
3599 .rc.core = {
3600 .rc_interval = DEFAULT_RC_INTERVAL,
3601 .rc_codes = RC_MAP_DIB0700_RC5_TABLE,
3602 .module_name = "dib0700",
3603 .rc_query = dib0700_rc_query_old_firmware,
3604 .allowed_protos = RC_TYPE_RC5 |
3605 RC_TYPE_RC6 |
3606 RC_TYPE_NEC,
3607 .change_protocol = dib0700_change_protocol,
3608 },
3609 }, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
3610 .num_adapters = 1,
3611 .adapter = {
3612 {
3613 .caps = DVB_USB_ADAP_HAS_PID_FILTER |
3614 DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
3615 .pid_filter_count = 32,
3616 .pid_filter = stk80xx_pid_filter,
3617 .pid_filter_ctrl = stk80xx_pid_filter_ctrl,
3618 .frontend_attach = nim8096md_frontend_attach,
3619 .tuner_attach = nim8096md_tuner_attach,
3620
3621 DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
3622
3623 .size_of_priv =
3624 sizeof(struct dib0700_adapter_state),
3625 },
3626 },
3627
3628 .num_device_descs = 1,
3629 .devices = {
3630 { "DiBcom NIM8096MD reference design",
3631 { &dib0700_usb_id_table[70], NULL },
3632 { NULL },
3633 },
3634 },
3635
3636 .rc.core = {
3637 .rc_interval = DEFAULT_RC_INTERVAL,
3638 .rc_codes = RC_MAP_DIB0700_RC5_TABLE,
3639 .module_name = "dib0700",
3640 .rc_query = dib0700_rc_query_old_firmware,
3641 .allowed_protos = RC_TYPE_RC5 |
3642 RC_TYPE_RC6 |
3643 RC_TYPE_NEC,
3644 .change_protocol = dib0700_change_protocol,
3645 },
3646 }, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
3647 .num_adapters = 1,
3648 .adapter = {
3649 {
3650 .caps = DVB_USB_ADAP_HAS_PID_FILTER |
3651 DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
3652 .pid_filter_count = 32,
3653 .pid_filter = dib90x0_pid_filter,
3654 .pid_filter_ctrl = dib90x0_pid_filter_ctrl,
3655 .frontend_attach = nim9090md_frontend_attach,
3656 .tuner_attach = nim9090md_tuner_attach,
3657
3658 DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
3659
3660 .size_of_priv =
3661 sizeof(struct dib0700_adapter_state),
3662 },
3663 },
3664
3665 .num_device_descs = 1,
3666 .devices = {
3667 { "DiBcom NIM9090MD reference design",
3668 { &dib0700_usb_id_table[71], NULL },
3669 { NULL },
3670 },
3671 },
3672
3673 .rc.core = {
3674 .rc_interval = DEFAULT_RC_INTERVAL,
3675 .rc_codes = RC_MAP_DIB0700_RC5_TABLE,
3676 .module_name = "dib0700",
3677 .rc_query = dib0700_rc_query_old_firmware,
3678 .allowed_protos = RC_TYPE_RC5 |
3679 RC_TYPE_RC6 |
3680 RC_TYPE_NEC,
3681 .change_protocol = dib0700_change_protocol,
3682 },
3683 }, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
3684 .num_adapters = 1,
3685 .adapter = {
3686 {
3687 .caps = DVB_USB_ADAP_HAS_PID_FILTER |
3688 DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
3689 .pid_filter_count = 32,
3690 .pid_filter = stk70x0p_pid_filter,
3691 .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
3692 .frontend_attach = nim7090_frontend_attach,
3693 .tuner_attach = nim7090_tuner_attach,
3694
3695 DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
3696
3697 .size_of_priv =
3698 sizeof(struct dib0700_adapter_state),
3699 },
3700 },
3701
3702 .num_device_descs = 1,
3703 .devices = {
3704 { "DiBcom NIM7090 reference design",
3705 { &dib0700_usb_id_table[72], NULL },
3706 { NULL },
3707 },
3708 },
3709
3710 .rc.core = {
3711 .rc_interval = DEFAULT_RC_INTERVAL,
3712 .rc_codes = RC_MAP_DIB0700_RC5_TABLE,
3713 .module_name = "dib0700",
3714 .rc_query = dib0700_rc_query_old_firmware,
3715 .allowed_protos = RC_TYPE_RC5 |
3716 RC_TYPE_RC6 |
3717 RC_TYPE_NEC,
3718 .change_protocol = dib0700_change_protocol,
3719 },
3720 }, { DIB0700_DEFAULT_DEVICE_PROPERTIES,
3721 .num_adapters = 2,
3722 .adapter = {
3723 {
3724 .caps = DVB_USB_ADAP_HAS_PID_FILTER |
3725 DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
3726 .pid_filter_count = 32,
3727 .pid_filter = stk70x0p_pid_filter,
3728 .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
3729 .frontend_attach = tfe7090pvr_frontend0_attach,
3730 .tuner_attach = tfe7090pvr_tuner0_attach,
3731
3732 DIB0700_DEFAULT_STREAMING_CONFIG(0x03),
3733
3734 .size_of_priv =
3735 sizeof(struct dib0700_adapter_state),
3736 },
3737 {
3738 .caps = DVB_USB_ADAP_HAS_PID_FILTER |
3739 DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
3740 .pid_filter_count = 32,
3741 .pid_filter = stk70x0p_pid_filter,
3742 .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
3743 .frontend_attach = tfe7090pvr_frontend1_attach,
3744 .tuner_attach = tfe7090pvr_tuner1_attach,
3745
3746 DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
3747
3748 .size_of_priv =
3749 sizeof(struct dib0700_adapter_state),
3750 },
3751 },
3752
3753 .num_device_descs = 1,
3754 .devices = {
3755 { "DiBcom TFE7090PVR reference design",
3756 { &dib0700_usb_id_table[73], NULL },
3757 { NULL },
3758 },
3759 },
3760
3761 .rc.core = {
3762 .rc_interval = DEFAULT_RC_INTERVAL,
3763 .rc_codes = RC_MAP_DIB0700_RC5_TABLE,
3764 .module_name = "dib0700",
3765 .rc_query = dib0700_rc_query_old_firmware,
3766 .allowed_protos = RC_TYPE_RC5 |
3767 RC_TYPE_RC6 |
3768 RC_TYPE_NEC,
3769 .change_protocol = dib0700_change_protocol,
3770 },
2622 }, 3771 },
2623}; 3772};
2624 3773
diff --git a/drivers/media/dvb/dvb-usb/digitv.c b/drivers/media/dvb/dvb-usb/digitv.c
index f2dbce7edb3b..f6344cdd360f 100644
--- a/drivers/media/dvb/dvb-usb/digitv.c
+++ b/drivers/media/dvb/dvb-usb/digitv.c
@@ -176,7 +176,7 @@ static struct rc_map_table rc_map_digitv_table[] = {
176 { 0xaf59, KEY_AUX }, 176 { 0xaf59, KEY_AUX },
177 { 0x5f5a, KEY_DVD }, 177 { 0x5f5a, KEY_DVD },
178 { 0x6f5a, KEY_POWER }, 178 { 0x6f5a, KEY_POWER },
179 { 0x9f5a, KEY_MHP }, /* labelled 'Picture' */ 179 { 0x9f5a, KEY_CAMERA }, /* labelled 'Picture' */
180 { 0xaf5a, KEY_AUDIO }, 180 { 0xaf5a, KEY_AUDIO },
181 { 0x5f65, KEY_INFO }, 181 { 0x5f65, KEY_INFO },
182 { 0x6f65, KEY_F13 }, /* 16:9 */ 182 { 0x6f65, KEY_F13 }, /* 16:9 */
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index 1a6310b61923..3a8b7446b7b0 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -106,8 +106,13 @@
106#define USB_PID_DIBCOM_STK807XP 0x1f90 106#define USB_PID_DIBCOM_STK807XP 0x1f90
107#define USB_PID_DIBCOM_STK807XPVR 0x1f98 107#define USB_PID_DIBCOM_STK807XPVR 0x1f98
108#define USB_PID_DIBCOM_STK8096GP 0x1fa0 108#define USB_PID_DIBCOM_STK8096GP 0x1fa0
109#define USB_PID_DIBCOM_NIM8096MD 0x1fa8
109#define USB_PID_DIBCOM_ANCHOR_2135_COLD 0x2131 110#define USB_PID_DIBCOM_ANCHOR_2135_COLD 0x2131
110#define USB_PID_DIBCOM_STK7770P 0x1e80 111#define USB_PID_DIBCOM_STK7770P 0x1e80
112#define USB_PID_DIBCOM_NIM7090 0x1bb2
113#define USB_PID_DIBCOM_TFE7090PVR 0x1bb4
114#define USB_PID_DIBCOM_NIM9090M 0x2383
115#define USB_PID_DIBCOM_NIM9090MD 0x2384
111#define USB_PID_DPOSH_M9206_COLD 0x9206 116#define USB_PID_DPOSH_M9206_COLD 0x9206
112#define USB_PID_DPOSH_M9206_WARM 0xa090 117#define USB_PID_DPOSH_M9206_WARM 0xa090
113#define USB_PID_E3C_EC168 0x1689 118#define USB_PID_E3C_EC168 0x1689
@@ -312,4 +317,6 @@
312#define USB_PID_TERRATEC_DVBS2CI_V2 0x10ac 317#define USB_PID_TERRATEC_DVBS2CI_V2 0x10ac
313#define USB_PID_TECHNISAT_USB2_HDCI_V1 0x0001 318#define USB_PID_TECHNISAT_USB2_HDCI_V1 0x0001
314#define USB_PID_TECHNISAT_USB2_HDCI_V2 0x0002 319#define USB_PID_TECHNISAT_USB2_HDCI_V2 0x0002
320#define USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2 0x0004
321#define USB_PID_TECHNISAT_USB2_DVB_S2 0x0500
315#endif 322#endif
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-remote.c b/drivers/media/dvb/dvb-usb/dvb-usb-remote.c
index 23005b3cf30b..41bacff24960 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-remote.c
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-remote.c
@@ -8,60 +8,71 @@
8#include "dvb-usb-common.h" 8#include "dvb-usb-common.h"
9#include <linux/usb/input.h> 9#include <linux/usb/input.h>
10 10
11static unsigned int
12legacy_dvb_usb_get_keymap_index(const struct input_keymap_entry *ke,
13 struct rc_map_table *keymap,
14 unsigned int keymap_size)
15{
16 unsigned int index;
17 unsigned int scancode;
18
19 if (ke->flags & INPUT_KEYMAP_BY_INDEX) {
20 index = ke->index;
21 } else {
22 if (input_scancode_to_scalar(ke, &scancode))
23 return keymap_size;
24
25 /* See if we can match the raw key code. */
26 for (index = 0; index < keymap_size; index++)
27 if (keymap[index].scancode == scancode)
28 break;
29
30 /* See if there is an unused hole in the map */
31 if (index >= keymap_size) {
32 for (index = 0; index < keymap_size; index++) {
33 if (keymap[index].keycode == KEY_RESERVED ||
34 keymap[index].keycode == KEY_UNKNOWN) {
35 break;
36 }
37 }
38 }
39 }
40
41 return index;
42}
43
11static int legacy_dvb_usb_getkeycode(struct input_dev *dev, 44static int legacy_dvb_usb_getkeycode(struct input_dev *dev,
12 unsigned int scancode, unsigned int *keycode) 45 struct input_keymap_entry *ke)
13{ 46{
14 struct dvb_usb_device *d = input_get_drvdata(dev); 47 struct dvb_usb_device *d = input_get_drvdata(dev);
15
16 struct rc_map_table *keymap = d->props.rc.legacy.rc_map_table; 48 struct rc_map_table *keymap = d->props.rc.legacy.rc_map_table;
17 int i; 49 unsigned int keymap_size = d->props.rc.legacy.rc_map_size;
50 unsigned int index;
18 51
19 /* See if we can match the raw key code. */ 52 index = legacy_dvb_usb_get_keymap_index(ke, keymap, keymap_size);
20 for (i = 0; i < d->props.rc.legacy.rc_map_size; i++) 53 if (index >= keymap_size)
21 if (keymap[i].scancode == scancode) { 54 return -EINVAL;
22 *keycode = keymap[i].keycode;
23 return 0;
24 }
25 55
26 /* 56 ke->keycode = keymap[index].keycode;
27 * If is there extra space, returns KEY_RESERVED, 57 if (ke->keycode == KEY_UNKNOWN)
28 * otherwise, input core won't let legacy_dvb_usb_setkeycode 58 ke->keycode = KEY_RESERVED;
29 * to work 59 ke->len = sizeof(keymap[index].scancode);
30 */ 60 memcpy(&ke->scancode, &keymap[index].scancode, ke->len);
31 for (i = 0; i < d->props.rc.legacy.rc_map_size; i++) 61 ke->index = index;
32 if (keymap[i].keycode == KEY_RESERVED ||
33 keymap[i].keycode == KEY_UNKNOWN) {
34 *keycode = KEY_RESERVED;
35 return 0;
36 }
37 62
38 return -EINVAL; 63 return 0;
39} 64}
40 65
41static int legacy_dvb_usb_setkeycode(struct input_dev *dev, 66static int legacy_dvb_usb_setkeycode(struct input_dev *dev,
42 unsigned int scancode, unsigned int keycode) 67 const struct input_keymap_entry *ke,
68 unsigned int *old_keycode)
43{ 69{
44 struct dvb_usb_device *d = input_get_drvdata(dev); 70 struct dvb_usb_device *d = input_get_drvdata(dev);
45
46 struct rc_map_table *keymap = d->props.rc.legacy.rc_map_table; 71 struct rc_map_table *keymap = d->props.rc.legacy.rc_map_table;
47 int i; 72 unsigned int keymap_size = d->props.rc.legacy.rc_map_size;
48 73 unsigned int index;
49 /* Search if it is replacing an existing keycode */
50 for (i = 0; i < d->props.rc.legacy.rc_map_size; i++)
51 if (keymap[i].scancode == scancode) {
52 keymap[i].keycode = keycode;
53 return 0;
54 }
55
56 /* Search if is there a clean entry. If so, use it */
57 for (i = 0; i < d->props.rc.legacy.rc_map_size; i++)
58 if (keymap[i].keycode == KEY_RESERVED ||
59 keymap[i].keycode == KEY_UNKNOWN) {
60 keymap[i].scancode = scancode;
61 keymap[i].keycode = keycode;
62 return 0;
63 }
64 74
75 index = legacy_dvb_usb_get_keymap_index(ke, keymap, keymap_size);
65 /* 76 /*
66 * FIXME: Currently, it is not possible to increase the size of 77 * FIXME: Currently, it is not possible to increase the size of
67 * scancode table. For it to happen, one possibility 78 * scancode table. For it to happen, one possibility
@@ -69,8 +80,24 @@ static int legacy_dvb_usb_setkeycode(struct input_dev *dev,
69 * copying data, appending the new key on it, and freeing 80 * copying data, appending the new key on it, and freeing
70 * the old one - or maybe just allocating some spare space 81 * the old one - or maybe just allocating some spare space
71 */ 82 */
83 if (index >= keymap_size)
84 return -EINVAL;
85
86 *old_keycode = keymap[index].keycode;
87 keymap->keycode = ke->keycode;
88 __set_bit(ke->keycode, dev->keybit);
89
90 if (*old_keycode != KEY_RESERVED) {
91 __clear_bit(*old_keycode, dev->keybit);
92 for (index = 0; index < keymap_size; index++) {
93 if (keymap[index].keycode == *old_keycode) {
94 __set_bit(*old_keycode, dev->keybit);
95 break;
96 }
97 }
98 }
72 99
73 return -EINVAL; 100 return 0;
74} 101}
75 102
76/* Remote-control poll function - called every dib->rc_query_interval ms to see 103/* Remote-control poll function - called every dib->rc_query_interval ms to see
@@ -246,7 +273,7 @@ static int rc_core_dvb_usb_remote_init(struct dvb_usb_device *d)
246 dev->map_name = d->props.rc.core.rc_codes; 273 dev->map_name = d->props.rc.core.rc_codes;
247 dev->change_protocol = d->props.rc.core.change_protocol; 274 dev->change_protocol = d->props.rc.core.change_protocol;
248 dev->allowed_protos = d->props.rc.core.allowed_protos; 275 dev->allowed_protos = d->props.rc.core.allowed_protos;
249 dev->driver_type = RC_DRIVER_SCANCODE; 276 dev->driver_type = d->props.rc.core.driver_type;
250 usb_to_input_id(d->udev, &dev->input_id); 277 usb_to_input_id(d->udev, &dev->input_id);
251 dev->input_name = "IR-receiver inside an USB DVB receiver"; 278 dev->input_name = "IR-receiver inside an USB DVB receiver";
252 dev->input_phys = d->rc_phys; 279 dev->input_phys = d->rc_phys;
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb.h b/drivers/media/dvb/dvb-usb/dvb-usb.h
index 65fa9268e7f7..76a80968482a 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb.h
@@ -181,6 +181,7 @@ struct dvb_rc_legacy {
181 * @rc_codes: name of rc codes table 181 * @rc_codes: name of rc codes table
182 * @protocol: type of protocol(s) currently used by the driver 182 * @protocol: type of protocol(s) currently used by the driver
183 * @allowed_protos: protocol(s) supported by the driver 183 * @allowed_protos: protocol(s) supported by the driver
184 * @driver_type: Used to point if a device supports raw mode
184 * @change_protocol: callback to change protocol 185 * @change_protocol: callback to change protocol
185 * @rc_query: called to query an event event. 186 * @rc_query: called to query an event event.
186 * @rc_interval: time in ms between two queries. 187 * @rc_interval: time in ms between two queries.
@@ -190,6 +191,7 @@ struct dvb_rc {
190 char *rc_codes; 191 char *rc_codes;
191 u64 protocol; 192 u64 protocol;
192 u64 allowed_protos; 193 u64 allowed_protos;
194 enum rc_driver_type driver_type;
193 int (*change_protocol)(struct rc_dev *dev, u64 rc_type); 195 int (*change_protocol)(struct rc_dev *dev, u64 rc_type);
194 char *module_name; 196 char *module_name;
195 int (*rc_query) (struct dvb_usb_device *d); 197 int (*rc_query) (struct dvb_usb_device *d);
diff --git a/drivers/media/dvb/dvb-usb/dw2102.c b/drivers/media/dvb/dvb-usb/dw2102.c
index 2c307ba0d28b..f5b9da18f611 100644
--- a/drivers/media/dvb/dvb-usb/dw2102.c
+++ b/drivers/media/dvb/dvb-usb/dw2102.c
@@ -1,15 +1,16 @@
1/* DVB USB framework compliant Linux driver for the 1/* DVB USB framework compliant Linux driver for the
2* DVBWorld DVB-S 2101, 2102, DVB-S2 2104, DVB-C 3101, 2 * DVBWorld DVB-S 2101, 2102, DVB-S2 2104, DVB-C 3101,
3* TeVii S600, S630, S650, 3 * TeVii S600, S630, S650, S660, S480,
4* Prof 1100, 7500 Cards 4 * Prof 1100, 7500,
5* Copyright (C) 2008,2009 Igor M. Liplianin (liplianin@me.by) 5 * Geniatech SU3000 Cards
6* 6 * Copyright (C) 2008-2011 Igor M. Liplianin (liplianin@me.by)
7* This program is free software; you can redistribute it and/or modify it 7 *
8* under the terms of the GNU General Public License as published by the 8 * This program is free software; you can redistribute it and/or modify it
9* Free Software Foundation, version 2. 9 * under the terms of the GNU General Public License as published by the
10* 10 * Free Software Foundation, version 2.
11* see Documentation/dvb/README.dvb-usb for more information 11 *
12*/ 12 * see Documentation/dvb/README.dvb-usb for more information
13 */
13#include "dw2102.h" 14#include "dw2102.h"
14#include "si21xx.h" 15#include "si21xx.h"
15#include "stv0299.h" 16#include "stv0299.h"
@@ -55,6 +56,14 @@
55#define USB_PID_TEVII_S660 0xd660 56#define USB_PID_TEVII_S660 0xd660
56#endif 57#endif
57 58
59#ifndef USB_PID_TEVII_S480_1
60#define USB_PID_TEVII_S480_1 0xd481
61#endif
62
63#ifndef USB_PID_TEVII_S480_2
64#define USB_PID_TEVII_S480_2 0xd482
65#endif
66
58#ifndef USB_PID_PROF_1100 67#ifndef USB_PID_PROF_1100
59#define USB_PID_PROF_1100 0xb012 68#define USB_PID_PROF_1100 0xb012
60#endif 69#endif
@@ -67,7 +76,9 @@
67#define REG_21_SYMBOLRATE_BYTE2 0x21 76#define REG_21_SYMBOLRATE_BYTE2 0x21
68/* on my own*/ 77/* on my own*/
69#define DW2102_VOLTAGE_CTRL (0x1800) 78#define DW2102_VOLTAGE_CTRL (0x1800)
79#define SU3000_STREAM_CTRL (0x1900)
70#define DW2102_RC_QUERY (0x1a00) 80#define DW2102_RC_QUERY (0x1a00)
81#define DW2102_LED_CTRL (0x1b00)
71 82
72#define err_str "did not find the firmware file. (%s) " \ 83#define err_str "did not find the firmware file. (%s) " \
73 "Please see linux/Documentation/dvb/ for more details " \ 84 "Please see linux/Documentation/dvb/ for more details " \
@@ -78,6 +89,14 @@ struct rc_map_dvb_usb_table_table {
78 int rc_keys_size; 89 int rc_keys_size;
79}; 90};
80 91
92struct su3000_state {
93 u8 initialized;
94};
95
96struct s6x0_state {
97 int (*old_set_voltage)(struct dvb_frontend *f, fe_sec_voltage_t v);
98};
99
81/* debug */ 100/* debug */
82static int dvb_usb_dw2102_debug; 101static int dvb_usb_dw2102_debug;
83module_param_named(debug, dvb_usb_dw2102_debug, int, 0644); 102module_param_named(debug, dvb_usb_dw2102_debug, int, 0644);
@@ -87,7 +106,8 @@ MODULE_PARM_DESC(debug, "set debugging level (1=info 2=xfer 4=rc(or-able))."
87/* keymaps */ 106/* keymaps */
88static int ir_keymap; 107static int ir_keymap;
89module_param_named(keymap, ir_keymap, int, 0644); 108module_param_named(keymap, ir_keymap, int, 0644);
90MODULE_PARM_DESC(keymap, "set keymap 0=default 1=dvbworld 2=tevii 3=tbs ..."); 109MODULE_PARM_DESC(keymap, "set keymap 0=default 1=dvbworld 2=tevii 3=tbs ..."
110 " 256=none");
91 111
92/* demod probe */ 112/* demod probe */
93static int demod_probe = 1; 113static int demod_probe = 1;
@@ -136,8 +156,7 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
136 /* read stv0299 register */ 156 /* read stv0299 register */
137 value = msg[0].buf[0];/* register */ 157 value = msg[0].buf[0];/* register */
138 for (i = 0; i < msg[1].len; i++) { 158 for (i = 0; i < msg[1].len; i++) {
139 value = value + i; 159 ret = dw210x_op_rw(d->udev, 0xb5, value + i, 0,
140 ret = dw210x_op_rw(d->udev, 0xb5, value, 0,
141 buf6, 2, DW210X_READ_MSG); 160 buf6, 2, DW210X_READ_MSG);
142 msg[1].buf[i] = buf6[0]; 161 msg[1].buf[i] = buf6[0];
143 } 162 }
@@ -483,10 +502,10 @@ static int s6x0_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
483 for (j = 0; j < num; j++) { 502 for (j = 0; j < num; j++) {
484 switch (msg[j].addr) { 503 switch (msg[j].addr) {
485 case (DW2102_RC_QUERY): { 504 case (DW2102_RC_QUERY): {
486 u8 ibuf[4]; 505 u8 ibuf[5];
487 ret = dw210x_op_rw(d->udev, 0xb8, 0, 0, 506 ret = dw210x_op_rw(d->udev, 0xb8, 0, 0,
488 ibuf, 4, DW210X_READ_MSG); 507 ibuf, 5, DW210X_READ_MSG);
489 memcpy(msg[j].buf, ibuf + 1, 2); 508 memcpy(msg[j].buf, ibuf + 3, 2);
490 break; 509 break;
491 } 510 }
492 case (DW2102_VOLTAGE_CTRL): { 511 case (DW2102_VOLTAGE_CTRL): {
@@ -502,6 +521,15 @@ static int s6x0_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
502 obuf, 2, DW210X_WRITE_MSG); 521 obuf, 2, DW210X_WRITE_MSG);
503 break; 522 break;
504 } 523 }
524 case (DW2102_LED_CTRL): {
525 u8 obuf[2];
526
527 obuf[0] = 5;
528 obuf[1] = msg[j].buf[0];
529 ret = dw210x_op_rw(d->udev, 0x8a, 0, 0,
530 obuf, 2, DW210X_WRITE_MSG);
531 break;
532 }
505 /*case 0x55: cx24116 533 /*case 0x55: cx24116
506 case 0x6a: stv0903 534 case 0x6a: stv0903
507 case 0x68: ds3000, stv0903 535 case 0x68: ds3000, stv0903
@@ -535,14 +563,15 @@ static int s6x0_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
535 i += 16; 563 i += 16;
536 len -= 16; 564 len -= 16;
537 } while (len > 0); 565 } while (len > 0);
538 } else if ((udev->descriptor.idProduct == 0x7500) 566 } else if (j < (num - 1)) {
539 && (j < (num - 1))) {
540 /* write register addr before read */ 567 /* write register addr before read */
541 u8 obuf[msg[j].len + 2]; 568 u8 obuf[msg[j].len + 2];
542 obuf[0] = msg[j + 1].len; 569 obuf[0] = msg[j + 1].len;
543 obuf[1] = (msg[j].addr << 1); 570 obuf[1] = (msg[j].addr << 1);
544 memcpy(obuf + 2, msg[j].buf, msg[j].len); 571 memcpy(obuf + 2, msg[j].buf, msg[j].len);
545 ret = dw210x_op_rw(d->udev, 0x92, 0, 0, 572 ret = dw210x_op_rw(d->udev,
573 udev->descriptor.idProduct ==
574 0x7500 ? 0x92 : 0x90, 0, 0,
546 obuf, msg[j].len + 2, 575 obuf, msg[j].len + 2,
547 DW210X_WRITE_MSG); 576 DW210X_WRITE_MSG);
548 break; 577 break;
@@ -552,8 +581,7 @@ static int s6x0_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
552 obuf[0] = msg[j].len + 1; 581 obuf[0] = msg[j].len + 1;
553 obuf[1] = (msg[j].addr << 1); 582 obuf[1] = (msg[j].addr << 1);
554 memcpy(obuf + 2, msg[j].buf, msg[j].len); 583 memcpy(obuf + 2, msg[j].buf, msg[j].len);
555 ret = dw210x_op_rw(d->udev, 584 ret = dw210x_op_rw(d->udev, 0x80, 0, 0,
556 (num > 1 ? 0x90 : 0x80), 0, 0,
557 obuf, msg[j].len + 2, 585 obuf, msg[j].len + 2,
558 DW210X_WRITE_MSG); 586 DW210X_WRITE_MSG);
559 break; 587 break;
@@ -561,14 +589,76 @@ static int s6x0_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
561 break; 589 break;
562 } 590 }
563 } 591 }
564
565 msleep(3);
566 } 592 }
567 593
568 mutex_unlock(&d->i2c_mutex); 594 mutex_unlock(&d->i2c_mutex);
569 return num; 595 return num;
570} 596}
571 597
598static int su3000_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
599 int num)
600{
601 struct dvb_usb_device *d = i2c_get_adapdata(adap);
602 u8 obuf[0x40], ibuf[0x40];
603
604 if (!d)
605 return -ENODEV;
606 if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
607 return -EAGAIN;
608
609 switch (num) {
610 case 1:
611 switch (msg[0].addr) {
612 case SU3000_STREAM_CTRL:
613 obuf[0] = msg[0].buf[0] + 0x36;
614 obuf[1] = 3;
615 obuf[2] = 0;
616 if (dvb_usb_generic_rw(d, obuf, 3, ibuf, 0, 0) < 0)
617 err("i2c transfer failed.");
618 break;
619 case DW2102_RC_QUERY:
620 obuf[0] = 0x10;
621 if (dvb_usb_generic_rw(d, obuf, 1, ibuf, 2, 0) < 0)
622 err("i2c transfer failed.");
623 msg[0].buf[1] = ibuf[0];
624 msg[0].buf[0] = ibuf[1];
625 break;
626 default:
627 /* always i2c write*/
628 obuf[0] = 0x08;
629 obuf[1] = msg[0].addr;
630 obuf[2] = msg[0].len;
631
632 memcpy(&obuf[3], msg[0].buf, msg[0].len);
633
634 if (dvb_usb_generic_rw(d, obuf, msg[0].len + 3,
635 ibuf, 1, 0) < 0)
636 err("i2c transfer failed.");
637
638 }
639 break;
640 case 2:
641 /* always i2c read */
642 obuf[0] = 0x09;
643 obuf[1] = msg[0].len;
644 obuf[2] = msg[1].len;
645 obuf[3] = msg[0].addr;
646 memcpy(&obuf[4], msg[0].buf, msg[0].len);
647
648 if (dvb_usb_generic_rw(d, obuf, msg[0].len + 4,
649 ibuf, msg[1].len + 1, 0) < 0)
650 err("i2c transfer failed.");
651
652 memcpy(msg[1].buf, &ibuf[1], msg[1].len);
653 break;
654 default:
655 warn("more than 2 i2c messages at a time is not handled yet.");
656 break;
657 }
658 mutex_unlock(&d->i2c_mutex);
659 return num;
660}
661
572static u32 dw210x_i2c_func(struct i2c_adapter *adapter) 662static u32 dw210x_i2c_func(struct i2c_adapter *adapter)
573{ 663{
574 return I2C_FUNC_I2C; 664 return I2C_FUNC_I2C;
@@ -604,6 +694,11 @@ static struct i2c_algorithm s6x0_i2c_algo = {
604 .functionality = dw210x_i2c_func, 694 .functionality = dw210x_i2c_func,
605}; 695};
606 696
697static struct i2c_algorithm su3000_i2c_algo = {
698 .master_xfer = su3000_i2c_transfer,
699 .functionality = dw210x_i2c_func,
700};
701
607static int dw210x_read_mac_address(struct dvb_usb_device *d, u8 mac[6]) 702static int dw210x_read_mac_address(struct dvb_usb_device *d, u8 mac[6])
608{ 703{
609 int i; 704 int i;
@@ -668,6 +763,82 @@ static int s6x0_read_mac_address(struct dvb_usb_device *d, u8 mac[6])
668 return 0; 763 return 0;
669}; 764};
670 765
766static int su3000_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff)
767{
768 static u8 command_start[] = {0x00};
769 static u8 command_stop[] = {0x01};
770 struct i2c_msg msg = {
771 .addr = SU3000_STREAM_CTRL,
772 .flags = 0,
773 .buf = onoff ? command_start : command_stop,
774 .len = 1
775 };
776
777 i2c_transfer(&adap->dev->i2c_adap, &msg, 1);
778
779 return 0;
780}
781
782static int su3000_power_ctrl(struct dvb_usb_device *d, int i)
783{
784 struct su3000_state *state = (struct su3000_state *)d->priv;
785 u8 obuf[] = {0xde, 0};
786
787 info("%s: %d, initialized %d\n", __func__, i, state->initialized);
788
789 if (i && !state->initialized) {
790 state->initialized = 1;
791 /* reset board */
792 dvb_usb_generic_rw(d, obuf, 2, NULL, 0, 0);
793 }
794
795 return 0;
796}
797
798static int su3000_read_mac_address(struct dvb_usb_device *d, u8 mac[6])
799{
800 int i;
801 u8 obuf[] = { 0x1f, 0xf0 };
802 u8 ibuf[] = { 0 };
803 struct i2c_msg msg[] = {
804 {
805 .addr = 0x51,
806 .flags = 0,
807 .buf = obuf,
808 .len = 2,
809 }, {
810 .addr = 0x51,
811 .flags = I2C_M_RD,
812 .buf = ibuf,
813 .len = 1,
814
815 }
816 };
817
818 for (i = 0; i < 6; i++) {
819 obuf[1] = 0xf0 + i;
820 if (i2c_transfer(&d->i2c_adap, msg, 2) != 2)
821 break;
822 else
823 mac[i] = ibuf[0];
824
825 debug_dump(mac, 6, printk);
826 }
827
828 return 0;
829}
830
831static int su3000_identify_state(struct usb_device *udev,
832 struct dvb_usb_device_properties *props,
833 struct dvb_usb_device_description **desc,
834 int *cold)
835{
836 info("%s\n", __func__);
837
838 *cold = 0;
839 return 0;
840}
841
671static int dw210x_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) 842static int dw210x_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
672{ 843{
673 static u8 command_13v[] = {0x00, 0x01}; 844 static u8 command_13v[] = {0x00, 0x01};
@@ -692,6 +863,37 @@ static int dw210x_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
692 return 0; 863 return 0;
693} 864}
694 865
866static int s660_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
867{
868 struct dvb_usb_adapter *d =
869 (struct dvb_usb_adapter *)(fe->dvb->priv);
870 struct s6x0_state *st = (struct s6x0_state *)d->dev->priv;
871
872 dw210x_set_voltage(fe, voltage);
873 if (st->old_set_voltage)
874 st->old_set_voltage(fe, voltage);
875
876 return 0;
877}
878
879static void dw210x_led_ctrl(struct dvb_frontend *fe, int offon)
880{
881 static u8 led_off[] = { 0 };
882 static u8 led_on[] = { 1 };
883 struct i2c_msg msg = {
884 .addr = DW2102_LED_CTRL,
885 .flags = 0,
886 .buf = led_off,
887 .len = 1
888 };
889 struct dvb_usb_adapter *udev_adap =
890 (struct dvb_usb_adapter *)(fe->dvb->priv);
891
892 if (offon)
893 msg.buf = led_on;
894 i2c_transfer(&udev_adap->dev->i2c_adap, &msg, 1);
895}
896
695static struct stv0299_config sharp_z0194a_config = { 897static struct stv0299_config sharp_z0194a_config = {
696 .demod_address = 0x68, 898 .demod_address = 0x68,
697 .inittab = sharp_z0194a_inittab, 899 .inittab = sharp_z0194a_inittab,
@@ -771,6 +973,12 @@ static struct stv0900_config prof_7500_stv0900_config = {
771 .tun1_adc = 0,/* 2 Vpp */ 973 .tun1_adc = 0,/* 2 Vpp */
772 .path1_mode = 3, 974 .path1_mode = 3,
773 .tun1_type = 3, 975 .tun1_type = 3,
976 .set_lock_led = dw210x_led_ctrl,
977};
978
979static struct ds3000_config su3000_ds3000_config = {
980 .demod_address = 0x68,
981 .ci_mode = 1,
774}; 982};
775 983
776static int dw2104_frontend_attach(struct dvb_usb_adapter *d) 984static int dw2104_frontend_attach(struct dvb_usb_adapter *d)
@@ -885,7 +1093,7 @@ static int dw3101_frontend_attach(struct dvb_usb_adapter *d)
885 return -EIO; 1093 return -EIO;
886} 1094}
887 1095
888static int s6x0_frontend_attach(struct dvb_usb_adapter *d) 1096static int zl100313_frontend_attach(struct dvb_usb_adapter *d)
889{ 1097{
890 d->fe = dvb_attach(mt312_attach, &zl313_config, 1098 d->fe = dvb_attach(mt312_attach, &zl313_config,
891 &d->dev->i2c_adap); 1099 &d->dev->i2c_adap);
@@ -898,41 +1106,108 @@ static int s6x0_frontend_attach(struct dvb_usb_adapter *d)
898 } 1106 }
899 } 1107 }
900 1108
1109 return -EIO;
1110}
1111
1112static int stv0288_frontend_attach(struct dvb_usb_adapter *d)
1113{
1114 u8 obuf[] = {7, 1};
1115
901 d->fe = dvb_attach(stv0288_attach, &earda_config, 1116 d->fe = dvb_attach(stv0288_attach, &earda_config,
902 &d->dev->i2c_adap); 1117 &d->dev->i2c_adap);
903 if (d->fe != NULL) { 1118
904 if (dvb_attach(stb6000_attach, d->fe, 0x61, 1119 if (d->fe == NULL)
905 &d->dev->i2c_adap)) { 1120 return -EIO;
906 d->fe->ops.set_voltage = dw210x_set_voltage; 1121
907 info("Attached stv0288+stb6000!\n"); 1122 if (NULL == dvb_attach(stb6000_attach, d->fe, 0x61, &d->dev->i2c_adap))
908 return 0; 1123 return -EIO;
909 } 1124
910 } 1125 d->fe->ops.set_voltage = dw210x_set_voltage;
1126
1127 dw210x_op_rw(d->dev->udev, 0x8a, 0, 0, obuf, 2, DW210X_WRITE_MSG);
1128
1129 info("Attached stv0288+stb6000!\n");
1130
1131 return 0;
1132
1133}
1134
1135static int ds3000_frontend_attach(struct dvb_usb_adapter *d)
1136{
1137 struct s6x0_state *st = (struct s6x0_state *)d->dev->priv;
1138 u8 obuf[] = {7, 1};
911 1139
912 d->fe = dvb_attach(ds3000_attach, &dw2104_ds3000_config, 1140 d->fe = dvb_attach(ds3000_attach, &dw2104_ds3000_config,
913 &d->dev->i2c_adap); 1141 &d->dev->i2c_adap);
914 if (d->fe != NULL) {
915 d->fe->ops.set_voltage = dw210x_set_voltage;
916 info("Attached ds3000+ds2020!\n");
917 return 0;
918 }
919 1142
920 return -EIO; 1143 if (d->fe == NULL)
1144 return -EIO;
1145
1146 st->old_set_voltage = d->fe->ops.set_voltage;
1147 d->fe->ops.set_voltage = s660_set_voltage;
1148
1149 dw210x_op_rw(d->dev->udev, 0x8a, 0, 0, obuf, 2, DW210X_WRITE_MSG);
1150
1151 info("Attached ds3000+ds2020!\n");
1152
1153 return 0;
921} 1154}
922 1155
923static int prof_7500_frontend_attach(struct dvb_usb_adapter *d) 1156static int prof_7500_frontend_attach(struct dvb_usb_adapter *d)
924{ 1157{
1158 u8 obuf[] = {7, 1};
1159
925 d->fe = dvb_attach(stv0900_attach, &prof_7500_stv0900_config, 1160 d->fe = dvb_attach(stv0900_attach, &prof_7500_stv0900_config,
926 &d->dev->i2c_adap, 0); 1161 &d->dev->i2c_adap, 0);
927 if (d->fe == NULL) 1162 if (d->fe == NULL)
928 return -EIO; 1163 return -EIO;
1164
929 d->fe->ops.set_voltage = dw210x_set_voltage; 1165 d->fe->ops.set_voltage = dw210x_set_voltage;
930 1166
1167 dw210x_op_rw(d->dev->udev, 0x8a, 0, 0, obuf, 2, DW210X_WRITE_MSG);
1168
931 info("Attached STV0900+STB6100A!\n"); 1169 info("Attached STV0900+STB6100A!\n");
932 1170
933 return 0; 1171 return 0;
934} 1172}
935 1173
1174static int su3000_frontend_attach(struct dvb_usb_adapter *d)
1175{
1176 u8 obuf[3] = { 0xe, 0x80, 0 };
1177 u8 ibuf[] = { 0 };
1178
1179 if (dvb_usb_generic_rw(d->dev, obuf, 3, ibuf, 1, 0) < 0)
1180 err("command 0x0e transfer failed.");
1181
1182 obuf[0] = 0xe;
1183 obuf[1] = 0x83;
1184 obuf[2] = 0;
1185
1186 if (dvb_usb_generic_rw(d->dev, obuf, 3, ibuf, 1, 0) < 0)
1187 err("command 0x0e transfer failed.");
1188
1189 obuf[0] = 0xe;
1190 obuf[1] = 0x83;
1191 obuf[2] = 1;
1192
1193 if (dvb_usb_generic_rw(d->dev, obuf, 3, ibuf, 1, 0) < 0)
1194 err("command 0x0e transfer failed.");
1195
1196 obuf[0] = 0x51;
1197
1198 if (dvb_usb_generic_rw(d->dev, obuf, 1, ibuf, 1, 0) < 0)
1199 err("command 0x51 transfer failed.");
1200
1201 d->fe = dvb_attach(ds3000_attach, &su3000_ds3000_config,
1202 &d->dev->i2c_adap);
1203 if (d->fe == NULL)
1204 return -EIO;
1205
1206 info("Attached DS3000!\n");
1207
1208 return 0;
1209}
1210
936static int dw2102_tuner_attach(struct dvb_usb_adapter *adap) 1211static int dw2102_tuner_attach(struct dvb_usb_adapter *adap)
937{ 1212{
938 dvb_attach(dvb_pll_attach, adap->fe, 0x60, 1213 dvb_attach(dvb_pll_attach, adap->fe, 0x60,
@@ -949,8 +1224,8 @@ static int dw3101_tuner_attach(struct dvb_usb_adapter *adap)
949} 1224}
950 1225
951static struct rc_map_table rc_map_dw210x_table[] = { 1226static struct rc_map_table rc_map_dw210x_table[] = {
952 { 0xf80a, KEY_Q }, /*power*/ 1227 { 0xf80a, KEY_POWER2 }, /*power*/
953 { 0xf80c, KEY_M }, /*mute*/ 1228 { 0xf80c, KEY_MUTE }, /*mute*/
954 { 0xf811, KEY_1 }, 1229 { 0xf811, KEY_1 },
955 { 0xf812, KEY_2 }, 1230 { 0xf812, KEY_2 },
956 { 0xf813, KEY_3 }, 1231 { 0xf813, KEY_3 },
@@ -961,25 +1236,25 @@ static struct rc_map_table rc_map_dw210x_table[] = {
961 { 0xf818, KEY_8 }, 1236 { 0xf818, KEY_8 },
962 { 0xf819, KEY_9 }, 1237 { 0xf819, KEY_9 },
963 { 0xf810, KEY_0 }, 1238 { 0xf810, KEY_0 },
964 { 0xf81c, KEY_PAGEUP }, /*ch+*/ 1239 { 0xf81c, KEY_CHANNELUP }, /*ch+*/
965 { 0xf80f, KEY_PAGEDOWN }, /*ch-*/ 1240 { 0xf80f, KEY_CHANNELDOWN }, /*ch-*/
966 { 0xf81a, KEY_O }, /*vol+*/ 1241 { 0xf81a, KEY_VOLUMEUP }, /*vol+*/
967 { 0xf80e, KEY_Z }, /*vol-*/ 1242 { 0xf80e, KEY_VOLUMEDOWN }, /*vol-*/
968 { 0xf804, KEY_R }, /*rec*/ 1243 { 0xf804, KEY_RECORD }, /*rec*/
969 { 0xf809, KEY_D }, /*fav*/ 1244 { 0xf809, KEY_FAVORITES }, /*fav*/
970 { 0xf808, KEY_BACKSPACE }, /*rewind*/ 1245 { 0xf808, KEY_REWIND }, /*rewind*/
971 { 0xf807, KEY_A }, /*fast*/ 1246 { 0xf807, KEY_FASTFORWARD }, /*fast*/
972 { 0xf80b, KEY_P }, /*pause*/ 1247 { 0xf80b, KEY_PAUSE }, /*pause*/
973 { 0xf802, KEY_ESC }, /*cancel*/ 1248 { 0xf802, KEY_ESC }, /*cancel*/
974 { 0xf803, KEY_G }, /*tab*/ 1249 { 0xf803, KEY_TAB }, /*tab*/
975 { 0xf800, KEY_UP }, /*up*/ 1250 { 0xf800, KEY_UP }, /*up*/
976 { 0xf81f, KEY_ENTER }, /*ok*/ 1251 { 0xf81f, KEY_OK }, /*ok*/
977 { 0xf801, KEY_DOWN }, /*down*/ 1252 { 0xf801, KEY_DOWN }, /*down*/
978 { 0xf805, KEY_C }, /*cap*/ 1253 { 0xf805, KEY_CAMERA }, /*cap*/
979 { 0xf806, KEY_S }, /*stop*/ 1254 { 0xf806, KEY_STOP }, /*stop*/
980 { 0xf840, KEY_F }, /*full*/ 1255 { 0xf840, KEY_ZOOM }, /*full*/
981 { 0xf81e, KEY_W }, /*tvmode*/ 1256 { 0xf81e, KEY_TV }, /*tvmode*/
982 { 0xf81b, KEY_B }, /*recall*/ 1257 { 0xf81b, KEY_LAST }, /*recall*/
983}; 1258};
984 1259
985static struct rc_map_table rc_map_tevii_table[] = { 1260static struct rc_map_table rc_map_tevii_table[] = {
@@ -1067,10 +1342,49 @@ static struct rc_map_table rc_map_tbs_table[] = {
1067 { 0xf89b, KEY_MODE } 1342 { 0xf89b, KEY_MODE }
1068}; 1343};
1069 1344
1345static struct rc_map_table rc_map_su3000_table[] = {
1346 { 0x25, KEY_POWER }, /* right-bottom Red */
1347 { 0x0a, KEY_MUTE }, /* -/-- */
1348 { 0x01, KEY_1 },
1349 { 0x02, KEY_2 },
1350 { 0x03, KEY_3 },
1351 { 0x04, KEY_4 },
1352 { 0x05, KEY_5 },
1353 { 0x06, KEY_6 },
1354 { 0x07, KEY_7 },
1355 { 0x08, KEY_8 },
1356 { 0x09, KEY_9 },
1357 { 0x00, KEY_0 },
1358 { 0x20, KEY_UP }, /* CH+ */
1359 { 0x21, KEY_DOWN }, /* CH+ */
1360 { 0x12, KEY_VOLUMEUP }, /* Brightness Up */
1361 { 0x13, KEY_VOLUMEDOWN },/* Brightness Down */
1362 { 0x1f, KEY_RECORD },
1363 { 0x17, KEY_PLAY },
1364 { 0x16, KEY_PAUSE },
1365 { 0x0b, KEY_STOP },
1366 { 0x27, KEY_FASTFORWARD },/* >> */
1367 { 0x26, KEY_REWIND }, /* << */
1368 { 0x0d, KEY_OK }, /* Mute */
1369 { 0x11, KEY_LEFT }, /* VOL- */
1370 { 0x10, KEY_RIGHT }, /* VOL+ */
1371 { 0x29, KEY_BACK }, /* button under 9 */
1372 { 0x2c, KEY_MENU }, /* TTX */
1373 { 0x2b, KEY_EPG }, /* EPG */
1374 { 0x1e, KEY_RED }, /* OSD */
1375 { 0x0e, KEY_GREEN }, /* Window */
1376 { 0x2d, KEY_YELLOW }, /* button under << */
1377 { 0x0f, KEY_BLUE }, /* bottom yellow button */
1378 { 0x14, KEY_AUDIO }, /* Snapshot */
1379 { 0x38, KEY_TV }, /* TV/Radio */
1380 { 0x0c, KEY_ESC } /* upper Red buttton */
1381};
1382
1070static struct rc_map_dvb_usb_table_table keys_tables[] = { 1383static struct rc_map_dvb_usb_table_table keys_tables[] = {
1071 { rc_map_dw210x_table, ARRAY_SIZE(rc_map_dw210x_table) }, 1384 { rc_map_dw210x_table, ARRAY_SIZE(rc_map_dw210x_table) },
1072 { rc_map_tevii_table, ARRAY_SIZE(rc_map_tevii_table) }, 1385 { rc_map_tevii_table, ARRAY_SIZE(rc_map_tevii_table) },
1073 { rc_map_tbs_table, ARRAY_SIZE(rc_map_tbs_table) }, 1386 { rc_map_tbs_table, ARRAY_SIZE(rc_map_tbs_table) },
1387 { rc_map_su3000_table, ARRAY_SIZE(rc_map_su3000_table) },
1074}; 1388};
1075 1389
1076static int dw2102_rc_query(struct dvb_usb_device *d, u32 *event, int *state) 1390static int dw2102_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
@@ -1089,7 +1403,8 @@ static int dw2102_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
1089 if ((ir_keymap > 0) && (ir_keymap <= ARRAY_SIZE(keys_tables))) { 1403 if ((ir_keymap > 0) && (ir_keymap <= ARRAY_SIZE(keys_tables))) {
1090 keymap = keys_tables[ir_keymap - 1].rc_keys ; 1404 keymap = keys_tables[ir_keymap - 1].rc_keys ;
1091 keymap_size = keys_tables[ir_keymap - 1].rc_keys_size; 1405 keymap_size = keys_tables[ir_keymap - 1].rc_keys_size;
1092 } 1406 } else if (ir_keymap > ARRAY_SIZE(keys_tables))
1407 return 0; /* none */
1093 1408
1094 *state = REMOTE_NO_KEY_PRESSED; 1409 *state = REMOTE_NO_KEY_PRESSED;
1095 if (d->props.i2c_algo->master_xfer(&d->i2c_adap, &msg, 1) == 1) { 1410 if (d->props.i2c_algo->master_xfer(&d->i2c_adap, &msg, 1) == 1) {
@@ -1125,6 +1440,11 @@ static struct usb_device_id dw2102_table[] = {
1125 {USB_DEVICE(0x3011, USB_PID_PROF_1100)}, 1440 {USB_DEVICE(0x3011, USB_PID_PROF_1100)},
1126 {USB_DEVICE(0x9022, USB_PID_TEVII_S660)}, 1441 {USB_DEVICE(0x9022, USB_PID_TEVII_S660)},
1127 {USB_DEVICE(0x3034, 0x7500)}, 1442 {USB_DEVICE(0x3034, 0x7500)},
1443 {USB_DEVICE(0x1f4d, 0x3000)},
1444 {USB_DEVICE(USB_VID_TERRATEC, 0x00a8)},
1445 {USB_DEVICE(0x9022, USB_PID_TEVII_S480_1)},
1446 {USB_DEVICE(0x9022, USB_PID_TEVII_S480_2)},
1447 {USB_DEVICE(0x1f4d, 0x3100)},
1128 { } 1448 { }
1129}; 1449};
1130 1450
@@ -1184,11 +1504,6 @@ static int dw2102_load_firmware(struct usb_device *dev,
1184 } 1504 }
1185 /* init registers */ 1505 /* init registers */
1186 switch (dev->descriptor.idProduct) { 1506 switch (dev->descriptor.idProduct) {
1187 case USB_PID_PROF_1100:
1188 s6x0_properties.rc.legacy.rc_map_table = rc_map_tbs_table;
1189 s6x0_properties.rc.legacy.rc_map_size =
1190 ARRAY_SIZE(rc_map_tbs_table);
1191 break;
1192 case USB_PID_TEVII_S650: 1507 case USB_PID_TEVII_S650:
1193 dw2104_properties.rc.legacy.rc_map_table = rc_map_tevii_table; 1508 dw2104_properties.rc.legacy.rc_map_table = rc_map_tevii_table;
1194 dw2104_properties.rc.legacy.rc_map_size = 1509 dw2104_properties.rc.legacy.rc_map_size =
@@ -1271,8 +1586,6 @@ static struct dvb_usb_device_properties dw2102_properties = {
1271 .adapter = { 1586 .adapter = {
1272 { 1587 {
1273 .frontend_attach = dw2102_frontend_attach, 1588 .frontend_attach = dw2102_frontend_attach,
1274 .streaming_ctrl = NULL,
1275 .tuner_attach = NULL,
1276 .stream = { 1589 .stream = {
1277 .type = USB_BULK, 1590 .type = USB_BULK,
1278 .count = 8, 1591 .count = 8,
@@ -1324,8 +1637,6 @@ static struct dvb_usb_device_properties dw2104_properties = {
1324 .adapter = { 1637 .adapter = {
1325 { 1638 {
1326 .frontend_attach = dw2104_frontend_attach, 1639 .frontend_attach = dw2104_frontend_attach,
1327 .streaming_ctrl = NULL,
1328 /*.tuner_attach = dw2104_tuner_attach,*/
1329 .stream = { 1640 .stream = {
1330 .type = USB_BULK, 1641 .type = USB_BULK,
1331 .count = 8, 1642 .count = 8,
@@ -1373,7 +1684,6 @@ static struct dvb_usb_device_properties dw3101_properties = {
1373 .adapter = { 1684 .adapter = {
1374 { 1685 {
1375 .frontend_attach = dw3101_frontend_attach, 1686 .frontend_attach = dw3101_frontend_attach,
1376 .streaming_ctrl = NULL,
1377 .tuner_attach = dw3101_tuner_attach, 1687 .tuner_attach = dw3101_tuner_attach,
1378 .stream = { 1688 .stream = {
1379 .type = USB_BULK, 1689 .type = USB_BULK,
@@ -1399,6 +1709,7 @@ static struct dvb_usb_device_properties dw3101_properties = {
1399static struct dvb_usb_device_properties s6x0_properties = { 1709static struct dvb_usb_device_properties s6x0_properties = {
1400 .caps = DVB_USB_IS_AN_I2C_ADAPTER, 1710 .caps = DVB_USB_IS_AN_I2C_ADAPTER,
1401 .usb_ctrl = DEVICE_SPECIFIC, 1711 .usb_ctrl = DEVICE_SPECIFIC,
1712 .size_of_priv = sizeof(struct s6x0_state),
1402 .firmware = "dvb-usb-s630.fw", 1713 .firmware = "dvb-usb-s630.fw",
1403 .no_reconnect = 1, 1714 .no_reconnect = 1,
1404 1715
@@ -1416,9 +1727,7 @@ static struct dvb_usb_device_properties s6x0_properties = {
1416 .read_mac_address = s6x0_read_mac_address, 1727 .read_mac_address = s6x0_read_mac_address,
1417 .adapter = { 1728 .adapter = {
1418 { 1729 {
1419 .frontend_attach = s6x0_frontend_attach, 1730 .frontend_attach = zl100313_frontend_attach,
1420 .streaming_ctrl = NULL,
1421 .tuner_attach = NULL,
1422 .stream = { 1731 .stream = {
1423 .type = USB_BULK, 1732 .type = USB_BULK,
1424 .count = 8, 1733 .count = 8,
@@ -1431,23 +1740,41 @@ static struct dvb_usb_device_properties s6x0_properties = {
1431 }, 1740 },
1432 } 1741 }
1433 }, 1742 },
1434 .num_device_descs = 3, 1743 .num_device_descs = 1,
1435 .devices = { 1744 .devices = {
1436 {"TeVii S630 USB", 1745 {"TeVii S630 USB",
1437 {&dw2102_table[6], NULL}, 1746 {&dw2102_table[6], NULL},
1438 {NULL}, 1747 {NULL},
1439 }, 1748 },
1440 {"Prof 1100 USB ",
1441 {&dw2102_table[7], NULL},
1442 {NULL},
1443 },
1444 {"TeVii S660 USB",
1445 {&dw2102_table[8], NULL},
1446 {NULL},
1447 },
1448 } 1749 }
1449}; 1750};
1450 1751
1752struct dvb_usb_device_properties *p1100;
1753static struct dvb_usb_device_description d1100 = {
1754 "Prof 1100 USB ",
1755 {&dw2102_table[7], NULL},
1756 {NULL},
1757};
1758
1759struct dvb_usb_device_properties *s660;
1760static struct dvb_usb_device_description d660 = {
1761 "TeVii S660 USB",
1762 {&dw2102_table[8], NULL},
1763 {NULL},
1764};
1765
1766static struct dvb_usb_device_description d480_1 = {
1767 "TeVii S480.1 USB",
1768 {&dw2102_table[12], NULL},
1769 {NULL},
1770};
1771
1772static struct dvb_usb_device_description d480_2 = {
1773 "TeVii S480.2 USB",
1774 {&dw2102_table[13], NULL},
1775 {NULL},
1776};
1777
1451struct dvb_usb_device_properties *p7500; 1778struct dvb_usb_device_properties *p7500;
1452static struct dvb_usb_device_description d7500 = { 1779static struct dvb_usb_device_description d7500 = {
1453 "Prof 7500 USB DVB-S2", 1780 "Prof 7500 USB DVB-S2",
@@ -1455,17 +1782,97 @@ static struct dvb_usb_device_description d7500 = {
1455 {NULL}, 1782 {NULL},
1456}; 1783};
1457 1784
1785static struct dvb_usb_device_properties su3000_properties = {
1786 .caps = DVB_USB_IS_AN_I2C_ADAPTER,
1787 .usb_ctrl = DEVICE_SPECIFIC,
1788 .size_of_priv = sizeof(struct su3000_state),
1789 .power_ctrl = su3000_power_ctrl,
1790 .num_adapters = 1,
1791 .identify_state = su3000_identify_state,
1792 .i2c_algo = &su3000_i2c_algo,
1793
1794 .rc.legacy = {
1795 .rc_map_table = rc_map_su3000_table,
1796 .rc_map_size = ARRAY_SIZE(rc_map_su3000_table),
1797 .rc_interval = 150,
1798 .rc_query = dw2102_rc_query,
1799 },
1800
1801 .read_mac_address = su3000_read_mac_address,
1802
1803 .generic_bulk_ctrl_endpoint = 0x01,
1804
1805 .adapter = {
1806 {
1807 .streaming_ctrl = su3000_streaming_ctrl,
1808 .frontend_attach = su3000_frontend_attach,
1809 .stream = {
1810 .type = USB_BULK,
1811 .count = 8,
1812 .endpoint = 0x82,
1813 .u = {
1814 .bulk = {
1815 .buffersize = 4096,
1816 }
1817 }
1818 }
1819 }
1820 },
1821 .num_device_descs = 3,
1822 .devices = {
1823 { "SU3000HD DVB-S USB2.0",
1824 { &dw2102_table[10], NULL },
1825 { NULL },
1826 },
1827 { "Terratec Cinergy S2 USB HD",
1828 { &dw2102_table[11], NULL },
1829 { NULL },
1830 },
1831 { "X3M TV SPC1400HD PCI",
1832 { &dw2102_table[14], NULL },
1833 { NULL },
1834 },
1835 }
1836};
1837
1458static int dw2102_probe(struct usb_interface *intf, 1838static int dw2102_probe(struct usb_interface *intf,
1459 const struct usb_device_id *id) 1839 const struct usb_device_id *id)
1460{ 1840{
1841 p1100 = kzalloc(sizeof(struct dvb_usb_device_properties), GFP_KERNEL);
1842 if (!p1100)
1843 return -ENOMEM;
1844 /* copy default structure */
1845 memcpy(p1100, &s6x0_properties,
1846 sizeof(struct dvb_usb_device_properties));
1847 /* fill only different fields */
1848 p1100->firmware = "dvb-usb-p1100.fw";
1849 p1100->devices[0] = d1100;
1850 p1100->rc.legacy.rc_map_table = rc_map_tbs_table;
1851 p1100->rc.legacy.rc_map_size = ARRAY_SIZE(rc_map_tbs_table);
1852 p1100->adapter->frontend_attach = stv0288_frontend_attach;
1853
1854 s660 = kzalloc(sizeof(struct dvb_usb_device_properties), GFP_KERNEL);
1855 if (!s660) {
1856 kfree(p1100);
1857 return -ENOMEM;
1858 }
1859 memcpy(s660, &s6x0_properties,
1860 sizeof(struct dvb_usb_device_properties));
1861 s660->firmware = "dvb-usb-s660.fw";
1862 s660->num_device_descs = 3;
1863 s660->devices[0] = d660;
1864 s660->devices[1] = d480_1;
1865 s660->devices[2] = d480_2;
1866 s660->adapter->frontend_attach = ds3000_frontend_attach;
1461 1867
1462 p7500 = kzalloc(sizeof(struct dvb_usb_device_properties), GFP_KERNEL); 1868 p7500 = kzalloc(sizeof(struct dvb_usb_device_properties), GFP_KERNEL);
1463 if (!p7500) 1869 if (!p7500) {
1870 kfree(p1100);
1871 kfree(s660);
1464 return -ENOMEM; 1872 return -ENOMEM;
1465 /* copy default structure */ 1873 }
1466 memcpy(p7500, &s6x0_properties, 1874 memcpy(p7500, &s6x0_properties,
1467 sizeof(struct dvb_usb_device_properties)); 1875 sizeof(struct dvb_usb_device_properties));
1468 /* fill only different fields */
1469 p7500->firmware = "dvb-usb-p7500.fw"; 1876 p7500->firmware = "dvb-usb-p7500.fw";
1470 p7500->devices[0] = d7500; 1877 p7500->devices[0] = d7500;
1471 p7500->rc.legacy.rc_map_table = rc_map_tbs_table; 1878 p7500->rc.legacy.rc_map_table = rc_map_tbs_table;
@@ -1480,8 +1887,14 @@ static int dw2102_probe(struct usb_interface *intf,
1480 THIS_MODULE, NULL, adapter_nr) || 1887 THIS_MODULE, NULL, adapter_nr) ||
1481 0 == dvb_usb_device_init(intf, &s6x0_properties, 1888 0 == dvb_usb_device_init(intf, &s6x0_properties,
1482 THIS_MODULE, NULL, adapter_nr) || 1889 THIS_MODULE, NULL, adapter_nr) ||
1890 0 == dvb_usb_device_init(intf, p1100,
1891 THIS_MODULE, NULL, adapter_nr) ||
1892 0 == dvb_usb_device_init(intf, s660,
1893 THIS_MODULE, NULL, adapter_nr) ||
1483 0 == dvb_usb_device_init(intf, p7500, 1894 0 == dvb_usb_device_init(intf, p7500,
1484 THIS_MODULE, NULL, adapter_nr)) 1895 THIS_MODULE, NULL, adapter_nr) ||
1896 0 == dvb_usb_device_init(intf, &su3000_properties,
1897 THIS_MODULE, NULL, adapter_nr))
1485 return 0; 1898 return 0;
1486 1899
1487 return -ENODEV; 1900 return -ENODEV;
@@ -1514,7 +1927,8 @@ module_exit(dw2102_module_exit);
1514MODULE_AUTHOR("Igor M. Liplianin (c) liplianin@me.by"); 1927MODULE_AUTHOR("Igor M. Liplianin (c) liplianin@me.by");
1515MODULE_DESCRIPTION("Driver for DVBWorld DVB-S 2101, 2102, DVB-S2 2104," 1928MODULE_DESCRIPTION("Driver for DVBWorld DVB-S 2101, 2102, DVB-S2 2104,"
1516 " DVB-C 3101 USB2.0," 1929 " DVB-C 3101 USB2.0,"
1517 " TeVii S600, S630, S650, S660 USB2.0," 1930 " TeVii S600, S630, S650, S660, S480,"
1518 " Prof 1100, 7500 USB2.0 devices"); 1931 " Prof 1100, 7500 USB2.0,"
1932 " Geniatech SU3000 devices");
1519MODULE_VERSION("0.1"); 1933MODULE_VERSION("0.1");
1520MODULE_LICENSE("GPL"); 1934MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c
index 46ccd01a7696..cd26e7c1536a 100644
--- a/drivers/media/dvb/dvb-usb/lmedm04.c
+++ b/drivers/media/dvb/dvb-usb/lmedm04.c
@@ -2,7 +2,9 @@
2 * 2 *
3 * DM04/QQBOX DVB-S USB BOX LME2510C + SHARP:BS2F7HZ7395 3 * DM04/QQBOX DVB-S USB BOX LME2510C + SHARP:BS2F7HZ7395
4 * LME2510C + LG TDQY-P001F 4 * LME2510C + LG TDQY-P001F
5 * LME2510C + BS2F7HZ0194
5 * LME2510 + LG TDQY-P001F 6 * LME2510 + LG TDQY-P001F
7 * LME2510 + BS2F7HZ0194
6 * 8 *
7 * MVB7395 (LME2510C+SHARP:BS2F7HZ7395) 9 * MVB7395 (LME2510C+SHARP:BS2F7HZ7395)
8 * SHARP:BS2F7HZ7395 = (STV0288+Sharp IX2505V) 10 * SHARP:BS2F7HZ7395 = (STV0288+Sharp IX2505V)
@@ -12,20 +14,22 @@
12 * 14 *
13 * MVB0001F (LME2510C+LGTDQT-P001F) 15 * MVB0001F (LME2510C+LGTDQT-P001F)
14 * 16 *
17 * MV0194 (LME2510+SHARP:BS2F7HZ0194)
18 * SHARP:BS2F7HZ0194 = (STV0299+IX2410)
19 *
20 * MVB0194 (LME2510C+SHARP0194)
21 *
15 * For firmware see Documentation/dvb/lmedm04.txt 22 * For firmware see Documentation/dvb/lmedm04.txt
16 * 23 *
17 * I2C addresses: 24 * I2C addresses:
18 * 0xd0 - STV0288 - Demodulator 25 * 0xd0 - STV0288 - Demodulator
19 * 0xc0 - Sharp IX2505V - Tuner 26 * 0xc0 - Sharp IX2505V - Tuner
20 * --or-- 27 * --
21 * 0x1c - TDA10086 - Demodulator 28 * 0x1c - TDA10086 - Demodulator
22 * 0xc0 - TDA8263 - Tuner 29 * 0xc0 - TDA8263 - Tuner
23 * 30 * --
24 * ***Please Note*** 31 * 0xd0 - STV0299 - Demodulator
25 * There are other variants of the DM04 32 * 0xc0 - IX2410 - Tuner
26 * ***NOT SUPPORTED***
27 * MV0194 (LME2510+SHARP0194)
28 * MVB0194 (LME2510C+SHARP0194)
29 * 33 *
30 * 34 *
31 * VID = 3344 PID LME2510=1122 LME2510C=1120 35 * VID = 3344 PID LME2510=1122 LME2510C=1120
@@ -55,6 +59,9 @@
55 * 59 *
56 * QQbox suffers from noise on LNB voltage. 60 * QQbox suffers from noise on LNB voltage.
57 * 61 *
62 * LME2510: SHARP:BS2F7HZ0194(MV0194) cannot cold reset and share system
63 * with other tuners. After a cold reset streaming will not start.
64 *
58 * PID functions have been removed from this driver version due to 65 * PID functions have been removed from this driver version due to
59 * problems with different firmware and application versions. 66 * problems with different firmware and application versions.
60 */ 67 */
@@ -69,6 +76,9 @@
69#include "tda10086.h" 76#include "tda10086.h"
70#include "stv0288.h" 77#include "stv0288.h"
71#include "ix2505v.h" 78#include "ix2505v.h"
79#include "stv0299.h"
80#include "dvb-pll.h"
81#include "z0194a.h"
72 82
73 83
74 84
@@ -96,8 +106,11 @@ MODULE_PARM_DESC(firmware, "set default firmware 0=Sharp7395 1=LG");
96 106
97 107
98DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 108DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
109
110#define TUNER_DEFAULT 0x0
99#define TUNER_LG 0x1 111#define TUNER_LG 0x1
100#define TUNER_S7395 0x2 112#define TUNER_S7395 0x2
113#define TUNER_S0194 0x3
101 114
102struct lme2510_state { 115struct lme2510_state {
103 u8 id; 116 u8 id;
@@ -191,7 +204,7 @@ static int lme2510_stream_restart(struct dvb_usb_device *d)
191 rbuff, sizeof(rbuff)); 204 rbuff, sizeof(rbuff));
192 return ret; 205 return ret;
193} 206}
194static int lme2510_remote_keypress(struct dvb_usb_adapter *adap, u16 keypress) 207static int lme2510_remote_keypress(struct dvb_usb_adapter *adap, u32 keypress)
195{ 208{
196 struct dvb_usb_device *d = adap->dev; 209 struct dvb_usb_device *d = adap->dev;
197 210
@@ -237,7 +250,8 @@ static void lme2510_int_response(struct urb *lme_urb)
237 case 0xaa: 250 case 0xaa:
238 debug_data_snipet(1, "INT Remote data snipet in", ibuf); 251 debug_data_snipet(1, "INT Remote data snipet in", ibuf);
239 lme2510_remote_keypress(adap, 252 lme2510_remote_keypress(adap,
240 (u16)(ibuf[4]<<8)+ibuf[5]); 253 (u32)(ibuf[2] << 24) + (ibuf[3] << 16) +
254 (ibuf[4] << 8) + ibuf[5]);
241 break; 255 break;
242 case 0xbb: 256 case 0xbb:
243 switch (st->tuner_config) { 257 switch (st->tuner_config) {
@@ -249,6 +263,7 @@ static void lme2510_int_response(struct urb *lme_urb)
249 st->time_key = ibuf[7]; 263 st->time_key = ibuf[7];
250 break; 264 break;
251 case TUNER_S7395: 265 case TUNER_S7395:
266 case TUNER_S0194:
252 /* Tweak for earlier firmware*/ 267 /* Tweak for earlier firmware*/
253 if (ibuf[1] == 0x03) { 268 if (ibuf[1] == 0x03) {
254 if (ibuf[2] > 1) 269 if (ibuf[2] > 1)
@@ -364,6 +379,18 @@ static int lme2510_msg(struct dvb_usb_device *d,
364 msleep(5); 379 msleep(5);
365 } 380 }
366 break; 381 break;
382 case TUNER_S0194:
383 if (wbuf[2] == 0xd0) {
384 if (wbuf[3] == 0x1b) {
385 st->signal_lock = rbuf[1];
386 if ((st->stream_on & 1) &&
387 (st->signal_lock & 0x8)) {
388 lme2510_stream_restart(d);
389 st->i2c_talk_onoff = 0;
390 }
391 }
392 }
393 break;
367 default: 394 default:
368 break; 395 break;
369 } 396 }
@@ -423,6 +450,34 @@ static int lme2510_msg(struct dvb_usb_device *d,
423 break; 450 break;
424 } 451 }
425 break; 452 break;
453 case TUNER_S0194:
454 switch (wbuf[3]) {
455 case 0x18:
456 rbuf[0] = 0x55;
457 rbuf[1] = (st->signal_level & 0x80)
458 ? 0 : (st->signal_level * 2);
459 break;
460 case 0x24:
461 rbuf[0] = 0x55;
462 rbuf[1] = st->signal_sn;
463 break;
464 case 0x1b:
465 rbuf[0] = 0x55;
466 rbuf[1] = st->signal_lock;
467 break;
468 case 0x19:
469 case 0x25:
470 case 0x1e:
471 case 0x1d:
472 rbuf[0] = 0x55;
473 rbuf[1] = 0x00;
474 break;
475 default:
476 lme2510_usb_talk(d, wbuf, wlen, rbuf, rlen);
477 st->i2c_talk_onoff = 1;
478 break;
479 }
480 break;
426 default: 481 default:
427 break; 482 break;
428 } 483 }
@@ -517,17 +572,14 @@ static int lme2510_identify_state(struct usb_device *udev,
517 struct dvb_usb_device_description **desc, 572 struct dvb_usb_device_description **desc,
518 int *cold) 573 int *cold)
519{ 574{
520 if (lme2510_return_status(udev) == 0x44) 575 *cold = 0;
521 *cold = 1;
522 else
523 *cold = 0;
524 return 0; 576 return 0;
525} 577}
526 578
527static int lme2510_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) 579static int lme2510_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff)
528{ 580{
529 struct lme2510_state *st = adap->dev->priv; 581 struct lme2510_state *st = adap->dev->priv;
530 static u8 clear_reg_3[] = LME_CLEAR_PID; 582 static u8 clear_reg_3[] = LME_CLEAR_PID;
531 static u8 rbuf[1]; 583 static u8 rbuf[1];
532 int ret = 0, rlen = sizeof(rbuf); 584 int ret = 0, rlen = sizeof(rbuf);
533 585
@@ -658,9 +710,6 @@ static int lme2510_download_firmware(struct usb_device *dev,
658 return (ret < 0) ? -ENODEV : 0; 710 return (ret < 0) ? -ENODEV : 0;
659} 711}
660 712
661/* Default firmware for LME2510C */
662char lme_firmware[50] = "dvb-usb-lme2510c-s7395.fw";
663
664static void lme_coldreset(struct usb_device *dev) 713static void lme_coldreset(struct usb_device *dev)
665{ 714{
666 int ret = 0, len_in; 715 int ret = 0, len_in;
@@ -678,49 +727,83 @@ static void lme_coldreset(struct usb_device *dev)
678static int lme_firmware_switch(struct usb_device *udev, int cold) 727static int lme_firmware_switch(struct usb_device *udev, int cold)
679{ 728{
680 const struct firmware *fw = NULL; 729 const struct firmware *fw = NULL;
681 char lme2510c_s7395[] = "dvb-usb-lme2510c-s7395.fw"; 730 const char fw_c_s7395[] = "dvb-usb-lme2510c-s7395.fw";
682 char lme2510c_lg[] = "dvb-usb-lme2510c-lg.fw"; 731 const char fw_c_lg[] = "dvb-usb-lme2510c-lg.fw";
683 char *firm_msg[] = {"Loading", "Switching to"}; 732 const char fw_c_s0194[] = "dvb-usb-lme2510c-s0194.fw";
684 int ret; 733 const char fw_lg[] = "dvb-usb-lme2510-lg.fw";
734 const char fw_s0194[] = "dvb-usb-lme2510-s0194.fw";
735 const char *fw_lme;
736 int ret, cold_fw;
685 737
686 cold = (cold > 0) ? (cold & 1) : 0; 738 cold = (cold > 0) ? (cold & 1) : 0;
687 739
688 if (udev->descriptor.idProduct == 0x1122) 740 cold_fw = !cold;
689 return 0;
690 741
691 switch (dvb_usb_lme2510_firmware) { 742 if (udev->descriptor.idProduct == 0x1122) {
692 case 0: 743 switch (dvb_usb_lme2510_firmware) {
693 default: 744 default:
694 memcpy(&lme_firmware, lme2510c_s7395, sizeof(lme2510c_s7395)); 745 dvb_usb_lme2510_firmware = TUNER_S0194;
695 ret = request_firmware(&fw, lme_firmware, &udev->dev); 746 case TUNER_S0194:
696 if (ret == 0) { 747 fw_lme = fw_s0194;
697 info("FRM %s S7395 Firmware", firm_msg[cold]); 748 ret = request_firmware(&fw, fw_lme, &udev->dev);
749 if (ret == 0) {
750 cold = 0;/*lme2510-s0194 cannot cold reset*/
751 break;
752 }
753 dvb_usb_lme2510_firmware = TUNER_LG;
754 case TUNER_LG:
755 fw_lme = fw_lg;
756 ret = request_firmware(&fw, fw_lme, &udev->dev);
757 if (ret == 0)
758 break;
759 info("FRM No Firmware Found - please install");
760 dvb_usb_lme2510_firmware = TUNER_DEFAULT;
761 cold = 0;
762 cold_fw = 0;
698 break; 763 break;
699 } 764 }
700 if (cold == 0) 765 } else {
701 dvb_usb_lme2510_firmware = 1; 766 switch (dvb_usb_lme2510_firmware) {
702 else 767 default:
768 dvb_usb_lme2510_firmware = TUNER_S7395;
769 case TUNER_S7395:
770 fw_lme = fw_c_s7395;
771 ret = request_firmware(&fw, fw_lme, &udev->dev);
772 if (ret == 0)
773 break;
774 dvb_usb_lme2510_firmware = TUNER_LG;
775 case TUNER_LG:
776 fw_lme = fw_c_lg;
777 ret = request_firmware(&fw, fw_lme, &udev->dev);
778 if (ret == 0)
779 break;
780 dvb_usb_lme2510_firmware = TUNER_S0194;
781 case TUNER_S0194:
782 fw_lme = fw_c_s0194;
783 ret = request_firmware(&fw, fw_lme, &udev->dev);
784 if (ret == 0)
785 break;
786 info("FRM No Firmware Found - please install");
787 dvb_usb_lme2510_firmware = TUNER_DEFAULT;
703 cold = 0; 788 cold = 0;
704 case 1: 789 cold_fw = 0;
705 memcpy(&lme_firmware, lme2510c_lg, sizeof(lme2510c_lg));
706 ret = request_firmware(&fw, lme_firmware, &udev->dev);
707 if (ret == 0) {
708 info("FRM %s LG Firmware", firm_msg[cold]);
709 break; 790 break;
710 } 791 }
711 info("FRM No Firmware Found - please install");
712 dvb_usb_lme2510_firmware = 0;
713 cold = 0;
714 break;
715 } 792 }
716 793
717 release_firmware(fw); 794 if (cold_fw) {
795 info("FRM Loading %s file", fw_lme);
796 ret = lme2510_download_firmware(udev, fw);
797 }
718 798
719 if (cold) { 799 if (cold) {
800 info("FRM Changing to %s firmware", fw_lme);
720 lme_coldreset(udev); 801 lme_coldreset(udev);
721 return -ENODEV; 802 return -ENODEV;
722 } 803 }
723 804
805 release_firmware(fw);
806
724 return ret; 807 return ret;
725} 808}
726 809
@@ -758,6 +841,18 @@ static struct ix2505v_config lme_tuner = {
758 .tuner_chargepump = 0x3, 841 .tuner_chargepump = 0x3,
759}; 842};
760 843
844static struct stv0299_config sharp_z0194_config = {
845 .demod_address = 0xd0,
846 .inittab = sharp_z0194a_inittab,
847 .mclk = 88000000UL,
848 .invert = 0,
849 .skip_reinit = 0,
850 .lock_output = STV0299_LOCKOUTPUT_1,
851 .volt13_op0_op1 = STV0299_VOLT13_OP1,
852 .min_delay_ms = 100,
853 .set_symbol_rate = sharp_z0194a_set_symbol_rate,
854};
855
761static int dm04_lme2510_set_voltage(struct dvb_frontend *fe, 856static int dm04_lme2510_set_voltage(struct dvb_frontend *fe,
762 fe_sec_voltage_t voltage) 857 fe_sec_voltage_t voltage)
763{ 858{
@@ -793,7 +888,8 @@ static int lme_name(struct dvb_usb_adapter *adap)
793{ 888{
794 struct lme2510_state *st = adap->dev->priv; 889 struct lme2510_state *st = adap->dev->priv;
795 const char *desc = adap->dev->desc->name; 890 const char *desc = adap->dev->desc->name;
796 char *fe_name[] = {"", " LG TDQY-P001F", " SHARP:BS2F7HZ7395"}; 891 char *fe_name[] = {"", " LG TDQY-P001F", " SHARP:BS2F7HZ7395",
892 " SHARP:BS2F7HZ0194"};
797 char *name = adap->fe->ops.info.name; 893 char *name = adap->fe->ops.info.name;
798 894
799 strlcpy(name, desc, 128); 895 strlcpy(name, desc, 128);
@@ -820,26 +916,40 @@ static int dm04_lme2510_frontend_attach(struct dvb_usb_adapter *adap)
820 st->i2c_tuner_gate_r = 4; 916 st->i2c_tuner_gate_r = 4;
821 st->i2c_tuner_addr = 0xc0; 917 st->i2c_tuner_addr = 0xc0;
822 st->tuner_config = TUNER_LG; 918 st->tuner_config = TUNER_LG;
823 if (dvb_usb_lme2510_firmware != 1) { 919 if (dvb_usb_lme2510_firmware != TUNER_LG) {
824 dvb_usb_lme2510_firmware = 1; 920 dvb_usb_lme2510_firmware = TUNER_LG;
825 ret = lme_firmware_switch(adap->dev->udev, 1); 921 ret = lme_firmware_switch(adap->dev->udev, 1);
826 } else /*stops LG/Sharp multi tuner problems*/ 922 }
827 dvb_usb_lme2510_firmware = 0; 923 goto end;
924 }
925
926 st->i2c_gate = 4;
927 adap->fe = dvb_attach(stv0299_attach, &sharp_z0194_config,
928 &adap->dev->i2c_adap);
929 if (adap->fe) {
930 info("FE Found Stv0299");
931 st->i2c_tuner_gate_w = 4;
932 st->i2c_tuner_gate_r = 5;
933 st->i2c_tuner_addr = 0xc0;
934 st->tuner_config = TUNER_S0194;
935 if (dvb_usb_lme2510_firmware != TUNER_S0194) {
936 dvb_usb_lme2510_firmware = TUNER_S0194;
937 ret = lme_firmware_switch(adap->dev->udev, 1);
938 }
828 goto end; 939 goto end;
829 } 940 }
830 941
831 st->i2c_gate = 5; 942 st->i2c_gate = 5;
832 adap->fe = dvb_attach(stv0288_attach, &lme_config, 943 adap->fe = dvb_attach(stv0288_attach, &lme_config,
833 &adap->dev->i2c_adap); 944 &adap->dev->i2c_adap);
834
835 if (adap->fe) { 945 if (adap->fe) {
836 info("FE Found Stv0288"); 946 info("FE Found Stv0288");
837 st->i2c_tuner_gate_w = 4; 947 st->i2c_tuner_gate_w = 4;
838 st->i2c_tuner_gate_r = 5; 948 st->i2c_tuner_gate_r = 5;
839 st->i2c_tuner_addr = 0xc0; 949 st->i2c_tuner_addr = 0xc0;
840 st->tuner_config = TUNER_S7395; 950 st->tuner_config = TUNER_S7395;
841 if (dvb_usb_lme2510_firmware != 0) { 951 if (dvb_usb_lme2510_firmware != TUNER_S7395) {
842 dvb_usb_lme2510_firmware = 0; 952 dvb_usb_lme2510_firmware = TUNER_S7395;
843 ret = lme_firmware_switch(adap->dev->udev, 1); 953 ret = lme_firmware_switch(adap->dev->udev, 1);
844 } 954 }
845 } else { 955 } else {
@@ -847,6 +957,7 @@ static int dm04_lme2510_frontend_attach(struct dvb_usb_adapter *adap)
847 return -ENODEV; 957 return -ENODEV;
848 } 958 }
849 959
960
850end: if (ret) { 961end: if (ret) {
851 kfree(adap->fe); 962 kfree(adap->fe);
852 adap->fe = NULL; 963 adap->fe = NULL;
@@ -855,14 +966,13 @@ end: if (ret) {
855 966
856 adap->fe->ops.set_voltage = dm04_lme2510_set_voltage; 967 adap->fe->ops.set_voltage = dm04_lme2510_set_voltage;
857 ret = lme_name(adap); 968 ret = lme_name(adap);
858
859 return ret; 969 return ret;
860} 970}
861 971
862static int dm04_lme2510_tuner(struct dvb_usb_adapter *adap) 972static int dm04_lme2510_tuner(struct dvb_usb_adapter *adap)
863{ 973{
864 struct lme2510_state *st = adap->dev->priv; 974 struct lme2510_state *st = adap->dev->priv;
865 char *tun_msg[] = {"", "TDA8263", "IX2505V"}; 975 char *tun_msg[] = {"", "TDA8263", "IX2505V", "DVB_PLL_OPERA"};
866 int ret = 0; 976 int ret = 0;
867 977
868 switch (st->tuner_config) { 978 switch (st->tuner_config) {
@@ -876,6 +986,11 @@ static int dm04_lme2510_tuner(struct dvb_usb_adapter *adap)
876 &adap->dev->i2c_adap)) 986 &adap->dev->i2c_adap))
877 ret = st->tuner_config; 987 ret = st->tuner_config;
878 break; 988 break;
989 case TUNER_S0194:
990 if (dvb_attach(dvb_pll_attach , adap->fe, 0xc0,
991 &adap->dev->i2c_adap, DVB_PLL_OPERA1))
992 ret = st->tuner_config;
993 break;
879 default: 994 default:
880 break; 995 break;
881 } 996 }
@@ -936,7 +1051,10 @@ static int lme2510_probe(struct usb_interface *intf,
936 return -ENODEV; 1051 return -ENODEV;
937 } 1052 }
938 1053
939 lme_firmware_switch(udev, 0); 1054 if (lme2510_return_status(udev) == 0x44) {
1055 lme_firmware_switch(udev, 0);
1056 return -ENODEV;
1057 }
940 1058
941 if (0 == dvb_usb_device_init(intf, &lme2510_properties, 1059 if (0 == dvb_usb_device_init(intf, &lme2510_properties,
942 THIS_MODULE, NULL, adapter_nr)) { 1060 THIS_MODULE, NULL, adapter_nr)) {
@@ -964,10 +1082,6 @@ MODULE_DEVICE_TABLE(usb, lme2510_table);
964 1082
965static struct dvb_usb_device_properties lme2510_properties = { 1083static struct dvb_usb_device_properties lme2510_properties = {
966 .caps = DVB_USB_IS_AN_I2C_ADAPTER, 1084 .caps = DVB_USB_IS_AN_I2C_ADAPTER,
967 .usb_ctrl = DEVICE_SPECIFIC,
968 .download_firmware = lme2510_download_firmware,
969 .firmware = "dvb-usb-lme2510-lg.fw",
970
971 .size_of_priv = sizeof(struct lme2510_state), 1085 .size_of_priv = sizeof(struct lme2510_state),
972 .num_adapters = 1, 1086 .num_adapters = 1,
973 .adapter = { 1087 .adapter = {
@@ -1004,9 +1118,6 @@ static struct dvb_usb_device_properties lme2510_properties = {
1004 1118
1005static struct dvb_usb_device_properties lme2510c_properties = { 1119static struct dvb_usb_device_properties lme2510c_properties = {
1006 .caps = DVB_USB_IS_AN_I2C_ADAPTER, 1120 .caps = DVB_USB_IS_AN_I2C_ADAPTER,
1007 .usb_ctrl = DEVICE_SPECIFIC,
1008 .download_firmware = lme2510_download_firmware,
1009 .firmware = (const char *)&lme_firmware,
1010 .size_of_priv = sizeof(struct lme2510_state), 1121 .size_of_priv = sizeof(struct lme2510_state),
1011 .num_adapters = 1, 1122 .num_adapters = 1,
1012 .adapter = { 1123 .adapter = {
@@ -1109,5 +1220,5 @@ module_exit(lme2510_module_exit);
1109 1220
1110MODULE_AUTHOR("Malcolm Priestley <tvboxspy@gmail.com>"); 1221MODULE_AUTHOR("Malcolm Priestley <tvboxspy@gmail.com>");
1111MODULE_DESCRIPTION("LME2510(C) DVB-S USB2.0"); 1222MODULE_DESCRIPTION("LME2510(C) DVB-S USB2.0");
1112MODULE_VERSION("1.75"); 1223MODULE_VERSION("1.80");
1113MODULE_LICENSE("GPL"); 1224MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/opera1.c b/drivers/media/dvb/dvb-usb/opera1.c
index 1f1b7d6980a5..7e569f4dd80b 100644
--- a/drivers/media/dvb/dvb-usb/opera1.c
+++ b/drivers/media/dvb/dvb-usb/opera1.c
@@ -342,23 +342,22 @@ static struct rc_map_table rc_map_opera1_table[] = {
342 {0x49b6, KEY_8}, 342 {0x49b6, KEY_8},
343 {0x05fa, KEY_9}, 343 {0x05fa, KEY_9},
344 {0x45ba, KEY_0}, 344 {0x45ba, KEY_0},
345 {0x09f6, KEY_UP}, /*chanup */ 345 {0x09f6, KEY_CHANNELUP}, /*chanup */
346 {0x1be5, KEY_DOWN}, /*chandown */ 346 {0x1be5, KEY_CHANNELDOWN}, /*chandown */
347 {0x5da3, KEY_LEFT}, /*voldown */ 347 {0x5da3, KEY_VOLUMEDOWN}, /*voldown */
348 {0x5fa1, KEY_RIGHT}, /*volup */ 348 {0x5fa1, KEY_VOLUMEUP}, /*volup */
349 {0x07f8, KEY_SPACE}, /*tab */ 349 {0x07f8, KEY_SPACE}, /*tab */
350 {0x1fe1, KEY_ENTER}, /*play ok */ 350 {0x1fe1, KEY_OK}, /*play ok */
351 {0x1be4, KEY_Z}, /*zoom */ 351 {0x1be4, KEY_ZOOM}, /*zoom */
352 {0x59a6, KEY_M}, /*mute */ 352 {0x59a6, KEY_MUTE}, /*mute */
353 {0x5ba5, KEY_F}, /*tv/f */ 353 {0x5ba5, KEY_RADIO}, /*tv/f */
354 {0x19e7, KEY_R}, /*rec */ 354 {0x19e7, KEY_RECORD}, /*rec */
355 {0x01fe, KEY_S}, /*Stop */ 355 {0x01fe, KEY_STOP}, /*Stop */
356 {0x03fd, KEY_P}, /*pause */ 356 {0x03fd, KEY_PAUSE}, /*pause */
357 {0x03fc, KEY_W}, /*<- -> */ 357 {0x03fc, KEY_SCREEN}, /*<- -> */
358 {0x07f9, KEY_C}, /*capture */ 358 {0x07f9, KEY_CAMERA}, /*capture */
359 {0x47b9, KEY_Q}, /*exit */ 359 {0x47b9, KEY_ESC}, /*exit */
360 {0x43bc, KEY_O}, /*power */ 360 {0x43bc, KEY_POWER2}, /*power */
361
362}; 361};
363 362
364static int opera1_rc_query(struct dvb_usb_device *dev, u32 * event, int *state) 363static int opera1_rc_query(struct dvb_usb_device *dev, u32 * event, int *state)
diff --git a/drivers/media/dvb/dvb-usb/technisat-usb2.c b/drivers/media/dvb/dvb-usb/technisat-usb2.c
new file mode 100644
index 000000000000..08f8842ad280
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/technisat-usb2.c
@@ -0,0 +1,807 @@
1/*
2 * Linux driver for Technisat DVB-S/S2 USB 2.0 device
3 *
4 * Copyright (C) 2010 Patrick Boettcher,
5 * Kernel Labs Inc. PO Box 745, St James, NY 11780
6 *
7 * Development was sponsored by Technisat Digital UK Limited, whose
8 * registered office is Witan Gate House 500 - 600 Witan Gate West,
9 * Milton Keynes, MK9 1SH
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 * THIS PROGRAM IS PROVIDED "AS IS" AND BOTH THE COPYRIGHT HOLDER AND
22 * TECHNISAT DIGITAL UK LTD DISCLAIM ALL WARRANTIES WITH REGARD TO
23 * THIS PROGRAM INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY OR
24 * FITNESS FOR A PARTICULAR PURPOSE. NEITHER THE COPYRIGHT HOLDER
25 * NOR TECHNISAT DIGITAL UK LIMITED SHALL BE LIABLE FOR ANY SPECIAL,
26 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
27 * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
28 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR
29 * IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS PROGRAM. See the
30 * GNU General Public License for more details.
31 */
32
33#define DVB_USB_LOG_PREFIX "technisat-usb2"
34#include "dvb-usb.h"
35
36#include "stv6110x.h"
37#include "stv090x.h"
38
39/* module parameters */
40DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
41
42static int debug;
43module_param(debug, int, 0644);
44MODULE_PARM_DESC(debug,
45 "set debugging level (bit-mask: 1=info,2=eeprom,4=i2c,8=rc)." \
46 DVB_USB_DEBUG_STATUS);
47
48/* disables all LED control command and
49 * also does not start the signal polling thread */
50static int disable_led_control;
51module_param(disable_led_control, int, 0444);
52MODULE_PARM_DESC(disable_led_control,
53 "disable LED control of the device "
54 "(default: 0 - LED control is active).");
55
56/* device private data */
57struct technisat_usb2_state {
58 struct dvb_usb_device *dev;
59 struct delayed_work green_led_work;
60 u8 power_state;
61
62 u16 last_scan_code;
63};
64
65/* debug print helpers */
66#define deb_info(args...) dprintk(debug, 0x01, args)
67#define deb_eeprom(args...) dprintk(debug, 0x02, args)
68#define deb_i2c(args...) dprintk(debug, 0x04, args)
69#define deb_rc(args...) dprintk(debug, 0x08, args)
70
71/* vendor requests */
72#define SET_IFCLK_TO_EXTERNAL_TSCLK_VENDOR_REQUEST 0xB3
73#define SET_FRONT_END_RESET_VENDOR_REQUEST 0xB4
74#define GET_VERSION_INFO_VENDOR_REQUEST 0xB5
75#define SET_GREEN_LED_VENDOR_REQUEST 0xB6
76#define SET_RED_LED_VENDOR_REQUEST 0xB7
77#define GET_IR_DATA_VENDOR_REQUEST 0xB8
78#define SET_LED_TIMER_DIVIDER_VENDOR_REQUEST 0xB9
79#define SET_USB_REENUMERATION 0xBA
80
81/* i2c-access methods */
82#define I2C_SPEED_100KHZ_BIT 0x40
83
84#define I2C_STATUS_NAK 7
85#define I2C_STATUS_OK 8
86
87static int technisat_usb2_i2c_access(struct usb_device *udev,
88 u8 device_addr, u8 *tx, u8 txlen, u8 *rx, u8 rxlen)
89{
90 u8 b[64];
91 int ret, actual_length;
92
93 deb_i2c("i2c-access: %02x, tx: ", device_addr);
94 debug_dump(tx, txlen, deb_i2c);
95 deb_i2c(" ");
96
97 if (txlen > 62) {
98 err("i2c TX buffer can't exceed 62 bytes (dev 0x%02x)",
99 device_addr);
100 txlen = 62;
101 }
102 if (rxlen > 62) {
103 err("i2c RX buffer can't exceed 62 bytes (dev 0x%02x)",
104 device_addr);
105 txlen = 62;
106 }
107
108 b[0] = I2C_SPEED_100KHZ_BIT;
109 b[1] = device_addr << 1;
110
111 if (rx != NULL) {
112 b[0] |= rxlen;
113 b[1] |= 1;
114 }
115
116 memcpy(&b[2], tx, txlen);
117 ret = usb_bulk_msg(udev,
118 usb_sndbulkpipe(udev, 0x01),
119 b, 2 + txlen,
120 NULL, 1000);
121
122 if (ret < 0) {
123 err("i2c-error: out failed %02x = %d", device_addr, ret);
124 return -ENODEV;
125 }
126
127 ret = usb_bulk_msg(udev,
128 usb_rcvbulkpipe(udev, 0x01),
129 b, 64, &actual_length, 1000);
130 if (ret < 0) {
131 err("i2c-error: in failed %02x = %d", device_addr, ret);
132 return -ENODEV;
133 }
134
135 if (b[0] != I2C_STATUS_OK) {
136 err("i2c-error: %02x = %d", device_addr, b[0]);
137 /* handle tuner-i2c-nak */
138 if (!(b[0] == I2C_STATUS_NAK &&
139 device_addr == 0x60
140 /* && device_is_technisat_usb2 */))
141 return -ENODEV;
142 }
143
144 deb_i2c("status: %d, ", b[0]);
145
146 if (rx != NULL) {
147 memcpy(rx, &b[2], rxlen);
148
149 deb_i2c("rx (%d): ", rxlen);
150 debug_dump(rx, rxlen, deb_i2c);
151 }
152
153 deb_i2c("\n");
154
155 return 0;
156}
157
158static int technisat_usb2_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
159 int num)
160{
161 int ret = 0, i;
162 struct dvb_usb_device *d = i2c_get_adapdata(adap);
163
164 /* Ensure nobody else hits the i2c bus while we're sending our
165 sequence of messages, (such as the remote control thread) */
166 if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
167 return -EAGAIN;
168
169 for (i = 0; i < num; i++) {
170 if (i+1 < num && msg[i+1].flags & I2C_M_RD) {
171 ret = technisat_usb2_i2c_access(d->udev, msg[i+1].addr,
172 msg[i].buf, msg[i].len,
173 msg[i+1].buf, msg[i+1].len);
174 if (ret != 0)
175 break;
176 i++;
177 } else {
178 ret = technisat_usb2_i2c_access(d->udev, msg[i].addr,
179 msg[i].buf, msg[i].len,
180 NULL, 0);
181 if (ret != 0)
182 break;
183 }
184 }
185
186 if (ret == 0)
187 ret = i;
188
189 mutex_unlock(&d->i2c_mutex);
190
191 return ret;
192}
193
194static u32 technisat_usb2_i2c_func(struct i2c_adapter *adapter)
195{
196 return I2C_FUNC_I2C;
197}
198
199static struct i2c_algorithm technisat_usb2_i2c_algo = {
200 .master_xfer = technisat_usb2_i2c_xfer,
201 .functionality = technisat_usb2_i2c_func,
202};
203
204#if 0
205static void technisat_usb2_frontend_reset(struct usb_device *udev)
206{
207 usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
208 SET_FRONT_END_RESET_VENDOR_REQUEST,
209 USB_TYPE_VENDOR | USB_DIR_OUT,
210 10, 0,
211 NULL, 0, 500);
212}
213#endif
214
215/* LED control */
216enum technisat_usb2_led_state {
217 LED_OFF,
218 LED_BLINK,
219 LED_ON,
220 LED_UNDEFINED
221};
222
223static int technisat_usb2_set_led(struct dvb_usb_device *d, int red, enum technisat_usb2_led_state state)
224{
225 int ret;
226
227 u8 led[8] = {
228 red ? SET_RED_LED_VENDOR_REQUEST : SET_GREEN_LED_VENDOR_REQUEST,
229 0
230 };
231
232 if (disable_led_control && state != LED_OFF)
233 return 0;
234
235 switch (state) {
236 case LED_ON:
237 led[1] = 0x82;
238 break;
239 case LED_BLINK:
240 led[1] = 0x82;
241 if (red) {
242 led[2] = 0x02;
243 led[3] = 10;
244 led[4] = 10;
245 } else {
246 led[2] = 0xff;
247 led[3] = 50;
248 led[4] = 50;
249 }
250 led[5] = 1;
251 break;
252
253 default:
254 case LED_OFF:
255 led[1] = 0x80;
256 break;
257 }
258
259 if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
260 return -EAGAIN;
261
262 ret = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0),
263 red ? SET_RED_LED_VENDOR_REQUEST : SET_GREEN_LED_VENDOR_REQUEST,
264 USB_TYPE_VENDOR | USB_DIR_OUT,
265 0, 0,
266 led, sizeof(led), 500);
267
268 mutex_unlock(&d->i2c_mutex);
269 return ret;
270}
271
272static int technisat_usb2_set_led_timer(struct dvb_usb_device *d, u8 red, u8 green)
273{
274 int ret;
275 u8 b = 0;
276
277 if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
278 return -EAGAIN;
279
280 ret = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0),
281 SET_LED_TIMER_DIVIDER_VENDOR_REQUEST,
282 USB_TYPE_VENDOR | USB_DIR_OUT,
283 (red << 8) | green, 0,
284 &b, 1, 500);
285
286 mutex_unlock(&d->i2c_mutex);
287
288 return ret;
289}
290
291static void technisat_usb2_green_led_control(struct work_struct *work)
292{
293 struct technisat_usb2_state *state =
294 container_of(work, struct technisat_usb2_state, green_led_work.work);
295 struct dvb_frontend *fe = state->dev->adapter[0].fe;
296
297 if (state->power_state == 0)
298 goto schedule;
299
300 if (fe != NULL) {
301 enum fe_status status;
302
303 if (fe->ops.read_status(fe, &status) != 0)
304 goto schedule;
305
306 if (status & FE_HAS_LOCK) {
307 u32 ber;
308
309 if (fe->ops.read_ber(fe, &ber) != 0)
310 goto schedule;
311
312 if (ber > 1000)
313 technisat_usb2_set_led(state->dev, 0, LED_BLINK);
314 else
315 technisat_usb2_set_led(state->dev, 0, LED_ON);
316 } else
317 technisat_usb2_set_led(state->dev, 0, LED_OFF);
318 }
319
320schedule:
321 schedule_delayed_work(&state->green_led_work,
322 msecs_to_jiffies(500));
323}
324
325/* method to find out whether the firmware has to be downloaded or not */
326static int technisat_usb2_identify_state(struct usb_device *udev,
327 struct dvb_usb_device_properties *props,
328 struct dvb_usb_device_description **desc, int *cold)
329{
330 int ret;
331 u8 version[3];
332
333 /* first select the interface */
334 if (usb_set_interface(udev, 0, 1) != 0)
335 err("could not set alternate setting to 0");
336 else
337 info("set alternate setting");
338
339 *cold = 0; /* by default do not download a firmware - just in case something is wrong */
340
341 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
342 GET_VERSION_INFO_VENDOR_REQUEST,
343 USB_TYPE_VENDOR | USB_DIR_IN,
344 0, 0,
345 version, sizeof(version), 500);
346
347 if (ret < 0)
348 *cold = 1;
349 else {
350 info("firmware version: %d.%d", version[1], version[2]);
351 *cold = 0;
352 }
353
354 return 0;
355}
356
357/* power control */
358static int technisat_usb2_power_ctrl(struct dvb_usb_device *d, int level)
359{
360 struct technisat_usb2_state *state = d->priv;
361
362 state->power_state = level;
363
364 if (disable_led_control)
365 return 0;
366
367 /* green led is turned off in any case - will be turned on when tuning */
368 technisat_usb2_set_led(d, 0, LED_OFF);
369 /* red led is turned on all the time */
370 technisat_usb2_set_led(d, 1, LED_ON);
371 return 0;
372}
373
374/* mac address reading - from the eeprom */
375#if 0
376static void technisat_usb2_eeprom_dump(struct dvb_usb_device *d)
377{
378 u8 reg;
379 u8 b[16];
380 int i, j;
381
382 /* full EEPROM dump */
383 for (j = 0; j < 256 * 4; j += 16) {
384 reg = j;
385 if (technisat_usb2_i2c_access(d->udev, 0x50 + j / 256, &reg, 1, b, 16) != 0)
386 break;
387
388 deb_eeprom("EEPROM: %01x%02x: ", j / 256, reg);
389 for (i = 0; i < 16; i++)
390 deb_eeprom("%02x ", b[i]);
391 deb_eeprom("\n");
392 }
393}
394#endif
395
396static u8 technisat_usb2_calc_lrc(const u8 *b, u16 length)
397{
398 u8 lrc = 0;
399 while (--length)
400 lrc ^= *b++;
401 return lrc;
402}
403
404static int technisat_usb2_eeprom_lrc_read(struct dvb_usb_device *d,
405 u16 offset, u8 *b, u16 length, u8 tries)
406{
407 u8 bo = offset & 0xff;
408 struct i2c_msg msg[] = {
409 {
410 .addr = 0x50 | ((offset >> 8) & 0x3),
411 .buf = &bo,
412 .len = 1
413 }, {
414 .addr = 0x50 | ((offset >> 8) & 0x3),
415 .flags = I2C_M_RD,
416 .buf = b,
417 .len = length
418 }
419 };
420
421 while (tries--) {
422 int status;
423
424 if (i2c_transfer(&d->i2c_adap, msg, 2) != 2)
425 break;
426
427 status =
428 technisat_usb2_calc_lrc(b, length - 1) == b[length - 1];
429
430 if (status)
431 return 0;
432 }
433
434 return -EREMOTEIO;
435}
436
437#define EEPROM_MAC_START 0x3f8
438#define EEPROM_MAC_TOTAL 8
439static int technisat_usb2_read_mac_address(struct dvb_usb_device *d,
440 u8 mac[])
441{
442 u8 buf[EEPROM_MAC_TOTAL];
443
444 if (technisat_usb2_eeprom_lrc_read(d, EEPROM_MAC_START,
445 buf, EEPROM_MAC_TOTAL, 4) != 0)
446 return -ENODEV;
447
448 memcpy(mac, buf, 6);
449 return 0;
450}
451
452/* frontend attach */
453static int technisat_usb2_set_voltage(struct dvb_frontend *fe,
454 fe_sec_voltage_t voltage)
455{
456 int i;
457 u8 gpio[3] = { 0 }; /* 0 = 2, 1 = 3, 2 = 4 */
458
459 gpio[2] = 1; /* high - voltage ? */
460
461 switch (voltage) {
462 case SEC_VOLTAGE_13:
463 gpio[0] = 1;
464 break;
465 case SEC_VOLTAGE_18:
466 gpio[0] = 1;
467 gpio[1] = 1;
468 break;
469 default:
470 case SEC_VOLTAGE_OFF:
471 break;
472 }
473
474 for (i = 0; i < 3; i++)
475 if (stv090x_set_gpio(fe, i+2, 0, gpio[i], 0) != 0)
476 return -EREMOTEIO;
477 return 0;
478}
479
480static struct stv090x_config technisat_usb2_stv090x_config = {
481 .device = STV0903,
482 .demod_mode = STV090x_SINGLE,
483 .clk_mode = STV090x_CLK_EXT,
484
485 .xtal = 8000000,
486 .address = 0x68,
487
488 .ts1_mode = STV090x_TSMODE_DVBCI,
489 .ts1_clk = 13400000,
490 .ts1_tei = 1,
491
492 .repeater_level = STV090x_RPTLEVEL_64,
493
494 .tuner_bbgain = 6,
495};
496
497static struct stv6110x_config technisat_usb2_stv6110x_config = {
498 .addr = 0x60,
499 .refclk = 16000000,
500 .clk_div = 2,
501};
502
503static int technisat_usb2_frontend_attach(struct dvb_usb_adapter *a)
504{
505 struct usb_device *udev = a->dev->udev;
506 int ret;
507
508 a->fe = dvb_attach(stv090x_attach, &technisat_usb2_stv090x_config,
509 &a->dev->i2c_adap, STV090x_DEMODULATOR_0);
510
511 if (a->fe) {
512 struct stv6110x_devctl *ctl;
513
514 ctl = dvb_attach(stv6110x_attach,
515 a->fe,
516 &technisat_usb2_stv6110x_config,
517 &a->dev->i2c_adap);
518
519 if (ctl) {
520 technisat_usb2_stv090x_config.tuner_init = ctl->tuner_init;
521 technisat_usb2_stv090x_config.tuner_sleep = ctl->tuner_sleep;
522 technisat_usb2_stv090x_config.tuner_set_mode = ctl->tuner_set_mode;
523 technisat_usb2_stv090x_config.tuner_set_frequency = ctl->tuner_set_frequency;
524 technisat_usb2_stv090x_config.tuner_get_frequency = ctl->tuner_get_frequency;
525 technisat_usb2_stv090x_config.tuner_set_bandwidth = ctl->tuner_set_bandwidth;
526 technisat_usb2_stv090x_config.tuner_get_bandwidth = ctl->tuner_get_bandwidth;
527 technisat_usb2_stv090x_config.tuner_set_bbgain = ctl->tuner_set_bbgain;
528 technisat_usb2_stv090x_config.tuner_get_bbgain = ctl->tuner_get_bbgain;
529 technisat_usb2_stv090x_config.tuner_set_refclk = ctl->tuner_set_refclk;
530 technisat_usb2_stv090x_config.tuner_get_status = ctl->tuner_get_status;
531
532 /* call the init function once to initialize
533 tuner's clock output divider and demod's
534 master clock */
535 if (a->fe->ops.init)
536 a->fe->ops.init(a->fe);
537
538 if (mutex_lock_interruptible(&a->dev->i2c_mutex) < 0)
539 return -EAGAIN;
540
541 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
542 SET_IFCLK_TO_EXTERNAL_TSCLK_VENDOR_REQUEST,
543 USB_TYPE_VENDOR | USB_DIR_OUT,
544 0, 0,
545 NULL, 0, 500);
546 mutex_unlock(&a->dev->i2c_mutex);
547
548 if (ret != 0)
549 err("could not set IF_CLK to external");
550
551 a->fe->ops.set_voltage = technisat_usb2_set_voltage;
552
553 /* if everything was successful assign a nice name to the frontend */
554 strlcpy(a->fe->ops.info.name, a->dev->desc->name,
555 sizeof(a->fe->ops.info.name));
556 } else {
557 dvb_frontend_detach(a->fe);
558 a->fe = NULL;
559 }
560 }
561
562 technisat_usb2_set_led_timer(a->dev, 1, 1);
563
564 return a->fe == NULL ? -ENODEV : 0;
565}
566
567/* Remote control */
568
569/* the device is giving providing raw IR-signals to the host mapping
570 * it only to one remote control is just the default implementation
571 */
572#define NOMINAL_IR_BIT_TRANSITION_TIME_US 889
573#define NOMINAL_IR_BIT_TIME_US (2 * NOMINAL_IR_BIT_TRANSITION_TIME_US)
574
575#define FIRMWARE_CLOCK_TICK 83333
576#define FIRMWARE_CLOCK_DIVISOR 256
577
578#define IR_PERCENT_TOLERANCE 15
579
580#define NOMINAL_IR_BIT_TRANSITION_TICKS ((NOMINAL_IR_BIT_TRANSITION_TIME_US * 1000 * 1000) / FIRMWARE_CLOCK_TICK)
581#define NOMINAL_IR_BIT_TRANSITION_TICK_COUNT (NOMINAL_IR_BIT_TRANSITION_TICKS / FIRMWARE_CLOCK_DIVISOR)
582
583#define NOMINAL_IR_BIT_TIME_TICKS ((NOMINAL_IR_BIT_TIME_US * 1000 * 1000) / FIRMWARE_CLOCK_TICK)
584#define NOMINAL_IR_BIT_TIME_TICK_COUNT (NOMINAL_IR_BIT_TIME_TICKS / FIRMWARE_CLOCK_DIVISOR)
585
586#define MINIMUM_IR_BIT_TRANSITION_TICK_COUNT (NOMINAL_IR_BIT_TRANSITION_TICK_COUNT - ((NOMINAL_IR_BIT_TRANSITION_TICK_COUNT * IR_PERCENT_TOLERANCE) / 100))
587#define MAXIMUM_IR_BIT_TRANSITION_TICK_COUNT (NOMINAL_IR_BIT_TRANSITION_TICK_COUNT + ((NOMINAL_IR_BIT_TRANSITION_TICK_COUNT * IR_PERCENT_TOLERANCE) / 100))
588
589#define MINIMUM_IR_BIT_TIME_TICK_COUNT (NOMINAL_IR_BIT_TIME_TICK_COUNT - ((NOMINAL_IR_BIT_TIME_TICK_COUNT * IR_PERCENT_TOLERANCE) / 100))
590#define MAXIMUM_IR_BIT_TIME_TICK_COUNT (NOMINAL_IR_BIT_TIME_TICK_COUNT + ((NOMINAL_IR_BIT_TIME_TICK_COUNT * IR_PERCENT_TOLERANCE) / 100))
591
592static int technisat_usb2_get_ir(struct dvb_usb_device *d)
593{
594 u8 buf[62], *b;
595 int ret;
596 struct ir_raw_event ev;
597
598 buf[0] = GET_IR_DATA_VENDOR_REQUEST;
599 buf[1] = 0x08;
600 buf[2] = 0x8f;
601 buf[3] = MINIMUM_IR_BIT_TRANSITION_TICK_COUNT;
602 buf[4] = MAXIMUM_IR_BIT_TIME_TICK_COUNT;
603
604 if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
605 return -EAGAIN;
606 ret = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0),
607 GET_IR_DATA_VENDOR_REQUEST,
608 USB_TYPE_VENDOR | USB_DIR_OUT,
609 0, 0,
610 buf, 5, 500);
611 if (ret < 0)
612 goto unlock;
613
614 buf[1] = 0;
615 buf[2] = 0;
616 ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0),
617 GET_IR_DATA_VENDOR_REQUEST,
618 USB_TYPE_VENDOR | USB_DIR_IN,
619 0x8080, 0,
620 buf, sizeof(buf), 500);
621
622unlock:
623 mutex_unlock(&d->i2c_mutex);
624
625 if (ret < 0)
626 return ret;
627
628 if (ret == 1)
629 return 0; /* no key pressed */
630
631 /* decoding */
632 b = buf+1;
633
634#if 0
635 deb_rc("RC: %d ", ret);
636 debug_dump(b, ret, deb_rc);
637#endif
638
639 ev.pulse = 0;
640 while (1) {
641 ev.pulse = !ev.pulse;
642 ev.duration = (*b * FIRMWARE_CLOCK_DIVISOR * FIRMWARE_CLOCK_TICK) / 1000;
643 ir_raw_event_store(d->rc_dev, &ev);
644
645 b++;
646 if (*b == 0xff) {
647 ev.pulse = 0;
648 ev.duration = 888888*2;
649 ir_raw_event_store(d->rc_dev, &ev);
650 break;
651 }
652 }
653
654 ir_raw_event_handle(d->rc_dev);
655
656 return 1;
657}
658
659static int technisat_usb2_rc_query(struct dvb_usb_device *d)
660{
661 int ret = technisat_usb2_get_ir(d);
662
663 if (ret < 0)
664 return ret;
665
666 if (ret == 0)
667 return 0;
668
669 if (!disable_led_control)
670 technisat_usb2_set_led(d, 1, LED_BLINK);
671
672 return 0;
673}
674
675/* DVB-USB and USB stuff follows */
676static struct usb_device_id technisat_usb2_id_table[] = {
677 { USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_USB2_DVB_S2) },
678 { 0 } /* Terminating entry */
679};
680
681/* device description */
682static struct dvb_usb_device_properties technisat_usb2_devices = {
683 .caps = DVB_USB_IS_AN_I2C_ADAPTER,
684
685 .usb_ctrl = CYPRESS_FX2,
686
687 .identify_state = technisat_usb2_identify_state,
688 .firmware = "dvb-usb-SkyStar_USB_HD_FW_v17_63.HEX.fw",
689
690 .size_of_priv = sizeof(struct technisat_usb2_state),
691
692 .i2c_algo = &technisat_usb2_i2c_algo,
693
694 .power_ctrl = technisat_usb2_power_ctrl,
695 .read_mac_address = technisat_usb2_read_mac_address,
696
697 .num_adapters = 1,
698 .adapter = {
699 {
700 .frontend_attach = technisat_usb2_frontend_attach,
701
702 .stream = {
703 .type = USB_ISOC,
704 .count = 8,
705 .endpoint = 0x2,
706 .u = {
707 .isoc = {
708 .framesperurb = 32,
709 .framesize = 2048,
710 .interval = 3,
711 }
712 }
713 },
714
715 .size_of_priv = 0,
716 },
717 },
718
719 .num_device_descs = 1,
720 .devices = {
721 { "Technisat SkyStar USB HD (DVB-S/S2)",
722 { &technisat_usb2_id_table[0], NULL },
723 { NULL },
724 },
725 },
726
727 .rc.core = {
728 .rc_interval = 100,
729 .rc_codes = RC_MAP_TECHNISAT_USB2,
730 .module_name = "technisat-usb2",
731 .rc_query = technisat_usb2_rc_query,
732 .allowed_protos = RC_TYPE_ALL,
733 .driver_type = RC_DRIVER_IR_RAW,
734 }
735};
736
737static int technisat_usb2_probe(struct usb_interface *intf,
738 const struct usb_device_id *id)
739{
740 struct dvb_usb_device *dev;
741
742 if (dvb_usb_device_init(intf, &technisat_usb2_devices, THIS_MODULE,
743 &dev, adapter_nr) != 0)
744 return -ENODEV;
745
746 if (dev) {
747 struct technisat_usb2_state *state = dev->priv;
748 state->dev = dev;
749
750 if (!disable_led_control) {
751 INIT_DELAYED_WORK(&state->green_led_work,
752 technisat_usb2_green_led_control);
753 schedule_delayed_work(&state->green_led_work,
754 msecs_to_jiffies(500));
755 }
756 }
757
758 return 0;
759}
760
761static void technisat_usb2_disconnect(struct usb_interface *intf)
762{
763 struct dvb_usb_device *dev = usb_get_intfdata(intf);
764
765 /* work and stuff was only created when the device is is hot-state */
766 if (dev != NULL) {
767 struct technisat_usb2_state *state = dev->priv;
768 if (state != NULL) {
769 cancel_delayed_work_sync(&state->green_led_work);
770 flush_scheduled_work();
771 }
772 }
773
774 dvb_usb_device_exit(intf);
775}
776
777static struct usb_driver technisat_usb2_driver = {
778 .name = "dvb_usb_technisat_usb2",
779 .probe = technisat_usb2_probe,
780 .disconnect = technisat_usb2_disconnect,
781 .id_table = technisat_usb2_id_table,
782};
783
784/* module stuff */
785static int __init technisat_usb2_module_init(void)
786{
787 int result = usb_register(&technisat_usb2_driver);
788 if (result) {
789 err("usb_register failed. Code %d", result);
790 return result;
791 }
792
793 return 0;
794}
795
796static void __exit technisat_usb2_module_exit(void)
797{
798 usb_deregister(&technisat_usb2_driver);
799}
800
801module_init(technisat_usb2_module_init);
802module_exit(technisat_usb2_module_exit);
803
804MODULE_AUTHOR("Patrick Boettcher <pboettcher@kernellabs.com>");
805MODULE_DESCRIPTION("Driver for Technisat DVB-S/S2 USB 2.0 device");
806MODULE_VERSION("1.0");
807MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/firewire/Kconfig b/drivers/media/dvb/firewire/Kconfig
index 4afa29256df1..f3e9448c3955 100644
--- a/drivers/media/dvb/firewire/Kconfig
+++ b/drivers/media/dvb/firewire/Kconfig
@@ -1,6 +1,6 @@
1config DVB_FIREDTV 1config DVB_FIREDTV
2 tristate "FireDTV and FloppyDTV" 2 tristate "FireDTV and FloppyDTV"
3 depends on DVB_CORE && (FIREWIRE || IEEE1394) 3 depends on DVB_CORE && FIREWIRE
4 help 4 help
5 Support for DVB receivers from Digital Everywhere 5 Support for DVB receivers from Digital Everywhere
6 which are connected via IEEE 1394 (FireWire). 6 which are connected via IEEE 1394 (FireWire).
@@ -13,12 +13,6 @@ config DVB_FIREDTV
13 13
14if DVB_FIREDTV 14if DVB_FIREDTV
15 15
16config DVB_FIREDTV_FIREWIRE
17 def_bool FIREWIRE = y || (FIREWIRE = m && DVB_FIREDTV = m)
18
19config DVB_FIREDTV_IEEE1394
20 def_bool IEEE1394 = y || (IEEE1394 = m && DVB_FIREDTV = m)
21
22config DVB_FIREDTV_INPUT 16config DVB_FIREDTV_INPUT
23 def_bool INPUT = y || (INPUT = m && DVB_FIREDTV = m) 17 def_bool INPUT = y || (INPUT = m && DVB_FIREDTV = m)
24 18
diff --git a/drivers/media/dvb/firewire/Makefile b/drivers/media/dvb/firewire/Makefile
index da84203d51c6..357b3aab186b 100644
--- a/drivers/media/dvb/firewire/Makefile
+++ b/drivers/media/dvb/firewire/Makefile
@@ -1,9 +1,6 @@
1obj-$(CONFIG_DVB_FIREDTV) += firedtv.o 1obj-$(CONFIG_DVB_FIREDTV) += firedtv.o
2 2
3firedtv-y := firedtv-avc.o firedtv-ci.o firedtv-dvb.o firedtv-fe.o 3firedtv-y := firedtv-avc.o firedtv-ci.o firedtv-dvb.o firedtv-fe.o firedtv-fw.o
4firedtv-$(CONFIG_DVB_FIREDTV_FIREWIRE) += firedtv-fw.o
5firedtv-$(CONFIG_DVB_FIREDTV_IEEE1394) += firedtv-1394.o
6firedtv-$(CONFIG_DVB_FIREDTV_INPUT) += firedtv-rc.o 4firedtv-$(CONFIG_DVB_FIREDTV_INPUT) += firedtv-rc.o
7 5
8ccflags-y += -Idrivers/media/dvb/dvb-core 6ccflags-y += -Idrivers/media/dvb/dvb-core
9ccflags-$(CONFIG_DVB_FIREDTV_IEEE1394) += -Idrivers/ieee1394
diff --git a/drivers/media/dvb/firewire/firedtv-1394.c b/drivers/media/dvb/firewire/firedtv-1394.c
deleted file mode 100644
index b34ca7afb0e6..000000000000
--- a/drivers/media/dvb/firewire/firedtv-1394.c
+++ /dev/null
@@ -1,300 +0,0 @@
1/*
2 * FireDTV driver -- ieee1394 I/O backend
3 *
4 * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
5 * Copyright (C) 2007-2008 Ben Backx <ben@bbackx.com>
6 * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/kernel.h>
17#include <linux/list.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/types.h>
21
22#include <dma.h>
23#include <csr1212.h>
24#include <highlevel.h>
25#include <hosts.h>
26#include <ieee1394.h>
27#include <iso.h>
28#include <nodemgr.h>
29
30#include <dvb_demux.h>
31
32#include "firedtv.h"
33
34static LIST_HEAD(node_list);
35static DEFINE_SPINLOCK(node_list_lock);
36
37#define CIP_HEADER_SIZE 8
38#define MPEG2_TS_HEADER_SIZE 4
39#define MPEG2_TS_SOURCE_PACKET_SIZE (4 + 188)
40
41static void rawiso_activity_cb(struct hpsb_iso *iso)
42{
43 struct firedtv *f, *fdtv = NULL;
44 unsigned int i, num, packet;
45 unsigned char *buf;
46 unsigned long flags;
47 int count;
48
49 spin_lock_irqsave(&node_list_lock, flags);
50 list_for_each_entry(f, &node_list, list)
51 if (f->backend_data == iso) {
52 fdtv = f;
53 break;
54 }
55 spin_unlock_irqrestore(&node_list_lock, flags);
56
57 packet = iso->first_packet;
58 num = hpsb_iso_n_ready(iso);
59
60 if (!fdtv) {
61 pr_err("received at unknown iso channel\n");
62 goto out;
63 }
64
65 for (i = 0; i < num; i++, packet = (packet + 1) % iso->buf_packets) {
66 buf = dma_region_i(&iso->data_buf, unsigned char,
67 iso->infos[packet].offset + CIP_HEADER_SIZE);
68 count = (iso->infos[packet].len - CIP_HEADER_SIZE) /
69 MPEG2_TS_SOURCE_PACKET_SIZE;
70
71 /* ignore empty packet */
72 if (iso->infos[packet].len <= CIP_HEADER_SIZE)
73 continue;
74
75 while (count--) {
76 if (buf[MPEG2_TS_HEADER_SIZE] == 0x47)
77 dvb_dmx_swfilter_packets(&fdtv->demux,
78 &buf[MPEG2_TS_HEADER_SIZE], 1);
79 else
80 dev_err(fdtv->device,
81 "skipping invalid packet\n");
82 buf += MPEG2_TS_SOURCE_PACKET_SIZE;
83 }
84 }
85out:
86 hpsb_iso_recv_release_packets(iso, num);
87}
88
89static inline struct node_entry *node_of(struct firedtv *fdtv)
90{
91 return container_of(fdtv->device, struct unit_directory, device)->ne;
92}
93
94static int node_lock(struct firedtv *fdtv, u64 addr, void *data)
95{
96 quadlet_t *d = data;
97 int ret;
98
99 ret = hpsb_node_lock(node_of(fdtv), addr,
100 EXTCODE_COMPARE_SWAP, &d[1], d[0]);
101 d[0] = d[1];
102
103 return ret;
104}
105
106static int node_read(struct firedtv *fdtv, u64 addr, void *data)
107{
108 return hpsb_node_read(node_of(fdtv), addr, data, 4);
109}
110
111static int node_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
112{
113 return hpsb_node_write(node_of(fdtv), addr, data, len);
114}
115
116#define FDTV_ISO_BUFFER_PACKETS 256
117#define FDTV_ISO_BUFFER_SIZE (FDTV_ISO_BUFFER_PACKETS * 200)
118
119static int start_iso(struct firedtv *fdtv)
120{
121 struct hpsb_iso *iso_handle;
122 int ret;
123
124 iso_handle = hpsb_iso_recv_init(node_of(fdtv)->host,
125 FDTV_ISO_BUFFER_SIZE, FDTV_ISO_BUFFER_PACKETS,
126 fdtv->isochannel, HPSB_ISO_DMA_DEFAULT,
127 -1, /* stat.config.irq_interval */
128 rawiso_activity_cb);
129 if (iso_handle == NULL) {
130 dev_err(fdtv->device, "cannot initialize iso receive\n");
131 return -ENOMEM;
132 }
133 fdtv->backend_data = iso_handle;
134
135 ret = hpsb_iso_recv_start(iso_handle, -1, -1, 0);
136 if (ret != 0) {
137 dev_err(fdtv->device, "cannot start iso receive\n");
138 hpsb_iso_shutdown(iso_handle);
139 fdtv->backend_data = NULL;
140 }
141 return ret;
142}
143
144static void stop_iso(struct firedtv *fdtv)
145{
146 struct hpsb_iso *iso_handle = fdtv->backend_data;
147
148 if (iso_handle != NULL) {
149 hpsb_iso_stop(iso_handle);
150 hpsb_iso_shutdown(iso_handle);
151 }
152 fdtv->backend_data = NULL;
153}
154
155static const struct firedtv_backend fdtv_1394_backend = {
156 .lock = node_lock,
157 .read = node_read,
158 .write = node_write,
159 .start_iso = start_iso,
160 .stop_iso = stop_iso,
161};
162
163static void fcp_request(struct hpsb_host *host, int nodeid, int direction,
164 int cts, u8 *data, size_t length)
165{
166 struct firedtv *f, *fdtv = NULL;
167 unsigned long flags;
168 int su;
169
170 if (length == 0 || (data[0] & 0xf0) != 0)
171 return;
172
173 su = data[1] & 0x7;
174
175 spin_lock_irqsave(&node_list_lock, flags);
176 list_for_each_entry(f, &node_list, list)
177 if (node_of(f)->host == host &&
178 node_of(f)->nodeid == nodeid &&
179 (f->subunit == su || (f->subunit == 0 && su == 0x7))) {
180 fdtv = f;
181 break;
182 }
183 spin_unlock_irqrestore(&node_list_lock, flags);
184
185 if (fdtv)
186 avc_recv(fdtv, data, length);
187}
188
189static int node_probe(struct device *dev)
190{
191 struct unit_directory *ud =
192 container_of(dev, struct unit_directory, device);
193 struct firedtv *fdtv;
194 int kv_len, err;
195 void *kv_str;
196
197 if (ud->model_name_kv) {
198 kv_len = (ud->model_name_kv->value.leaf.len - 2) * 4;
199 kv_str = CSR1212_TEXTUAL_DESCRIPTOR_LEAF_DATA(ud->model_name_kv);
200 } else {
201 kv_len = 0;
202 kv_str = NULL;
203 }
204 fdtv = fdtv_alloc(dev, &fdtv_1394_backend, kv_str, kv_len);
205 if (!fdtv)
206 return -ENOMEM;
207
208 /*
209 * Work around a bug in udev's path_id script: Use the fw-host's dev
210 * instead of the unit directory's dev as parent of the input device.
211 */
212 err = fdtv_register_rc(fdtv, dev->parent->parent);
213 if (err)
214 goto fail_free;
215
216 spin_lock_irq(&node_list_lock);
217 list_add_tail(&fdtv->list, &node_list);
218 spin_unlock_irq(&node_list_lock);
219
220 err = avc_identify_subunit(fdtv);
221 if (err)
222 goto fail;
223
224 err = fdtv_dvb_register(fdtv);
225 if (err)
226 goto fail;
227
228 avc_register_remote_control(fdtv);
229
230 return 0;
231fail:
232 spin_lock_irq(&node_list_lock);
233 list_del(&fdtv->list);
234 spin_unlock_irq(&node_list_lock);
235 fdtv_unregister_rc(fdtv);
236fail_free:
237 kfree(fdtv);
238
239 return err;
240}
241
242static int node_remove(struct device *dev)
243{
244 struct firedtv *fdtv = dev_get_drvdata(dev);
245
246 fdtv_dvb_unregister(fdtv);
247
248 spin_lock_irq(&node_list_lock);
249 list_del(&fdtv->list);
250 spin_unlock_irq(&node_list_lock);
251
252 fdtv_unregister_rc(fdtv);
253 kfree(fdtv);
254
255 return 0;
256}
257
258static int node_update(struct unit_directory *ud)
259{
260 struct firedtv *fdtv = dev_get_drvdata(&ud->device);
261
262 if (fdtv->isochannel >= 0)
263 cmp_establish_pp_connection(fdtv, fdtv->subunit,
264 fdtv->isochannel);
265 return 0;
266}
267
268static struct hpsb_protocol_driver fdtv_driver = {
269 .name = "firedtv",
270 .id_table = fdtv_id_table,
271 .update = node_update,
272 .driver = {
273 .probe = node_probe,
274 .remove = node_remove,
275 },
276};
277
278static struct hpsb_highlevel fdtv_highlevel = {
279 .name = "firedtv",
280 .fcp_request = fcp_request,
281};
282
283int __init fdtv_1394_init(void)
284{
285 int ret;
286
287 hpsb_register_highlevel(&fdtv_highlevel);
288 ret = hpsb_register_protocol(&fdtv_driver);
289 if (ret) {
290 printk(KERN_ERR "firedtv: failed to register protocol\n");
291 hpsb_unregister_highlevel(&fdtv_highlevel);
292 }
293 return ret;
294}
295
296void __exit fdtv_1394_exit(void)
297{
298 hpsb_unregister_protocol(&fdtv_driver);
299 hpsb_unregister_highlevel(&fdtv_highlevel);
300}
diff --git a/drivers/media/dvb/firewire/firedtv-avc.c b/drivers/media/dvb/firewire/firedtv-avc.c
index f0f1842fab60..fc5ccd8c923a 100644
--- a/drivers/media/dvb/firewire/firedtv-avc.c
+++ b/drivers/media/dvb/firewire/firedtv-avc.c
@@ -241,8 +241,8 @@ static int avc_write(struct firedtv *fdtv)
241 if (unlikely(avc_debug)) 241 if (unlikely(avc_debug))
242 debug_fcp(fdtv->avc_data, fdtv->avc_data_length); 242 debug_fcp(fdtv->avc_data, fdtv->avc_data_length);
243 243
244 err = fdtv->backend->write(fdtv, FCP_COMMAND_REGISTER, 244 err = fdtv_write(fdtv, FCP_COMMAND_REGISTER,
245 fdtv->avc_data, fdtv->avc_data_length); 245 fdtv->avc_data, fdtv->avc_data_length);
246 if (err) { 246 if (err) {
247 dev_err(fdtv->device, "FCP command write failed\n"); 247 dev_err(fdtv->device, "FCP command write failed\n");
248 248
@@ -1322,7 +1322,7 @@ static int cmp_read(struct firedtv *fdtv, u64 addr, __be32 *data)
1322 1322
1323 mutex_lock(&fdtv->avc_mutex); 1323 mutex_lock(&fdtv->avc_mutex);
1324 1324
1325 ret = fdtv->backend->read(fdtv, addr, data); 1325 ret = fdtv_read(fdtv, addr, data);
1326 if (ret < 0) 1326 if (ret < 0)
1327 dev_err(fdtv->device, "CMP: read I/O error\n"); 1327 dev_err(fdtv->device, "CMP: read I/O error\n");
1328 1328
@@ -1340,7 +1340,7 @@ static int cmp_lock(struct firedtv *fdtv, u64 addr, __be32 data[])
1340 /* data[] is stack-allocated and should not be DMA-mapped. */ 1340 /* data[] is stack-allocated and should not be DMA-mapped. */
1341 memcpy(fdtv->avc_data, data, 8); 1341 memcpy(fdtv->avc_data, data, 8);
1342 1342
1343 ret = fdtv->backend->lock(fdtv, addr, fdtv->avc_data); 1343 ret = fdtv_lock(fdtv, addr, fdtv->avc_data);
1344 if (ret < 0) 1344 if (ret < 0)
1345 dev_err(fdtv->device, "CMP: lock I/O error\n"); 1345 dev_err(fdtv->device, "CMP: lock I/O error\n");
1346 else 1346 else
@@ -1405,10 +1405,7 @@ repeat:
1405 /* FIXME: this is for the worst case - optimize */ 1405 /* FIXME: this is for the worst case - optimize */
1406 set_opcr_overhead_id(opcr, 0); 1406 set_opcr_overhead_id(opcr, 0);
1407 1407
1408 /* 1408 /* FIXME: allocate isochronous channel and bandwidth at IRM */
1409 * FIXME: allocate isochronous channel and bandwidth at IRM
1410 * fdtv->backend->alloc_resources(fdtv, channels_mask, bw);
1411 */
1412 } 1409 }
1413 1410
1414 set_opcr_p2p_connections(opcr, get_opcr_p2p_connections(*opcr) + 1); 1411 set_opcr_p2p_connections(opcr, get_opcr_p2p_connections(*opcr) + 1);
@@ -1424,8 +1421,6 @@ repeat:
1424 /* 1421 /*
1425 * FIXME: if old_opcr.P2P_Connections > 0, 1422 * FIXME: if old_opcr.P2P_Connections > 0,
1426 * deallocate isochronous channel and bandwidth at IRM 1423 * deallocate isochronous channel and bandwidth at IRM
1427 * if (...)
1428 * fdtv->backend->dealloc_resources(fdtv, channel, bw);
1429 */ 1424 */
1430 1425
1431 if (++attempts < 6) /* arbitrary limit */ 1426 if (++attempts < 6) /* arbitrary limit */
diff --git a/drivers/media/dvb/firewire/firedtv-dvb.c b/drivers/media/dvb/firewire/firedtv-dvb.c
index 079e8c5b0475..fd8bbbfa5c59 100644
--- a/drivers/media/dvb/firewire/firedtv-dvb.c
+++ b/drivers/media/dvb/firewire/firedtv-dvb.c
@@ -14,14 +14,9 @@
14#include <linux/device.h> 14#include <linux/device.h>
15#include <linux/errno.h> 15#include <linux/errno.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/mod_devicetable.h>
18#include <linux/module.h> 17#include <linux/module.h>
19#include <linux/mutex.h> 18#include <linux/mutex.h>
20#include <linux/slab.h>
21#include <linux/string.h>
22#include <linux/types.h> 19#include <linux/types.h>
23#include <linux/wait.h>
24#include <linux/workqueue.h>
25 20
26#include <dmxdev.h> 21#include <dmxdev.h>
27#include <dvb_demux.h> 22#include <dvb_demux.h>
@@ -166,11 +161,11 @@ int fdtv_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
166 161
167DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 162DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
168 163
169int fdtv_dvb_register(struct firedtv *fdtv) 164int fdtv_dvb_register(struct firedtv *fdtv, const char *name)
170{ 165{
171 int err; 166 int err;
172 167
173 err = dvb_register_adapter(&fdtv->adapter, fdtv_model_names[fdtv->type], 168 err = dvb_register_adapter(&fdtv->adapter, name,
174 THIS_MODULE, fdtv->device, adapter_nr); 169 THIS_MODULE, fdtv->device, adapter_nr);
175 if (err < 0) 170 if (err < 0)
176 goto fail_log; 171 goto fail_log;
@@ -210,7 +205,7 @@ int fdtv_dvb_register(struct firedtv *fdtv)
210 205
211 dvb_net_init(&fdtv->adapter, &fdtv->dvbnet, &fdtv->demux.dmx); 206 dvb_net_init(&fdtv->adapter, &fdtv->dvbnet, &fdtv->demux.dmx);
212 207
213 fdtv_frontend_init(fdtv); 208 fdtv_frontend_init(fdtv, name);
214 err = dvb_register_frontend(&fdtv->adapter, &fdtv->fe); 209 err = dvb_register_frontend(&fdtv->adapter, &fdtv->fe);
215 if (err) 210 if (err)
216 goto fail_net_release; 211 goto fail_net_release;
@@ -248,127 +243,3 @@ void fdtv_dvb_unregister(struct firedtv *fdtv)
248 dvb_dmx_release(&fdtv->demux); 243 dvb_dmx_release(&fdtv->demux);
249 dvb_unregister_adapter(&fdtv->adapter); 244 dvb_unregister_adapter(&fdtv->adapter);
250} 245}
251
252const char *fdtv_model_names[] = {
253 [FIREDTV_UNKNOWN] = "unknown type",
254 [FIREDTV_DVB_S] = "FireDTV S/CI",
255 [FIREDTV_DVB_C] = "FireDTV C/CI",
256 [FIREDTV_DVB_T] = "FireDTV T/CI",
257 [FIREDTV_DVB_S2] = "FireDTV S2 ",
258};
259
260struct firedtv *fdtv_alloc(struct device *dev,
261 const struct firedtv_backend *backend,
262 const char *name, size_t name_len)
263{
264 struct firedtv *fdtv;
265 int i;
266
267 fdtv = kzalloc(sizeof(*fdtv), GFP_KERNEL);
268 if (!fdtv)
269 return NULL;
270
271 dev_set_drvdata(dev, fdtv);
272 fdtv->device = dev;
273 fdtv->isochannel = -1;
274 fdtv->voltage = 0xff;
275 fdtv->tone = 0xff;
276 fdtv->backend = backend;
277
278 mutex_init(&fdtv->avc_mutex);
279 init_waitqueue_head(&fdtv->avc_wait);
280 mutex_init(&fdtv->demux_mutex);
281 INIT_WORK(&fdtv->remote_ctrl_work, avc_remote_ctrl_work);
282
283 for (i = ARRAY_SIZE(fdtv_model_names); --i; )
284 if (strlen(fdtv_model_names[i]) <= name_len &&
285 strncmp(name, fdtv_model_names[i], name_len) == 0)
286 break;
287 fdtv->type = i;
288
289 return fdtv;
290}
291
292#define MATCH_FLAGS (IEEE1394_MATCH_VENDOR_ID | IEEE1394_MATCH_MODEL_ID | \
293 IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION)
294
295#define DIGITAL_EVERYWHERE_OUI 0x001287
296#define AVC_UNIT_SPEC_ID_ENTRY 0x00a02d
297#define AVC_SW_VERSION_ENTRY 0x010001
298
299const struct ieee1394_device_id fdtv_id_table[] = {
300 {
301 /* FloppyDTV S/CI and FloppyDTV S2 */
302 .match_flags = MATCH_FLAGS,
303 .vendor_id = DIGITAL_EVERYWHERE_OUI,
304 .model_id = 0x000024,
305 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
306 .version = AVC_SW_VERSION_ENTRY,
307 }, {
308 /* FloppyDTV T/CI */
309 .match_flags = MATCH_FLAGS,
310 .vendor_id = DIGITAL_EVERYWHERE_OUI,
311 .model_id = 0x000025,
312 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
313 .version = AVC_SW_VERSION_ENTRY,
314 }, {
315 /* FloppyDTV C/CI */
316 .match_flags = MATCH_FLAGS,
317 .vendor_id = DIGITAL_EVERYWHERE_OUI,
318 .model_id = 0x000026,
319 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
320 .version = AVC_SW_VERSION_ENTRY,
321 }, {
322 /* FireDTV S/CI and FloppyDTV S2 */
323 .match_flags = MATCH_FLAGS,
324 .vendor_id = DIGITAL_EVERYWHERE_OUI,
325 .model_id = 0x000034,
326 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
327 .version = AVC_SW_VERSION_ENTRY,
328 }, {
329 /* FireDTV T/CI */
330 .match_flags = MATCH_FLAGS,
331 .vendor_id = DIGITAL_EVERYWHERE_OUI,
332 .model_id = 0x000035,
333 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
334 .version = AVC_SW_VERSION_ENTRY,
335 }, {
336 /* FireDTV C/CI */
337 .match_flags = MATCH_FLAGS,
338 .vendor_id = DIGITAL_EVERYWHERE_OUI,
339 .model_id = 0x000036,
340 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
341 .version = AVC_SW_VERSION_ENTRY,
342 }, {}
343};
344MODULE_DEVICE_TABLE(ieee1394, fdtv_id_table);
345
346static int __init fdtv_init(void)
347{
348 int ret;
349
350 ret = fdtv_fw_init();
351 if (ret < 0)
352 return ret;
353
354 ret = fdtv_1394_init();
355 if (ret < 0)
356 fdtv_fw_exit();
357
358 return ret;
359}
360
361static void __exit fdtv_exit(void)
362{
363 fdtv_1394_exit();
364 fdtv_fw_exit();
365}
366
367module_init(fdtv_init);
368module_exit(fdtv_exit);
369
370MODULE_AUTHOR("Andreas Monitzer <andy@monitzer.com>");
371MODULE_AUTHOR("Ben Backx <ben@bbackx.com>");
372MODULE_DESCRIPTION("FireDTV DVB Driver");
373MODULE_LICENSE("GPL");
374MODULE_SUPPORTED_DEVICE("FireDTV DVB");
diff --git a/drivers/media/dvb/firewire/firedtv-fe.c b/drivers/media/dvb/firewire/firedtv-fe.c
index d10920e2f3a2..8748a61be73d 100644
--- a/drivers/media/dvb/firewire/firedtv-fe.c
+++ b/drivers/media/dvb/firewire/firedtv-fe.c
@@ -36,14 +36,14 @@ static int fdtv_dvb_init(struct dvb_frontend *fe)
36 return err; 36 return err;
37 } 37 }
38 38
39 return fdtv->backend->start_iso(fdtv); 39 return fdtv_start_iso(fdtv);
40} 40}
41 41
42static int fdtv_sleep(struct dvb_frontend *fe) 42static int fdtv_sleep(struct dvb_frontend *fe)
43{ 43{
44 struct firedtv *fdtv = fe->sec_priv; 44 struct firedtv *fdtv = fe->sec_priv;
45 45
46 fdtv->backend->stop_iso(fdtv); 46 fdtv_stop_iso(fdtv);
47 cmp_break_pp_connection(fdtv, fdtv->subunit, fdtv->isochannel); 47 cmp_break_pp_connection(fdtv, fdtv->subunit, fdtv->isochannel);
48 fdtv->isochannel = -1; 48 fdtv->isochannel = -1;
49 return 0; 49 return 0;
@@ -165,7 +165,7 @@ static int fdtv_set_property(struct dvb_frontend *fe, struct dtv_property *tvp)
165 return 0; 165 return 0;
166} 166}
167 167
168void fdtv_frontend_init(struct firedtv *fdtv) 168void fdtv_frontend_init(struct firedtv *fdtv, const char *name)
169{ 169{
170 struct dvb_frontend_ops *ops = &fdtv->fe.ops; 170 struct dvb_frontend_ops *ops = &fdtv->fe.ops;
171 struct dvb_frontend_info *fi = &ops->info; 171 struct dvb_frontend_info *fi = &ops->info;
@@ -266,7 +266,7 @@ void fdtv_frontend_init(struct firedtv *fdtv)
266 dev_err(fdtv->device, "no frontend for model type %d\n", 266 dev_err(fdtv->device, "no frontend for model type %d\n",
267 fdtv->type); 267 fdtv->type);
268 } 268 }
269 strcpy(fi->name, fdtv_model_names[fdtv->type]); 269 strcpy(fi->name, name);
270 270
271 fdtv->fe.dvb = &fdtv->adapter; 271 fdtv->fe.dvb = &fdtv->adapter;
272 fdtv->fe.sec_priv = fdtv; 272 fdtv->fe.sec_priv = fdtv;
diff --git a/drivers/media/dvb/firewire/firedtv-fw.c b/drivers/media/dvb/firewire/firedtv-fw.c
index 7424b0493f9d..8022b743af91 100644
--- a/drivers/media/dvb/firewire/firedtv-fw.c
+++ b/drivers/media/dvb/firewire/firedtv-fw.c
@@ -9,11 +9,18 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/list.h> 10#include <linux/list.h>
11#include <linux/mm.h> 11#include <linux/mm.h>
12#include <linux/mod_devicetable.h>
13#include <linux/module.h>
14#include <linux/mutex.h>
12#include <linux/slab.h> 15#include <linux/slab.h>
13#include <linux/spinlock.h> 16#include <linux/spinlock.h>
17#include <linux/string.h>
14#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/wait.h>
20#include <linux/workqueue.h>
15 21
16#include <asm/page.h> 22#include <asm/page.h>
23#include <asm/system.h>
17 24
18#include <dvb_demux.h> 25#include <dvb_demux.h>
19 26
@@ -41,17 +48,17 @@ static int node_req(struct firedtv *fdtv, u64 addr, void *data, size_t len,
41 return rcode != RCODE_COMPLETE ? -EIO : 0; 48 return rcode != RCODE_COMPLETE ? -EIO : 0;
42} 49}
43 50
44static int node_lock(struct firedtv *fdtv, u64 addr, void *data) 51int fdtv_lock(struct firedtv *fdtv, u64 addr, void *data)
45{ 52{
46 return node_req(fdtv, addr, data, 8, TCODE_LOCK_COMPARE_SWAP); 53 return node_req(fdtv, addr, data, 8, TCODE_LOCK_COMPARE_SWAP);
47} 54}
48 55
49static int node_read(struct firedtv *fdtv, u64 addr, void *data) 56int fdtv_read(struct firedtv *fdtv, u64 addr, void *data)
50{ 57{
51 return node_req(fdtv, addr, data, 4, TCODE_READ_QUADLET_REQUEST); 58 return node_req(fdtv, addr, data, 4, TCODE_READ_QUADLET_REQUEST);
52} 59}
53 60
54static int node_write(struct firedtv *fdtv, u64 addr, void *data, size_t len) 61int fdtv_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
55{ 62{
56 return node_req(fdtv, addr, data, len, TCODE_WRITE_BLOCK_REQUEST); 63 return node_req(fdtv, addr, data, len, TCODE_WRITE_BLOCK_REQUEST);
57} 64}
@@ -67,7 +74,7 @@ static int node_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
67#define N_PAGES DIV_ROUND_UP(N_PACKETS, PACKETS_PER_PAGE) 74#define N_PAGES DIV_ROUND_UP(N_PACKETS, PACKETS_PER_PAGE)
68#define IRQ_INTERVAL 16 75#define IRQ_INTERVAL 16
69 76
70struct firedtv_receive_context { 77struct fdtv_ir_context {
71 struct fw_iso_context *context; 78 struct fw_iso_context *context;
72 struct fw_iso_buffer buffer; 79 struct fw_iso_buffer buffer;
73 int interrupt_packet; 80 int interrupt_packet;
@@ -75,7 +82,7 @@ struct firedtv_receive_context {
75 char *pages[N_PAGES]; 82 char *pages[N_PAGES];
76}; 83};
77 84
78static int queue_iso(struct firedtv_receive_context *ctx, int index) 85static int queue_iso(struct fdtv_ir_context *ctx, int index)
79{ 86{
80 struct fw_iso_packet p; 87 struct fw_iso_packet p;
81 88
@@ -92,7 +99,7 @@ static void handle_iso(struct fw_iso_context *context, u32 cycle,
92 size_t header_length, void *header, void *data) 99 size_t header_length, void *header, void *data)
93{ 100{
94 struct firedtv *fdtv = data; 101 struct firedtv *fdtv = data;
95 struct firedtv_receive_context *ctx = fdtv->backend_data; 102 struct fdtv_ir_context *ctx = fdtv->ir_context;
96 __be32 *h, *h_end; 103 __be32 *h, *h_end;
97 int length, err, i = ctx->current_packet; 104 int length, err, i = ctx->current_packet;
98 char *p, *p_end; 105 char *p, *p_end;
@@ -121,9 +128,9 @@ static void handle_iso(struct fw_iso_context *context, u32 cycle,
121 ctx->current_packet = i; 128 ctx->current_packet = i;
122} 129}
123 130
124static int start_iso(struct firedtv *fdtv) 131int fdtv_start_iso(struct firedtv *fdtv)
125{ 132{
126 struct firedtv_receive_context *ctx; 133 struct fdtv_ir_context *ctx;
127 struct fw_device *device = device_of(fdtv); 134 struct fw_device *device = device_of(fdtv);
128 int i, err; 135 int i, err;
129 136
@@ -161,7 +168,7 @@ static int start_iso(struct firedtv *fdtv)
161 if (err) 168 if (err)
162 goto fail; 169 goto fail;
163 170
164 fdtv->backend_data = ctx; 171 fdtv->ir_context = ctx;
165 172
166 return 0; 173 return 0;
167fail: 174fail:
@@ -174,9 +181,9 @@ fail_free:
174 return err; 181 return err;
175} 182}
176 183
177static void stop_iso(struct firedtv *fdtv) 184void fdtv_stop_iso(struct firedtv *fdtv)
178{ 185{
179 struct firedtv_receive_context *ctx = fdtv->backend_data; 186 struct fdtv_ir_context *ctx = fdtv->ir_context;
180 187
181 fw_iso_context_stop(ctx->context); 188 fw_iso_context_stop(ctx->context);
182 fw_iso_buffer_destroy(&ctx->buffer, device_of(fdtv)->card); 189 fw_iso_buffer_destroy(&ctx->buffer, device_of(fdtv)->card);
@@ -184,14 +191,6 @@ static void stop_iso(struct firedtv *fdtv)
184 kfree(ctx); 191 kfree(ctx);
185} 192}
186 193
187static const struct firedtv_backend backend = {
188 .lock = node_lock,
189 .read = node_read,
190 .write = node_write,
191 .start_iso = start_iso,
192 .stop_iso = stop_iso,
193};
194
195static void handle_fcp(struct fw_card *card, struct fw_request *request, 194static void handle_fcp(struct fw_card *card, struct fw_request *request,
196 int tcode, int destination, int source, int generation, 195 int tcode, int destination, int source, int generation,
197 unsigned long long offset, void *payload, size_t length, 196 unsigned long long offset, void *payload, size_t length,
@@ -238,6 +237,14 @@ static const struct fw_address_region fcp_region = {
238 .end = CSR_REGISTER_BASE + CSR_FCP_END, 237 .end = CSR_REGISTER_BASE + CSR_FCP_END,
239}; 238};
240 239
240static const char * const model_names[] = {
241 [FIREDTV_UNKNOWN] = "unknown type",
242 [FIREDTV_DVB_S] = "FireDTV S/CI",
243 [FIREDTV_DVB_C] = "FireDTV C/CI",
244 [FIREDTV_DVB_T] = "FireDTV T/CI",
245 [FIREDTV_DVB_S2] = "FireDTV S2 ",
246};
247
241/* Adjust the template string if models with longer names appear. */ 248/* Adjust the template string if models with longer names appear. */
242#define MAX_MODEL_NAME_LEN sizeof("FireDTV ????") 249#define MAX_MODEL_NAME_LEN sizeof("FireDTV ????")
243 250
@@ -245,15 +252,31 @@ static int node_probe(struct device *dev)
245{ 252{
246 struct firedtv *fdtv; 253 struct firedtv *fdtv;
247 char name[MAX_MODEL_NAME_LEN]; 254 char name[MAX_MODEL_NAME_LEN];
248 int name_len, err; 255 int name_len, i, err;
249
250 name_len = fw_csr_string(fw_unit(dev)->directory, CSR_MODEL,
251 name, sizeof(name));
252 256
253 fdtv = fdtv_alloc(dev, &backend, name, name_len >= 0 ? name_len : 0); 257 fdtv = kzalloc(sizeof(*fdtv), GFP_KERNEL);
254 if (!fdtv) 258 if (!fdtv)
255 return -ENOMEM; 259 return -ENOMEM;
256 260
261 dev_set_drvdata(dev, fdtv);
262 fdtv->device = dev;
263 fdtv->isochannel = -1;
264 fdtv->voltage = 0xff;
265 fdtv->tone = 0xff;
266
267 mutex_init(&fdtv->avc_mutex);
268 init_waitqueue_head(&fdtv->avc_wait);
269 mutex_init(&fdtv->demux_mutex);
270 INIT_WORK(&fdtv->remote_ctrl_work, avc_remote_ctrl_work);
271
272 name_len = fw_csr_string(fw_unit(dev)->directory, CSR_MODEL,
273 name, sizeof(name));
274 for (i = ARRAY_SIZE(model_names); --i; )
275 if (strlen(model_names[i]) <= name_len &&
276 strncmp(name, model_names[i], name_len) == 0)
277 break;
278 fdtv->type = i;
279
257 err = fdtv_register_rc(fdtv, dev); 280 err = fdtv_register_rc(fdtv, dev);
258 if (err) 281 if (err)
259 goto fail_free; 282 goto fail_free;
@@ -266,7 +289,7 @@ static int node_probe(struct device *dev)
266 if (err) 289 if (err)
267 goto fail; 290 goto fail;
268 291
269 err = fdtv_dvb_register(fdtv); 292 err = fdtv_dvb_register(fdtv, model_names[fdtv->type]);
270 if (err) 293 if (err)
271 goto fail; 294 goto fail;
272 295
@@ -309,6 +332,60 @@ static void node_update(struct fw_unit *unit)
309 fdtv->isochannel); 332 fdtv->isochannel);
310} 333}
311 334
335#define MATCH_FLAGS (IEEE1394_MATCH_VENDOR_ID | IEEE1394_MATCH_MODEL_ID | \
336 IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION)
337
338#define DIGITAL_EVERYWHERE_OUI 0x001287
339#define AVC_UNIT_SPEC_ID_ENTRY 0x00a02d
340#define AVC_SW_VERSION_ENTRY 0x010001
341
342static const struct ieee1394_device_id fdtv_id_table[] = {
343 {
344 /* FloppyDTV S/CI and FloppyDTV S2 */
345 .match_flags = MATCH_FLAGS,
346 .vendor_id = DIGITAL_EVERYWHERE_OUI,
347 .model_id = 0x000024,
348 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
349 .version = AVC_SW_VERSION_ENTRY,
350 }, {
351 /* FloppyDTV T/CI */
352 .match_flags = MATCH_FLAGS,
353 .vendor_id = DIGITAL_EVERYWHERE_OUI,
354 .model_id = 0x000025,
355 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
356 .version = AVC_SW_VERSION_ENTRY,
357 }, {
358 /* FloppyDTV C/CI */
359 .match_flags = MATCH_FLAGS,
360 .vendor_id = DIGITAL_EVERYWHERE_OUI,
361 .model_id = 0x000026,
362 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
363 .version = AVC_SW_VERSION_ENTRY,
364 }, {
365 /* FireDTV S/CI and FloppyDTV S2 */
366 .match_flags = MATCH_FLAGS,
367 .vendor_id = DIGITAL_EVERYWHERE_OUI,
368 .model_id = 0x000034,
369 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
370 .version = AVC_SW_VERSION_ENTRY,
371 }, {
372 /* FireDTV T/CI */
373 .match_flags = MATCH_FLAGS,
374 .vendor_id = DIGITAL_EVERYWHERE_OUI,
375 .model_id = 0x000035,
376 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
377 .version = AVC_SW_VERSION_ENTRY,
378 }, {
379 /* FireDTV C/CI */
380 .match_flags = MATCH_FLAGS,
381 .vendor_id = DIGITAL_EVERYWHERE_OUI,
382 .model_id = 0x000036,
383 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
384 .version = AVC_SW_VERSION_ENTRY,
385 }, {}
386};
387MODULE_DEVICE_TABLE(ieee1394, fdtv_id_table);
388
312static struct fw_driver fdtv_driver = { 389static struct fw_driver fdtv_driver = {
313 .driver = { 390 .driver = {
314 .owner = THIS_MODULE, 391 .owner = THIS_MODULE,
@@ -321,7 +398,7 @@ static struct fw_driver fdtv_driver = {
321 .id_table = fdtv_id_table, 398 .id_table = fdtv_id_table,
322}; 399};
323 400
324int __init fdtv_fw_init(void) 401static int __init fdtv_init(void)
325{ 402{
326 int ret; 403 int ret;
327 404
@@ -329,11 +406,24 @@ int __init fdtv_fw_init(void)
329 if (ret < 0) 406 if (ret < 0)
330 return ret; 407 return ret;
331 408
332 return driver_register(&fdtv_driver.driver); 409 ret = driver_register(&fdtv_driver.driver);
410 if (ret < 0)
411 fw_core_remove_address_handler(&fcp_handler);
412
413 return ret;
333} 414}
334 415
335void fdtv_fw_exit(void) 416static void __exit fdtv_exit(void)
336{ 417{
337 driver_unregister(&fdtv_driver.driver); 418 driver_unregister(&fdtv_driver.driver);
338 fw_core_remove_address_handler(&fcp_handler); 419 fw_core_remove_address_handler(&fcp_handler);
339} 420}
421
422module_init(fdtv_init);
423module_exit(fdtv_exit);
424
425MODULE_AUTHOR("Andreas Monitzer <andy@monitzer.com>");
426MODULE_AUTHOR("Ben Backx <ben@bbackx.com>");
427MODULE_DESCRIPTION("FireDTV DVB Driver");
428MODULE_LICENSE("GPL");
429MODULE_SUPPORTED_DEVICE("FireDTV DVB");
diff --git a/drivers/media/dvb/firewire/firedtv.h b/drivers/media/dvb/firewire/firedtv.h
index 78cc28f36914..bd00b04e079d 100644
--- a/drivers/media/dvb/firewire/firedtv.h
+++ b/drivers/media/dvb/firewire/firedtv.h
@@ -70,15 +70,7 @@ enum model_type {
70 70
71struct device; 71struct device;
72struct input_dev; 72struct input_dev;
73struct firedtv; 73struct fdtv_ir_context;
74
75struct firedtv_backend {
76 int (*lock)(struct firedtv *fdtv, u64 addr, void *data);
77 int (*read)(struct firedtv *fdtv, u64 addr, void *data);
78 int (*write)(struct firedtv *fdtv, u64 addr, void *data, size_t len);
79 int (*start_iso)(struct firedtv *fdtv);
80 void (*stop_iso)(struct firedtv *fdtv);
81};
82 74
83struct firedtv { 75struct firedtv {
84 struct device *device; 76 struct device *device;
@@ -104,12 +96,11 @@ struct firedtv {
104 enum model_type type; 96 enum model_type type;
105 char subunit; 97 char subunit;
106 char isochannel; 98 char isochannel;
99 struct fdtv_ir_context *ir_context;
100
107 fe_sec_voltage_t voltage; 101 fe_sec_voltage_t voltage;
108 fe_sec_tone_mode_t tone; 102 fe_sec_tone_mode_t tone;
109 103
110 const struct firedtv_backend *backend;
111 void *backend_data;
112
113 struct mutex demux_mutex; 104 struct mutex demux_mutex;
114 unsigned long channel_active; 105 unsigned long channel_active;
115 u16 channel_pid[16]; 106 u16 channel_pid[16];
@@ -118,15 +109,6 @@ struct firedtv {
118 u8 avc_data[512]; 109 u8 avc_data[512];
119}; 110};
120 111
121/* firedtv-1394.c */
122#ifdef CONFIG_DVB_FIREDTV_IEEE1394
123int fdtv_1394_init(void);
124void fdtv_1394_exit(void);
125#else
126static inline int fdtv_1394_init(void) { return 0; }
127static inline void fdtv_1394_exit(void) {}
128#endif
129
130/* firedtv-avc.c */ 112/* firedtv-avc.c */
131int avc_recv(struct firedtv *fdtv, void *data, size_t length); 113int avc_recv(struct firedtv *fdtv, void *data, size_t length);
132int avc_tuner_status(struct firedtv *fdtv, struct firedtv_tuner_status *stat); 114int avc_tuner_status(struct firedtv *fdtv, struct firedtv_tuner_status *stat);
@@ -158,25 +140,18 @@ void fdtv_ca_release(struct firedtv *fdtv);
158/* firedtv-dvb.c */ 140/* firedtv-dvb.c */
159int fdtv_start_feed(struct dvb_demux_feed *dvbdmxfeed); 141int fdtv_start_feed(struct dvb_demux_feed *dvbdmxfeed);
160int fdtv_stop_feed(struct dvb_demux_feed *dvbdmxfeed); 142int fdtv_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
161int fdtv_dvb_register(struct firedtv *fdtv); 143int fdtv_dvb_register(struct firedtv *fdtv, const char *name);
162void fdtv_dvb_unregister(struct firedtv *fdtv); 144void fdtv_dvb_unregister(struct firedtv *fdtv);
163struct firedtv *fdtv_alloc(struct device *dev,
164 const struct firedtv_backend *backend,
165 const char *name, size_t name_len);
166extern const char *fdtv_model_names[];
167extern const struct ieee1394_device_id fdtv_id_table[];
168 145
169/* firedtv-fe.c */ 146/* firedtv-fe.c */
170void fdtv_frontend_init(struct firedtv *fdtv); 147void fdtv_frontend_init(struct firedtv *fdtv, const char *name);
171 148
172/* firedtv-fw.c */ 149/* firedtv-fw.c */
173#ifdef CONFIG_DVB_FIREDTV_FIREWIRE 150int fdtv_lock(struct firedtv *fdtv, u64 addr, void *data);
174int fdtv_fw_init(void); 151int fdtv_read(struct firedtv *fdtv, u64 addr, void *data);
175void fdtv_fw_exit(void); 152int fdtv_write(struct firedtv *fdtv, u64 addr, void *data, size_t len);
176#else 153int fdtv_start_iso(struct firedtv *fdtv);
177static inline int fdtv_fw_init(void) { return 0; } 154void fdtv_stop_iso(struct firedtv *fdtv);
178static inline void fdtv_fw_exit(void) {}
179#endif
180 155
181/* firedtv-rc.c */ 156/* firedtv-rc.c */
182#ifdef CONFIG_DVB_FIREDTV_INPUT 157#ifdef CONFIG_DVB_FIREDTV_INPUT
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index b8519ba511e5..83093d1f4f74 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -349,6 +349,14 @@ config DVB_DIB7000P
349 A DVB-T tuner module. Designed for mobile usage. Say Y when you want 349 A DVB-T tuner module. Designed for mobile usage. Say Y when you want
350 to support this frontend. 350 to support this frontend.
351 351
352config DVB_DIB9000
353 tristate "DiBcom 9000"
354 depends on DVB_CORE && I2C
355 default m if DVB_FE_CUSTOMISE
356 help
357 A DVB-T tuner module. Designed for mobile usage. Say Y when you want
358 to support this frontend.
359
352config DVB_TDA10048 360config DVB_TDA10048
353 tristate "Philips TDA10048HN based" 361 tristate "Philips TDA10048HN based"
354 depends on DVB_CORE && I2C 362 depends on DVB_CORE && I2C
@@ -370,6 +378,13 @@ config DVB_EC100
370 help 378 help
371 Say Y when you want to support this frontend. 379 Say Y when you want to support this frontend.
372 380
381config DVB_STV0367
382 tristate "ST STV0367 based"
383 depends on DVB_CORE && I2C
384 default m if DVB_FE_CUSTOMISE
385 help
386 A DVB-T/C tuner module. Say Y when you want to support this frontend.
387
373comment "DVB-C (cable) frontends" 388comment "DVB-C (cable) frontends"
374 depends on DVB_CORE 389 depends on DVB_CORE
375 390
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index b1d9525aa7e3..3b0c4bdc4b2b 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_DVB_DIB3000MC) += dib3000mc.o dibx000_common.o
24obj-$(CONFIG_DVB_DIB7000M) += dib7000m.o dibx000_common.o 24obj-$(CONFIG_DVB_DIB7000M) += dib7000m.o dibx000_common.o
25obj-$(CONFIG_DVB_DIB7000P) += dib7000p.o dibx000_common.o 25obj-$(CONFIG_DVB_DIB7000P) += dib7000p.o dibx000_common.o
26obj-$(CONFIG_DVB_DIB8000) += dib8000.o dibx000_common.o 26obj-$(CONFIG_DVB_DIB8000) += dib8000.o dibx000_common.o
27obj-$(CONFIG_DVB_DIB9000) += dib9000.o dibx000_common.o
27obj-$(CONFIG_DVB_MT312) += mt312.o 28obj-$(CONFIG_DVB_MT312) += mt312.o
28obj-$(CONFIG_DVB_VES1820) += ves1820.o 29obj-$(CONFIG_DVB_VES1820) += ves1820.o
29obj-$(CONFIG_DVB_VES1X93) += ves1x93.o 30obj-$(CONFIG_DVB_VES1X93) += ves1x93.o
@@ -83,3 +84,4 @@ obj-$(CONFIG_DVB_DS3000) += ds3000.o
83obj-$(CONFIG_DVB_MB86A16) += mb86a16.o 84obj-$(CONFIG_DVB_MB86A16) += mb86a16.o
84obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o 85obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
85obj-$(CONFIG_DVB_IX2505V) += ix2505v.o 86obj-$(CONFIG_DVB_IX2505V) += ix2505v.o
87obj-$(CONFIG_DVB_STV0367) += stv0367.o
diff --git a/drivers/media/dvb/frontends/af9013.c b/drivers/media/dvb/frontends/af9013.c
index ba25fa0b0fc2..345311c33383 100644
--- a/drivers/media/dvb/frontends/af9013.c
+++ b/drivers/media/dvb/frontends/af9013.c
@@ -1323,13 +1323,11 @@ static struct dvb_frontend_ops af9013_ops;
1323 1323
1324static int af9013_download_firmware(struct af9013_state *state) 1324static int af9013_download_firmware(struct af9013_state *state)
1325{ 1325{
1326 int i, len, packets, remainder, ret; 1326 int i, len, remaining, ret;
1327 const struct firmware *fw; 1327 const struct firmware *fw;
1328 u16 addr = 0x5100; /* firmware start address */
1329 u16 checksum = 0; 1328 u16 checksum = 0;
1330 u8 val; 1329 u8 val;
1331 u8 fw_params[4]; 1330 u8 fw_params[4];
1332 u8 *data;
1333 u8 *fw_file = AF9013_DEFAULT_FIRMWARE; 1331 u8 *fw_file = AF9013_DEFAULT_FIRMWARE;
1334 1332
1335 msleep(100); 1333 msleep(100);
@@ -1373,21 +1371,18 @@ static int af9013_download_firmware(struct af9013_state *state)
1373 if (ret) 1371 if (ret)
1374 goto error_release; 1372 goto error_release;
1375 1373
1376 #define FW_PACKET_MAX_DATA 16 1374 #define FW_ADDR 0x5100 /* firmware start address */
1377 1375 #define LEN_MAX 16 /* max packet size */
1378 packets = fw->size / FW_PACKET_MAX_DATA; 1376 for (remaining = fw->size; remaining > 0; remaining -= LEN_MAX) {
1379 remainder = fw->size % FW_PACKET_MAX_DATA; 1377 len = remaining;
1380 len = FW_PACKET_MAX_DATA; 1378 if (len > LEN_MAX)
1381 for (i = 0; i <= packets; i++) { 1379 len = LEN_MAX;
1382 if (i == packets) /* set size of the last packet */
1383 len = remainder;
1384
1385 data = (u8 *)(fw->data + i * FW_PACKET_MAX_DATA);
1386 ret = af9013_write_ofsm_regs(state, addr, data, len);
1387 addr += FW_PACKET_MAX_DATA;
1388 1380
1381 ret = af9013_write_ofsm_regs(state,
1382 FW_ADDR + fw->size - remaining,
1383 (u8 *) &fw->data[fw->size - remaining], len);
1389 if (ret) { 1384 if (ret) {
1390 err("firmware download failed at %d with %d", i, ret); 1385 err("firmware download failed:%d", ret);
1391 goto error_release; 1386 goto error_release;
1392 } 1387 }
1393 } 1388 }
@@ -1466,20 +1461,6 @@ struct dvb_frontend *af9013_attach(const struct af9013_config *config,
1466 state->i2c = i2c; 1461 state->i2c = i2c;
1467 memcpy(&state->config, config, sizeof(struct af9013_config)); 1462 memcpy(&state->config, config, sizeof(struct af9013_config));
1468 1463
1469 /* chip version */
1470 ret = af9013_read_reg_bits(state, 0xd733, 4, 4, &buf[2]);
1471 if (ret)
1472 goto error;
1473
1474 /* ROM version */
1475 for (i = 0; i < 2; i++) {
1476 ret = af9013_read_reg(state, 0x116b + i, &buf[i]);
1477 if (ret)
1478 goto error;
1479 }
1480 deb_info("%s: chip version:%d ROM version:%d.%d\n", __func__,
1481 buf[2], buf[0], buf[1]);
1482
1483 /* download firmware */ 1464 /* download firmware */
1484 if (state->config.output_mode != AF9013_OUTPUT_MODE_USB) { 1465 if (state->config.output_mode != AF9013_OUTPUT_MODE_USB) {
1485 ret = af9013_download_firmware(state); 1466 ret = af9013_download_firmware(state);
@@ -1495,6 +1476,20 @@ struct dvb_frontend *af9013_attach(const struct af9013_config *config,
1495 } 1476 }
1496 info("firmware version:%d.%d.%d.%d", buf[0], buf[1], buf[2], buf[3]); 1477 info("firmware version:%d.%d.%d.%d", buf[0], buf[1], buf[2], buf[3]);
1497 1478
1479 /* chip version */
1480 ret = af9013_read_reg_bits(state, 0xd733, 4, 4, &buf[2]);
1481 if (ret)
1482 goto error;
1483
1484 /* ROM version */
1485 for (i = 0; i < 2; i++) {
1486 ret = af9013_read_reg(state, 0x116b + i, &buf[i]);
1487 if (ret)
1488 goto error;
1489 }
1490 deb_info("%s: chip version:%d ROM version:%d.%d\n", __func__,
1491 buf[2], buf[0], buf[1]);
1492
1498 /* settings for mp2if */ 1493 /* settings for mp2if */
1499 if (state->config.output_mode == AF9013_OUTPUT_MODE_USB) { 1494 if (state->config.output_mode == AF9013_OUTPUT_MODE_USB) {
1500 /* AF9015 split PSB to 1.5k + 0.5k */ 1495 /* AF9015 split PSB to 1.5k + 0.5k */
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
index 65240b7801e8..52ff1a252a90 100644
--- a/drivers/media/dvb/frontends/dib0090.c
+++ b/drivers/media/dvb/frontends/dib0090.c
@@ -45,6 +45,7 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
45 } \ 45 } \
46} while (0) 46} while (0)
47 47
48#define CONFIG_SYS_DVBT
48#define CONFIG_SYS_ISDBT 49#define CONFIG_SYS_ISDBT
49#define CONFIG_BAND_CBAND 50#define CONFIG_BAND_CBAND
50#define CONFIG_BAND_VHF 51#define CONFIG_BAND_VHF
@@ -76,6 +77,34 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
76#define EN_SBD 0x44E9 77#define EN_SBD 0x44E9
77#define EN_CAB 0x88E9 78#define EN_CAB 0x88E9
78 79
80/* Calibration defines */
81#define DC_CAL 0x1
82#define WBD_CAL 0x2
83#define TEMP_CAL 0x4
84#define CAPTRIM_CAL 0x8
85
86#define KROSUS_PLL_LOCKED 0x800
87#define KROSUS 0x2
88
89/* Use those defines to identify SOC version */
90#define SOC 0x02
91#define SOC_7090_P1G_11R1 0x82
92#define SOC_7090_P1G_21R1 0x8a
93#define SOC_8090_P1G_11R1 0x86
94#define SOC_8090_P1G_21R1 0x8e
95
96/* else use thos ones to check */
97#define P1A_B 0x0
98#define P1C 0x1
99#define P1D_E_F 0x3
100#define P1G 0x7
101#define P1G_21R2 0xf
102
103#define MP001 0x1 /* Single 9090/8096 */
104#define MP005 0x4 /* Single Sband */
105#define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
106#define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
107
79#define pgm_read_word(w) (*w) 108#define pgm_read_word(w) (*w)
80 109
81struct dc_calibration; 110struct dc_calibration;
@@ -84,7 +113,7 @@ struct dib0090_tuning {
84 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */ 113 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
85 u8 switch_trim; 114 u8 switch_trim;
86 u8 lna_tune; 115 u8 lna_tune;
87 u8 lna_bias; 116 u16 lna_bias;
88 u16 v2i; 117 u16 v2i;
89 u16 mix; 118 u16 mix;
90 u16 load; 119 u16 load;
@@ -99,13 +128,19 @@ struct dib0090_pll {
99 u8 topresc; 128 u8 topresc;
100}; 129};
101 130
131struct dib0090_identity {
132 u8 version;
133 u8 product;
134 u8 p1g;
135 u8 in_soc;
136};
137
102struct dib0090_state { 138struct dib0090_state {
103 struct i2c_adapter *i2c; 139 struct i2c_adapter *i2c;
104 struct dvb_frontend *fe; 140 struct dvb_frontend *fe;
105 const struct dib0090_config *config; 141 const struct dib0090_config *config;
106 142
107 u8 current_band; 143 u8 current_band;
108 u16 revision;
109 enum frontend_tune_state tune_state; 144 enum frontend_tune_state tune_state;
110 u32 current_rf; 145 u32 current_rf;
111 146
@@ -143,7 +178,26 @@ struct dib0090_state {
143 u8 tuner_is_tuned; 178 u8 tuner_is_tuned;
144 u8 agc_freeze; 179 u8 agc_freeze;
145 180
146 u8 reset; 181 struct dib0090_identity identity;
182
183 u32 rf_request;
184 u8 current_standard;
185
186 u8 calibrate;
187 u32 rest;
188 u16 bias;
189 s16 temperature;
190
191 u8 wbd_calibration_gain;
192 const struct dib0090_wbd_slope *current_wbd_table;
193 u16 wbdmux;
194};
195
196struct dib0090_fw_state {
197 struct i2c_adapter *i2c;
198 struct dvb_frontend *fe;
199 struct dib0090_identity identity;
200 const struct dib0090_config *config;
147}; 201};
148 202
149static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) 203static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
@@ -171,6 +225,28 @@ static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
171 return 0; 225 return 0;
172} 226}
173 227
228static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
229{
230 u8 b[2];
231 struct i2c_msg msg = {.addr = reg, .flags = I2C_M_RD, .buf = b, .len = 2 };
232 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
233 printk(KERN_WARNING "DiB0090 I2C read failed\n");
234 return 0;
235 }
236 return (b[0] << 8) | b[1];
237}
238
239static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
240{
241 u8 b[2] = { val >> 8, val & 0xff };
242 struct i2c_msg msg = {.addr = reg, .flags = 0, .buf = b, .len = 2 };
243 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
244 printk(KERN_WARNING "DiB0090 I2C write failed\n");
245 return -EREMOTEIO;
246 }
247 return 0;
248}
249
174#define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0) 250#define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0)
175#define ADC_TARGET -220 251#define ADC_TARGET -220
176#define GAIN_ALPHA 5 252#define GAIN_ALPHA 5
@@ -183,89 +259,327 @@ static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b,
183 } while (--c); 259 } while (--c);
184} 260}
185 261
186static u16 dib0090_identify(struct dvb_frontend *fe) 262static int dib0090_identify(struct dvb_frontend *fe)
187{ 263{
188 struct dib0090_state *state = fe->tuner_priv; 264 struct dib0090_state *state = fe->tuner_priv;
189 u16 v; 265 u16 v;
266 struct dib0090_identity *identity = &state->identity;
190 267
191 v = dib0090_read_reg(state, 0x1a); 268 v = dib0090_read_reg(state, 0x1a);
192 269
193#ifdef FIRMWARE_FIREFLY 270 identity->p1g = 0;
194 /* pll is not locked locked */ 271 identity->in_soc = 0;
195 if (!(v & 0x800)) 272
196 dprintk("FE%d : Identification : pll is not yet locked", fe->id); 273 dprintk("Tuner identification (Version = 0x%04x)", v);
197#endif
198 274
199 /* without PLL lock info */ 275 /* without PLL lock info */
200 v &= 0x3ff; 276 v &= ~KROSUS_PLL_LOCKED;
201 dprintk("P/V: %04x:", v);
202 277
203 if ((v >> 8) & 0xf) 278 identity->version = v & 0xff;
204 dprintk("FE%d : Product ID = 0x%x : KROSUS", fe->id, (v >> 8) & 0xf); 279 identity->product = (v >> 8) & 0xf;
205 else 280
206 return 0xff; 281 if (identity->product != KROSUS)
207 282 goto identification_error;
208 v &= 0xff; 283
209 if (((v >> 5) & 0x7) == 0x1) 284 if ((identity->version & 0x3) == SOC) {
210 dprintk("FE%d : MP001 : 9090/8096", fe->id); 285 identity->in_soc = 1;
211 else if (((v >> 5) & 0x7) == 0x4) 286 switch (identity->version) {
212 dprintk("FE%d : MP005 : Single Sband", fe->id); 287 case SOC_8090_P1G_11R1:
213 else if (((v >> 5) & 0x7) == 0x6) 288 dprintk("SOC 8090 P1-G11R1 Has been detected");
214 dprintk("FE%d : MP008 : diversity VHF-UHF-LBAND", fe->id); 289 identity->p1g = 1;
215 else if (((v >> 5) & 0x7) == 0x7) 290 break;
216 dprintk("FE%d : MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND", fe->id); 291 case SOC_8090_P1G_21R1:
217 else 292 dprintk("SOC 8090 P1-G21R1 Has been detected");
218 return 0xff; 293 identity->p1g = 1;
219 294 break;
220 /* revision only */ 295 case SOC_7090_P1G_11R1:
221 if ((v & 0x1f) == 0x3) 296 dprintk("SOC 7090 P1-G11R1 Has been detected");
222 dprintk("FE%d : P1-D/E/F detected", fe->id); 297 identity->p1g = 1;
223 else if ((v & 0x1f) == 0x1) 298 break;
224 dprintk("FE%d : P1C detected", fe->id); 299 case SOC_7090_P1G_21R1:
225 else if ((v & 0x1f) == 0x0) { 300 dprintk("SOC 7090 P1-G21R1 Has been detected");
226#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT 301 identity->p1g = 1;
227 dprintk("FE%d : P1-A/B detected: using previous driver - support will be removed soon", fe->id); 302 break;
228 dib0090_p1b_register(fe); 303 default:
229#else 304 goto identification_error;
230 dprintk("FE%d : P1-A/B detected: driver is deactivated - not available", fe->id); 305 }
231 return 0xff; 306 } else {
232#endif 307 switch ((identity->version >> 5) & 0x7) {
308 case MP001:
309 dprintk("MP001 : 9090/8096");
310 break;
311 case MP005:
312 dprintk("MP005 : Single Sband");
313 break;
314 case MP008:
315 dprintk("MP008 : diversity VHF-UHF-LBAND");
316 break;
317 case MP009:
318 dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
319 break;
320 default:
321 goto identification_error;
322 }
323
324 switch (identity->version & 0x1f) {
325 case P1G_21R2:
326 dprintk("P1G_21R2 detected");
327 identity->p1g = 1;
328 break;
329 case P1G:
330 dprintk("P1G detected");
331 identity->p1g = 1;
332 break;
333 case P1D_E_F:
334 dprintk("P1D/E/F detected");
335 break;
336 case P1C:
337 dprintk("P1C detected");
338 break;
339 case P1A_B:
340 dprintk("P1-A/B detected: driver is deactivated - not available");
341 goto identification_error;
342 break;
343 default:
344 goto identification_error;
345 }
233 } 346 }
234 347
235 return v; 348 return 0;
349
350identification_error:
351 return -EIO;
352}
353
354static int dib0090_fw_identify(struct dvb_frontend *fe)
355{
356 struct dib0090_fw_state *state = fe->tuner_priv;
357 struct dib0090_identity *identity = &state->identity;
358
359 u16 v = dib0090_fw_read_reg(state, 0x1a);
360 identity->p1g = 0;
361 identity->in_soc = 0;
362
363 dprintk("FE: Tuner identification (Version = 0x%04x)", v);
364
365 /* without PLL lock info */
366 v &= ~KROSUS_PLL_LOCKED;
367
368 identity->version = v & 0xff;
369 identity->product = (v >> 8) & 0xf;
370
371 if (identity->product != KROSUS)
372 goto identification_error;
373
374 if ((identity->version & 0x3) == SOC) {
375 identity->in_soc = 1;
376 switch (identity->version) {
377 case SOC_8090_P1G_11R1:
378 dprintk("SOC 8090 P1-G11R1 Has been detected");
379 identity->p1g = 1;
380 break;
381 case SOC_8090_P1G_21R1:
382 dprintk("SOC 8090 P1-G21R1 Has been detected");
383 identity->p1g = 1;
384 break;
385 case SOC_7090_P1G_11R1:
386 dprintk("SOC 7090 P1-G11R1 Has been detected");
387 identity->p1g = 1;
388 break;
389 case SOC_7090_P1G_21R1:
390 dprintk("SOC 7090 P1-G21R1 Has been detected");
391 identity->p1g = 1;
392 break;
393 default:
394 goto identification_error;
395 }
396 } else {
397 switch ((identity->version >> 5) & 0x7) {
398 case MP001:
399 dprintk("MP001 : 9090/8096");
400 break;
401 case MP005:
402 dprintk("MP005 : Single Sband");
403 break;
404 case MP008:
405 dprintk("MP008 : diversity VHF-UHF-LBAND");
406 break;
407 case MP009:
408 dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
409 break;
410 default:
411 goto identification_error;
412 }
413
414 switch (identity->version & 0x1f) {
415 case P1G_21R2:
416 dprintk("P1G_21R2 detected");
417 identity->p1g = 1;
418 break;
419 case P1G:
420 dprintk("P1G detected");
421 identity->p1g = 1;
422 break;
423 case P1D_E_F:
424 dprintk("P1D/E/F detected");
425 break;
426 case P1C:
427 dprintk("P1C detected");
428 break;
429 case P1A_B:
430 dprintk("P1-A/B detected: driver is deactivated - not available");
431 goto identification_error;
432 break;
433 default:
434 goto identification_error;
435 }
436 }
437
438 return 0;
439
440identification_error:
441 return -EIO;;
236} 442}
237 443
238static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg) 444static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
239{ 445{
240 struct dib0090_state *state = fe->tuner_priv; 446 struct dib0090_state *state = fe->tuner_priv;
447 u16 PllCfg, i, v;
241 448
242 HARD_RESET(state); 449 HARD_RESET(state);
243 450
244 dib0090_write_reg(state, 0x24, EN_PLL); 451 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
245 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */ 452 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
246 453
247 /* adcClkOutRatio=8->7, release reset */ 454 if (!cfg->in_soc) {
248 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0); 455 /* adcClkOutRatio=8->7, release reset */
456 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
457 if (cfg->clkoutdrive != 0)
458 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
459 | (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
460 else
461 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
462 | (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
463 }
464
465 /* Read Pll current config * */
466 PllCfg = dib0090_read_reg(state, 0x21);
467
468 /** Reconfigure PLL if current setting is different from default setting **/
469 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
470 && !cfg->io.pll_bypass) {
471
472 /* Set Bypass mode */
473 PllCfg |= (1 << 15);
474 dib0090_write_reg(state, 0x21, PllCfg);
475
476 /* Set Reset Pll */
477 PllCfg &= ~(1 << 13);
478 dib0090_write_reg(state, 0x21, PllCfg);
479
480 /*** Set new Pll configuration in bypass and reset state ***/
481 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
482 dib0090_write_reg(state, 0x21, PllCfg);
483
484 /* Remove Reset Pll */
485 PllCfg |= (1 << 13);
486 dib0090_write_reg(state, 0x21, PllCfg);
487
488 /*** Wait for PLL lock ***/
489 i = 100;
490 do {
491 v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
492 if (v)
493 break;
494 } while (--i);
495
496 if (i == 0) {
497 dprintk("Pll: Unable to lock Pll");
498 return;
499 }
500
501 /* Finally Remove Bypass mode */
502 PllCfg &= ~(1 << 15);
503 dib0090_write_reg(state, 0x21, PllCfg);
504 }
505
506 if (cfg->io.pll_bypass) {
507 PllCfg |= (cfg->io.pll_bypass << 15);
508 dib0090_write_reg(state, 0x21, PllCfg);
509 }
510}
511
512static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
513{
514 struct dib0090_fw_state *state = fe->tuner_priv;
515 u16 PllCfg;
516 u16 v;
517 int i;
518
519 dprintk("fw reset digital");
520 HARD_RESET(state);
521
522 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
523 dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
524
525 dib0090_fw_write_reg(state, 0x20,
526 ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) | cfg->ls_cfg_pad_drv);
527
528 v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
249 if (cfg->clkoutdrive != 0) 529 if (cfg->clkoutdrive != 0)
250 dib0090_write_reg(state, 0x23, 530 v |= cfg->clkoutdrive << 5;
251 (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (cfg->clkoutdrive << 5) | (cfg->
252 clkouttobamse
253 << 4) | (0
254 <<
255 2)
256 | (0));
257 else 531 else
258 dib0090_write_reg(state, 0x23, 532 v |= 7 << 5;
259 (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (7 << 5) | (cfg-> 533
260 clkouttobamse << 4) | (0 534 v |= 2 << 10;
261 << 535 dib0090_fw_write_reg(state, 0x23, v);
262 2) 536
263 | (0)); 537 /* Read Pll current config * */
538 PllCfg = dib0090_fw_read_reg(state, 0x21);
539
540 /** Reconfigure PLL if current setting is different from default setting **/
541 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
264 542
265 /* enable pll, de-activate reset, ratio: 2/1 = 60MHz */ 543 /* Set Bypass mode */
266 dib0090_write_reg(state, 0x21, 544 PllCfg |= (1 << 15);
267 (cfg->io.pll_bypass << 15) | (1 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)); 545 dib0090_fw_write_reg(state, 0x21, PllCfg);
268 546
547 /* Set Reset Pll */
548 PllCfg &= ~(1 << 13);
549 dib0090_fw_write_reg(state, 0x21, PllCfg);
550
551 /*** Set new Pll configuration in bypass and reset state ***/
552 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
553 dib0090_fw_write_reg(state, 0x21, PllCfg);
554
555 /* Remove Reset Pll */
556 PllCfg |= (1 << 13);
557 dib0090_fw_write_reg(state, 0x21, PllCfg);
558
559 /*** Wait for PLL lock ***/
560 i = 100;
561 do {
562 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
563 if (v)
564 break;
565 } while (--i);
566
567 if (i == 0) {
568 dprintk("Pll: Unable to lock Pll");
569 return -EIO;
570 }
571
572 /* Finally Remove Bypass mode */
573 PllCfg &= ~(1 << 15);
574 dib0090_fw_write_reg(state, 0x21, PllCfg);
575 }
576
577 if (cfg->io.pll_bypass) {
578 PllCfg |= (cfg->io.pll_bypass << 15);
579 dib0090_fw_write_reg(state, 0x21, PllCfg);
580 }
581
582 return dib0090_fw_identify(fe);
269} 583}
270 584
271static int dib0090_wakeup(struct dvb_frontend *fe) 585static int dib0090_wakeup(struct dvb_frontend *fe)
@@ -273,6 +587,9 @@ static int dib0090_wakeup(struct dvb_frontend *fe)
273 struct dib0090_state *state = fe->tuner_priv; 587 struct dib0090_state *state = fe->tuner_priv;
274 if (state->config->sleep) 588 if (state->config->sleep)
275 state->config->sleep(fe, 0); 589 state->config->sleep(fe, 0);
590
591 /* enable dataTX in case we have been restarted in the wrong moment */
592 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
276 return 0; 593 return 0;
277} 594}
278 595
@@ -292,8 +609,75 @@ void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
292 else 609 else
293 dib0090_write_reg(state, 0x04, 1); 610 dib0090_write_reg(state, 0x04, 1);
294} 611}
612
295EXPORT_SYMBOL(dib0090_dcc_freq); 613EXPORT_SYMBOL(dib0090_dcc_freq);
296 614
615static const u16 bb_ramp_pwm_normal_socs[] = {
616 550, /* max BB gain in 10th of dB */
617 (1 << 9) | 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
618 440,
619 (4 << 9) | 0, /* BB_RAMP3 = 26dB */
620 (0 << 9) | 208, /* BB_RAMP4 */
621 (4 << 9) | 208, /* BB_RAMP5 = 29dB */
622 (0 << 9) | 440, /* BB_RAMP6 */
623};
624
625static const u16 rf_ramp_pwm_cband_7090[] = {
626 280, /* max RF gain in 10th of dB */
627 18, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
628 504, /* ramp_max = maximum X used on the ramp */
629 (29 << 10) | 364, /* RF_RAMP5, LNA 1 = 8dB */
630 (0 << 10) | 504, /* RF_RAMP6, LNA 1 */
631 (60 << 10) | 228, /* RF_RAMP7, LNA 2 = 7.7dB */
632 (0 << 10) | 364, /* RF_RAMP8, LNA 2 */
633 (34 << 10) | 109, /* GAIN_4_1, LNA 3 = 6.8dB */
634 (0 << 10) | 228, /* GAIN_4_2, LNA 3 */
635 (37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
636 (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
637};
638
639static const u16 rf_ramp_pwm_cband_8090[] = {
640 345, /* max RF gain in 10th of dB */
641 29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
642 1000, /* ramp_max = maximum X used on the ramp */
643 (35 << 10) | 772, /* RF_RAMP3, LNA 1 = 8dB */
644 (0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
645 (58 << 10) | 496, /* RF_RAMP5, LNA 2 = 9.5dB */
646 (0 << 10) | 772, /* RF_RAMP6, LNA 2 */
647 (27 << 10) | 200, /* RF_RAMP7, LNA 3 = 10.5dB */
648 (0 << 10) | 496, /* RF_RAMP8, LNA 3 */
649 (40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
650 (0 << 10) | 200, /* GAIN_4_2, LNA 4 */
651};
652
653static const u16 rf_ramp_pwm_uhf_7090[] = {
654 407, /* max RF gain in 10th of dB */
655 13, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
656 529, /* ramp_max = maximum X used on the ramp */
657 (23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
658 (0 << 10) | 176, /* RF_RAMP4, LNA 1 */
659 (63 << 10) | 400, /* RF_RAMP5, LNA 2 = 8dB */
660 (0 << 10) | 529, /* RF_RAMP6, LNA 2 */
661 (48 << 10) | 316, /* RF_RAMP7, LNA 3 = 6.8dB */
662 (0 << 10) | 400, /* RF_RAMP8, LNA 3 */
663 (29 << 10) | 176, /* GAIN_4_1, LNA 4 = 11.5dB */
664 (0 << 10) | 316, /* GAIN_4_2, LNA 4 */
665};
666
667static const u16 rf_ramp_pwm_uhf_8090[] = {
668 388, /* max RF gain in 10th of dB */
669 26, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
670 1008, /* ramp_max = maximum X used on the ramp */
671 (11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
672 (0 << 10) | 369, /* RF_RAMP4, LNA 1 */
673 (41 << 10) | 809, /* RF_RAMP5, LNA 2 = 8dB */
674 (0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
675 (27 << 10) | 659, /* RF_RAMP7, LNA 3 = 6dB */
676 (0 << 10) | 809, /* RF_RAMP8, LNA 3 */
677 (14 << 10) | 369, /* GAIN_4_1, LNA 4 = 11.5dB */
678 (0 << 10) | 659, /* GAIN_4_2, LNA 4 */
679};
680
297static const u16 rf_ramp_pwm_cband[] = { 681static const u16 rf_ramp_pwm_cband[] = {
298 0, /* max RF gain in 10th of dB */ 682 0, /* max RF gain in 10th of dB */
299 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */ 683 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
@@ -326,6 +710,16 @@ static const u16 rf_ramp_uhf[] = {
326 0, 0, 127, /* CBAND : 0.0 dB */ 710 0, 0, 127, /* CBAND : 0.0 dB */
327}; 711};
328 712
713static const u16 rf_ramp_cband_broadmatching[] = /* for p1G only */
714{
715 314, /* Calibrated at 200MHz order has been changed g4-g3-g2-g1 */
716 84, 314, 127, /* LNA1 */
717 80, 230, 255, /* LNA2 */
718 80, 150, 127, /* LNA3 It was measured 12dB, do not lock if 120 */
719 70, 70, 127, /* LNA4 */
720 0, 0, 127, /* CBAND */
721};
722
329static const u16 rf_ramp_cband[] = { 723static const u16 rf_ramp_cband[] = {
330 332, /* max RF gain in 10th of dB */ 724 332, /* max RF gain in 10th of dB */
331 132, 252, 127, /* LNA1, dB */ 725 132, 252, 127, /* LNA1, dB */
@@ -380,8 +774,8 @@ static const u16 bb_ramp_pwm_normal[] = {
380}; 774};
381 775
382struct slope { 776struct slope {
383 int16_t range; 777 s16 range;
384 int16_t slope; 778 s16 slope;
385}; 779};
386static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val) 780static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
387{ 781{
@@ -597,19 +991,39 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
597#endif 991#endif
598#ifdef CONFIG_BAND_CBAND 992#ifdef CONFIG_BAND_CBAND
599 if (state->current_band == BAND_CBAND) { 993 if (state->current_band == BAND_CBAND) {
600 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband); 994 if (state->identity.in_soc) {
601 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 995 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
996 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
997 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090);
998 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
999 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090);
1000 } else {
1001 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
1002 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1003 }
602 } else 1004 } else
603#endif 1005#endif
604#ifdef CONFIG_BAND_VHF 1006#ifdef CONFIG_BAND_VHF
605 if (state->current_band == BAND_VHF) { 1007 if (state->current_band == BAND_VHF) {
606 dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf); 1008 if (state->identity.in_soc) {
607 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 1009 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
1010 } else {
1011 dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
1012 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1013 }
608 } else 1014 } else
609#endif 1015#endif
610 { 1016 {
611 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf); 1017 if (state->identity.in_soc) {
612 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 1018 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1019 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_8090);
1020 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
1021 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_7090);
1022 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
1023 } else {
1024 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
1025 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1026 }
613 } 1027 }
614 1028
615 if (state->rf_ramp[0] != 0) 1029 if (state->rf_ramp[0] != 0)
@@ -617,11 +1031,21 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
617 else 1031 else
618 dib0090_write_reg(state, 0x32, (0 << 11)); 1032 dib0090_write_reg(state, 0x32, (0 << 11));
619 1033
1034 dib0090_write_reg(state, 0x04, 0x01);
620 dib0090_write_reg(state, 0x39, (1 << 10)); 1035 dib0090_write_reg(state, 0x39, (1 << 10));
621 } 1036 }
622} 1037}
1038
623EXPORT_SYMBOL(dib0090_pwm_gain_reset); 1039EXPORT_SYMBOL(dib0090_pwm_gain_reset);
624 1040
1041static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
1042{
1043 u16 adc_val = dib0090_read_reg(state, 0x1d);
1044 if (state->identity.in_soc)
1045 adc_val >>= 2;
1046 return adc_val;
1047}
1048
625int dib0090_gain_control(struct dvb_frontend *fe) 1049int dib0090_gain_control(struct dvb_frontend *fe)
626{ 1050{
627 struct dib0090_state *state = fe->tuner_priv; 1051 struct dib0090_state *state = fe->tuner_priv;
@@ -643,18 +1067,21 @@ int dib0090_gain_control(struct dvb_frontend *fe)
643 } else 1067 } else
644#endif 1068#endif
645#ifdef CONFIG_BAND_VHF 1069#ifdef CONFIG_BAND_VHF
646 if (state->current_band == BAND_VHF) { 1070 if (state->current_band == BAND_VHF && !state->identity.p1g) {
647 dib0090_set_rframp(state, rf_ramp_vhf); 1071 dib0090_set_rframp(state, rf_ramp_vhf);
648 dib0090_set_bbramp(state, bb_ramp_boost); 1072 dib0090_set_bbramp(state, bb_ramp_boost);
649 } else 1073 } else
650#endif 1074#endif
651#ifdef CONFIG_BAND_CBAND 1075#ifdef CONFIG_BAND_CBAND
652 if (state->current_band == BAND_CBAND) { 1076 if (state->current_band == BAND_CBAND && !state->identity.p1g) {
653 dib0090_set_rframp(state, rf_ramp_cband); 1077 dib0090_set_rframp(state, rf_ramp_cband);
654 dib0090_set_bbramp(state, bb_ramp_boost); 1078 dib0090_set_bbramp(state, bb_ramp_boost);
655 } else 1079 } else
656#endif 1080#endif
657 { 1081 if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) {
1082 dib0090_set_rframp(state, rf_ramp_cband_broadmatching);
1083 dib0090_set_bbramp(state, bb_ramp_boost);
1084 } else {
658 dib0090_set_rframp(state, rf_ramp_uhf); 1085 dib0090_set_rframp(state, rf_ramp_uhf);
659 dib0090_set_bbramp(state, bb_ramp_boost); 1086 dib0090_set_bbramp(state, bb_ramp_boost);
660 } 1087 }
@@ -669,17 +1096,25 @@ int dib0090_gain_control(struct dvb_frontend *fe)
669 1096
670 *tune_state = CT_AGC_STEP_0; 1097 *tune_state = CT_AGC_STEP_0;
671 } else if (!state->agc_freeze) { 1098 } else if (!state->agc_freeze) {
672 s16 wbd; 1099 s16 wbd = 0, i, cnt;
673 1100
674 int adc; 1101 int adc;
675 wbd_val = dib0090_read_reg(state, 0x1d); 1102 wbd_val = dib0090_get_slow_adc_val(state);
676 1103
677 /* read and calc the wbd power */ 1104 if (*tune_state == CT_AGC_STEP_0)
678 wbd = dib0090_wbd_to_db(state, wbd_val); 1105 cnt = 5;
1106 else
1107 cnt = 1;
1108
1109 for (i = 0; i < cnt; i++) {
1110 wbd_val = dib0090_get_slow_adc_val(state);
1111 wbd += dib0090_wbd_to_db(state, wbd_val);
1112 }
1113 wbd /= cnt;
679 wbd_error = state->wbd_target - wbd; 1114 wbd_error = state->wbd_target - wbd;
680 1115
681 if (*tune_state == CT_AGC_STEP_0) { 1116 if (*tune_state == CT_AGC_STEP_0) {
682 if (wbd_error < 0 && state->rf_gain_limit > 0) { 1117 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {
683#ifdef CONFIG_BAND_CBAND 1118#ifdef CONFIG_BAND_CBAND
684 /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */ 1119 /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
685 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; 1120 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
@@ -700,39 +1135,39 @@ int dib0090_gain_control(struct dvb_frontend *fe)
700 adc_error = (s16) (((s32) ADC_TARGET) - adc); 1135 adc_error = (s16) (((s32) ADC_TARGET) - adc);
701#ifdef CONFIG_STANDARD_DAB 1136#ifdef CONFIG_STANDARD_DAB
702 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) 1137 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
703 adc_error += 130; 1138 adc_error -= 10;
704#endif 1139#endif
705#ifdef CONFIG_STANDARD_DVBT 1140#ifdef CONFIG_STANDARD_DVBT
706 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT && 1141 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
707 (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16)) 1142 (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
708 adc_error += 60; 1143 adc_error += 60;
709#endif 1144#endif
710#ifdef CONFIG_SYS_ISDBT 1145#ifdef CONFIG_SYS_ISDBT
711 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count > 1146 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
712 0) 1147 0)
713 && 1148 &&
714 ((state->fe->dtv_property_cache.layer[0].modulation == 1149 ((state->fe->dtv_property_cache.layer[0].modulation ==
715 QAM_64) 1150 QAM_64)
716 || (state->fe->dtv_property_cache.layer[0]. 1151 || (state->fe->dtv_property_cache.
717 modulation == QAM_16))) 1152 layer[0].modulation == QAM_16)))
718 || 1153 ||
719 ((state->fe->dtv_property_cache.layer[1].segment_count > 1154 ((state->fe->dtv_property_cache.layer[1].segment_count >
720 0) 1155 0)
721 && 1156 &&
722 ((state->fe->dtv_property_cache.layer[1].modulation == 1157 ((state->fe->dtv_property_cache.layer[1].modulation ==
723 QAM_64) 1158 QAM_64)
724 || (state->fe->dtv_property_cache.layer[1]. 1159 || (state->fe->dtv_property_cache.
725 modulation == QAM_16))) 1160 layer[1].modulation == QAM_16)))
726 || 1161 ||
727 ((state->fe->dtv_property_cache.layer[2].segment_count > 1162 ((state->fe->dtv_property_cache.layer[2].segment_count >
728 0) 1163 0)
729 && 1164 &&
730 ((state->fe->dtv_property_cache.layer[2].modulation == 1165 ((state->fe->dtv_property_cache.layer[2].modulation ==
731 QAM_64) 1166 QAM_64)
732 || (state->fe->dtv_property_cache.layer[2]. 1167 || (state->fe->dtv_property_cache.
733 modulation == QAM_16))) 1168 layer[2].modulation == QAM_16)))
734 ) 1169 )
735 ) 1170 )
736 adc_error += 60; 1171 adc_error += 60;
737#endif 1172#endif
738 1173
@@ -760,9 +1195,9 @@ int dib0090_gain_control(struct dvb_frontend *fe)
760 } 1195 }
761#ifdef DEBUG_AGC 1196#ifdef DEBUG_AGC
762 dprintk 1197 dprintk
763 ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm", 1198 ("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
764 (u32) fe->id, (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val, 1199 (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
765 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); 1200 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
766#endif 1201#endif
767 } 1202 }
768 1203
@@ -771,6 +1206,7 @@ int dib0090_gain_control(struct dvb_frontend *fe)
771 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); 1206 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
772 return ret; 1207 return ret;
773} 1208}
1209
774EXPORT_SYMBOL(dib0090_gain_control); 1210EXPORT_SYMBOL(dib0090_gain_control);
775 1211
776void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt) 1212void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
@@ -785,13 +1221,47 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
785 if (rflt) 1221 if (rflt)
786 *rflt = (state->rf_lt_def >> 10) & 0x7; 1222 *rflt = (state->rf_lt_def >> 10) & 0x7;
787} 1223}
1224
788EXPORT_SYMBOL(dib0090_get_current_gain); 1225EXPORT_SYMBOL(dib0090_get_current_gain);
789 1226
790u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner) 1227u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
791{ 1228{
792 struct dib0090_state *st = tuner->tuner_priv; 1229 struct dib0090_state *state = fe->tuner_priv;
793 return st->wbd_offset; 1230 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
1231 s32 current_temp = state->temperature;
1232 s32 wbd_thot, wbd_tcold;
1233 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1234
1235 while (f_MHz > wbd->max_freq)
1236 wbd++;
1237
1238 dprintk("using wbd-table-entry with max freq %d", wbd->max_freq);
1239
1240 if (current_temp < 0)
1241 current_temp = 0;
1242 if (current_temp > 128)
1243 current_temp = 128;
1244
1245 state->wbdmux &= ~(7 << 13);
1246 if (wbd->wbd_gain != 0)
1247 state->wbdmux |= (wbd->wbd_gain << 13);
1248 else
1249 state->wbdmux |= (4 << 13);
1250
1251 dib0090_write_reg(state, 0x10, state->wbdmux);
1252
1253 wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
1254 wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
1255
1256 wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
1257
1258 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);
1259 dprintk("wbd-target: %d dB", (u32) state->wbd_target);
1260 dprintk("wbd offset applied is %d", wbd_tcold);
1261
1262 return state->wbd_offset + wbd_tcold;
794} 1263}
1264
795EXPORT_SYMBOL(dib0090_get_wbd_offset); 1265EXPORT_SYMBOL(dib0090_get_wbd_offset);
796 1266
797static const u16 dib0090_defaults[] = { 1267static const u16 dib0090_defaults[] = {
@@ -801,7 +1271,7 @@ static const u16 dib0090_defaults[] = {
801 0x99a0, 1271 0x99a0,
802 0x6008, 1272 0x6008,
803 0x0000, 1273 0x0000,
804 0x8acb, 1274 0x8bcb,
805 0x0000, 1275 0x0000,
806 0x0405, 1276 0x0405,
807 0x0000, 1277 0x0000,
@@ -829,8 +1299,6 @@ static const u16 dib0090_defaults[] = {
829 1, 0x39, 1299 1, 0x39,
830 0x0000, 1300 0x0000,
831 1301
832 1, 0x1b,
833 EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL,
834 2, 0x1e, 1302 2, 0x1e,
835 0x07FF, 1303 0x07FF,
836 0x0007, 1304 0x0007,
@@ -844,50 +1312,125 @@ static const u16 dib0090_defaults[] = {
844 0 1312 0
845}; 1313};
846 1314
847static int dib0090_reset(struct dvb_frontend *fe) 1315static const u16 dib0090_p1g_additionnal_defaults[] = {
848{ 1316 1, 0x05,
849 struct dib0090_state *state = fe->tuner_priv; 1317 0xabcd,
850 u16 l, r, *n;
851 1318
852 dib0090_reset_digital(fe, state->config); 1319 1, 0x11,
853 state->revision = dib0090_identify(fe); 1320 0x00b4,
854 1321
855 /* Revision definition */ 1322 1, 0x1c,
856 if (state->revision == 0xff) 1323 0xfffd,
857 return -EINVAL;
858#ifdef EFUSE
859 else if ((state->revision & 0x1f) >= 3) /* Update the efuse : Only available for KROSUS > P1C */
860 dib0090_set_EFUSE(state);
861#endif
862 1324
863#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT 1325 1, 0x40,
864 if (!(state->revision & 0x1)) /* it is P1B - reset is already done */ 1326 0x108,
865 return 0; 1327 0
866#endif 1328};
1329
1330static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)
1331{
1332 u16 l, r;
867 1333
868 /* Upload the default values */
869 n = (u16 *) dib0090_defaults;
870 l = pgm_read_word(n++); 1334 l = pgm_read_word(n++);
871 while (l) { 1335 while (l) {
872 r = pgm_read_word(n++); 1336 r = pgm_read_word(n++);
873 do { 1337 do {
874 /* DEBUG_TUNER */
875 /* dprintk("%d, %d, %d", l, r, pgm_read_word(n)); */
876 dib0090_write_reg(state, r, pgm_read_word(n++)); 1338 dib0090_write_reg(state, r, pgm_read_word(n++));
877 r++; 1339 r++;
878 } while (--l); 1340 } while (--l);
879 l = pgm_read_word(n++); 1341 l = pgm_read_word(n++);
880 } 1342 }
1343}
1344
1345#define CAP_VALUE_MIN (u8) 9
1346#define CAP_VALUE_MAX (u8) 40
1347#define HR_MIN (u8) 25
1348#define HR_MAX (u8) 40
1349#define POLY_MIN (u8) 0
1350#define POLY_MAX (u8) 8
1351
1352void dib0090_set_EFUSE(struct dib0090_state *state)
1353{
1354 u8 c, h, n;
1355 u16 e2, e4;
1356 u16 cal;
1357
1358 e2 = dib0090_read_reg(state, 0x26);
1359 e4 = dib0090_read_reg(state, 0x28);
1360
1361 if ((state->identity.version == P1D_E_F) ||
1362 (state->identity.version == P1G) || (e2 == 0xffff)) {
1363
1364 dib0090_write_reg(state, 0x22, 0x10);
1365 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;
1366
1367 if ((cal < 670) || (cal == 1023))
1368 cal = 850;
1369 n = 165 - ((cal * 10)>>6) ;
1370 e2 = e4 = (3<<12) | (34<<6) | (n);
1371 }
1372
1373 if (e2 != e4)
1374 e2 &= e4; /* Remove the redundancy */
1375
1376 if (e2 != 0xffff) {
1377 c = e2 & 0x3f;
1378 n = (e2 >> 12) & 0xf;
1379 h = (e2 >> 6) & 0x3f;
1380
1381 if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
1382 c = 32;
1383 if ((h >= HR_MAX) || (h <= HR_MIN))
1384 h = 34;
1385 if ((n >= POLY_MAX) || (n <= POLY_MIN))
1386 n = 3;
1387
1388 dib0090_write_reg(state, 0x13, (h << 10)) ;
1389 e2 = (n<<11) | ((h>>2)<<6) | (c);
1390 dib0090_write_reg(state, 0x2, e2) ; /* Load the BB_2 */
1391 }
1392}
1393
1394static int dib0090_reset(struct dvb_frontend *fe)
1395{
1396 struct dib0090_state *state = fe->tuner_priv;
1397
1398 dib0090_reset_digital(fe, state->config);
1399 if (dib0090_identify(fe) < 0)
1400 return -EIO;
1401
1402#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
1403 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */
1404 return 0;
1405#endif
1406
1407 if (!state->identity.in_soc) {
1408 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
1409 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1410 else
1411 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1412 }
1413
1414 dib0090_set_default_config(state, dib0090_defaults);
1415
1416 if (state->identity.in_soc)
1417 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
1418
1419 if (state->identity.p1g)
1420 dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
1421
1422 /* Update the efuse : Only available for KROSUS > P1C and SOC as well*/
1423 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc))
1424 dib0090_set_EFUSE(state);
881 1425
882 /* Congigure in function of the crystal */ 1426 /* Congigure in function of the crystal */
883 if (state->config->io.clock_khz >= 24000) 1427 if (state->config->io.clock_khz >= 24000)
884 l = 1; 1428 dib0090_write_reg(state, 0x14, 1);
885 else 1429 else
886 l = 2; 1430 dib0090_write_reg(state, 0x14, 2);
887 dib0090_write_reg(state, 0x14, l);
888 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); 1431 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
889 1432
890 state->reset = 3; /* enable iq-offset-calibration and wbd-calibration when tuning next time */ 1433 state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
891 1434
892 return 0; 1435 return 0;
893} 1436}
@@ -927,11 +1470,11 @@ static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_st
927} 1470}
928 1471
929struct dc_calibration { 1472struct dc_calibration {
930 uint8_t addr; 1473 u8 addr;
931 uint8_t offset; 1474 u8 offset;
932 uint8_t pga:1; 1475 u8 pga:1;
933 uint16_t bb1; 1476 u16 bb1;
934 uint8_t i:1; 1477 u8 i:1;
935}; 1478};
936 1479
937static const struct dc_calibration dc_table[] = { 1480static const struct dc_calibration dc_table[] = {
@@ -944,6 +1487,17 @@ static const struct dc_calibration dc_table[] = {
944 {0}, 1487 {0},
945}; 1488};
946 1489
1490static const struct dc_calibration dc_p1g_table[] = {
1491 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1492 /* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
1493 {0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
1494 {0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
1495 /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
1496 {0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
1497 {0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
1498 {0},
1499};
1500
947static void dib0090_set_trim(struct dib0090_state *state) 1501static void dib0090_set_trim(struct dib0090_state *state)
948{ 1502{
949 u16 *val; 1503 u16 *val;
@@ -962,41 +1516,45 @@ static void dib0090_set_trim(struct dib0090_state *state)
962static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) 1516static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
963{ 1517{
964 int ret = 0; 1518 int ret = 0;
1519 u16 reg;
965 1520
966 switch (*tune_state) { 1521 switch (*tune_state) {
967
968 case CT_TUNER_START: 1522 case CT_TUNER_START:
969 /* init */ 1523 dprintk("Start DC offset calibration");
970 dprintk("Internal DC calibration");
971
972 /* the LNA is off */
973 dib0090_write_reg(state, 0x24, 0x02ed);
974 1524
975 /* force vcm2 = 0.8V */ 1525 /* force vcm2 = 0.8V */
976 state->bb6 = 0; 1526 state->bb6 = 0;
977 state->bb7 = 0x040d; 1527 state->bb7 = 0x040d;
978 1528
1529 /* the LNA AND LO are off */
1530 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
1531 dib0090_write_reg(state, 0x24, reg);
1532
1533 state->wbdmux = dib0090_read_reg(state, 0x10);
1534 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);
1535 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
1536
979 state->dc = dc_table; 1537 state->dc = dc_table;
980 1538
1539 if (state->identity.p1g)
1540 state->dc = dc_p1g_table;
981 *tune_state = CT_TUNER_STEP_0; 1541 *tune_state = CT_TUNER_STEP_0;
982 1542
983 /* fall through */ 1543 /* fall through */
984 1544
985 case CT_TUNER_STEP_0: 1545 case CT_TUNER_STEP_0:
1546 dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q");
986 dib0090_write_reg(state, 0x01, state->dc->bb1); 1547 dib0090_write_reg(state, 0x01, state->dc->bb1);
987 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); 1548 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
988 1549
989 state->step = 0; 1550 state->step = 0;
990
991 state->min_adc_diff = 1023; 1551 state->min_adc_diff = 1023;
992
993 *tune_state = CT_TUNER_STEP_1; 1552 *tune_state = CT_TUNER_STEP_1;
994 ret = 50; 1553 ret = 50;
995 break; 1554 break;
996 1555
997 case CT_TUNER_STEP_1: 1556 case CT_TUNER_STEP_1:
998 dib0090_set_trim(state); 1557 dib0090_set_trim(state);
999
1000 *tune_state = CT_TUNER_STEP_2; 1558 *tune_state = CT_TUNER_STEP_2;
1001 break; 1559 break;
1002 1560
@@ -1007,7 +1565,13 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1007 break; 1565 break;
1008 1566
1009 case CT_TUNER_STEP_5: /* found an offset */ 1567 case CT_TUNER_STEP_5: /* found an offset */
1010 dprintk("FE%d: IQC read=%d, current=%x", state->fe->id, (u32) state->adc_diff, state->step); 1568 dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step);
1569 if (state->step == 0 && state->adc_diff < 0) {
1570 state->min_adc_diff = -1023;
1571 dprintk("Change of sign of the minimum adc diff");
1572 }
1573
1574 dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state->step);
1011 1575
1012 /* first turn for this frequency */ 1576 /* first turn for this frequency */
1013 if (state->step == 0) { 1577 if (state->step == 0) {
@@ -1017,20 +1581,21 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1017 state->step = 0x10; 1581 state->step = 0x10;
1018 } 1582 }
1019 1583
1020 state->adc_diff = ABS(state->adc_diff); 1584 /* Look for a change of Sign in the Adc_diff.min_adc_diff is used to STORE the setp N-1 */
1021 1585 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
1022 if (state->adc_diff < state->min_adc_diff && steps(state->step) < 15) { /* stop search when the delta to 0 is increasing */ 1586 /* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
1023 state->step++; 1587 state->step++;
1024 state->min_adc_diff = state->adc_diff; 1588 state->min_adc_diff = state->adc_diff;
1025 *tune_state = CT_TUNER_STEP_1; 1589 *tune_state = CT_TUNER_STEP_1;
1026 } else { 1590 } else {
1027
1028 /* the minimum was what we have seen in the step before */ 1591 /* the minimum was what we have seen in the step before */
1029 state->step--; 1592 if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) {
1030 dib0090_set_trim(state); 1593 dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_diff);
1594 state->step--;
1595 }
1031 1596
1032 dprintk("FE%d: BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->fe->id, state->dc->addr, state->adc_diff, 1597 dib0090_set_trim(state);
1033 state->step); 1598 dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->step);
1034 1599
1035 state->dc++; 1600 state->dc++;
1036 if (state->dc->addr == 0) /* done */ 1601 if (state->dc->addr == 0) /* done */
@@ -1045,7 +1610,7 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1045 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); 1610 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
1046 dib0090_write_reg(state, 0x1f, 0x7); 1611 dib0090_write_reg(state, 0x1f, 0x7);
1047 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ 1612 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
1048 state->reset &= ~0x1; 1613 state->calibrate &= ~DC_CAL;
1049 default: 1614 default:
1050 break; 1615 break;
1051 } 1616 }
@@ -1054,21 +1619,43 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1054 1619
1055static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) 1620static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1056{ 1621{
1622 u8 wbd_gain;
1623 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1624
1057 switch (*tune_state) { 1625 switch (*tune_state) {
1058 case CT_TUNER_START: 1626 case CT_TUNER_START:
1059 /* WBD-mode=log, Bias=2, Gain=6, Testmode=1, en=1, WBDMUX=1 */ 1627 while (state->current_rf / 1000 > wbd->max_freq)
1060 dib0090_write_reg(state, 0x10, 0xdb09 | (1 << 10)); 1628 wbd++;
1061 dib0090_write_reg(state, 0x24, EN_UHF & 0x0fff); 1629 if (wbd->wbd_gain != 0)
1630 wbd_gain = wbd->wbd_gain;
1631 else {
1632 wbd_gain = 4;
1633#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
1634 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))
1635 wbd_gain = 2;
1636#endif
1637 }
1638
1639 if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */
1640 *tune_state = CT_TUNER_START;
1641 state->calibrate &= ~WBD_CAL;
1642 return 0;
1643 }
1644
1645 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));
1062 1646
1647 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));
1063 *tune_state = CT_TUNER_STEP_0; 1648 *tune_state = CT_TUNER_STEP_0;
1649 state->wbd_calibration_gain = wbd_gain;
1064 return 90; /* wait for the WBDMUX to switch and for the ADC to sample */ 1650 return 90; /* wait for the WBDMUX to switch and for the ADC to sample */
1651
1065 case CT_TUNER_STEP_0: 1652 case CT_TUNER_STEP_0:
1066 state->wbd_offset = dib0090_read_reg(state, 0x1d); 1653 state->wbd_offset = dib0090_get_slow_adc_val(state);
1067 dprintk("WBD calibration offset = %d", state->wbd_offset); 1654 dprintk("WBD calibration offset = %d", state->wbd_offset);
1068
1069 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ 1655 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
1070 state->reset &= ~0x2; 1656 state->calibrate &= ~WBD_CAL;
1071 break; 1657 break;
1658
1072 default: 1659 default:
1073 break; 1660 break;
1074 } 1661 }
@@ -1092,6 +1679,15 @@ static void dib0090_set_bandwidth(struct dib0090_state *state)
1092 state->bb_1_def |= tmp; 1679 state->bb_1_def |= tmp;
1093 1680
1094 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ 1681 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
1682
1683 dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
1684 dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
1685 if (state->identity.in_soc) {
1686 dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
1687 } else {
1688 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
1689 dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
1690 }
1095} 1691}
1096 1692
1097static const struct dib0090_pll dib0090_pll_table[] = { 1693static const struct dib0090_pll dib0090_pll_table[] = {
@@ -1180,6 +1776,255 @@ static const struct dib0090_tuning dib0090_tuning_table[] = {
1180#endif 1776#endif
1181}; 1777};
1182 1778
1779static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
1780#ifdef CONFIG_BAND_CBAND
1781 {170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
1782#endif
1783#ifdef CONFIG_BAND_VHF
1784 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1785 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1786 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1787#endif
1788#ifdef CONFIG_BAND_UHF
1789 {510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1790 {540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1791 {600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1792 {630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1793 {680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1794 {720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1795 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1796#endif
1797#ifdef CONFIG_BAND_LBAND
1798 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1799 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1800 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1801#endif
1802#ifdef CONFIG_BAND_SBAND
1803 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1804 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1805#endif
1806};
1807
1808static const struct dib0090_pll dib0090_p1g_pll_table[] = {
1809#ifdef CONFIG_BAND_CBAND
1810 {57000, 0, 11, 48, 6},
1811 {70000, 1, 11, 48, 6},
1812 {86000, 0, 10, 32, 4},
1813 {105000, 1, 10, 32, 4},
1814 {115000, 0, 9, 24, 6},
1815 {140000, 1, 9, 24, 6},
1816 {170000, 0, 8, 16, 4},
1817#endif
1818#ifdef CONFIG_BAND_VHF
1819 {200000, 1, 8, 16, 4},
1820 {230000, 0, 7, 12, 6},
1821 {280000, 1, 7, 12, 6},
1822 {340000, 0, 6, 8, 4},
1823 {380000, 1, 6, 8, 4},
1824 {455000, 0, 5, 6, 6},
1825#endif
1826#ifdef CONFIG_BAND_UHF
1827 {580000, 1, 5, 6, 6},
1828 {680000, 0, 4, 4, 4},
1829 {860000, 1, 4, 4, 4},
1830#endif
1831#ifdef CONFIG_BAND_LBAND
1832 {1800000, 1, 2, 2, 4},
1833#endif
1834#ifdef CONFIG_BAND_SBAND
1835 {2900000, 0, 1, 1, 6},
1836#endif
1837};
1838
1839static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
1840#ifdef CONFIG_BAND_CBAND
1841 {184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
1842 {227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
1843 {380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
1844#endif
1845#ifdef CONFIG_BAND_UHF
1846 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1847 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1848 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1849 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1850 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1851 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1852#endif
1853#ifdef CONFIG_BAND_LBAND
1854 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1855 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1856 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1857#endif
1858#ifdef CONFIG_BAND_SBAND
1859 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1860 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1861#endif
1862};
1863
1864static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
1865#ifdef CONFIG_BAND_CBAND
1866 {300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1867 {380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1868 {570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1869 {858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1870#endif
1871};
1872
1873static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1874{
1875 int ret = 0;
1876 u16 lo4 = 0xe900;
1877
1878 s16 adc_target;
1879 u16 adc;
1880 s8 step_sign;
1881 u8 force_soft_search = 0;
1882
1883 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1884 force_soft_search = 1;
1885
1886 if (*tune_state == CT_TUNER_START) {
1887 dprintk("Start Captrim search : %s", (force_soft_search == 1) ? "FORCE SOFT SEARCH" : "AUTO");
1888 dib0090_write_reg(state, 0x10, 0x2B1);
1889 dib0090_write_reg(state, 0x1e, 0x0032);
1890
1891 if (!state->tuner_is_tuned) {
1892 /* prepare a complete captrim */
1893 if (!state->identity.p1g || force_soft_search)
1894 state->step = state->captrim = state->fcaptrim = 64;
1895
1896 state->current_rf = state->rf_request;
1897 } else { /* we are already tuned to this frequency - the configuration is correct */
1898 if (!state->identity.p1g || force_soft_search) {
1899 /* do a minimal captrim even if the frequency has not changed */
1900 state->step = 4;
1901 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
1902 }
1903 }
1904 state->adc_diff = 3000;
1905 *tune_state = CT_TUNER_STEP_0;
1906
1907 } else if (*tune_state == CT_TUNER_STEP_0) {
1908 if (state->identity.p1g && !force_soft_search) {
1909 u8 ratio = 31;
1910
1911 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
1912 dib0090_read_reg(state, 0x40);
1913 ret = 50;
1914 } else {
1915 state->step /= 2;
1916 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
1917
1918 if (state->identity.in_soc)
1919 ret = 25;
1920 }
1921 *tune_state = CT_TUNER_STEP_1;
1922
1923 } else if (*tune_state == CT_TUNER_STEP_1) {
1924 if (state->identity.p1g && !force_soft_search) {
1925 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
1926 dib0090_read_reg(state, 0x40);
1927
1928 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
1929 dprintk("***Final Captrim= 0x%x", state->fcaptrim);
1930 *tune_state = CT_TUNER_STEP_3;
1931
1932 } else {
1933 /* MERGE for all krosus before P1G */
1934 adc = dib0090_get_slow_adc_val(state);
1935 dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024);
1936
1937 if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */
1938 adc_target = 200;
1939 } else
1940 adc_target = 400;
1941
1942 if (adc >= adc_target) {
1943 adc -= adc_target;
1944 step_sign = -1;
1945 } else {
1946 adc = adc_target - adc;
1947 step_sign = 1;
1948 }
1949
1950 if (adc < state->adc_diff) {
1951 dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
1952 state->adc_diff = adc;
1953 state->fcaptrim = state->captrim;
1954 }
1955
1956 state->captrim += step_sign * state->step;
1957 if (state->step >= 1)
1958 *tune_state = CT_TUNER_STEP_0;
1959 else
1960 *tune_state = CT_TUNER_STEP_2;
1961
1962 ret = 25;
1963 }
1964 } else if (*tune_state == CT_TUNER_STEP_2) { /* this step is only used by krosus < P1G */
1965 /*write the final cptrim config */
1966 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
1967
1968 *tune_state = CT_TUNER_STEP_3;
1969
1970 } else if (*tune_state == CT_TUNER_STEP_3) {
1971 state->calibrate &= ~CAPTRIM_CAL;
1972 *tune_state = CT_TUNER_STEP_0;
1973 }
1974
1975 return ret;
1976}
1977
1978static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1979{
1980 int ret = 15;
1981 s16 val;
1982
1983 switch (*tune_state) {
1984 case CT_TUNER_START:
1985 state->wbdmux = dib0090_read_reg(state, 0x10);
1986 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));
1987
1988 state->bias = dib0090_read_reg(state, 0x13);
1989 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));
1990
1991 *tune_state = CT_TUNER_STEP_0;
1992 /* wait for the WBDMUX to switch and for the ADC to sample */
1993 break;
1994
1995 case CT_TUNER_STEP_0:
1996 state->adc_diff = dib0090_get_slow_adc_val(state);
1997 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));
1998 *tune_state = CT_TUNER_STEP_1;
1999 break;
2000
2001 case CT_TUNER_STEP_1:
2002 val = dib0090_get_slow_adc_val(state);
2003 state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;
2004
2005 dprintk("temperature: %d C", state->temperature - 30);
2006
2007 *tune_state = CT_TUNER_STEP_2;
2008 break;
2009
2010 case CT_TUNER_STEP_2:
2011 dib0090_write_reg(state, 0x13, state->bias);
2012 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
2013
2014 *tune_state = CT_TUNER_START;
2015 state->calibrate &= ~TEMP_CAL;
2016 if (state->config->analog_output == 0)
2017 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2018
2019 break;
2020
2021 default:
2022 ret = 0;
2023 break;
2024 }
2025 return ret;
2026}
2027
1183#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */ 2028#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
1184static int dib0090_tune(struct dvb_frontend *fe) 2029static int dib0090_tune(struct dvb_frontend *fe)
1185{ 2030{
@@ -1188,87 +2033,131 @@ static int dib0090_tune(struct dvb_frontend *fe)
1188 const struct dib0090_pll *pll = state->current_pll_table_index; 2033 const struct dib0090_pll *pll = state->current_pll_table_index;
1189 enum frontend_tune_state *tune_state = &state->tune_state; 2034 enum frontend_tune_state *tune_state = &state->tune_state;
1190 2035
1191 u32 rf; 2036 u16 lo5, lo6, Den, tmp;
1192 u16 lo4 = 0xe900, lo5, lo6, Den;
1193 u32 FBDiv, Rest, FREF, VCOF_kHz = 0; 2037 u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
1194 u16 tmp, adc;
1195 int8_t step_sign;
1196 int ret = 10; /* 1ms is the default delay most of the time */ 2038 int ret = 10; /* 1ms is the default delay most of the time */
1197 u8 c, i; 2039 u8 c, i;
1198 2040
1199 state->current_band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000); 2041 /************************* VCO ***************************/
1200 rf = fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
1201 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->freq_offset_khz_vhf);
1202 /* in any case we first need to do a reset if needed */
1203 if (state->reset & 0x1)
1204 return dib0090_dc_offset_calibration(state, tune_state);
1205 else if (state->reset & 0x2)
1206 return dib0090_wbd_calibration(state, tune_state);
1207
1208 /************************* VCO ***************************/
1209 /* Default values for FG */ 2042 /* Default values for FG */
1210 /* from these are needed : */ 2043 /* from these are needed : */
1211 /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */ 2044 /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */
1212 2045
1213#ifdef CONFIG_SYS_ISDBT 2046 /* in any case we first need to do a calibration if needed */
1214 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1) 2047 if (*tune_state == CT_TUNER_START) {
1215 rf += 850; 2048 /* deactivate DataTX before some calibrations */
1216#endif 2049 if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
2050 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
2051 else
2052 /* Activate DataTX in case a calibration has been done before */
2053 if (state->config->analog_output == 0)
2054 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2055 }
1217 2056
1218 if (state->current_rf != rf) { 2057 if (state->calibrate & DC_CAL)
1219 state->tuner_is_tuned = 0; 2058 return dib0090_dc_offset_calibration(state, tune_state);
2059 else if (state->calibrate & WBD_CAL) {
2060 if (state->current_rf == 0)
2061 state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
2062 return dib0090_wbd_calibration(state, tune_state);
2063 } else if (state->calibrate & TEMP_CAL)
2064 return dib0090_get_temperature(state, tune_state);
2065 else if (state->calibrate & CAPTRIM_CAL)
2066 return dib0090_captrim_search(state, tune_state);
1220 2067
1221 tune = dib0090_tuning_table; 2068 if (*tune_state == CT_TUNER_START) {
2069 /* if soc and AGC pwm control, disengage mux to be able to R/W access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, otherwise, SOC SERPAR error when accessing to 0x01 */
2070 if (state->config->use_pwm_agc && state->identity.in_soc) {
2071 tmp = dib0090_read_reg(state, 0x39);
2072 if ((tmp >> 10) & 0x1)
2073 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));
2074 }
1222 2075
1223 tmp = (state->revision >> 5) & 0x7; 2076 state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
1224 if (tmp == 0x4 || tmp == 0x7) { 2077 state->rf_request =
1225 /* CBAND tuner version for VHF */ 2078 state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
1226 if (state->current_band == BAND_FM || state->current_band == BAND_VHF) { 2079 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->
1227 /* Force CBAND */ 2080 freq_offset_khz_vhf);
1228 state->current_band = BAND_CBAND; 2081
1229 tune = dib0090_tuning_table_fm_vhf_on_cband; 2082 /* in ISDB-T 1seg we shift tuning frequency */
2083 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1
2084 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {
2085 const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;
2086 u8 found_offset = 0;
2087 u32 margin_khz = 100;
2088
2089 if (LUT_offset != NULL) {
2090 while (LUT_offset->RF_freq != 0xffff) {
2091 if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))
2092 && (state->rf_request < (LUT_offset->RF_freq + margin_khz)))
2093 && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {
2094 state->rf_request += LUT_offset->offset_khz;
2095 found_offset = 1;
2096 break;
2097 }
2098 LUT_offset++;
2099 }
1230 } 2100 }
2101
2102 if (found_offset == 0)
2103 state->rf_request += 400;
1231 } 2104 }
2105 if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) {
2106 state->tuner_is_tuned = 0;
2107 state->current_rf = 0;
2108 state->current_standard = 0;
1232 2109
1233 pll = dib0090_pll_table; 2110 tune = dib0090_tuning_table;
1234 /* Look for the interval */ 2111 if (state->identity.p1g)
1235 while (rf > tune->max_freq) 2112 tune = dib0090_p1g_tuning_table;
1236 tune++;
1237 while (rf > pll->max_freq)
1238 pll++;
1239 state->current_tune_table_index = tune;
1240 state->current_pll_table_index = pll;
1241 }
1242 2113
1243 if (*tune_state == CT_TUNER_START) { 2114 tmp = (state->identity.version >> 5) & 0x7;
1244 2115
1245 if (state->tuner_is_tuned == 0) 2116 if (state->identity.in_soc) {
1246 state->current_rf = 0; 2117 if (state->config->force_cband_input) { /* Use the CBAND input for all band */
2118 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
2119 || state->current_band & BAND_UHF) {
2120 state->current_band = BAND_CBAND;
2121 tune = dib0090_tuning_table_cband_7090;
2122 }
2123 } else { /* Use the CBAND input for all band under UHF */
2124 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
2125 state->current_band = BAND_CBAND;
2126 tune = dib0090_tuning_table_cband_7090;
2127 }
2128 }
2129 } else
2130 if (tmp == 0x4 || tmp == 0x7) {
2131 /* CBAND tuner version for VHF */
2132 if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) {
2133 state->current_band = BAND_CBAND; /* Force CBAND */
2134
2135 tune = dib0090_tuning_table_fm_vhf_on_cband;
2136 if (state->identity.p1g)
2137 tune = dib0090_p1g_tuning_table_fm_vhf_on_cband;
2138 }
2139 }
1247 2140
1248 if (state->current_rf != rf) { 2141 pll = dib0090_pll_table;
2142 if (state->identity.p1g)
2143 pll = dib0090_p1g_pll_table;
1249 2144
1250 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); 2145 /* Look for the interval */
2146 while (state->rf_request > tune->max_freq)
2147 tune++;
2148 while (state->rf_request > pll->max_freq)
2149 pll++;
1251 2150
1252 /* external loop filter, otherwise: 2151 state->current_tune_table_index = tune;
1253 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4; 2152 state->current_pll_table_index = pll;
1254 * lo6 = 0x0e34 */
1255 if (pll->vco_band)
1256 lo5 = 0x049e;
1257 else if (state->config->analog_output)
1258 lo5 = 0x041d;
1259 else
1260 lo5 = 0x041c;
1261
1262 lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
1263 2153
1264 if (!state->config->io.pll_int_loop_filt) 2154 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
1265 lo6 = 0xff28;
1266 else
1267 lo6 = (state->config->io.pll_int_loop_filt << 3);
1268 2155
1269 VCOF_kHz = (pll->hfdiv * rf) * 2; 2156 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
1270 2157
1271 FREF = state->config->io.clock_khz; 2158 FREF = state->config->io.clock_khz;
2159 if (state->config->fref_clock_ratio != 0)
2160 FREF /= state->config->fref_clock_ratio;
1272 2161
1273 FBDiv = (VCOF_kHz / pll->topresc / FREF); 2162 FBDiv = (VCOF_kHz / pll->topresc / FREF);
1274 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; 2163 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
@@ -1283,144 +2172,132 @@ static int dib0090_tune(struct dvb_frontend *fe)
1283 } else if (Rest > (FREF - 2 * LPF)) 2172 } else if (Rest > (FREF - 2 * LPF))
1284 Rest = FREF - 2 * LPF; 2173 Rest = FREF - 2 * LPF;
1285 Rest = (Rest * 6528) / (FREF / 10); 2174 Rest = (Rest * 6528) / (FREF / 10);
2175 state->rest = Rest;
1286 2176
1287 Den = 1; 2177 /* external loop filter, otherwise:
2178 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
2179 * lo6 = 0x0e34 */
2180
2181 if (Rest == 0) {
2182 if (pll->vco_band)
2183 lo5 = 0x049f;
2184 else
2185 lo5 = 0x041f;
2186 } else {
2187 if (pll->vco_band)
2188 lo5 = 0x049e;
2189 else if (state->config->analog_output)
2190 lo5 = 0x041d;
2191 else
2192 lo5 = 0x041c;
2193 }
2194
2195 if (state->identity.p1g) { /* Bias is done automatically in P1G */
2196 if (state->identity.in_soc) {
2197 if (state->identity.version == SOC_8090_P1G_11R1)
2198 lo5 = 0x46f;
2199 else
2200 lo5 = 0x42f;
2201 } else
2202 lo5 = 0x42c;
2203 }
2204
2205 lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
1288 2206
1289 dprintk(" ***** ******* Rest value = %d", Rest); 2207 if (!state->config->io.pll_int_loop_filt) {
2208 if (state->identity.in_soc)
2209 lo6 = 0xff98;
2210 else if (state->identity.p1g || (Rest == 0))
2211 lo6 = 0xfff8;
2212 else
2213 lo6 = 0xff28;
2214 } else
2215 lo6 = (state->config->io.pll_int_loop_filt << 3);
2216
2217 Den = 1;
1290 2218
1291 if (Rest > 0) { 2219 if (Rest > 0) {
1292 if (state->config->analog_output) 2220 if (state->config->analog_output)
1293 lo6 |= (1 << 2) | 2; 2221 lo6 |= (1 << 2) | 2;
1294 else 2222 else {
1295 lo6 |= (1 << 2) | 1; 2223 if (state->identity.in_soc)
2224 lo6 |= (1 << 2) | 2;
2225 else
2226 lo6 |= (1 << 2) | 2;
2227 }
1296 Den = 255; 2228 Den = 255;
1297 } 2229 }
1298#ifdef CONFIG_BAND_SBAND
1299 if (state->current_band == BAND_SBAND)
1300 lo6 &= 0xfffb;
1301#endif
1302
1303 dib0090_write_reg(state, 0x15, (u16) FBDiv); 2230 dib0090_write_reg(state, 0x15, (u16) FBDiv);
1304 2231 if (state->config->fref_clock_ratio != 0)
1305 dib0090_write_reg(state, 0x16, (Den << 8) | 1); 2232 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
1306 2233 else
2234 dib0090_write_reg(state, 0x16, (Den << 8) | 1);
1307 dib0090_write_reg(state, 0x17, (u16) Rest); 2235 dib0090_write_reg(state, 0x17, (u16) Rest);
1308
1309 dib0090_write_reg(state, 0x19, lo5); 2236 dib0090_write_reg(state, 0x19, lo5);
1310
1311 dib0090_write_reg(state, 0x1c, lo6); 2237 dib0090_write_reg(state, 0x1c, lo6);
1312 2238
1313 lo6 = tune->tuner_enable; 2239 lo6 = tune->tuner_enable;
1314 if (state->config->analog_output) 2240 if (state->config->analog_output)
1315 lo6 = (lo6 & 0xff9f) | 0x2; 2241 lo6 = (lo6 & 0xff9f) | 0x2;
1316 2242
1317 dib0090_write_reg(state, 0x24, lo6 | EN_LO 2243 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
1318#ifdef CONFIG_DIB0090_USE_PWM_AGC
1319 | state->config->use_pwm_agc * EN_CRYSTAL
1320#endif
1321 );
1322
1323 state->current_rf = rf;
1324
1325 /* prepare a complete captrim */
1326 state->step = state->captrim = state->fcaptrim = 64;
1327
1328 } else { /* we are already tuned to this frequency - the configuration is correct */
1329 2244
1330 /* do a minimal captrim even if the frequency has not changed */
1331 state->step = 4;
1332 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
1333 } 2245 }
1334 state->adc_diff = 3000;
1335
1336 dib0090_write_reg(state, 0x10, 0x2B1);
1337 2246
1338 dib0090_write_reg(state, 0x1e, 0x0032); 2247 state->current_rf = state->rf_request;
2248 state->current_standard = state->fe->dtv_property_cache.delivery_system;
1339 2249
1340 ret = 20; 2250 ret = 20;
1341 *tune_state = CT_TUNER_STEP_1; 2251 state->calibrate = CAPTRIM_CAL; /* captrim serach now */
1342 } else if (*tune_state == CT_TUNER_STEP_0) { 2252 }
1343 /* nothing */
1344 } else if (*tune_state == CT_TUNER_STEP_1) {
1345 state->step /= 2;
1346 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
1347 *tune_state = CT_TUNER_STEP_2;
1348 } else if (*tune_state == CT_TUNER_STEP_2) {
1349 2253
1350 adc = dib0090_read_reg(state, 0x1d); 2254 else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
1351 dprintk("FE %d CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) fe->id, (u32) state->captrim, (u32) adc, 2255 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1352 (u32) (adc) * (u32) 1800 / (u32) 1024);
1353 2256
1354 if (adc >= 400) { 2257 while (state->current_rf / 1000 > wbd->max_freq)
1355 adc -= 400; 2258 wbd++;
1356 step_sign = -1;
1357 } else {
1358 adc = 400 - adc;
1359 step_sign = 1;
1360 }
1361 2259
1362 if (adc < state->adc_diff) { 2260 dib0090_write_reg(state, 0x1e, 0x07ff);
1363 dprintk("FE %d CAPTRIM=%d is closer to target (%d/%d)", (u32) fe->id, (u32) state->captrim, (u32) adc, (u32) state->adc_diff); 2261 dprintk("Final Captrim: %d", (u32) state->fcaptrim);
1364 state->adc_diff = adc; 2262 dprintk("HFDIV code: %d", (u32) pll->hfdiv_code);
1365 state->fcaptrim = state->captrim; 2263 dprintk("VCO = %d", (u32) pll->vco_band);
1366 2264 dprintk("VCOF in kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
1367 } 2265 dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz);
2266 dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
2267 dprintk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
2268 (u32) dib0090_read_reg(state, 0x1c) & 0x3);
1368 2269
1369 state->captrim += step_sign * state->step; 2270#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
1370 if (state->step >= 1) 2271 c = 4;
1371 *tune_state = CT_TUNER_STEP_1; 2272 i = 3;
1372 else
1373 *tune_state = CT_TUNER_STEP_3;
1374 2273
1375 ret = 15; 2274 if (wbd->wbd_gain != 0)
1376 } else if (*tune_state == CT_TUNER_STEP_3) { 2275 c = wbd->wbd_gain;
1377 /*write the final cptrim config */
1378 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
1379 2276
1380#ifdef CONFIG_TUNER_DIB0090_CAPTRIM_MEMORY 2277 state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
1381 state->memory[state->memory_index].cap = state->fcaptrim; 2278 dib0090_write_reg(state, 0x10, state->wbdmux);
1382#endif
1383 2279
1384 *tune_state = CT_TUNER_STEP_4; 2280 if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {
1385 } else if (*tune_state == CT_TUNER_STEP_4) { 2281 dprintk("P1G : The cable band is selected and lna_tune = %d", tune->lna_tune);
1386 dib0090_write_reg(state, 0x1e, 0x07ff); 2282 dib0090_write_reg(state, 0x09, tune->lna_bias);
1387 2283 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
1388 dprintk("FE %d Final Captrim: %d", (u32) fe->id, (u32) state->fcaptrim); 2284 } else
1389 dprintk("FE %d HFDIV code: %d", (u32) fe->id, (u32) pll->hfdiv_code); 2285 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
1390 dprintk("FE %d VCO = %d", (u32) fe->id, (u32) pll->vco_band);
1391 dprintk("FE %d VCOF in kHz: %d ((%d*%d) << 1))", (u32) fe->id, (u32) ((pll->hfdiv * rf) * 2), (u32) pll->hfdiv, (u32) rf);
1392 dprintk("FE %d REFDIV: %d, FREF: %d", (u32) fe->id, (u32) 1, (u32) state->config->io.clock_khz);
1393 dprintk("FE %d FBDIV: %d, Rest: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
1394 dprintk("FE %d Num: %d, Den: %d, SD: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x17),
1395 (u32) (dib0090_read_reg(state, 0x16) >> 8), (u32) dib0090_read_reg(state, 0x1c) & 0x3);
1396 2286
1397 c = 4;
1398 i = 3;
1399#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
1400 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) {
1401 c = 2;
1402 i = 2;
1403 }
1404#endif
1405 dib0090_write_reg(state, 0x10, (c << 13) | (i << 11) | (WBD
1406#ifdef CONFIG_DIB0090_USE_PWM_AGC
1407 | (state->config->use_pwm_agc << 1)
1408#endif
1409 ));
1410 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | (tune->lna_bias << 0));
1411 dib0090_write_reg(state, 0x0c, tune->v2i); 2287 dib0090_write_reg(state, 0x0c, tune->v2i);
1412 dib0090_write_reg(state, 0x0d, tune->mix); 2288 dib0090_write_reg(state, 0x0d, tune->mix);
1413 dib0090_write_reg(state, 0x0e, tune->load); 2289 dib0090_write_reg(state, 0x0e, tune->load);
2290 *tune_state = CT_TUNER_STEP_1;
1414 2291
1415 *tune_state = CT_TUNER_STEP_5; 2292 } else if (*tune_state == CT_TUNER_STEP_1) {
1416 } else if (*tune_state == CT_TUNER_STEP_5) {
1417
1418 /* initialize the lt gain register */ 2293 /* initialize the lt gain register */
1419 state->rf_lt_def = 0x7c00; 2294 state->rf_lt_def = 0x7c00;
1420 dib0090_write_reg(state, 0x0f, state->rf_lt_def);
1421 2295
1422 dib0090_set_bandwidth(state); 2296 dib0090_set_bandwidth(state);
1423 state->tuner_is_tuned = 1; 2297 state->tuner_is_tuned = 1;
2298
2299 state->calibrate |= WBD_CAL;
2300 state->calibrate |= TEMP_CAL;
1424 *tune_state = CT_TUNER_STOP; 2301 *tune_state = CT_TUNER_STOP;
1425 } else 2302 } else
1426 ret = FE_CALLBACK_TIME_NEVER; 2303 ret = FE_CALLBACK_TIME_NEVER;
@@ -1440,6 +2317,7 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
1440 2317
1441 return state->tune_state; 2318 return state->tune_state;
1442} 2319}
2320
1443EXPORT_SYMBOL(dib0090_get_tune_state); 2321EXPORT_SYMBOL(dib0090_get_tune_state);
1444 2322
1445int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) 2323int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
@@ -1449,6 +2327,7 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
1449 state->tune_state = tune_state; 2327 state->tune_state = tune_state;
1450 return 0; 2328 return 0;
1451} 2329}
2330
1452EXPORT_SYMBOL(dib0090_set_tune_state); 2331EXPORT_SYMBOL(dib0090_set_tune_state);
1453 2332
1454static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency) 2333static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
@@ -1462,7 +2341,7 @@ static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
1462static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 2341static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
1463{ 2342{
1464 struct dib0090_state *state = fe->tuner_priv; 2343 struct dib0090_state *state = fe->tuner_priv;
1465 uint32_t ret; 2344 u32 ret;
1466 2345
1467 state->tune_state = CT_TUNER_START; 2346 state->tune_state = CT_TUNER_START;
1468 2347
@@ -1492,6 +2371,29 @@ static const struct dvb_tuner_ops dib0090_ops = {
1492 .get_frequency = dib0090_get_frequency, 2371 .get_frequency = dib0090_get_frequency,
1493}; 2372};
1494 2373
2374static const struct dvb_tuner_ops dib0090_fw_ops = {
2375 .info = {
2376 .name = "DiBcom DiB0090",
2377 .frequency_min = 45000000,
2378 .frequency_max = 860000000,
2379 .frequency_step = 1000,
2380 },
2381 .release = dib0090_release,
2382
2383 .init = NULL,
2384 .sleep = NULL,
2385 .set_params = NULL,
2386 .get_frequency = NULL,
2387};
2388
2389static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
2390 {470, 0, 250, 0, 100, 4},
2391 {860, 51, 866, 21, 375, 4},
2392 {1700, 0, 800, 0, 850, 4},
2393 {2900, 0, 250, 0, 100, 6},
2394 {0xFFFF, 0, 0, 0, 0, 0},
2395};
2396
1495struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config) 2397struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
1496{ 2398{
1497 struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL); 2399 struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
@@ -1503,6 +2405,11 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
1503 st->fe = fe; 2405 st->fe = fe;
1504 fe->tuner_priv = st; 2406 fe->tuner_priv = st;
1505 2407
2408 if (config->wbd == NULL)
2409 st->current_wbd_table = dib0090_wbd_table_default;
2410 else
2411 st->current_wbd_table = config->wbd;
2412
1506 if (dib0090_reset(fe) != 0) 2413 if (dib0090_reset(fe) != 0)
1507 goto free_mem; 2414 goto free_mem;
1508 2415
@@ -1515,8 +2422,34 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
1515 fe->tuner_priv = NULL; 2422 fe->tuner_priv = NULL;
1516 return NULL; 2423 return NULL;
1517} 2424}
2425
1518EXPORT_SYMBOL(dib0090_register); 2426EXPORT_SYMBOL(dib0090_register);
1519 2427
2428struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
2429{
2430 struct dib0090_fw_state *st = kzalloc(sizeof(struct dib0090_fw_state), GFP_KERNEL);
2431 if (st == NULL)
2432 return NULL;
2433
2434 st->config = config;
2435 st->i2c = i2c;
2436 st->fe = fe;
2437 fe->tuner_priv = st;
2438
2439 if (dib0090_fw_reset_digital(fe, st->config) != 0)
2440 goto free_mem;
2441
2442 dprintk("DiB0090 FW: successfully identified");
2443 memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
2444
2445 return fe;
2446free_mem:
2447 kfree(st);
2448 fe->tuner_priv = NULL;
2449 return NULL;
2450}
2451EXPORT_SYMBOL(dib0090_fw_register);
2452
1520MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); 2453MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
1521MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>"); 2454MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>");
1522MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner"); 2455MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
diff --git a/drivers/media/dvb/frontends/dib0090.h b/drivers/media/dvb/frontends/dib0090.h
index aa7711e88776..13d85244ec16 100644
--- a/drivers/media/dvb/frontends/dib0090.h
+++ b/drivers/media/dvb/frontends/dib0090.h
@@ -27,6 +27,21 @@ struct dib0090_io_config {
27 u16 pll_int_loop_filt; 27 u16 pll_int_loop_filt;
28}; 28};
29 29
30struct dib0090_wbd_slope {
31 u16 max_freq; /* for every frequency less than or equal to that field: this information is correct */
32 u16 slope_cold;
33 u16 offset_cold;
34 u16 slope_hot;
35 u16 offset_hot;
36 u8 wbd_gain;
37};
38
39struct dib0090_low_if_offset_table {
40 int std;
41 u32 RF_freq;
42 s32 offset_khz;
43};
44
30struct dib0090_config { 45struct dib0090_config {
31 struct dib0090_io_config io; 46 struct dib0090_io_config io;
32 int (*reset) (struct dvb_frontend *, int); 47 int (*reset) (struct dvb_frontend *, int);
@@ -47,10 +62,20 @@ struct dib0090_config {
47 u16 wbd_cband_offset; 62 u16 wbd_cband_offset;
48 u8 use_pwm_agc; 63 u8 use_pwm_agc;
49 u8 clkoutdrive; 64 u8 clkoutdrive;
65
66 u8 ls_cfg_pad_drv;
67 u8 data_tx_drv;
68
69 u8 in_soc;
70 const struct dib0090_low_if_offset_table *low_if;
71 u8 fref_clock_ratio;
72 u16 force_cband_input;
73 struct dib0090_wbd_slope *wbd;
50}; 74};
51 75
52#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE)) 76#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE))
53extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config); 77extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
78extern struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
54extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast); 79extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast);
55extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe); 80extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe);
56extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner); 81extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner);
@@ -65,6 +90,12 @@ static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, str
65 return NULL; 90 return NULL;
66} 91}
67 92
93static inline struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0090_config *config)
94{
95 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
96 return NULL;
97}
98
68static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast) 99static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
69{ 100{
70 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 101 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index 6aa02cb80733..900af60b9d36 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -26,24 +26,29 @@ MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (defau
26 26
27#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0) 27#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0)
28 28
29struct i2c_device {
30 struct i2c_adapter *i2c_adap;
31 u8 i2c_addr;
32};
33
29struct dib7000p_state { 34struct dib7000p_state {
30 struct dvb_frontend demod; 35 struct dvb_frontend demod;
31 struct dib7000p_config cfg; 36 struct dib7000p_config cfg;
32 37
33 u8 i2c_addr; 38 u8 i2c_addr;
34 struct i2c_adapter *i2c_adap; 39 struct i2c_adapter *i2c_adap;
35 40
36 struct dibx000_i2c_master i2c_master; 41 struct dibx000_i2c_master i2c_master;
37 42
38 u16 wbd_ref; 43 u16 wbd_ref;
39 44
40 u8 current_band; 45 u8 current_band;
41 u32 current_bandwidth; 46 u32 current_bandwidth;
42 struct dibx000_agc_config *current_agc; 47 struct dibx000_agc_config *current_agc;
43 u32 timf; 48 u32 timf;
44 49
45 u8 div_force_off : 1; 50 u8 div_force_off:1;
46 u8 div_state : 1; 51 u8 div_state:1;
47 u16 div_sync_wait; 52 u16 div_sync_wait;
48 53
49 u8 agc_state; 54 u8 agc_state;
@@ -51,7 +56,13 @@ struct dib7000p_state {
51 u16 gpio_dir; 56 u16 gpio_dir;
52 u16 gpio_val; 57 u16 gpio_val;
53 58
54 u8 sfn_workaround_active :1; 59 u8 sfn_workaround_active:1;
60
61#define SOC7090 0x7090
62 u16 version;
63
64 u16 tuner_enable;
65 struct i2c_adapter dib7090_tuner_adap;
55}; 66};
56 67
57enum dib7000p_power_mode { 68enum dib7000p_power_mode {
@@ -60,17 +71,20 @@ enum dib7000p_power_mode {
60 DIB7000P_POWER_INTERFACE_ONLY, 71 DIB7000P_POWER_INTERFACE_ONLY,
61}; 72};
62 73
74static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
75static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
76
63static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg) 77static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
64{ 78{
65 u8 wb[2] = { reg >> 8, reg & 0xff }; 79 u8 wb[2] = { reg >> 8, reg & 0xff };
66 u8 rb[2]; 80 u8 rb[2];
67 struct i2c_msg msg[2] = { 81 struct i2c_msg msg[2] = {
68 { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 }, 82 {.addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
69 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 }, 83 {.addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
70 }; 84 };
71 85
72 if (i2c_transfer(state->i2c_adap, msg, 2) != 2) 86 if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
73 dprintk("i2c read error on %d",reg); 87 dprintk("i2c read error on %d", reg);
74 88
75 return (rb[0] << 8) | rb[1]; 89 return (rb[0] << 8) | rb[1];
76} 90}
@@ -86,7 +100,8 @@ static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
86 }; 100 };
87 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; 101 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
88} 102}
89static void dib7000p_write_tab(struct dib7000p_state *state, u16 *buf) 103
104static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
90{ 105{
91 u16 l = 0, r, *n; 106 u16 l = 0, r, *n;
92 n = buf; 107 n = buf;
@@ -104,54 +119,54 @@ static void dib7000p_write_tab(struct dib7000p_state *state, u16 *buf)
104 119
105static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode) 120static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
106{ 121{
107 int ret = 0; 122 int ret = 0;
108 u16 outreg, fifo_threshold, smo_mode; 123 u16 outreg, fifo_threshold, smo_mode;
109 124
110 outreg = 0; 125 outreg = 0;
111 fifo_threshold = 1792; 126 fifo_threshold = 1792;
112 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1); 127 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
113 128
114 dprintk( "setting output mode for demod %p to %d", 129 dprintk("setting output mode for demod %p to %d", &state->demod, mode);
115 &state->demod, mode);
116 130
117 switch (mode) { 131 switch (mode) {
118 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock 132 case OUTMODE_MPEG2_PAR_GATED_CLK:
119 outreg = (1 << 10); /* 0x0400 */ 133 outreg = (1 << 10); /* 0x0400 */
120 break; 134 break;
121 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock 135 case OUTMODE_MPEG2_PAR_CONT_CLK:
122 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ 136 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
123 break; 137 break;
124 case OUTMODE_MPEG2_SERIAL: // STBs with serial input 138 case OUTMODE_MPEG2_SERIAL:
125 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */ 139 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
126 break; 140 break;
127 case OUTMODE_DIVERSITY: 141 case OUTMODE_DIVERSITY:
128 if (state->cfg.hostbus_diversity) 142 if (state->cfg.hostbus_diversity)
129 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ 143 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
130 else 144 else
131 outreg = (1 << 11); 145 outreg = (1 << 11);
132 break; 146 break;
133 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding 147 case OUTMODE_MPEG2_FIFO:
134 smo_mode |= (3 << 1); 148 smo_mode |= (3 << 1);
135 fifo_threshold = 512; 149 fifo_threshold = 512;
136 outreg = (1 << 10) | (5 << 6); 150 outreg = (1 << 10) | (5 << 6);
137 break; 151 break;
138 case OUTMODE_ANALOG_ADC: 152 case OUTMODE_ANALOG_ADC:
139 outreg = (1 << 10) | (3 << 6); 153 outreg = (1 << 10) | (3 << 6);
140 break; 154 break;
141 case OUTMODE_HIGH_Z: // disable 155 case OUTMODE_HIGH_Z:
142 outreg = 0; 156 outreg = 0;
143 break; 157 break;
144 default: 158 default:
145 dprintk( "Unhandled output_mode passed to be set for demod %p",&state->demod); 159 dprintk("Unhandled output_mode passed to be set for demod %p", &state->demod);
146 break; 160 break;
147 } 161 }
148 162
149 if (state->cfg.output_mpeg2_in_188_bytes) 163 if (state->cfg.output_mpeg2_in_188_bytes)
150 smo_mode |= (1 << 5) ; 164 smo_mode |= (1 << 5);
151 165
152 ret |= dib7000p_write_word(state, 235, smo_mode); 166 ret |= dib7000p_write_word(state, 235, smo_mode);
153 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */ 167 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
154 ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */ 168 if (state->version != SOC7090)
169 ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
155 170
156 return ret; 171 return ret;
157} 172}
@@ -161,13 +176,13 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
161 struct dib7000p_state *state = demod->demodulator_priv; 176 struct dib7000p_state *state = demod->demodulator_priv;
162 177
163 if (state->div_force_off) { 178 if (state->div_force_off) {
164 dprintk( "diversity combination deactivated - forced by COFDM parameters"); 179 dprintk("diversity combination deactivated - forced by COFDM parameters");
165 onoff = 0; 180 onoff = 0;
166 dib7000p_write_word(state, 207, 0); 181 dib7000p_write_word(state, 207, 0);
167 } else 182 } else
168 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0)); 183 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
169 184
170 state->div_state = (u8)onoff; 185 state->div_state = (u8) onoff;
171 186
172 if (onoff) { 187 if (onoff) {
173 dib7000p_write_word(state, 204, 6); 188 dib7000p_write_word(state, 204, 6);
@@ -184,37 +199,48 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
184static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode) 199static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
185{ 200{
186 /* by default everything is powered off */ 201 /* by default everything is powered off */
187 u16 reg_774 = 0xffff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, 202 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
188 reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
189 203
190 /* now, depending on the requested mode, we power on */ 204 /* now, depending on the requested mode, we power on */
191 switch (mode) { 205 switch (mode) {
192 /* power up everything in the demod */ 206 /* power up everything in the demod */
193 case DIB7000P_POWER_ALL: 207 case DIB7000P_POWER_ALL:
194 reg_774 = 0x0000; reg_775 = 0x0000; reg_776 = 0x0; reg_899 = 0x0; reg_1280 &= 0x01ff; 208 reg_774 = 0x0000;
195 break; 209 reg_775 = 0x0000;
196 210 reg_776 = 0x0;
197 case DIB7000P_POWER_ANALOG_ADC: 211 reg_899 = 0x0;
198 /* dem, cfg, iqc, sad, agc */ 212 if (state->version == SOC7090)
199 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9)); 213 reg_1280 &= 0x001f;
200 /* nud */ 214 else
201 reg_776 &= ~((1 << 0)); 215 reg_1280 &= 0x01ff;
202 /* Dout */ 216 break;
217
218 case DIB7000P_POWER_ANALOG_ADC:
219 /* dem, cfg, iqc, sad, agc */
220 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
221 /* nud */
222 reg_776 &= ~((1 << 0));
223 /* Dout */
224 if (state->version != SOC7090)
203 reg_1280 &= ~((1 << 11)); 225 reg_1280 &= ~((1 << 11));
204 /* fall through wanted to enable the interfaces */ 226 reg_1280 &= ~(1 << 6);
227 /* fall through wanted to enable the interfaces */
205 228
206 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */ 229 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
207 case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */ 230 case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */
231 if (state->version == SOC7090)
232 reg_1280 &= ~((1 << 7) | (1 << 5));
233 else
208 reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10)); 234 reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
209 break; 235 break;
210 236
211/* TODO following stuff is just converted from the dib7000-driver - check when is used what */ 237/* TODO following stuff is just converted from the dib7000-driver - check when is used what */
212 } 238 }
213 239
214 dib7000p_write_word(state, 774, reg_774); 240 dib7000p_write_word(state, 774, reg_774);
215 dib7000p_write_word(state, 775, reg_775); 241 dib7000p_write_word(state, 775, reg_775);
216 dib7000p_write_word(state, 776, reg_776); 242 dib7000p_write_word(state, 776, reg_776);
217 dib7000p_write_word(state, 899, reg_899); 243 dib7000p_write_word(state, 899, reg_899);
218 dib7000p_write_word(state, 1280, reg_1280); 244 dib7000p_write_word(state, 1280, reg_1280);
219 245
220 return 0; 246 return 0;
@@ -222,40 +248,57 @@ static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_p
222 248
223static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no) 249static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
224{ 250{
225 u16 reg_908 = dib7000p_read_word(state, 908), 251 u16 reg_908 = dib7000p_read_word(state, 908), reg_909 = dib7000p_read_word(state, 909);
226 reg_909 = dib7000p_read_word(state, 909); 252 u16 reg;
227 253
228 switch (no) { 254 switch (no) {
229 case DIBX000_SLOW_ADC_ON: 255 case DIBX000_SLOW_ADC_ON:
256 if (state->version == SOC7090) {
257 reg = dib7000p_read_word(state, 1925);
258
259 dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */
260
261 reg = dib7000p_read_word(state, 1925); /* read acces to make it works... strange ... */
262 msleep(200);
263 dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */
264
265 reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
266 dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
267 } else {
230 reg_909 |= (1 << 1) | (1 << 0); 268 reg_909 |= (1 << 1) | (1 << 0);
231 dib7000p_write_word(state, 909, reg_909); 269 dib7000p_write_word(state, 909, reg_909);
232 reg_909 &= ~(1 << 1); 270 reg_909 &= ~(1 << 1);
233 break; 271 }
272 break;
234 273
235 case DIBX000_SLOW_ADC_OFF: 274 case DIBX000_SLOW_ADC_OFF:
236 reg_909 |= (1 << 1) | (1 << 0); 275 if (state->version == SOC7090) {
237 break; 276 reg = dib7000p_read_word(state, 1925);
277 dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
278 } else
279 reg_909 |= (1 << 1) | (1 << 0);
280 break;
238 281
239 case DIBX000_ADC_ON: 282 case DIBX000_ADC_ON:
240 reg_908 &= 0x0fff; 283 reg_908 &= 0x0fff;
241 reg_909 &= 0x0003; 284 reg_909 &= 0x0003;
242 break; 285 break;
243 286
244 case DIBX000_ADC_OFF: // leave the VBG voltage on 287 case DIBX000_ADC_OFF:
245 reg_908 |= (1 << 14) | (1 << 13) | (1 << 12); 288 reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
246 reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2); 289 reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
247 break; 290 break;
248 291
249 case DIBX000_VBG_ENABLE: 292 case DIBX000_VBG_ENABLE:
250 reg_908 &= ~(1 << 15); 293 reg_908 &= ~(1 << 15);
251 break; 294 break;
252 295
253 case DIBX000_VBG_DISABLE: 296 case DIBX000_VBG_DISABLE:
254 reg_908 |= (1 << 15); 297 reg_908 |= (1 << 15);
255 break; 298 break;
256 299
257 default: 300 default:
258 break; 301 break;
259 } 302 }
260 303
261// dprintk( "908: %x, 909: %x\n", reg_908, reg_909); 304// dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
@@ -275,17 +318,17 @@ static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
275 state->current_bandwidth = bw; 318 state->current_bandwidth = bw;
276 319
277 if (state->timf == 0) { 320 if (state->timf == 0) {
278 dprintk( "using default timf"); 321 dprintk("using default timf");
279 timf = state->cfg.bw->timf; 322 timf = state->cfg.bw->timf;
280 } else { 323 } else {
281 dprintk( "using updated timf"); 324 dprintk("using updated timf");
282 timf = state->timf; 325 timf = state->timf;
283 } 326 }
284 327
285 timf = timf * (bw / 50) / 160; 328 timf = timf * (bw / 50) / 160;
286 329
287 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); 330 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
288 dib7000p_write_word(state, 24, (u16) ((timf ) & 0xffff)); 331 dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
289 332
290 return 0; 333 return 0;
291} 334}
@@ -293,9 +336,12 @@ static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
293static int dib7000p_sad_calib(struct dib7000p_state *state) 336static int dib7000p_sad_calib(struct dib7000p_state *state)
294{ 337{
295/* internal */ 338/* internal */
296// dib7000p_write_word(state, 72, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth
297 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0)); 339 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
298 dib7000p_write_word(state, 74, 776); // 0.625*3.3 / 4096 340
341 if (state->version == SOC7090)
342 dib7000p_write_word(state, 74, 2048);
343 else
344 dib7000p_write_word(state, 74, 776);
299 345
300 /* do the calibration */ 346 /* do the calibration */
301 dib7000p_write_word(state, 73, (1 << 0)); 347 dib7000p_write_word(state, 73, (1 << 0));
@@ -314,37 +360,91 @@ int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
314 state->wbd_ref = value; 360 state->wbd_ref = value;
315 return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value); 361 return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
316} 362}
317
318EXPORT_SYMBOL(dib7000p_set_wbd_ref); 363EXPORT_SYMBOL(dib7000p_set_wbd_ref);
364
319static void dib7000p_reset_pll(struct dib7000p_state *state) 365static void dib7000p_reset_pll(struct dib7000p_state *state)
320{ 366{
321 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; 367 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
322 u16 clk_cfg0; 368 u16 clk_cfg0;
323 369
324 /* force PLL bypass */ 370 if (state->version == SOC7090) {
325 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) | 371 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
326 (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | 372
327 (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0); 373 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
374 ;
328 375
329 dib7000p_write_word(state, 900, clk_cfg0); 376 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
377 } else {
378 /* force PLL bypass */
379 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
380 (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
381
382 dib7000p_write_word(state, 900, clk_cfg0);
330 383
331 /* P_pll_cfg */ 384 /* P_pll_cfg */
332 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset); 385 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
333 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff); 386 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
334 dib7000p_write_word(state, 900, clk_cfg0); 387 dib7000p_write_word(state, 900, clk_cfg0);
388 }
335 389
336 dib7000p_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); 390 dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
337 dib7000p_write_word(state, 19, (u16) ( (bw->internal*1000 ) & 0xffff)); 391 dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
338 dib7000p_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); 392 dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
339 dib7000p_write_word(state, 22, (u16) ( (bw->ifreq ) & 0xffff)); 393 dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
340 394
341 dib7000p_write_word(state, 72, bw->sad_cfg); 395 dib7000p_write_word(state, 72, bw->sad_cfg);
342} 396}
343 397
398static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
399{
400 u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
401 internal |= (u32) dib7000p_read_word(state, 19);
402 internal /= 1000;
403
404 return internal;
405}
406
407int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
408{
409 struct dib7000p_state *state = fe->demodulator_priv;
410 u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
411 u8 loopdiv, prediv;
412 u32 internal, xtal;
413
414 /* get back old values */
415 prediv = reg_1856 & 0x3f;
416 loopdiv = (reg_1856 >> 6) & 0x3f;
417
418 if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
419 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
420 reg_1856 &= 0xf000;
421 reg_1857 = dib7000p_read_word(state, 1857);
422 dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
423
424 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
425
426 /* write new system clk into P_sec_len */
427 internal = dib7000p_get_internal_freq(state);
428 xtal = (internal / loopdiv) * prediv;
429 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
430 dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
431 dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
432
433 dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
434
435 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
436 dprintk("Waiting for PLL to lock");
437
438 return 0;
439 }
440 return -EIO;
441}
442EXPORT_SYMBOL(dib7000p_update_pll);
443
344static int dib7000p_reset_gpio(struct dib7000p_state *st) 444static int dib7000p_reset_gpio(struct dib7000p_state *st)
345{ 445{
346 /* reset the GPIOs */ 446 /* reset the GPIOs */
347 dprintk( "gpio dir: %x: val: %x, pwm_pos: %x",st->gpio_dir, st->gpio_val,st->cfg.gpio_pwm_pos); 447 dprintk("gpio dir: %x: val: %x, pwm_pos: %x", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
348 448
349 dib7000p_write_word(st, 1029, st->gpio_dir); 449 dib7000p_write_word(st, 1029, st->gpio_dir);
350 dib7000p_write_word(st, 1030, st->gpio_val); 450 dib7000p_write_word(st, 1030, st->gpio_val);
@@ -360,13 +460,13 @@ static int dib7000p_reset_gpio(struct dib7000p_state *st)
360static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val) 460static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
361{ 461{
362 st->gpio_dir = dib7000p_read_word(st, 1029); 462 st->gpio_dir = dib7000p_read_word(st, 1029);
363 st->gpio_dir &= ~(1 << num); /* reset the direction bit */ 463 st->gpio_dir &= ~(1 << num); /* reset the direction bit */
364 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */ 464 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
365 dib7000p_write_word(st, 1029, st->gpio_dir); 465 dib7000p_write_word(st, 1029, st->gpio_dir);
366 466
367 st->gpio_val = dib7000p_read_word(st, 1030); 467 st->gpio_val = dib7000p_read_word(st, 1030);
368 st->gpio_val &= ~(1 << num); /* reset the direction bit */ 468 st->gpio_val &= ~(1 << num); /* reset the direction bit */
369 st->gpio_val |= (val & 0x01) << num; /* set the new value */ 469 st->gpio_val |= (val & 0x01) << num; /* set the new value */
370 dib7000p_write_word(st, 1030, st->gpio_val); 470 dib7000p_write_word(st, 1030, st->gpio_val);
371 471
372 return 0; 472 return 0;
@@ -377,96 +477,94 @@ int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
377 struct dib7000p_state *state = demod->demodulator_priv; 477 struct dib7000p_state *state = demod->demodulator_priv;
378 return dib7000p_cfg_gpio(state, num, dir, val); 478 return dib7000p_cfg_gpio(state, num, dir, val);
379} 479}
380
381EXPORT_SYMBOL(dib7000p_set_gpio); 480EXPORT_SYMBOL(dib7000p_set_gpio);
382static u16 dib7000p_defaults[] =
383 481
384{ 482static u16 dib7000p_defaults[] = {
385 // auto search configuration 483 // auto search configuration
386 3, 2, 484 3, 2,
387 0x0004, 485 0x0004,
388 0x1000, 486 0x1000,
389 0x0814, /* Equal Lock */ 487 0x0814, /* Equal Lock */
390 488
391 12, 6, 489 12, 6,
392 0x001b, 490 0x001b,
393 0x7740, 491 0x7740,
394 0x005b, 492 0x005b,
395 0x8d80, 493 0x8d80,
396 0x01c9, 494 0x01c9,
397 0xc380, 495 0xc380,
398 0x0000, 496 0x0000,
399 0x0080, 497 0x0080,
400 0x0000, 498 0x0000,
401 0x0090, 499 0x0090,
402 0x0001, 500 0x0001,
403 0xd4c0, 501 0xd4c0,
404 502
405 1, 26, 503 1, 26,
406 0x6680, // P_timf_alpha=6, P_corm_alpha=6, P_corm_thres=128 default: 6,4,26 504 0x6680,
407 505
408 /* set ADC level to -16 */ 506 /* set ADC level to -16 */
409 11, 79, 507 11, 79,
410 (1 << 13) - 825 - 117, 508 (1 << 13) - 825 - 117,
411 (1 << 13) - 837 - 117, 509 (1 << 13) - 837 - 117,
412 (1 << 13) - 811 - 117, 510 (1 << 13) - 811 - 117,
413 (1 << 13) - 766 - 117, 511 (1 << 13) - 766 - 117,
414 (1 << 13) - 737 - 117, 512 (1 << 13) - 737 - 117,
415 (1 << 13) - 693 - 117, 513 (1 << 13) - 693 - 117,
416 (1 << 13) - 648 - 117, 514 (1 << 13) - 648 - 117,
417 (1 << 13) - 619 - 117, 515 (1 << 13) - 619 - 117,
418 (1 << 13) - 575 - 117, 516 (1 << 13) - 575 - 117,
419 (1 << 13) - 531 - 117, 517 (1 << 13) - 531 - 117,
420 (1 << 13) - 501 - 117, 518 (1 << 13) - 501 - 117,
421 519
422 1, 142, 520 1, 142,
423 0x0410, // P_palf_filter_on=1, P_palf_filter_freeze=0, P_palf_alpha_regul=16 521 0x0410,
424 522
425 /* disable power smoothing */ 523 /* disable power smoothing */
426 8, 145, 524 8, 145,
427 0, 525 0,
428 0, 526 0,
429 0, 527 0,
430 0, 528 0,
431 0, 529 0,
432 0, 530 0,
433 0, 531 0,
434 0, 532 0,
435 533
436 1, 154, 534 1, 154,
437 1 << 13, // P_fft_freq_dir=1, P_fft_nb_to_cut=0 535 1 << 13,
438 536
439 1, 168, 537 1, 168,
440 0x0ccd, // P_pha3_thres, default 0x3000 538 0x0ccd,
441
442// 1, 169,
443// 0x0010, // P_cti_use_cpe=0, P_cti_use_prog=0, P_cti_win_len=16, default: 0x0010
444 539
445 1, 183, 540 1, 183,
446 0x200f, // P_cspu_regul=512, P_cspu_win_cut=15, default: 0x2005 541 0x200f,
542
543 1, 212,
544 0x169,
447 545
448 5, 187, 546 5, 187,
449 0x023d, // P_adp_regul_cnt=573, default: 410 547 0x023d,
450 0x00a4, // P_adp_noise_cnt= 548 0x00a4,
451 0x00a4, // P_adp_regul_ext 549 0x00a4,
452 0x7ff0, // P_adp_noise_ext 550 0x7ff0,
453 0x3ccc, // P_adp_fil 551 0x3ccc,
454 552
455 1, 198, 553 1, 198,
456 0x800, // P_equal_thres_wgn 554 0x800,
457 555
458 1, 222, 556 1, 222,
459 0x0010, // P_fec_ber_rs_len=2 557 0x0010,
460 558
461 1, 235, 559 1, 235,
462 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard 560 0x0062,
463 561
464 2, 901, 562 2, 901,
465 0x0006, // P_clk_cfg1 563 0x0006,
466 (3 << 10) | (1 << 6), // P_divclksel=3 P_divbitsel=1 564 (3 << 10) | (1 << 6),
467 565
468 1, 905, 566 1, 905,
469 0x2c8e, // Tuner IO bank: max drive (14mA) + divout pads max drive 567 0x2c8e,
470 568
471 0, 569 0,
472}; 570};
@@ -475,51 +573,64 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
475{ 573{
476 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 574 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
477 575
576 if (state->version == SOC7090)
577 dibx000_reset_i2c_master(&state->i2c_master);
578
478 dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE); 579 dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
479 580
480 /* restart all parts */ 581 /* restart all parts */
481 dib7000p_write_word(state, 770, 0xffff); 582 dib7000p_write_word(state, 770, 0xffff);
482 dib7000p_write_word(state, 771, 0xffff); 583 dib7000p_write_word(state, 771, 0xffff);
483 dib7000p_write_word(state, 772, 0x001f); 584 dib7000p_write_word(state, 772, 0x001f);
484 dib7000p_write_word(state, 898, 0x0003); 585 dib7000p_write_word(state, 898, 0x0003);
485 /* except i2c, sdio, gpio - control interfaces */ 586 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
486 dib7000p_write_word(state, 1280, 0x01fc - ((1 << 7) | (1 << 6) | (1 << 5)) ); 587
487 588 dib7000p_write_word(state, 770, 0);
488 dib7000p_write_word(state, 770, 0); 589 dib7000p_write_word(state, 771, 0);
489 dib7000p_write_word(state, 771, 0); 590 dib7000p_write_word(state, 772, 0);
490 dib7000p_write_word(state, 772, 0); 591 dib7000p_write_word(state, 898, 0);
491 dib7000p_write_word(state, 898, 0);
492 dib7000p_write_word(state, 1280, 0); 592 dib7000p_write_word(state, 1280, 0);
493 593
494 /* default */ 594 /* default */
495 dib7000p_reset_pll(state); 595 dib7000p_reset_pll(state);
496 596
497 if (dib7000p_reset_gpio(state) != 0) 597 if (dib7000p_reset_gpio(state) != 0)
498 dprintk( "GPIO reset was not successful."); 598 dprintk("GPIO reset was not successful.");
499
500 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
501 dprintk( "OUTPUT_MODE could not be reset.");
502 599
503 /* unforce divstr regardless whether i2c enumeration was done or not */ 600 if (state->version == SOC7090) {
504 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1) ); 601 dib7000p_write_word(state, 899, 0);
505 602
506 dib7000p_set_bandwidth(state, 8000); 603 /* impulse noise */
604 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
605 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
606 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
607 dib7000p_write_word(state, 273, (1<<6) | 30);
608 }
609 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
610 dprintk("OUTPUT_MODE could not be reset.");
507 611
508 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); 612 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
509 dib7000p_sad_calib(state); 613 dib7000p_sad_calib(state);
510 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF); 614 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
511 615
512 // P_iqc_alpha_pha, P_iqc_alpha_amp_dcc_alpha, ... 616 /* unforce divstr regardless whether i2c enumeration was done or not */
513 if(state->cfg.tuner_is_baseband) 617 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
514 dib7000p_write_word(state, 36,0x0755); 618
515 else 619 dib7000p_set_bandwidth(state, 8000);
516 dib7000p_write_word(state, 36,0x1f55); 620
621 if (state->version == SOC7090) {
622 dib7000p_write_word(state, 36, 0x5755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
623 } else {
624 if (state->cfg.tuner_is_baseband)
625 dib7000p_write_word(state, 36, 0x0755);
626 else
627 dib7000p_write_word(state, 36, 0x1f55);
628 }
517 629
518 dib7000p_write_tab(state, dib7000p_defaults); 630 dib7000p_write_tab(state, dib7000p_defaults);
519 631
520 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 632 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
521 633
522
523 return 0; 634 return 0;
524} 635}
525 636
@@ -527,9 +638,9 @@ static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
527{ 638{
528 u16 tmp = 0; 639 u16 tmp = 0;
529 tmp = dib7000p_read_word(state, 903); 640 tmp = dib7000p_read_word(state, 903);
530 dib7000p_write_word(state, 903, (tmp | 0x1)); //pwr-up pll 641 dib7000p_write_word(state, 903, (tmp | 0x1));
531 tmp = dib7000p_read_word(state, 900); 642 tmp = dib7000p_read_word(state, 900);
532 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6)); //use High freq clock 643 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
533} 644}
534 645
535static void dib7000p_restart_agc(struct dib7000p_state *state) 646static void dib7000p_restart_agc(struct dib7000p_state *state)
@@ -543,11 +654,9 @@ static int dib7000p_update_lna(struct dib7000p_state *state)
543{ 654{
544 u16 dyn_gain; 655 u16 dyn_gain;
545 656
546 // when there is no LNA to program return immediatly
547 if (state->cfg.update_lna) { 657 if (state->cfg.update_lna) {
548 // read dyn_gain here (because it is demod-dependent and not fe)
549 dyn_gain = dib7000p_read_word(state, 394); 658 dyn_gain = dib7000p_read_word(state, 394);
550 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed 659 if (state->cfg.update_lna(&state->demod, dyn_gain)) {
551 dib7000p_restart_agc(state); 660 dib7000p_restart_agc(state);
552 return 1; 661 return 1;
553 } 662 }
@@ -571,24 +680,24 @@ static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
571 } 680 }
572 681
573 if (agc == NULL) { 682 if (agc == NULL) {
574 dprintk( "no valid AGC configuration found for band 0x%02x",band); 683 dprintk("no valid AGC configuration found for band 0x%02x", band);
575 return -EINVAL; 684 return -EINVAL;
576 } 685 }
577 686
578 state->current_agc = agc; 687 state->current_agc = agc;
579 688
580 /* AGC */ 689 /* AGC */
581 dib7000p_write_word(state, 75 , agc->setup ); 690 dib7000p_write_word(state, 75, agc->setup);
582 dib7000p_write_word(state, 76 , agc->inv_gain ); 691 dib7000p_write_word(state, 76, agc->inv_gain);
583 dib7000p_write_word(state, 77 , agc->time_stabiliz ); 692 dib7000p_write_word(state, 77, agc->time_stabiliz);
584 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock); 693 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
585 694
586 // Demod AGC loop configuration 695 // Demod AGC loop configuration
587 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp); 696 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
588 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp); 697 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
589 698
590 /* AGC continued */ 699 /* AGC continued */
591 dprintk( "WBD: ref: %d, sel: %d, active: %d, alpha: %d", 700 dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
592 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); 701 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
593 702
594 if (state->wbd_ref != 0) 703 if (state->wbd_ref != 0)
@@ -598,101 +707,135 @@ static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
598 707
599 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); 708 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
600 709
601 dib7000p_write_word(state, 107, agc->agc1_max); 710 dib7000p_write_word(state, 107, agc->agc1_max);
602 dib7000p_write_word(state, 108, agc->agc1_min); 711 dib7000p_write_word(state, 108, agc->agc1_min);
603 dib7000p_write_word(state, 109, agc->agc2_max); 712 dib7000p_write_word(state, 109, agc->agc2_max);
604 dib7000p_write_word(state, 110, agc->agc2_min); 713 dib7000p_write_word(state, 110, agc->agc2_min);
605 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2); 714 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
606 dib7000p_write_word(state, 112, agc->agc1_pt3); 715 dib7000p_write_word(state, 112, agc->agc1_pt3);
607 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); 716 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
608 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); 717 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
609 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); 718 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
610 return 0; 719 return 0;
611} 720}
612 721
722static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
723{
724 u32 internal = dib7000p_get_internal_freq(state);
725 s32 unit_khz_dds_val = 67108864 / (internal); /* 2**26 / Fsampling is the unit 1KHz offset */
726 u32 abs_offset_khz = ABS(offset_khz);
727 u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
728 u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
729
730 dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d", offset_khz, internal, invert);
731
732 if (offset_khz < 0)
733 unit_khz_dds_val *= -1;
734
735 /* IF tuner */
736 if (invert)
737 dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
738 else
739 dds += (abs_offset_khz * unit_khz_dds_val);
740
741 if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
742 dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
743 dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
744 }
745}
746
613static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 747static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
614{ 748{
615 struct dib7000p_state *state = demod->demodulator_priv; 749 struct dib7000p_state *state = demod->demodulator_priv;
616 int ret = -1; 750 int ret = -1;
617 u8 *agc_state = &state->agc_state; 751 u8 *agc_state = &state->agc_state;
618 u8 agc_split; 752 u8 agc_split;
753 u16 reg;
754 u32 upd_demod_gain_period = 0x1000;
619 755
620 switch (state->agc_state) { 756 switch (state->agc_state) {
621 case 0: 757 case 0:
622 // set power-up level: interf+analog+AGC 758 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
623 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 759 if (state->version == SOC7090) {
760 reg = dib7000p_read_word(state, 0x79b) & 0xff00;
761 dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */
762 dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
763
764 /* enable adc i & q */
765 reg = dib7000p_read_word(state, 0x780);
766 dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
767 } else {
624 dib7000p_set_adc_state(state, DIBX000_ADC_ON); 768 dib7000p_set_adc_state(state, DIBX000_ADC_ON);
625 dib7000p_pll_clk_cfg(state); 769 dib7000p_pll_clk_cfg(state);
770 }
626 771
627 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0) 772 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
628 return -1; 773 return -1;
629
630 ret = 7;
631 (*agc_state)++;
632 break;
633 774
634 case 1: 775 dib7000p_set_dds(state, 0);
635 // AGC initialization 776 ret = 7;
636 if (state->cfg.agc_control) 777 (*agc_state)++;
637 state->cfg.agc_control(&state->demod, 1); 778 break;
638
639 dib7000p_write_word(state, 78, 32768);
640 if (!state->current_agc->perform_agc_softsplit) {
641 /* we are using the wbd - so slow AGC startup */
642 /* force 0 split on WBD and restart AGC */
643 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
644 (*agc_state)++;
645 ret = 5;
646 } else {
647 /* default AGC startup */
648 (*agc_state) = 4;
649 /* wait AGC rough lock time */
650 ret = 7;
651 }
652 779
653 dib7000p_restart_agc(state); 780 case 1:
654 break; 781 if (state->cfg.agc_control)
782 state->cfg.agc_control(&state->demod, 1);
655 783
656 case 2: /* fast split search path after 5sec */ 784 dib7000p_write_word(state, 78, 32768);
657 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */ 785 if (!state->current_agc->perform_agc_softsplit) {
658 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */ 786 /* we are using the wbd - so slow AGC startup */
787 /* force 0 split on WBD and restart AGC */
788 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
659 (*agc_state)++; 789 (*agc_state)++;
660 ret = 14; 790 ret = 5;
661 break; 791 } else {
792 /* default AGC startup */
793 (*agc_state) = 4;
794 /* wait AGC rough lock time */
795 ret = 7;
796 }
662 797
663 case 3: /* split search ended */ 798 dib7000p_restart_agc(state);
664 agc_split = (u8)dib7000p_read_word(state, 396); /* store the split value for the next time */ 799 break;
665 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
666 800
667 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */ 801 case 2: /* fast split search path after 5sec */
668 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */ 802 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
803 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
804 (*agc_state)++;
805 ret = 14;
806 break;
669 807
670 dib7000p_restart_agc(state); 808 case 3: /* split search ended */
809 agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */
810 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
671 811
672 dprintk( "SPLIT %p: %hd", demod, agc_split); 812 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
813 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
673 814
674 (*agc_state)++; 815 dib7000p_restart_agc(state);
675 ret = 5;
676 break;
677 816
678 case 4: /* LNA startup */ 817 dprintk("SPLIT %p: %hd", demod, agc_split);
679 // wait AGC accurate lock time
680 ret = 7;
681 818
682 if (dib7000p_update_lna(state)) 819 (*agc_state)++;
683 // wait only AGC rough lock time 820 ret = 5;
684 ret = 5; 821 break;
685 else // nothing was done, go to the next state
686 (*agc_state)++;
687 break;
688 822
689 case 5: 823 case 4: /* LNA startup */
690 if (state->cfg.agc_control) 824 ret = 7;
691 state->cfg.agc_control(&state->demod, 0); 825
826 if (dib7000p_update_lna(state))
827 ret = 5;
828 else
692 (*agc_state)++; 829 (*agc_state)++;
693 break; 830 break;
694 default: 831
695 break; 832 case 5:
833 if (state->cfg.agc_control)
834 state->cfg.agc_control(&state->demod, 0);
835 (*agc_state)++;
836 break;
837 default:
838 break;
696 } 839 }
697 return ret; 840 return ret;
698} 841}
@@ -703,45 +846,89 @@ static void dib7000p_update_timf(struct dib7000p_state *state)
703 state->timf = timf * 160 / (state->current_bandwidth / 50); 846 state->timf = timf * 160 / (state->current_bandwidth / 50);
704 dib7000p_write_word(state, 23, (u16) (timf >> 16)); 847 dib7000p_write_word(state, 23, (u16) (timf >> 16));
705 dib7000p_write_word(state, 24, (u16) (timf & 0xffff)); 848 dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
706 dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->cfg.bw->timf); 849 dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf);
850
851}
707 852
853u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
854{
855 struct dib7000p_state *state = fe->demodulator_priv;
856 switch (op) {
857 case DEMOD_TIMF_SET:
858 state->timf = timf;
859 break;
860 case DEMOD_TIMF_UPDATE:
861 dib7000p_update_timf(state);
862 break;
863 case DEMOD_TIMF_GET:
864 break;
865 }
866 dib7000p_set_bandwidth(state, state->current_bandwidth);
867 return state->timf;
708} 868}
869EXPORT_SYMBOL(dib7000p_ctrl_timf);
709 870
710static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq) 871static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq)
711{ 872{
712 u16 value, est[4]; 873 u16 value, est[4];
713 874
714 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 875 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
715 876
716 /* nfft, guard, qam, alpha */ 877 /* nfft, guard, qam, alpha */
717 value = 0; 878 value = 0;
718 switch (ch->u.ofdm.transmission_mode) { 879 switch (ch->u.ofdm.transmission_mode) {
719 case TRANSMISSION_MODE_2K: value |= (0 << 7); break; 880 case TRANSMISSION_MODE_2K:
720 case TRANSMISSION_MODE_4K: value |= (2 << 7); break; 881 value |= (0 << 7);
721 default: 882 break;
722 case TRANSMISSION_MODE_8K: value |= (1 << 7); break; 883 case TRANSMISSION_MODE_4K:
884 value |= (2 << 7);
885 break;
886 default:
887 case TRANSMISSION_MODE_8K:
888 value |= (1 << 7);
889 break;
723 } 890 }
724 switch (ch->u.ofdm.guard_interval) { 891 switch (ch->u.ofdm.guard_interval) {
725 case GUARD_INTERVAL_1_32: value |= (0 << 5); break; 892 case GUARD_INTERVAL_1_32:
726 case GUARD_INTERVAL_1_16: value |= (1 << 5); break; 893 value |= (0 << 5);
727 case GUARD_INTERVAL_1_4: value |= (3 << 5); break; 894 break;
728 default: 895 case GUARD_INTERVAL_1_16:
729 case GUARD_INTERVAL_1_8: value |= (2 << 5); break; 896 value |= (1 << 5);
897 break;
898 case GUARD_INTERVAL_1_4:
899 value |= (3 << 5);
900 break;
901 default:
902 case GUARD_INTERVAL_1_8:
903 value |= (2 << 5);
904 break;
730 } 905 }
731 switch (ch->u.ofdm.constellation) { 906 switch (ch->u.ofdm.constellation) {
732 case QPSK: value |= (0 << 3); break; 907 case QPSK:
733 case QAM_16: value |= (1 << 3); break; 908 value |= (0 << 3);
734 default: 909 break;
735 case QAM_64: value |= (2 << 3); break; 910 case QAM_16:
911 value |= (1 << 3);
912 break;
913 default:
914 case QAM_64:
915 value |= (2 << 3);
916 break;
736 } 917 }
737 switch (HIERARCHY_1) { 918 switch (HIERARCHY_1) {
738 case HIERARCHY_2: value |= 2; break; 919 case HIERARCHY_2:
739 case HIERARCHY_4: value |= 4; break; 920 value |= 2;
740 default: 921 break;
741 case HIERARCHY_1: value |= 1; break; 922 case HIERARCHY_4:
923 value |= 4;
924 break;
925 default:
926 case HIERARCHY_1:
927 value |= 1;
928 break;
742 } 929 }
743 dib7000p_write_word(state, 0, value); 930 dib7000p_write_word(state, 0, value);
744 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */ 931 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
745 932
746 /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */ 933 /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
747 value = 0; 934 value = 0;
@@ -752,39 +939,63 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
752 if (1 == 1) 939 if (1 == 1)
753 value |= 1; 940 value |= 1;
754 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) { 941 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
755 case FEC_2_3: value |= (2 << 1); break; 942 case FEC_2_3:
756 case FEC_3_4: value |= (3 << 1); break; 943 value |= (2 << 1);
757 case FEC_5_6: value |= (5 << 1); break; 944 break;
758 case FEC_7_8: value |= (7 << 1); break; 945 case FEC_3_4:
759 default: 946 value |= (3 << 1);
760 case FEC_1_2: value |= (1 << 1); break; 947 break;
948 case FEC_5_6:
949 value |= (5 << 1);
950 break;
951 case FEC_7_8:
952 value |= (7 << 1);
953 break;
954 default:
955 case FEC_1_2:
956 value |= (1 << 1);
957 break;
761 } 958 }
762 dib7000p_write_word(state, 208, value); 959 dib7000p_write_word(state, 208, value);
763 960
764 /* offset loop parameters */ 961 /* offset loop parameters */
765 dib7000p_write_word(state, 26, 0x6680); // timf(6xxx) 962 dib7000p_write_word(state, 26, 0x6680);
766 dib7000p_write_word(state, 32, 0x0003); // pha_off_max(xxx3) 963 dib7000p_write_word(state, 32, 0x0003);
767 dib7000p_write_word(state, 29, 0x1273); // isi 964 dib7000p_write_word(state, 29, 0x1273);
768 dib7000p_write_word(state, 33, 0x0005); // sfreq(xxx5) 965 dib7000p_write_word(state, 33, 0x0005);
769 966
770 /* P_dvsy_sync_wait */ 967 /* P_dvsy_sync_wait */
771 switch (ch->u.ofdm.transmission_mode) { 968 switch (ch->u.ofdm.transmission_mode) {
772 case TRANSMISSION_MODE_8K: value = 256; break; 969 case TRANSMISSION_MODE_8K:
773 case TRANSMISSION_MODE_4K: value = 128; break; 970 value = 256;
774 case TRANSMISSION_MODE_2K: 971 break;
775 default: value = 64; break; 972 case TRANSMISSION_MODE_4K:
973 value = 128;
974 break;
975 case TRANSMISSION_MODE_2K:
976 default:
977 value = 64;
978 break;
776 } 979 }
777 switch (ch->u.ofdm.guard_interval) { 980 switch (ch->u.ofdm.guard_interval) {
778 case GUARD_INTERVAL_1_16: value *= 2; break; 981 case GUARD_INTERVAL_1_16:
779 case GUARD_INTERVAL_1_8: value *= 4; break; 982 value *= 2;
780 case GUARD_INTERVAL_1_4: value *= 8; break; 983 break;
781 default: 984 case GUARD_INTERVAL_1_8:
782 case GUARD_INTERVAL_1_32: value *= 1; break; 985 value *= 4;
986 break;
987 case GUARD_INTERVAL_1_4:
988 value *= 8;
989 break;
990 default:
991 case GUARD_INTERVAL_1_32:
992 value *= 1;
993 break;
783 } 994 }
784 if (state->cfg.diversity_delay == 0) 995 if (state->cfg.diversity_delay == 0)
785 state->div_sync_wait = (value * 3) / 2 + 48; // add 50% SFN margin + compensate for one DVSY-fifo 996 state->div_sync_wait = (value * 3) / 2 + 48;
786 else 997 else
787 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compensate for one DVSY-fifo 998 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
788 999
789 /* deactive the possibility of diversity reception if extended interleaver */ 1000 /* deactive the possibility of diversity reception if extended interleaver */
790 state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K; 1001 state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K;
@@ -792,24 +1003,24 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
792 1003
793 /* channel estimation fine configuration */ 1004 /* channel estimation fine configuration */
794 switch (ch->u.ofdm.constellation) { 1005 switch (ch->u.ofdm.constellation) {
795 case QAM_64: 1006 case QAM_64:
796 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ 1007 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
797 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ 1008 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
798 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 1009 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
799 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ 1010 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
800 break; 1011 break;
801 case QAM_16: 1012 case QAM_16:
802 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */ 1013 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
803 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ 1014 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
804 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 1015 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
805 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */ 1016 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
806 break; 1017 break;
807 default: 1018 default:
808 est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */ 1019 est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
809 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */ 1020 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
810 est[2] = 0x0333; /* P_adp_regul_ext 0.1 */ 1021 est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
811 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */ 1022 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
812 break; 1023 break;
813 } 1024 }
814 for (value = 0; value < 4; value++) 1025 for (value = 0; value < 4; value++)
815 dib7000p_write_word(state, 187 + value, est[value]); 1026 dib7000p_write_word(state, 187 + value, est[value]);
@@ -820,14 +1031,15 @@ static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_fron
820 struct dib7000p_state *state = demod->demodulator_priv; 1031 struct dib7000p_state *state = demod->demodulator_priv;
821 struct dvb_frontend_parameters schan; 1032 struct dvb_frontend_parameters schan;
822 u32 value, factor; 1033 u32 value, factor;
1034 u32 internal = dib7000p_get_internal_freq(state);
823 1035
824 schan = *ch; 1036 schan = *ch;
825 schan.u.ofdm.constellation = QAM_64; 1037 schan.u.ofdm.constellation = QAM_64;
826 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 1038 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
827 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 1039 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
828 schan.u.ofdm.code_rate_HP = FEC_2_3; 1040 schan.u.ofdm.code_rate_HP = FEC_2_3;
829 schan.u.ofdm.code_rate_LP = FEC_3_4; 1041 schan.u.ofdm.code_rate_LP = FEC_3_4;
830 schan.u.ofdm.hierarchy_information = 0; 1042 schan.u.ofdm.hierarchy_information = 0;
831 1043
832 dib7000p_set_channel(state, &schan, 7); 1044 dib7000p_set_channel(state, &schan, 7);
833 1045
@@ -837,16 +1049,15 @@ static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_fron
837 else 1049 else
838 factor = 6; 1050 factor = 6;
839 1051
840 // always use the setting for 8MHz here lock_time for 7,6 MHz are longer 1052 value = 30 * internal * factor;
841 value = 30 * state->cfg.bw->internal * factor; 1053 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
842 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time 1054 dib7000p_write_word(state, 7, (u16) (value & 0xffff));
843 dib7000p_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time 1055 value = 100 * internal * factor;
844 value = 100 * state->cfg.bw->internal * factor; 1056 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
845 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time 1057 dib7000p_write_word(state, 9, (u16) (value & 0xffff));
846 dib7000p_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time 1058 value = 500 * internal * factor;
847 value = 500 * state->cfg.bw->internal * factor; 1059 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
848 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time 1060 dib7000p_write_word(state, 11, (u16) (value & 0xffff));
849 dib7000p_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
850 1061
851 value = dib7000p_read_word(state, 0); 1062 value = dib7000p_read_word(state, 0);
852 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value)); 1063 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
@@ -861,101 +1072,101 @@ static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
861 struct dib7000p_state *state = demod->demodulator_priv; 1072 struct dib7000p_state *state = demod->demodulator_priv;
862 u16 irq_pending = dib7000p_read_word(state, 1284); 1073 u16 irq_pending = dib7000p_read_word(state, 1284);
863 1074
864 if (irq_pending & 0x1) // failed 1075 if (irq_pending & 0x1)
865 return 1; 1076 return 1;
866 1077
867 if (irq_pending & 0x2) // succeeded 1078 if (irq_pending & 0x2)
868 return 2; 1079 return 2;
869 1080
870 return 0; // still pending 1081 return 0;
871} 1082}
872 1083
873static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw) 1084static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
874{ 1085{
875 static s16 notch[]={16143, 14402, 12238, 9713, 6902, 3888, 759, -2392}; 1086 static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
876 static u8 sine [] ={0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22, 1087 static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
877 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51, 1088 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
878 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80, 1089 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
879 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105, 1090 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
880 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126, 1091 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
881 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146, 1092 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
882 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165, 1093 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
883 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182, 1094 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
884 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 1095 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
885 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212, 1096 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
886 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224, 1097 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
887 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235, 1098 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
888 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243, 1099 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
889 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249, 1100 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
890 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254, 1101 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
891 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1102 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
892 255, 255, 255, 255, 255, 255}; 1103 255, 255, 255, 255, 255, 255
1104 };
893 1105
894 u32 xtal = state->cfg.bw->xtal_hz / 1000; 1106 u32 xtal = state->cfg.bw->xtal_hz / 1000;
895 int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz; 1107 int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
896 int k; 1108 int k;
897 int coef_re[8],coef_im[8]; 1109 int coef_re[8], coef_im[8];
898 int bw_khz = bw; 1110 int bw_khz = bw;
899 u32 pha; 1111 u32 pha;
900 1112
901 dprintk( "relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal); 1113 dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
902
903 1114
904 if (f_rel < -bw_khz/2 || f_rel > bw_khz/2) 1115 if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
905 return; 1116 return;
906 1117
907 bw_khz /= 100; 1118 bw_khz /= 100;
908 1119
909 dib7000p_write_word(state, 142 ,0x0610); 1120 dib7000p_write_word(state, 142, 0x0610);
910 1121
911 for (k = 0; k < 8; k++) { 1122 for (k = 0; k < 8; k++) {
912 pha = ((f_rel * (k+1) * 112 * 80/bw_khz) /1000) & 0x3ff; 1123 pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
913 1124
914 if (pha==0) { 1125 if (pha == 0) {
915 coef_re[k] = 256; 1126 coef_re[k] = 256;
916 coef_im[k] = 0; 1127 coef_im[k] = 0;
917 } else if(pha < 256) { 1128 } else if (pha < 256) {
918 coef_re[k] = sine[256-(pha&0xff)]; 1129 coef_re[k] = sine[256 - (pha & 0xff)];
919 coef_im[k] = sine[pha&0xff]; 1130 coef_im[k] = sine[pha & 0xff];
920 } else if (pha == 256) { 1131 } else if (pha == 256) {
921 coef_re[k] = 0; 1132 coef_re[k] = 0;
922 coef_im[k] = 256; 1133 coef_im[k] = 256;
923 } else if (pha < 512) { 1134 } else if (pha < 512) {
924 coef_re[k] = -sine[pha&0xff]; 1135 coef_re[k] = -sine[pha & 0xff];
925 coef_im[k] = sine[256 - (pha&0xff)]; 1136 coef_im[k] = sine[256 - (pha & 0xff)];
926 } else if (pha == 512) { 1137 } else if (pha == 512) {
927 coef_re[k] = -256; 1138 coef_re[k] = -256;
928 coef_im[k] = 0; 1139 coef_im[k] = 0;
929 } else if (pha < 768) { 1140 } else if (pha < 768) {
930 coef_re[k] = -sine[256-(pha&0xff)]; 1141 coef_re[k] = -sine[256 - (pha & 0xff)];
931 coef_im[k] = -sine[pha&0xff]; 1142 coef_im[k] = -sine[pha & 0xff];
932 } else if (pha == 768) { 1143 } else if (pha == 768) {
933 coef_re[k] = 0; 1144 coef_re[k] = 0;
934 coef_im[k] = -256; 1145 coef_im[k] = -256;
935 } else { 1146 } else {
936 coef_re[k] = sine[pha&0xff]; 1147 coef_re[k] = sine[pha & 0xff];
937 coef_im[k] = -sine[256 - (pha&0xff)]; 1148 coef_im[k] = -sine[256 - (pha & 0xff)];
938 } 1149 }
939 1150
940 coef_re[k] *= notch[k]; 1151 coef_re[k] *= notch[k];
941 coef_re[k] += (1<<14); 1152 coef_re[k] += (1 << 14);
942 if (coef_re[k] >= (1<<24)) 1153 if (coef_re[k] >= (1 << 24))
943 coef_re[k] = (1<<24) - 1; 1154 coef_re[k] = (1 << 24) - 1;
944 coef_re[k] /= (1<<15); 1155 coef_re[k] /= (1 << 15);
945 1156
946 coef_im[k] *= notch[k]; 1157 coef_im[k] *= notch[k];
947 coef_im[k] += (1<<14); 1158 coef_im[k] += (1 << 14);
948 if (coef_im[k] >= (1<<24)) 1159 if (coef_im[k] >= (1 << 24))
949 coef_im[k] = (1<<24)-1; 1160 coef_im[k] = (1 << 24) - 1;
950 coef_im[k] /= (1<<15); 1161 coef_im[k] /= (1 << 15);
951 1162
952 dprintk( "PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]); 1163 dprintk("PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
953 1164
954 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); 1165 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
955 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff); 1166 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
956 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); 1167 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
957 } 1168 }
958 dib7000p_write_word(state,143 ,0); 1169 dib7000p_write_word(state, 143, 0);
959} 1170}
960 1171
961static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 1172static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
@@ -976,11 +1187,11 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
976 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */ 1187 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
977 tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3); 1188 tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
978 if (state->sfn_workaround_active) { 1189 if (state->sfn_workaround_active) {
979 dprintk( "SFN workaround is active"); 1190 dprintk("SFN workaround is active");
980 tmp |= (1 << 9); 1191 tmp |= (1 << 9);
981 dib7000p_write_word(state, 166, 0x4000); // P_pha3_force_pha_shift 1192 dib7000p_write_word(state, 166, 0x4000);
982 } else { 1193 } else {
983 dib7000p_write_word(state, 166, 0x0000); // P_pha3_force_pha_shift 1194 dib7000p_write_word(state, 166, 0x0000);
984 } 1195 }
985 dib7000p_write_word(state, 29, tmp); 1196 dib7000p_write_word(state, 29, tmp);
986 1197
@@ -993,51 +1204,72 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
993 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ 1204 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
994 tmp = (6 << 8) | 0x80; 1205 tmp = (6 << 8) | 0x80;
995 switch (ch->u.ofdm.transmission_mode) { 1206 switch (ch->u.ofdm.transmission_mode) {
996 case TRANSMISSION_MODE_2K: tmp |= (7 << 12); break; 1207 case TRANSMISSION_MODE_2K:
997 case TRANSMISSION_MODE_4K: tmp |= (8 << 12); break; 1208 tmp |= (2 << 12);
998 default: 1209 break;
999 case TRANSMISSION_MODE_8K: tmp |= (9 << 12); break; 1210 case TRANSMISSION_MODE_4K:
1211 tmp |= (3 << 12);
1212 break;
1213 default:
1214 case TRANSMISSION_MODE_8K:
1215 tmp |= (4 << 12);
1216 break;
1000 } 1217 }
1001 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */ 1218 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
1002 1219
1003 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ 1220 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
1004 tmp = (0 << 4); 1221 tmp = (0 << 4);
1005 switch (ch->u.ofdm.transmission_mode) { 1222 switch (ch->u.ofdm.transmission_mode) {
1006 case TRANSMISSION_MODE_2K: tmp |= 0x6; break; 1223 case TRANSMISSION_MODE_2K:
1007 case TRANSMISSION_MODE_4K: tmp |= 0x7; break; 1224 tmp |= 0x6;
1008 default: 1225 break;
1009 case TRANSMISSION_MODE_8K: tmp |= 0x8; break; 1226 case TRANSMISSION_MODE_4K:
1227 tmp |= 0x7;
1228 break;
1229 default:
1230 case TRANSMISSION_MODE_8K:
1231 tmp |= 0x8;
1232 break;
1010 } 1233 }
1011 dib7000p_write_word(state, 32, tmp); 1234 dib7000p_write_word(state, 32, tmp);
1012 1235
1013 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ 1236 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
1014 tmp = (0 << 4); 1237 tmp = (0 << 4);
1015 switch (ch->u.ofdm.transmission_mode) { 1238 switch (ch->u.ofdm.transmission_mode) {
1016 case TRANSMISSION_MODE_2K: tmp |= 0x6; break; 1239 case TRANSMISSION_MODE_2K:
1017 case TRANSMISSION_MODE_4K: tmp |= 0x7; break; 1240 tmp |= 0x6;
1018 default: 1241 break;
1019 case TRANSMISSION_MODE_8K: tmp |= 0x8; break; 1242 case TRANSMISSION_MODE_4K:
1243 tmp |= 0x7;
1244 break;
1245 default:
1246 case TRANSMISSION_MODE_8K:
1247 tmp |= 0x8;
1248 break;
1020 } 1249 }
1021 dib7000p_write_word(state, 33, tmp); 1250 dib7000p_write_word(state, 33, tmp);
1022 1251
1023 tmp = dib7000p_read_word(state,509); 1252 tmp = dib7000p_read_word(state, 509);
1024 if (!((tmp >> 6) & 0x1)) { 1253 if (!((tmp >> 6) & 0x1)) {
1025 /* restart the fec */ 1254 /* restart the fec */
1026 tmp = dib7000p_read_word(state,771); 1255 tmp = dib7000p_read_word(state, 771);
1027 dib7000p_write_word(state, 771, tmp | (1 << 1)); 1256 dib7000p_write_word(state, 771, tmp | (1 << 1));
1028 dib7000p_write_word(state, 771, tmp); 1257 dib7000p_write_word(state, 771, tmp);
1029 msleep(10); 1258 msleep(40);
1030 tmp = dib7000p_read_word(state,509); 1259 tmp = dib7000p_read_word(state, 509);
1031 } 1260 }
1032
1033 // we achieved a lock - it's time to update the osc freq 1261 // we achieved a lock - it's time to update the osc freq
1034 if ((tmp >> 6) & 0x1) 1262 if ((tmp >> 6) & 0x1) {
1035 dib7000p_update_timf(state); 1263 dib7000p_update_timf(state);
1264 /* P_timf_alpha += 2 */
1265 tmp = dib7000p_read_word(state, 26);
1266 dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
1267 }
1036 1268
1037 if (state->cfg.spur_protect) 1269 if (state->cfg.spur_protect)
1038 dib7000p_spur_protect(state, ch->frequency/1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1270 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
1039 1271
1040 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1272 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
1041 return 0; 1273 return 0;
1042} 1274}
1043 1275
@@ -1046,63 +1278,82 @@ static int dib7000p_wakeup(struct dvb_frontend *demod)
1046 struct dib7000p_state *state = demod->demodulator_priv; 1278 struct dib7000p_state *state = demod->demodulator_priv;
1047 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 1279 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
1048 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); 1280 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1281 if (state->version == SOC7090)
1282 dib7000p_sad_calib(state);
1049 return 0; 1283 return 0;
1050} 1284}
1051 1285
1052static int dib7000p_sleep(struct dvb_frontend *demod) 1286static int dib7000p_sleep(struct dvb_frontend *demod)
1053{ 1287{
1054 struct dib7000p_state *state = demod->demodulator_priv; 1288 struct dib7000p_state *state = demod->demodulator_priv;
1289 if (state->version == SOC7090)
1290 return dib7090_set_output_mode(demod, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1055 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 1291 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1056} 1292}
1057 1293
1058static int dib7000p_identify(struct dib7000p_state *st) 1294static int dib7000p_identify(struct dib7000p_state *st)
1059{ 1295{
1060 u16 value; 1296 u16 value;
1061 dprintk( "checking demod on I2C address: %d (%x)", 1297 dprintk("checking demod on I2C address: %d (%x)", st->i2c_addr, st->i2c_addr);
1062 st->i2c_addr, st->i2c_addr);
1063 1298
1064 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) { 1299 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
1065 dprintk( "wrong Vendor ID (read=0x%x)",value); 1300 dprintk("wrong Vendor ID (read=0x%x)", value);
1066 return -EREMOTEIO; 1301 return -EREMOTEIO;
1067 } 1302 }
1068 1303
1069 if ((value = dib7000p_read_word(st, 769)) != 0x4000) { 1304 if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
1070 dprintk( "wrong Device ID (%x)",value); 1305 dprintk("wrong Device ID (%x)", value);
1071 return -EREMOTEIO; 1306 return -EREMOTEIO;
1072 } 1307 }
1073 1308
1074 return 0; 1309 return 0;
1075} 1310}
1076 1311
1077 1312static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1078static int dib7000p_get_frontend(struct dvb_frontend* fe,
1079 struct dvb_frontend_parameters *fep)
1080{ 1313{
1081 struct dib7000p_state *state = fe->demodulator_priv; 1314 struct dib7000p_state *state = fe->demodulator_priv;
1082 u16 tps = dib7000p_read_word(state,463); 1315 u16 tps = dib7000p_read_word(state, 463);
1083 1316
1084 fep->inversion = INVERSION_AUTO; 1317 fep->inversion = INVERSION_AUTO;
1085 1318
1086 fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth); 1319 fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth);
1087 1320
1088 switch ((tps >> 8) & 0x3) { 1321 switch ((tps >> 8) & 0x3) {
1089 case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break; 1322 case 0:
1090 case 1: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; break; 1323 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1091 /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */ 1324 break;
1325 case 1:
1326 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1327 break;
1328 /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */
1092 } 1329 }
1093 1330
1094 switch (tps & 0x3) { 1331 switch (tps & 0x3) {
1095 case 0: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; break; 1332 case 0:
1096 case 1: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; break; 1333 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1097 case 2: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; break; 1334 break;
1098 case 3: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; break; 1335 case 1:
1336 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1337 break;
1338 case 2:
1339 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1340 break;
1341 case 3:
1342 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1343 break;
1099 } 1344 }
1100 1345
1101 switch ((tps >> 14) & 0x3) { 1346 switch ((tps >> 14) & 0x3) {
1102 case 0: fep->u.ofdm.constellation = QPSK; break; 1347 case 0:
1103 case 1: fep->u.ofdm.constellation = QAM_16; break; 1348 fep->u.ofdm.constellation = QPSK;
1104 case 2: 1349 break;
1105 default: fep->u.ofdm.constellation = QAM_64; break; 1350 case 1:
1351 fep->u.ofdm.constellation = QAM_16;
1352 break;
1353 case 2:
1354 default:
1355 fep->u.ofdm.constellation = QAM_64;
1356 break;
1106 } 1357 }
1107 1358
1108 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */ 1359 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
@@ -1110,22 +1361,42 @@ static int dib7000p_get_frontend(struct dvb_frontend* fe,
1110 1361
1111 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE; 1362 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1112 switch ((tps >> 5) & 0x7) { 1363 switch ((tps >> 5) & 0x7) {
1113 case 1: fep->u.ofdm.code_rate_HP = FEC_1_2; break; 1364 case 1:
1114 case 2: fep->u.ofdm.code_rate_HP = FEC_2_3; break; 1365 fep->u.ofdm.code_rate_HP = FEC_1_2;
1115 case 3: fep->u.ofdm.code_rate_HP = FEC_3_4; break; 1366 break;
1116 case 5: fep->u.ofdm.code_rate_HP = FEC_5_6; break; 1367 case 2:
1117 case 7: 1368 fep->u.ofdm.code_rate_HP = FEC_2_3;
1118 default: fep->u.ofdm.code_rate_HP = FEC_7_8; break; 1369 break;
1370 case 3:
1371 fep->u.ofdm.code_rate_HP = FEC_3_4;
1372 break;
1373 case 5:
1374 fep->u.ofdm.code_rate_HP = FEC_5_6;
1375 break;
1376 case 7:
1377 default:
1378 fep->u.ofdm.code_rate_HP = FEC_7_8;
1379 break;
1119 1380
1120 } 1381 }
1121 1382
1122 switch ((tps >> 2) & 0x7) { 1383 switch ((tps >> 2) & 0x7) {
1123 case 1: fep->u.ofdm.code_rate_LP = FEC_1_2; break; 1384 case 1:
1124 case 2: fep->u.ofdm.code_rate_LP = FEC_2_3; break; 1385 fep->u.ofdm.code_rate_LP = FEC_1_2;
1125 case 3: fep->u.ofdm.code_rate_LP = FEC_3_4; break; 1386 break;
1126 case 5: fep->u.ofdm.code_rate_LP = FEC_5_6; break; 1387 case 2:
1127 case 7: 1388 fep->u.ofdm.code_rate_LP = FEC_2_3;
1128 default: fep->u.ofdm.code_rate_LP = FEC_7_8; break; 1389 break;
1390 case 3:
1391 fep->u.ofdm.code_rate_LP = FEC_3_4;
1392 break;
1393 case 5:
1394 fep->u.ofdm.code_rate_LP = FEC_5_6;
1395 break;
1396 case 7:
1397 default:
1398 fep->u.ofdm.code_rate_LP = FEC_7_8;
1399 break;
1129 } 1400 }
1130 1401
1131 /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */ 1402 /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */
@@ -1133,15 +1404,18 @@ static int dib7000p_get_frontend(struct dvb_frontend* fe,
1133 return 0; 1404 return 0;
1134} 1405}
1135 1406
1136static int dib7000p_set_frontend(struct dvb_frontend* fe, 1407static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1137 struct dvb_frontend_parameters *fep)
1138{ 1408{
1139 struct dib7000p_state *state = fe->demodulator_priv; 1409 struct dib7000p_state *state = fe->demodulator_priv;
1140 int time, ret; 1410 int time, ret;
1141 1411
1142 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z); 1412 if (state->version == SOC7090) {
1413 dib7090_set_diversity_in(fe, 0);
1414 dib7090_set_output_mode(fe, OUTMODE_HIGH_Z);
1415 } else
1416 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
1143 1417
1144 /* maybe the parameter has been changed */ 1418 /* maybe the parameter has been changed */
1145 state->sfn_workaround_active = buggy_sfn_workaround; 1419 state->sfn_workaround_active = buggy_sfn_workaround;
1146 1420
1147 if (fe->ops.tuner_ops.set_params) 1421 if (fe->ops.tuner_ops.set_params)
@@ -1156,9 +1430,7 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
1156 } while (time != -1); 1430 } while (time != -1);
1157 1431
1158 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 1432 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
1159 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || 1433 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1160 fep->u.ofdm.constellation == QAM_AUTO ||
1161 fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1162 int i = 800, found; 1434 int i = 800, found;
1163 1435
1164 dib7000p_autosearch_start(fe, fep); 1436 dib7000p_autosearch_start(fe, fep);
@@ -1167,9 +1439,9 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
1167 found = dib7000p_autosearch_is_irq(fe); 1439 found = dib7000p_autosearch_is_irq(fe);
1168 } while (found == 0 && i--); 1440 } while (found == 0 && i--);
1169 1441
1170 dprintk("autosearch returns: %d",found); 1442 dprintk("autosearch returns: %d", found);
1171 if (found == 0 || found == 1) 1443 if (found == 0 || found == 1)
1172 return 0; // no channel found 1444 return 0;
1173 1445
1174 dib7000p_get_frontend(fe, fep); 1446 dib7000p_get_frontend(fe, fep);
1175 } 1447 }
@@ -1177,11 +1449,15 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
1177 ret = dib7000p_tune(fe, fep); 1449 ret = dib7000p_tune(fe, fep);
1178 1450
1179 /* make this a config parameter */ 1451 /* make this a config parameter */
1180 dib7000p_set_output_mode(state, state->cfg.output_mode); 1452 if (state->version == SOC7090)
1181 return ret; 1453 dib7090_set_output_mode(fe, state->cfg.output_mode);
1454 else
1455 dib7000p_set_output_mode(state, state->cfg.output_mode);
1456
1457 return ret;
1182} 1458}
1183 1459
1184static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat) 1460static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t * stat)
1185{ 1461{
1186 struct dib7000p_state *state = fe->demodulator_priv; 1462 struct dib7000p_state *state = fe->demodulator_priv;
1187 u16 lock = dib7000p_read_word(state, 509); 1463 u16 lock = dib7000p_read_word(state, 509);
@@ -1196,27 +1472,27 @@ static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
1196 *stat |= FE_HAS_VITERBI; 1472 *stat |= FE_HAS_VITERBI;
1197 if (lock & 0x0010) 1473 if (lock & 0x0010)
1198 *stat |= FE_HAS_SYNC; 1474 *stat |= FE_HAS_SYNC;
1199 if ((lock & 0x0038) == 0x38) 1475 if ((lock & 0x0038) == 0x38)
1200 *stat |= FE_HAS_LOCK; 1476 *stat |= FE_HAS_LOCK;
1201 1477
1202 return 0; 1478 return 0;
1203} 1479}
1204 1480
1205static int dib7000p_read_ber(struct dvb_frontend *fe, u32 *ber) 1481static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
1206{ 1482{
1207 struct dib7000p_state *state = fe->demodulator_priv; 1483 struct dib7000p_state *state = fe->demodulator_priv;
1208 *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501); 1484 *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
1209 return 0; 1485 return 0;
1210} 1486}
1211 1487
1212static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 *unc) 1488static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
1213{ 1489{
1214 struct dib7000p_state *state = fe->demodulator_priv; 1490 struct dib7000p_state *state = fe->demodulator_priv;
1215 *unc = dib7000p_read_word(state, 506); 1491 *unc = dib7000p_read_word(state, 506);
1216 return 0; 1492 return 0;
1217} 1493}
1218 1494
1219static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 1495static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
1220{ 1496{
1221 struct dib7000p_state *state = fe->demodulator_priv; 1497 struct dib7000p_state *state = fe->demodulator_priv;
1222 u16 val = dib7000p_read_word(state, 394); 1498 u16 val = dib7000p_read_word(state, 394);
@@ -1224,7 +1500,7 @@ static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1224 return 0; 1500 return 0;
1225} 1501}
1226 1502
1227static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr) 1503static int dib7000p_read_snr(struct dvb_frontend *fe, u16 * snr)
1228{ 1504{
1229 struct dib7000p_state *state = fe->demodulator_priv; 1505 struct dib7000p_state *state = fe->demodulator_priv;
1230 u16 val; 1506 u16 val;
@@ -1240,19 +1516,17 @@ static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr)
1240 noise_exp -= 0x40; 1516 noise_exp -= 0x40;
1241 1517
1242 signal_mant = (val >> 6) & 0xFF; 1518 signal_mant = (val >> 6) & 0xFF;
1243 signal_exp = (val & 0x3F); 1519 signal_exp = (val & 0x3F);
1244 if ((signal_exp & 0x20) != 0) 1520 if ((signal_exp & 0x20) != 0)
1245 signal_exp -= 0x40; 1521 signal_exp -= 0x40;
1246 1522
1247 if (signal_mant != 0) 1523 if (signal_mant != 0)
1248 result = intlog10(2) * 10 * signal_exp + 10 * 1524 result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
1249 intlog10(signal_mant);
1250 else 1525 else
1251 result = intlog10(2) * 10 * signal_exp - 100; 1526 result = intlog10(2) * 10 * signal_exp - 100;
1252 1527
1253 if (noise_mant != 0) 1528 if (noise_mant != 0)
1254 result -= intlog10(2) * 10 * noise_exp + 10 * 1529 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
1255 intlog10(noise_mant);
1256 else 1530 else
1257 result -= intlog10(2) * 10 * noise_exp - 100; 1531 result -= intlog10(2) * 10 * noise_exp - 100;
1258 1532
@@ -1260,7 +1534,7 @@ static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr)
1260 return 0; 1534 return 0;
1261} 1535}
1262 1536
1263static int dib7000p_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune) 1537static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1264{ 1538{
1265 tune->min_delay_ms = 1000; 1539 tune->min_delay_ms = 1000;
1266 return 0; 1540 return 0;
@@ -1270,6 +1544,7 @@ static void dib7000p_release(struct dvb_frontend *demod)
1270{ 1544{
1271 struct dib7000p_state *st = demod->demodulator_priv; 1545 struct dib7000p_state *st = demod->demodulator_priv;
1272 dibx000_exit_i2c_master(&st->i2c_master); 1546 dibx000_exit_i2c_master(&st->i2c_master);
1547 i2c_del_adapter(&st->dib7090_tuner_adap);
1273 kfree(st); 1548 kfree(st);
1274} 1549}
1275 1550
@@ -1277,8 +1552,8 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap)
1277{ 1552{
1278 u8 tx[2], rx[2]; 1553 u8 tx[2], rx[2];
1279 struct i2c_msg msg[2] = { 1554 struct i2c_msg msg[2] = {
1280 { .addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2 }, 1555 {.addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2},
1281 { .addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2 }, 1556 {.addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2},
1282 }; 1557 };
1283 1558
1284 tx[0] = 0x03; 1559 tx[0] = 0x03;
@@ -1303,7 +1578,7 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap)
1303} 1578}
1304EXPORT_SYMBOL(dib7000pc_detection); 1579EXPORT_SYMBOL(dib7000pc_detection);
1305 1580
1306struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating) 1581struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
1307{ 1582{
1308 struct dib7000p_state *st = demod->demodulator_priv; 1583 struct dib7000p_state *st = demod->demodulator_priv;
1309 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating); 1584 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
@@ -1312,19 +1587,19 @@ EXPORT_SYMBOL(dib7000p_get_i2c_master);
1312 1587
1313int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff) 1588int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1314{ 1589{
1315 struct dib7000p_state *state = fe->demodulator_priv; 1590 struct dib7000p_state *state = fe->demodulator_priv;
1316 u16 val = dib7000p_read_word(state, 235) & 0xffef; 1591 u16 val = dib7000p_read_word(state, 235) & 0xffef;
1317 val |= (onoff & 0x1) << 4; 1592 val |= (onoff & 0x1) << 4;
1318 dprintk("PID filter enabled %d", onoff); 1593 dprintk("PID filter enabled %d", onoff);
1319 return dib7000p_write_word(state, 235, val); 1594 return dib7000p_write_word(state, 235, val);
1320} 1595}
1321EXPORT_SYMBOL(dib7000p_pid_filter_ctrl); 1596EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
1322 1597
1323int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff) 1598int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1324{ 1599{
1325 struct dib7000p_state *state = fe->demodulator_priv; 1600 struct dib7000p_state *state = fe->demodulator_priv;
1326 dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff); 1601 dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
1327 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0); 1602 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
1328} 1603}
1329EXPORT_SYMBOL(dib7000p_pid_filter); 1604EXPORT_SYMBOL(dib7000p_pid_filter);
1330 1605
@@ -1340,16 +1615,19 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1340 1615
1341 dpst->i2c_adap = i2c; 1616 dpst->i2c_adap = i2c;
1342 1617
1343 for (k = no_of_demods-1; k >= 0; k--) { 1618 for (k = no_of_demods - 1; k >= 0; k--) {
1344 dpst->cfg = cfg[k]; 1619 dpst->cfg = cfg[k];
1345 1620
1346 /* designated i2c address */ 1621 /* designated i2c address */
1347 new_addr = (0x40 + k) << 1; 1622 if (cfg[k].default_i2c_addr != 0)
1623 new_addr = cfg[k].default_i2c_addr + (k << 1);
1624 else
1625 new_addr = (0x40 + k) << 1;
1348 dpst->i2c_addr = new_addr; 1626 dpst->i2c_addr = new_addr;
1349 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */ 1627 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
1350 if (dib7000p_identify(dpst) != 0) { 1628 if (dib7000p_identify(dpst) != 0) {
1351 dpst->i2c_addr = default_addr; 1629 dpst->i2c_addr = default_addr;
1352 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */ 1630 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
1353 if (dib7000p_identify(dpst) != 0) { 1631 if (dib7000p_identify(dpst) != 0) {
1354 dprintk("DiB7000P #%d: not identified\n", k); 1632 dprintk("DiB7000P #%d: not identified\n", k);
1355 kfree(dpst); 1633 kfree(dpst);
@@ -1368,7 +1646,10 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1368 1646
1369 for (k = 0; k < no_of_demods; k++) { 1647 for (k = 0; k < no_of_demods; k++) {
1370 dpst->cfg = cfg[k]; 1648 dpst->cfg = cfg[k];
1371 dpst->i2c_addr = (0x40 + k) << 1; 1649 if (cfg[k].default_i2c_addr != 0)
1650 dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
1651 else
1652 dpst->i2c_addr = (0x40 + k) << 1;
1372 1653
1373 // unforce divstr 1654 // unforce divstr
1374 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2); 1655 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
@@ -1382,8 +1663,613 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1382} 1663}
1383EXPORT_SYMBOL(dib7000p_i2c_enumeration); 1664EXPORT_SYMBOL(dib7000p_i2c_enumeration);
1384 1665
1666static const s32 lut_1000ln_mant[] = {
1667 6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
1668};
1669
1670static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
1671{
1672 struct dib7000p_state *state = fe->demodulator_priv;
1673 u32 tmp_val = 0, exp = 0, mant = 0;
1674 s32 pow_i;
1675 u16 buf[2];
1676 u8 ix = 0;
1677
1678 buf[0] = dib7000p_read_word(state, 0x184);
1679 buf[1] = dib7000p_read_word(state, 0x185);
1680 pow_i = (buf[0] << 16) | buf[1];
1681 dprintk("raw pow_i = %d", pow_i);
1682
1683 tmp_val = pow_i;
1684 while (tmp_val >>= 1)
1685 exp++;
1686
1687 mant = (pow_i * 1000 / (1 << exp));
1688 dprintk(" mant = %d exp = %d", mant / 1000, exp);
1689
1690 ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
1691 dprintk(" ix = %d", ix);
1692
1693 pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
1694 pow_i = (pow_i << 8) / 1000;
1695 dprintk(" pow_i = %d", pow_i);
1696
1697 return pow_i;
1698}
1699
1700static int map_addr_to_serpar_number(struct i2c_msg *msg)
1701{
1702 if ((msg->buf[0] <= 15))
1703 msg->buf[0] -= 1;
1704 else if (msg->buf[0] == 17)
1705 msg->buf[0] = 15;
1706 else if (msg->buf[0] == 16)
1707 msg->buf[0] = 17;
1708 else if (msg->buf[0] == 19)
1709 msg->buf[0] = 16;
1710 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1711 msg->buf[0] -= 3;
1712 else if (msg->buf[0] == 28)
1713 msg->buf[0] = 23;
1714 else
1715 return -EINVAL;
1716 return 0;
1717}
1718
1719static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1720{
1721 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1722 u8 n_overflow = 1;
1723 u16 i = 1000;
1724 u16 serpar_num = msg[0].buf[0];
1725
1726 while (n_overflow == 1 && i) {
1727 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
1728 i--;
1729 if (i == 0)
1730 dprintk("Tuner ITF: write busy (overflow)");
1731 }
1732 dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1733 dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1734
1735 return num;
1736}
1737
1738static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1739{
1740 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1741 u8 n_overflow = 1, n_empty = 1;
1742 u16 i = 1000;
1743 u16 serpar_num = msg[0].buf[0];
1744 u16 read_word;
1745
1746 while (n_overflow == 1 && i) {
1747 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
1748 i--;
1749 if (i == 0)
1750 dprintk("TunerITF: read busy (overflow)");
1751 }
1752 dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
1753
1754 i = 1000;
1755 while (n_empty == 1 && i) {
1756 n_empty = dib7000p_read_word(state, 1984) & 0x1;
1757 i--;
1758 if (i == 0)
1759 dprintk("TunerITF: read busy (empty)");
1760 }
1761 read_word = dib7000p_read_word(state, 1987);
1762 msg[1].buf[0] = (read_word >> 8) & 0xff;
1763 msg[1].buf[1] = (read_word) & 0xff;
1764
1765 return num;
1766}
1767
1768static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1769{
1770 if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
1771 if (num == 1) { /* write */
1772 return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
1773 } else { /* read */
1774 return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
1775 }
1776 }
1777 return num;
1778}
1779
1780int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num, u16 apb_address)
1781{
1782 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1783 u16 word;
1784
1785 if (num == 1) { /* write */
1786 dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1787 } else {
1788 word = dib7000p_read_word(state, apb_address);
1789 msg[1].buf[0] = (word >> 8) & 0xff;
1790 msg[1].buf[1] = (word) & 0xff;
1791 }
1792
1793 return num;
1794}
1795
1796static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1797{
1798 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1799
1800 u16 apb_address = 0, word;
1801 int i = 0;
1802 switch (msg[0].buf[0]) {
1803 case 0x12:
1804 apb_address = 1920;
1805 break;
1806 case 0x14:
1807 apb_address = 1921;
1808 break;
1809 case 0x24:
1810 apb_address = 1922;
1811 break;
1812 case 0x1a:
1813 apb_address = 1923;
1814 break;
1815 case 0x22:
1816 apb_address = 1924;
1817 break;
1818 case 0x33:
1819 apb_address = 1926;
1820 break;
1821 case 0x34:
1822 apb_address = 1927;
1823 break;
1824 case 0x35:
1825 apb_address = 1928;
1826 break;
1827 case 0x36:
1828 apb_address = 1929;
1829 break;
1830 case 0x37:
1831 apb_address = 1930;
1832 break;
1833 case 0x38:
1834 apb_address = 1931;
1835 break;
1836 case 0x39:
1837 apb_address = 1932;
1838 break;
1839 case 0x2a:
1840 apb_address = 1935;
1841 break;
1842 case 0x2b:
1843 apb_address = 1936;
1844 break;
1845 case 0x2c:
1846 apb_address = 1937;
1847 break;
1848 case 0x2d:
1849 apb_address = 1938;
1850 break;
1851 case 0x2e:
1852 apb_address = 1939;
1853 break;
1854 case 0x2f:
1855 apb_address = 1940;
1856 break;
1857 case 0x30:
1858 apb_address = 1941;
1859 break;
1860 case 0x31:
1861 apb_address = 1942;
1862 break;
1863 case 0x32:
1864 apb_address = 1943;
1865 break;
1866 case 0x3e:
1867 apb_address = 1944;
1868 break;
1869 case 0x3f:
1870 apb_address = 1945;
1871 break;
1872 case 0x40:
1873 apb_address = 1948;
1874 break;
1875 case 0x25:
1876 apb_address = 914;
1877 break;
1878 case 0x26:
1879 apb_address = 915;
1880 break;
1881 case 0x27:
1882 apb_address = 916;
1883 break;
1884 case 0x28:
1885 apb_address = 917;
1886 break;
1887 case 0x1d:
1888 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
1889 word = dib7000p_read_word(state, 384 + i);
1890 msg[1].buf[0] = (word >> 8) & 0xff;
1891 msg[1].buf[1] = (word) & 0xff;
1892 return num;
1893 case 0x1f:
1894 if (num == 1) { /* write */
1895 word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
1896 word &= 0x3;
1897 word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
1898 dib7000p_write_word(state, 72, word); /* Set the proper input */
1899 return num;
1900 }
1901 }
1902
1903 if (apb_address != 0) /* R/W acces via APB */
1904 return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
1905 else /* R/W access via SERPAR */
1906 return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
1907
1908 return 0;
1909}
1910
1911static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
1912{
1913 return I2C_FUNC_I2C;
1914}
1915
1916static struct i2c_algorithm dib7090_tuner_xfer_algo = {
1917 .master_xfer = dib7090_tuner_xfer,
1918 .functionality = dib7000p_i2c_func,
1919};
1920
1921struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
1922{
1923 struct dib7000p_state *st = fe->demodulator_priv;
1924 return &st->dib7090_tuner_adap;
1925}
1926EXPORT_SYMBOL(dib7090_get_i2c_tuner);
1927
1928static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
1929{
1930 u16 reg;
1931
1932 /* drive host bus 2, 3, 4 */
1933 reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1934 reg |= (drive << 12) | (drive << 6) | drive;
1935 dib7000p_write_word(state, 1798, reg);
1936
1937 /* drive host bus 5,6 */
1938 reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1939 reg |= (drive << 8) | (drive << 2);
1940 dib7000p_write_word(state, 1799, reg);
1941
1942 /* drive host bus 7, 8, 9 */
1943 reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1944 reg |= (drive << 12) | (drive << 6) | drive;
1945 dib7000p_write_word(state, 1800, reg);
1946
1947 /* drive host bus 10, 11 */
1948 reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1949 reg |= (drive << 8) | (drive << 2);
1950 dib7000p_write_word(state, 1801, reg);
1951
1952 /* drive host bus 12, 13, 14 */
1953 reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1954 reg |= (drive << 12) | (drive << 6) | drive;
1955 dib7000p_write_word(state, 1802, reg);
1956
1957 return 0;
1958}
1959
1960static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
1961{
1962 u32 quantif = 3;
1963 u32 nom = (insertExtSynchro * P_Kin + syncSize);
1964 u32 denom = P_Kout;
1965 u32 syncFreq = ((nom << quantif) / denom);
1966
1967 if ((syncFreq & ((1 << quantif) - 1)) != 0)
1968 syncFreq = (syncFreq >> quantif) + 1;
1969 else
1970 syncFreq = (syncFreq >> quantif);
1971
1972 if (syncFreq != 0)
1973 syncFreq = syncFreq - 1;
1974
1975 return syncFreq;
1976}
1977
1978static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
1979{
1980 u8 index_buf;
1981 u16 rx_copy_buf[22];
1982
1983 dprintk("Configure DibStream Tx");
1984 for (index_buf = 0; index_buf < 22; index_buf++)
1985 rx_copy_buf[index_buf] = dib7000p_read_word(state, 1536+index_buf);
1986
1987 dib7000p_write_word(state, 1615, 1);
1988 dib7000p_write_word(state, 1603, P_Kin);
1989 dib7000p_write_word(state, 1605, P_Kout);
1990 dib7000p_write_word(state, 1606, insertExtSynchro);
1991 dib7000p_write_word(state, 1608, synchroMode);
1992 dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1993 dib7000p_write_word(state, 1610, syncWord & 0xffff);
1994 dib7000p_write_word(state, 1612, syncSize);
1995 dib7000p_write_word(state, 1615, 0);
1996
1997 for (index_buf = 0; index_buf < 22; index_buf++)
1998 dib7000p_write_word(state, 1536+index_buf, rx_copy_buf[index_buf]);
1999
2000 return 0;
2001}
2002
2003static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
2004 u32 dataOutRate)
2005{
2006 u32 syncFreq;
2007
2008 dprintk("Configure DibStream Rx");
2009 if ((P_Kin != 0) && (P_Kout != 0)) {
2010 syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
2011 dib7000p_write_word(state, 1542, syncFreq);
2012 }
2013 dib7000p_write_word(state, 1554, 1);
2014 dib7000p_write_word(state, 1536, P_Kin);
2015 dib7000p_write_word(state, 1537, P_Kout);
2016 dib7000p_write_word(state, 1539, synchroMode);
2017 dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
2018 dib7000p_write_word(state, 1541, syncWord & 0xffff);
2019 dib7000p_write_word(state, 1543, syncSize);
2020 dib7000p_write_word(state, 1544, dataOutRate);
2021 dib7000p_write_word(state, 1554, 0);
2022
2023 return 0;
2024}
2025
2026static int dib7090_enDivOnHostBus(struct dib7000p_state *state)
2027{
2028 u16 reg;
2029
2030 dprintk("Enable Diversity on host bus");
2031 reg = (1 << 8) | (1 << 5);
2032 dib7000p_write_word(state, 1288, reg);
2033
2034 return dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2035}
2036
2037static int dib7090_enAdcOnHostBus(struct dib7000p_state *state)
2038{
2039 u16 reg;
2040
2041 dprintk("Enable ADC on host bus");
2042 reg = (1 << 7) | (1 << 5);
2043 dib7000p_write_word(state, 1288, reg);
2044
2045 return dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2046}
2047
2048static int dib7090_enMpegOnHostBus(struct dib7000p_state *state)
2049{
2050 u16 reg;
2051
2052 dprintk("Enable Mpeg on host bus");
2053 reg = (1 << 9) | (1 << 5);
2054 dib7000p_write_word(state, 1288, reg);
2055
2056 return dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
2057}
2058
2059static int dib7090_enMpegInput(struct dib7000p_state *state)
2060{
2061 dprintk("Enable Mpeg input");
2062 return dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
2063}
2064
2065static int dib7090_enMpegMux(struct dib7000p_state *state, u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
2066{
2067 u16 reg = (1 << 7) | ((pulseWidth & 0x1f) << 2) | ((enSerialMode & 0x1) << 1) | (enSerialClkDiv2 & 0x1);
2068
2069 dprintk("Enable Mpeg mux");
2070 dib7000p_write_word(state, 1287, reg);
2071
2072 reg &= ~(1 << 7);
2073 dib7000p_write_word(state, 1287, reg);
2074
2075 reg = (1 << 4);
2076 dib7000p_write_word(state, 1288, reg);
2077
2078 return 0;
2079}
2080
2081static int dib7090_disableMpegMux(struct dib7000p_state *state)
2082{
2083 u16 reg;
2084
2085 dprintk("Disable Mpeg mux");
2086 dib7000p_write_word(state, 1288, 0);
2087
2088 reg = dib7000p_read_word(state, 1287);
2089 reg &= ~(1 << 7);
2090 dib7000p_write_word(state, 1287, reg);
2091
2092 return 0;
2093}
2094
2095static int dib7090_set_input_mode(struct dvb_frontend *fe, int mode)
2096{
2097 struct dib7000p_state *state = fe->demodulator_priv;
2098
2099 switch (mode) {
2100 case INPUT_MODE_DIVERSITY:
2101 dprintk("Enable diversity INPUT");
2102 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
2103 break;
2104 case INPUT_MODE_MPEG:
2105 dprintk("Enable Mpeg INPUT");
2106 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
2107 break;
2108 case INPUT_MODE_OFF:
2109 default:
2110 dprintk("Disable INPUT");
2111 dib7090_cfg_DibRx(state, 0, 0, 0, 0, 0, 0, 0);
2112 break;
2113 }
2114 return 0;
2115}
2116
2117static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
2118{
2119 switch (onoff) {
2120 case 0: /* only use the internal way - not the diversity input */
2121 dib7090_set_input_mode(fe, INPUT_MODE_MPEG);
2122 break;
2123 case 1: /* both ways */
2124 case 2: /* only the diversity input */
2125 dib7090_set_input_mode(fe, INPUT_MODE_DIVERSITY);
2126 break;
2127 }
2128
2129 return 0;
2130}
2131
2132static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
2133{
2134 struct dib7000p_state *state = fe->demodulator_priv;
2135
2136 u16 outreg, smo_mode, fifo_threshold;
2137 u8 prefer_mpeg_mux_use = 1;
2138 int ret = 0;
2139
2140 dib7090_host_bus_drive(state, 1);
2141
2142 fifo_threshold = 1792;
2143 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
2144 outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
2145
2146 switch (mode) {
2147 case OUTMODE_HIGH_Z:
2148 outreg = 0;
2149 break;
2150
2151 case OUTMODE_MPEG2_SERIAL:
2152 if (prefer_mpeg_mux_use) {
2153 dprintk("Sip 7090P setting output mode TS_SERIAL using Mpeg Mux");
2154 dib7090_enMpegOnHostBus(state);
2155 dib7090_enMpegInput(state);
2156 if (state->cfg.enMpegOutput == 1)
2157 dib7090_enMpegMux(state, 3, 1, 1);
2158
2159 } else { /* Use Smooth block */
2160 dprintk("Sip 7090P setting output mode TS_SERIAL using Smooth bloc");
2161 dib7090_disableMpegMux(state);
2162 dib7000p_write_word(state, 1288, (1 << 6));
2163 outreg |= (2 << 6) | (0 << 1);
2164 }
2165 break;
2166
2167 case OUTMODE_MPEG2_PAR_GATED_CLK:
2168 if (prefer_mpeg_mux_use) {
2169 dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
2170 dib7090_enMpegOnHostBus(state);
2171 dib7090_enMpegInput(state);
2172 if (state->cfg.enMpegOutput == 1)
2173 dib7090_enMpegMux(state, 2, 0, 0);
2174 } else { /* Use Smooth block */
2175 dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Smooth block");
2176 dib7090_disableMpegMux(state);
2177 dib7000p_write_word(state, 1288, (1 << 6));
2178 outreg |= (0 << 6);
2179 }
2180 break;
2181
2182 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
2183 dprintk("Sip 7090P setting output mode TS_PARALLEL_CONT using Smooth block");
2184 dib7090_disableMpegMux(state);
2185 dib7000p_write_word(state, 1288, (1 << 6));
2186 outreg |= (1 << 6);
2187 break;
2188
2189 case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
2190 dprintk("Sip 7090P setting output mode TS_FIFO using Smooth block");
2191 dib7090_disableMpegMux(state);
2192 dib7000p_write_word(state, 1288, (1 << 6));
2193 outreg |= (5 << 6);
2194 smo_mode |= (3 << 1);
2195 fifo_threshold = 512;
2196 break;
2197
2198 case OUTMODE_DIVERSITY:
2199 dprintk("Sip 7090P setting output mode MODE_DIVERSITY");
2200 dib7090_disableMpegMux(state);
2201 dib7090_enDivOnHostBus(state);
2202 break;
2203
2204 case OUTMODE_ANALOG_ADC:
2205 dprintk("Sip 7090P setting output mode MODE_ANALOG_ADC");
2206 dib7090_enAdcOnHostBus(state);
2207 break;
2208 }
2209
2210 if (state->cfg.output_mpeg2_in_188_bytes)
2211 smo_mode |= (1 << 5);
2212
2213 ret |= dib7000p_write_word(state, 235, smo_mode);
2214 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
2215 ret |= dib7000p_write_word(state, 1286, outreg | (1 << 10)); /* allways set Dout active = 1 !!! */
2216
2217 return ret;
2218}
2219
2220int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
2221{
2222 struct dib7000p_state *state = fe->demodulator_priv;
2223 u16 en_cur_state;
2224
2225 dprintk("sleep dib7090: %d", onoff);
2226
2227 en_cur_state = dib7000p_read_word(state, 1922);
2228
2229 if (en_cur_state > 0xff)
2230 state->tuner_enable = en_cur_state;
2231
2232 if (onoff)
2233 en_cur_state &= 0x00ff;
2234 else {
2235 if (state->tuner_enable != 0)
2236 en_cur_state = state->tuner_enable;
2237 }
2238
2239 dib7000p_write_word(state, 1922, en_cur_state);
2240
2241 return 0;
2242}
2243EXPORT_SYMBOL(dib7090_tuner_sleep);
2244
2245int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
2246{
2247 dprintk("AGC restart callback: %d", restart);
2248 return 0;
2249}
2250EXPORT_SYMBOL(dib7090_agc_restart);
2251
2252int dib7090_get_adc_power(struct dvb_frontend *fe)
2253{
2254 return dib7000p_get_adc_power(fe);
2255}
2256EXPORT_SYMBOL(dib7090_get_adc_power);
2257
2258int dib7090_slave_reset(struct dvb_frontend *fe)
2259{
2260 struct dib7000p_state *state = fe->demodulator_priv;
2261 u16 reg;
2262
2263 reg = dib7000p_read_word(state, 1794);
2264 dib7000p_write_word(state, 1794, reg | (4 << 12));
2265
2266 dib7000p_write_word(state, 1032, 0xffff);
2267 return 0;
2268}
2269EXPORT_SYMBOL(dib7090_slave_reset);
2270
1385static struct dvb_frontend_ops dib7000p_ops; 2271static struct dvb_frontend_ops dib7000p_ops;
1386struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg) 2272struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
1387{ 2273{
1388 struct dvb_frontend *demod; 2274 struct dvb_frontend *demod;
1389 struct dib7000p_state *st; 2275 struct dib7000p_state *st;
@@ -1400,28 +2286,41 @@ struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
1400 /* Ensure the output mode remains at the previous default if it's 2286 /* Ensure the output mode remains at the previous default if it's
1401 * not specifically set by the caller. 2287 * not specifically set by the caller.
1402 */ 2288 */
1403 if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && 2289 if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
1404 (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
1405 st->cfg.output_mode = OUTMODE_MPEG2_FIFO; 2290 st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
1406 2291
1407 demod = &st->demod; 2292 demod = &st->demod;
1408 demod->demodulator_priv = st; 2293 demod->demodulator_priv = st;
1409 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops)); 2294 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
1410 2295
1411 dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */ 2296 dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
1412 2297
1413 if (dib7000p_identify(st) != 0) 2298 if (dib7000p_identify(st) != 0)
1414 goto error; 2299 goto error;
1415 2300
2301 st->version = dib7000p_read_word(st, 897);
2302
1416 /* FIXME: make sure the dev.parent field is initialized, or else 2303 /* FIXME: make sure the dev.parent field is initialized, or else
1417 request_firmware() will hit an OOPS (this should be moved somewhere 2304 request_firmware() will hit an OOPS (this should be moved somewhere
1418 more common) */ 2305 more common) */
1419 st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
1420 2306
1421 dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr); 2307 dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
1422 2308
2309 /* init 7090 tuner adapter */
2310 strncpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface", sizeof(st->dib7090_tuner_adap.name));
2311 st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
2312 st->dib7090_tuner_adap.algo_data = NULL;
2313 st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
2314 i2c_set_adapdata(&st->dib7090_tuner_adap, st);
2315 i2c_add_adapter(&st->dib7090_tuner_adap);
2316
1423 dib7000p_demod_reset(st); 2317 dib7000p_demod_reset(st);
1424 2318
2319 if (st->version == SOC7090) {
2320 dib7090_set_output_mode(demod, st->cfg.output_mode);
2321 dib7090_set_diversity_in(demod, 0);
2322 }
2323
1425 return demod; 2324 return demod;
1426 2325
1427error: 2326error:
@@ -1432,37 +2331,35 @@ EXPORT_SYMBOL(dib7000p_attach);
1432 2331
1433static struct dvb_frontend_ops dib7000p_ops = { 2332static struct dvb_frontend_ops dib7000p_ops = {
1434 .info = { 2333 .info = {
1435 .name = "DiBcom 7000PC", 2334 .name = "DiBcom 7000PC",
1436 .type = FE_OFDM, 2335 .type = FE_OFDM,
1437 .frequency_min = 44250000, 2336 .frequency_min = 44250000,
1438 .frequency_max = 867250000, 2337 .frequency_max = 867250000,
1439 .frequency_stepsize = 62500, 2338 .frequency_stepsize = 62500,
1440 .caps = FE_CAN_INVERSION_AUTO | 2339 .caps = FE_CAN_INVERSION_AUTO |
1441 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 2340 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1442 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 2341 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1443 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 2342 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1444 FE_CAN_TRANSMISSION_MODE_AUTO | 2343 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
1445 FE_CAN_GUARD_INTERVAL_AUTO | 2344 },
1446 FE_CAN_RECOVER | 2345
1447 FE_CAN_HIERARCHY_AUTO, 2346 .release = dib7000p_release,
1448 }, 2347
1449 2348 .init = dib7000p_wakeup,
1450 .release = dib7000p_release, 2349 .sleep = dib7000p_sleep,
1451 2350
1452 .init = dib7000p_wakeup, 2351 .set_frontend = dib7000p_set_frontend,
1453 .sleep = dib7000p_sleep, 2352 .get_tune_settings = dib7000p_fe_get_tune_settings,
1454 2353 .get_frontend = dib7000p_get_frontend,
1455 .set_frontend = dib7000p_set_frontend, 2354
1456 .get_tune_settings = dib7000p_fe_get_tune_settings, 2355 .read_status = dib7000p_read_status,
1457 .get_frontend = dib7000p_get_frontend, 2356 .read_ber = dib7000p_read_ber,
1458
1459 .read_status = dib7000p_read_status,
1460 .read_ber = dib7000p_read_ber,
1461 .read_signal_strength = dib7000p_read_signal_strength, 2357 .read_signal_strength = dib7000p_read_signal_strength,
1462 .read_snr = dib7000p_read_snr, 2358 .read_snr = dib7000p_read_snr,
1463 .read_ucblocks = dib7000p_read_unc_blocks, 2359 .read_ucblocks = dib7000p_read_unc_blocks,
1464}; 2360};
1465 2361
2362MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
1466MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); 2363MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
1467MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator"); 2364MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
1468MODULE_LICENSE("GPL"); 2365MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
index da17345bf5bd..0179f9474bac 100644
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ b/drivers/media/dvb/frontends/dib7000p.h
@@ -33,59 +33,54 @@ struct dib7000p_config {
33 int (*agc_control) (struct dvb_frontend *, u8 before); 33 int (*agc_control) (struct dvb_frontend *, u8 before);
34 34
35 u8 output_mode; 35 u8 output_mode;
36 u8 disable_sample_and_hold : 1; 36 u8 disable_sample_and_hold:1;
37 37
38 u8 enable_current_mirror : 1; 38 u8 enable_current_mirror:1;
39 u8 diversity_delay; 39 u16 diversity_delay;
40 40
41 u8 default_i2c_addr;
42 u8 enMpegOutput:1;
41}; 43};
42 44
43#define DEFAULT_DIB7000P_I2C_ADDRESS 18 45#define DEFAULT_DIB7000P_I2C_ADDRESS 18
44 46
45#if defined(CONFIG_DVB_DIB7000P) || (defined(CONFIG_DVB_DIB7000P_MODULE) && \ 47#if defined(CONFIG_DVB_DIB7000P) || (defined(CONFIG_DVB_DIB7000P_MODULE) && \
46 defined(MODULE)) 48 defined(MODULE))
47extern struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, 49extern struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg);
48 u8 i2c_addr, 50extern struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *, enum dibx000_i2c_interface, int);
49 struct dib7000p_config *cfg); 51extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[]);
50extern struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *,
51 enum dibx000_i2c_interface,
52 int);
53extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c,
54 int no_of_demods, u8 default_addr,
55 struct dib7000p_config cfg[]);
56extern int dib7000p_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val); 52extern int dib7000p_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
57extern int dib7000p_set_wbd_ref(struct dvb_frontend *, u16 value); 53extern int dib7000p_set_wbd_ref(struct dvb_frontend *, u16 value);
58extern int dib7000pc_detection(struct i2c_adapter *i2c_adap); 54extern int dib7000pc_detection(struct i2c_adapter *i2c_adap);
59extern int dib7000p_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff); 55extern int dib7000p_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
60extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff); 56extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
57extern int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw);
58extern u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf);
59extern int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart);
60extern int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff);
61extern int dib7090_get_adc_power(struct dvb_frontend *fe);
62extern struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe);
63extern int dib7090_slave_reset(struct dvb_frontend *fe);
61#else 64#else
62static inline 65static inline struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
63struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
64 struct dib7000p_config *cfg)
65{ 66{
66 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 67 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
67 return NULL; 68 return NULL;
68} 69}
69 70
70static inline 71static inline struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface i, int x)
71struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *fe,
72 enum dibx000_i2c_interface i,
73 int x)
74{ 72{
75 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 73 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
76 return NULL; 74 return NULL;
77} 75}
78 76
79static inline int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, 77static inline int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
80 int no_of_demods, u8 default_addr,
81 struct dib7000p_config cfg[])
82{ 78{
83 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 79 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
84 return -ENODEV; 80 return -ENODEV;
85} 81}
86 82
87static inline int dib7000p_set_gpio(struct dvb_frontend *fe, 83static inline int dib7000p_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
88 u8 num, u8 dir, u8 val)
89{ 84{
90 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 85 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
91 return -ENODEV; 86 return -ENODEV;
@@ -102,16 +97,59 @@ static inline int dib7000pc_detection(struct i2c_adapter *i2c_adap)
102 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 97 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
103 return -ENODEV; 98 return -ENODEV;
104} 99}
100
105static inline int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff) 101static inline int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
106{ 102{
107 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 103 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
108 return -ENODEV; 104 return -ENODEV;
109} 105}
110 106
111static inline int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, uint8_t onoff) 107static inline int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, uint8_t onoff)
112{ 108{
113 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 109 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
114 return -ENODEV; 110 return -ENODEV;
111}
112
113static inline int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
114{
115 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
116 return -ENODEV;
117}
118
119static inline u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
120{
121 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
122 return 0;
123}
124
125static inline int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
126{
127 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
128 return -ENODEV;
129}
130
131static inline int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
132{
133 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
134 return -ENODEV;
135}
136
137static inline int dib7090_get_adc_power(struct dvb_frontend *fe)
138{
139 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
140 return -ENODEV;
141}
142
143static inline struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
144{
145 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
146 return NULL;
147}
148
149static inline int dib7090_slave_reset(struct dvb_frontend *fe)
150{
151 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
152 return -ENODEV;
115} 153}
116#endif 154#endif
117 155
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
index df17b91b3250..c1c3e26906e2 100644
--- a/drivers/media/dvb/frontends/dib8000.c
+++ b/drivers/media/dvb/frontends/dib8000.c
@@ -22,6 +22,7 @@
22#define LAYER_C 3 22#define LAYER_C 3
23 23
24#define FE_CALLBACK_TIME_NEVER 0xffffffff 24#define FE_CALLBACK_TIME_NEVER 0xffffffff
25#define MAX_NUMBER_OF_FRONTENDS 6
25 26
26static int debug; 27static int debug;
27module_param(debug, int, 0644); 28module_param(debug, int, 0644);
@@ -37,7 +38,6 @@ struct i2c_device {
37}; 38};
38 39
39struct dib8000_state { 40struct dib8000_state {
40 struct dvb_frontend fe;
41 struct dib8000_config cfg; 41 struct dib8000_config cfg;
42 42
43 struct i2c_device i2c; 43 struct i2c_device i2c;
@@ -68,6 +68,8 @@ struct dib8000_state {
68 u8 isdbt_cfg_loaded; 68 u8 isdbt_cfg_loaded;
69 enum frontend_tune_state tune_state; 69 enum frontend_tune_state tune_state;
70 u32 status; 70 u32 status;
71
72 struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
71}; 73};
72 74
73enum dib8000_power_mode { 75enum dib8000_power_mode {
@@ -122,111 +124,111 @@ static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
122 return dib8000_i2c_write16(&state->i2c, reg, val); 124 return dib8000_i2c_write16(&state->i2c, reg, val);
123} 125}
124 126
125static const int16_t coeff_2k_sb_1seg_dqpsk[8] = { 127static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
126 (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c, 128 (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
127 (920 << 5) | 0x09 129 (920 << 5) | 0x09
128}; 130};
129 131
130static const int16_t coeff_2k_sb_1seg[8] = { 132static const s16 coeff_2k_sb_1seg[8] = {
131 (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f 133 (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
132}; 134};
133 135
134static const int16_t coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = { 136static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
135 (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11, 137 (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
136 (-931 << 5) | 0x0f 138 (-931 << 5) | 0x0f
137}; 139};
138 140
139static const int16_t coeff_2k_sb_3seg_0dqpsk[8] = { 141static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
140 (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e, 142 (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
141 (982 << 5) | 0x0c 143 (982 << 5) | 0x0c
142}; 144};
143 145
144static const int16_t coeff_2k_sb_3seg_1dqpsk[8] = { 146static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
145 (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12, 147 (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
146 (-720 << 5) | 0x0d 148 (-720 << 5) | 0x0d
147}; 149};
148 150
149static const int16_t coeff_2k_sb_3seg[8] = { 151static const s16 coeff_2k_sb_3seg[8] = {
150 (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e, 152 (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
151 (-610 << 5) | 0x0a 153 (-610 << 5) | 0x0a
152}; 154};
153 155
154static const int16_t coeff_4k_sb_1seg_dqpsk[8] = { 156static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
155 (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f, 157 (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
156 (-922 << 5) | 0x0d 158 (-922 << 5) | 0x0d
157}; 159};
158 160
159static const int16_t coeff_4k_sb_1seg[8] = { 161static const s16 coeff_4k_sb_1seg[8] = {
160 (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d, 162 (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
161 (-655 << 5) | 0x0a 163 (-655 << 5) | 0x0a
162}; 164};
163 165
164static const int16_t coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = { 166static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
165 (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14, 167 (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
166 (-958 << 5) | 0x13 168 (-958 << 5) | 0x13
167}; 169};
168 170
169static const int16_t coeff_4k_sb_3seg_0dqpsk[8] = { 171static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
170 (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12, 172 (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
171 (-568 << 5) | 0x0f 173 (-568 << 5) | 0x0f
172}; 174};
173 175
174static const int16_t coeff_4k_sb_3seg_1dqpsk[8] = { 176static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
175 (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14, 177 (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
176 (-848 << 5) | 0x13 178 (-848 << 5) | 0x13
177}; 179};
178 180
179static const int16_t coeff_4k_sb_3seg[8] = { 181static const s16 coeff_4k_sb_3seg[8] = {
180 (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12, 182 (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
181 (-869 << 5) | 0x13 183 (-869 << 5) | 0x13
182}; 184};
183 185
184static const int16_t coeff_8k_sb_1seg_dqpsk[8] = { 186static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
185 (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13, 187 (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
186 (-598 << 5) | 0x10 188 (-598 << 5) | 0x10
187}; 189};
188 190
189static const int16_t coeff_8k_sb_1seg[8] = { 191static const s16 coeff_8k_sb_1seg[8] = {
190 (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f, 192 (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
191 (585 << 5) | 0x0f 193 (585 << 5) | 0x0f
192}; 194};
193 195
194static const int16_t coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = { 196static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
195 (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18, 197 (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
196 (0 << 5) | 0x14 198 (0 << 5) | 0x14
197}; 199};
198 200
199static const int16_t coeff_8k_sb_3seg_0dqpsk[8] = { 201static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
200 (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15, 202 (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
201 (-877 << 5) | 0x15 203 (-877 << 5) | 0x15
202}; 204};
203 205
204static const int16_t coeff_8k_sb_3seg_1dqpsk[8] = { 206static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
205 (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18, 207 (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
206 (-921 << 5) | 0x14 208 (-921 << 5) | 0x14
207}; 209};
208 210
209static const int16_t coeff_8k_sb_3seg[8] = { 211static const s16 coeff_8k_sb_3seg[8] = {
210 (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15, 212 (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
211 (690 << 5) | 0x14 213 (690 << 5) | 0x14
212}; 214};
213 215
214static const int16_t ana_fe_coeff_3seg[24] = { 216static const s16 ana_fe_coeff_3seg[24] = {
215 81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017 217 81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
216}; 218};
217 219
218static const int16_t ana_fe_coeff_1seg[24] = { 220static const s16 ana_fe_coeff_1seg[24] = {
219 249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003 221 249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
220}; 222};
221 223
222static const int16_t ana_fe_coeff_13seg[24] = { 224static const s16 ana_fe_coeff_13seg[24] = {
223 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1 225 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
224}; 226};
225 227
226static u16 fft_to_mode(struct dib8000_state *state) 228static u16 fft_to_mode(struct dib8000_state *state)
227{ 229{
228 u16 mode; 230 u16 mode;
229 switch (state->fe.dtv_property_cache.transmission_mode) { 231 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
230 case TRANSMISSION_MODE_2K: 232 case TRANSMISSION_MODE_2K:
231 mode = 1; 233 mode = 1;
232 break; 234 break;
@@ -249,16 +251,18 @@ static void dib8000_set_acquisition_mode(struct dib8000_state *state)
249 dprintk("acquisition mode activated"); 251 dprintk("acquisition mode activated");
250 dib8000_write_word(state, 298, nud); 252 dib8000_write_word(state, 298, nud);
251} 253}
252 254static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
253static int dib8000_set_output_mode(struct dib8000_state *state, int mode)
254{ 255{
256 struct dib8000_state *state = fe->demodulator_priv;
257
255 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */ 258 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */
256 259
257 outreg = 0; 260 outreg = 0;
258 fifo_threshold = 1792; 261 fifo_threshold = 1792;
259 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); 262 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
260 263
261 dprintk("-I- Setting output mode for demod %p to %d", &state->fe, mode); 264 dprintk("-I- Setting output mode for demod %p to %d",
265 &state->fe[0], mode);
262 266
263 switch (mode) { 267 switch (mode) {
264 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock 268 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
@@ -292,7 +296,8 @@ static int dib8000_set_output_mode(struct dib8000_state *state, int mode)
292 break; 296 break;
293 297
294 default: 298 default:
295 dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe); 299 dprintk("Unhandled output_mode passed to be set for demod %p",
300 &state->fe[0]);
296 return -EINVAL; 301 return -EINVAL;
297 } 302 }
298 303
@@ -342,7 +347,8 @@ static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_pow
342{ 347{
343 /* by default everything is going to be powered off */ 348 /* by default everything is going to be powered off */
344 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff, 349 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
345 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; 350 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
351 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
346 352
347 /* now, depending on the requested mode, we power on */ 353 /* now, depending on the requested mode, we power on */
348 switch (mode) { 354 switch (mode) {
@@ -411,8 +417,9 @@ static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_s
411 return ret; 417 return ret;
412} 418}
413 419
414static int dib8000_set_bandwidth(struct dib8000_state *state, u32 bw) 420static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
415{ 421{
422 struct dib8000_state *state = fe->demodulator_priv;
416 u32 timf; 423 u32 timf;
417 424
418 if (bw == 0) 425 if (bw == 0)
@@ -478,7 +485,8 @@ static void dib8000_reset_pll(struct dib8000_state *state)
478 485
479 // clk_cfg1 486 // clk_cfg1
480 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | 487 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
481 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | (pll->pll_range << 1) | (pll->pll_reset << 0); 488 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) |
489 (pll->pll_range << 1) | (pll->pll_reset << 0);
482 490
483 dib8000_write_word(state, 902, clk_cfg1); 491 dib8000_write_word(state, 902, clk_cfg1);
484 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); 492 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
@@ -488,11 +496,12 @@ static void dib8000_reset_pll(struct dib8000_state *state)
488 496
489 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */ 497 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
490 if (state->cfg.pll->ADClkSrc == 0) 498 if (state->cfg.pll->ADClkSrc == 0)
491 dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); 499 dib8000_write_word(state, 904, (0 << 15) | (0 << 12) | (0 << 10) |
500 (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
492 else if (state->cfg.refclksel != 0) 501 else if (state->cfg.refclksel != 0)
493 dib8000_write_word(state, 904, 502 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
494 (0 << 15) | (1 << 12) | ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) | (pll-> 503 ((state->cfg.refclksel & 0x3) << 10) | (pll->modulo << 8) |
495 ADClkSrc << 7) | (0 << 1)); 504 (pll->ADClkSrc << 7) | (0 << 1));
496 else 505 else
497 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1)); 506 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | (3 << 10) | (pll->modulo << 8) | (pll->ADClkSrc << 7) | (0 << 1));
498 507
@@ -560,7 +569,7 @@ static const u16 dib8000_defaults[] = {
560 0xd4c0, 569 0xd4c0,
561 570
562 /*1, 32, 571 /*1, 32,
563 0x6680 // P_corm_thres Lock algorithms configuration */ 572 0x6680 // P_corm_thres Lock algorithms configuration */
564 573
565 11, 80, /* set ADC level to -16 */ 574 11, 80, /* set ADC level to -16 */
566 (1 << 13) - 825 - 117, 575 (1 << 13) - 825 - 117,
@@ -623,14 +632,14 @@ static const u16 dib8000_defaults[] = {
623 1, 285, 632 1, 285,
624 0x0020, //p_fec_ 633 0x0020, //p_fec_
625 1, 299, 634 1, 299,
626 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard 635 0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
627 636
628 1, 338, 637 1, 338,
629 (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1 638 (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1
630 (1 << 10) | // P_ctrl_pre_freq_mode_sat=1 639 (1 << 10) |
631 (0 << 9) | // P_ctrl_pre_freq_inh=0 640 (0 << 9) | /* P_ctrl_pre_freq_inh=0 */
632 (3 << 5) | // P_ctrl_pre_freq_step=3 641 (3 << 5) | /* P_ctrl_pre_freq_step=3 */
633 (1 << 0), // P_pre_freq_win_len=1 642 (1 << 0), /* P_pre_freq_win_len=1 */
634 643
635 1, 903, 644 1, 903,
636 (0 << 4) | 2, // P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW) 645 (0 << 4) | 2, // P_divclksel=0 P_divbitsel=2 (was clk=3,bit=1 for MPW)
@@ -717,7 +726,7 @@ static int dib8000_reset(struct dvb_frontend *fe)
717 if (dib8000_reset_gpio(state) != 0) 726 if (dib8000_reset_gpio(state) != 0)
718 dprintk("GPIO reset was not successful."); 727 dprintk("GPIO reset was not successful.");
719 728
720 if (dib8000_set_output_mode(state, OUTMODE_HIGH_Z) != 0) 729 if (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0)
721 dprintk("OUTPUT_MODE could not be resetted."); 730 dprintk("OUTPUT_MODE could not be resetted.");
722 731
723 state->current_agc = NULL; 732 state->current_agc = NULL;
@@ -752,7 +761,7 @@ static int dib8000_reset(struct dvb_frontend *fe)
752 /* unforce divstr regardless whether i2c enumeration was done or not */ 761 /* unforce divstr regardless whether i2c enumeration was done or not */
753 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); 762 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
754 763
755 dib8000_set_bandwidth(state, 6000); 764 dib8000_set_bandwidth(fe, 6000);
756 765
757 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON); 766 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
758 dib8000_sad_calib(state); 767 dib8000_sad_calib(state);
@@ -778,7 +787,7 @@ static int dib8000_update_lna(struct dib8000_state *state)
778 // read dyn_gain here (because it is demod-dependent and not tuner) 787 // read dyn_gain here (because it is demod-dependent and not tuner)
779 dyn_gain = dib8000_read_word(state, 390); 788 dyn_gain = dib8000_read_word(state, 390);
780 789
781 if (state->cfg.update_lna(&state->fe, dyn_gain)) { // LNA has changed 790 if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
782 dib8000_restart_agc(state); 791 dib8000_restart_agc(state);
783 return 1; 792 return 1;
784 } 793 }
@@ -865,7 +874,8 @@ static int dib8000_agc_soft_split(struct dib8000_state *state)
865 split_offset = state->current_agc->split.max; 874 split_offset = state->current_agc->split.max;
866 else 875 else
867 split_offset = state->current_agc->split.max * 876 split_offset = state->current_agc->split.max *
868 (agc - state->current_agc->split.min_thres) / (state->current_agc->split.max_thres - state->current_agc->split.min_thres); 877 (agc - state->current_agc->split.min_thres) /
878 (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
869 879
870 dprintk("AGC split_offset: %d", split_offset); 880 dprintk("AGC split_offset: %d", split_offset);
871 881
@@ -900,7 +910,7 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
900 case CT_AGC_STEP_0: 910 case CT_AGC_STEP_0:
901 //AGC initialization 911 //AGC initialization
902 if (state->cfg.agc_control) 912 if (state->cfg.agc_control)
903 state->cfg.agc_control(&state->fe, 1); 913 state->cfg.agc_control(fe, 1);
904 914
905 dib8000_restart_agc(state); 915 dib8000_restart_agc(state);
906 916
@@ -924,7 +934,7 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
924 dib8000_agc_soft_split(state); 934 dib8000_agc_soft_split(state);
925 935
926 if (state->cfg.agc_control) 936 if (state->cfg.agc_control)
927 state->cfg.agc_control(&state->fe, 0); 937 state->cfg.agc_control(fe, 0);
928 938
929 *tune_state = CT_AGC_STOP; 939 *tune_state = CT_AGC_STOP;
930 break; 940 break;
@@ -936,29 +946,28 @@ static int dib8000_agc_startup(struct dvb_frontend *fe)
936 946
937} 947}
938 948
939static const int32_t lut_1000ln_mant[] = 949static const s32 lut_1000ln_mant[] =
940{ 950{
941 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600 951 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
942}; 952};
943 953
944int32_t dib8000_get_adc_power(struct dvb_frontend *fe, uint8_t mode) 954s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
945{ 955{
946 struct dib8000_state *state = fe->demodulator_priv; 956 struct dib8000_state *state = fe->demodulator_priv;
947 uint32_t ix = 0, tmp_val = 0, exp = 0, mant = 0; 957 u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
948 int32_t val; 958 s32 val;
949 959
950 val = dib8000_read32(state, 384); 960 val = dib8000_read32(state, 384);
951 /* mode = 1 : ln_agcpower calc using mant-exp conversion and mantis look up table */ 961 if (mode) {
952 if (mode) { 962 tmp_val = val;
953 tmp_val = val; 963 while (tmp_val >>= 1)
954 while (tmp_val >>= 1) 964 exp++;
955 exp++; 965 mant = (val * 1000 / (1<<exp));
956 mant = (val * 1000 / (1<<exp)); 966 ix = (u8)((mant-1000)/100); /* index of the LUT */
957 ix = (uint8_t)((mant-1000)/100); /* index of the LUT */ 967 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
958 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908); /* 1000 * ln(adcpower_real) ; 693 = 1000ln(2) ; 6908 = 1000*ln(1000) ; 20 comes from adc_real = adc_pow_int / 2**20 */ 968 val = (val*256)/1000;
959 val = (val*256)/1000; 969 }
960 } 970 return val;
961 return val;
962} 971}
963EXPORT_SYMBOL(dib8000_get_adc_power); 972EXPORT_SYMBOL(dib8000_get_adc_power);
964 973
@@ -1002,22 +1011,23 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1002 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); 1011 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
1003 1012
1004 i = dib8000_read_word(state, 26) & 1; // P_dds_invspec 1013 i = dib8000_read_word(state, 26) & 1; // P_dds_invspec
1005 dib8000_write_word(state, 26, state->fe.dtv_property_cache.inversion ^ i); 1014 dib8000_write_word(state, 26, state->fe[0]->dtv_property_cache.inversion^i);
1006 1015
1007 if (state->fe.dtv_property_cache.isdbt_sb_mode) { 1016 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
1008 //compute new dds_freq for the seg and adjust prbs 1017 //compute new dds_freq for the seg and adjust prbs
1009 int seg_offset = 1018 int seg_offset =
1010 state->fe.dtv_property_cache.isdbt_sb_segment_idx - (state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) - 1019 state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx -
1011 (state->fe.dtv_property_cache.isdbt_sb_segment_count % 2); 1020 (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) -
1021 (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2);
1012 int clk = state->cfg.pll->internal; 1022 int clk = state->cfg.pll->internal;
1013 u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26) 1023 u32 segtodds = ((u32) (430 << 23) / clk) << 3; // segtodds = SegBW / Fclk * pow(2,26)
1014 int dds_offset = seg_offset * segtodds; 1024 int dds_offset = seg_offset * segtodds;
1015 int new_dds, sub_channel; 1025 int new_dds, sub_channel;
1016 if ((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0) // if even 1026 if ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
1017 dds_offset -= (int)(segtodds / 2); 1027 dds_offset -= (int)(segtodds / 2);
1018 1028
1019 if (state->cfg.pll->ifreq == 0) { 1029 if (state->cfg.pll->ifreq == 0) {
1020 if ((state->fe.dtv_property_cache.inversion ^ i) == 0) { 1030 if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0) {
1021 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); 1031 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
1022 new_dds = dds_offset; 1032 new_dds = dds_offset;
1023 } else 1033 } else
@@ -1027,35 +1037,35 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1027 // - the segment of center frequency with an odd total number of segments 1037 // - the segment of center frequency with an odd total number of segments
1028 // - the segment to the left of center frequency with an even total number of segments 1038 // - the segment to the left of center frequency with an even total number of segments
1029 // - the segment to the right of center frequency with an even total number of segments 1039 // - the segment to the right of center frequency with an even total number of segments
1030 if ((state->fe.dtv_property_cache.delivery_system == SYS_ISDBT) && (state->fe.dtv_property_cache.isdbt_sb_mode == 1) 1040 if ((state->fe[0]->dtv_property_cache.delivery_system == SYS_ISDBT)
1031 && 1041 && (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
1032 (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) 1042 && (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
1033 && (state->fe.dtv_property_cache.isdbt_sb_segment_idx == 1043 && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
1034 ((state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) 1044 ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
1035 || (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0) 1045 || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
1036 && (state->fe.dtv_property_cache.isdbt_sb_segment_idx == (state->fe.dtv_property_cache.isdbt_sb_segment_count / 2))) 1046 && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx == (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2)))
1037 || (((state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) == 0) 1047 || (((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
1038 && (state->fe.dtv_property_cache.isdbt_sb_segment_idx == 1048 && (state->fe[0]->dtv_property_cache.isdbt_sb_segment_idx ==
1039 ((state->fe.dtv_property_cache.isdbt_sb_segment_count / 2) + 1))) 1049 ((state->fe[0]->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
1040 )) { 1050 )) {
1041 new_dds -= ((u32) (850 << 22) / clk) << 4; // new_dds = 850 (freq shift in KHz) / Fclk * pow(2,26) 1051 new_dds -= ((u32) (850 << 22) / clk) << 4; // new_dds = 850 (freq shift in KHz) / Fclk * pow(2,26)
1042 } 1052 }
1043 } else { 1053 } else {
1044 if ((state->fe.dtv_property_cache.inversion ^ i) == 0) 1054 if ((state->fe[0]->dtv_property_cache.inversion ^ i) == 0)
1045 new_dds = state->cfg.pll->ifreq - dds_offset; 1055 new_dds = state->cfg.pll->ifreq - dds_offset;
1046 else 1056 else
1047 new_dds = state->cfg.pll->ifreq + dds_offset; 1057 new_dds = state->cfg.pll->ifreq + dds_offset;
1048 } 1058 }
1049 dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff)); 1059 dib8000_write_word(state, 27, (u16) ((new_dds >> 16) & 0x01ff));
1050 dib8000_write_word(state, 28, (u16) (new_dds & 0xffff)); 1060 dib8000_write_word(state, 28, (u16) (new_dds & 0xffff));
1051 if (state->fe.dtv_property_cache.isdbt_sb_segment_count % 2) // if odd 1061 if (state->fe[0]->dtv_property_cache.isdbt_sb_segment_count % 2)
1052 sub_channel = ((state->fe.dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3; 1062 sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset) + 1) % 41) / 3;
1053 else // if even 1063 else
1054 sub_channel = ((state->fe.dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3; 1064 sub_channel = ((state->fe[0]->dtv_property_cache.isdbt_sb_subchannel + (3 * seg_offset)) % 41) / 3;
1055 sub_channel -= 6; 1065 sub_channel -= 6;
1056 1066
1057 if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K 1067 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K
1058 || state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) { 1068 || state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_4K) {
1059 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1 1069 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); //adp_pass =1
1060 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shift = 1 1070 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); //pha3_force_pha_shift = 1
1061 } else { 1071 } else {
@@ -1063,7 +1073,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1063 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0 1073 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); //pha3_force_pha_shift = 0
1064 } 1074 }
1065 1075
1066 switch (state->fe.dtv_property_cache.transmission_mode) { 1076 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1067 case TRANSMISSION_MODE_2K: 1077 case TRANSMISSION_MODE_2K:
1068 switch (sub_channel) { 1078 switch (sub_channel) {
1069 case -6: 1079 case -6:
@@ -1209,7 +1219,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1209 } 1219 }
1210 break; 1220 break;
1211 } 1221 }
1212 } else { // if not state->fe.dtv_property_cache.isdbt_sb_mode 1222 } else {
1213 dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff)); 1223 dib8000_write_word(state, 27, (u16) ((state->cfg.pll->ifreq >> 16) & 0x01ff));
1214 dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff)); 1224 dib8000_write_word(state, 28, (u16) (state->cfg.pll->ifreq & 0xffff));
1215 dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003)); 1225 dib8000_write_word(state, 26, (u16) ((state->cfg.pll->ifreq >> 25) & 0x0003));
@@ -1218,7 +1228,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1218 dib8000_write_word(state, 10, (seq << 4)); 1228 dib8000_write_word(state, 10, (seq << 4));
1219 // dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000); 1229 // dib8000_write_word(state, 287, (dib8000_read_word(state, 287) & 0xe000) | 0x1000);
1220 1230
1221 switch (state->fe.dtv_property_cache.guard_interval) { 1231 switch (state->fe[0]->dtv_property_cache.guard_interval) {
1222 case GUARD_INTERVAL_1_32: 1232 case GUARD_INTERVAL_1_32:
1223 guard = 0; 1233 guard = 0;
1224 break; 1234 break;
@@ -1238,7 +1248,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1238 1248
1239 max_constellation = DQPSK; 1249 max_constellation = DQPSK;
1240 for (i = 0; i < 3; i++) { 1250 for (i = 0; i < 3; i++) {
1241 switch (state->fe.dtv_property_cache.layer[i].modulation) { 1251 switch (state->fe[0]->dtv_property_cache.layer[i].modulation) {
1242 case DQPSK: 1252 case DQPSK:
1243 constellation = 0; 1253 constellation = 0;
1244 break; 1254 break;
@@ -1254,7 +1264,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1254 break; 1264 break;
1255 } 1265 }
1256 1266
1257 switch (state->fe.dtv_property_cache.layer[i].fec) { 1267 switch (state->fe[0]->dtv_property_cache.layer[i].fec) {
1258 case FEC_1_2: 1268 case FEC_1_2:
1259 crate = 1; 1269 crate = 1;
1260 break; 1270 break;
@@ -1273,26 +1283,26 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1273 break; 1283 break;
1274 } 1284 }
1275 1285
1276 if ((state->fe.dtv_property_cache.layer[i].interleaving > 0) && 1286 if ((state->fe[0]->dtv_property_cache.layer[i].interleaving > 0) &&
1277 ((state->fe.dtv_property_cache.layer[i].interleaving <= 3) || 1287 ((state->fe[0]->dtv_property_cache.layer[i].interleaving <= 3) ||
1278 (state->fe.dtv_property_cache.layer[i].interleaving == 4 && state->fe.dtv_property_cache.isdbt_sb_mode == 1)) 1288 (state->fe[0]->dtv_property_cache.layer[i].interleaving == 4 && state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1))
1279 ) 1289 )
1280 timeI = state->fe.dtv_property_cache.layer[i].interleaving; 1290 timeI = state->fe[0]->dtv_property_cache.layer[i].interleaving;
1281 else 1291 else
1282 timeI = 0; 1292 timeI = 0;
1283 dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe.dtv_property_cache.layer[i].segment_count & 0xf) << 6) | 1293 dib8000_write_word(state, 2 + i, (constellation << 10) | ((state->fe[0]->dtv_property_cache.layer[i].segment_count & 0xf) << 6) |
1284 (crate << 3) | timeI); 1294 (crate << 3) | timeI);
1285 if (state->fe.dtv_property_cache.layer[i].segment_count > 0) { 1295 if (state->fe[0]->dtv_property_cache.layer[i].segment_count > 0) {
1286 switch (max_constellation) { 1296 switch (max_constellation) {
1287 case DQPSK: 1297 case DQPSK:
1288 case QPSK: 1298 case QPSK:
1289 if (state->fe.dtv_property_cache.layer[i].modulation == QAM_16 || 1299 if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_16 ||
1290 state->fe.dtv_property_cache.layer[i].modulation == QAM_64) 1300 state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
1291 max_constellation = state->fe.dtv_property_cache.layer[i].modulation; 1301 max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
1292 break; 1302 break;
1293 case QAM_16: 1303 case QAM_16:
1294 if (state->fe.dtv_property_cache.layer[i].modulation == QAM_64) 1304 if (state->fe[0]->dtv_property_cache.layer[i].modulation == QAM_64)
1295 max_constellation = state->fe.dtv_property_cache.layer[i].modulation; 1305 max_constellation = state->fe[0]->dtv_property_cache.layer[i].modulation;
1296 break; 1306 break;
1297 } 1307 }
1298 } 1308 }
@@ -1303,34 +1313,34 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1303 //dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/ 1313 //dib8000_write_word(state, 5, 13); /*p_last_seg = 13*/
1304 1314
1305 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | 1315 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) |
1306 ((state->fe.dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe.dtv_property_cache. 1316 ((state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 5) | ((state->fe[0]->dtv_property_cache.
1307 isdbt_sb_mode & 1) << 4)); 1317 isdbt_sb_mode & 1) << 4));
1308 1318
1309 dprintk("mode = %d ; guard = %d", mode, state->fe.dtv_property_cache.guard_interval); 1319 dprintk("mode = %d ; guard = %d", mode, state->fe[0]->dtv_property_cache.guard_interval);
1310 1320
1311 /* signal optimization parameter */ 1321 /* signal optimization parameter */
1312 1322
1313 if (state->fe.dtv_property_cache.isdbt_partial_reception) { 1323 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception) {
1314 seg_diff_mask = (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0]; 1324 seg_diff_mask = (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) << permu_seg[0];
1315 for (i = 1; i < 3; i++) 1325 for (i = 1; i < 3; i++)
1316 nbseg_diff += 1326 nbseg_diff +=
1317 (state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * state->fe.dtv_property_cache.layer[i].segment_count; 1327 (state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
1318 for (i = 0; i < nbseg_diff; i++) 1328 for (i = 0; i < nbseg_diff; i++)
1319 seg_diff_mask |= 1 << permu_seg[i + 1]; 1329 seg_diff_mask |= 1 << permu_seg[i + 1];
1320 } else { 1330 } else {
1321 for (i = 0; i < 3; i++) 1331 for (i = 0; i < 3; i++)
1322 nbseg_diff += 1332 nbseg_diff +=
1323 (state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * state->fe.dtv_property_cache.layer[i].segment_count; 1333 (state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * state->fe[0]->dtv_property_cache.layer[i].segment_count;
1324 for (i = 0; i < nbseg_diff; i++) 1334 for (i = 0; i < nbseg_diff; i++)
1325 seg_diff_mask |= 1 << permu_seg[i]; 1335 seg_diff_mask |= 1 << permu_seg[i];
1326 } 1336 }
1327 dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask); 1337 dprintk("nbseg_diff = %X (%d)", seg_diff_mask, seg_diff_mask);
1328 1338
1329 state->differential_constellation = (seg_diff_mask != 0); 1339 state->differential_constellation = (seg_diff_mask != 0);
1330 dib8000_set_diversity_in(&state->fe, state->diversity_onoff); 1340 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
1331 1341
1332 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb 1342 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1333 if (state->fe.dtv_property_cache.isdbt_partial_reception == 1) // 3-segments 1343 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
1334 seg_mask13 = 0x00E0; 1344 seg_mask13 = 0x00E0;
1335 else // 1-segment 1345 else // 1-segment
1336 seg_mask13 = 0x0040; 1346 seg_mask13 = 0x0040;
@@ -1340,7 +1350,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1340 // WRITE: Mode & Diff mask 1350 // WRITE: Mode & Diff mask
1341 dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask); 1351 dib8000_write_word(state, 0, (mode << 13) | seg_diff_mask);
1342 1352
1343 if ((seg_diff_mask) || (state->fe.dtv_property_cache.isdbt_sb_mode)) 1353 if ((seg_diff_mask) || (state->fe[0]->dtv_property_cache.isdbt_sb_mode))
1344 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); 1354 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
1345 else 1355 else
1346 dib8000_write_word(state, 268, (2 << 9) | 39); //init value 1356 dib8000_write_word(state, 268, (2 << 9) | 39); //init value
@@ -1351,26 +1361,25 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1351 1361
1352 dib8000_write_word(state, 353, seg_mask13); // ADDR 353 1362 dib8000_write_word(state, 353, seg_mask13); // ADDR 353
1353 1363
1354/* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */ 1364/* // P_small_narrow_band=0, P_small_last_seg=13, P_small_offset_num_car=5 */
1355 // dib8000_write_word(state, 351, (state->fe.dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5 );
1356 1365
1357 // ---- SMALL ---- 1366 // ---- SMALL ----
1358 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { 1367 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1359 switch (state->fe.dtv_property_cache.transmission_mode) { 1368 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1360 case TRANSMISSION_MODE_2K: 1369 case TRANSMISSION_MODE_2K:
1361 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg 1370 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
1362 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK 1371 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
1363 ncoeff = coeff_2k_sb_1seg_dqpsk; 1372 ncoeff = coeff_2k_sb_1seg_dqpsk;
1364 else // QPSK or QAM 1373 else // QPSK or QAM
1365 ncoeff = coeff_2k_sb_1seg; 1374 ncoeff = coeff_2k_sb_1seg;
1366 } else { // 3-segments 1375 } else { // 3-segments
1367 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment 1376 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
1368 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments 1377 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
1369 ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk; 1378 ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
1370 else // QPSK or QAM on external segments 1379 else // QPSK or QAM on external segments
1371 ncoeff = coeff_2k_sb_3seg_0dqpsk; 1380 ncoeff = coeff_2k_sb_3seg_0dqpsk;
1372 } else { // QPSK or QAM on central segment 1381 } else { // QPSK or QAM on central segment
1373 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) // DQPSK on external segments 1382 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK)
1374 ncoeff = coeff_2k_sb_3seg_1dqpsk; 1383 ncoeff = coeff_2k_sb_3seg_1dqpsk;
1375 else // QPSK or QAM on external segments 1384 else // QPSK or QAM on external segments
1376 ncoeff = coeff_2k_sb_3seg; 1385 ncoeff = coeff_2k_sb_3seg;
@@ -1379,20 +1388,20 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1379 break; 1388 break;
1380 1389
1381 case TRANSMISSION_MODE_4K: 1390 case TRANSMISSION_MODE_4K:
1382 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg 1391 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
1383 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK 1392 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
1384 ncoeff = coeff_4k_sb_1seg_dqpsk; 1393 ncoeff = coeff_4k_sb_1seg_dqpsk;
1385 else // QPSK or QAM 1394 else // QPSK or QAM
1386 ncoeff = coeff_4k_sb_1seg; 1395 ncoeff = coeff_4k_sb_1seg;
1387 } else { // 3-segments 1396 } else { // 3-segments
1388 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment 1397 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
1389 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments 1398 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
1390 ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk; 1399 ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
1391 } else { // QPSK or QAM on external segments 1400 } else { // QPSK or QAM on external segments
1392 ncoeff = coeff_4k_sb_3seg_0dqpsk; 1401 ncoeff = coeff_4k_sb_3seg_0dqpsk;
1393 } 1402 }
1394 } else { // QPSK or QAM on central segment 1403 } else { // QPSK or QAM on central segment
1395 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments 1404 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
1396 ncoeff = coeff_4k_sb_3seg_1dqpsk; 1405 ncoeff = coeff_4k_sb_3seg_1dqpsk;
1397 } else // QPSK or QAM on external segments 1406 } else // QPSK or QAM on external segments
1398 ncoeff = coeff_4k_sb_3seg; 1407 ncoeff = coeff_4k_sb_3seg;
@@ -1403,20 +1412,20 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1403 case TRANSMISSION_MODE_AUTO: 1412 case TRANSMISSION_MODE_AUTO:
1404 case TRANSMISSION_MODE_8K: 1413 case TRANSMISSION_MODE_8K:
1405 default: 1414 default:
1406 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // 1-seg 1415 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
1407 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) // DQPSK 1416 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK)
1408 ncoeff = coeff_8k_sb_1seg_dqpsk; 1417 ncoeff = coeff_8k_sb_1seg_dqpsk;
1409 else // QPSK or QAM 1418 else // QPSK or QAM
1410 ncoeff = coeff_8k_sb_1seg; 1419 ncoeff = coeff_8k_sb_1seg;
1411 } else { // 3-segments 1420 } else { // 3-segments
1412 if (state->fe.dtv_property_cache.layer[0].modulation == DQPSK) { // DQPSK on central segment 1421 if (state->fe[0]->dtv_property_cache.layer[0].modulation == DQPSK) {
1413 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments 1422 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
1414 ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk; 1423 ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
1415 } else { // QPSK or QAM on external segments 1424 } else { // QPSK or QAM on external segments
1416 ncoeff = coeff_8k_sb_3seg_0dqpsk; 1425 ncoeff = coeff_8k_sb_3seg_0dqpsk;
1417 } 1426 }
1418 } else { // QPSK or QAM on central segment 1427 } else { // QPSK or QAM on central segment
1419 if (state->fe.dtv_property_cache.layer[1].modulation == DQPSK) { // DQPSK on external segments 1428 if (state->fe[0]->dtv_property_cache.layer[1].modulation == DQPSK) {
1420 ncoeff = coeff_8k_sb_3seg_1dqpsk; 1429 ncoeff = coeff_8k_sb_3seg_1dqpsk;
1421 } else // QPSK or QAM on external segments 1430 } else // QPSK or QAM on external segments
1422 ncoeff = coeff_8k_sb_3seg; 1431 ncoeff = coeff_8k_sb_3seg;
@@ -1430,22 +1439,22 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1430 1439
1431 // P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 1440 // P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5
1432 dib8000_write_word(state, 351, 1441 dib8000_write_word(state, 351,
1433 (state->fe.dtv_property_cache.isdbt_sb_mode << 9) | (state->fe.dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5); 1442 (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 9) | (state->fe[0]->dtv_property_cache.isdbt_sb_mode << 8) | (13 << 4) | 5);
1434 1443
1435 // ---- COFF ---- 1444 // ---- COFF ----
1436 // Carloff, the most robust 1445 // Carloff, the most robust
1437 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // Sound Broadcasting mode - use both TMCC and AC pilots 1446 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1438 1447
1439 // P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64 1448 // P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64
1440 // P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 1449 // P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1
1441 dib8000_write_word(state, 187, 1450 dib8000_write_word(state, 187,
1442 (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe.dtv_property_cache.isdbt_partial_reception & 1) << 2) 1451 (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~state->fe[0]->dtv_property_cache.isdbt_partial_reception & 1) << 2)
1443 | 0x3); 1452 | 0x3);
1444 1453
1445/* // P_small_coef_ext_enable = 1 */ 1454/* // P_small_coef_ext_enable = 1 */
1446/* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */ 1455/* dib8000_write_word(state, 351, dib8000_read_word(state, 351) | 0x200); */
1447 1456
1448 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg 1457 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
1449 1458
1450 // P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1) 1459 // P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width= (P_mode == 3) , P_coff_one_seg_sym= (P_mode-1)
1451 if (mode == 3) 1460 if (mode == 3)
@@ -1469,10 +1478,10 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1469 dib8000_write_word(state, 186, 80); 1478 dib8000_write_word(state, 186, 80);
1470 } else { // Sound Broadcasting mode 3 seg 1479 } else { // Sound Broadcasting mode 3 seg
1471 // P_coff_one_seg_sym= 1, P_coff_one_seg_width= 1, P_coff_winlen=63, P_coff_thres_lock=15 1480 // P_coff_one_seg_sym= 1, P_coff_one_seg_width= 1, P_coff_winlen=63, P_coff_thres_lock=15
1472 /* if (mode == 3) */ 1481 /* if (mode == 3) */
1473 /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */ 1482 /* dib8000_write_word(state, 180, 0x2fca | ((0) << 14)); */
1474 /* else */ 1483 /* else */
1475 /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */ 1484 /* dib8000_write_word(state, 180, 0x2fca | ((1) << 14)); */
1476 dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); 1485 dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
1477 1486
1478 // P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1, 1487 // P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1,
@@ -1509,7 +1518,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1509 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); 1518 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
1510 } 1519 }
1511 // ---- FFT ---- 1520 // ---- FFT ----
1512 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1 && state->fe.dtv_property_cache.isdbt_partial_reception == 0) // 1-seg 1521 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 && state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
1513 dib8000_write_word(state, 178, 64); // P_fft_powrange=64 1522 dib8000_write_word(state, 178, 64); // P_fft_powrange=64
1514 else 1523 else
1515 dib8000_write_word(state, 178, 32); // P_fft_powrange=32 1524 dib8000_write_word(state, 178, 32); // P_fft_powrange=32
@@ -1518,12 +1527,12 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1518 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed) 1527 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
1519 */ 1528 */
1520 /* if ( ( nbseg_diff>0)&&(nbseg_diff<13)) 1529 /* if ( ( nbseg_diff>0)&&(nbseg_diff<13))
1521 dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */ 1530 dib8000_write_word(state, 187, (dib8000_read_word(state, 187) & 0xfffb) | (1 << 3)); */
1522 1531
1523 dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */ 1532 dib8000_write_word(state, 189, ~seg_mask13 | seg_diff_mask); /* P_lmod4_seg_inh */
1524 dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */ 1533 dib8000_write_word(state, 192, ~seg_mask13 | seg_diff_mask); /* P_pha3_seg_inh */
1525 dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */ 1534 dib8000_write_word(state, 225, ~seg_mask13 | seg_diff_mask); /* P_tac_seg_inh */
1526 if ((!state->fe.dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0)) 1535 if ((!state->fe[0]->dtv_property_cache.isdbt_sb_mode) && (state->cfg.pll->ifreq == 0))
1527 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */ 1536 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
1528 else 1537 else
1529 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */ 1538 dib8000_write_word(state, 266, ~seg_mask13 | seg_diff_mask); /* P_equal_noise_seg_inh */
@@ -1538,8 +1547,8 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1538 dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */ 1547 dib8000_write_word(state, 211, seg_mask13 & (~seg_diff_mask)); /* P_des_seg_enabled */
1539 1548
1540 /* offset loop parameters */ 1549 /* offset loop parameters */
1541 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { 1550 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1542 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg 1551 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
1543 /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */ 1552 /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x80 */
1544 dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40); 1553 dib8000_write_word(state, 32, ((11 - mode) << 12) | (6 << 8) | 0x40);
1545 1554
@@ -1551,8 +1560,8 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1551 /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */ 1560 /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
1552 dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80); 1561 dib8000_write_word(state, 32, ((9 - mode) << 12) | (6 << 8) | 0x80);
1553 1562
1554 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { 1563 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1555 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg 1564 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
1556 /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */ 1565 /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (11-P_mode) */
1557 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode)); 1566 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (10 - mode));
1558 1567
@@ -1564,7 +1573,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1564 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode)); 1573 dib8000_write_word(state, 37, (3 << 5) | (0 << 4) | (8 - mode));
1565 1574
1566 /* P_dvsy_sync_wait - reuse mode */ 1575 /* P_dvsy_sync_wait - reuse mode */
1567 switch (state->fe.dtv_property_cache.transmission_mode) { 1576 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1568 case TRANSMISSION_MODE_8K: 1577 case TRANSMISSION_MODE_8K:
1569 mode = 256; 1578 mode = 256;
1570 break; 1579 break;
@@ -1624,15 +1633,15 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1624 } 1633 }
1625 1634
1626 // ---- ANA_FE ---- 1635 // ---- ANA_FE ----
1627 if (state->fe.dtv_property_cache.isdbt_sb_mode) { 1636 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
1628 if (state->fe.dtv_property_cache.isdbt_partial_reception == 1) // 3-segments 1637 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 1)
1629 ana_fe = ana_fe_coeff_3seg; 1638 ana_fe = ana_fe_coeff_3seg;
1630 else // 1-segment 1639 else // 1-segment
1631 ana_fe = ana_fe_coeff_1seg; 1640 ana_fe = ana_fe_coeff_1seg;
1632 } else 1641 } else
1633 ana_fe = ana_fe_coeff_13seg; 1642 ana_fe = ana_fe_coeff_13seg;
1634 1643
1635 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0) 1644 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1 || state->isdbt_cfg_loaded == 0)
1636 for (mode = 0; mode < 24; mode++) 1645 for (mode = 0; mode < 24; mode++)
1637 dib8000_write_word(state, 117 + mode, ana_fe[mode]); 1646 dib8000_write_word(state, 117 + mode, ana_fe[mode]);
1638 1647
@@ -1648,11 +1657,11 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1648 // "P_cspu_left_edge" not used => do not care 1657 // "P_cspu_left_edge" not used => do not care
1649 // "P_cspu_right_edge" not used => do not care 1658 // "P_cspu_right_edge" not used => do not care
1650 1659
1651 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { // ISDB-Tsb 1660 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1652 dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1 1661 dib8000_write_word(state, 228, 1); // P_2d_mode_byp=1
1653 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0 1662 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); // P_cspu_win_cut = 0
1654 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0 // 1-segment 1663 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0
1655 && state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) { 1664 && state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_2K) {
1656 //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0 1665 //dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); // P_adp_pass = 0
1657 dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15 1666 dib8000_write_word(state, 265, 15); // P_equal_noise_sel = 15
1658 } 1667 }
@@ -1664,7 +1673,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1664 // ---- TMCC ---- 1673 // ---- TMCC ----
1665 for (i = 0; i < 3; i++) 1674 for (i = 0; i < 3; i++)
1666 tmcc_pow += 1675 tmcc_pow +=
1667 (((state->fe.dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe.dtv_property_cache.layer[i].segment_count); 1676 (((state->fe[0]->dtv_property_cache.layer[i].modulation == DQPSK) * 4 + 1) * state->fe[0]->dtv_property_cache.layer[i].segment_count);
1668 // Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9); 1677 // Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9);
1669 // Threshold is set at 1/4 of max power. 1678 // Threshold is set at 1/4 of max power.
1670 tmcc_pow *= (1 << (9 - 2)); 1679 tmcc_pow *= (1 << (9 - 2));
@@ -1678,7 +1687,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
1678 if (state->isdbt_cfg_loaded == 0) 1687 if (state->isdbt_cfg_loaded == 0)
1679 dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */ 1688 dib8000_write_word(state, 250, 3285); /*p_2d_hspeed_thr0 */
1680 1689
1681 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) 1690 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1)
1682 state->isdbt_cfg_loaded = 0; 1691 state->isdbt_cfg_loaded = 0;
1683 else 1692 else
1684 state->isdbt_cfg_loaded = 1; 1693 state->isdbt_cfg_loaded = 1;
@@ -1693,38 +1702,38 @@ static int dib8000_autosearch_start(struct dvb_frontend *fe)
1693 1702
1694 int slist = 0; 1703 int slist = 0;
1695 1704
1696 state->fe.dtv_property_cache.inversion = 0; 1705 state->fe[0]->dtv_property_cache.inversion = 0;
1697 if (!state->fe.dtv_property_cache.isdbt_sb_mode) 1706 if (!state->fe[0]->dtv_property_cache.isdbt_sb_mode)
1698 state->fe.dtv_property_cache.layer[0].segment_count = 13; 1707 state->fe[0]->dtv_property_cache.layer[0].segment_count = 13;
1699 state->fe.dtv_property_cache.layer[0].modulation = QAM_64; 1708 state->fe[0]->dtv_property_cache.layer[0].modulation = QAM_64;
1700 state->fe.dtv_property_cache.layer[0].fec = FEC_2_3; 1709 state->fe[0]->dtv_property_cache.layer[0].fec = FEC_2_3;
1701 state->fe.dtv_property_cache.layer[0].interleaving = 0; 1710 state->fe[0]->dtv_property_cache.layer[0].interleaving = 0;
1702 1711
1703 //choose the right list, in sb, always do everything 1712 //choose the right list, in sb, always do everything
1704 if (state->fe.dtv_property_cache.isdbt_sb_mode) { 1713 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode) {
1705 state->fe.dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; 1714 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1706 state->fe.dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; 1715 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1707 slist = 7; 1716 slist = 7;
1708 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); 1717 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
1709 } else { 1718 } else {
1710 if (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) { 1719 if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) {
1711 if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) { 1720 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
1712 slist = 7; 1721 slist = 7;
1713 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to have autosearch start ok with mode2 1722 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 to have autosearch start ok with mode2
1714 } else 1723 } else
1715 slist = 3; 1724 slist = 3;
1716 } else { 1725 } else {
1717 if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) { 1726 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) {
1718 slist = 2; 1727 slist = 2;
1719 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1 1728 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); // P_mode = 1
1720 } else 1729 } else
1721 slist = 0; 1730 slist = 0;
1722 } 1731 }
1723 1732
1724 if (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) 1733 if (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO)
1725 state->fe.dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K; 1734 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1726 if (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) 1735 if (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO)
1727 state->fe.dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8; 1736 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1728 1737
1729 dprintk("using list for autosearch : %d", slist); 1738 dprintk("using list for autosearch : %d", slist);
1730 dib8000_set_channel(state, (unsigned char)slist, 1); 1739 dib8000_set_channel(state, (unsigned char)slist, 1);
@@ -1786,7 +1795,7 @@ static int dib8000_tune(struct dvb_frontend *fe)
1786 if (state == NULL) 1795 if (state == NULL)
1787 return -EINVAL; 1796 return -EINVAL;
1788 1797
1789 dib8000_set_bandwidth(state, state->fe.dtv_property_cache.bandwidth_hz / 1000); 1798 dib8000_set_bandwidth(fe, state->fe[0]->dtv_property_cache.bandwidth_hz / 1000);
1790 dib8000_set_channel(state, 0, 0); 1799 dib8000_set_channel(state, 0, 0);
1791 1800
1792 // restart demod 1801 // restart demod
@@ -1799,17 +1808,16 @@ static int dib8000_tune(struct dvb_frontend *fe)
1799 1808
1800 // never achieved a lock before - wait for timfreq to update 1809 // never achieved a lock before - wait for timfreq to update
1801 if (state->timf == 0) { 1810 if (state->timf == 0) {
1802 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { 1811 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1803 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) // Sound Broadcasting mode 1 seg 1812 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0)
1804 msleep(300); 1813 msleep(300);
1805 else // Sound Broadcasting mode 3 seg 1814 else // Sound Broadcasting mode 3 seg
1806 msleep(500); 1815 msleep(500);
1807 } else // 13 seg 1816 } else // 13 seg
1808 msleep(200); 1817 msleep(200);
1809 } 1818 }
1810 //dump_reg(state); 1819 if (state->fe[0]->dtv_property_cache.isdbt_sb_mode == 1) {
1811 if (state->fe.dtv_property_cache.isdbt_sb_mode == 1) { 1820 if (state->fe[0]->dtv_property_cache.isdbt_partial_reception == 0) {
1812 if (state->fe.dtv_property_cache.isdbt_partial_reception == 0) { // Sound Broadcasting mode 1 seg
1813 1821
1814 /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */ 1822 /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40 alpha to check on board */
1815 dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40); 1823 dib8000_write_word(state, 32, ((13 - mode) << 12) | (6 << 8) | 0x40);
@@ -1854,26 +1862,38 @@ static int dib8000_tune(struct dvb_frontend *fe)
1854static int dib8000_wakeup(struct dvb_frontend *fe) 1862static int dib8000_wakeup(struct dvb_frontend *fe)
1855{ 1863{
1856 struct dib8000_state *state = fe->demodulator_priv; 1864 struct dib8000_state *state = fe->demodulator_priv;
1865 u8 index_frontend;
1866 int ret;
1857 1867
1858 dib8000_set_power_mode(state, DIB8000M_POWER_ALL); 1868 dib8000_set_power_mode(state, DIB8000M_POWER_ALL);
1859 dib8000_set_adc_state(state, DIBX000_ADC_ON); 1869 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1860 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) 1870 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
1861 dprintk("could not start Slow ADC"); 1871 dprintk("could not start Slow ADC");
1862 1872
1873 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1874 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
1875 if (ret < 0)
1876 return ret;
1877 }
1878
1863 return 0; 1879 return 0;
1864} 1880}
1865 1881
1866static int dib8000_sleep(struct dvb_frontend *fe) 1882static int dib8000_sleep(struct dvb_frontend *fe)
1867{ 1883{
1868 struct dib8000_state *st = fe->demodulator_priv; 1884 struct dib8000_state *state = fe->demodulator_priv;
1869 if (1) { 1885 u8 index_frontend;
1870 dib8000_set_output_mode(st, OUTMODE_HIGH_Z); 1886 int ret;
1871 dib8000_set_power_mode(st, DIB8000M_POWER_INTERFACE_ONLY);
1872 return dib8000_set_adc_state(st, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(st, DIBX000_ADC_OFF);
1873 } else {
1874 1887
1875 return 0; 1888 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1889 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
1890 if (ret < 0)
1891 return ret;
1876 } 1892 }
1893
1894 dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
1895 dib8000_set_power_mode(state, DIB8000M_POWER_INTERFACE_ONLY);
1896 return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
1877} 1897}
1878 1898
1879enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe) 1899enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
@@ -1891,16 +1911,40 @@ int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
1891} 1911}
1892EXPORT_SYMBOL(dib8000_set_tune_state); 1912EXPORT_SYMBOL(dib8000_set_tune_state);
1893 1913
1894
1895
1896
1897static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 1914static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1898{ 1915{
1899 struct dib8000_state *state = fe->demodulator_priv; 1916 struct dib8000_state *state = fe->demodulator_priv;
1900 u16 i, val = 0; 1917 u16 i, val = 0;
1918 fe_status_t stat;
1919 u8 index_frontend, sub_index_frontend;
1901 1920
1902 fe->dtv_property_cache.bandwidth_hz = 6000000; 1921 fe->dtv_property_cache.bandwidth_hz = 6000000;
1903 1922
1923 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1924 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
1925 if (stat&FE_HAS_SYNC) {
1926 dprintk("TMCC lock on the slave%i", index_frontend);
1927 /* synchronize the cache with the other frontends */
1928 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
1929 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
1930 if (sub_index_frontend != index_frontend) {
1931 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
1932 state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
1933 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
1934 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
1935 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
1936 for (i = 0; i < 3; i++) {
1937 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
1938 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
1939 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
1940 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
1941 }
1942 }
1943 }
1944 return 0;
1945 }
1946 }
1947
1904 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; 1948 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
1905 1949
1906 val = dib8000_read_word(state, 570); 1950 val = dib8000_read_word(state, 570);
@@ -1992,112 +2036,200 @@ static int dib8000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_par
1992 break; 2036 break;
1993 } 2037 }
1994 } 2038 }
2039
2040 /* synchronize the cache with the other frontends */
2041 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2042 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode;
2043 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
2044 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
2045 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
2046 state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isdbt_partial_reception;
2047 for (i = 0; i < 3; i++) {
2048 state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.layer[i].segment_count;
2049 state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer[i].interleaving;
2050 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec;
2051 state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i].modulation;
2052 }
2053 }
1995 return 0; 2054 return 0;
1996} 2055}
1997 2056
1998static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep) 2057static int dib8000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1999{ 2058{
2000 struct dib8000_state *state = fe->demodulator_priv; 2059 struct dib8000_state *state = fe->demodulator_priv;
2060 u8 nbr_pending, exit_condition, index_frontend;
2061 s8 index_frontend_success = -1;
2001 int time, ret; 2062 int time, ret;
2063 int time_slave = FE_CALLBACK_TIME_NEVER;
2002 2064
2003 fe->dtv_property_cache.delivery_system = SYS_ISDBT; 2065 if (state->fe[0]->dtv_property_cache.frequency == 0) {
2066 dprintk("dib8000: must at least specify frequency ");
2067 return 0;
2068 }
2004 2069
2005 dib8000_set_output_mode(state, OUTMODE_HIGH_Z); 2070 if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
2071 dprintk("dib8000: no bandwidth specified, set to default ");
2072 state->fe[0]->dtv_property_cache.bandwidth_hz = 6000000;
2073 }
2074
2075 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2076 /* synchronization of the cache */
2077 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
2078 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
2079
2080 dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
2081 if (state->fe[index_frontend]->ops.tuner_ops.set_params)
2082 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend], fep);
2006 2083
2007 if (fe->ops.tuner_ops.set_params) 2084 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
2008 fe->ops.tuner_ops.set_params(fe, fep); 2085 }
2009 2086
2010 /* start up the AGC */ 2087 /* start up the AGC */
2011 state->tune_state = CT_AGC_START;
2012 do { 2088 do {
2013 time = dib8000_agc_startup(fe); 2089 time = dib8000_agc_startup(state->fe[0]);
2090 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2091 time_slave = dib8000_agc_startup(state->fe[index_frontend]);
2092 if (time == FE_CALLBACK_TIME_NEVER)
2093 time = time_slave;
2094 else if ((time_slave != FE_CALLBACK_TIME_NEVER) && (time_slave > time))
2095 time = time_slave;
2096 }
2014 if (time != FE_CALLBACK_TIME_NEVER) 2097 if (time != FE_CALLBACK_TIME_NEVER)
2015 msleep(time / 10); 2098 msleep(time / 10);
2016 else 2099 else
2017 break; 2100 break;
2018 } while (state->tune_state != CT_AGC_STOP); 2101 exit_condition = 1;
2019 2102 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2020 if (state->fe.dtv_property_cache.frequency == 0) { 2103 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
2021 dprintk("dib8000: must at least specify frequency "); 2104 exit_condition = 0;
2022 return 0; 2105 break;
2023 } 2106 }
2024 2107 }
2025 if (state->fe.dtv_property_cache.bandwidth_hz == 0) { 2108 } while (exit_condition == 0);
2026 dprintk("dib8000: no bandwidth specified, set to default "); 2109
2027 state->fe.dtv_property_cache.bandwidth_hz = 6000000; 2110 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2028 } 2111 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
2112
2113 if ((state->fe[0]->dtv_property_cache.delivery_system != SYS_ISDBT) ||
2114 (state->fe[0]->dtv_property_cache.inversion == INVERSION_AUTO) ||
2115 (state->fe[0]->dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) ||
2116 (state->fe[0]->dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) ||
2117 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) &&
2118 (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0xff) &&
2119 (state->fe[0]->dtv_property_cache.layer[0].segment_count != 0) &&
2120 ((state->fe[0]->dtv_property_cache.layer[0].modulation == QAM_AUTO) ||
2121 (state->fe[0]->dtv_property_cache.layer[0].fec == FEC_AUTO))) ||
2122 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) &&
2123 (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0xff) &&
2124 (state->fe[0]->dtv_property_cache.layer[1].segment_count != 0) &&
2125 ((state->fe[0]->dtv_property_cache.layer[1].modulation == QAM_AUTO) ||
2126 (state->fe[0]->dtv_property_cache.layer[1].fec == FEC_AUTO))) ||
2127 (((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) &&
2128 (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0xff) &&
2129 (state->fe[0]->dtv_property_cache.layer[2].segment_count != 0) &&
2130 ((state->fe[0]->dtv_property_cache.layer[2].modulation == QAM_AUTO) ||
2131 (state->fe[0]->dtv_property_cache.layer[2].fec == FEC_AUTO))) ||
2132 (((state->fe[0]->dtv_property_cache.layer[0].segment_count == 0) ||
2133 ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) &&
2134 ((state->fe[0]->dtv_property_cache.layer[1].segment_count == 0) ||
2135 ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
2136 ((state->fe[0]->dtv_property_cache.layer[2].segment_count == 0) || ((state->fe[0]->dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
2137 int i = 80000;
2138 u8 found = 0;
2139 u8 tune_failed = 0;
2140
2141 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2142 dib8000_set_bandwidth(state->fe[index_frontend], fe->dtv_property_cache.bandwidth_hz / 1000);
2143 dib8000_autosearch_start(state->fe[index_frontend]);
2144 }
2029 2145
2030 state->tune_state = CT_DEMOD_START;
2031
2032 if ((state->fe.dtv_property_cache.delivery_system != SYS_ISDBT) ||
2033 (state->fe.dtv_property_cache.inversion == INVERSION_AUTO) ||
2034 (state->fe.dtv_property_cache.transmission_mode == TRANSMISSION_MODE_AUTO) ||
2035 (state->fe.dtv_property_cache.guard_interval == GUARD_INTERVAL_AUTO) ||
2036 (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 0)) != 0) &&
2037 (state->fe.dtv_property_cache.layer[0].segment_count != 0xff) &&
2038 (state->fe.dtv_property_cache.layer[0].segment_count != 0) &&
2039 ((state->fe.dtv_property_cache.layer[0].modulation == QAM_AUTO) ||
2040 (state->fe.dtv_property_cache.layer[0].fec == FEC_AUTO))) ||
2041 (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 1)) != 0) &&
2042 (state->fe.dtv_property_cache.layer[1].segment_count != 0xff) &&
2043 (state->fe.dtv_property_cache.layer[1].segment_count != 0) &&
2044 ((state->fe.dtv_property_cache.layer[1].modulation == QAM_AUTO) ||
2045 (state->fe.dtv_property_cache.layer[1].fec == FEC_AUTO))) ||
2046 (((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 2)) != 0) &&
2047 (state->fe.dtv_property_cache.layer[2].segment_count != 0xff) &&
2048 (state->fe.dtv_property_cache.layer[2].segment_count != 0) &&
2049 ((state->fe.dtv_property_cache.layer[2].modulation == QAM_AUTO) ||
2050 (state->fe.dtv_property_cache.layer[2].fec == FEC_AUTO))) ||
2051 (((state->fe.dtv_property_cache.layer[0].segment_count == 0) ||
2052 ((state->fe.dtv_property_cache.isdbt_layer_enabled & (1 << 0)) == 0)) &&
2053 ((state->fe.dtv_property_cache.layer[1].segment_count == 0) ||
2054 ((state->fe.dtv_property_cache.isdbt_layer_enabled & (2 << 0)) == 0)) &&
2055 ((state->fe.dtv_property_cache.layer[2].segment_count == 0) || ((state->fe.dtv_property_cache.isdbt_layer_enabled & (3 << 0)) == 0)))) {
2056 int i = 800, found;
2057
2058 dib8000_set_bandwidth(state, fe->dtv_property_cache.bandwidth_hz / 1000);
2059 dib8000_autosearch_start(fe);
2060 do { 2146 do {
2061 msleep(10); 2147 msleep(20);
2062 found = dib8000_autosearch_irq(fe); 2148 nbr_pending = 0;
2063 } while (found == 0 && i--); 2149 exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
2150 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2151 if (((tune_failed >> index_frontend) & 0x1) == 0) {
2152 found = dib8000_autosearch_irq(state->fe[index_frontend]);
2153 switch (found) {
2154 case 0: /* tune pending */
2155 nbr_pending++;
2156 break;
2157 case 2:
2158 dprintk("autosearch succeed on the frontend%i", index_frontend);
2159 exit_condition = 2;
2160 index_frontend_success = index_frontend;
2161 break;
2162 default:
2163 dprintk("unhandled autosearch result");
2164 case 1:
2165 dprintk("autosearch failed for the frontend%i", index_frontend);
2166 break;
2167 }
2168 }
2169 }
2064 2170
2065 dprintk("Frequency %d Hz, autosearch returns: %d", fep->frequency, found); 2171 /* if all tune are done and no success, exit: tune failed */
2172 if ((nbr_pending == 0) && (exit_condition == 0))
2173 exit_condition = 1;
2174 } while ((exit_condition == 0) && i--);
2066 2175
2067 if (found == 0 || found == 1) 2176 if (exit_condition == 1) { /* tune failed */
2068 return 0; // no channel found 2177 dprintk("tune failed");
2178 return 0;
2179 }
2180
2181 dprintk("tune success on frontend%i", index_frontend_success);
2069 2182
2070 dib8000_get_frontend(fe, fep); 2183 dib8000_get_frontend(fe, fep);
2071 } 2184 }
2072 2185
2073 ret = dib8000_tune(fe); 2186 for (index_frontend = 0, ret = 0; (ret >= 0) && (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2187 ret = dib8000_tune(state->fe[index_frontend]);
2188
2189 /* set output mode and diversity input */
2190 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
2191 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2192 dib8000_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
2193 dib8000_set_diversity_in(state->fe[index_frontend-1], 1);
2194 }
2074 2195
2075 /* make this a config parameter */ 2196 /* turn off the diversity of the last chip */
2076 dib8000_set_output_mode(state, state->cfg.output_mode); 2197 dib8000_set_diversity_in(state->fe[index_frontend-1], 0);
2077 2198
2078 return ret; 2199 return ret;
2079} 2200}
2080 2201
2202static u16 dib8000_read_lock(struct dvb_frontend *fe)
2203{
2204 struct dib8000_state *state = fe->demodulator_priv;
2205
2206 return dib8000_read_word(state, 568);
2207}
2208
2081static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat) 2209static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2082{ 2210{
2083 struct dib8000_state *state = fe->demodulator_priv; 2211 struct dib8000_state *state = fe->demodulator_priv;
2084 u16 lock = dib8000_read_word(state, 568); 2212 u16 lock_slave = 0, lock = dib8000_read_word(state, 568);
2213 u8 index_frontend;
2214
2215 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2216 lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
2085 2217
2086 *stat = 0; 2218 *stat = 0;
2087 2219
2088 if ((lock >> 13) & 1) 2220 if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
2089 *stat |= FE_HAS_SIGNAL; 2221 *stat |= FE_HAS_SIGNAL;
2090 2222
2091 if ((lock >> 8) & 1) /* Equal */ 2223 if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
2092 *stat |= FE_HAS_CARRIER; 2224 *stat |= FE_HAS_CARRIER;
2093 2225
2094 if (((lock >> 1) & 0xf) == 0xf) /* TMCC_SYNC */ 2226 if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
2095 *stat |= FE_HAS_SYNC; 2227 *stat |= FE_HAS_SYNC;
2096 2228
2097 if (((lock >> 12) & 1) && ((lock >> 5) & 7)) /* FEC MPEG */ 2229 if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
2098 *stat |= FE_HAS_LOCK; 2230 *stat |= FE_HAS_LOCK;
2099 2231
2100 if ((lock >> 12) & 1) { 2232 if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
2101 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */ 2233 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
2102 if (lock & 0x01) 2234 if (lock & 0x01)
2103 *stat |= FE_HAS_VITERBI; 2235 *stat |= FE_HAS_VITERBI;
@@ -2131,44 +2263,120 @@ static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
2131static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength) 2263static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2132{ 2264{
2133 struct dib8000_state *state = fe->demodulator_priv; 2265 struct dib8000_state *state = fe->demodulator_priv;
2134 u16 val = dib8000_read_word(state, 390); 2266 u8 index_frontend;
2135 *strength = 65535 - val; 2267 u16 val;
2268
2269 *strength = 0;
2270 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2271 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
2272 if (val > 65535 - *strength)
2273 *strength = 65535;
2274 else
2275 *strength += val;
2276 }
2277
2278 val = 65535 - dib8000_read_word(state, 390);
2279 if (val > 65535 - *strength)
2280 *strength = 65535;
2281 else
2282 *strength += val;
2136 return 0; 2283 return 0;
2137} 2284}
2138 2285
2139static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr) 2286static u32 dib8000_get_snr(struct dvb_frontend *fe)
2140{ 2287{
2141 struct dib8000_state *state = fe->demodulator_priv; 2288 struct dib8000_state *state = fe->demodulator_priv;
2289 u32 n, s, exp;
2142 u16 val; 2290 u16 val;
2143 s32 signal_mant, signal_exp, noise_mant, noise_exp;
2144 u32 result = 0;
2145 2291
2146 val = dib8000_read_word(state, 542); 2292 val = dib8000_read_word(state, 542);
2147 noise_mant = (val >> 6) & 0xff; 2293 n = (val >> 6) & 0xff;
2148 noise_exp = (val & 0x3f); 2294 exp = (val & 0x3f);
2295 if ((exp & 0x20) != 0)
2296 exp -= 0x40;
2297 n <<= exp+16;
2149 2298
2150 val = dib8000_read_word(state, 543); 2299 val = dib8000_read_word(state, 543);
2151 signal_mant = (val >> 6) & 0xff; 2300 s = (val >> 6) & 0xff;
2152 signal_exp = (val & 0x3f); 2301 exp = (val & 0x3f);
2302 if ((exp & 0x20) != 0)
2303 exp -= 0x40;
2304 s <<= exp+16;
2305
2306 if (n > 0) {
2307 u32 t = (s/n) << 16;
2308 return t + ((s << 16) - n*t) / n;
2309 }
2310 return 0xffffffff;
2311}
2153 2312
2154 if ((noise_exp & 0x20) != 0) 2313static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
2155 noise_exp -= 0x40; 2314{
2156 if ((signal_exp & 0x20) != 0) 2315 struct dib8000_state *state = fe->demodulator_priv;
2157 signal_exp -= 0x40; 2316 u8 index_frontend;
2317 u32 snr_master;
2158 2318
2159 if (signal_mant != 0) 2319 snr_master = dib8000_get_snr(fe);
2160 result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant); 2320 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2161 else 2321 snr_master += dib8000_get_snr(state->fe[index_frontend]);
2162 result = intlog10(2) * 10 * signal_exp - 100; 2322
2163 if (noise_mant != 0) 2323 if (snr_master != 0) {
2164 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant); 2324 snr_master = 10*intlog10(snr_master>>16);
2325 *snr = snr_master / ((1 << 24) / 10);
2326 }
2165 else 2327 else
2166 result -= intlog10(2) * 10 * noise_exp - 100; 2328 *snr = 0;
2167 2329
2168 *snr = result / ((1 << 24) / 10);
2169 return 0; 2330 return 0;
2170} 2331}
2171 2332
2333int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
2334{
2335 struct dib8000_state *state = fe->demodulator_priv;
2336 u8 index_frontend = 1;
2337
2338 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2339 index_frontend++;
2340 if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
2341 dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
2342 state->fe[index_frontend] = fe_slave;
2343 return 0;
2344 }
2345
2346 dprintk("too many slave frontend");
2347 return -ENOMEM;
2348}
2349EXPORT_SYMBOL(dib8000_set_slave_frontend);
2350
2351int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
2352{
2353 struct dib8000_state *state = fe->demodulator_priv;
2354 u8 index_frontend = 1;
2355
2356 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2357 index_frontend++;
2358 if (index_frontend != 1) {
2359 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);
2360 state->fe[index_frontend] = NULL;
2361 return 0;
2362 }
2363
2364 dprintk("no frontend to be removed");
2365 return -ENODEV;
2366}
2367EXPORT_SYMBOL(dib8000_remove_slave_frontend);
2368
2369struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
2370{
2371 struct dib8000_state *state = fe->demodulator_priv;
2372
2373 if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
2374 return NULL;
2375 return state->fe[slave_index];
2376}
2377EXPORT_SYMBOL(dib8000_get_slave_frontend);
2378
2379
2172int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr) 2380int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
2173{ 2381{
2174 int k = 0; 2382 int k = 0;
@@ -2227,7 +2435,13 @@ static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_fron
2227static void dib8000_release(struct dvb_frontend *fe) 2435static void dib8000_release(struct dvb_frontend *fe)
2228{ 2436{
2229 struct dib8000_state *st = fe->demodulator_priv; 2437 struct dib8000_state *st = fe->demodulator_priv;
2438 u8 index_frontend;
2439
2440 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
2441 dvb_frontend_detach(st->fe[index_frontend]);
2442
2230 dibx000_exit_i2c_master(&st->i2c_master); 2443 dibx000_exit_i2c_master(&st->i2c_master);
2444 kfree(st->fe[0]);
2231 kfree(st); 2445 kfree(st);
2232} 2446}
2233 2447
@@ -2242,19 +2456,19 @@ EXPORT_SYMBOL(dib8000_get_i2c_master);
2242int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff) 2456int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
2243{ 2457{
2244 struct dib8000_state *st = fe->demodulator_priv; 2458 struct dib8000_state *st = fe->demodulator_priv;
2245 u16 val = dib8000_read_word(st, 299) & 0xffef; 2459 u16 val = dib8000_read_word(st, 299) & 0xffef;
2246 val |= (onoff & 0x1) << 4; 2460 val |= (onoff & 0x1) << 4;
2247 2461
2248 dprintk("pid filter enabled %d", onoff); 2462 dprintk("pid filter enabled %d", onoff);
2249 return dib8000_write_word(st, 299, val); 2463 return dib8000_write_word(st, 299, val);
2250} 2464}
2251EXPORT_SYMBOL(dib8000_pid_filter_ctrl); 2465EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
2252 2466
2253int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff) 2467int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
2254{ 2468{
2255 struct dib8000_state *st = fe->demodulator_priv; 2469 struct dib8000_state *st = fe->demodulator_priv;
2256 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff); 2470 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
2257 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0); 2471 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
2258} 2472}
2259EXPORT_SYMBOL(dib8000_pid_filter); 2473EXPORT_SYMBOL(dib8000_pid_filter);
2260 2474
@@ -2298,6 +2512,9 @@ struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, s
2298 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL); 2512 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
2299 if (state == NULL) 2513 if (state == NULL)
2300 return NULL; 2514 return NULL;
2515 fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
2516 if (fe == NULL)
2517 goto error;
2301 2518
2302 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config)); 2519 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
2303 state->i2c.adap = i2c_adap; 2520 state->i2c.adap = i2c_adap;
@@ -2311,9 +2528,9 @@ struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, s
2311 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) 2528 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2312 state->cfg.output_mode = OUTMODE_MPEG2_FIFO; 2529 state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
2313 2530
2314 fe = &state->fe; 2531 state->fe[0] = fe;
2315 fe->demodulator_priv = state; 2532 fe->demodulator_priv = state;
2316 memcpy(&state->fe.ops, &dib8000_ops, sizeof(struct dvb_frontend_ops)); 2533 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
2317 2534
2318 state->timf_default = cfg->pll->timf; 2535 state->timf_default = cfg->pll->timf;
2319 2536
diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h
index e0a9ded11df4..617f9eba3a09 100644
--- a/drivers/media/dvb/frontends/dib8000.h
+++ b/drivers/media/dvb/frontends/dib8000.h
@@ -50,6 +50,9 @@ extern int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_st
50extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe); 50extern enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe);
51extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe); 51extern void dib8000_pwm_agc_reset(struct dvb_frontend *fe);
52extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode); 52extern s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode);
53extern int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
54extern int dib8000_remove_slave_frontend(struct dvb_frontend *fe);
55extern struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
53#else 56#else
54static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg) 57static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
55{ 58{
@@ -111,6 +114,23 @@ static inline s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
111 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 114 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
112 return 0; 115 return 0;
113} 116}
117static inline int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
118{
119 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
120 return -ENODEV;
121}
122
123int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
124{
125 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
126 return -ENODEV;
127}
128
129static inline struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
130{
131 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
132 return NULL;
133}
114#endif 134#endif
115 135
116#endif 136#endif
diff --git a/drivers/media/dvb/frontends/dib9000.c b/drivers/media/dvb/frontends/dib9000.c
new file mode 100644
index 000000000000..91518761a2da
--- /dev/null
+++ b/drivers/media/dvb/frontends/dib9000.c
@@ -0,0 +1,2351 @@
1/*
2 * Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family.
3 *
4 * Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
9 */
10#include <linux/kernel.h>
11#include <linux/i2c.h>
12#include <linux/mutex.h>
13
14#include "dvb_math.h"
15#include "dvb_frontend.h"
16
17#include "dib9000.h"
18#include "dibx000_common.h"
19
20static int debug;
21module_param(debug, int, 0644);
22MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
23
24#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0)
25#define MAX_NUMBER_OF_FRONTENDS 6
26
27struct i2c_device {
28 struct i2c_adapter *i2c_adap;
29 u8 i2c_addr;
30};
31
32/* lock */
33#define DIB_LOCK struct mutex
34#define DibAcquireLock(lock) do { if (mutex_lock_interruptible(lock) < 0) dprintk("could not get the lock"); } while (0)
35#define DibReleaseLock(lock) mutex_unlock(lock)
36#define DibInitLock(lock) mutex_init(lock)
37#define DibFreeLock(lock)
38
39struct dib9000_state {
40 struct i2c_device i2c;
41
42 struct dibx000_i2c_master i2c_master;
43 struct i2c_adapter tuner_adap;
44 struct i2c_adapter component_bus;
45
46 u16 revision;
47 u8 reg_offs;
48
49 enum frontend_tune_state tune_state;
50 u32 status;
51 struct dvb_frontend_parametersContext channel_status;
52
53 u8 fe_id;
54
55#define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
56 u16 gpio_dir;
57#define DIB9000_GPIO_DEFAULT_VALUES 0x0000
58 u16 gpio_val;
59#define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff
60 u16 gpio_pwm_pos;
61
62 union { /* common for all chips */
63 struct {
64 u8 mobile_mode:1;
65 } host;
66
67 struct {
68 struct dib9000_fe_memory_map {
69 u16 addr;
70 u16 size;
71 } fe_mm[18];
72 u8 memcmd;
73
74 DIB_LOCK mbx_if_lock; /* to protect read/write operations */
75 DIB_LOCK mbx_lock; /* to protect the whole mailbox handling */
76
77 DIB_LOCK mem_lock; /* to protect the memory accesses */
78 DIB_LOCK mem_mbx_lock; /* to protect the memory-based mailbox */
79
80#define MBX_MAX_WORDS (256 - 200 - 2)
81#define DIB9000_MSG_CACHE_SIZE 2
82 u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS];
83 u8 fw_is_running;
84 } risc;
85 } platform;
86
87 union { /* common for all platforms */
88 struct {
89 struct dib9000_config cfg;
90 } d9;
91 } chip;
92
93 struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
94 u16 component_bus_speed;
95};
96
97u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
98 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
99 0, 0, 0
100};
101
102enum dib9000_power_mode {
103 DIB9000_POWER_ALL = 0,
104
105 DIB9000_POWER_NO,
106 DIB9000_POWER_INTERF_ANALOG_AGC,
107 DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
108 DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD,
109 DIB9000_POWER_INTERFACE_ONLY,
110};
111
112enum dib9000_out_messages {
113 OUT_MSG_HBM_ACK,
114 OUT_MSG_HOST_BUF_FAIL,
115 OUT_MSG_REQ_VERSION,
116 OUT_MSG_BRIDGE_I2C_W,
117 OUT_MSG_BRIDGE_I2C_R,
118 OUT_MSG_BRIDGE_APB_W,
119 OUT_MSG_BRIDGE_APB_R,
120 OUT_MSG_SCAN_CHANNEL,
121 OUT_MSG_MONIT_DEMOD,
122 OUT_MSG_CONF_GPIO,
123 OUT_MSG_DEBUG_HELP,
124 OUT_MSG_SUBBAND_SEL,
125 OUT_MSG_ENABLE_TIME_SLICE,
126 OUT_MSG_FE_FW_DL,
127 OUT_MSG_FE_CHANNEL_SEARCH,
128 OUT_MSG_FE_CHANNEL_TUNE,
129 OUT_MSG_FE_SLEEP,
130 OUT_MSG_FE_SYNC,
131 OUT_MSG_CTL_MONIT,
132
133 OUT_MSG_CONF_SVC,
134 OUT_MSG_SET_HBM,
135 OUT_MSG_INIT_DEMOD,
136 OUT_MSG_ENABLE_DIVERSITY,
137 OUT_MSG_SET_OUTPUT_MODE,
138 OUT_MSG_SET_PRIORITARY_CHANNEL,
139 OUT_MSG_ACK_FRG,
140 OUT_MSG_INIT_PMU,
141};
142
143enum dib9000_in_messages {
144 IN_MSG_DATA,
145 IN_MSG_FRAME_INFO,
146 IN_MSG_CTL_MONIT,
147 IN_MSG_ACK_FREE_ITEM,
148 IN_MSG_DEBUG_BUF,
149 IN_MSG_MPE_MONITOR,
150 IN_MSG_RAWTS_MONITOR,
151 IN_MSG_END_BRIDGE_I2C_RW,
152 IN_MSG_END_BRIDGE_APB_RW,
153 IN_MSG_VERSION,
154 IN_MSG_END_OF_SCAN,
155 IN_MSG_MONIT_DEMOD,
156 IN_MSG_ERROR,
157 IN_MSG_FE_FW_DL_DONE,
158 IN_MSG_EVENT,
159 IN_MSG_ACK_CHANGE_SVC,
160 IN_MSG_HBM_PROF,
161};
162
163/* memory_access requests */
164#define FE_MM_W_CHANNEL 0
165#define FE_MM_W_FE_INFO 1
166#define FE_MM_RW_SYNC 2
167
168#define FE_SYNC_CHANNEL 1
169#define FE_SYNC_W_GENERIC_MONIT 2
170#define FE_SYNC_COMPONENT_ACCESS 3
171
172#define FE_MM_R_CHANNEL_SEARCH_STATE 3
173#define FE_MM_R_CHANNEL_UNION_CONTEXT 4
174#define FE_MM_R_FE_INFO 5
175#define FE_MM_R_FE_MONITOR 6
176
177#define FE_MM_W_CHANNEL_HEAD 7
178#define FE_MM_W_CHANNEL_UNION 8
179#define FE_MM_W_CHANNEL_CONTEXT 9
180#define FE_MM_R_CHANNEL_UNION 10
181#define FE_MM_R_CHANNEL_CONTEXT 11
182#define FE_MM_R_CHANNEL_TUNE_STATE 12
183
184#define FE_MM_R_GENERIC_MONITORING_SIZE 13
185#define FE_MM_W_GENERIC_MONITORING 14
186#define FE_MM_R_GENERIC_MONITORING 15
187
188#define FE_MM_W_COMPONENT_ACCESS 16
189#define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
190static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
191static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
192
193static u16 to_fw_output_mode(u16 mode)
194{
195 switch (mode) {
196 case OUTMODE_HIGH_Z:
197 return 0;
198 case OUTMODE_MPEG2_PAR_GATED_CLK:
199 return 4;
200 case OUTMODE_MPEG2_PAR_CONT_CLK:
201 return 8;
202 case OUTMODE_MPEG2_SERIAL:
203 return 16;
204 case OUTMODE_DIVERSITY:
205 return 128;
206 case OUTMODE_MPEG2_FIFO:
207 return 2;
208 case OUTMODE_ANALOG_ADC:
209 return 1;
210 default:
211 return 0;
212 }
213}
214
215static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute)
216{
217 u32 chunk_size = 126;
218 u32 l;
219 int ret;
220 u8 wb[2] = { reg >> 8, reg & 0xff };
221 struct i2c_msg msg[2] = {
222 {.addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
223 {.addr = state->i2c.i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = len},
224 };
225
226 if (state->platform.risc.fw_is_running && (reg < 1024))
227 return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
228
229 if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
230 wb[0] |= (1 << 5);
231 if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
232 wb[0] |= (1 << 4);
233
234 do {
235 l = len < chunk_size ? len : chunk_size;
236 msg[1].len = l;
237 msg[1].buf = b;
238 ret = i2c_transfer(state->i2c.i2c_adap, msg, 2) != 2 ? -EREMOTEIO : 0;
239 if (ret != 0) {
240 dprintk("i2c read error on %d", reg);
241 return -EREMOTEIO;
242 }
243
244 b += l;
245 len -= l;
246
247 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
248 reg += l / 2;
249 } while ((ret == 0) && len);
250
251 return 0;
252}
253
254static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
255{
256 u8 b[2];
257 u8 wb[2] = { reg >> 8, reg & 0xff };
258 struct i2c_msg msg[2] = {
259 {.addr = i2c->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
260 {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = 2},
261 };
262
263 if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
264 dprintk("read register %x error", reg);
265 return 0;
266 }
267
268 return (b[0] << 8) | b[1];
269}
270
271static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
272{
273 u8 b[2];
274 if (dib9000_read16_attr(state, reg, b, 2, 0) != 0)
275 return 0;
276 return (b[0] << 8 | b[1]);
277}
278
279static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
280{
281 u8 b[2];
282 if (dib9000_read16_attr(state, reg, b, 2, attribute) != 0)
283 return 0;
284 return (b[0] << 8 | b[1]);
285}
286
287#define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
288
289static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute)
290{
291 u8 b[255];
292 u32 chunk_size = 126;
293 u32 l;
294 int ret;
295
296 struct i2c_msg msg = {
297 .addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = b, .len = len + 2
298 };
299
300 if (state->platform.risc.fw_is_running && (reg < 1024)) {
301 if (dib9000_risc_apb_access_write
302 (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
303 return -EINVAL;
304 return 0;
305 }
306
307 b[0] = (reg >> 8) & 0xff;
308 b[1] = (reg) & 0xff;
309
310 if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
311 b[0] |= (1 << 5);
312 if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
313 b[0] |= (1 << 4);
314
315 do {
316 l = len < chunk_size ? len : chunk_size;
317 msg.len = l + 2;
318 memcpy(&b[2], buf, l);
319
320 ret = i2c_transfer(state->i2c.i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
321
322 buf += l;
323 len -= l;
324
325 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
326 reg += l / 2;
327 } while ((ret == 0) && len);
328
329 return ret;
330}
331
332static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
333{
334 u8 b[4] = { (reg >> 8) & 0xff, reg & 0xff, (val >> 8) & 0xff, val & 0xff };
335 struct i2c_msg msg = {
336 .addr = i2c->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
337 };
338
339 return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
340}
341
342static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val)
343{
344 u8 b[2] = { val >> 8, val & 0xff };
345 return dib9000_write16_attr(state, reg, b, 2, 0);
346}
347
348static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute)
349{
350 u8 b[2] = { val >> 8, val & 0xff };
351 return dib9000_write16_attr(state, reg, b, 2, attribute);
352}
353
354#define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
355#define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
356#define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
357
358#define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
359#define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
360
361#define MAC_IRQ (1 << 1)
362#define IRQ_POL_MSK (1 << 4)
363
364#define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
365#define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
366
367static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading)
368{
369 u8 b[14] = { 0 };
370
371/* dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */
372/* b[0] = 0 << 7; */
373 b[1] = 1;
374
375/* b[2] = 0; */
376/* b[3] = 0; */
377 b[4] = (u8) (addr >> 8);
378 b[5] = (u8) (addr & 0xff);
379
380/* b[10] = 0; */
381/* b[11] = 0; */
382 b[12] = (u8) (addr >> 8);
383 b[13] = (u8) (addr & 0xff);
384
385 addr += len;
386/* b[6] = 0; */
387/* b[7] = 0; */
388 b[8] = (u8) (addr >> 8);
389 b[9] = (u8) (addr & 0xff);
390
391 dib9000_write(state, 1056, b, 14);
392 if (reading)
393 dib9000_write_word(state, 1056, (1 << 15) | 1);
394 state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-call to set it */
395}
396
397static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd)
398{
399 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
400 /* decide whether we need to "refresh" the memory controller */
401 if (state->platform.risc.memcmd == cmd && /* same command */
402 !(cmd & 0x80 && m->size < 67)) /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
403 return;
404 dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
405 state->platform.risc.memcmd = cmd;
406}
407
408static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len)
409{
410 if (!state->platform.risc.fw_is_running)
411 return -EIO;
412
413 DibAcquireLock(&state->platform.risc.mem_lock);
414 dib9000_risc_mem_setup(state, cmd | 0x80);
415 dib9000_risc_mem_read_chunks(state, b, len);
416 DibReleaseLock(&state->platform.risc.mem_lock);
417 return 0;
418}
419
420static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b)
421{
422 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd];
423 if (!state->platform.risc.fw_is_running)
424 return -EIO;
425
426 DibAcquireLock(&state->platform.risc.mem_lock);
427 dib9000_risc_mem_setup(state, cmd);
428 dib9000_risc_mem_write_chunks(state, b, m->size);
429 DibReleaseLock(&state->platform.risc.mem_lock);
430 return 0;
431}
432
433static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len)
434{
435 u16 offs;
436
437 if (risc_id == 1)
438 offs = 16;
439 else
440 offs = 0;
441
442 /* config crtl reg */
443 dib9000_write_word(state, 1024 + offs, 0x000f);
444 dib9000_write_word(state, 1025 + offs, 0);
445 dib9000_write_word(state, 1031 + offs, key);
446
447 dprintk("going to download %dB of microcode", len);
448 if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) {
449 dprintk("error while downloading microcode for RISC %c", 'A' + risc_id);
450 return -EIO;
451 }
452
453 dprintk("Microcode for RISC %c loaded", 'A' + risc_id);
454
455 return 0;
456}
457
458static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id)
459{
460 u16 mbox_offs;
461 u16 reset_reg;
462 u16 tries = 1000;
463
464 if (risc_id == 1)
465 mbox_offs = 16;
466 else
467 mbox_offs = 0;
468
469 /* Reset mailbox */
470 dib9000_write_word(state, 1027 + mbox_offs, 0x8000);
471
472 /* Read reset status */
473 do {
474 reset_reg = dib9000_read_word(state, 1027 + mbox_offs);
475 msleep(100);
476 } while ((reset_reg & 0x8000) && --tries);
477
478 if (reset_reg & 0x8000) {
479 dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id);
480 return -EIO;
481 }
482 dprintk("MBX: initialized");
483 return 0;
484}
485
486#define MAX_MAILBOX_TRY 100
487static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr)
488{
489 u8 *d, b[2];
490 u16 tmp;
491 u16 size;
492 u32 i;
493 int ret = 0;
494
495 if (!state->platform.risc.fw_is_running)
496 return -EINVAL;
497
498 DibAcquireLock(&state->platform.risc.mbx_if_lock);
499 tmp = MAX_MAILBOX_TRY;
500 do {
501 size = dib9000_read_word_attr(state, 1043, attr) & 0xff;
502 if ((size + len + 1) > MBX_MAX_WORDS && --tmp) {
503 dprintk("MBX: RISC mbx full, retrying");
504 msleep(100);
505 } else
506 break;
507 } while (1);
508
509 /*dprintk( "MBX: size: %d", size); */
510
511 if (tmp == 0) {
512 ret = -EINVAL;
513 goto out;
514 }
515#ifdef DUMP_MSG
516 dprintk("--> %02x %d ", id, len + 1);
517 for (i = 0; i < len; i++)
518 dprintk("%04x ", data[i]);
519 dprintk("\n");
520#endif
521
522 /* byte-order conversion - works on big (where it is not necessary) or little endian */
523 d = (u8 *) data;
524 for (i = 0; i < len; i++) {
525 tmp = data[i];
526 *d++ = tmp >> 8;
527 *d++ = tmp & 0xff;
528 }
529
530 /* write msg */
531 b[0] = id;
532 b[1] = len + 1;
533 if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) {
534 ret = -EIO;
535 goto out;
536 }
537
538 /* update register nb_mes_in_RX */
539 ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
540
541out:
542 DibReleaseLock(&state->platform.risc.mbx_if_lock);
543
544 return ret;
545}
546
547static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr)
548{
549#ifdef DUMP_MSG
550 u16 *d = data;
551#endif
552
553 u16 tmp, i;
554 u8 size;
555 u8 mc_base;
556
557 if (!state->platform.risc.fw_is_running)
558 return 0;
559
560 DibAcquireLock(&state->platform.risc.mbx_if_lock);
561 if (risc_id == 1)
562 mc_base = 16;
563 else
564 mc_base = 0;
565
566 /* Length and type in the first word */
567 *data = dib9000_read_word_attr(state, 1029 + mc_base, attr);
568
569 size = *data & 0xff;
570 if (size <= MBX_MAX_WORDS) {
571 data++;
572 size--; /* Initial word already read */
573
574 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr);
575
576 /* to word conversion */
577 for (i = 0; i < size; i++) {
578 tmp = *data;
579 *data = (tmp >> 8) | (tmp << 8);
580 data++;
581 }
582
583#ifdef DUMP_MSG
584 dprintk("<-- ");
585 for (i = 0; i < size + 1; i++)
586 dprintk("%04x ", d[i]);
587 dprintk("\n");
588#endif
589 } else {
590 dprintk("MBX: message is too big for message cache (%d), flushing message", size);
591 size--; /* Initial word already read */
592 while (size--)
593 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr);
594 }
595 /* Update register nb_mes_in_TX */
596 dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr);
597
598 DibReleaseLock(&state->platform.risc.mbx_if_lock);
599
600 return size + 1;
601}
602
603static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size)
604{
605 u32 ts = data[1] << 16 | data[0];
606 char *b = (char *)&data[2];
607
608 b[2 * (size - 2) - 1] = '\0'; /* Bullet proof the buffer */
609 if (*b == '~') {
610 b++;
611 dprintk(b);
612 } else
613 dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<emtpy>");
614 return 1;
615}
616
617static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr)
618{
619 int i;
620 u8 size;
621 u16 *block;
622 /* find a free slot */
623 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
624 block = state->platform.risc.message_cache[i];
625 if (*block == 0) {
626 size = dib9000_mbx_read(state, block, 1, attr);
627
628/* dprintk( "MBX: fetched %04x message to cache", *block); */
629
630 switch (*block >> 8) {
631 case IN_MSG_DEBUG_BUF:
632 dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */
633 *block = 0; /* free the block */
634 break;
635#if 0
636 case IN_MSG_DATA: /* FE-TRACE */
637 dib9000_risc_data_process(state, block + 1, size);
638 *block = 0;
639 break;
640#endif
641 default:
642 break;
643 }
644
645 return 1;
646 }
647 }
648 dprintk("MBX: no free cache-slot found for new message...");
649 return -1;
650}
651
652static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr)
653{
654 if (risc_id == 0)
655 return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f; /* 5 bit field */
656 else
657 return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f; /* 7 bit field */
658}
659
660static int dib9000_mbx_process(struct dib9000_state *state, u16 attr)
661{
662 int ret = 0;
663 u16 tmp;
664
665 if (!state->platform.risc.fw_is_running)
666 return -1;
667
668 DibAcquireLock(&state->platform.risc.mbx_lock);
669
670 if (dib9000_mbx_count(state, 1, attr)) /* 1=RiscB */
671 ret = dib9000_mbx_fetch_to_cache(state, attr);
672
673 tmp = dib9000_read_word_attr(state, 1229, attr); /* Clear the IRQ */
674/* if (tmp) */
675/* dprintk( "cleared IRQ: %x", tmp); */
676 DibReleaseLock(&state->platform.risc.mbx_lock);
677
678 return ret;
679}
680
681static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr)
682{
683 u8 i;
684 u16 *block;
685 u16 timeout = 30;
686
687 *msg = 0;
688 do {
689 /* dib9000_mbx_get_from_cache(); */
690 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
691 block = state->platform.risc.message_cache[i];
692 if ((*block >> 8) == id) {
693 *size = (*block & 0xff) - 1;
694 memcpy(msg, block + 1, (*size) * 2);
695 *block = 0; /* free the block */
696 i = 0; /* signal that we found a message */
697 break;
698 }
699 }
700
701 if (i == 0)
702 break;
703
704 if (dib9000_mbx_process(state, attr) == -1) /* try to fetch one message - if any */
705 return -1;
706
707 } while (--timeout);
708
709 if (timeout == 0) {
710 dprintk("waiting for message %d timed out", id);
711 return -1;
712 }
713
714 return i == 0;
715}
716
717static int dib9000_risc_check_version(struct dib9000_state *state)
718{
719 u8 r[4];
720 u8 size;
721 u16 fw_version = 0;
722
723 if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0)
724 return -EIO;
725
726 if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0)
727 return -EIO;
728
729 fw_version = (r[0] << 8) | r[1];
730 dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]);
731
732 if ((fw_version >> 10) != 7)
733 return -EINVAL;
734
735 switch (fw_version & 0x3ff) {
736 case 11:
737 case 12:
738 case 14:
739 case 15:
740 case 16:
741 case 17:
742 break;
743 default:
744 dprintk("RISC: invalid firmware version");
745 return -EINVAL;
746 }
747
748 dprintk("RISC: valid firmware version");
749 return 0;
750}
751
752static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)
753{
754 /* Reconfig pool mac ram */
755 dib9000_write_word(state, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */
756 dib9000_write_word(state, 1226, 0x05);
757
758 /* Toggles IP crypto to Host APB interface. */
759 dib9000_write_word(state, 1542, 1);
760
761 /* Set jump and no jump in the dma box */
762 dib9000_write_word(state, 1074, 0);
763 dib9000_write_word(state, 1075, 0);
764
765 /* Set MAC as APB Master. */
766 dib9000_write_word(state, 1237, 0);
767
768 /* Reset the RISCs */
769 if (codeA != NULL)
770 dib9000_write_word(state, 1024, 2);
771 else
772 dib9000_write_word(state, 1024, 15);
773 if (codeB != NULL)
774 dib9000_write_word(state, 1040, 2);
775
776 if (codeA != NULL)
777 dib9000_firmware_download(state, 0, 0x1234, codeA, lenA);
778 if (codeB != NULL)
779 dib9000_firmware_download(state, 1, 0x1234, codeB, lenB);
780
781 /* Run the RISCs */
782 if (codeA != NULL)
783 dib9000_write_word(state, 1024, 0);
784 if (codeB != NULL)
785 dib9000_write_word(state, 1040, 0);
786
787 if (codeA != NULL)
788 if (dib9000_mbx_host_init(state, 0) != 0)
789 return -EIO;
790 if (codeB != NULL)
791 if (dib9000_mbx_host_init(state, 1) != 0)
792 return -EIO;
793
794 msleep(100);
795 state->platform.risc.fw_is_running = 1;
796
797 if (dib9000_risc_check_version(state) != 0)
798 return -EINVAL;
799
800 state->platform.risc.memcmd = 0xff;
801 return 0;
802}
803
804static u16 dib9000_identify(struct i2c_device *client)
805{
806 u16 value;
807
808 value = dib9000_i2c_read16(client, 896);
809 if (value != 0x01b3) {
810 dprintk("wrong Vendor ID (0x%x)", value);
811 return 0;
812 }
813
814 value = dib9000_i2c_read16(client, 897);
815 if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) {
816 dprintk("wrong Device ID (0x%x)", value);
817 return 0;
818 }
819
820 /* protect this driver to be used with 7000PC */
821 if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) {
822 dprintk("this driver does not work with DiB7000PC");
823 return 0;
824 }
825
826 switch (value) {
827 case 0x4000:
828 dprintk("found DiB7000MA/PA/MB/PB");
829 break;
830 case 0x4001:
831 dprintk("found DiB7000HC");
832 break;
833 case 0x4002:
834 dprintk("found DiB7000MC");
835 break;
836 case 0x4003:
837 dprintk("found DiB9000A");
838 break;
839 case 0x4004:
840 dprintk("found DiB9000H");
841 break;
842 case 0x4005:
843 dprintk("found DiB9000M");
844 break;
845 }
846
847 return value;
848}
849
850static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode)
851{
852 /* by default everything is going to be powered off */
853 u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906;
854 u8 offset;
855
856 if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005)
857 offset = 1;
858 else
859 offset = 0;
860
861 reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */
862
863 /* now, depending on the requested mode, we power on */
864 switch (mode) {
865 /* power up everything in the demod */
866 case DIB9000_POWER_ALL:
867 reg_903 = 0x0000;
868 reg_904 = 0x0000;
869 reg_905 = 0x0000;
870 reg_906 = 0x0000;
871 break;
872
873 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
874 case DIB9000_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
875 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
876 break;
877
878 case DIB9000_POWER_INTERF_ANALOG_AGC:
879 reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
880 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
881 reg_906 &= ~((1 << 0));
882 break;
883
884 case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
885 reg_903 = 0x0000;
886 reg_904 = 0x801f;
887 reg_905 = 0x0000;
888 reg_906 &= ~((1 << 0));
889 break;
890
891 case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD:
892 reg_903 = 0x0000;
893 reg_904 = 0x8000;
894 reg_905 = 0x010b;
895 reg_906 &= ~((1 << 0));
896 break;
897 default:
898 case DIB9000_POWER_NO:
899 break;
900 }
901
902 /* always power down unused parts */
903 if (!state->platform.host.mobile_mode)
904 reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
905
906 /* P_sdio_select_clk = 0 on MC and after */
907 if (state->revision != 0x4000)
908 reg_906 <<= 1;
909
910 dib9000_write_word(state, 903 + offset, reg_903);
911 dib9000_write_word(state, 904 + offset, reg_904);
912 dib9000_write_word(state, 905 + offset, reg_905);
913 dib9000_write_word(state, 906 + offset, reg_906);
914}
915
916static int dib9000_fw_reset(struct dvb_frontend *fe)
917{
918 struct dib9000_state *state = fe->demodulator_priv;
919
920 dib9000_write_word(state, 1817, 0x0003);
921
922 dib9000_write_word(state, 1227, 1);
923 dib9000_write_word(state, 1227, 0);
924
925 switch ((state->revision = dib9000_identify(&state->i2c))) {
926 case 0x4003:
927 case 0x4004:
928 case 0x4005:
929 state->reg_offs = 1;
930 break;
931 default:
932 return -EINVAL;
933 }
934
935 /* reset the i2c-master to use the host interface */
936 dibx000_reset_i2c_master(&state->i2c_master);
937
938 dib9000_set_power_mode(state, DIB9000_POWER_ALL);
939
940 /* unforce divstr regardless whether i2c enumeration was done or not */
941 dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1));
942 dib9000_write_word(state, 1796, 0);
943 dib9000_write_word(state, 1805, 0x805);
944
945 /* restart all parts */
946 dib9000_write_word(state, 898, 0xffff);
947 dib9000_write_word(state, 899, 0xffff);
948 dib9000_write_word(state, 900, 0x0001);
949 dib9000_write_word(state, 901, 0xff19);
950 dib9000_write_word(state, 902, 0x003c);
951
952 dib9000_write_word(state, 898, 0);
953 dib9000_write_word(state, 899, 0);
954 dib9000_write_word(state, 900, 0);
955 dib9000_write_word(state, 901, 0);
956 dib9000_write_word(state, 902, 0);
957
958 dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
959
960 dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY);
961
962 return 0;
963}
964
965static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len)
966{
967 u16 mb[10];
968 u8 i, s;
969
970 if (address >= 1024 || !state->platform.risc.fw_is_running)
971 return -EINVAL;
972
973 /* dprintk( "APB access thru rd fw %d %x", address, attribute); */
974
975 mb[0] = (u16) address;
976 mb[1] = len / 2;
977 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
978 switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
979 case 1:
980 s--;
981 for (i = 0; i < s; i++) {
982 b[i * 2] = (mb[i + 1] >> 8) & 0xff;
983 b[i * 2 + 1] = (mb[i + 1]) & 0xff;
984 }
985 return 0;
986 default:
987 return -EIO;
988 }
989 return -EIO;
990}
991
992static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len)
993{
994 u16 mb[10];
995 u8 s, i;
996
997 if (address >= 1024 || !state->platform.risc.fw_is_running)
998 return -EINVAL;
999
1000 /* dprintk( "APB access thru wr fw %d %x", address, attribute); */
1001
1002 mb[0] = (unsigned short)address;
1003 for (i = 0; i < len && i < 20; i += 2)
1004 mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]);
1005
1006 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute);
1007 return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL;
1008}
1009
1010static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i)
1011{
1012 u8 index_loop = 10;
1013
1014 if (!state->platform.risc.fw_is_running)
1015 return 0;
1016 dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
1017 do {
1018 dib9000_risc_mem_read(state, FE_MM_RW_SYNC, &i, 1);
1019 } while (i && index_loop--);
1020
1021 if (index_loop > 0)
1022 return 0;
1023 return -EIO;
1024}
1025
1026static int dib9000_fw_init(struct dib9000_state *state)
1027{
1028 struct dibGPIOFunction *f;
1029 u16 b[40] = { 0 };
1030 u8 i;
1031 u8 size;
1032
1033 if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
1034 return -EIO;
1035
1036 /* initialize the firmware */
1037 for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
1038 f = &state->chip.d9.cfg.gpio_function[i];
1039 if (f->mask) {
1040 switch (f->function) {
1041 case BOARD_GPIO_FUNCTION_COMPONENT_ON:
1042 b[0] = (u16) f->mask;
1043 b[1] = (u16) f->direction;
1044 b[2] = (u16) f->value;
1045 break;
1046 case BOARD_GPIO_FUNCTION_COMPONENT_OFF:
1047 b[3] = (u16) f->mask;
1048 b[4] = (u16) f->direction;
1049 b[5] = (u16) f->value;
1050 break;
1051 }
1052 }
1053 }
1054 if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0)
1055 return -EIO;
1056
1057 /* subband */
1058 b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */
1059 for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
1060 b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
1061 b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
1062 b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
1063 b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
1064 }
1065 b[1 + i * 4] = 0; /* fe_id */
1066 if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
1067 return -EIO;
1068
1069 /* 0 - id, 1 - no_of_frontends */
1070 b[0] = (0 << 8) | 1;
1071 /* 0 = i2c-address demod, 0 = tuner */
1072 b[1] = (0 << 8) | (0);
1073 b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
1074 b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
1075 b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
1076 b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
1077 b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
1078 b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
1079 b[29] = state->chip.d9.cfg.if_drives;
1080 if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0)
1081 return -EIO;
1082
1083 if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0)
1084 return -EIO;
1085
1086 if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0)
1087 return -EIO;
1088
1089 if (size > ARRAY_SIZE(b)) {
1090 dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size,
1091 (int)ARRAY_SIZE(b));
1092 return -EINVAL;
1093 }
1094
1095 for (i = 0; i < size; i += 2) {
1096 state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
1097 state->platform.risc.fe_mm[i / 2].size = b[i + 1];
1098 }
1099
1100 return 0;
1101}
1102
1103static void dib9000_fw_set_channel_head(struct dib9000_state *state, struct dvb_frontend_parameters *ch)
1104{
1105 u8 b[9];
1106 u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
1107 if (state->fe_id % 2)
1108 freq += 101;
1109
1110 b[0] = (u8) ((freq >> 0) & 0xff);
1111 b[1] = (u8) ((freq >> 8) & 0xff);
1112 b[2] = (u8) ((freq >> 16) & 0xff);
1113 b[3] = (u8) ((freq >> 24) & 0xff);
1114 b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff);
1115 b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff);
1116 b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff);
1117 b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff);
1118 b[8] = 0x80; /* do not wait for CELL ID when doing autosearch */
1119 if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT)
1120 b[8] |= 1;
1121 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
1122}
1123
1124static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
1125{
1126 struct dib9000_state *state = fe->demodulator_priv;
1127 struct dibDVBTChannel {
1128 s8 spectrum_inversion;
1129
1130 s8 nfft;
1131 s8 guard;
1132 s8 constellation;
1133
1134 s8 hrch;
1135 s8 alpha;
1136 s8 code_rate_hp;
1137 s8 code_rate_lp;
1138 s8 select_hp;
1139
1140 s8 intlv_native;
1141 };
1142 struct dibDVBTChannel ch;
1143 int ret = 0;
1144
1145 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
1146 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
1147 goto error;
1148 ret = -EIO;
1149 }
1150
1151 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) &ch, sizeof(struct dibDVBTChannel));
1152
1153 switch (ch.spectrum_inversion & 0x7) {
1154 case 1:
1155 state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
1156 break;
1157 case 0:
1158 state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF;
1159 break;
1160 default:
1161 case -1:
1162 state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
1163 break;
1164 }
1165 switch (ch.nfft) {
1166 case 0:
1167 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
1168 break;
1169 case 2:
1170 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
1171 break;
1172 case 1:
1173 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1174 break;
1175 default:
1176 case -1:
1177 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
1178 break;
1179 }
1180 switch (ch.guard) {
1181 case 0:
1182 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
1183 break;
1184 case 1:
1185 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
1186 break;
1187 case 2:
1188 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1189 break;
1190 case 3:
1191 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
1192 break;
1193 default:
1194 case -1:
1195 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
1196 break;
1197 }
1198 switch (ch.constellation) {
1199 case 2:
1200 state->fe[0]->dtv_property_cache.modulation = QAM_64;
1201 break;
1202 case 1:
1203 state->fe[0]->dtv_property_cache.modulation = QAM_16;
1204 break;
1205 case 0:
1206 state->fe[0]->dtv_property_cache.modulation = QPSK;
1207 break;
1208 default:
1209 case -1:
1210 state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
1211 break;
1212 }
1213 switch (ch.hrch) {
1214 case 0:
1215 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
1216 break;
1217 case 1:
1218 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1;
1219 break;
1220 default:
1221 case -1:
1222 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
1223 break;
1224 }
1225 switch (ch.code_rate_hp) {
1226 case 1:
1227 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
1228 break;
1229 case 2:
1230 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3;
1231 break;
1232 case 3:
1233 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4;
1234 break;
1235 case 5:
1236 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6;
1237 break;
1238 case 7:
1239 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8;
1240 break;
1241 default:
1242 case -1:
1243 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
1244 break;
1245 }
1246 switch (ch.code_rate_lp) {
1247 case 1:
1248 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
1249 break;
1250 case 2:
1251 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3;
1252 break;
1253 case 3:
1254 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4;
1255 break;
1256 case 5:
1257 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6;
1258 break;
1259 case 7:
1260 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8;
1261 break;
1262 default:
1263 case -1:
1264 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO;
1265 break;
1266 }
1267
1268error:
1269 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1270 return ret;
1271}
1272
1273static int dib9000_fw_set_channel_union(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
1274{
1275 struct dib9000_state *state = fe->demodulator_priv;
1276 struct dibDVBTChannel {
1277 s8 spectrum_inversion;
1278
1279 s8 nfft;
1280 s8 guard;
1281 s8 constellation;
1282
1283 s8 hrch;
1284 s8 alpha;
1285 s8 code_rate_hp;
1286 s8 code_rate_lp;
1287 s8 select_hp;
1288
1289 s8 intlv_native;
1290 };
1291 struct dibDVBTChannel ch;
1292
1293 switch (state->fe[0]->dtv_property_cache.inversion) {
1294 case INVERSION_ON:
1295 ch.spectrum_inversion = 1;
1296 break;
1297 case INVERSION_OFF:
1298 ch.spectrum_inversion = 0;
1299 break;
1300 default:
1301 case INVERSION_AUTO:
1302 ch.spectrum_inversion = -1;
1303 break;
1304 }
1305 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1306 case TRANSMISSION_MODE_2K:
1307 ch.nfft = 0;
1308 break;
1309 case TRANSMISSION_MODE_4K:
1310 ch.nfft = 2;
1311 break;
1312 case TRANSMISSION_MODE_8K:
1313 ch.nfft = 1;
1314 break;
1315 default:
1316 case TRANSMISSION_MODE_AUTO:
1317 ch.nfft = 1;
1318 break;
1319 }
1320 switch (state->fe[0]->dtv_property_cache.guard_interval) {
1321 case GUARD_INTERVAL_1_32:
1322 ch.guard = 0;
1323 break;
1324 case GUARD_INTERVAL_1_16:
1325 ch.guard = 1;
1326 break;
1327 case GUARD_INTERVAL_1_8:
1328 ch.guard = 2;
1329 break;
1330 case GUARD_INTERVAL_1_4:
1331 ch.guard = 3;
1332 break;
1333 default:
1334 case GUARD_INTERVAL_AUTO:
1335 ch.guard = -1;
1336 break;
1337 }
1338 switch (state->fe[0]->dtv_property_cache.modulation) {
1339 case QAM_64:
1340 ch.constellation = 2;
1341 break;
1342 case QAM_16:
1343 ch.constellation = 1;
1344 break;
1345 case QPSK:
1346 ch.constellation = 0;
1347 break;
1348 default:
1349 case QAM_AUTO:
1350 ch.constellation = -1;
1351 break;
1352 }
1353 switch (state->fe[0]->dtv_property_cache.hierarchy) {
1354 case HIERARCHY_NONE:
1355 ch.hrch = 0;
1356 break;
1357 case HIERARCHY_1:
1358 case HIERARCHY_2:
1359 case HIERARCHY_4:
1360 ch.hrch = 1;
1361 break;
1362 default:
1363 case HIERARCHY_AUTO:
1364 ch.hrch = -1;
1365 break;
1366 }
1367 ch.alpha = 1;
1368 switch (state->fe[0]->dtv_property_cache.code_rate_HP) {
1369 case FEC_1_2:
1370 ch.code_rate_hp = 1;
1371 break;
1372 case FEC_2_3:
1373 ch.code_rate_hp = 2;
1374 break;
1375 case FEC_3_4:
1376 ch.code_rate_hp = 3;
1377 break;
1378 case FEC_5_6:
1379 ch.code_rate_hp = 5;
1380 break;
1381 case FEC_7_8:
1382 ch.code_rate_hp = 7;
1383 break;
1384 default:
1385 case FEC_AUTO:
1386 ch.code_rate_hp = -1;
1387 break;
1388 }
1389 switch (state->fe[0]->dtv_property_cache.code_rate_LP) {
1390 case FEC_1_2:
1391 ch.code_rate_lp = 1;
1392 break;
1393 case FEC_2_3:
1394 ch.code_rate_lp = 2;
1395 break;
1396 case FEC_3_4:
1397 ch.code_rate_lp = 3;
1398 break;
1399 case FEC_5_6:
1400 ch.code_rate_lp = 5;
1401 break;
1402 case FEC_7_8:
1403 ch.code_rate_lp = 7;
1404 break;
1405 default:
1406 case FEC_AUTO:
1407 ch.code_rate_lp = -1;
1408 break;
1409 }
1410 ch.select_hp = 1;
1411 ch.intlv_native = 1;
1412
1413 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch);
1414
1415 return 0;
1416}
1417
1418static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
1419{
1420 struct dib9000_state *state = fe->demodulator_priv;
1421 int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1422 s8 i;
1423
1424 switch (state->tune_state) {
1425 case CT_DEMOD_START:
1426 dib9000_fw_set_channel_head(state, ch);
1427
1428 /* write the channel context - a channel is initialized to 0, so it is OK */
1429 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
1430 dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info);
1431
1432 if (search)
1433 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
1434 else {
1435 dib9000_fw_set_channel_union(fe, ch);
1436 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
1437 }
1438 state->tune_state = CT_DEMOD_STEP_1;
1439 break;
1440 case CT_DEMOD_STEP_1:
1441 if (search)
1442 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) &i, 1);
1443 else
1444 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) &i, 1);
1445 switch (i) { /* something happened */
1446 case 0:
1447 break;
1448 case -2: /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */
1449 if (search)
1450 state->status = FE_STATUS_DEMOD_SUCCESS;
1451 else {
1452 state->tune_state = CT_DEMOD_STOP;
1453 state->status = FE_STATUS_LOCKED;
1454 }
1455 break;
1456 default:
1457 state->status = FE_STATUS_TUNE_FAILED;
1458 state->tune_state = CT_DEMOD_STOP;
1459 break;
1460 }
1461 break;
1462 default:
1463 ret = FE_CALLBACK_TIME_NEVER;
1464 break;
1465 }
1466
1467 return ret;
1468}
1469
1470static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff)
1471{
1472 struct dib9000_state *state = fe->demodulator_priv;
1473 u16 mode = (u16) onoff;
1474 return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1);
1475}
1476
1477static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode)
1478{
1479 struct dib9000_state *state = fe->demodulator_priv;
1480 u16 outreg, smo_mode;
1481
1482 dprintk("setting output mode for demod %p to %d", fe, mode);
1483
1484 switch (mode) {
1485 case OUTMODE_MPEG2_PAR_GATED_CLK:
1486 outreg = (1 << 10); /* 0x0400 */
1487 break;
1488 case OUTMODE_MPEG2_PAR_CONT_CLK:
1489 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
1490 break;
1491 case OUTMODE_MPEG2_SERIAL:
1492 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
1493 break;
1494 case OUTMODE_DIVERSITY:
1495 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
1496 break;
1497 case OUTMODE_MPEG2_FIFO:
1498 outreg = (1 << 10) | (5 << 6);
1499 break;
1500 case OUTMODE_HIGH_Z:
1501 outreg = 0;
1502 break;
1503 default:
1504 dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]);
1505 return -EINVAL;
1506 }
1507
1508 dib9000_write_word(state, 1795, outreg);
1509
1510 switch (mode) {
1511 case OUTMODE_MPEG2_PAR_GATED_CLK:
1512 case OUTMODE_MPEG2_PAR_CONT_CLK:
1513 case OUTMODE_MPEG2_SERIAL:
1514 case OUTMODE_MPEG2_FIFO:
1515 smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1);
1516 if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
1517 smo_mode |= (1 << 5);
1518 dib9000_write_word(state, 295, smo_mode);
1519 break;
1520 }
1521
1522 outreg = to_fw_output_mode(mode);
1523 return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1);
1524}
1525
1526static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1527{
1528 struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1529 u16 i, len, t, index_msg;
1530
1531 for (index_msg = 0; index_msg < num; index_msg++) {
1532 if (msg[index_msg].flags & I2C_M_RD) { /* read */
1533 len = msg[index_msg].len;
1534 if (len > 16)
1535 len = 16;
1536
1537 if (dib9000_read_word(state, 790) != 0)
1538 dprintk("TunerITF: read busy");
1539
1540 dib9000_write_word(state, 784, (u16) (msg[index_msg].addr));
1541 dib9000_write_word(state, 787, (len / 2) - 1);
1542 dib9000_write_word(state, 786, 1); /* start read */
1543
1544 i = 1000;
1545 while (dib9000_read_word(state, 790) != (len / 2) && i)
1546 i--;
1547
1548 if (i == 0)
1549 dprintk("TunerITF: read failed");
1550
1551 for (i = 0; i < len; i += 2) {
1552 t = dib9000_read_word(state, 785);
1553 msg[index_msg].buf[i] = (t >> 8) & 0xff;
1554 msg[index_msg].buf[i + 1] = (t) & 0xff;
1555 }
1556 if (dib9000_read_word(state, 790) != 0)
1557 dprintk("TunerITF: read more data than expected");
1558 } else {
1559 i = 1000;
1560 while (dib9000_read_word(state, 789) && i)
1561 i--;
1562 if (i == 0)
1563 dprintk("TunerITF: write busy");
1564
1565 len = msg[index_msg].len;
1566 if (len > 16)
1567 len = 16;
1568
1569 for (i = 0; i < len; i += 2)
1570 dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]);
1571 dib9000_write_word(state, 784, (u16) msg[index_msg].addr);
1572 dib9000_write_word(state, 787, (len / 2) - 1);
1573 dib9000_write_word(state, 786, 0); /* start write */
1574
1575 i = 1000;
1576 while (dib9000_read_word(state, 791) > 0 && i)
1577 i--;
1578 if (i == 0)
1579 dprintk("TunerITF: write failed");
1580 }
1581 }
1582 return num;
1583}
1584
1585int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
1586{
1587 struct dib9000_state *state = fe->demodulator_priv;
1588
1589 state->component_bus_speed = speed;
1590 return 0;
1591}
1592EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed);
1593
1594static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1595{
1596 struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1597 u8 type = 0; /* I2C */
1598 u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
1599 u16 scl = state->component_bus_speed; /* SCL frequency */
1600 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
1601 u8 p[13] = { 0 };
1602
1603 p[0] = type;
1604 p[1] = port;
1605 p[2] = msg[0].addr << 1;
1606
1607 p[3] = (u8) scl & 0xff; /* scl */
1608 p[4] = (u8) (scl >> 8);
1609
1610 p[7] = 0;
1611 p[8] = 0;
1612
1613 p[9] = (u8) (msg[0].len);
1614 p[10] = (u8) (msg[0].len >> 8);
1615 if ((num > 1) && (msg[1].flags & I2C_M_RD)) {
1616 p[11] = (u8) (msg[1].len);
1617 p[12] = (u8) (msg[1].len >> 8);
1618 } else {
1619 p[11] = 0;
1620 p[12] = 0;
1621 }
1622
1623 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
1624
1625 dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p);
1626
1627 { /* write-part */
1628 dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0);
1629 dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len);
1630 }
1631
1632 /* do the transaction */
1633 if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) {
1634 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1635 return 0;
1636 }
1637
1638 /* read back any possible result */
1639 if ((num > 1) && (msg[1].flags & I2C_M_RD))
1640 dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len);
1641
1642 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1643
1644 return num;
1645}
1646
1647static u32 dib9000_i2c_func(struct i2c_adapter *adapter)
1648{
1649 return I2C_FUNC_I2C;
1650}
1651
1652static struct i2c_algorithm dib9000_tuner_algo = {
1653 .master_xfer = dib9000_tuner_xfer,
1654 .functionality = dib9000_i2c_func,
1655};
1656
1657static struct i2c_algorithm dib9000_component_bus_algo = {
1658 .master_xfer = dib9000_fw_component_bus_xfer,
1659 .functionality = dib9000_i2c_func,
1660};
1661
1662struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
1663{
1664 struct dib9000_state *st = fe->demodulator_priv;
1665 return &st->tuner_adap;
1666}
1667EXPORT_SYMBOL(dib9000_get_tuner_interface);
1668
1669struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
1670{
1671 struct dib9000_state *st = fe->demodulator_priv;
1672 return &st->component_bus;
1673}
1674EXPORT_SYMBOL(dib9000_get_component_bus_interface);
1675
1676struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
1677{
1678 struct dib9000_state *st = fe->demodulator_priv;
1679 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
1680}
1681EXPORT_SYMBOL(dib9000_get_i2c_master);
1682
1683int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
1684{
1685 struct dib9000_state *st = fe->demodulator_priv;
1686
1687 st->i2c.i2c_adap = i2c;
1688 return 0;
1689}
1690EXPORT_SYMBOL(dib9000_set_i2c_adapter);
1691
1692static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
1693{
1694 st->gpio_dir = dib9000_read_word(st, 773);
1695 st->gpio_dir &= ~(1 << num); /* reset the direction bit */
1696 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
1697 dib9000_write_word(st, 773, st->gpio_dir);
1698
1699 st->gpio_val = dib9000_read_word(st, 774);
1700 st->gpio_val &= ~(1 << num); /* reset the direction bit */
1701 st->gpio_val |= (val & 0x01) << num; /* set the new value */
1702 dib9000_write_word(st, 774, st->gpio_val);
1703
1704 dprintk("gpio dir: %04x: gpio val: %04x", st->gpio_dir, st->gpio_val);
1705
1706 return 0;
1707}
1708
1709int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
1710{
1711 struct dib9000_state *state = fe->demodulator_priv;
1712 return dib9000_cfg_gpio(state, num, dir, val);
1713}
1714EXPORT_SYMBOL(dib9000_set_gpio);
1715
1716int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1717{
1718 struct dib9000_state *state = fe->demodulator_priv;
1719 u16 val = dib9000_read_word(state, 294 + 1) & 0xffef;
1720 val |= (onoff & 0x1) << 4;
1721
1722 dprintk("PID filter enabled %d", onoff);
1723 return dib9000_write_word(state, 294 + 1, val);
1724}
1725EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
1726
1727int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1728{
1729 struct dib9000_state *state = fe->demodulator_priv;
1730 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
1731 return dib9000_write_word(state, 300 + 1 + id, onoff ? (1 << 13) | pid : 0);
1732}
1733EXPORT_SYMBOL(dib9000_fw_pid_filter);
1734
1735int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
1736{
1737 struct dib9000_state *state = fe->demodulator_priv;
1738 return dib9000_fw_init(state);
1739}
1740EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
1741
1742static void dib9000_release(struct dvb_frontend *demod)
1743{
1744 struct dib9000_state *st = demod->demodulator_priv;
1745 u8 index_frontend;
1746
1747 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
1748 dvb_frontend_detach(st->fe[index_frontend]);
1749
1750 DibFreeLock(&state->platform.risc.mbx_if_lock);
1751 DibFreeLock(&state->platform.risc.mbx_lock);
1752 DibFreeLock(&state->platform.risc.mem_lock);
1753 DibFreeLock(&state->platform.risc.mem_mbx_lock);
1754 dibx000_exit_i2c_master(&st->i2c_master);
1755
1756 i2c_del_adapter(&st->tuner_adap);
1757 i2c_del_adapter(&st->component_bus);
1758 kfree(st->fe[0]);
1759 kfree(st);
1760}
1761
1762static int dib9000_wakeup(struct dvb_frontend *fe)
1763{
1764 return 0;
1765}
1766
1767static int dib9000_sleep(struct dvb_frontend *fe)
1768{
1769 struct dib9000_state *state = fe->demodulator_priv;
1770 u8 index_frontend;
1771 int ret;
1772
1773 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1774 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
1775 if (ret < 0)
1776 return ret;
1777 }
1778 return dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0);
1779}
1780
1781static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1782{
1783 tune->min_delay_ms = 1000;
1784 return 0;
1785}
1786
1787static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1788{
1789 struct dib9000_state *state = fe->demodulator_priv;
1790 u8 index_frontend, sub_index_frontend;
1791 fe_status_t stat;
1792 int ret;
1793
1794 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1795 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
1796 if (stat & FE_HAS_SYNC) {
1797 dprintk("TPS lock on the slave%i", index_frontend);
1798
1799 /* synchronize the cache with the other frontends */
1800 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
1801 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
1802 sub_index_frontend++) {
1803 if (sub_index_frontend != index_frontend) {
1804 state->fe[sub_index_frontend]->dtv_property_cache.modulation =
1805 state->fe[index_frontend]->dtv_property_cache.modulation;
1806 state->fe[sub_index_frontend]->dtv_property_cache.inversion =
1807 state->fe[index_frontend]->dtv_property_cache.inversion;
1808 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode =
1809 state->fe[index_frontend]->dtv_property_cache.transmission_mode;
1810 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval =
1811 state->fe[index_frontend]->dtv_property_cache.guard_interval;
1812 state->fe[sub_index_frontend]->dtv_property_cache.hierarchy =
1813 state->fe[index_frontend]->dtv_property_cache.hierarchy;
1814 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP =
1815 state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
1816 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP =
1817 state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
1818 state->fe[sub_index_frontend]->dtv_property_cache.rolloff =
1819 state->fe[index_frontend]->dtv_property_cache.rolloff;
1820 }
1821 }
1822 return 0;
1823 }
1824 }
1825
1826 /* get the channel from master chip */
1827 ret = dib9000_fw_get_channel(fe, fep);
1828 if (ret != 0)
1829 return ret;
1830
1831 /* synchronize the cache with the other frontends */
1832 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1833 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
1834 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
1835 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
1836 state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation;
1837 state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy;
1838 state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP;
1839 state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP;
1840 state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff;
1841 }
1842
1843 return 0;
1844}
1845
1846static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
1847{
1848 struct dib9000_state *state = fe->demodulator_priv;
1849 state->tune_state = tune_state;
1850 if (tune_state == CT_DEMOD_START)
1851 state->status = FE_STATUS_TUNE_PENDING;
1852
1853 return 0;
1854}
1855
1856static u32 dib9000_get_status(struct dvb_frontend *fe)
1857{
1858 struct dib9000_state *state = fe->demodulator_priv;
1859 return state->status;
1860}
1861
1862static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status)
1863{
1864 struct dib9000_state *state = fe->demodulator_priv;
1865
1866 memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext));
1867 return 0;
1868}
1869
1870static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1871{
1872 struct dib9000_state *state = fe->demodulator_priv;
1873 int sleep_time, sleep_time_slave;
1874 u32 frontend_status;
1875 u8 nbr_pending, exit_condition, index_frontend, index_frontend_success;
1876 struct dvb_frontend_parametersContext channel_status;
1877
1878 /* check that the correct parameters are set */
1879 if (state->fe[0]->dtv_property_cache.frequency == 0) {
1880 dprintk("dib9000: must specify frequency ");
1881 return 0;
1882 }
1883
1884 if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
1885 dprintk("dib9000: must specify bandwidth ");
1886 return 0;
1887 }
1888 fe->dtv_property_cache.delivery_system = SYS_DVBT;
1889
1890 /* set the master status */
1891 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
1892 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1893 /* no channel specified, autosearch the channel */
1894 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1895 } else
1896 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
1897
1898 /* set mode and status for the different frontends */
1899 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1900 dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
1901
1902 /* synchronization of the cache */
1903 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
1904
1905 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT;
1906 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
1907
1908 dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status);
1909 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
1910 }
1911
1912 /* actual tune */
1913 exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
1914 index_frontend_success = 0;
1915 do {
1916 sleep_time = dib9000_fw_tune(state->fe[0], NULL);
1917 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1918 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
1919 if (sleep_time == FE_CALLBACK_TIME_NEVER)
1920 sleep_time = sleep_time_slave;
1921 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
1922 sleep_time = sleep_time_slave;
1923 }
1924 if (sleep_time != FE_CALLBACK_TIME_NEVER)
1925 msleep(sleep_time / 10);
1926 else
1927 break;
1928
1929 nbr_pending = 0;
1930 exit_condition = 0;
1931 index_frontend_success = 0;
1932 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1933 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
1934 if (frontend_status > -FE_STATUS_TUNE_PENDING) {
1935 exit_condition = 2; /* tune success */
1936 index_frontend_success = index_frontend;
1937 break;
1938 }
1939 if (frontend_status == -FE_STATUS_TUNE_PENDING)
1940 nbr_pending++; /* some frontends are still tuning */
1941 }
1942 if ((exit_condition != 2) && (nbr_pending == 0))
1943 exit_condition = 1; /* if all tune are done and no success, exit: tune failed */
1944
1945 } while (exit_condition == 0);
1946
1947 /* check the tune result */
1948 if (exit_condition == 1) { /* tune failed */
1949 dprintk("tune failed");
1950 return 0;
1951 }
1952
1953 dprintk("tune success on frontend%i", index_frontend_success);
1954
1955 /* synchronize all the channel cache */
1956 dib9000_get_frontend(state->fe[0], fep);
1957
1958 /* retune the other frontends with the found channel */
1959 channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
1960 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1961 /* only retune the frontends which was not tuned success */
1962 if (index_frontend != index_frontend_success) {
1963 dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
1964 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
1965 }
1966 }
1967 do {
1968 sleep_time = FE_CALLBACK_TIME_NEVER;
1969 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1970 if (index_frontend != index_frontend_success) {
1971 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
1972 if (sleep_time == FE_CALLBACK_TIME_NEVER)
1973 sleep_time = sleep_time_slave;
1974 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
1975 sleep_time = sleep_time_slave;
1976 }
1977 }
1978 if (sleep_time != FE_CALLBACK_TIME_NEVER)
1979 msleep(sleep_time / 10);
1980 else
1981 break;
1982
1983 nbr_pending = 0;
1984 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1985 if (index_frontend != index_frontend_success) {
1986 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
1987 if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
1988 nbr_pending++; /* some frontends are still tuning */
1989 }
1990 }
1991 } while (nbr_pending != 0);
1992
1993 /* set the output mode */
1994 dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
1995 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
1996 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
1997
1998 /* turn off the diversity for the last frontend */
1999 dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0);
2000
2001 return 0;
2002}
2003
2004static u16 dib9000_read_lock(struct dvb_frontend *fe)
2005{
2006 struct dib9000_state *state = fe->demodulator_priv;
2007
2008 return dib9000_read_word(state, 535);
2009}
2010
2011static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2012{
2013 struct dib9000_state *state = fe->demodulator_priv;
2014 u8 index_frontend;
2015 u16 lock = 0, lock_slave = 0;
2016
2017 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2018 lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
2019
2020 lock = dib9000_read_word(state, 535);
2021
2022 *stat = 0;
2023
2024 if ((lock & 0x8000) || (lock_slave & 0x8000))
2025 *stat |= FE_HAS_SIGNAL;
2026 if ((lock & 0x3000) || (lock_slave & 0x3000))
2027 *stat |= FE_HAS_CARRIER;
2028 if ((lock & 0x0100) || (lock_slave & 0x0100))
2029 *stat |= FE_HAS_VITERBI;
2030 if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38))
2031 *stat |= FE_HAS_SYNC;
2032 if ((lock & 0x0008) || (lock_slave & 0x0008))
2033 *stat |= FE_HAS_LOCK;
2034
2035 return 0;
2036}
2037
2038static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
2039{
2040 struct dib9000_state *state = fe->demodulator_priv;
2041 u16 c[16];
2042
2043 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2044 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2045 return -EIO;
2046 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2047 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2048
2049 *ber = c[10] << 16 | c[11];
2050 return 0;
2051}
2052
2053static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2054{
2055 struct dib9000_state *state = fe->demodulator_priv;
2056 u8 index_frontend;
2057 u16 c[16];
2058 u16 val;
2059
2060 *strength = 0;
2061 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2062 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
2063 if (val > 65535 - *strength)
2064 *strength = 65535;
2065 else
2066 *strength += val;
2067 }
2068
2069 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2070 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2071 return -EIO;
2072 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2073 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2074
2075 val = 65535 - c[4];
2076 if (val > 65535 - *strength)
2077 *strength = 65535;
2078 else
2079 *strength += val;
2080 return 0;
2081}
2082
2083static u32 dib9000_get_snr(struct dvb_frontend *fe)
2084{
2085 struct dib9000_state *state = fe->demodulator_priv;
2086 u16 c[16];
2087 u32 n, s, exp;
2088 u16 val;
2089
2090 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2091 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2092 return -EIO;
2093 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2094 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2095
2096 val = c[7];
2097 n = (val >> 4) & 0xff;
2098 exp = ((val & 0xf) << 2);
2099 val = c[8];
2100 exp += ((val >> 14) & 0x3);
2101 if ((exp & 0x20) != 0)
2102 exp -= 0x40;
2103 n <<= exp + 16;
2104
2105 s = (val >> 6) & 0xFF;
2106 exp = (val & 0x3F);
2107 if ((exp & 0x20) != 0)
2108 exp -= 0x40;
2109 s <<= exp + 16;
2110
2111 if (n > 0) {
2112 u32 t = (s / n) << 16;
2113 return t + ((s << 16) - n * t) / n;
2114 }
2115 return 0xffffffff;
2116}
2117
2118static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr)
2119{
2120 struct dib9000_state *state = fe->demodulator_priv;
2121 u8 index_frontend;
2122 u32 snr_master;
2123
2124 snr_master = dib9000_get_snr(fe);
2125 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2126 snr_master += dib9000_get_snr(state->fe[index_frontend]);
2127
2128 if ((snr_master >> 16) != 0) {
2129 snr_master = 10 * intlog10(snr_master >> 16);
2130 *snr = snr_master / ((1 << 24) / 10);
2131 } else
2132 *snr = 0;
2133
2134 return 0;
2135}
2136
2137static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
2138{
2139 struct dib9000_state *state = fe->demodulator_priv;
2140 u16 c[16];
2141
2142 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2143 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2144 return -EIO;
2145 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2146 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2147
2148 *unc = c[12];
2149 return 0;
2150}
2151
2152int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
2153{
2154 int k = 0;
2155 u8 new_addr = 0;
2156 struct i2c_device client = {.i2c_adap = i2c };
2157
2158 client.i2c_addr = default_addr + 16;
2159 dib9000_i2c_write16(&client, 1796, 0x0);
2160
2161 for (k = no_of_demods - 1; k >= 0; k--) {
2162 /* designated i2c address */
2163 new_addr = first_addr + (k << 1);
2164 client.i2c_addr = default_addr;
2165
2166 dib9000_i2c_write16(&client, 1817, 3);
2167 dib9000_i2c_write16(&client, 1796, 0);
2168 dib9000_i2c_write16(&client, 1227, 1);
2169 dib9000_i2c_write16(&client, 1227, 0);
2170
2171 client.i2c_addr = new_addr;
2172 dib9000_i2c_write16(&client, 1817, 3);
2173 dib9000_i2c_write16(&client, 1796, 0);
2174 dib9000_i2c_write16(&client, 1227, 1);
2175 dib9000_i2c_write16(&client, 1227, 0);
2176
2177 if (dib9000_identify(&client) == 0) {
2178 client.i2c_addr = default_addr;
2179 if (dib9000_identify(&client) == 0) {
2180 dprintk("DiB9000 #%d: not identified", k);
2181 return -EIO;
2182 }
2183 }
2184
2185 dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6));
2186 dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2);
2187
2188 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
2189 }
2190
2191 for (k = 0; k < no_of_demods; k++) {
2192 new_addr = first_addr | (k << 1);
2193 client.i2c_addr = new_addr;
2194
2195 dib9000_i2c_write16(&client, 1794, (new_addr << 2));
2196 dib9000_i2c_write16(&client, 1795, 0);
2197 }
2198
2199 return 0;
2200}
2201EXPORT_SYMBOL(dib9000_i2c_enumeration);
2202
2203int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
2204{
2205 struct dib9000_state *state = fe->demodulator_priv;
2206 u8 index_frontend = 1;
2207
2208 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2209 index_frontend++;
2210 if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
2211 dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
2212 state->fe[index_frontend] = fe_slave;
2213 return 0;
2214 }
2215
2216 dprintk("too many slave frontend");
2217 return -ENOMEM;
2218}
2219EXPORT_SYMBOL(dib9000_set_slave_frontend);
2220
2221int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
2222{
2223 struct dib9000_state *state = fe->demodulator_priv;
2224 u8 index_frontend = 1;
2225
2226 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2227 index_frontend++;
2228 if (index_frontend != 1) {
2229 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1);
2230 state->fe[index_frontend] = NULL;
2231 return 0;
2232 }
2233
2234 dprintk("no frontend to be removed");
2235 return -ENODEV;
2236}
2237EXPORT_SYMBOL(dib9000_remove_slave_frontend);
2238
2239struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
2240{
2241 struct dib9000_state *state = fe->demodulator_priv;
2242
2243 if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
2244 return NULL;
2245 return state->fe[slave_index];
2246}
2247EXPORT_SYMBOL(dib9000_get_slave_frontend);
2248
2249static struct dvb_frontend_ops dib9000_ops;
2250struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg)
2251{
2252 struct dvb_frontend *fe;
2253 struct dib9000_state *st;
2254 st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL);
2255 if (st == NULL)
2256 return NULL;
2257 fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
2258 if (fe == NULL)
2259 return NULL;
2260
2261 memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
2262 st->i2c.i2c_adap = i2c_adap;
2263 st->i2c.i2c_addr = i2c_addr;
2264
2265 st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
2266 st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
2267 st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS;
2268
2269 DibInitLock(&st->platform.risc.mbx_if_lock);
2270 DibInitLock(&st->platform.risc.mbx_lock);
2271 DibInitLock(&st->platform.risc.mem_lock);
2272 DibInitLock(&st->platform.risc.mem_mbx_lock);
2273
2274 st->fe[0] = fe;
2275 fe->demodulator_priv = st;
2276 memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops));
2277
2278 /* Ensure the output mode remains at the previous default if it's
2279 * not specifically set by the caller.
2280 */
2281 if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2282 st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;
2283
2284 if (dib9000_identify(&st->i2c) == 0)
2285 goto error;
2286
2287 dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr);
2288
2289 st->tuner_adap.dev.parent = i2c_adap->dev.parent;
2290 strncpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS", sizeof(st->tuner_adap.name));
2291 st->tuner_adap.algo = &dib9000_tuner_algo;
2292 st->tuner_adap.algo_data = NULL;
2293 i2c_set_adapdata(&st->tuner_adap, st);
2294 if (i2c_add_adapter(&st->tuner_adap) < 0)
2295 goto error;
2296
2297 st->component_bus.dev.parent = i2c_adap->dev.parent;
2298 strncpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st->component_bus.name));
2299 st->component_bus.algo = &dib9000_component_bus_algo;
2300 st->component_bus.algo_data = NULL;
2301 st->component_bus_speed = 340;
2302 i2c_set_adapdata(&st->component_bus, st);
2303 if (i2c_add_adapter(&st->component_bus) < 0)
2304 goto component_bus_add_error;
2305
2306 dib9000_fw_reset(fe);
2307
2308 return fe;
2309
2310component_bus_add_error:
2311 i2c_del_adapter(&st->tuner_adap);
2312error:
2313 kfree(st);
2314 return NULL;
2315}
2316EXPORT_SYMBOL(dib9000_attach);
2317
2318static struct dvb_frontend_ops dib9000_ops = {
2319 .info = {
2320 .name = "DiBcom 9000",
2321 .type = FE_OFDM,
2322 .frequency_min = 44250000,
2323 .frequency_max = 867250000,
2324 .frequency_stepsize = 62500,
2325 .caps = FE_CAN_INVERSION_AUTO |
2326 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2327 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2328 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2329 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2330 },
2331
2332 .release = dib9000_release,
2333
2334 .init = dib9000_wakeup,
2335 .sleep = dib9000_sleep,
2336
2337 .set_frontend = dib9000_set_frontend,
2338 .get_tune_settings = dib9000_fe_get_tune_settings,
2339 .get_frontend = dib9000_get_frontend,
2340
2341 .read_status = dib9000_read_status,
2342 .read_ber = dib9000_read_ber,
2343 .read_signal_strength = dib9000_read_signal_strength,
2344 .read_snr = dib9000_read_snr,
2345 .read_ucblocks = dib9000_read_unc_blocks,
2346};
2347
2348MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
2349MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
2350MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
2351MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/dib9000.h b/drivers/media/dvb/frontends/dib9000.h
new file mode 100644
index 000000000000..b5781a48034c
--- /dev/null
+++ b/drivers/media/dvb/frontends/dib9000.h
@@ -0,0 +1,131 @@
1#ifndef DIB9000_H
2#define DIB9000_H
3
4#include "dibx000_common.h"
5
6struct dib9000_config {
7 u8 dvbt_mode;
8 u8 output_mpeg2_in_188_bytes;
9 u8 hostbus_diversity;
10 struct dibx000_bandwidth_config *bw;
11
12 u16 if_drives;
13
14 u32 timing_frequency;
15 u32 xtal_clock_khz;
16 u32 vcxo_timer;
17 u32 demod_clock_khz;
18
19 const u8 *microcode_B_fe_buffer;
20 u32 microcode_B_fe_size;
21
22 struct dibGPIOFunction gpio_function[2];
23 struct dibSubbandSelection subband;
24
25 u8 output_mode;
26};
27
28#define DEFAULT_DIB9000_I2C_ADDRESS 18
29
30#if defined(CONFIG_DVB_DIB9000) || (defined(CONFIG_DVB_DIB9000_MODULE) && defined(MODULE))
31extern struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg);
32extern int dib9000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr);
33extern struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe);
34extern struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating);
35extern int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val);
36extern int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
37extern int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff);
38extern int dib9000_firmware_post_pll_init(struct dvb_frontend *fe);
39extern int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave);
40extern int dib9000_remove_slave_frontend(struct dvb_frontend *fe);
41extern struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index);
42extern struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe);
43extern int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c);
44extern int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed);
45#else
46static inline struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib9000_config *cfg)
47{
48 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
49 return NULL;
50}
51
52static inline struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
53{
54 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
55 return NULL;
56}
57
58static inline int dib9000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
59{
60 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
61 return -ENODEV;
62}
63
64static inline struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
65{
66 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
67 return NULL;
68}
69
70static inline int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
71{
72 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
73 return -ENODEV;
74}
75
76static inline int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
77{
78 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
79 return -ENODEV;
80}
81
82static inline int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
83{
84 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
85 return -ENODEV;
86}
87
88static inline int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
89{
90 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
91 return -ENODEV;
92}
93
94static inline int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
95{
96 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
97 return -ENODEV;
98}
99
100int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
101{
102 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
103 return -ENODEV;
104}
105
106static inline struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
107{
108 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
109 return NULL;
110}
111
112static inline struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
113{
114 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
115 return NULL;
116}
117
118static inline int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
119{
120 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
121 return -ENODEV;
122}
123
124static inline int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
125{
126 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
127 return -ENODEV;
128}
129#endif
130
131#endif
diff --git a/drivers/media/dvb/frontends/dibx000_common.c b/drivers/media/dvb/frontends/dibx000_common.c
index 2311c0a3406c..f6938f97feb4 100644
--- a/drivers/media/dvb/frontends/dibx000_common.c
+++ b/drivers/media/dvb/frontends/dibx000_common.c
@@ -17,9 +17,145 @@ static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val)
17 struct i2c_msg msg = { 17 struct i2c_msg msg = {
18 .addr = mst->i2c_addr,.flags = 0,.buf = b,.len = 4 18 .addr = mst->i2c_addr,.flags = 0,.buf = b,.len = 4
19 }; 19 };
20
20 return i2c_transfer(mst->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; 21 return i2c_transfer(mst->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
21} 22}
22 23
24static u16 dibx000_read_word(struct dibx000_i2c_master *mst, u16 reg)
25{
26 u8 wb[2] = { reg >> 8, reg & 0xff };
27 u8 rb[2];
28 struct i2c_msg msg[2] = {
29 {.addr = mst->i2c_addr, .flags = 0, .buf = wb, .len = 2},
30 {.addr = mst->i2c_addr, .flags = I2C_M_RD, .buf = rb, .len = 2},
31 };
32
33 if (i2c_transfer(mst->i2c_adap, msg, 2) != 2)
34 dprintk("i2c read error on %d", reg);
35
36 return (rb[0] << 8) | rb[1];
37}
38
39static int dibx000_is_i2c_done(struct dibx000_i2c_master *mst)
40{
41 int i = 100;
42 u16 status;
43
44 while (((status = dibx000_read_word(mst, mst->base_reg + 2)) & 0x0100) == 0 && --i > 0)
45 ;
46
47 /* i2c timed out */
48 if (i == 0)
49 return -EREMOTEIO;
50
51 /* no acknowledge */
52 if ((status & 0x0080) == 0)
53 return -EREMOTEIO;
54
55 return 0;
56}
57
58static int dibx000_master_i2c_write(struct dibx000_i2c_master *mst, struct i2c_msg *msg, u8 stop)
59{
60 u16 data;
61 u16 da;
62 u16 i;
63 u16 txlen = msg->len, len;
64 const u8 *b = msg->buf;
65
66 while (txlen) {
67 dibx000_read_word(mst, mst->base_reg + 2);
68
69 len = txlen > 8 ? 8 : txlen;
70 for (i = 0; i < len; i += 2) {
71 data = *b++ << 8;
72 if (i+1 < len)
73 data |= *b++;
74 dibx000_write_word(mst, mst->base_reg, data);
75 }
76 da = (((u8) (msg->addr)) << 9) |
77 (1 << 8) |
78 (1 << 7) |
79 (0 << 6) |
80 (0 << 5) |
81 ((len & 0x7) << 2) |
82 (0 << 1) |
83 (0 << 0);
84
85 if (txlen == msg->len)
86 da |= 1 << 5; /* start */
87
88 if (txlen-len == 0 && stop)
89 da |= 1 << 6; /* stop */
90
91 dibx000_write_word(mst, mst->base_reg+1, da);
92
93 if (dibx000_is_i2c_done(mst) != 0)
94 return -EREMOTEIO;
95 txlen -= len;
96 }
97
98 return 0;
99}
100
101static int dibx000_master_i2c_read(struct dibx000_i2c_master *mst, struct i2c_msg *msg)
102{
103 u16 da;
104 u8 *b = msg->buf;
105 u16 rxlen = msg->len, len;
106
107 while (rxlen) {
108 len = rxlen > 8 ? 8 : rxlen;
109 da = (((u8) (msg->addr)) << 9) |
110 (1 << 8) |
111 (1 << 7) |
112 (0 << 6) |
113 (0 << 5) |
114 ((len & 0x7) << 2) |
115 (1 << 1) |
116 (0 << 0);
117
118 if (rxlen == msg->len)
119 da |= 1 << 5; /* start */
120
121 if (rxlen-len == 0)
122 da |= 1 << 6; /* stop */
123 dibx000_write_word(mst, mst->base_reg+1, da);
124
125 if (dibx000_is_i2c_done(mst) != 0)
126 return -EREMOTEIO;
127
128 rxlen -= len;
129
130 while (len) {
131 da = dibx000_read_word(mst, mst->base_reg);
132 *b++ = (da >> 8) & 0xff;
133 len--;
134 if (len >= 1) {
135 *b++ = da & 0xff;
136 len--;
137 }
138 }
139 }
140
141 return 0;
142}
143
144int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed)
145{
146 struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
147
148 if (mst->device_rev < DIB7000MC && speed < 235)
149 speed = 235;
150 return dibx000_write_word(mst, mst->base_reg + 3, (u16)(60000 / speed));
151
152}
153EXPORT_SYMBOL(dibx000_i2c_set_speed);
154
155static u32 dibx000_i2c_func(struct i2c_adapter *adapter)
156{
157 return I2C_FUNC_I2C;
158}
23 159
24static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst, 160static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst,
25 enum dibx000_i2c_interface intf) 161 enum dibx000_i2c_interface intf)
@@ -32,6 +168,60 @@ static int dibx000_i2c_select_interface(struct dibx000_i2c_master *mst,
32 return 0; 168 return 0;
33} 169}
34 170
171static int dibx000_i2c_master_xfer_gpio12(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
172{
173 struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
174 int msg_index;
175 int ret = 0;
176
177 dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_1_2);
178 for (msg_index = 0; msg_index < num; msg_index++) {
179 if (msg[msg_index].flags & I2C_M_RD) {
180 ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
181 if (ret != 0)
182 return 0;
183 } else {
184 ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
185 if (ret != 0)
186 return 0;
187 }
188 }
189
190 return num;
191}
192
193static int dibx000_i2c_master_xfer_gpio34(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
194{
195 struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
196 int msg_index;
197 int ret = 0;
198
199 dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_3_4);
200 for (msg_index = 0; msg_index < num; msg_index++) {
201 if (msg[msg_index].flags & I2C_M_RD) {
202 ret = dibx000_master_i2c_read(mst, &msg[msg_index]);
203 if (ret != 0)
204 return 0;
205 } else {
206 ret = dibx000_master_i2c_write(mst, &msg[msg_index], 1);
207 if (ret != 0)
208 return 0;
209 }
210 }
211
212 return num;
213}
214
215static struct i2c_algorithm dibx000_i2c_master_gpio12_xfer_algo = {
216 .master_xfer = dibx000_i2c_master_xfer_gpio12,
217 .functionality = dibx000_i2c_func,
218};
219
220static struct i2c_algorithm dibx000_i2c_master_gpio34_xfer_algo = {
221 .master_xfer = dibx000_i2c_master_xfer_gpio34,
222 .functionality = dibx000_i2c_func,
223};
224
35static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4], 225static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4],
36 u8 addr, int onoff) 226 u8 addr, int onoff)
37{ 227{
@@ -54,11 +244,37 @@ static int dibx000_i2c_gate_ctrl(struct dibx000_i2c_master *mst, u8 tx[4],
54 return 0; 244 return 0;
55} 245}
56 246
57static u32 dibx000_i2c_func(struct i2c_adapter *adapter) 247static int dibx000_i2c_gated_gpio67_xfer(struct i2c_adapter *i2c_adap,
248 struct i2c_msg msg[], int num)
58{ 249{
59 return I2C_FUNC_I2C; 250 struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
251 struct i2c_msg m[2 + num];
252 u8 tx_open[4], tx_close[4];
253
254 memset(m, 0, sizeof(struct i2c_msg) * (2 + num));
255
256 dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_6_7);
257
258 dibx000_i2c_gate_ctrl(mst, tx_open, msg[0].addr, 1);
259 m[0].addr = mst->i2c_addr;
260 m[0].buf = tx_open;
261 m[0].len = 4;
262
263 memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
264
265 dibx000_i2c_gate_ctrl(mst, tx_close, 0, 0);
266 m[num + 1].addr = mst->i2c_addr;
267 m[num + 1].buf = tx_close;
268 m[num + 1].len = 4;
269
270 return i2c_transfer(mst->i2c_adap, m, 2 + num) == 2 + num ? num : -EIO;
60} 271}
61 272
273static struct i2c_algorithm dibx000_i2c_gated_gpio67_algo = {
274 .master_xfer = dibx000_i2c_gated_gpio67_xfer,
275 .functionality = dibx000_i2c_func,
276};
277
62static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap, 278static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap,
63 struct i2c_msg msg[], int num) 279 struct i2c_msg msg[], int num)
64{ 280{
@@ -91,8 +307,8 @@ static struct i2c_algorithm dibx000_i2c_gated_tuner_algo = {
91}; 307};
92 308
93struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst, 309struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst,
94 enum dibx000_i2c_interface intf, 310 enum dibx000_i2c_interface intf,
95 int gating) 311 int gating)
96{ 312{
97 struct i2c_adapter *i2c = NULL; 313 struct i2c_adapter *i2c = NULL;
98 314
@@ -101,6 +317,18 @@ struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst,
101 if (gating) 317 if (gating)
102 i2c = &mst->gated_tuner_i2c_adap; 318 i2c = &mst->gated_tuner_i2c_adap;
103 break; 319 break;
320 case DIBX000_I2C_INTERFACE_GPIO_1_2:
321 if (!gating)
322 i2c = &mst->master_i2c_adap_gpio12;
323 break;
324 case DIBX000_I2C_INTERFACE_GPIO_3_4:
325 if (!gating)
326 i2c = &mst->master_i2c_adap_gpio34;
327 break;
328 case DIBX000_I2C_INTERFACE_GPIO_6_7:
329 if (gating)
330 i2c = &mst->master_i2c_adap_gpio67;
331 break;
104 default: 332 default:
105 printk(KERN_ERR "DiBX000: incorrect I2C interface selected\n"); 333 printk(KERN_ERR "DiBX000: incorrect I2C interface selected\n");
106 break; 334 break;
@@ -126,8 +354,8 @@ void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst)
126EXPORT_SYMBOL(dibx000_reset_i2c_master); 354EXPORT_SYMBOL(dibx000_reset_i2c_master);
127 355
128static int i2c_adapter_init(struct i2c_adapter *i2c_adap, 356static int i2c_adapter_init(struct i2c_adapter *i2c_adap,
129 struct i2c_algorithm *algo, const char *name, 357 struct i2c_algorithm *algo, const char *name,
130 struct dibx000_i2c_master *mst) 358 struct dibx000_i2c_master *mst)
131{ 359{
132 strncpy(i2c_adap->name, name, sizeof(i2c_adap->name)); 360 strncpy(i2c_adap->name, name, sizeof(i2c_adap->name));
133 i2c_adap->algo = algo; 361 i2c_adap->algo = algo;
@@ -139,7 +367,7 @@ static int i2c_adapter_init(struct i2c_adapter *i2c_adap,
139} 367}
140 368
141int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev, 369int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev,
142 struct i2c_adapter *i2c_adap, u8 i2c_addr) 370 struct i2c_adapter *i2c_adap, u8 i2c_addr)
143{ 371{
144 u8 tx[4]; 372 u8 tx[4];
145 struct i2c_msg m = {.addr = i2c_addr >> 1,.buf = tx,.len = 4 }; 373 struct i2c_msg m = {.addr = i2c_addr >> 1,.buf = tx,.len = 4 };
@@ -153,11 +381,33 @@ int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev,
153 else 381 else
154 mst->base_reg = 768; 382 mst->base_reg = 768;
155 383
384 mst->gated_tuner_i2c_adap.dev.parent = mst->i2c_adap->dev.parent;
385 if (i2c_adapter_init
386 (&mst->gated_tuner_i2c_adap, &dibx000_i2c_gated_tuner_algo,
387 "DiBX000 tuner I2C bus", mst) != 0)
388 printk(KERN_ERR
389 "DiBX000: could not initialize the tuner i2c_adapter\n");
390
391 mst->master_i2c_adap_gpio12.dev.parent = mst->i2c_adap->dev.parent;
392 if (i2c_adapter_init
393 (&mst->master_i2c_adap_gpio12, &dibx000_i2c_master_gpio12_xfer_algo,
394 "DiBX000 master GPIO12 I2C bus", mst) != 0)
395 printk(KERN_ERR
396 "DiBX000: could not initialize the master i2c_adapter\n");
397
398 mst->master_i2c_adap_gpio34.dev.parent = mst->i2c_adap->dev.parent;
399 if (i2c_adapter_init
400 (&mst->master_i2c_adap_gpio34, &dibx000_i2c_master_gpio34_xfer_algo,
401 "DiBX000 master GPIO34 I2C bus", mst) != 0)
402 printk(KERN_ERR
403 "DiBX000: could not initialize the master i2c_adapter\n");
404
405 mst->master_i2c_adap_gpio67.dev.parent = mst->i2c_adap->dev.parent;
156 if (i2c_adapter_init 406 if (i2c_adapter_init
157 (&mst->gated_tuner_i2c_adap, &dibx000_i2c_gated_tuner_algo, 407 (&mst->master_i2c_adap_gpio67, &dibx000_i2c_gated_gpio67_algo,
158 "DiBX000 tuner I2C bus", mst) != 0) 408 "DiBX000 master GPIO67 I2C bus", mst) != 0)
159 printk(KERN_ERR 409 printk(KERN_ERR
160 "DiBX000: could not initialize the tuner i2c_adapter\n"); 410 "DiBX000: could not initialize the master i2c_adapter\n");
161 411
162 /* initialize the i2c-master by closing the gate */ 412 /* initialize the i2c-master by closing the gate */
163 dibx000_i2c_gate_ctrl(mst, tx, 0, 0); 413 dibx000_i2c_gate_ctrl(mst, tx, 0, 0);
@@ -170,16 +420,19 @@ EXPORT_SYMBOL(dibx000_init_i2c_master);
170void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst) 420void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst)
171{ 421{
172 i2c_del_adapter(&mst->gated_tuner_i2c_adap); 422 i2c_del_adapter(&mst->gated_tuner_i2c_adap);
423 i2c_del_adapter(&mst->master_i2c_adap_gpio12);
424 i2c_del_adapter(&mst->master_i2c_adap_gpio34);
425 i2c_del_adapter(&mst->master_i2c_adap_gpio67);
173} 426}
174EXPORT_SYMBOL(dibx000_exit_i2c_master); 427EXPORT_SYMBOL(dibx000_exit_i2c_master);
175 428
176 429
177u32 systime(void) 430u32 systime(void)
178{ 431{
179 struct timespec t; 432 struct timespec t;
180 433
181 t = current_kernel_time(); 434 t = current_kernel_time();
182 return (t.tv_sec * 10000) + (t.tv_nsec / 100000); 435 return (t.tv_sec * 10000) + (t.tv_nsec / 100000);
183} 436}
184EXPORT_SYMBOL(systime); 437EXPORT_SYMBOL(systime);
185 438
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h
index 4f5d141a308d..977d343369aa 100644
--- a/drivers/media/dvb/frontends/dibx000_common.h
+++ b/drivers/media/dvb/frontends/dibx000_common.h
@@ -4,7 +4,8 @@
4enum dibx000_i2c_interface { 4enum dibx000_i2c_interface {
5 DIBX000_I2C_INTERFACE_TUNER = 0, 5 DIBX000_I2C_INTERFACE_TUNER = 0,
6 DIBX000_I2C_INTERFACE_GPIO_1_2 = 1, 6 DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
7 DIBX000_I2C_INTERFACE_GPIO_3_4 = 2 7 DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
8 DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
8}; 9};
9 10
10struct dibx000_i2c_master { 11struct dibx000_i2c_master {
@@ -17,8 +18,11 @@ struct dibx000_i2c_master {
17 18
18 enum dibx000_i2c_interface selected_interface; 19 enum dibx000_i2c_interface selected_interface;
19 20
20// struct i2c_adapter tuner_i2c_adap; 21/* struct i2c_adapter tuner_i2c_adap; */
21 struct i2c_adapter gated_tuner_i2c_adap; 22 struct i2c_adapter gated_tuner_i2c_adap;
23 struct i2c_adapter master_i2c_adap_gpio12;
24 struct i2c_adapter master_i2c_adap_gpio34;
25 struct i2c_adapter master_i2c_adap_gpio67;
22 26
23 struct i2c_adapter *i2c_adap; 27 struct i2c_adapter *i2c_adap;
24 u8 i2c_addr; 28 u8 i2c_addr;
@@ -27,14 +31,15 @@ struct dibx000_i2c_master {
27}; 31};
28 32
29extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, 33extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
30 u16 device_rev, struct i2c_adapter *i2c_adap, 34 u16 device_rev, struct i2c_adapter *i2c_adap,
31 u8 i2c_addr); 35 u8 i2c_addr);
32extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master 36extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
33 *mst, 37 *mst,
34 enum dibx000_i2c_interface 38 enum dibx000_i2c_interface
35 intf, int gating); 39 intf, int gating);
36extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst); 40extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
37extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst); 41extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
42extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);
38 43
39extern u32 systime(void); 44extern u32 systime(void);
40 45
@@ -42,7 +47,7 @@ extern u32 systime(void);
42#define BAND_UHF 0x02 47#define BAND_UHF 0x02
43#define BAND_VHF 0x04 48#define BAND_VHF 0x04
44#define BAND_SBAND 0x08 49#define BAND_SBAND 0x08
45#define BAND_FM 0x10 50#define BAND_FM 0x10
46#define BAND_CBAND 0x20 51#define BAND_CBAND 0x20
47 52
48#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \ 53#define BAND_OF_FREQUENCY(freq_kHz) ((freq_kHz) <= 170000 ? BAND_CBAND : \
@@ -135,9 +140,9 @@ enum dibx000_adc_states {
135 DIBX000_VBG_DISABLE, 140 DIBX000_VBG_DISABLE,
136}; 141};
137 142
138#define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ ? 8000 : \ 143#define BANDWIDTH_TO_KHZ(v) ((v) == BANDWIDTH_8_MHZ ? 8000 : \
139 (v) == BANDWIDTH_7_MHZ ? 7000 : \ 144 (v) == BANDWIDTH_7_MHZ ? 7000 : \
140 (v) == BANDWIDTH_6_MHZ ? 6000 : 8000 ) 145 (v) == BANDWIDTH_6_MHZ ? 6000 : 8000)
141 146
142#define BANDWIDTH_TO_INDEX(v) ( \ 147#define BANDWIDTH_TO_INDEX(v) ( \
143 (v) == 8000 ? BANDWIDTH_8_MHZ : \ 148 (v) == 8000 ? BANDWIDTH_8_MHZ : \
@@ -153,53 +158,57 @@ enum dibx000_adc_states {
153#define OUTMODE_MPEG2_FIFO 5 158#define OUTMODE_MPEG2_FIFO 5
154#define OUTMODE_ANALOG_ADC 6 159#define OUTMODE_ANALOG_ADC 6
155 160
161#define INPUT_MODE_OFF 0x11
162#define INPUT_MODE_DIVERSITY 0x12
163#define INPUT_MODE_MPEG 0x13
164
156enum frontend_tune_state { 165enum frontend_tune_state {
157 CT_TUNER_START = 10, 166 CT_TUNER_START = 10,
158 CT_TUNER_STEP_0, 167 CT_TUNER_STEP_0,
159 CT_TUNER_STEP_1, 168 CT_TUNER_STEP_1,
160 CT_TUNER_STEP_2, 169 CT_TUNER_STEP_2,
161 CT_TUNER_STEP_3, 170 CT_TUNER_STEP_3,
162 CT_TUNER_STEP_4, 171 CT_TUNER_STEP_4,
163 CT_TUNER_STEP_5, 172 CT_TUNER_STEP_5,
164 CT_TUNER_STEP_6, 173 CT_TUNER_STEP_6,
165 CT_TUNER_STEP_7, 174 CT_TUNER_STEP_7,
166 CT_TUNER_STOP, 175 CT_TUNER_STOP,
167 176
168 CT_AGC_START = 20, 177 CT_AGC_START = 20,
169 CT_AGC_STEP_0, 178 CT_AGC_STEP_0,
170 CT_AGC_STEP_1, 179 CT_AGC_STEP_1,
171 CT_AGC_STEP_2, 180 CT_AGC_STEP_2,
172 CT_AGC_STEP_3, 181 CT_AGC_STEP_3,
173 CT_AGC_STEP_4, 182 CT_AGC_STEP_4,
174 CT_AGC_STOP, 183 CT_AGC_STOP,
175 184
176 CT_DEMOD_START = 30, 185 CT_DEMOD_START = 30,
177 CT_DEMOD_STEP_1, 186 CT_DEMOD_STEP_1,
178 CT_DEMOD_STEP_2, 187 CT_DEMOD_STEP_2,
179 CT_DEMOD_STEP_3, 188 CT_DEMOD_STEP_3,
180 CT_DEMOD_STEP_4, 189 CT_DEMOD_STEP_4,
181 CT_DEMOD_STEP_5, 190 CT_DEMOD_STEP_5,
182 CT_DEMOD_STEP_6, 191 CT_DEMOD_STEP_6,
183 CT_DEMOD_STEP_7, 192 CT_DEMOD_STEP_7,
184 CT_DEMOD_STEP_8, 193 CT_DEMOD_STEP_8,
185 CT_DEMOD_STEP_9, 194 CT_DEMOD_STEP_9,
186 CT_DEMOD_STEP_10, 195 CT_DEMOD_STEP_10,
187 CT_DEMOD_SEARCH_NEXT = 41, 196 CT_DEMOD_SEARCH_NEXT = 41,
188 CT_DEMOD_STEP_LOCKED, 197 CT_DEMOD_STEP_LOCKED,
189 CT_DEMOD_STOP, 198 CT_DEMOD_STOP,
190 199
191 CT_DONE = 100, 200 CT_DONE = 100,
192 CT_SHUTDOWN, 201 CT_SHUTDOWN,
193 202
194}; 203};
195 204
196struct dvb_frontend_parametersContext { 205struct dvb_frontend_parametersContext {
197#define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01 206#define CHANNEL_STATUS_PARAMETERS_UNKNOWN 0x01
198#define CHANNEL_STATUS_PARAMETERS_SET 0x02 207#define CHANNEL_STATUS_PARAMETERS_SET 0x02
199 u8 status; 208 u8 status;
200 u32 tune_time_estimation[2]; 209 u32 tune_time_estimation[2];
201 s32 tps_available; 210 s32 tps_available;
202 u16 tps[9]; 211 u16 tps[9];
203}; 212};
204 213
205#define FE_STATUS_TUNE_FAILED 0 214#define FE_STATUS_TUNE_FAILED 0
@@ -216,4 +225,49 @@ struct dvb_frontend_parametersContext {
216 225
217#define ABS(x) ((x < 0) ? (-x) : (x)) 226#define ABS(x) ((x < 0) ? (-x) : (x))
218 227
228#define DATA_BUS_ACCESS_MODE_8BIT 0x01
229#define DATA_BUS_ACCESS_MODE_16BIT 0x02
230#define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10
231
232struct dibGPIOFunction {
233#define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
234#define BOARD_GPIO_COMPONENT_DEMOD 2
235 u8 component;
236
237#define BOARD_GPIO_FUNCTION_BOARD_ON 1
238#define BOARD_GPIO_FUNCTION_BOARD_OFF 2
239#define BOARD_GPIO_FUNCTION_COMPONENT_ON 3
240#define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
241#define BOARD_GPIO_FUNCTION_SUBBAND_PWM 5
242#define BOARD_GPIO_FUNCTION_SUBBAND_GPIO 6
243 u8 function;
244
245/* mask, direction and value are used specify which GPIO to change GPIO0
246 * is LSB and possible GPIO31 is MSB. The same bit-position as in the
247 * mask is used for the direction and the value. Direction == 1 is OUT,
248 * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
249 * value has no meaning.
250 *
251 * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
252 * used to do the PWM. Direction gives the PWModulator to be used.
253 * Value gives the PWM value in device-dependent scale.
254 */
255 u32 mask;
256 u32 direction;
257 u32 value;
258};
259
260#define MAX_NB_SUBBANDS 8
261struct dibSubbandSelection {
262 u8 size; /* Actual number of subbands. */
263 struct {
264 u16 f_mhz;
265 struct dibGPIOFunction gpio;
266 } subband[MAX_NB_SUBBANDS];
267};
268
269#define DEMOD_TIMF_SET 0x00
270#define DEMOD_TIMF_GET 0x01
271#define DEMOD_TIMF_UPDATE 0x02
272
219#endif 273#endif
diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c
index fc61d9230db8..90bf573308b0 100644
--- a/drivers/media/dvb/frontends/ds3000.c
+++ b/drivers/media/dvb/frontends/ds3000.c
@@ -229,31 +229,11 @@ static u8 ds3000_dvbs2_init_tab[] = {
229 0xb8, 0x00, 229 0xb8, 0x00,
230}; 230};
231 231
232/* DS3000 doesn't need some parameters as input and auto-detects them */
233/* save input from the application of those parameters */
234struct ds3000_tuning {
235 u32 frequency;
236 u32 symbol_rate;
237 fe_spectral_inversion_t inversion;
238 enum fe_code_rate fec;
239
240 /* input values */
241 u8 inversion_val;
242 fe_modulation_t delivery;
243 u8 rolloff;
244};
245
246struct ds3000_state { 232struct ds3000_state {
247 struct i2c_adapter *i2c; 233 struct i2c_adapter *i2c;
248 const struct ds3000_config *config; 234 const struct ds3000_config *config;
249
250 struct dvb_frontend frontend; 235 struct dvb_frontend frontend;
251
252 struct ds3000_tuning dcur;
253 struct ds3000_tuning dnxt;
254
255 u8 skip_fw_load; 236 u8 skip_fw_load;
256
257 /* previous uncorrected block counter for DVB-S2 */ 237 /* previous uncorrected block counter for DVB-S2 */
258 u16 prevUCBS2; 238 u16 prevUCBS2;
259}; 239};
@@ -305,7 +285,7 @@ static int ds3000_writeFW(struct ds3000_state *state, int reg,
305 struct i2c_msg msg; 285 struct i2c_msg msg;
306 u8 *buf; 286 u8 *buf;
307 287
308 buf = kmalloc(3, GFP_KERNEL); 288 buf = kmalloc(33, GFP_KERNEL);
309 if (buf == NULL) { 289 if (buf == NULL) {
310 printk(KERN_ERR "Unable to kmalloc\n"); 290 printk(KERN_ERR "Unable to kmalloc\n");
311 ret = -ENOMEM; 291 ret = -ENOMEM;
@@ -317,10 +297,10 @@ static int ds3000_writeFW(struct ds3000_state *state, int reg,
317 msg.addr = state->config->demod_address; 297 msg.addr = state->config->demod_address;
318 msg.flags = 0; 298 msg.flags = 0;
319 msg.buf = buf; 299 msg.buf = buf;
320 msg.len = 3; 300 msg.len = 33;
321 301
322 for (i = 0; i < len; i += 2) { 302 for (i = 0; i < len; i += 32) {
323 memcpy(buf + 1, data + i, 2); 303 memcpy(buf + 1, data + i, 32);
324 304
325 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len); 305 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
326 306
@@ -401,45 +381,6 @@ static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
401 return b1[0]; 381 return b1[0];
402} 382}
403 383
404static int ds3000_set_inversion(struct ds3000_state *state,
405 fe_spectral_inversion_t inversion)
406{
407 dprintk("%s(%d)\n", __func__, inversion);
408
409 switch (inversion) {
410 case INVERSION_OFF:
411 case INVERSION_ON:
412 case INVERSION_AUTO:
413 break;
414 default:
415 return -EINVAL;
416 }
417
418 state->dnxt.inversion = inversion;
419
420 return 0;
421}
422
423static int ds3000_set_symbolrate(struct ds3000_state *state, u32 rate)
424{
425 int ret = 0;
426
427 dprintk("%s()\n", __func__);
428
429 dprintk("%s() symbol_rate = %d\n", __func__, state->dnxt.symbol_rate);
430
431 /* check if symbol rate is within limits */
432 if ((state->dnxt.symbol_rate >
433 state->frontend.ops.info.symbol_rate_max) ||
434 (state->dnxt.symbol_rate <
435 state->frontend.ops.info.symbol_rate_min))
436 ret = -EOPNOTSUPP;
437
438 state->dnxt.symbol_rate = rate;
439
440 return ret;
441}
442
443static int ds3000_load_firmware(struct dvb_frontend *fe, 384static int ds3000_load_firmware(struct dvb_frontend *fe,
444 const struct firmware *fw); 385 const struct firmware *fw);
445 386
@@ -509,23 +450,31 @@ static int ds3000_load_firmware(struct dvb_frontend *fe,
509 return 0; 450 return 0;
510} 451}
511 452
512static void ds3000_dump_registers(struct dvb_frontend *fe) 453static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
513{ 454{
514 struct ds3000_state *state = fe->demodulator_priv; 455 struct ds3000_state *state = fe->demodulator_priv;
515 int x, y, reg = 0, val; 456 u8 data;
516 457
517 for (y = 0; y < 16; y++) { 458 dprintk("%s(%d)\n", __func__, voltage);
518 dprintk("%s: %02x: ", __func__, y); 459
519 for (x = 0; x < 16; x++) { 460 data = ds3000_readreg(state, 0xa2);
520 reg = (y << 4) + x; 461 data |= 0x03; /* bit0 V/H, bit1 off/on */
521 val = ds3000_readreg(state, reg); 462
522 if (x != 15) 463 switch (voltage) {
523 dprintk("%02x ", val); 464 case SEC_VOLTAGE_18:
524 else 465 data &= ~0x03;
525 dprintk("%02x\n", val); 466 break;
526 } 467 case SEC_VOLTAGE_13:
468 data &= ~0x03;
469 data |= 0x01;
470 break;
471 case SEC_VOLTAGE_OFF:
472 break;
527 } 473 }
528 dprintk("%s: -- DS3000 DUMP DONE --\n", __func__); 474
475 ds3000_writereg(state, 0xa2, data);
476
477 return 0;
529} 478}
530 479
531static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status) 480static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
@@ -562,16 +511,6 @@ static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
562 return 0; 511 return 0;
563} 512}
564 513
565#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
566static int ds3000_is_tuned(struct dvb_frontend *fe)
567{
568 fe_status_t tunerstat;
569
570 ds3000_read_status(fe, &tunerstat);
571
572 return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
573}
574
575/* read DS3000 BER value */ 514/* read DS3000 BER value */
576static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber) 515static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
577{ 516{
@@ -792,13 +731,6 @@ static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
792 return 0; 731 return 0;
793} 732}
794 733
795/* Overwrite the current tuning params, we are about to tune */
796static void ds3000_clone_params(struct dvb_frontend *fe)
797{
798 struct ds3000_state *state = fe->demodulator_priv;
799 memcpy(&state->dcur, &state->dnxt, sizeof(state->dcur));
800}
801
802static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 734static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
803{ 735{
804 struct ds3000_state *state = fe->demodulator_priv; 736 struct ds3000_state *state = fe->demodulator_priv;
@@ -1016,287 +948,298 @@ static int ds3000_get_property(struct dvb_frontend *fe,
1016 return 0; 948 return 0;
1017} 949}
1018 950
1019static int ds3000_tune(struct dvb_frontend *fe, 951static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
952 s32 carrier_offset_khz)
953{
954 struct ds3000_state *state = fe->demodulator_priv;
955 s32 tmp;
956
957 tmp = carrier_offset_khz;
958 tmp *= 65536;
959 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
960
961 if (tmp < 0)
962 tmp += 65536;
963
964 ds3000_writereg(state, 0x5f, tmp >> 8);
965 ds3000_writereg(state, 0x5e, tmp & 0xff);
966
967 return 0;
968}
969
970static int ds3000_set_frontend(struct dvb_frontend *fe,
1020 struct dvb_frontend_parameters *p) 971 struct dvb_frontend_parameters *p)
1021{ 972{
1022 struct ds3000_state *state = fe->demodulator_priv; 973 struct ds3000_state *state = fe->demodulator_priv;
1023 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 974 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1024 975
1025 int ret = 0, retune, i; 976 int i;
1026 u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf; 977 fe_status_t status;
978 u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4;
979 s32 offset_khz;
1027 u16 value, ndiv; 980 u16 value, ndiv;
1028 u32 f3db; 981 u32 f3db;
1029 982
1030 dprintk("%s() ", __func__); 983 dprintk("%s() ", __func__);
1031 984
1032 /* Load the firmware if required */ 985 if (state->config->set_ts_params)
1033 ret = ds3000_firmware_ondemand(fe); 986 state->config->set_ts_params(fe, 0);
1034 if (ret != 0) { 987 /* Tune */
1035 printk(KERN_ERR "%s: Unable initialise the firmware\n", 988 /* unknown */
1036 __func__); 989 ds3000_tuner_writereg(state, 0x07, 0x02);
1037 return ret; 990 ds3000_tuner_writereg(state, 0x10, 0x00);
991 ds3000_tuner_writereg(state, 0x60, 0x79);
992 ds3000_tuner_writereg(state, 0x08, 0x01);
993 ds3000_tuner_writereg(state, 0x00, 0x01);
994 div4 = 0;
995
996 /* calculate and set freq divider */
997 if (p->frequency < 1146000) {
998 ds3000_tuner_writereg(state, 0x10, 0x11);
999 div4 = 1;
1000 ndiv = ((p->frequency * (6 + 8) * 4) +
1001 (DS3000_XTAL_FREQ / 2)) /
1002 DS3000_XTAL_FREQ - 1024;
1003 } else {
1004 ds3000_tuner_writereg(state, 0x10, 0x01);
1005 ndiv = ((p->frequency * (6 + 8) * 2) +
1006 (DS3000_XTAL_FREQ / 2)) /
1007 DS3000_XTAL_FREQ - 1024;
1038 } 1008 }
1039 1009
1040 state->dnxt.delivery = c->modulation; 1010 ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
1041 state->dnxt.frequency = c->frequency; 1011 ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
1042 state->dnxt.rolloff = 2; /* fixme */ 1012
1043 state->dnxt.fec = c->fec_inner; 1013 /* set pll */
1014 ds3000_tuner_writereg(state, 0x03, 0x06);
1015 ds3000_tuner_writereg(state, 0x51, 0x0f);
1016 ds3000_tuner_writereg(state, 0x51, 0x1f);
1017 ds3000_tuner_writereg(state, 0x50, 0x10);
1018 ds3000_tuner_writereg(state, 0x50, 0x00);
1019 msleep(5);
1020
1021 /* unknown */
1022 ds3000_tuner_writereg(state, 0x51, 0x17);
1023 ds3000_tuner_writereg(state, 0x51, 0x1f);
1024 ds3000_tuner_writereg(state, 0x50, 0x08);
1025 ds3000_tuner_writereg(state, 0x50, 0x00);
1026 msleep(5);
1027
1028 value = ds3000_tuner_readreg(state, 0x3d);
1029 value &= 0x0f;
1030 if ((value > 4) && (value < 15)) {
1031 value -= 3;
1032 if (value < 4)
1033 value = 4;
1034 value = ((value << 3) | 0x01) & 0x79;
1035 }
1044 1036
1045 ret = ds3000_set_inversion(state, p->inversion); 1037 ds3000_tuner_writereg(state, 0x60, value);
1046 if (ret != 0) 1038 ds3000_tuner_writereg(state, 0x51, 0x17);
1047 return ret; 1039 ds3000_tuner_writereg(state, 0x51, 0x1f);
1040 ds3000_tuner_writereg(state, 0x50, 0x08);
1041 ds3000_tuner_writereg(state, 0x50, 0x00);
1042
1043 /* set low-pass filter period */
1044 ds3000_tuner_writereg(state, 0x04, 0x2e);
1045 ds3000_tuner_writereg(state, 0x51, 0x1b);
1046 ds3000_tuner_writereg(state, 0x51, 0x1f);
1047 ds3000_tuner_writereg(state, 0x50, 0x04);
1048 ds3000_tuner_writereg(state, 0x50, 0x00);
1049 msleep(5);
1050
1051 f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000;
1052 if ((c->symbol_rate / 1000) < 5000)
1053 f3db += 3000;
1054 if (f3db < 7000)
1055 f3db = 7000;
1056 if (f3db > 40000)
1057 f3db = 40000;
1058
1059 /* set low-pass filter baseband */
1060 value = ds3000_tuner_readreg(state, 0x26);
1061 mlpf = 0x2e * 207 / ((value << 1) + 151);
1062 mlpf_max = mlpf * 135 / 100;
1063 mlpf_min = mlpf * 78 / 100;
1064 if (mlpf_max > 63)
1065 mlpf_max = 63;
1066
1067 /* rounded to the closest integer */
1068 nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
1069 / (2766 * DS3000_XTAL_FREQ);
1070 if (nlpf > 23)
1071 nlpf = 23;
1072 if (nlpf < 1)
1073 nlpf = 1;
1074
1075 /* rounded to the closest integer */
1076 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1077 (1000 * f3db / 2)) / (1000 * f3db);
1078
1079 if (mlpf_new < mlpf_min) {
1080 nlpf++;
1081 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1082 (1000 * f3db / 2)) / (1000 * f3db);
1083 }
1048 1084
1049 ret = ds3000_set_symbolrate(state, c->symbol_rate); 1085 if (mlpf_new > mlpf_max)
1050 if (ret != 0) 1086 mlpf_new = mlpf_max;
1051 return ret; 1087
1088 ds3000_tuner_writereg(state, 0x04, mlpf_new);
1089 ds3000_tuner_writereg(state, 0x06, nlpf);
1090 ds3000_tuner_writereg(state, 0x51, 0x1b);
1091 ds3000_tuner_writereg(state, 0x51, 0x1f);
1092 ds3000_tuner_writereg(state, 0x50, 0x04);
1093 ds3000_tuner_writereg(state, 0x50, 0x00);
1094 msleep(5);
1095
1096 /* unknown */
1097 ds3000_tuner_writereg(state, 0x51, 0x1e);
1098 ds3000_tuner_writereg(state, 0x51, 0x1f);
1099 ds3000_tuner_writereg(state, 0x50, 0x01);
1100 ds3000_tuner_writereg(state, 0x50, 0x00);
1101 msleep(60);
1102
1103 offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
1104 / (6 + 8) / (div4 + 1) / 2 - p->frequency;
1105
1106 /* ds3000 global reset */
1107 ds3000_writereg(state, 0x07, 0x80);
1108 ds3000_writereg(state, 0x07, 0x00);
1109 /* ds3000 build-in uC reset */
1110 ds3000_writereg(state, 0xb2, 0x01);
1111 /* ds3000 software reset */
1112 ds3000_writereg(state, 0x00, 0x01);
1052 1113
1053 /* discard the 'current' tuning parameters and prepare to tune */ 1114 switch (c->delivery_system) {
1054 ds3000_clone_params(fe); 1115 case SYS_DVBS:
1055 1116 /* initialise the demod in DVB-S mode */
1056 retune = 1; /* try 1 times */ 1117 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
1057 dprintk("%s: retune = %d\n", __func__, retune); 1118 ds3000_writereg(state,
1058 dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency); 1119 ds3000_dvbs_init_tab[i],
1059 dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate); 1120 ds3000_dvbs_init_tab[i + 1]);
1060 dprintk("%s: FEC = %d \n", __func__, 1121 value = ds3000_readreg(state, 0xfe);
1061 state->dcur.fec); 1122 value &= 0xc0;
1062 dprintk("%s: Inversion = %d\n", __func__, state->dcur.inversion); 1123 value |= 0x1b;
1063 1124 ds3000_writereg(state, 0xfe, value);
1064 do { 1125 break;
1065 /* Reset status register */ 1126 case SYS_DVBS2:
1066 status = 0; 1127 /* initialise the demod in DVB-S2 mode */
1067 /* Tune */ 1128 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1068 /* TS2020 init */ 1129 ds3000_writereg(state,
1069 ds3000_tuner_writereg(state, 0x42, 0x73); 1130 ds3000_dvbs2_init_tab[i],
1070 ds3000_tuner_writereg(state, 0x05, 0x01); 1131 ds3000_dvbs2_init_tab[i + 1]);
1071 ds3000_tuner_writereg(state, 0x62, 0xf5); 1132 ds3000_writereg(state, 0xfe, 0x98);
1072 /* unknown */ 1133 break;
1073 ds3000_tuner_writereg(state, 0x07, 0x02); 1134 default:
1074 ds3000_tuner_writereg(state, 0x10, 0x00); 1135 return 1;
1075 ds3000_tuner_writereg(state, 0x60, 0x79); 1136 }
1076 ds3000_tuner_writereg(state, 0x08, 0x01);
1077 ds3000_tuner_writereg(state, 0x00, 0x01);
1078 /* calculate and set freq divider */
1079 if (state->dcur.frequency < 1146000) {
1080 ds3000_tuner_writereg(state, 0x10, 0x11);
1081 ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
1082 (DS3000_XTAL_FREQ / 2)) /
1083 DS3000_XTAL_FREQ - 1024;
1084 } else {
1085 ds3000_tuner_writereg(state, 0x10, 0x01);
1086 ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
1087 (DS3000_XTAL_FREQ / 2)) /
1088 DS3000_XTAL_FREQ - 1024;
1089 }
1090 1137
1091 ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8); 1138 /* enable 27MHz clock output */
1092 ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff); 1139 ds3000_writereg(state, 0x29, 0x80);
1093 1140 /* enable ac coupling */
1094 /* set pll */ 1141 ds3000_writereg(state, 0x25, 0x8a);
1095 ds3000_tuner_writereg(state, 0x03, 0x06); 1142
1096 ds3000_tuner_writereg(state, 0x51, 0x0f); 1143 /* enhance symbol rate performance */
1097 ds3000_tuner_writereg(state, 0x51, 0x1f); 1144 if ((c->symbol_rate / 1000) <= 5000) {
1098 ds3000_tuner_writereg(state, 0x50, 0x10); 1145 value = 29777 / (c->symbol_rate / 1000) + 1;
1099 ds3000_tuner_writereg(state, 0x50, 0x00); 1146 if (value % 2 != 0)
1100 msleep(5); 1147 value++;
1101 1148 ds3000_writereg(state, 0xc3, 0x0d);
1102 /* unknown */ 1149 ds3000_writereg(state, 0xc8, value);
1103 ds3000_tuner_writereg(state, 0x51, 0x17); 1150 ds3000_writereg(state, 0xc4, 0x10);
1104 ds3000_tuner_writereg(state, 0x51, 0x1f); 1151 ds3000_writereg(state, 0xc7, 0x0e);
1105 ds3000_tuner_writereg(state, 0x50, 0x08); 1152 } else if ((c->symbol_rate / 1000) <= 10000) {
1106 ds3000_tuner_writereg(state, 0x50, 0x00); 1153 value = 92166 / (c->symbol_rate / 1000) + 1;
1107 msleep(5); 1154 if (value % 2 != 0)
1108 1155 value++;
1109 value = ds3000_tuner_readreg(state, 0x3d); 1156 ds3000_writereg(state, 0xc3, 0x07);
1110 value &= 0x0f; 1157 ds3000_writereg(state, 0xc8, value);
1111 if ((value > 4) && (value < 15)) { 1158 ds3000_writereg(state, 0xc4, 0x09);
1112 value -= 3; 1159 ds3000_writereg(state, 0xc7, 0x12);
1113 if (value < 4) 1160 } else if ((c->symbol_rate / 1000) <= 20000) {
1114 value = 4; 1161 value = 64516 / (c->symbol_rate / 1000) + 1;
1115 value = ((value << 3) | 0x01) & 0x79; 1162 ds3000_writereg(state, 0xc3, value);
1116 } 1163 ds3000_writereg(state, 0xc8, 0x0e);
1164 ds3000_writereg(state, 0xc4, 0x07);
1165 ds3000_writereg(state, 0xc7, 0x18);
1166 } else {
1167 value = 129032 / (c->symbol_rate / 1000) + 1;
1168 ds3000_writereg(state, 0xc3, value);
1169 ds3000_writereg(state, 0xc8, 0x0a);
1170 ds3000_writereg(state, 0xc4, 0x05);
1171 ds3000_writereg(state, 0xc7, 0x24);
1172 }
1117 1173
1118 ds3000_tuner_writereg(state, 0x60, value); 1174 /* normalized symbol rate rounded to the closest integer */
1119 ds3000_tuner_writereg(state, 0x51, 0x17); 1175 value = (((c->symbol_rate / 1000) << 16) +
1120 ds3000_tuner_writereg(state, 0x51, 0x1f); 1176 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
1121 ds3000_tuner_writereg(state, 0x50, 0x08); 1177 ds3000_writereg(state, 0x61, value & 0x00ff);
1122 ds3000_tuner_writereg(state, 0x50, 0x00); 1178 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1123
1124 /* set low-pass filter period */
1125 ds3000_tuner_writereg(state, 0x04, 0x2e);
1126 ds3000_tuner_writereg(state, 0x51, 0x1b);
1127 ds3000_tuner_writereg(state, 0x51, 0x1f);
1128 ds3000_tuner_writereg(state, 0x50, 0x04);
1129 ds3000_tuner_writereg(state, 0x50, 0x00);
1130 msleep(5);
1131
1132 f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
1133 if ((state->dcur.symbol_rate / 1000) < 5000)
1134 f3db += 3000;
1135 if (f3db < 7000)
1136 f3db = 7000;
1137 if (f3db > 40000)
1138 f3db = 40000;
1139
1140 /* set low-pass filter baseband */
1141 value = ds3000_tuner_readreg(state, 0x26);
1142 mlpf = 0x2e * 207 / ((value << 1) + 151);
1143 mlpf_max = mlpf * 135 / 100;
1144 mlpf_min = mlpf * 78 / 100;
1145 if (mlpf_max > 63)
1146 mlpf_max = 63;
1147
1148 /* rounded to the closest integer */
1149 nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
1150 / (2766 * DS3000_XTAL_FREQ);
1151 if (nlpf > 23)
1152 nlpf = 23;
1153 if (nlpf < 1)
1154 nlpf = 1;
1155
1156 /* rounded to the closest integer */
1157 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1158 (1000 * f3db / 2)) / (1000 * f3db);
1159 1179
1160 if (mlpf_new < mlpf_min) { 1180 /* co-channel interference cancellation disabled */
1161 nlpf++; 1181 ds3000_writereg(state, 0x56, 0x00);
1162 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) + 1182
1163 (1000 * f3db / 2)) / (1000 * f3db); 1183 /* equalizer disabled */
1164 } 1184 ds3000_writereg(state, 0x76, 0x00);
1165 1185
1166 if (mlpf_new > mlpf_max) 1186 /*ds3000_writereg(state, 0x08, 0x03);
1167 mlpf_new = mlpf_max; 1187 ds3000_writereg(state, 0xfd, 0x22);
1168 1188 ds3000_writereg(state, 0x08, 0x07);
1169 ds3000_tuner_writereg(state, 0x04, mlpf_new); 1189 ds3000_writereg(state, 0xfd, 0x42);
1170 ds3000_tuner_writereg(state, 0x06, nlpf); 1190 ds3000_writereg(state, 0x08, 0x07);*/
1171 ds3000_tuner_writereg(state, 0x51, 0x1b);
1172 ds3000_tuner_writereg(state, 0x51, 0x1f);
1173 ds3000_tuner_writereg(state, 0x50, 0x04);
1174 ds3000_tuner_writereg(state, 0x50, 0x00);
1175 msleep(5);
1176
1177 /* unknown */
1178 ds3000_tuner_writereg(state, 0x51, 0x1e);
1179 ds3000_tuner_writereg(state, 0x51, 0x1f);
1180 ds3000_tuner_writereg(state, 0x50, 0x01);
1181 ds3000_tuner_writereg(state, 0x50, 0x00);
1182 msleep(60);
1183
1184 /* ds3000 global reset */
1185 ds3000_writereg(state, 0x07, 0x80);
1186 ds3000_writereg(state, 0x07, 0x00);
1187 /* ds3000 build-in uC reset */
1188 ds3000_writereg(state, 0xb2, 0x01);
1189 /* ds3000 software reset */
1190 ds3000_writereg(state, 0x00, 0x01);
1191 1191
1192 if (state->config->ci_mode) {
1192 switch (c->delivery_system) { 1193 switch (c->delivery_system) {
1193 case SYS_DVBS: 1194 case SYS_DVBS:
1194 /* initialise the demod in DVB-S mode */ 1195 default:
1195 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2) 1196 ds3000_writereg(state, 0xfd, 0x80);
1196 ds3000_writereg(state, 1197 break;
1197 ds3000_dvbs_init_tab[i],
1198 ds3000_dvbs_init_tab[i + 1]);
1199 value = ds3000_readreg(state, 0xfe);
1200 value &= 0xc0;
1201 value |= 0x1b;
1202 ds3000_writereg(state, 0xfe, value);
1203 break;
1204 case SYS_DVBS2: 1198 case SYS_DVBS2:
1205 /* initialise the demod in DVB-S2 mode */ 1199 ds3000_writereg(state, 0xfd, 0x01);
1206 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1207 ds3000_writereg(state,
1208 ds3000_dvbs2_init_tab[i],
1209 ds3000_dvbs2_init_tab[i + 1]);
1210 ds3000_writereg(state, 0xfe, 0x54);
1211 break; 1200 break;
1212 default:
1213 return 1;
1214 } 1201 }
1202 }
1215 1203
1216 /* enable 27MHz clock output */ 1204 /* ds3000 out of software reset */
1217 ds3000_writereg(state, 0x29, 0x80); 1205 ds3000_writereg(state, 0x00, 0x00);
1218 /* enable ac coupling */ 1206 /* start ds3000 build-in uC */
1219 ds3000_writereg(state, 0x25, 0x8a); 1207 ds3000_writereg(state, 0xb2, 0x00);
1220
1221 /* enhance symbol rate performance */
1222 if ((state->dcur.symbol_rate / 1000) <= 5000) {
1223 value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
1224 if (value % 2 != 0)
1225 value++;
1226 ds3000_writereg(state, 0xc3, 0x0d);
1227 ds3000_writereg(state, 0xc8, value);
1228 ds3000_writereg(state, 0xc4, 0x10);
1229 ds3000_writereg(state, 0xc7, 0x0e);
1230 } else if ((state->dcur.symbol_rate / 1000) <= 10000) {
1231 value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
1232 if (value % 2 != 0)
1233 value++;
1234 ds3000_writereg(state, 0xc3, 0x07);
1235 ds3000_writereg(state, 0xc8, value);
1236 ds3000_writereg(state, 0xc4, 0x09);
1237 ds3000_writereg(state, 0xc7, 0x12);
1238 } else if ((state->dcur.symbol_rate / 1000) <= 20000) {
1239 value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
1240 ds3000_writereg(state, 0xc3, value);
1241 ds3000_writereg(state, 0xc8, 0x0e);
1242 ds3000_writereg(state, 0xc4, 0x07);
1243 ds3000_writereg(state, 0xc7, 0x18);
1244 } else {
1245 value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
1246 ds3000_writereg(state, 0xc3, value);
1247 ds3000_writereg(state, 0xc8, 0x0a);
1248 ds3000_writereg(state, 0xc4, 0x05);
1249 ds3000_writereg(state, 0xc7, 0x24);
1250 }
1251 1208
1252 /* normalized symbol rate rounded to the closest integer */ 1209 ds3000_set_carrier_offset(fe, offset_khz);
1253 value = (((state->dcur.symbol_rate / 1000) << 16) +
1254 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
1255 ds3000_writereg(state, 0x61, value & 0x00ff);
1256 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1257
1258 /* co-channel interference cancellation disabled */
1259 ds3000_writereg(state, 0x56, 0x00);
1260
1261 /* equalizer disabled */
1262 ds3000_writereg(state, 0x76, 0x00);
1263
1264 /*ds3000_writereg(state, 0x08, 0x03);
1265 ds3000_writereg(state, 0xfd, 0x22);
1266 ds3000_writereg(state, 0x08, 0x07);
1267 ds3000_writereg(state, 0xfd, 0x42);
1268 ds3000_writereg(state, 0x08, 0x07);*/
1269
1270 /* ds3000 out of software reset */
1271 ds3000_writereg(state, 0x00, 0x00);
1272 /* start ds3000 build-in uC */
1273 ds3000_writereg(state, 0xb2, 0x00);
1274
1275 /* TODO: calculate and set carrier offset */
1276
1277 /* wait before retrying */
1278 for (i = 0; i < 30 ; i++) {
1279 if (ds3000_is_tuned(fe)) {
1280 dprintk("%s: Tuned\n", __func__);
1281 ds3000_dump_registers(fe);
1282 goto tuned;
1283 }
1284 msleep(1);
1285 }
1286 1210
1287 dprintk("%s: Not tuned\n", __func__); 1211 for (i = 0; i < 30 ; i++) {
1288 ds3000_dump_registers(fe); 1212 ds3000_read_status(fe, &status);
1213 if (status && FE_HAS_LOCK)
1214 break;
1289 1215
1290 } while (--retune); 1216 msleep(10);
1217 }
1291 1218
1292tuned: 1219 return 0;
1293 return ret; 1220}
1221
1222static int ds3000_tune(struct dvb_frontend *fe,
1223 struct dvb_frontend_parameters *p,
1224 unsigned int mode_flags,
1225 unsigned int *delay,
1226 fe_status_t *status)
1227{
1228 if (p) {
1229 int ret = ds3000_set_frontend(fe, p);
1230 if (ret)
1231 return ret;
1232 }
1233
1234 *delay = HZ / 5;
1235
1236 return ds3000_read_status(fe, status);
1294} 1237}
1295 1238
1296static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe) 1239static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1297{ 1240{
1298 dprintk("%s()\n", __func__); 1241 dprintk("%s()\n", __func__);
1299 return DVBFE_ALGO_SW; 1242 return DVBFE_ALGO_HW;
1300} 1243}
1301 1244
1302/* 1245/*
@@ -1306,7 +1249,25 @@ static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1306 */ 1249 */
1307static int ds3000_initfe(struct dvb_frontend *fe) 1250static int ds3000_initfe(struct dvb_frontend *fe)
1308{ 1251{
1252 struct ds3000_state *state = fe->demodulator_priv;
1253 int ret;
1254
1309 dprintk("%s()\n", __func__); 1255 dprintk("%s()\n", __func__);
1256 /* hard reset */
1257 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1258 msleep(1);
1259
1260 /* TS2020 init */
1261 ds3000_tuner_writereg(state, 0x42, 0x73);
1262 ds3000_tuner_writereg(state, 0x05, 0x01);
1263 ds3000_tuner_writereg(state, 0x62, 0xf5);
1264 /* Load the firmware if required */
1265 ret = ds3000_firmware_ondemand(fe);
1266 if (ret != 0) {
1267 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1268 return ret;
1269 }
1270
1310 return 0; 1271 return 0;
1311} 1272}
1312 1273
@@ -1345,6 +1306,7 @@ static struct dvb_frontend_ops ds3000_ops = {
1345 .read_signal_strength = ds3000_read_signal_strength, 1306 .read_signal_strength = ds3000_read_signal_strength,
1346 .read_snr = ds3000_read_snr, 1307 .read_snr = ds3000_read_snr,
1347 .read_ucblocks = ds3000_read_ucblocks, 1308 .read_ucblocks = ds3000_read_ucblocks,
1309 .set_voltage = ds3000_set_voltage,
1348 .set_tone = ds3000_set_tone, 1310 .set_tone = ds3000_set_tone,
1349 .diseqc_send_master_cmd = ds3000_send_diseqc_msg, 1311 .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1350 .diseqc_send_burst = ds3000_diseqc_send_burst, 1312 .diseqc_send_burst = ds3000_diseqc_send_burst,
@@ -1352,7 +1314,8 @@ static struct dvb_frontend_ops ds3000_ops = {
1352 1314
1353 .set_property = ds3000_set_property, 1315 .set_property = ds3000_set_property,
1354 .get_property = ds3000_get_property, 1316 .get_property = ds3000_get_property,
1355 .set_frontend = ds3000_tune, 1317 .set_frontend = ds3000_set_frontend,
1318 .tune = ds3000_tune,
1356}; 1319};
1357 1320
1358module_param(debug, int, 0644); 1321module_param(debug, int, 0644);
diff --git a/drivers/media/dvb/frontends/ds3000.h b/drivers/media/dvb/frontends/ds3000.h
index 67f67038740a..1b736888ea37 100644
--- a/drivers/media/dvb/frontends/ds3000.h
+++ b/drivers/media/dvb/frontends/ds3000.h
@@ -27,6 +27,9 @@
27struct ds3000_config { 27struct ds3000_config {
28 /* the demodulator's i2c address */ 28 /* the demodulator's i2c address */
29 u8 demod_address; 29 u8 demod_address;
30 u8 ci_mode;
31 /* Set device param to start dma */
32 int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
30}; 33};
31 34
32#if defined(CONFIG_DVB_DS3000) || \ 35#if defined(CONFIG_DVB_DS3000) || \
diff --git a/drivers/media/dvb/frontends/dvb-pll.c b/drivers/media/dvb/frontends/dvb-pll.c
index 4d4d0bb5920a..62a65efdf8d6 100644
--- a/drivers/media/dvb/frontends/dvb-pll.c
+++ b/drivers/media/dvb/frontends/dvb-pll.c
@@ -64,6 +64,7 @@ struct dvb_pll_desc {
64 void (*set)(struct dvb_frontend *fe, u8 *buf, 64 void (*set)(struct dvb_frontend *fe, u8 *buf,
65 const struct dvb_frontend_parameters *params); 65 const struct dvb_frontend_parameters *params);
66 u8 *initdata; 66 u8 *initdata;
67 u8 *initdata2;
67 u8 *sleepdata; 68 u8 *sleepdata;
68 int count; 69 int count;
69 struct { 70 struct {
@@ -321,26 +322,73 @@ static struct dvb_pll_desc dvb_pll_philips_sd1878_tda8261 = {
321static void opera1_bw(struct dvb_frontend *fe, u8 *buf, 322static void opera1_bw(struct dvb_frontend *fe, u8 *buf,
322 const struct dvb_frontend_parameters *params) 323 const struct dvb_frontend_parameters *params)
323{ 324{
324 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) 325 struct dvb_pll_priv *priv = fe->tuner_priv;
325 buf[2] |= 0x08; 326 u32 b_w = (params->u.qpsk.symbol_rate * 27) / 32000;
327 struct i2c_msg msg = {
328 .addr = priv->pll_i2c_address,
329 .flags = 0,
330 .buf = buf,
331 .len = 4
332 };
333 int result;
334 u8 lpf;
335
336 if (fe->ops.i2c_gate_ctrl)
337 fe->ops.i2c_gate_ctrl(fe, 1);
338
339 result = i2c_transfer(priv->i2c, &msg, 1);
340 if (result != 1)
341 printk(KERN_ERR "%s: i2c_transfer failed:%d",
342 __func__, result);
343
344 if (b_w <= 10000)
345 lpf = 0xc;
346 else if (b_w <= 12000)
347 lpf = 0x2;
348 else if (b_w <= 14000)
349 lpf = 0xa;
350 else if (b_w <= 16000)
351 lpf = 0x6;
352 else if (b_w <= 18000)
353 lpf = 0xe;
354 else if (b_w <= 20000)
355 lpf = 0x1;
356 else if (b_w <= 22000)
357 lpf = 0x9;
358 else if (b_w <= 24000)
359 lpf = 0x5;
360 else if (b_w <= 26000)
361 lpf = 0xd;
362 else if (b_w <= 28000)
363 lpf = 0x3;
364 else
365 lpf = 0xb;
366 buf[2] ^= 0x1c; /* Flip bits 3-5 */
367 /* Set lpf */
368 buf[2] |= ((lpf >> 2) & 0x3) << 3;
369 buf[3] |= (lpf & 0x3) << 2;
370
371 return;
326} 372}
327 373
328static struct dvb_pll_desc dvb_pll_opera1 = { 374static struct dvb_pll_desc dvb_pll_opera1 = {
329 .name = "Opera Tuner", 375 .name = "Opera Tuner",
330 .min = 900000, 376 .min = 900000,
331 .max = 2250000, 377 .max = 2250000,
378 .initdata = (u8[]){ 4, 0x08, 0xe5, 0xe1, 0x00 },
379 .initdata2 = (u8[]){ 4, 0x08, 0xe5, 0xe5, 0x00 },
332 .iffreq= 0, 380 .iffreq= 0,
333 .set = opera1_bw, 381 .set = opera1_bw,
334 .count = 8, 382 .count = 8,
335 .entries = { 383 .entries = {
336 { 1064000, 500, 0xe5, 0xc6 }, 384 { 1064000, 500, 0xf9, 0xc2 },
337 { 1169000, 500, 0xe5, 0xe6 }, 385 { 1169000, 500, 0xf9, 0xe2 },
338 { 1299000, 500, 0xe5, 0x24 }, 386 { 1299000, 500, 0xf9, 0x20 },
339 { 1444000, 500, 0xe5, 0x44 }, 387 { 1444000, 500, 0xf9, 0x40 },
340 { 1606000, 500, 0xe5, 0x64 }, 388 { 1606000, 500, 0xf9, 0x60 },
341 { 1777000, 500, 0xe5, 0x84 }, 389 { 1777000, 500, 0xf9, 0x80 },
342 { 1941000, 500, 0xe5, 0xa4 }, 390 { 1941000, 500, 0xf9, 0xa0 },
343 { 2250000, 500, 0xe5, 0xc4 }, 391 { 2250000, 500, 0xf9, 0xc0 },
344 } 392 }
345}; 393};
346 394
@@ -648,8 +696,17 @@ static int dvb_pll_init(struct dvb_frontend *fe)
648 int result; 696 int result;
649 if (fe->ops.i2c_gate_ctrl) 697 if (fe->ops.i2c_gate_ctrl)
650 fe->ops.i2c_gate_ctrl(fe, 1); 698 fe->ops.i2c_gate_ctrl(fe, 1);
651 if ((result = i2c_transfer(priv->i2c, &msg, 1)) != 1) { 699 result = i2c_transfer(priv->i2c, &msg, 1);
700 if (result != 1)
652 return result; 701 return result;
702 if (priv->pll_desc->initdata2) {
703 msg.buf = priv->pll_desc->initdata2 + 1;
704 msg.len = priv->pll_desc->initdata2[0];
705 if (fe->ops.i2c_gate_ctrl)
706 fe->ops.i2c_gate_ctrl(fe, 1);
707 result = i2c_transfer(priv->i2c, &msg, 1);
708 if (result != 1)
709 return result;
653 } 710 }
654 return 0; 711 return 0;
655 } 712 }
diff --git a/drivers/media/dvb/frontends/stv0288.c b/drivers/media/dvb/frontends/stv0288.c
index 63db8fd2754c..e3fe17fd96fb 100644
--- a/drivers/media/dvb/frontends/stv0288.c
+++ b/drivers/media/dvb/frontends/stv0288.c
@@ -367,8 +367,11 @@ static int stv0288_read_status(struct dvb_frontend *fe, fe_status_t *status)
367 dprintk("%s : FE_READ_STATUS : VSTATUS: 0x%02x\n", __func__, sync); 367 dprintk("%s : FE_READ_STATUS : VSTATUS: 0x%02x\n", __func__, sync);
368 368
369 *status = 0; 369 *status = 0;
370 370 if (sync & 0x80)
371 if ((sync & 0x08) == 0x08) { 371 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
372 if (sync & 0x10)
373 *status |= FE_HAS_VITERBI;
374 if (sync & 0x08) {
372 *status |= FE_HAS_LOCK; 375 *status |= FE_HAS_LOCK;
373 dprintk("stv0288 has locked\n"); 376 dprintk("stv0288 has locked\n");
374 } 377 }
diff --git a/drivers/media/dvb/frontends/stv0367.c b/drivers/media/dvb/frontends/stv0367.c
new file mode 100644
index 000000000000..4e0e6a873b8c
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv0367.c
@@ -0,0 +1,3459 @@
1/*
2 * stv0367.c
3 *
4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/string.h>
29#include <linux/slab.h>
30#include <linux/i2c.h>
31
32#include "stv0367.h"
33#include "stv0367_regs.h"
34#include "stv0367_priv.h"
35
36static int stvdebug;
37module_param_named(debug, stvdebug, int, 0644);
38
39static int i2cdebug;
40module_param_named(i2c_debug, i2cdebug, int, 0644);
41
42#define dprintk(args...) \
43 do { \
44 if (stvdebug) \
45 printk(KERN_DEBUG args); \
46 } while (0)
47 /* DVB-C */
48
49struct stv0367cab_state {
50 enum stv0367_cab_signal_type state;
51 u32 mclk;
52 u32 adc_clk;
53 s32 search_range;
54 s32 derot_offset;
55 /* results */
56 int locked; /* channel found */
57 u32 freq_khz; /* found frequency (in kHz) */
58 u32 symbol_rate; /* found symbol rate (in Bds) */
59 enum stv0367cab_mod modulation; /* modulation */
60 fe_spectral_inversion_t spect_inv; /* Spectrum Inversion */
61};
62
63struct stv0367ter_state {
64 /* DVB-T */
65 enum stv0367_ter_signal_type state;
66 enum stv0367_ter_if_iq_mode if_iq_mode;
67 enum stv0367_ter_mode mode;/* mode 2K or 8K */
68 fe_guard_interval_t guard;
69 enum stv0367_ter_hierarchy hierarchy;
70 u32 frequency;
71 fe_spectral_inversion_t sense; /* current search spectrum */
72 u8 force; /* force mode/guard */
73 u8 bw; /* channel width 6, 7 or 8 in MHz */
74 u8 pBW; /* channel width used during previous lock */
75 u32 pBER;
76 u32 pPER;
77 u32 ucblocks;
78 s8 echo_pos; /* echo position */
79 u8 first_lock;
80 u8 unlock_counter;
81 u32 agc_val;
82};
83
84struct stv0367_state {
85 struct dvb_frontend fe;
86 struct i2c_adapter *i2c;
87 /* config settings */
88 const struct stv0367_config *config;
89 u8 chip_id;
90 /* DVB-C */
91 struct stv0367cab_state *cab_state;
92 /* DVB-T */
93 struct stv0367ter_state *ter_state;
94};
95
96struct st_register {
97 u16 addr;
98 u8 value;
99};
100
101/* values for STV4100 XTAL=30M int clk=53.125M*/
102static struct st_register def0367ter[STV0367TER_NBREGS] = {
103 {R367TER_ID, 0x60},
104 {R367TER_I2CRPT, 0xa0},
105 /* {R367TER_I2CRPT, 0x22},*/
106 {R367TER_TOPCTRL, 0x00},/* for xc5000; was 0x02 */
107 {R367TER_IOCFG0, 0x40},
108 {R367TER_DAC0R, 0x00},
109 {R367TER_IOCFG1, 0x00},
110 {R367TER_DAC1R, 0x00},
111 {R367TER_IOCFG2, 0x62},
112 {R367TER_SDFR, 0x00},
113 {R367TER_STATUS, 0xf8},
114 {R367TER_AUX_CLK, 0x0a},
115 {R367TER_FREESYS1, 0x00},
116 {R367TER_FREESYS2, 0x00},
117 {R367TER_FREESYS3, 0x00},
118 {R367TER_GPIO_CFG, 0x55},
119 {R367TER_GPIO_CMD, 0x00},
120 {R367TER_AGC2MAX, 0xff},
121 {R367TER_AGC2MIN, 0x00},
122 {R367TER_AGC1MAX, 0xff},
123 {R367TER_AGC1MIN, 0x00},
124 {R367TER_AGCR, 0xbc},
125 {R367TER_AGC2TH, 0x00},
126 {R367TER_AGC12C, 0x00},
127 {R367TER_AGCCTRL1, 0x85},
128 {R367TER_AGCCTRL2, 0x1f},
129 {R367TER_AGC1VAL1, 0x00},
130 {R367TER_AGC1VAL2, 0x00},
131 {R367TER_AGC2VAL1, 0x6f},
132 {R367TER_AGC2VAL2, 0x05},
133 {R367TER_AGC2PGA, 0x00},
134 {R367TER_OVF_RATE1, 0x00},
135 {R367TER_OVF_RATE2, 0x00},
136 {R367TER_GAIN_SRC1, 0xaa},/* for xc5000; was 0x2b */
137 {R367TER_GAIN_SRC2, 0xd6},/* for xc5000; was 0x04 */
138 {R367TER_INC_DEROT1, 0x55},
139 {R367TER_INC_DEROT2, 0x55},
140 {R367TER_PPM_CPAMP_DIR, 0x2c},
141 {R367TER_PPM_CPAMP_INV, 0x00},
142 {R367TER_FREESTFE_1, 0x00},
143 {R367TER_FREESTFE_2, 0x1c},
144 {R367TER_DCOFFSET, 0x00},
145 {R367TER_EN_PROCESS, 0x05},
146 {R367TER_SDI_SMOOTHER, 0x80},
147 {R367TER_FE_LOOP_OPEN, 0x1c},
148 {R367TER_FREQOFF1, 0x00},
149 {R367TER_FREQOFF2, 0x00},
150 {R367TER_FREQOFF3, 0x00},
151 {R367TER_TIMOFF1, 0x00},
152 {R367TER_TIMOFF2, 0x00},
153 {R367TER_EPQ, 0x02},
154 {R367TER_EPQAUTO, 0x01},
155 {R367TER_SYR_UPDATE, 0xf5},
156 {R367TER_CHPFREE, 0x00},
157 {R367TER_PPM_STATE_MAC, 0x23},
158 {R367TER_INR_THRESHOLD, 0xff},
159 {R367TER_EPQ_TPS_ID_CELL, 0xf9},
160 {R367TER_EPQ_CFG, 0x00},
161 {R367TER_EPQ_STATUS, 0x01},
162 {R367TER_AUTORELOCK, 0x81},
163 {R367TER_BER_THR_VMSB, 0x00},
164 {R367TER_BER_THR_MSB, 0x00},
165 {R367TER_BER_THR_LSB, 0x00},
166 {R367TER_CCD, 0x83},
167 {R367TER_SPECTR_CFG, 0x00},
168 {R367TER_CHC_DUMMY, 0x18},
169 {R367TER_INC_CTL, 0x88},
170 {R367TER_INCTHRES_COR1, 0xb4},
171 {R367TER_INCTHRES_COR2, 0x96},
172 {R367TER_INCTHRES_DET1, 0x0e},
173 {R367TER_INCTHRES_DET2, 0x11},
174 {R367TER_IIR_CELLNB, 0x8d},
175 {R367TER_IIRCX_COEFF1_MSB, 0x00},
176 {R367TER_IIRCX_COEFF1_LSB, 0x00},
177 {R367TER_IIRCX_COEFF2_MSB, 0x09},
178 {R367TER_IIRCX_COEFF2_LSB, 0x18},
179 {R367TER_IIRCX_COEFF3_MSB, 0x14},
180 {R367TER_IIRCX_COEFF3_LSB, 0x9c},
181 {R367TER_IIRCX_COEFF4_MSB, 0x00},
182 {R367TER_IIRCX_COEFF4_LSB, 0x00},
183 {R367TER_IIRCX_COEFF5_MSB, 0x36},
184 {R367TER_IIRCX_COEFF5_LSB, 0x42},
185 {R367TER_FEPATH_CFG, 0x00},
186 {R367TER_PMC1_FUNC, 0x65},
187 {R367TER_PMC1_FOR, 0x00},
188 {R367TER_PMC2_FUNC, 0x00},
189 {R367TER_STATUS_ERR_DA, 0xe0},
190 {R367TER_DIG_AGC_R, 0xfe},
191 {R367TER_COMAGC_TARMSB, 0x0b},
192 {R367TER_COM_AGC_TAR_ENMODE, 0x41},
193 {R367TER_COM_AGC_CFG, 0x3e},
194 {R367TER_COM_AGC_GAIN1, 0x39},
195 {R367TER_AUT_AGC_TARGETMSB, 0x0b},
196 {R367TER_LOCK_DET_MSB, 0x01},
197 {R367TER_AGCTAR_LOCK_LSBS, 0x40},
198 {R367TER_AUT_GAIN_EN, 0xf4},
199 {R367TER_AUT_CFG, 0xf0},
200 {R367TER_LOCKN, 0x23},
201 {R367TER_INT_X_3, 0x00},
202 {R367TER_INT_X_2, 0x03},
203 {R367TER_INT_X_1, 0x8d},
204 {R367TER_INT_X_0, 0xa0},
205 {R367TER_MIN_ERRX_MSB, 0x00},
206 {R367TER_COR_CTL, 0x23},
207 {R367TER_COR_STAT, 0xf6},
208 {R367TER_COR_INTEN, 0x00},
209 {R367TER_COR_INTSTAT, 0x3f},
210 {R367TER_COR_MODEGUARD, 0x03},
211 {R367TER_AGC_CTL, 0x08},
212 {R367TER_AGC_MANUAL1, 0x00},
213 {R367TER_AGC_MANUAL2, 0x00},
214 {R367TER_AGC_TARG, 0x16},
215 {R367TER_AGC_GAIN1, 0x53},
216 {R367TER_AGC_GAIN2, 0x1d},
217 {R367TER_RESERVED_1, 0x00},
218 {R367TER_RESERVED_2, 0x00},
219 {R367TER_RESERVED_3, 0x00},
220 {R367TER_CAS_CTL, 0x44},
221 {R367TER_CAS_FREQ, 0xb3},
222 {R367TER_CAS_DAGCGAIN, 0x12},
223 {R367TER_SYR_CTL, 0x04},
224 {R367TER_SYR_STAT, 0x10},
225 {R367TER_SYR_NCO1, 0x00},
226 {R367TER_SYR_NCO2, 0x00},
227 {R367TER_SYR_OFFSET1, 0x00},
228 {R367TER_SYR_OFFSET2, 0x00},
229 {R367TER_FFT_CTL, 0x00},
230 {R367TER_SCR_CTL, 0x70},
231 {R367TER_PPM_CTL1, 0xf8},
232 {R367TER_TRL_CTL, 0x14},/* for xc5000; was 0xac */
233 {R367TER_TRL_NOMRATE1, 0xae},/* for xc5000; was 0x1e */
234 {R367TER_TRL_NOMRATE2, 0x56},/* for xc5000; was 0x58 */
235 {R367TER_TRL_TIME1, 0x1d},
236 {R367TER_TRL_TIME2, 0xfc},
237 {R367TER_CRL_CTL, 0x24},
238 {R367TER_CRL_FREQ1, 0xad},
239 {R367TER_CRL_FREQ2, 0x9d},
240 {R367TER_CRL_FREQ3, 0xff},
241 {R367TER_CHC_CTL, 0x01},
242 {R367TER_CHC_SNR, 0xf0},
243 {R367TER_BDI_CTL, 0x00},
244 {R367TER_DMP_CTL, 0x00},
245 {R367TER_TPS_RCVD1, 0x30},
246 {R367TER_TPS_RCVD2, 0x02},
247 {R367TER_TPS_RCVD3, 0x01},
248 {R367TER_TPS_RCVD4, 0x00},
249 {R367TER_TPS_ID_CELL1, 0x00},
250 {R367TER_TPS_ID_CELL2, 0x00},
251 {R367TER_TPS_RCVD5_SET1, 0x02},
252 {R367TER_TPS_SET2, 0x02},
253 {R367TER_TPS_SET3, 0x01},
254 {R367TER_TPS_CTL, 0x00},
255 {R367TER_CTL_FFTOSNUM, 0x34},
256 {R367TER_TESTSELECT, 0x09},
257 {R367TER_MSC_REV, 0x0a},
258 {R367TER_PIR_CTL, 0x00},
259 {R367TER_SNR_CARRIER1, 0xa1},
260 {R367TER_SNR_CARRIER2, 0x9a},
261 {R367TER_PPM_CPAMP, 0x2c},
262 {R367TER_TSM_AP0, 0x00},
263 {R367TER_TSM_AP1, 0x00},
264 {R367TER_TSM_AP2 , 0x00},
265 {R367TER_TSM_AP3, 0x00},
266 {R367TER_TSM_AP4, 0x00},
267 {R367TER_TSM_AP5, 0x00},
268 {R367TER_TSM_AP6, 0x00},
269 {R367TER_TSM_AP7, 0x00},
270 {R367TER_TSTRES, 0x00},
271 {R367TER_ANACTRL, 0x0D},/* PLL stoped, restart at init!!! */
272 {R367TER_TSTBUS, 0x00},
273 {R367TER_TSTRATE, 0x00},
274 {R367TER_CONSTMODE, 0x01},
275 {R367TER_CONSTCARR1, 0x00},
276 {R367TER_CONSTCARR2, 0x00},
277 {R367TER_ICONSTEL, 0x0a},
278 {R367TER_QCONSTEL, 0x15},
279 {R367TER_TSTBISTRES0, 0x00},
280 {R367TER_TSTBISTRES1, 0x00},
281 {R367TER_TSTBISTRES2, 0x28},
282 {R367TER_TSTBISTRES3, 0x00},
283 {R367TER_RF_AGC1, 0xff},
284 {R367TER_RF_AGC2, 0x83},
285 {R367TER_ANADIGCTRL, 0x19},
286 {R367TER_PLLMDIV, 0x01},/* for xc5000; was 0x0c */
287 {R367TER_PLLNDIV, 0x06},/* for xc5000; was 0x55 */
288 {R367TER_PLLSETUP, 0x18},
289 {R367TER_DUAL_AD12, 0x0C},/* for xc5000 AGC voltage 1.6V */
290 {R367TER_TSTBIST, 0x00},
291 {R367TER_PAD_COMP_CTRL, 0x00},
292 {R367TER_PAD_COMP_WR, 0x00},
293 {R367TER_PAD_COMP_RD, 0xe0},
294 {R367TER_SYR_TARGET_FFTADJT_MSB, 0x00},
295 {R367TER_SYR_TARGET_FFTADJT_LSB, 0x00},
296 {R367TER_SYR_TARGET_CHCADJT_MSB, 0x00},
297 {R367TER_SYR_TARGET_CHCADJT_LSB, 0x00},
298 {R367TER_SYR_FLAG, 0x00},
299 {R367TER_CRL_TARGET1, 0x00},
300 {R367TER_CRL_TARGET2, 0x00},
301 {R367TER_CRL_TARGET3, 0x00},
302 {R367TER_CRL_TARGET4, 0x00},
303 {R367TER_CRL_FLAG, 0x00},
304 {R367TER_TRL_TARGET1, 0x00},
305 {R367TER_TRL_TARGET2, 0x00},
306 {R367TER_TRL_CHC, 0x00},
307 {R367TER_CHC_SNR_TARG, 0x00},
308 {R367TER_TOP_TRACK, 0x00},
309 {R367TER_TRACKER_FREE1, 0x00},
310 {R367TER_ERROR_CRL1, 0x00},
311 {R367TER_ERROR_CRL2, 0x00},
312 {R367TER_ERROR_CRL3, 0x00},
313 {R367TER_ERROR_CRL4, 0x00},
314 {R367TER_DEC_NCO1, 0x2c},
315 {R367TER_DEC_NCO2, 0x0f},
316 {R367TER_DEC_NCO3, 0x20},
317 {R367TER_SNR, 0xf1},
318 {R367TER_SYR_FFTADJ1, 0x00},
319 {R367TER_SYR_FFTADJ2, 0x00},
320 {R367TER_SYR_CHCADJ1, 0x00},
321 {R367TER_SYR_CHCADJ2, 0x00},
322 {R367TER_SYR_OFF, 0x00},
323 {R367TER_PPM_OFFSET1, 0x00},
324 {R367TER_PPM_OFFSET2, 0x03},
325 {R367TER_TRACKER_FREE2, 0x00},
326 {R367TER_DEBG_LT10, 0x00},
327 {R367TER_DEBG_LT11, 0x00},
328 {R367TER_DEBG_LT12, 0x00},
329 {R367TER_DEBG_LT13, 0x00},
330 {R367TER_DEBG_LT14, 0x00},
331 {R367TER_DEBG_LT15, 0x00},
332 {R367TER_DEBG_LT16, 0x00},
333 {R367TER_DEBG_LT17, 0x00},
334 {R367TER_DEBG_LT18, 0x00},
335 {R367TER_DEBG_LT19, 0x00},
336 {R367TER_DEBG_LT1A, 0x00},
337 {R367TER_DEBG_LT1B, 0x00},
338 {R367TER_DEBG_LT1C, 0x00},
339 {R367TER_DEBG_LT1D, 0x00},
340 {R367TER_DEBG_LT1E, 0x00},
341 {R367TER_DEBG_LT1F, 0x00},
342 {R367TER_RCCFGH, 0x00},
343 {R367TER_RCCFGM, 0x00},
344 {R367TER_RCCFGL, 0x00},
345 {R367TER_RCINSDELH, 0x00},
346 {R367TER_RCINSDELM, 0x00},
347 {R367TER_RCINSDELL, 0x00},
348 {R367TER_RCSTATUS, 0x00},
349 {R367TER_RCSPEED, 0x6f},
350 {R367TER_RCDEBUGM, 0xe7},
351 {R367TER_RCDEBUGL, 0x9b},
352 {R367TER_RCOBSCFG, 0x00},
353 {R367TER_RCOBSM, 0x00},
354 {R367TER_RCOBSL, 0x00},
355 {R367TER_RCFECSPY, 0x00},
356 {R367TER_RCFSPYCFG, 0x00},
357 {R367TER_RCFSPYDATA, 0x00},
358 {R367TER_RCFSPYOUT, 0x00},
359 {R367TER_RCFSTATUS, 0x00},
360 {R367TER_RCFGOODPACK, 0x00},
361 {R367TER_RCFPACKCNT, 0x00},
362 {R367TER_RCFSPYMISC, 0x00},
363 {R367TER_RCFBERCPT4, 0x00},
364 {R367TER_RCFBERCPT3, 0x00},
365 {R367TER_RCFBERCPT2, 0x00},
366 {R367TER_RCFBERCPT1, 0x00},
367 {R367TER_RCFBERCPT0, 0x00},
368 {R367TER_RCFBERERR2, 0x00},
369 {R367TER_RCFBERERR1, 0x00},
370 {R367TER_RCFBERERR0, 0x00},
371 {R367TER_RCFSTATESM, 0x00},
372 {R367TER_RCFSTATESL, 0x00},
373 {R367TER_RCFSPYBER, 0x00},
374 {R367TER_RCFSPYDISTM, 0x00},
375 {R367TER_RCFSPYDISTL, 0x00},
376 {R367TER_RCFSPYOBS7, 0x00},
377 {R367TER_RCFSPYOBS6, 0x00},
378 {R367TER_RCFSPYOBS5, 0x00},
379 {R367TER_RCFSPYOBS4, 0x00},
380 {R367TER_RCFSPYOBS3, 0x00},
381 {R367TER_RCFSPYOBS2, 0x00},
382 {R367TER_RCFSPYOBS1, 0x00},
383 {R367TER_RCFSPYOBS0, 0x00},
384 {R367TER_TSGENERAL, 0x00},
385 {R367TER_RC1SPEED, 0x6f},
386 {R367TER_TSGSTATUS, 0x18},
387 {R367TER_FECM, 0x01},
388 {R367TER_VTH12, 0xff},
389 {R367TER_VTH23, 0xa1},
390 {R367TER_VTH34, 0x64},
391 {R367TER_VTH56, 0x40},
392 {R367TER_VTH67, 0x00},
393 {R367TER_VTH78, 0x2c},
394 {R367TER_VITCURPUN, 0x12},
395 {R367TER_VERROR, 0x01},
396 {R367TER_PRVIT, 0x3f},
397 {R367TER_VAVSRVIT, 0x00},
398 {R367TER_VSTATUSVIT, 0xbd},
399 {R367TER_VTHINUSE, 0xa1},
400 {R367TER_KDIV12, 0x20},
401 {R367TER_KDIV23, 0x40},
402 {R367TER_KDIV34, 0x20},
403 {R367TER_KDIV56, 0x30},
404 {R367TER_KDIV67, 0x00},
405 {R367TER_KDIV78, 0x30},
406 {R367TER_SIGPOWER, 0x54},
407 {R367TER_DEMAPVIT, 0x40},
408 {R367TER_VITSCALE, 0x00},
409 {R367TER_FFEC1PRG, 0x00},
410 {R367TER_FVITCURPUN, 0x12},
411 {R367TER_FVERROR, 0x01},
412 {R367TER_FVSTATUSVIT, 0xbd},
413 {R367TER_DEBUG_LT1, 0x00},
414 {R367TER_DEBUG_LT2, 0x00},
415 {R367TER_DEBUG_LT3, 0x00},
416 {R367TER_TSTSFMET, 0x00},
417 {R367TER_SELOUT, 0x00},
418 {R367TER_TSYNC, 0x00},
419 {R367TER_TSTERR, 0x00},
420 {R367TER_TSFSYNC, 0x00},
421 {R367TER_TSTSFERR, 0x00},
422 {R367TER_TSTTSSF1, 0x01},
423 {R367TER_TSTTSSF2, 0x1f},
424 {R367TER_TSTTSSF3, 0x00},
425 {R367TER_TSTTS1, 0x00},
426 {R367TER_TSTTS2, 0x1f},
427 {R367TER_TSTTS3, 0x01},
428 {R367TER_TSTTS4, 0x00},
429 {R367TER_TSTTSRC, 0x00},
430 {R367TER_TSTTSRS, 0x00},
431 {R367TER_TSSTATEM, 0xb0},
432 {R367TER_TSSTATEL, 0x40},
433 {R367TER_TSCFGH, 0xC0},
434 {R367TER_TSCFGM, 0xc0},/* for xc5000; was 0x00 */
435 {R367TER_TSCFGL, 0x20},
436 {R367TER_TSSYNC, 0x00},
437 {R367TER_TSINSDELH, 0x00},
438 {R367TER_TSINSDELM, 0x00},
439 {R367TER_TSINSDELL, 0x00},
440 {R367TER_TSDIVN, 0x03},
441 {R367TER_TSDIVPM, 0x00},
442 {R367TER_TSDIVPL, 0x00},
443 {R367TER_TSDIVQM, 0x00},
444 {R367TER_TSDIVQL, 0x00},
445 {R367TER_TSDILSTKM, 0x00},
446 {R367TER_TSDILSTKL, 0x00},
447 {R367TER_TSSPEED, 0x40},/* for xc5000; was 0x6f */
448 {R367TER_TSSTATUS, 0x81},
449 {R367TER_TSSTATUS2, 0x6a},
450 {R367TER_TSBITRATEM, 0x0f},
451 {R367TER_TSBITRATEL, 0xc6},
452 {R367TER_TSPACKLENM, 0x00},
453 {R367TER_TSPACKLENL, 0xfc},
454 {R367TER_TSBLOCLENM, 0x0a},
455 {R367TER_TSBLOCLENL, 0x80},
456 {R367TER_TSDLYH, 0x90},
457 {R367TER_TSDLYM, 0x68},
458 {R367TER_TSDLYL, 0x01},
459 {R367TER_TSNPDAV, 0x00},
460 {R367TER_TSBUFSTATH, 0x00},
461 {R367TER_TSBUFSTATM, 0x00},
462 {R367TER_TSBUFSTATL, 0x00},
463 {R367TER_TSDEBUGM, 0xcf},
464 {R367TER_TSDEBUGL, 0x1e},
465 {R367TER_TSDLYSETH, 0x00},
466 {R367TER_TSDLYSETM, 0x68},
467 {R367TER_TSDLYSETL, 0x00},
468 {R367TER_TSOBSCFG, 0x00},
469 {R367TER_TSOBSM, 0x47},
470 {R367TER_TSOBSL, 0x1f},
471 {R367TER_ERRCTRL1, 0x95},
472 {R367TER_ERRCNT1H, 0x80},
473 {R367TER_ERRCNT1M, 0x00},
474 {R367TER_ERRCNT1L, 0x00},
475 {R367TER_ERRCTRL2, 0x95},
476 {R367TER_ERRCNT2H, 0x00},
477 {R367TER_ERRCNT2M, 0x00},
478 {R367TER_ERRCNT2L, 0x00},
479 {R367TER_FECSPY, 0x88},
480 {R367TER_FSPYCFG, 0x2c},
481 {R367TER_FSPYDATA, 0x3a},
482 {R367TER_FSPYOUT, 0x06},
483 {R367TER_FSTATUS, 0x61},
484 {R367TER_FGOODPACK, 0xff},
485 {R367TER_FPACKCNT, 0xff},
486 {R367TER_FSPYMISC, 0x66},
487 {R367TER_FBERCPT4, 0x00},
488 {R367TER_FBERCPT3, 0x00},
489 {R367TER_FBERCPT2, 0x36},
490 {R367TER_FBERCPT1, 0x36},
491 {R367TER_FBERCPT0, 0x14},
492 {R367TER_FBERERR2, 0x00},
493 {R367TER_FBERERR1, 0x03},
494 {R367TER_FBERERR0, 0x28},
495 {R367TER_FSTATESM, 0x00},
496 {R367TER_FSTATESL, 0x02},
497 {R367TER_FSPYBER, 0x00},
498 {R367TER_FSPYDISTM, 0x01},
499 {R367TER_FSPYDISTL, 0x9f},
500 {R367TER_FSPYOBS7, 0xc9},
501 {R367TER_FSPYOBS6, 0x99},
502 {R367TER_FSPYOBS5, 0x08},
503 {R367TER_FSPYOBS4, 0xec},
504 {R367TER_FSPYOBS3, 0x01},
505 {R367TER_FSPYOBS2, 0x0f},
506 {R367TER_FSPYOBS1, 0xf5},
507 {R367TER_FSPYOBS0, 0x08},
508 {R367TER_SFDEMAP, 0x40},
509 {R367TER_SFERROR, 0x00},
510 {R367TER_SFAVSR, 0x30},
511 {R367TER_SFECSTATUS, 0xcc},
512 {R367TER_SFKDIV12, 0x20},
513 {R367TER_SFKDIV23, 0x40},
514 {R367TER_SFKDIV34, 0x20},
515 {R367TER_SFKDIV56, 0x20},
516 {R367TER_SFKDIV67, 0x00},
517 {R367TER_SFKDIV78, 0x20},
518 {R367TER_SFDILSTKM, 0x00},
519 {R367TER_SFDILSTKL, 0x00},
520 {R367TER_SFSTATUS, 0xb5},
521 {R367TER_SFDLYH, 0x90},
522 {R367TER_SFDLYM, 0x60},
523 {R367TER_SFDLYL, 0x01},
524 {R367TER_SFDLYSETH, 0xc0},
525 {R367TER_SFDLYSETM, 0x60},
526 {R367TER_SFDLYSETL, 0x00},
527 {R367TER_SFOBSCFG, 0x00},
528 {R367TER_SFOBSM, 0x47},
529 {R367TER_SFOBSL, 0x05},
530 {R367TER_SFECINFO, 0x40},
531 {R367TER_SFERRCTRL, 0x74},
532 {R367TER_SFERRCNTH, 0x80},
533 {R367TER_SFERRCNTM , 0x00},
534 {R367TER_SFERRCNTL, 0x00},
535 {R367TER_SYMBRATEM, 0x2f},
536 {R367TER_SYMBRATEL, 0x50},
537 {R367TER_SYMBSTATUS, 0x7f},
538 {R367TER_SYMBCFG, 0x00},
539 {R367TER_SYMBFIFOM, 0xf4},
540 {R367TER_SYMBFIFOL, 0x0d},
541 {R367TER_SYMBOFFSM, 0xf0},
542 {R367TER_SYMBOFFSL, 0x2d},
543 {R367TER_DEBUG_LT4, 0x00},
544 {R367TER_DEBUG_LT5, 0x00},
545 {R367TER_DEBUG_LT6, 0x00},
546 {R367TER_DEBUG_LT7, 0x00},
547 {R367TER_DEBUG_LT8, 0x00},
548 {R367TER_DEBUG_LT9, 0x00},
549};
550
551#define RF_LOOKUP_TABLE_SIZE 31
552#define RF_LOOKUP_TABLE2_SIZE 16
553/* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
554s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
555 {/*AGC1*/
556 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
557 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
558 76, 77, 78, 80, 83, 85, 88,
559 }, {/*RF(dbm)*/
560 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
561 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
562 49, 50, 52, 53, 54, 55, 56,
563 }
564};
565/* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
566s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
567 {/*AGC2*/
568 28, 29, 31, 32, 34, 35, 36, 37,
569 38, 39, 40, 41, 42, 43, 44, 45,
570 }, {/*RF(dbm)*/
571 57, 58, 59, 60, 61, 62, 63, 64,
572 65, 66, 67, 68, 69, 70, 71, 72,
573 }
574};
575
576static struct st_register def0367cab[STV0367CAB_NBREGS] = {
577 {R367CAB_ID, 0x60},
578 {R367CAB_I2CRPT, 0xa0},
579 /*{R367CAB_I2CRPT, 0x22},*/
580 {R367CAB_TOPCTRL, 0x10},
581 {R367CAB_IOCFG0, 0x80},
582 {R367CAB_DAC0R, 0x00},
583 {R367CAB_IOCFG1, 0x00},
584 {R367CAB_DAC1R, 0x00},
585 {R367CAB_IOCFG2, 0x00},
586 {R367CAB_SDFR, 0x00},
587 {R367CAB_AUX_CLK, 0x00},
588 {R367CAB_FREESYS1, 0x00},
589 {R367CAB_FREESYS2, 0x00},
590 {R367CAB_FREESYS3, 0x00},
591 {R367CAB_GPIO_CFG, 0x55},
592 {R367CAB_GPIO_CMD, 0x01},
593 {R367CAB_TSTRES, 0x00},
594 {R367CAB_ANACTRL, 0x0d},/* was 0x00 need to check - I.M.L.*/
595 {R367CAB_TSTBUS, 0x00},
596 {R367CAB_RF_AGC1, 0xea},
597 {R367CAB_RF_AGC2, 0x82},
598 {R367CAB_ANADIGCTRL, 0x0b},
599 {R367CAB_PLLMDIV, 0x01},
600 {R367CAB_PLLNDIV, 0x08},
601 {R367CAB_PLLSETUP, 0x18},
602 {R367CAB_DUAL_AD12, 0x0C}, /* for xc5000 AGC voltage 1.6V */
603 {R367CAB_TSTBIST, 0x00},
604 {R367CAB_CTRL_1, 0x00},
605 {R367CAB_CTRL_2, 0x03},
606 {R367CAB_IT_STATUS1, 0x2b},
607 {R367CAB_IT_STATUS2, 0x08},
608 {R367CAB_IT_EN1, 0x00},
609 {R367CAB_IT_EN2, 0x00},
610 {R367CAB_CTRL_STATUS, 0x04},
611 {R367CAB_TEST_CTL, 0x00},
612 {R367CAB_AGC_CTL, 0x73},
613 {R367CAB_AGC_IF_CFG, 0x50},
614 {R367CAB_AGC_RF_CFG, 0x00},
615 {R367CAB_AGC_PWM_CFG, 0x03},
616 {R367CAB_AGC_PWR_REF_L, 0x5a},
617 {R367CAB_AGC_PWR_REF_H, 0x00},
618 {R367CAB_AGC_RF_TH_L, 0xff},
619 {R367CAB_AGC_RF_TH_H, 0x07},
620 {R367CAB_AGC_IF_LTH_L, 0x00},
621 {R367CAB_AGC_IF_LTH_H, 0x08},
622 {R367CAB_AGC_IF_HTH_L, 0xff},
623 {R367CAB_AGC_IF_HTH_H, 0x07},
624 {R367CAB_AGC_PWR_RD_L, 0xa0},
625 {R367CAB_AGC_PWR_RD_M, 0xe9},
626 {R367CAB_AGC_PWR_RD_H, 0x03},
627 {R367CAB_AGC_PWM_IFCMD_L, 0xe4},
628 {R367CAB_AGC_PWM_IFCMD_H, 0x00},
629 {R367CAB_AGC_PWM_RFCMD_L, 0xff},
630 {R367CAB_AGC_PWM_RFCMD_H, 0x07},
631 {R367CAB_IQDEM_CFG, 0x01},
632 {R367CAB_MIX_NCO_LL, 0x22},
633 {R367CAB_MIX_NCO_HL, 0x96},
634 {R367CAB_MIX_NCO_HH, 0x55},
635 {R367CAB_SRC_NCO_LL, 0xff},
636 {R367CAB_SRC_NCO_LH, 0x0c},
637 {R367CAB_SRC_NCO_HL, 0xf5},
638 {R367CAB_SRC_NCO_HH, 0x20},
639 {R367CAB_IQDEM_GAIN_SRC_L, 0x06},
640 {R367CAB_IQDEM_GAIN_SRC_H, 0x01},
641 {R367CAB_IQDEM_DCRM_CFG_LL, 0xfe},
642 {R367CAB_IQDEM_DCRM_CFG_LH, 0xff},
643 {R367CAB_IQDEM_DCRM_CFG_HL, 0x0f},
644 {R367CAB_IQDEM_DCRM_CFG_HH, 0x00},
645 {R367CAB_IQDEM_ADJ_COEFF0, 0x34},
646 {R367CAB_IQDEM_ADJ_COEFF1, 0xae},
647 {R367CAB_IQDEM_ADJ_COEFF2, 0x46},
648 {R367CAB_IQDEM_ADJ_COEFF3, 0x77},
649 {R367CAB_IQDEM_ADJ_COEFF4, 0x96},
650 {R367CAB_IQDEM_ADJ_COEFF5, 0x69},
651 {R367CAB_IQDEM_ADJ_COEFF6, 0xc7},
652 {R367CAB_IQDEM_ADJ_COEFF7, 0x01},
653 {R367CAB_IQDEM_ADJ_EN, 0x04},
654 {R367CAB_IQDEM_ADJ_AGC_REF, 0x94},
655 {R367CAB_ALLPASSFILT1, 0xc9},
656 {R367CAB_ALLPASSFILT2, 0x2d},
657 {R367CAB_ALLPASSFILT3, 0xa3},
658 {R367CAB_ALLPASSFILT4, 0xfb},
659 {R367CAB_ALLPASSFILT5, 0xf6},
660 {R367CAB_ALLPASSFILT6, 0x45},
661 {R367CAB_ALLPASSFILT7, 0x6f},
662 {R367CAB_ALLPASSFILT8, 0x7e},
663 {R367CAB_ALLPASSFILT9, 0x05},
664 {R367CAB_ALLPASSFILT10, 0x0a},
665 {R367CAB_ALLPASSFILT11, 0x51},
666 {R367CAB_TRL_AGC_CFG, 0x20},
667 {R367CAB_TRL_LPF_CFG, 0x28},
668 {R367CAB_TRL_LPF_ACQ_GAIN, 0x44},
669 {R367CAB_TRL_LPF_TRK_GAIN, 0x22},
670 {R367CAB_TRL_LPF_OUT_GAIN, 0x03},
671 {R367CAB_TRL_LOCKDET_LTH, 0x04},
672 {R367CAB_TRL_LOCKDET_HTH, 0x11},
673 {R367CAB_TRL_LOCKDET_TRGVAL, 0x20},
674 {R367CAB_IQ_QAM, 0x01},
675 {R367CAB_FSM_STATE, 0xa0},
676 {R367CAB_FSM_CTL, 0x08},
677 {R367CAB_FSM_STS, 0x0c},
678 {R367CAB_FSM_SNR0_HTH, 0x00},
679 {R367CAB_FSM_SNR1_HTH, 0x00},
680 {R367CAB_FSM_SNR2_HTH, 0x23},/* 0x00 */
681 {R367CAB_FSM_SNR0_LTH, 0x00},
682 {R367CAB_FSM_SNR1_LTH, 0x00},
683 {R367CAB_FSM_EQA1_HTH, 0x00},
684 {R367CAB_FSM_TEMPO, 0x32},
685 {R367CAB_FSM_CONFIG, 0x03},
686 {R367CAB_EQU_I_TESTTAP_L, 0x11},
687 {R367CAB_EQU_I_TESTTAP_M, 0x00},
688 {R367CAB_EQU_I_TESTTAP_H, 0x00},
689 {R367CAB_EQU_TESTAP_CFG, 0x00},
690 {R367CAB_EQU_Q_TESTTAP_L, 0xff},
691 {R367CAB_EQU_Q_TESTTAP_M, 0x00},
692 {R367CAB_EQU_Q_TESTTAP_H, 0x00},
693 {R367CAB_EQU_TAP_CTRL, 0x00},
694 {R367CAB_EQU_CTR_CRL_CONTROL_L, 0x11},
695 {R367CAB_EQU_CTR_CRL_CONTROL_H, 0x05},
696 {R367CAB_EQU_CTR_HIPOW_L, 0x00},
697 {R367CAB_EQU_CTR_HIPOW_H, 0x00},
698 {R367CAB_EQU_I_EQU_LO, 0xef},
699 {R367CAB_EQU_I_EQU_HI, 0x00},
700 {R367CAB_EQU_Q_EQU_LO, 0xee},
701 {R367CAB_EQU_Q_EQU_HI, 0x00},
702 {R367CAB_EQU_MAPPER, 0xc5},
703 {R367CAB_EQU_SWEEP_RATE, 0x80},
704 {R367CAB_EQU_SNR_LO, 0x64},
705 {R367CAB_EQU_SNR_HI, 0x03},
706 {R367CAB_EQU_GAMMA_LO, 0x00},
707 {R367CAB_EQU_GAMMA_HI, 0x00},
708 {R367CAB_EQU_ERR_GAIN, 0x36},
709 {R367CAB_EQU_RADIUS, 0xaa},
710 {R367CAB_EQU_FFE_MAINTAP, 0x00},
711 {R367CAB_EQU_FFE_LEAKAGE, 0x63},
712 {R367CAB_EQU_FFE_MAINTAP_POS, 0xdf},
713 {R367CAB_EQU_GAIN_WIDE, 0x88},
714 {R367CAB_EQU_GAIN_NARROW, 0x41},
715 {R367CAB_EQU_CTR_LPF_GAIN, 0xd1},
716 {R367CAB_EQU_CRL_LPF_GAIN, 0xa7},
717 {R367CAB_EQU_GLOBAL_GAIN, 0x06},
718 {R367CAB_EQU_CRL_LD_SEN, 0x85},
719 {R367CAB_EQU_CRL_LD_VAL, 0xe2},
720 {R367CAB_EQU_CRL_TFR, 0x20},
721 {R367CAB_EQU_CRL_BISTH_LO, 0x00},
722 {R367CAB_EQU_CRL_BISTH_HI, 0x00},
723 {R367CAB_EQU_SWEEP_RANGE_LO, 0x00},
724 {R367CAB_EQU_SWEEP_RANGE_HI, 0x00},
725 {R367CAB_EQU_CRL_LIMITER, 0x40},
726 {R367CAB_EQU_MODULUS_MAP, 0x90},
727 {R367CAB_EQU_PNT_GAIN, 0xa7},
728 {R367CAB_FEC_AC_CTR_0, 0x16},
729 {R367CAB_FEC_AC_CTR_1, 0x0b},
730 {R367CAB_FEC_AC_CTR_2, 0x88},
731 {R367CAB_FEC_AC_CTR_3, 0x02},
732 {R367CAB_FEC_STATUS, 0x12},
733 {R367CAB_RS_COUNTER_0, 0x7d},
734 {R367CAB_RS_COUNTER_1, 0xd0},
735 {R367CAB_RS_COUNTER_2, 0x19},
736 {R367CAB_RS_COUNTER_3, 0x0b},
737 {R367CAB_RS_COUNTER_4, 0xa3},
738 {R367CAB_RS_COUNTER_5, 0x00},
739 {R367CAB_BERT_0, 0x01},
740 {R367CAB_BERT_1, 0x25},
741 {R367CAB_BERT_2, 0x41},
742 {R367CAB_BERT_3, 0x39},
743 {R367CAB_OUTFORMAT_0, 0xc2},
744 {R367CAB_OUTFORMAT_1, 0x22},
745 {R367CAB_SMOOTHER_2, 0x28},
746 {R367CAB_TSMF_CTRL_0, 0x01},
747 {R367CAB_TSMF_CTRL_1, 0xc6},
748 {R367CAB_TSMF_CTRL_3, 0x43},
749 {R367CAB_TS_ON_ID_0, 0x00},
750 {R367CAB_TS_ON_ID_1, 0x00},
751 {R367CAB_TS_ON_ID_2, 0x00},
752 {R367CAB_TS_ON_ID_3, 0x00},
753 {R367CAB_RE_STATUS_0, 0x00},
754 {R367CAB_RE_STATUS_1, 0x00},
755 {R367CAB_RE_STATUS_2, 0x00},
756 {R367CAB_RE_STATUS_3, 0x00},
757 {R367CAB_TS_STATUS_0, 0x00},
758 {R367CAB_TS_STATUS_1, 0x00},
759 {R367CAB_TS_STATUS_2, 0xa0},
760 {R367CAB_TS_STATUS_3, 0x00},
761 {R367CAB_T_O_ID_0, 0x00},
762 {R367CAB_T_O_ID_1, 0x00},
763 {R367CAB_T_O_ID_2, 0x00},
764 {R367CAB_T_O_ID_3, 0x00},
765};
766
767static
768int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
769{
770 u8 buf[len + 2];
771 struct i2c_msg msg = {
772 .addr = state->config->demod_address,
773 .flags = 0,
774 .buf = buf,
775 .len = len + 2
776 };
777 int ret;
778
779 buf[0] = MSB(reg);
780 buf[1] = LSB(reg);
781 memcpy(buf + 2, data, len);
782
783 if (i2cdebug)
784 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, buf[2]);
785
786 ret = i2c_transfer(state->i2c, &msg, 1);
787 if (ret != 1)
788 printk(KERN_ERR "%s: i2c write error!\n", __func__);
789
790 return (ret != 1) ? -EREMOTEIO : 0;
791}
792
793static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
794{
795 return stv0367_writeregs(state, reg, &data, 1);
796}
797
798static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
799{
800 u8 b0[] = { 0, 0 };
801 u8 b1[] = { 0 };
802 struct i2c_msg msg[] = {
803 {
804 .addr = state->config->demod_address,
805 .flags = 0,
806 .buf = b0,
807 .len = 2
808 }, {
809 .addr = state->config->demod_address,
810 .flags = I2C_M_RD,
811 .buf = b1,
812 .len = 1
813 }
814 };
815 int ret;
816
817 b0[0] = MSB(reg);
818 b0[1] = LSB(reg);
819
820 ret = i2c_transfer(state->i2c, msg, 2);
821 if (ret != 2)
822 printk(KERN_ERR "%s: i2c read error\n", __func__);
823
824 if (i2cdebug)
825 printk(KERN_DEBUG "%s: %02x: %02x\n", __func__, reg, b1[0]);
826
827 return b1[0];
828}
829
830static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
831{
832 u8 position = 0, i = 0;
833
834 (*mask) = label & 0xff;
835
836 while ((position == 0) && (i < 8)) {
837 position = ((*mask) >> i) & 0x01;
838 i++;
839 }
840
841 (*pos) = (i - 1);
842}
843
844static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
845{
846 u8 reg, mask, pos;
847
848 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
849 extract_mask_pos(label, &mask, &pos);
850
851 val = mask & (val << pos);
852
853 reg = (reg & (~mask)) | val;
854 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
855
856}
857
858static void stv0367_setbits(u8 *reg, u32 label, u8 val)
859{
860 u8 mask, pos;
861
862 extract_mask_pos(label, &mask, &pos);
863
864 val = mask & (val << pos);
865
866 (*reg) = ((*reg) & (~mask)) | val;
867}
868
869static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
870{
871 u8 val = 0xff;
872 u8 mask, pos;
873
874 extract_mask_pos(label, &mask, &pos);
875
876 val = stv0367_readreg(state, label >> 16);
877 val = (val & mask) >> pos;
878
879 return val;
880}
881
882u8 stv0367_getbits(u8 reg, u32 label)
883{
884 u8 mask, pos;
885
886 extract_mask_pos(label, &mask, &pos);
887
888 return (reg & mask) >> pos;
889}
890
891static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
892{
893 struct stv0367_state *state = fe->demodulator_priv;
894 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
895
896 dprintk("%s:\n", __func__);
897
898 if (enable) {
899 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
900 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
901 } else {
902 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
903 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
904 }
905
906 stv0367_writereg(state, R367TER_I2CRPT, tmp);
907
908 return 0;
909}
910
911static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
912{
913 struct dvb_frontend_ops *frontend_ops = NULL;
914 struct dvb_tuner_ops *tuner_ops = NULL;
915 u32 freq = 0;
916 int err = 0;
917
918 dprintk("%s:\n", __func__);
919
920
921 if (&fe->ops)
922 frontend_ops = &fe->ops;
923 if (&frontend_ops->tuner_ops)
924 tuner_ops = &frontend_ops->tuner_ops;
925 if (tuner_ops->get_frequency) {
926 err = tuner_ops->get_frequency(fe, &freq);
927 if (err < 0) {
928 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
929 return err;
930 }
931
932 dprintk("%s: frequency=%d\n", __func__, freq);
933
934 } else
935 return -1;
936
937 return freq;
938}
939
940static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
941 {
942 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
943 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
944 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
945 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
946 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
947 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
948 }, {
949 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
950 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
951 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
952 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
953 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
954 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
955 }, {
956 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
957 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
958 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
959 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
960 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
961 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
962 }
963};
964
965static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
966 {
967 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
968 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
969 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
970 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
971 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
972 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
973 }, {
974 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
975 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
976 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
977 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
978 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
979 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
980 }, {
981 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
982 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
983 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
984 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
985 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
986 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
987 }
988};
989
990static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
991 {
992 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
993 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
994 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
995 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
996 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
997 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
998 }, {
999 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
1000 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
1001 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
1002 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
1003 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
1004 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
1005
1006 }, {
1007 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
1008 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1009 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1010 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1011 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
1012 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
1013 }
1014};
1015
1016static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
1017{
1018 u32 mclk_Hz = 0; /* master clock frequency (Hz) */
1019 u32 m, n, p;
1020
1021 dprintk("%s:\n", __func__);
1022
1023 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
1024 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
1025 if (n == 0)
1026 n = n + 1;
1027
1028 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
1029 if (m == 0)
1030 m = m + 1;
1031
1032 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
1033 if (p > 5)
1034 p = 5;
1035
1036 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
1037
1038 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
1039 n, m, p, mclk_Hz, ExtClk_Hz);
1040 } else
1041 mclk_Hz = ExtClk_Hz;
1042
1043 dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
1044
1045 return mclk_Hz;
1046}
1047
1048static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
1049 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
1050{
1051 int i, j, k, freq;
1052
1053 dprintk("%s:\n", __func__);
1054
1055 freq = stv0367ter_get_mclk(state, DemodXtal);
1056
1057 if (freq == 53125000)
1058 k = 1; /* equivalent to Xtal 25M on 362*/
1059 else if (freq == 54000000)
1060 k = 0; /* equivalent to Xtal 27M on 362*/
1061 else if (freq == 52500000)
1062 k = 2; /* equivalent to Xtal 30M on 362*/
1063 else
1064 return 0;
1065
1066 for (i = 1; i <= 6; i++) {
1067 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
1068
1069 for (j = 1; j <= 5; j++) {
1070 stv0367_writereg(state,
1071 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
1072 MSB(CellsCoeffs[k][i-1][j-1]));
1073 stv0367_writereg(state,
1074 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
1075 LSB(CellsCoeffs[k][i-1][j-1]));
1076 }
1077 }
1078
1079 return 1;
1080
1081}
1082
1083static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
1084{
1085 dprintk("%s:\n", __func__);
1086
1087 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
1088
1089 /* Lock detect 1 */
1090 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
1091 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1092 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1093
1094 /* Lock detect 2 */
1095 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
1096 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
1097 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
1098
1099 /* Lock detect 3 */
1100 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
1101 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1102 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1103
1104 /* Lock detect 4 */
1105 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
1106 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
1107 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
1108
1109}
1110
1111static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
1112 u32 DemodXtalValue)
1113{
1114 dprintk("%s:\n", __func__);
1115
1116 stv0367_writebits(state, F367TER_NRST_IIR, 0);
1117
1118 switch (Bandwidth) {
1119 case 6:
1120 if (!stv0367ter_filt_coeff_init(state,
1121 CellsCoeffs_6MHz_367cofdm,
1122 DemodXtalValue))
1123 return 0;
1124 break;
1125 case 7:
1126 if (!stv0367ter_filt_coeff_init(state,
1127 CellsCoeffs_7MHz_367cofdm,
1128 DemodXtalValue))
1129 return 0;
1130 break;
1131 case 8:
1132 if (!stv0367ter_filt_coeff_init(state,
1133 CellsCoeffs_8MHz_367cofdm,
1134 DemodXtalValue))
1135 return 0;
1136 break;
1137 default:
1138 return 0;
1139 }
1140
1141 stv0367_writebits(state, F367TER_NRST_IIR, 1);
1142
1143 return 1;
1144}
1145
1146static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
1147{
1148
1149 u8 com_n;
1150
1151 dprintk("%s:\n", __func__);
1152
1153 com_n = stv0367_readbits(state, F367TER_COM_N);
1154
1155 stv0367_writebits(state, F367TER_COM_N, 0x07);
1156
1157 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
1158 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
1159
1160 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
1161 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
1162
1163 stv0367_writebits(state, F367TER_COM_N, com_n);
1164
1165}
1166
1167static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
1168{
1169 int local_tempo = 0;
1170 switch (mode) {
1171 case 0:
1172 local_tempo = tempo1;
1173 break;
1174 case 1:
1175 local_tempo = tempo2;
1176 break ;
1177
1178 case 2:
1179 local_tempo = tempo3;
1180 break;
1181
1182 default:
1183 break;
1184 }
1185 /* msleep(local_tempo); */
1186 return local_tempo;
1187}
1188
1189static enum
1190stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
1191{
1192 int wd = 100;
1193 unsigned short int SYR_var;
1194 s32 SYRStatus;
1195
1196 dprintk("%s:\n", __func__);
1197
1198 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1199
1200 while ((!SYR_var) && (wd > 0)) {
1201 usleep_range(2000, 3000);
1202 wd -= 2;
1203 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
1204 }
1205
1206 if (!SYR_var)
1207 SYRStatus = FE_TER_NOSYMBOL;
1208 else
1209 SYRStatus = FE_TER_SYMBOLOK;
1210
1211 dprintk("stv0367ter_check_syr SYRStatus %s\n",
1212 SYR_var == 0 ? "No Symbol" : "OK");
1213
1214 return SYRStatus;
1215}
1216
1217static enum
1218stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
1219 s32 FFTmode)
1220{
1221
1222 s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
1223 int wd = 0;
1224
1225 dprintk("%s:\n", __func__);
1226
1227 switch (FFTmode) {
1228 case 0: /*2k mode*/
1229 CPAMPMin = 20;
1230 wd = 10;
1231 break;
1232 case 1: /*8k mode*/
1233 CPAMPMin = 80;
1234 wd = 55;
1235 break;
1236 case 2: /*4k mode*/
1237 CPAMPMin = 40;
1238 wd = 30;
1239 break;
1240 default:
1241 CPAMPMin = 0xffff; /*drives to NOCPAMP */
1242 break;
1243 }
1244
1245 dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
1246
1247 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1248 while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
1249 usleep_range(1000, 2000);
1250 wd -= 1;
1251 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
1252 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
1253 }
1254 dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
1255 if (CPAMPvalue < CPAMPMin) {
1256 CPAMPStatus = FE_TER_NOCPAMP;
1257 printk(KERN_ERR "CPAMP failed\n");
1258 } else {
1259 printk(KERN_ERR "CPAMP OK !\n");
1260 CPAMPStatus = FE_TER_CPAMPOK;
1261 }
1262
1263 return CPAMPStatus;
1264}
1265
1266enum
1267stv0367_ter_signal_type stv0367ter_lock_algo(struct stv0367_state *state)
1268{
1269 enum stv0367_ter_signal_type ret_flag;
1270 short int wd, tempo;
1271 u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
1272 u8 tmp, tmp2;
1273
1274 dprintk("%s:\n", __func__);
1275
1276 if (state == NULL)
1277 return FE_TER_SWNOK;
1278
1279 try = 0;
1280 do {
1281 ret_flag = FE_TER_LOCKOK;
1282
1283 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1284
1285 if (state->config->if_iq_mode != 0)
1286 stv0367_writebits(state, F367TER_COM_N, 0x07);
1287
1288 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
1289 stv0367_writebits(state, F367TER_MODE, 0);
1290 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
1291 usleep_range(5000, 10000);
1292
1293 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1294
1295
1296 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
1297 return FE_TER_NOSYMBOL;
1298 else { /*
1299 if chip locked on wrong mode first try,
1300 it must lock correctly second try */
1301 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1302 if (stv0367ter_check_cpamp(state, mode) ==
1303 FE_TER_NOCPAMP) {
1304 if (try == 0)
1305 ret_flag = FE_TER_NOCPAMP;
1306
1307 }
1308 }
1309
1310 try++;
1311 } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
1312
1313 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
1314 tmp2 = stv0367_readreg(state, R367TER_STATUS);
1315 dprintk("state=%p\n", state);
1316 dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
1317 mode, tmp, tmp2);
1318
1319 tmp = stv0367_readreg(state, R367TER_PRVIT);
1320 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
1321 dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
1322
1323 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
1324 dprintk("GAIN_SRC1=0x%x\n", tmp);
1325
1326 if ((mode != 0) && (mode != 1) && (mode != 2))
1327 return FE_TER_SWNOK;
1328
1329 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
1330
1331 /*supress EPQ auto for SYR_GARD 1/16 or 1/32
1332 and set channel predictor in automatic */
1333#if 0
1334 switch (guard) {
1335
1336 case 0:
1337 case 1:
1338 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1339 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
1340 break;
1341 case 2:
1342 case 3:
1343 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1344 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1345 break;
1346
1347 default:
1348 return FE_TER_SWNOK;
1349 }
1350#endif
1351
1352 /*reset fec an reedsolo FOR 367 only*/
1353 stv0367_writebits(state, F367TER_RST_SFEC, 1);
1354 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
1355 usleep_range(1000, 2000);
1356 stv0367_writebits(state, F367TER_RST_SFEC, 0);
1357 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
1358
1359 u_var1 = stv0367_readbits(state, F367TER_LK);
1360 u_var2 = stv0367_readbits(state, F367TER_PRF);
1361 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1362 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
1363
1364 wd = stv0367ter_duration(mode, 125, 500, 250);
1365 tempo = stv0367ter_duration(mode, 4, 16, 8);
1366
1367 /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
1368 while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
1369 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1370 wd -= tempo;
1371 u_var1 = stv0367_readbits(state, F367TER_LK);
1372 u_var2 = stv0367_readbits(state, F367TER_PRF);
1373 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
1374 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
1375 }
1376
1377 if (!u_var1)
1378 return FE_TER_NOLOCK;
1379
1380
1381 if (!u_var2)
1382 return FE_TER_NOPRFOUND;
1383
1384 if (!u_var3)
1385 return FE_TER_NOTPS;
1386
1387 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1388 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
1389 switch (guard) {
1390 case 0:
1391 case 1:
1392 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
1393 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
1394 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
1395 break;
1396 case 2:
1397 case 3:
1398 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
1399 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
1400 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
1401 break;
1402
1403 default:
1404 return FE_TER_SWNOK;
1405 }
1406
1407 /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
1408 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
1409 (mode == 1) &&
1410 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
1411 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
1412 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
1413 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
1414 } else
1415 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
1416
1417 wd = stv0367ter_duration(mode, 125, 500, 250);
1418 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1419
1420 while ((!u_var4) && (wd >= 0)) {
1421 usleep_range(1000 * tempo, 1000 * (tempo + 1));
1422 wd -= tempo;
1423 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
1424 }
1425
1426 if (!u_var4)
1427 return FE_TER_NOLOCK;
1428
1429 /* for 367 leave COM_N at 0x7 for IQ_mode*/
1430 /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
1431 tempo=0;
1432 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
1433 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
1434 ChipWaitOrAbort(state,1);
1435 tempo+=1;
1436 }
1437
1438 stv0367_writebits(state,F367TER_COM_N,0x17);
1439 } */
1440
1441 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
1442
1443 dprintk("FE_TER_LOCKOK !!!\n");
1444
1445 return FE_TER_LOCKOK;
1446
1447}
1448
1449static void stv0367ter_set_ts_mode(struct stv0367_state *state,
1450 enum stv0367_ts_mode PathTS)
1451{
1452
1453 dprintk("%s:\n", __func__);
1454
1455 if (state == NULL)
1456 return;
1457
1458 stv0367_writebits(state, F367TER_TS_DIS, 0);
1459 switch (PathTS) {
1460 default:
1461 /*for removing warning :default we can assume in parallel mode*/
1462 case STV0367_PARALLEL_PUNCT_CLOCK:
1463 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
1464 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
1465 break;
1466 case STV0367_SERIAL_PUNCT_CLOCK:
1467 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
1468 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
1469 break;
1470 }
1471}
1472
1473static void stv0367ter_set_clk_pol(struct stv0367_state *state,
1474 enum stv0367_clk_pol clock)
1475{
1476
1477 dprintk("%s:\n", __func__);
1478
1479 if (state == NULL)
1480 return;
1481
1482 switch (clock) {
1483 case STV0367_RISINGEDGE_CLOCK:
1484 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
1485 break;
1486 case STV0367_FALLINGEDGE_CLOCK:
1487 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1488 break;
1489 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
1490 default:
1491 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
1492 break;
1493 }
1494}
1495
1496#if 0
1497static void stv0367ter_core_sw(struct stv0367_state *state)
1498{
1499
1500 dprintk("%s:\n", __func__);
1501
1502 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1503 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1504 msleep(350);
1505}
1506#endif
1507static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
1508{
1509 struct stv0367_state *state = fe->demodulator_priv;
1510
1511 dprintk("%s:\n", __func__);
1512
1513 if (standby_on) {
1514 stv0367_writebits(state, F367TER_STDBY, 1);
1515 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
1516 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
1517 } else {
1518 stv0367_writebits(state, F367TER_STDBY, 0);
1519 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
1520 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
1521 }
1522
1523 return 0;
1524}
1525
1526static int stv0367ter_sleep(struct dvb_frontend *fe)
1527{
1528 return stv0367ter_standby(fe, 1);
1529}
1530
1531int stv0367ter_init(struct dvb_frontend *fe)
1532{
1533 struct stv0367_state *state = fe->demodulator_priv;
1534 struct stv0367ter_state *ter_state = state->ter_state;
1535 int i;
1536
1537 dprintk("%s:\n", __func__);
1538
1539 ter_state->pBER = 0;
1540
1541 for (i = 0; i < STV0367TER_NBREGS; i++)
1542 stv0367_writereg(state, def0367ter[i].addr,
1543 def0367ter[i].value);
1544
1545 switch (state->config->xtal) {
1546 /*set internal freq to 53.125MHz */
1547 case 25000000:
1548 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
1549 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1550 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1551 break;
1552 default:
1553 case 27000000:
1554 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
1555 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
1556 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
1557 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1558 break;
1559 case 30000000:
1560 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
1561 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
1562 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
1563 break;
1564 }
1565
1566 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
1567 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
1568
1569 /*Set TS1 and TS2 to serial or parallel mode */
1570 stv0367ter_set_ts_mode(state, state->config->ts_mode);
1571 stv0367ter_set_clk_pol(state, state->config->clk_pol);
1572
1573 state->chip_id = stv0367_readreg(state, R367TER_ID);
1574 ter_state->first_lock = 0;
1575 ter_state->unlock_counter = 2;
1576
1577 return 0;
1578}
1579
1580static int stv0367ter_algo(struct dvb_frontend *fe,
1581 struct dvb_frontend_parameters *param)
1582{
1583 struct stv0367_state *state = fe->demodulator_priv;
1584 struct stv0367ter_state *ter_state = state->ter_state;
1585 int offset = 0, tempo = 0;
1586 u8 u_var;
1587 u8 /*constell,*/ counter, tps_rcvd[2];
1588 s8 step;
1589 s32 timing_offset = 0;
1590 u32 trl_nomrate = 0, InternalFreq = 0, temp = 0;
1591
1592 dprintk("%s:\n", __func__);
1593
1594 ter_state->frequency = param->frequency;
1595 ter_state->force = FE_TER_FORCENONE
1596 + stv0367_readbits(state, F367TER_FORCE) * 2;
1597 ter_state->if_iq_mode = state->config->if_iq_mode;
1598 switch (state->config->if_iq_mode) {
1599 case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
1600 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1601 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1602 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1603 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1604 break;
1605 case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
1606 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1607 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1608 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1609 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1610 break;
1611 case FE_TER_IQ_TUNER: /* IQ mode */
1612 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1613 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1614 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1615 break;
1616 default:
1617 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1618 return -EINVAL;
1619 }
1620
1621 usleep_range(5000, 7000);
1622
1623 switch (param->inversion) {
1624 case INVERSION_AUTO:
1625 default:
1626 dprintk("%s: inversion AUTO\n", __func__);
1627 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1628 stv0367_writebits(state, F367TER_IQ_INVERT,
1629 ter_state->sense);
1630 else
1631 stv0367_writebits(state, F367TER_INV_SPECTR,
1632 ter_state->sense);
1633
1634 break;
1635 case INVERSION_ON:
1636 case INVERSION_OFF:
1637 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1638 stv0367_writebits(state, F367TER_IQ_INVERT,
1639 param->inversion);
1640 else
1641 stv0367_writebits(state, F367TER_INV_SPECTR,
1642 param->inversion);
1643
1644 break;
1645 }
1646
1647 if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1648 (ter_state->pBW != ter_state->bw)) {
1649 stv0367ter_agc_iir_lock_detect_set(state);
1650
1651 /*set fine agc target to 180 for LPIF or IQ mode*/
1652 /* set Q_AGCTarget */
1653 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1654 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1655 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1656
1657 /* set Q_AGCTarget */
1658 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1659 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1660 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1661
1662 if (!stv0367_iir_filt_init(state, ter_state->bw,
1663 state->config->xtal))
1664 return -EINVAL;
1665 /*set IIR filter once for 6,7 or 8MHz BW*/
1666 ter_state->pBW = ter_state->bw;
1667
1668 stv0367ter_agc_iir_rst(state);
1669 }
1670
1671 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1672 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1673 else
1674 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1675
1676 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1677 temp = (int)
1678 ((((ter_state->bw * 64 * (1 << 15) * 100)
1679 / (InternalFreq)) * 10) / 7);
1680
1681 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1682 temp = temp / 2;
1683 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1684 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1685
1686 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1687 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1688 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1689 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1690 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1691 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1692 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1693 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1694
1695 temp = (int)
1696 ((InternalFreq - state->config->if_khz) * (1 << 16)
1697 / (InternalFreq));
1698
1699 dprintk("DEROT temp=0x%x\n", temp);
1700 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1701 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1702
1703 ter_state->echo_pos = 0;
1704 ter_state->ucblocks = 0; /* liplianin */
1705 ter_state->pBER = 0; /* liplianin */
1706 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1707
1708 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1709 return 0;
1710
1711 ter_state->state = FE_TER_LOCKOK;
1712 /* update results */
1713 tps_rcvd[0] = stv0367_readreg(state, R367TER_TPS_RCVD2);
1714 tps_rcvd[1] = stv0367_readreg(state, R367TER_TPS_RCVD3);
1715
1716 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1717 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1718
1719 ter_state->first_lock = 1; /* we know sense now :) */
1720
1721 ter_state->agc_val =
1722 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1723 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1724 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1725 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1726
1727 /* Carrier offset calculation */
1728 stv0367_writebits(state, F367TER_FREEZE, 1);
1729 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1730 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1731 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1732 stv0367_writebits(state, F367TER_FREEZE, 0);
1733 if (offset > 8388607)
1734 offset -= 16777216;
1735
1736 offset = offset * 2 / 16384;
1737
1738 if (ter_state->mode == FE_TER_MODE_2K)
1739 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1740 else if (ter_state->mode == FE_TER_MODE_4K)
1741 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1742 else if (ter_state->mode == FE_TER_MODE_8K)
1743 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1744
1745 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1746 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1747 (stv0367_readbits(state,
1748 F367TER_STATUS_INV_SPECRUM) == 1)))
1749 offset = offset * -1;
1750 }
1751
1752 if (ter_state->bw == 6)
1753 offset = (offset * 6) / 8;
1754 else if (ter_state->bw == 7)
1755 offset = (offset * 7) / 8;
1756
1757 ter_state->frequency += offset;
1758
1759 tempo = 10; /* exit even if timing_offset stays null */
1760 while ((timing_offset == 0) && (tempo > 0)) {
1761 usleep_range(10000, 20000); /*was 20ms */
1762 /* fine tuning of timing offset if required */
1763 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1764 + 256 * stv0367_readbits(state,
1765 F367TER_TRL_TOFFSET_HI);
1766 if (timing_offset >= 32768)
1767 timing_offset -= 65536;
1768 trl_nomrate = (512 * stv0367_readbits(state,
1769 F367TER_TRL_NOMRATE_HI)
1770 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1771 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1772
1773 timing_offset = ((signed)(1000000 / trl_nomrate) *
1774 timing_offset) / 2048;
1775 tempo--;
1776 }
1777
1778 if (timing_offset <= 0) {
1779 timing_offset = (timing_offset - 11) / 22;
1780 step = -1;
1781 } else {
1782 timing_offset = (timing_offset + 11) / 22;
1783 step = 1;
1784 }
1785
1786 for (counter = 0; counter < abs(timing_offset); counter++) {
1787 trl_nomrate += step;
1788 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1789 trl_nomrate % 2);
1790 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1791 trl_nomrate / 2);
1792 usleep_range(1000, 2000);
1793 }
1794
1795 usleep_range(5000, 6000);
1796 /* unlocks could happen in case of trl centring big step,
1797 then a core off/on restarts demod */
1798 u_var = stv0367_readbits(state, F367TER_LK);
1799
1800 if (!u_var) {
1801 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1802 msleep(20);
1803 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1804 }
1805
1806 return 0;
1807}
1808
1809static int stv0367ter_set_frontend(struct dvb_frontend *fe,
1810 struct dvb_frontend_parameters *param)
1811{
1812 struct dvb_ofdm_parameters *op = &param->u.ofdm;
1813 struct stv0367_state *state = fe->demodulator_priv;
1814 struct stv0367ter_state *ter_state = state->ter_state;
1815
1816 /*u8 trials[2]; */
1817 s8 num_trials, index;
1818 u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1819
1820 stv0367ter_init(fe);
1821
1822 if (fe->ops.tuner_ops.set_params) {
1823 if (fe->ops.i2c_gate_ctrl)
1824 fe->ops.i2c_gate_ctrl(fe, 1);
1825 fe->ops.tuner_ops.set_params(fe, param);
1826 if (fe->ops.i2c_gate_ctrl)
1827 fe->ops.i2c_gate_ctrl(fe, 0);
1828 }
1829
1830 switch (op->transmission_mode) {
1831 default:
1832 case TRANSMISSION_MODE_AUTO:
1833 case TRANSMISSION_MODE_2K:
1834 ter_state->mode = FE_TER_MODE_2K;
1835 break;
1836/* case TRANSMISSION_MODE_4K:
1837 pLook.mode = FE_TER_MODE_4K;
1838 break;*/
1839 case TRANSMISSION_MODE_8K:
1840 ter_state->mode = FE_TER_MODE_8K;
1841 break;
1842 }
1843
1844 switch (op->guard_interval) {
1845 default:
1846 case GUARD_INTERVAL_1_32:
1847 case GUARD_INTERVAL_1_16:
1848 case GUARD_INTERVAL_1_8:
1849 case GUARD_INTERVAL_1_4:
1850 ter_state->guard = op->guard_interval;
1851 break;
1852 case GUARD_INTERVAL_AUTO:
1853 ter_state->guard = GUARD_INTERVAL_1_32;
1854 break;
1855 }
1856
1857 switch (op->bandwidth) {
1858 case BANDWIDTH_6_MHZ:
1859 ter_state->bw = FE_TER_CHAN_BW_6M;
1860 break;
1861 case BANDWIDTH_7_MHZ:
1862 ter_state->bw = FE_TER_CHAN_BW_7M;
1863 break;
1864 case BANDWIDTH_8_MHZ:
1865 default:
1866 ter_state->bw = FE_TER_CHAN_BW_8M;
1867 }
1868
1869 ter_state->hierarchy = FE_TER_HIER_NONE;
1870
1871 switch (param->inversion) {
1872 case INVERSION_OFF:
1873 case INVERSION_ON:
1874 num_trials = 1;
1875 break;
1876 default:
1877 num_trials = 2;
1878 if (ter_state->first_lock)
1879 num_trials = 1;
1880 break;
1881 }
1882
1883 ter_state->state = FE_TER_NOLOCK;
1884 index = 0;
1885
1886 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1887 if (!ter_state->first_lock) {
1888 if (param->inversion == INVERSION_AUTO)
1889 ter_state->sense = SenseTrials[index];
1890
1891 }
1892 stv0367ter_algo(fe,/* &pLook, result,*/ param);
1893
1894 if ((ter_state->state == FE_TER_LOCKOK) &&
1895 (param->inversion == INVERSION_AUTO) &&
1896 (index == 1)) {
1897 /* invert spectrum sense */
1898 SenseTrials[index] = SenseTrials[0];
1899 SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1900 }
1901
1902 index++;
1903 }
1904
1905 return 0;
1906}
1907
1908static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1909{
1910 struct stv0367_state *state = fe->demodulator_priv;
1911 struct stv0367ter_state *ter_state = state->ter_state;
1912 u32 errs = 0;
1913
1914 /*wait for counting completion*/
1915 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1916 errs =
1917 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1918 * (1 << 16))
1919 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1920 * (1 << 8))
1921 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1922 ter_state->ucblocks = errs;
1923 }
1924
1925 (*ucblocks) = ter_state->ucblocks;
1926
1927 return 0;
1928}
1929
1930static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1931 struct dvb_frontend_parameters *param)
1932{
1933 struct stv0367_state *state = fe->demodulator_priv;
1934 struct stv0367ter_state *ter_state = state->ter_state;
1935 struct dvb_ofdm_parameters *op = &param->u.ofdm;
1936 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1937
1938 int error = 0;
1939 enum stv0367_ter_mode mode;
1940 int constell = 0,/* snr = 0,*/ Data = 0;
1941
1942 param->frequency = stv0367_get_tuner_freq(fe);
1943 if ((int)param->frequency < 0)
1944 param->frequency = c->frequency;
1945
1946 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1947 if (constell == 0)
1948 op->constellation = QPSK;
1949 else if (constell == 1)
1950 op->constellation = QAM_16;
1951 else
1952 op->constellation = QAM_64;
1953
1954 param->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1955
1956 /* Get the Hierarchical mode */
1957 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1958
1959 switch (Data) {
1960 case 0:
1961 op->hierarchy_information = HIERARCHY_NONE;
1962 break;
1963 case 1:
1964 op->hierarchy_information = HIERARCHY_1;
1965 break;
1966 case 2:
1967 op->hierarchy_information = HIERARCHY_2;
1968 break;
1969 case 3:
1970 op->hierarchy_information = HIERARCHY_4;
1971 break;
1972 default:
1973 op->hierarchy_information = HIERARCHY_AUTO;
1974 break; /* error */
1975 }
1976
1977 /* Get the FEC Rate */
1978 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1979 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1980 else
1981 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1982
1983 switch (Data) {
1984 case 0:
1985 op->code_rate_HP = FEC_1_2;
1986 break;
1987 case 1:
1988 op->code_rate_HP = FEC_2_3;
1989 break;
1990 case 2:
1991 op->code_rate_HP = FEC_3_4;
1992 break;
1993 case 3:
1994 op->code_rate_HP = FEC_5_6;
1995 break;
1996 case 4:
1997 op->code_rate_HP = FEC_7_8;
1998 break;
1999 default:
2000 op->code_rate_HP = FEC_AUTO;
2001 break; /* error */
2002 }
2003
2004 mode = stv0367_readbits(state, F367TER_SYR_MODE);
2005
2006 switch (mode) {
2007 case FE_TER_MODE_2K:
2008 op->transmission_mode = TRANSMISSION_MODE_2K;
2009 break;
2010/* case FE_TER_MODE_4K:
2011 op->transmission_mode = TRANSMISSION_MODE_4K;
2012 break;*/
2013 case FE_TER_MODE_8K:
2014 op->transmission_mode = TRANSMISSION_MODE_8K;
2015 break;
2016 default:
2017 op->transmission_mode = TRANSMISSION_MODE_AUTO;
2018 }
2019
2020 op->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
2021
2022 return error;
2023}
2024
2025static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
2026{
2027 struct stv0367_state *state = fe->demodulator_priv;
2028 u32 snru32 = 0;
2029 int cpt = 0;
2030 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
2031
2032 while (cpt < 10) {
2033 usleep_range(2000, 3000);
2034 if (cut == 0x50) /*cut 1.0 cut 1.1*/
2035 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
2036 else /*cu2.0*/
2037 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
2038
2039 cpt++;
2040 }
2041
2042 snru32 /= 10;/*average on 10 values*/
2043
2044 *snr = snru32 / 1000;
2045
2046 return 0;
2047}
2048
2049#if 0
2050static int stv0367ter_status(struct dvb_frontend *fe)
2051{
2052
2053 struct stv0367_state *state = fe->demodulator_priv;
2054 struct stv0367ter_state *ter_state = state->ter_state;
2055 int locked = FALSE;
2056
2057 locked = (stv0367_readbits(state, F367TER_LK));
2058 if (!locked)
2059 ter_state->unlock_counter += 1;
2060 else
2061 ter_state->unlock_counter = 0;
2062
2063 if (ter_state->unlock_counter > 2) {
2064 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
2065 (!stv0367_readbits(state, F367TER_LK))) {
2066 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
2067 usleep_range(2000, 3000);
2068 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
2069 msleep(350);
2070 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
2071 (stv0367_readbits(state, F367TER_LK));
2072 }
2073
2074 }
2075
2076 return locked;
2077}
2078#endif
2079static int stv0367ter_read_status(struct dvb_frontend *fe, fe_status_t *status)
2080{
2081 struct stv0367_state *state = fe->demodulator_priv;
2082
2083 dprintk("%s:\n", __func__);
2084
2085 *status = 0;
2086
2087 if (stv0367_readbits(state, F367TER_LK)) {
2088 *status |= FE_HAS_LOCK;
2089 dprintk("%s: stv0367 has locked\n", __func__);
2090 }
2091
2092 return 0;
2093}
2094
2095static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
2096{
2097 struct stv0367_state *state = fe->demodulator_priv;
2098 struct stv0367ter_state *ter_state = state->ter_state;
2099 u32 Errors = 0, tber = 0, temporary = 0;
2100 int abc = 0, def = 0;
2101
2102
2103 /*wait for counting completion*/
2104 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
2105 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
2106 * (1 << 16))
2107 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
2108 * (1 << 8))
2109 + ((u32)stv0367_readbits(state,
2110 F367TER_SFEC_ERR_CNT_LO));
2111 /*measurement not completed, load previous value*/
2112 else {
2113 tber = ter_state->pBER;
2114 return 0;
2115 }
2116
2117 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
2118 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
2119
2120 if (Errors == 0) {
2121 tber = 0;
2122 } else if (abc == 0x7) {
2123 if (Errors <= 4) {
2124 temporary = (Errors * 1000000000) / (8 * (1 << 14));
2125 temporary = temporary;
2126 } else if (Errors <= 42) {
2127 temporary = (Errors * 100000000) / (8 * (1 << 14));
2128 temporary = temporary * 10;
2129 } else if (Errors <= 429) {
2130 temporary = (Errors * 10000000) / (8 * (1 << 14));
2131 temporary = temporary * 100;
2132 } else if (Errors <= 4294) {
2133 temporary = (Errors * 1000000) / (8 * (1 << 14));
2134 temporary = temporary * 1000;
2135 } else if (Errors <= 42949) {
2136 temporary = (Errors * 100000) / (8 * (1 << 14));
2137 temporary = temporary * 10000;
2138 } else if (Errors <= 429496) {
2139 temporary = (Errors * 10000) / (8 * (1 << 14));
2140 temporary = temporary * 100000;
2141 } else { /*if (Errors<4294967) 2^22 max error*/
2142 temporary = (Errors * 1000) / (8 * (1 << 14));
2143 temporary = temporary * 100000; /* still to *10 */
2144 }
2145
2146 /* Byte error*/
2147 if (def == 2)
2148 /*tber=Errors/(8*(1 <<14));*/
2149 tber = temporary;
2150 else if (def == 3)
2151 /*tber=Errors/(8*(1 <<16));*/
2152 tber = temporary / 4;
2153 else if (def == 4)
2154 /*tber=Errors/(8*(1 <<18));*/
2155 tber = temporary / 16;
2156 else if (def == 5)
2157 /*tber=Errors/(8*(1 <<20));*/
2158 tber = temporary / 64;
2159 else if (def == 6)
2160 /*tber=Errors/(8*(1 <<22));*/
2161 tber = temporary / 256;
2162 else
2163 /* should not pass here*/
2164 tber = 0;
2165
2166 if ((Errors < 4294967) && (Errors > 429496))
2167 tber *= 10;
2168
2169 }
2170
2171 /* save actual value */
2172 ter_state->pBER = tber;
2173
2174 (*ber) = tber;
2175
2176 return 0;
2177}
2178#if 0
2179static u32 stv0367ter_get_per(struct stv0367_state *state)
2180{
2181 struct stv0367ter_state *ter_state = state->ter_state;
2182 u32 Errors = 0, Per = 0, temporary = 0;
2183 int abc = 0, def = 0, cpt = 0;
2184
2185 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
2186 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
2187 usleep_range(1000, 2000);
2188 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
2189 * (1 << 16))
2190 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
2191 * (1 << 8))
2192 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
2193 cpt++;
2194 }
2195 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
2196 def = stv0367_readbits(state, F367TER_NUM_EVT1);
2197
2198 if (Errors == 0)
2199 Per = 0;
2200 else if (abc == 0x9) {
2201 if (Errors <= 4) {
2202 temporary = (Errors * 1000000000) / (8 * (1 << 8));
2203 temporary = temporary;
2204 } else if (Errors <= 42) {
2205 temporary = (Errors * 100000000) / (8 * (1 << 8));
2206 temporary = temporary * 10;
2207 } else if (Errors <= 429) {
2208 temporary = (Errors * 10000000) / (8 * (1 << 8));
2209 temporary = temporary * 100;
2210 } else if (Errors <= 4294) {
2211 temporary = (Errors * 1000000) / (8 * (1 << 8));
2212 temporary = temporary * 1000;
2213 } else if (Errors <= 42949) {
2214 temporary = (Errors * 100000) / (8 * (1 << 8));
2215 temporary = temporary * 10000;
2216 } else { /*if(Errors<=429496) 2^16 errors max*/
2217 temporary = (Errors * 10000) / (8 * (1 << 8));
2218 temporary = temporary * 100000;
2219 }
2220
2221 /* pkt error*/
2222 if (def == 2)
2223 /*Per=Errors/(1 << 8);*/
2224 Per = temporary;
2225 else if (def == 3)
2226 /*Per=Errors/(1 << 10);*/
2227 Per = temporary / 4;
2228 else if (def == 4)
2229 /*Per=Errors/(1 << 12);*/
2230 Per = temporary / 16;
2231 else if (def == 5)
2232 /*Per=Errors/(1 << 14);*/
2233 Per = temporary / 64;
2234 else if (def == 6)
2235 /*Per=Errors/(1 << 16);*/
2236 Per = temporary / 256;
2237 else
2238 Per = 0;
2239
2240 }
2241 /* save actual value */
2242 ter_state->pPER = Per;
2243
2244 return Per;
2245}
2246#endif
2247static int stv0367_get_tune_settings(struct dvb_frontend *fe,
2248 struct dvb_frontend_tune_settings
2249 *fe_tune_settings)
2250{
2251 fe_tune_settings->min_delay_ms = 1000;
2252 fe_tune_settings->step_size = 0;
2253 fe_tune_settings->max_drift = 0;
2254
2255 return 0;
2256}
2257
2258static void stv0367_release(struct dvb_frontend *fe)
2259{
2260 struct stv0367_state *state = fe->demodulator_priv;
2261
2262 kfree(state->ter_state);
2263 kfree(state->cab_state);
2264 kfree(state);
2265}
2266
2267static struct dvb_frontend_ops stv0367ter_ops = {
2268 .info = {
2269 .name = "ST STV0367 DVB-T",
2270 .type = FE_OFDM,
2271 .frequency_min = 47000000,
2272 .frequency_max = 862000000,
2273 .frequency_stepsize = 15625,
2274 .frequency_tolerance = 0,
2275 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2276 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2277 FE_CAN_FEC_AUTO |
2278 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2279 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
2280 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
2281 FE_CAN_INVERSION_AUTO |
2282 FE_CAN_MUTE_TS
2283 },
2284 .release = stv0367_release,
2285 .init = stv0367ter_init,
2286 .sleep = stv0367ter_sleep,
2287 .i2c_gate_ctrl = stv0367ter_gate_ctrl,
2288 .set_frontend = stv0367ter_set_frontend,
2289 .get_frontend = stv0367ter_get_frontend,
2290 .get_tune_settings = stv0367_get_tune_settings,
2291 .read_status = stv0367ter_read_status,
2292 .read_ber = stv0367ter_read_ber,/* too slow */
2293/* .read_signal_strength = stv0367_read_signal_strength,*/
2294 .read_snr = stv0367ter_read_snr,
2295 .read_ucblocks = stv0367ter_read_ucblocks,
2296};
2297
2298struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
2299 struct i2c_adapter *i2c)
2300{
2301 struct stv0367_state *state = NULL;
2302 struct stv0367ter_state *ter_state = NULL;
2303
2304 /* allocate memory for the internal state */
2305 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2306 if (state == NULL)
2307 goto error;
2308 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
2309 if (ter_state == NULL)
2310 goto error;
2311
2312 /* setup the state */
2313 state->i2c = i2c;
2314 state->config = config;
2315 state->ter_state = ter_state;
2316 state->fe.ops = stv0367ter_ops;
2317 state->fe.demodulator_priv = state;
2318 state->chip_id = stv0367_readreg(state, 0xf000);
2319
2320 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2321
2322 /* check if the demod is there */
2323 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2324 goto error;
2325
2326 return &state->fe;
2327
2328error:
2329 kfree(ter_state);
2330 kfree(state);
2331 return NULL;
2332}
2333EXPORT_SYMBOL(stv0367ter_attach);
2334
2335static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
2336{
2337 struct stv0367_state *state = fe->demodulator_priv;
2338
2339 dprintk("%s:\n", __func__);
2340
2341 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
2342
2343 return 0;
2344}
2345
2346static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
2347{
2348 struct stv0367_state *state = fe->demodulator_priv;
2349 u32 mclk_Hz = 0;/* master clock frequency (Hz) */
2350 u32 M, N, P;
2351
2352
2353 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
2354 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
2355 if (N == 0)
2356 N = N + 1;
2357
2358 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
2359 if (M == 0)
2360 M = M + 1;
2361
2362 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
2363
2364 if (P > 5)
2365 P = 5;
2366
2367 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
2368 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
2369 mclk_Hz);
2370 } else
2371 mclk_Hz = ExtClk_Hz;
2372
2373 dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
2374
2375 return mclk_Hz;
2376}
2377
2378static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
2379{
2380 u32 ADCClk_Hz = ExtClk_Hz;
2381
2382 ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
2383
2384 return ADCClk_Hz;
2385}
2386
2387enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
2388 u32 SymbolRate,
2389 enum stv0367cab_mod QAMSize)
2390{
2391 /* Set QAM size */
2392 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
2393
2394 /* Set Registers settings specific to the QAM size */
2395 switch (QAMSize) {
2396 case FE_CAB_MOD_QAM4:
2397 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2398 break;
2399 case FE_CAB_MOD_QAM16:
2400 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
2401 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2402 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2403 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2404 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2405 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2406 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2407 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
2408 break;
2409 case FE_CAB_MOD_QAM32:
2410 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2411 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
2412 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2413 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2414 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
2415 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
2416 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2417 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2418 break;
2419 case FE_CAB_MOD_QAM64:
2420 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
2421 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2422 if (SymbolRate > 45000000) {
2423 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
2424 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2425 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
2426 } else if (SymbolRate > 25000000) {
2427 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2428 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2429 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2430 } else {
2431 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2432 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2433 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2434 }
2435 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
2436 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2437 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
2438 break;
2439 case FE_CAB_MOD_QAM128:
2440 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2441 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
2442 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
2443 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
2444 if (SymbolRate > 45000000)
2445 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2446 else if (SymbolRate > 25000000)
2447 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
2448 else
2449 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
2450
2451 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
2452 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
2453 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2454 break;
2455 case FE_CAB_MOD_QAM256:
2456 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
2457 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
2458 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
2459 if (SymbolRate > 45000000)
2460 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2461 else if (SymbolRate > 25000000)
2462 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
2463 else
2464 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
2465
2466 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
2467 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
2468 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
2469 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
2470 break;
2471 case FE_CAB_MOD_QAM512:
2472 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2473 break;
2474 case FE_CAB_MOD_QAM1024:
2475 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
2476 break;
2477 default:
2478 break;
2479 }
2480
2481 return QAMSize;
2482}
2483
2484static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
2485 u32 adc_hz, s32 derot_hz)
2486{
2487 u32 sampled_if = 0;
2488 u32 adc_khz;
2489
2490 adc_khz = adc_hz / 1000;
2491
2492 dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
2493
2494 if (adc_khz != 0) {
2495 if (derot_hz < 1000000)
2496 derot_hz = adc_hz / 4; /* ZIF operation */
2497 if (derot_hz > adc_hz)
2498 derot_hz = derot_hz - adc_hz;
2499 sampled_if = (u32)derot_hz / 1000;
2500 sampled_if *= 32768;
2501 sampled_if /= adc_khz;
2502 sampled_if *= 256;
2503 }
2504
2505 if (sampled_if > 8388607)
2506 sampled_if = 8388607;
2507
2508 dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
2509
2510 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
2511 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
2512 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
2513
2514 return derot_hz;
2515}
2516
2517static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
2518{
2519 u32 sampled_if;
2520
2521 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
2522 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
2523 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
2524
2525 sampled_if /= 256;
2526 sampled_if *= (adc_hz / 1000);
2527 sampled_if += 1;
2528 sampled_if /= 32768;
2529
2530 return sampled_if;
2531}
2532
2533static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
2534 u32 mclk_hz, u32 SymbolRate,
2535 enum stv0367cab_mod QAMSize)
2536{
2537 u32 QamSizeCorr = 0;
2538 u32 u32_tmp = 0, u32_tmp1 = 0;
2539 u32 adp_khz;
2540
2541 dprintk("%s:\n", __func__);
2542
2543 /* Set Correction factor of SRC gain */
2544 switch (QAMSize) {
2545 case FE_CAB_MOD_QAM4:
2546 QamSizeCorr = 1110;
2547 break;
2548 case FE_CAB_MOD_QAM16:
2549 QamSizeCorr = 1032;
2550 break;
2551 case FE_CAB_MOD_QAM32:
2552 QamSizeCorr = 954;
2553 break;
2554 case FE_CAB_MOD_QAM64:
2555 QamSizeCorr = 983;
2556 break;
2557 case FE_CAB_MOD_QAM128:
2558 QamSizeCorr = 957;
2559 break;
2560 case FE_CAB_MOD_QAM256:
2561 QamSizeCorr = 948;
2562 break;
2563 case FE_CAB_MOD_QAM512:
2564 QamSizeCorr = 0;
2565 break;
2566 case FE_CAB_MOD_QAM1024:
2567 QamSizeCorr = 944;
2568 break;
2569 default:
2570 break;
2571 }
2572
2573 /* Transfer ratio calculation */
2574 if (adc_hz != 0) {
2575 u32_tmp = 256 * SymbolRate;
2576 u32_tmp = u32_tmp / adc_hz;
2577 }
2578 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2579
2580 /* Symbol rate and SRC gain calculation */
2581 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2582 if (adp_khz != 0) {
2583 u32_tmp = SymbolRate;
2584 u32_tmp1 = SymbolRate;
2585
2586 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2587 /* Symbol rate calculation */
2588 u32_tmp *= 2048; /* 2048 = 2^11 */
2589 u32_tmp = u32_tmp / adp_khz;
2590 u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2591 u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2592 u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2593
2594 /* SRC Gain Calculation */
2595 u32_tmp1 *= 2048; /* *2*2^10 */
2596 u32_tmp1 /= 439; /* *2/878 */
2597 u32_tmp1 *= 256; /* *2^8 */
2598 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2599 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2600 u32_tmp1 = u32_tmp1 / 10000000;
2601
2602 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2603 /* Symbol rate calculation */
2604 u32_tmp *= 1024 ; /* 1024 = 2**10 */
2605 u32_tmp = u32_tmp / adp_khz;
2606 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2607 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2608 u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2609
2610 /* SRC Gain Calculation */
2611 u32_tmp1 *= 1024; /* *2*2^9 */
2612 u32_tmp1 /= 439; /* *2/878 */
2613 u32_tmp1 *= 256; /* *2^8 */
2614 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2615 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2616 u32_tmp1 = u32_tmp1 / 5000000;
2617 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2618 /* Symbol rate calculation */
2619 u32_tmp *= 512 ; /* 512 = 2**9 */
2620 u32_tmp = u32_tmp / adp_khz;
2621 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2622 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2623 u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2624
2625 /* SRC Gain Calculation */
2626 u32_tmp1 *= 512; /* *2*2^8 */
2627 u32_tmp1 /= 439; /* *2/878 */
2628 u32_tmp1 *= 256; /* *2^8 */
2629 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2630 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2631 u32_tmp1 = u32_tmp1 / 2500000;
2632 } else {
2633 /* Symbol rate calculation */
2634 u32_tmp *= 256 ; /* 256 = 2**8 */
2635 u32_tmp = u32_tmp / adp_khz;
2636 u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2637 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2638 u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2639
2640 /* SRC Gain Calculation */
2641 u32_tmp1 *= 256; /* 2*2^7 */
2642 u32_tmp1 /= 439; /* *2/878 */
2643 u32_tmp1 *= 256; /* *2^8 */
2644 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2645 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2646 u32_tmp1 = u32_tmp1 / 1250000;
2647 }
2648 }
2649#if 0
2650 /* Filters' coefficients are calculated and written
2651 into registers only if the filters are enabled */
2652 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2653 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2654 SymbolRate);
2655 /* AllPass filter must be enabled
2656 when the adjacents filter is used */
2657 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2658 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2659 } else
2660 /* AllPass filter must be disabled
2661 when the adjacents filter is not used */
2662#endif
2663 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2664
2665 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2666 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2667 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2668 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2669
2670 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2671 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2672
2673 return SymbolRate ;
2674}
2675
2676static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2677{
2678 u32 regsym;
2679 u32 adp_khz;
2680
2681 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2682 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2683 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2684 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2685
2686 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2687
2688 if (regsym < 134217728) { /* 134217728L = 2**27*/
2689 regsym = regsym * 32; /* 32 = 2**5 */
2690 regsym = regsym / 32768; /* 32768L = 2**15 */
2691 regsym = adp_khz * regsym; /* AdpClk in kHz */
2692 regsym = regsym / 128; /* 128 = 2**7 */
2693 regsym *= 125 ; /* 125 = 1000/2**3 */
2694 regsym /= 2048 ; /* 2048 = 2**11 */
2695 } else if (regsym < 268435456) { /* 268435456L = 2**28 */
2696 regsym = regsym * 16; /* 16 = 2**4 */
2697 regsym = regsym / 32768; /* 32768L = 2**15 */
2698 regsym = adp_khz * regsym; /* AdpClk in kHz */
2699 regsym = regsym / 128; /* 128 = 2**7 */
2700 regsym *= 125 ; /* 125 = 1000/2**3*/
2701 regsym /= 1024 ; /* 256 = 2**10*/
2702 } else if (regsym < 536870912) { /* 536870912L = 2**29*/
2703 regsym = regsym * 8; /* 8 = 2**3 */
2704 regsym = regsym / 32768; /* 32768L = 2**15 */
2705 regsym = adp_khz * regsym; /* AdpClk in kHz */
2706 regsym = regsym / 128; /* 128 = 2**7 */
2707 regsym *= 125 ; /* 125 = 1000/2**3 */
2708 regsym /= 512 ; /* 128 = 2**9 */
2709 } else {
2710 regsym = regsym * 4; /* 4 = 2**2 */
2711 regsym = regsym / 32768; /* 32768L = 2**15 */
2712 regsym = adp_khz * regsym; /* AdpClk in kHz */
2713 regsym = regsym / 128; /* 128 = 2**7 */
2714 regsym *= 125 ; /* 125 = 1000/2**3 */
2715 regsym /= 256 ; /* 64 = 2**8 */
2716 }
2717
2718 return regsym;
2719}
2720
2721static int stv0367cab_read_status(struct dvb_frontend *fe, fe_status_t *status)
2722{
2723 struct stv0367_state *state = fe->demodulator_priv;
2724
2725 dprintk("%s:\n", __func__);
2726
2727 *status = 0;
2728
2729 if (stv0367_readbits(state, F367CAB_QAMFEC_LOCK)) {
2730 *status |= FE_HAS_LOCK;
2731 dprintk("%s: stv0367 has locked\n", __func__);
2732 }
2733
2734 return 0;
2735}
2736
2737static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2738{
2739 struct stv0367_state *state = fe->demodulator_priv;
2740
2741 dprintk("%s:\n", __func__);
2742
2743 if (standby_on) {
2744 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2745 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2746 stv0367_writebits(state, F367CAB_STDBY, 1);
2747 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2748 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2749 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2750 stv0367_writebits(state, F367CAB_POFFQ, 1);
2751 stv0367_writebits(state, F367CAB_POFFI, 1);
2752 } else {
2753 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2754 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2755 stv0367_writebits(state, F367CAB_STDBY, 0);
2756 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2757 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2758 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2759 stv0367_writebits(state, F367CAB_POFFQ, 0);
2760 stv0367_writebits(state, F367CAB_POFFI, 0);
2761 }
2762
2763 return 0;
2764}
2765
2766static int stv0367cab_sleep(struct dvb_frontend *fe)
2767{
2768 return stv0367cab_standby(fe, 1);
2769}
2770
2771int stv0367cab_init(struct dvb_frontend *fe)
2772{
2773 struct stv0367_state *state = fe->demodulator_priv;
2774 struct stv0367cab_state *cab_state = state->cab_state;
2775 int i;
2776
2777 dprintk("%s:\n", __func__);
2778
2779 for (i = 0; i < STV0367CAB_NBREGS; i++)
2780 stv0367_writereg(state, def0367cab[i].addr,
2781 def0367cab[i].value);
2782
2783 switch (state->config->ts_mode) {
2784 case STV0367_DVBCI_CLOCK:
2785 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2786 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2787 break;
2788 case STV0367_SERIAL_PUNCT_CLOCK:
2789 case STV0367_SERIAL_CONT_CLOCK:
2790 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2791 break;
2792 case STV0367_PARALLEL_PUNCT_CLOCK:
2793 case STV0367_OUTPUTMODE_DEFAULT:
2794 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2795 break;
2796 }
2797
2798 switch (state->config->clk_pol) {
2799 case STV0367_RISINGEDGE_CLOCK:
2800 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2801 break;
2802 case STV0367_FALLINGEDGE_CLOCK:
2803 case STV0367_CLOCKPOLARITY_DEFAULT:
2804 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2805 break;
2806 }
2807
2808 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2809
2810 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2811
2812 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2813
2814 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2815
2816 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2817
2818 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2819 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2820
2821 return 0;
2822}
2823static
2824enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2825 struct dvb_frontend_parameters *param)
2826{
2827 struct dvb_qam_parameters *op = &param->u.qam;
2828 struct stv0367cab_state *cab_state = state->cab_state;
2829 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2830 u32 QAMFEC_Lock, QAM_Lock, u32_tmp,
2831 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2832 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2833 u8 TrackAGCAccum;
2834 s32 tmp;
2835
2836 dprintk("%s:\n", __func__);
2837
2838 /* Timeouts calculation */
2839 /* A max lock time of 25 ms is allowed for delayed AGC */
2840 AGCTimeOut = 25;
2841 /* 100000 symbols needed by the TRL as a maximum value */
2842 TRLTimeOut = 100000000 / op->symbol_rate;
2843 /* CRLSymbols is the needed number of symbols to achieve a lock
2844 within [-4%, +4%] of the symbol rate.
2845 CRL timeout is calculated
2846 for a lock within [-search_range, +search_range].
2847 EQL timeout can be changed depending on
2848 the micro-reflections we want to handle.
2849 A characterization must be performed
2850 with these echoes to get new timeout values.
2851 */
2852 switch (op->modulation) {
2853 case QAM_16:
2854 CRLSymbols = 150000;
2855 EQLTimeOut = 100;
2856 break;
2857 case QAM_32:
2858 CRLSymbols = 250000;
2859 EQLTimeOut = 100;
2860 break;
2861 case QAM_64:
2862 CRLSymbols = 200000;
2863 EQLTimeOut = 100;
2864 break;
2865 case QAM_128:
2866 CRLSymbols = 250000;
2867 EQLTimeOut = 100;
2868 break;
2869 case QAM_256:
2870 CRLSymbols = 250000;
2871 EQLTimeOut = 100;
2872 break;
2873 default:
2874 CRLSymbols = 200000;
2875 EQLTimeOut = 100;
2876 break;
2877 }
2878#if 0
2879 if (pIntParams->search_range < 0) {
2880 CRLTimeOut = (25 * CRLSymbols *
2881 (-pIntParams->search_range / 1000)) /
2882 (pIntParams->symbol_rate / 1000);
2883 } else
2884#endif
2885 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2886 (op->symbol_rate / 1000);
2887
2888 CRLTimeOut = (1000 * CRLTimeOut) / op->symbol_rate;
2889 /* Timeouts below 50ms are coerced */
2890 if (CRLTimeOut < 50)
2891 CRLTimeOut = 50;
2892 /* A maximum of 100 TS packets is needed to get FEC lock even in case
2893 the spectrum inversion needs to be changed.
2894 This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2895 */
2896 FECTimeOut = 20;
2897 DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2898
2899 dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2900
2901 /* Reset the TRL to ensure nothing starts until the
2902 AGC is stable which ensures a better lock time
2903 */
2904 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2905 /* Set AGC accumulation time to minimum and lock threshold to maximum
2906 in order to speed up the AGC lock */
2907 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2908 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2909 /* Modulus Mapper is disabled */
2910 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2911 /* Disable the sweep function */
2912 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2913 /* The sweep function is never used, Sweep rate must be set to 0 */
2914 /* Set the derotator frequency in Hz */
2915 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2916 (1000 * (s32)state->config->if_khz + cab_state->derot_offset));
2917 /* Disable the Allpass Filter when the symbol rate is out of range */
2918 if ((op->symbol_rate > 10800000) | (op->symbol_rate < 1800000)) {
2919 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2920 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2921 }
2922#if 0
2923 /* Check if the tuner is locked */
2924 tuner_lock = stv0367cab_tuner_get_status(fe);
2925 if (tuner_lock == 0)
2926 return FE_367CAB_NOTUNER;
2927#endif
2928 /* Relase the TRL to start demodulator acquisition */
2929 /* Wait for QAM lock */
2930 LockTime = 0;
2931 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2932 do {
2933 QAM_Lock = stv0367_readbits(state, F367CAB_FSM_STATUS);
2934 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2935 (QAM_Lock == 0x04))
2936 /*
2937 * We don't wait longer, the frequency/phase offset
2938 * must be too big
2939 */
2940 LockTime = DemodTimeOut;
2941 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2942 (QAM_Lock == 0x02))
2943 /*
2944 * We don't wait longer, either there is no signal or
2945 * it is not the right symbol rate or it is an analog
2946 * carrier
2947 */
2948 {
2949 LockTime = DemodTimeOut;
2950 u32_tmp = stv0367_readbits(state,
2951 F367CAB_AGC_PWR_WORD_LO) +
2952 (stv0367_readbits(state,
2953 F367CAB_AGC_PWR_WORD_ME) << 8) +
2954 (stv0367_readbits(state,
2955 F367CAB_AGC_PWR_WORD_HI) << 16);
2956 if (u32_tmp >= 131072)
2957 u32_tmp = 262144 - u32_tmp;
2958 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2959 F367CAB_AGC_IF_BWSEL)));
2960
2961 if (u32_tmp < stv0367_readbits(state,
2962 F367CAB_AGC_PWRREF_LO) +
2963 256 * stv0367_readbits(state,
2964 F367CAB_AGC_PWRREF_HI) - 10)
2965 QAM_Lock = 0x0f;
2966 } else {
2967 usleep_range(10000, 20000);
2968 LockTime += 10;
2969 }
2970 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2971 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2972
2973 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2974
2975 } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2976 (LockTime < DemodTimeOut));
2977
2978 dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2979
2980 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2981 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2982 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2983 dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2984
2985 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2986 dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2987
2988 if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2989 /* Wait for FEC lock */
2990 LockTime = 0;
2991 do {
2992 usleep_range(5000, 7000);
2993 LockTime += 5;
2994 QAMFEC_Lock = stv0367_readbits(state,
2995 F367CAB_QAMFEC_LOCK);
2996 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2997 } else
2998 QAMFEC_Lock = 0;
2999
3000 if (QAMFEC_Lock) {
3001 signalType = FE_CAB_DATAOK;
3002 cab_state->modulation = op->modulation;
3003 cab_state->spect_inv = stv0367_readbits(state,
3004 F367CAB_QUAD_INV);
3005#if 0
3006/* not clear for me */
3007 if (state->config->if_khz != 0) {
3008 if (state->config->if_khz > cab_state->adc_clk / 1000) {
3009 cab_state->freq_khz =
3010 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3011 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3012 - cab_state->adc_clk / 1000 + state->config->if_khz;
3013 } else {
3014 cab_state->freq_khz =
3015 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
3016 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3017 + state->config->if_khz;
3018 }
3019 } else {
3020 cab_state->freq_khz =
3021 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
3022 stv0367cab_get_derot_freq(state,
3023 cab_state->adc_clk) -
3024 cab_state->adc_clk / 4000;
3025 }
3026#endif
3027 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
3028 cab_state->mclk);
3029 cab_state->locked = 1;
3030
3031 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
3032 } else {
3033 switch (QAM_Lock) {
3034 case 1:
3035 signalType = FE_CAB_NOAGC;
3036 break;
3037 case 2:
3038 signalType = FE_CAB_NOTIMING;
3039 break;
3040 case 3:
3041 signalType = FE_CAB_TIMINGOK;
3042 break;
3043 case 4:
3044 signalType = FE_CAB_NOCARRIER;
3045 break;
3046 case 5:
3047 signalType = FE_CAB_CARRIEROK;
3048 break;
3049 case 7:
3050 signalType = FE_CAB_NOBLIND;
3051 break;
3052 case 8:
3053 signalType = FE_CAB_BLINDOK;
3054 break;
3055 case 10:
3056 signalType = FE_CAB_NODEMOD;
3057 break;
3058 case 11:
3059 signalType = FE_CAB_DEMODOK;
3060 break;
3061 case 12:
3062 signalType = FE_CAB_DEMODOK;
3063 break;
3064 case 13:
3065 signalType = FE_CAB_NODEMOD;
3066 break;
3067 case 14:
3068 signalType = FE_CAB_NOBLIND;
3069 break;
3070 case 15:
3071 signalType = FE_CAB_NOSIGNAL;
3072 break;
3073 default:
3074 break;
3075 }
3076
3077 }
3078
3079 /* Set the AGC control values to tracking values */
3080 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
3081 return signalType;
3082}
3083
3084static int stv0367cab_set_frontend(struct dvb_frontend *fe,
3085 struct dvb_frontend_parameters *param)
3086{
3087 struct stv0367_state *state = fe->demodulator_priv;
3088 struct stv0367cab_state *cab_state = state->cab_state;
3089 struct dvb_qam_parameters *op = &param->u.qam;
3090 enum stv0367cab_mod QAMSize = 0;
3091
3092 dprintk("%s: freq = %d, srate = %d\n", __func__,
3093 param->frequency, op->symbol_rate);
3094
3095 cab_state->derot_offset = 0;
3096
3097 switch (op->modulation) {
3098 case QAM_16:
3099 QAMSize = FE_CAB_MOD_QAM16;
3100 break;
3101 case QAM_32:
3102 QAMSize = FE_CAB_MOD_QAM32;
3103 break;
3104 case QAM_64:
3105 QAMSize = FE_CAB_MOD_QAM64;
3106 break;
3107 case QAM_128:
3108 QAMSize = FE_CAB_MOD_QAM128;
3109 break;
3110 case QAM_256:
3111 QAMSize = FE_CAB_MOD_QAM256;
3112 break;
3113 default:
3114 break;
3115 }
3116
3117 stv0367cab_init(fe);
3118
3119 /* Tuner Frequency Setting */
3120 if (fe->ops.tuner_ops.set_params) {
3121 if (fe->ops.i2c_gate_ctrl)
3122 fe->ops.i2c_gate_ctrl(fe, 1);
3123 fe->ops.tuner_ops.set_params(fe, param);
3124 if (fe->ops.i2c_gate_ctrl)
3125 fe->ops.i2c_gate_ctrl(fe, 0);
3126 }
3127
3128 stv0367cab_SetQamSize(
3129 state,
3130 op->symbol_rate,
3131 QAMSize);
3132
3133 stv0367cab_set_srate(state,
3134 cab_state->adc_clk,
3135 cab_state->mclk,
3136 op->symbol_rate,
3137 QAMSize);
3138 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
3139 cab_state->state = stv0367cab_algo(state, param);
3140 return 0;
3141}
3142
3143static int stv0367cab_get_frontend(struct dvb_frontend *fe,
3144 struct dvb_frontend_parameters *param)
3145{
3146 struct stv0367_state *state = fe->demodulator_priv;
3147 struct stv0367cab_state *cab_state = state->cab_state;
3148 struct dvb_qam_parameters *op = &param->u.qam;
3149
3150 enum stv0367cab_mod QAMSize;
3151
3152 dprintk("%s:\n", __func__);
3153
3154 op->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
3155
3156 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3157 switch (QAMSize) {
3158 case FE_CAB_MOD_QAM16:
3159 op->modulation = QAM_16;
3160 break;
3161 case FE_CAB_MOD_QAM32:
3162 op->modulation = QAM_32;
3163 break;
3164 case FE_CAB_MOD_QAM64:
3165 op->modulation = QAM_64;
3166 break;
3167 case FE_CAB_MOD_QAM128:
3168 op->modulation = QAM_128;
3169 break;
3170 case QAM_256:
3171 op->modulation = QAM_256;
3172 break;
3173 default:
3174 break;
3175 }
3176
3177 param->frequency = stv0367_get_tuner_freq(fe);
3178
3179 dprintk("%s: tuner frequency = %d\n", __func__, param->frequency);
3180
3181 if (state->config->if_khz == 0) {
3182 param->frequency +=
3183 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
3184 cab_state->adc_clk / 4000);
3185 return 0;
3186 }
3187
3188 if (state->config->if_khz > cab_state->adc_clk / 1000)
3189 param->frequency += (state->config->if_khz
3190 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
3191 - cab_state->adc_clk / 1000);
3192 else
3193 param->frequency += (state->config->if_khz
3194 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
3195
3196 return 0;
3197}
3198
3199#if 0
3200void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
3201 u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
3202{
3203 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
3204 stv0367cab_GetPacketsCount(state, Monitor_results);
3205
3206 return;
3207}
3208
3209static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
3210{
3211 struct stv0367_state *state = fe->demodulator_priv;
3212
3213 return 0;
3214}
3215#endif
3216static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
3217{
3218 s32 rfLevel = 0;
3219 s32 RfAgcPwm = 0, IfAgcPwm = 0;
3220 u8 i;
3221
3222 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
3223
3224 RfAgcPwm =
3225 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
3226 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
3227 RfAgcPwm = 100 * RfAgcPwm / 1023;
3228
3229 IfAgcPwm =
3230 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
3231 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
3232 if (IfAgcPwm >= 2048)
3233 IfAgcPwm -= 2048;
3234 else
3235 IfAgcPwm += 2048;
3236
3237 IfAgcPwm = 100 * IfAgcPwm / 4095;
3238
3239 /* For DTT75467 on NIM */
3240 if (RfAgcPwm < 90 && IfAgcPwm < 28) {
3241 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
3242 if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
3243 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
3244 break;
3245 }
3246 }
3247 if (i == RF_LOOKUP_TABLE_SIZE)
3248 rfLevel = -56;
3249 } else { /*if IF AGC>10*/
3250 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
3251 if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
3252 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
3253 break;
3254 }
3255 }
3256 if (i == RF_LOOKUP_TABLE2_SIZE)
3257 rfLevel = -72;
3258 }
3259 return rfLevel;
3260}
3261
3262static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
3263{
3264 struct stv0367_state *state = fe->demodulator_priv;
3265
3266 s32 signal = stv0367cab_get_rf_lvl(state);
3267
3268 dprintk("%s: signal=%d dBm\n", __func__, signal);
3269
3270 if (signal <= -72)
3271 *strength = 65535;
3272 else
3273 *strength = (22 + signal) * (-1311);
3274
3275 dprintk("%s: strength=%d\n", __func__, (*strength));
3276
3277 return 0;
3278}
3279
3280static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
3281{
3282 struct stv0367_state *state = fe->demodulator_priv;
3283 u32 noisepercentage;
3284 enum stv0367cab_mod QAMSize;
3285 u32 regval = 0, temp = 0;
3286 int power, i;
3287
3288 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
3289 switch (QAMSize) {
3290 case FE_CAB_MOD_QAM4:
3291 power = 21904;
3292 break;
3293 case FE_CAB_MOD_QAM16:
3294 power = 20480;
3295 break;
3296 case FE_CAB_MOD_QAM32:
3297 power = 23040;
3298 break;
3299 case FE_CAB_MOD_QAM64:
3300 power = 21504;
3301 break;
3302 case FE_CAB_MOD_QAM128:
3303 power = 23616;
3304 break;
3305 case FE_CAB_MOD_QAM256:
3306 power = 21760;
3307 break;
3308 case FE_CAB_MOD_QAM512:
3309 power = 1;
3310 break;
3311 case FE_CAB_MOD_QAM1024:
3312 power = 21280;
3313 break;
3314 default:
3315 power = 1;
3316 break;
3317 }
3318
3319 for (i = 0; i < 10; i++) {
3320 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
3321 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
3322 }
3323
3324 regval /= 10; /*for average over 10 times in for loop above*/
3325 if (regval != 0) {
3326 temp = power
3327 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
3328 temp /= regval;
3329 }
3330
3331 /* table values, not needed to calculate logarithms */
3332 if (temp >= 5012)
3333 noisepercentage = 100;
3334 else if (temp >= 3981)
3335 noisepercentage = 93;
3336 else if (temp >= 3162)
3337 noisepercentage = 86;
3338 else if (temp >= 2512)
3339 noisepercentage = 79;
3340 else if (temp >= 1995)
3341 noisepercentage = 72;
3342 else if (temp >= 1585)
3343 noisepercentage = 65;
3344 else if (temp >= 1259)
3345 noisepercentage = 58;
3346 else if (temp >= 1000)
3347 noisepercentage = 50;
3348 else if (temp >= 794)
3349 noisepercentage = 43;
3350 else if (temp >= 501)
3351 noisepercentage = 36;
3352 else if (temp >= 316)
3353 noisepercentage = 29;
3354 else if (temp >= 200)
3355 noisepercentage = 22;
3356 else if (temp >= 158)
3357 noisepercentage = 14;
3358 else if (temp >= 126)
3359 noisepercentage = 7;
3360 else
3361 noisepercentage = 0;
3362
3363 dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
3364
3365 *snr = (noisepercentage * 65535) / 100;
3366
3367 return 0;
3368}
3369
3370static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
3371{
3372 struct stv0367_state *state = fe->demodulator_priv;
3373 int corrected, tscount;
3374
3375 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
3376 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
3377 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
3378 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
3379 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
3380 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
3381
3382 dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
3383 __func__, *ucblocks, corrected, tscount);
3384
3385 return 0;
3386};
3387
3388static struct dvb_frontend_ops stv0367cab_ops = {
3389 .info = {
3390 .name = "ST STV0367 DVB-C",
3391 .type = FE_QAM,
3392 .frequency_min = 47000000,
3393 .frequency_max = 862000000,
3394 .frequency_stepsize = 62500,
3395 .symbol_rate_min = 870000,
3396 .symbol_rate_max = 11700000,
3397 .caps = 0x400 |/* FE_CAN_QAM_4 */
3398 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
3399 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3400 FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
3401 },
3402 .release = stv0367_release,
3403 .init = stv0367cab_init,
3404 .sleep = stv0367cab_sleep,
3405 .i2c_gate_ctrl = stv0367cab_gate_ctrl,
3406 .set_frontend = stv0367cab_set_frontend,
3407 .get_frontend = stv0367cab_get_frontend,
3408 .read_status = stv0367cab_read_status,
3409/* .read_ber = stv0367cab_read_ber, */
3410 .read_signal_strength = stv0367cab_read_strength,
3411 .read_snr = stv0367cab_read_snr,
3412 .read_ucblocks = stv0367cab_read_ucblcks,
3413 .get_tune_settings = stv0367_get_tune_settings,
3414};
3415
3416struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
3417 struct i2c_adapter *i2c)
3418{
3419 struct stv0367_state *state = NULL;
3420 struct stv0367cab_state *cab_state = NULL;
3421
3422 /* allocate memory for the internal state */
3423 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3424 if (state == NULL)
3425 goto error;
3426 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3427 if (cab_state == NULL)
3428 goto error;
3429
3430 /* setup the state */
3431 state->i2c = i2c;
3432 state->config = config;
3433 cab_state->search_range = 280000;
3434 state->cab_state = cab_state;
3435 state->fe.ops = stv0367cab_ops;
3436 state->fe.demodulator_priv = state;
3437 state->chip_id = stv0367_readreg(state, 0xf000);
3438
3439 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3440
3441 /* check if the demod is there */
3442 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3443 goto error;
3444
3445 return &state->fe;
3446
3447error:
3448 kfree(cab_state);
3449 kfree(state);
3450 return NULL;
3451}
3452EXPORT_SYMBOL(stv0367cab_attach);
3453
3454MODULE_PARM_DESC(debug, "Set debug");
3455MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3456
3457MODULE_AUTHOR("Igor M. Liplianin");
3458MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3459MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stv0367.h b/drivers/media/dvb/frontends/stv0367.h
new file mode 100644
index 000000000000..93cc4a57eea0
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv0367.h
@@ -0,0 +1,66 @@
1/*
2 * stv0367.h
3 *
4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#ifndef STV0367_H
27#define STV0367_H
28
29#include <linux/dvb/frontend.h>
30#include "dvb_frontend.h"
31
32struct stv0367_config {
33 u8 demod_address;
34 u32 xtal;
35 u32 if_khz;/*4500*/
36 int if_iq_mode;
37 int ts_mode;
38 int clk_pol;
39};
40
41#if defined(CONFIG_DVB_STV0367) || (defined(CONFIG_DVB_STV0367_MODULE) \
42 && defined(MODULE))
43extern struct
44dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
45 struct i2c_adapter *i2c);
46extern struct
47dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
48 struct i2c_adapter *i2c);
49#else
50static inline struct
51dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
52 struct i2c_adapter *i2c)
53{
54 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
55 return NULL;
56}
57static inline struct
58dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
59 struct i2c_adapter *i2c)
60{
61 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
62 return NULL;
63}
64#endif
65
66#endif
diff --git a/drivers/media/dvb/frontends/stv0367_priv.h b/drivers/media/dvb/frontends/stv0367_priv.h
new file mode 100644
index 000000000000..995db0689ddd
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv0367_priv.h
@@ -0,0 +1,212 @@
1/*
2 * stv0367_priv.h
3 *
4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25/* Common driver error constants */
26
27#ifndef STV0367_PRIV_H
28#define STV0367_PRIV_H
29
30#ifndef TRUE
31 #define TRUE (1 == 1)
32#endif
33#ifndef FALSE
34 #define FALSE (!TRUE)
35#endif
36
37#ifndef NULL
38#define NULL 0
39#endif
40
41/* MACRO definitions */
42#define ABS(X) ((X) < 0 ? (-1 * (X)) : (X))
43#define MAX(X, Y) ((X) >= (Y) ? (X) : (Y))
44#define MIN(X, Y) ((X) <= (Y) ? (X) : (Y))
45#define INRANGE(X, Y, Z) \
46 ((((X) <= (Y)) && ((Y) <= (Z))) || \
47 (((Z) <= (Y)) && ((Y) <= (X))) ? 1 : 0)
48
49#ifndef MAKEWORD
50#define MAKEWORD(X, Y) (((X) << 8) + (Y))
51#endif
52
53#define LSB(X) (((X) & 0xff))
54#define MSB(Y) (((Y) >> 8) & 0xff)
55#define MMSB(Y)(((Y) >> 16) & 0xff)
56
57enum stv0367_ter_signal_type {
58 FE_TER_NOAGC = 0,
59 FE_TER_AGCOK = 5,
60 FE_TER_NOTPS = 6,
61 FE_TER_TPSOK = 7,
62 FE_TER_NOSYMBOL = 8,
63 FE_TER_BAD_CPQ = 9,
64 FE_TER_PRFOUNDOK = 10,
65 FE_TER_NOPRFOUND = 11,
66 FE_TER_LOCKOK = 12,
67 FE_TER_NOLOCK = 13,
68 FE_TER_SYMBOLOK = 15,
69 FE_TER_CPAMPOK = 16,
70 FE_TER_NOCPAMP = 17,
71 FE_TER_SWNOK = 18
72};
73
74enum stv0367_ts_mode {
75 STV0367_OUTPUTMODE_DEFAULT,
76 STV0367_SERIAL_PUNCT_CLOCK,
77 STV0367_SERIAL_CONT_CLOCK,
78 STV0367_PARALLEL_PUNCT_CLOCK,
79 STV0367_DVBCI_CLOCK
80};
81
82enum stv0367_clk_pol {
83 STV0367_CLOCKPOLARITY_DEFAULT,
84 STV0367_RISINGEDGE_CLOCK,
85 STV0367_FALLINGEDGE_CLOCK
86};
87
88enum stv0367_ter_bw {
89 FE_TER_CHAN_BW_6M = 6,
90 FE_TER_CHAN_BW_7M = 7,
91 FE_TER_CHAN_BW_8M = 8
92};
93
94#if 0
95enum FE_TER_Rate_TPS {
96 FE_TER_TPS_1_2 = 0,
97 FE_TER_TPS_2_3 = 1,
98 FE_TER_TPS_3_4 = 2,
99 FE_TER_TPS_5_6 = 3,
100 FE_TER_TPS_7_8 = 4
101};
102#endif
103
104enum stv0367_ter_mode {
105 FE_TER_MODE_2K,
106 FE_TER_MODE_8K,
107 FE_TER_MODE_4K
108};
109#if 0
110enum FE_TER_Hierarchy_Alpha {
111 FE_TER_HIER_ALPHA_NONE, /* Regular modulation */
112 FE_TER_HIER_ALPHA_1, /* Hierarchical modulation a = 1*/
113 FE_TER_HIER_ALPHA_2, /* Hierarchical modulation a = 2*/
114 FE_TER_HIER_ALPHA_4 /* Hierarchical modulation a = 4*/
115};
116#endif
117enum stv0367_ter_hierarchy {
118 FE_TER_HIER_NONE, /*Hierarchy None*/
119 FE_TER_HIER_LOW_PRIO, /*Hierarchy : Low Priority*/
120 FE_TER_HIER_HIGH_PRIO, /*Hierarchy : High Priority*/
121 FE_TER_HIER_PRIO_ANY /*Hierarchy :Any*/
122};
123
124#if 0
125enum fe_stv0367_ter_spec {
126 FE_TER_INVERSION_NONE = 0,
127 FE_TER_INVERSION = 1,
128 FE_TER_INVERSION_AUTO = 2,
129 FE_TER_INVERSION_UNK = 4
130};
131#endif
132
133enum stv0367_ter_if_iq_mode {
134 FE_TER_NORMAL_IF_TUNER = 0,
135 FE_TER_LONGPATH_IF_TUNER = 1,
136 FE_TER_IQ_TUNER = 2
137
138};
139
140#if 0
141enum FE_TER_FECRate {
142 FE_TER_FEC_NONE = 0x00, /* no FEC rate specified */
143 FE_TER_FEC_ALL = 0xFF, /* Logical OR of all FECs */
144 FE_TER_FEC_1_2 = 1,
145 FE_TER_FEC_2_3 = (1 << 1),
146 FE_TER_FEC_3_4 = (1 << 2),
147 FE_TER_FEC_4_5 = (1 << 3),
148 FE_TER_FEC_5_6 = (1 << 4),
149 FE_TER_FEC_6_7 = (1 << 5),
150 FE_TER_FEC_7_8 = (1 << 6),
151 FE_TER_FEC_8_9 = (1 << 7)
152};
153
154enum FE_TER_Rate {
155 FE_TER_FE_1_2 = 0,
156 FE_TER_FE_2_3 = 1,
157 FE_TER_FE_3_4 = 2,
158 FE_TER_FE_5_6 = 3,
159 FE_TER_FE_6_7 = 4,
160 FE_TER_FE_7_8 = 5
161};
162#endif
163
164enum stv0367_ter_force {
165 FE_TER_FORCENONE = 0,
166 FE_TER_FORCE_M_G = 1
167};
168
169enum stv0367cab_mod {
170 FE_CAB_MOD_QAM4,
171 FE_CAB_MOD_QAM16,
172 FE_CAB_MOD_QAM32,
173 FE_CAB_MOD_QAM64,
174 FE_CAB_MOD_QAM128,
175 FE_CAB_MOD_QAM256,
176 FE_CAB_MOD_QAM512,
177 FE_CAB_MOD_QAM1024
178};
179#if 0
180enum {
181 FE_CAB_FEC_A = 1, /* J83 Annex A */
182 FE_CAB_FEC_B = (1 << 1),/* J83 Annex B */
183 FE_CAB_FEC_C = (1 << 2) /* J83 Annex C */
184} FE_CAB_FECType_t;
185#endif
186struct stv0367_cab_signal_info {
187 int locked;
188 u32 frequency; /* kHz */
189 u32 symbol_rate; /* Mbds */
190 enum stv0367cab_mod modulation;
191 fe_spectral_inversion_t spect_inv;
192 s32 Power_dBmx10; /* Power of the RF signal (dBm x 10) */
193 u32 CN_dBx10; /* Carrier to noise ratio (dB x 10) */
194 u32 BER; /* Bit error rate (x 10000000) */
195};
196
197enum stv0367_cab_signal_type {
198 FE_CAB_NOTUNER,
199 FE_CAB_NOAGC,
200 FE_CAB_NOSIGNAL,
201 FE_CAB_NOTIMING,
202 FE_CAB_TIMINGOK,
203 FE_CAB_NOCARRIER,
204 FE_CAB_CARRIEROK,
205 FE_CAB_NOBLIND,
206 FE_CAB_BLINDOK,
207 FE_CAB_NODEMOD,
208 FE_CAB_DEMODOK,
209 FE_CAB_DATAOK
210};
211
212#endif
diff --git a/drivers/media/dvb/frontends/stv0367_regs.h b/drivers/media/dvb/frontends/stv0367_regs.h
new file mode 100644
index 000000000000..a96fbdc7e25e
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv0367_regs.h
@@ -0,0 +1,3614 @@
1/*
2 * stv0367_regs.h
3 *
4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
5 *
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 *
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#ifndef STV0367_REGS_H
27#define STV0367_REGS_H
28
29/* ID */
30#define R367TER_ID 0xf000
31#define F367TER_IDENTIFICATIONREG 0xf00000ff
32
33/* I2CRPT */
34#define R367TER_I2CRPT 0xf001
35#define F367TER_I2CT_ON 0xf0010080
36#define F367TER_ENARPT_LEVEL 0xf0010070
37#define F367TER_SCLT_DELAY 0xf0010008
38#define F367TER_SCLT_NOD 0xf0010004
39#define F367TER_STOP_ENABLE 0xf0010002
40#define F367TER_SDAT_NOD 0xf0010001
41
42/* TOPCTRL */
43#define R367TER_TOPCTRL 0xf002
44#define F367TER_STDBY 0xf0020080
45#define F367TER_STDBY_FEC 0xf0020040
46#define F367TER_STDBY_CORE 0xf0020020
47#define F367TER_QAM_COFDM 0xf0020010
48#define F367TER_TS_DIS 0xf0020008
49#define F367TER_DIR_CLK_216 0xf0020004
50#define F367TER_TUNER_BB 0xf0020002
51#define F367TER_DVBT_H 0xf0020001
52
53/* IOCFG0 */
54#define R367TER_IOCFG0 0xf003
55#define F367TER_OP0_SD 0xf0030080
56#define F367TER_OP0_VAL 0xf0030040
57#define F367TER_OP0_OD 0xf0030020
58#define F367TER_OP0_INV 0xf0030010
59#define F367TER_OP0_DACVALUE_HI 0xf003000f
60
61/* DAc0R */
62#define R367TER_DAC0R 0xf004
63#define F367TER_OP0_DACVALUE_LO 0xf00400ff
64
65/* IOCFG1 */
66#define R367TER_IOCFG1 0xf005
67#define F367TER_IP0 0xf0050040
68#define F367TER_OP1_OD 0xf0050020
69#define F367TER_OP1_INV 0xf0050010
70#define F367TER_OP1_DACVALUE_HI 0xf005000f
71
72/* DAC1R */
73#define R367TER_DAC1R 0xf006
74#define F367TER_OP1_DACVALUE_LO 0xf00600ff
75
76/* IOCFG2 */
77#define R367TER_IOCFG2 0xf007
78#define F367TER_OP2_LOCK_CONF 0xf00700e0
79#define F367TER_OP2_OD 0xf0070010
80#define F367TER_OP2_VAL 0xf0070008
81#define F367TER_OP1_LOCK_CONF 0xf0070007
82
83/* SDFR */
84#define R367TER_SDFR 0xf008
85#define F367TER_OP0_FREQ 0xf00800f0
86#define F367TER_OP1_FREQ 0xf008000f
87
88/* STATUS */
89#define R367TER_STATUS 0xf009
90#define F367TER_TPS_LOCK 0xf0090080
91#define F367TER_SYR_LOCK 0xf0090040
92#define F367TER_AGC_LOCK 0xf0090020
93#define F367TER_PRF 0xf0090010
94#define F367TER_LK 0xf0090008
95#define F367TER_PR 0xf0090007
96
97/* AUX_CLK */
98#define R367TER_AUX_CLK 0xf00a
99#define F367TER_AUXFEC_CTL 0xf00a00c0
100#define F367TER_DIS_CKX4 0xf00a0020
101#define F367TER_CKSEL 0xf00a0018
102#define F367TER_CKDIV_PROG 0xf00a0006
103#define F367TER_AUXCLK_ENA 0xf00a0001
104
105/* FREESYS1 */
106#define R367TER_FREESYS1 0xf00b
107#define F367TER_FREE_SYS1 0xf00b00ff
108
109/* FREESYS2 */
110#define R367TER_FREESYS2 0xf00c
111#define F367TER_FREE_SYS2 0xf00c00ff
112
113/* FREESYS3 */
114#define R367TER_FREESYS3 0xf00d
115#define F367TER_FREE_SYS3 0xf00d00ff
116
117/* GPIO_CFG */
118#define R367TER_GPIO_CFG 0xf00e
119#define F367TER_GPIO7_NOD 0xf00e0080
120#define F367TER_GPIO7_CFG 0xf00e0040
121#define F367TER_GPIO6_NOD 0xf00e0020
122#define F367TER_GPIO6_CFG 0xf00e0010
123#define F367TER_GPIO5_NOD 0xf00e0008
124#define F367TER_GPIO5_CFG 0xf00e0004
125#define F367TER_GPIO4_NOD 0xf00e0002
126#define F367TER_GPIO4_CFG 0xf00e0001
127
128/* GPIO_CMD */
129#define R367TER_GPIO_CMD 0xf00f
130#define F367TER_GPIO7_VAL 0xf00f0008
131#define F367TER_GPIO6_VAL 0xf00f0004
132#define F367TER_GPIO5_VAL 0xf00f0002
133#define F367TER_GPIO4_VAL 0xf00f0001
134
135/* AGC2MAX */
136#define R367TER_AGC2MAX 0xf010
137#define F367TER_AGC2_MAX 0xf01000ff
138
139/* AGC2MIN */
140#define R367TER_AGC2MIN 0xf011
141#define F367TER_AGC2_MIN 0xf01100ff
142
143/* AGC1MAX */
144#define R367TER_AGC1MAX 0xf012
145#define F367TER_AGC1_MAX 0xf01200ff
146
147/* AGC1MIN */
148#define R367TER_AGC1MIN 0xf013
149#define F367TER_AGC1_MIN 0xf01300ff
150
151/* AGCR */
152#define R367TER_AGCR 0xf014
153#define F367TER_RATIO_A 0xf01400e0
154#define F367TER_RATIO_B 0xf0140018
155#define F367TER_RATIO_C 0xf0140007
156
157/* AGC2TH */
158#define R367TER_AGC2TH 0xf015
159#define F367TER_AGC2_THRES 0xf01500ff
160
161/* AGC12c */
162#define R367TER_AGC12C 0xf016
163#define F367TER_AGC1_IV 0xf0160080
164#define F367TER_AGC1_OD 0xf0160040
165#define F367TER_AGC1_LOAD 0xf0160020
166#define F367TER_AGC2_IV 0xf0160010
167#define F367TER_AGC2_OD 0xf0160008
168#define F367TER_AGC2_LOAD 0xf0160004
169#define F367TER_AGC12_MODE 0xf0160003
170
171/* AGCCTRL1 */
172#define R367TER_AGCCTRL1 0xf017
173#define F367TER_DAGC_ON 0xf0170080
174#define F367TER_INVERT_AGC12 0xf0170040
175#define F367TER_AGC1_MODE 0xf0170008
176#define F367TER_AGC2_MODE 0xf0170007
177
178/* AGCCTRL2 */
179#define R367TER_AGCCTRL2 0xf018
180#define F367TER_FRZ2_CTRL 0xf0180060
181#define F367TER_FRZ1_CTRL 0xf0180018
182#define F367TER_TIME_CST 0xf0180007
183
184/* AGC1VAL1 */
185#define R367TER_AGC1VAL1 0xf019
186#define F367TER_AGC1_VAL_LO 0xf01900ff
187
188/* AGC1VAL2 */
189#define R367TER_AGC1VAL2 0xf01a
190#define F367TER_AGC1_VAL_HI 0xf01a000f
191
192/* AGC2VAL1 */
193#define R367TER_AGC2VAL1 0xf01b
194#define F367TER_AGC2_VAL_LO 0xf01b00ff
195
196/* AGC2VAL2 */
197#define R367TER_AGC2VAL2 0xf01c
198#define F367TER_AGC2_VAL_HI 0xf01c000f
199
200/* AGC2PGA */
201#define R367TER_AGC2PGA 0xf01d
202#define F367TER_AGC2_PGA 0xf01d00ff
203
204/* OVF_RATE1 */
205#define R367TER_OVF_RATE1 0xf01e
206#define F367TER_OVF_RATE_HI 0xf01e000f
207
208/* OVF_RATE2 */
209#define R367TER_OVF_RATE2 0xf01f
210#define F367TER_OVF_RATE_LO 0xf01f00ff
211
212/* GAIN_SRC1 */
213#define R367TER_GAIN_SRC1 0xf020
214#define F367TER_INV_SPECTR 0xf0200080
215#define F367TER_IQ_INVERT 0xf0200040
216#define F367TER_INR_BYPASS 0xf0200020
217#define F367TER_STATUS_INV_SPECRUM 0xf0200010
218#define F367TER_GAIN_SRC_HI 0xf020000f
219
220/* GAIN_SRC2 */
221#define R367TER_GAIN_SRC2 0xf021
222#define F367TER_GAIN_SRC_LO 0xf02100ff
223
224/* INC_DEROT1 */
225#define R367TER_INC_DEROT1 0xf022
226#define F367TER_INC_DEROT_HI 0xf02200ff
227
228/* INC_DEROT2 */
229#define R367TER_INC_DEROT2 0xf023
230#define F367TER_INC_DEROT_LO 0xf02300ff
231
232/* PPM_CPAMP_DIR */
233#define R367TER_PPM_CPAMP_DIR 0xf024
234#define F367TER_PPM_CPAMP_DIRECT 0xf02400ff
235
236/* PPM_CPAMP_INV */
237#define R367TER_PPM_CPAMP_INV 0xf025
238#define F367TER_PPM_CPAMP_INVER 0xf02500ff
239
240/* FREESTFE_1 */
241#define R367TER_FREESTFE_1 0xf026
242#define F367TER_SYMBOL_NUMBER_INC 0xf02600c0
243#define F367TER_SEL_LSB 0xf0260004
244#define F367TER_AVERAGE_ON 0xf0260002
245#define F367TER_DC_ADJ 0xf0260001
246
247/* FREESTFE_2 */
248#define R367TER_FREESTFE_2 0xf027
249#define F367TER_SEL_SRCOUT 0xf02700c0
250#define F367TER_SEL_SYRTHR 0xf027001f
251
252/* DCOFFSET */
253#define R367TER_DCOFFSET 0xf028
254#define F367TER_SELECT_I_Q 0xf0280080
255#define F367TER_DC_OFFSET 0xf028007f
256
257/* EN_PROCESS */
258#define R367TER_EN_PROCESS 0xf029
259#define F367TER_FREE 0xf02900f0
260#define F367TER_ENAB_MANUAL 0xf0290001
261
262/* SDI_SMOOTHER */
263#define R367TER_SDI_SMOOTHER 0xf02a
264#define F367TER_DIS_SMOOTH 0xf02a0080
265#define F367TER_SDI_INC_SMOOTHER 0xf02a007f
266
267/* FE_LOOP_OPEN */
268#define R367TER_FE_LOOP_OPEN 0xf02b
269#define F367TER_TRL_LOOP_OP 0xf02b0002
270#define F367TER_CRL_LOOP_OP 0xf02b0001
271
272/* FREQOFF1 */
273#define R367TER_FREQOFF1 0xf02c
274#define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff
275
276/* FREQOFF2 */
277#define R367TER_FREQOFF2 0xf02d
278#define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff
279
280/* FREQOFF3 */
281#define R367TER_FREQOFF3 0xf02e
282#define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff
283
284/* TIMOFF1 */
285#define R367TER_TIMOFF1 0xf02f
286#define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff
287
288/* TIMOFF2 */
289#define R367TER_TIMOFF2 0xf030
290#define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff
291
292/* EPQ */
293#define R367TER_EPQ 0xf031
294#define F367TER_EPQ1 0xf03100ff
295
296/* EPQAUTO */
297#define R367TER_EPQAUTO 0xf032
298#define F367TER_EPQ2 0xf03200ff
299
300/* SYR_UPDATE */
301#define R367TER_SYR_UPDATE 0xf033
302#define F367TER_SYR_PROTV 0xf0330080
303#define F367TER_SYR_PROTV_GAIN 0xf0330060
304#define F367TER_SYR_FILTER 0xf0330010
305#define F367TER_SYR_TRACK_THRES 0xf033000c
306
307/* CHPFREE */
308#define R367TER_CHPFREE 0xf034
309#define F367TER_CHP_FREE 0xf03400ff
310
311/* PPM_STATE_MAC */
312#define R367TER_PPM_STATE_MAC 0xf035
313#define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f
314
315/* INR_THRESHOLD */
316#define R367TER_INR_THRESHOLD 0xf036
317#define F367TER_INR_THRESH 0xf03600ff
318
319/* EPQ_TPS_ID_CELL */
320#define R367TER_EPQ_TPS_ID_CELL 0xf037
321#define F367TER_ENABLE_LGTH_TO_CF 0xf0370080
322#define F367TER_DIS_TPS_RSVD 0xf0370040
323#define F367TER_DIS_BCH 0xf0370020
324#define F367TER_DIS_ID_CEL 0xf0370010
325#define F367TER_TPS_ADJUST_SYM 0xf037000f
326
327/* EPQ_CFG */
328#define R367TER_EPQ_CFG 0xf038
329#define F367TER_EPQ_RANGE 0xf0380002
330#define F367TER_EPQ_SOFT 0xf0380001
331
332/* EPQ_STATUS */
333#define R367TER_EPQ_STATUS 0xf039
334#define F367TER_SLOPE_INC 0xf03900fc
335#define F367TER_TPS_FIELD 0xf0390003
336
337/* AUTORELOCK */
338#define R367TER_AUTORELOCK 0xf03a
339#define F367TER_BYPASS_BER_TEMPO 0xf03a0080
340#define F367TER_BER_TEMPO 0xf03a0070
341#define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008
342#define F367TER_COFDM_TEMPO 0xf03a0007
343
344/* BER_THR_VMSB */
345#define R367TER_BER_THR_VMSB 0xf03b
346#define F367TER_BER_THRESHOLD_HI 0xf03b00ff
347
348/* BER_THR_MSB */
349#define R367TER_BER_THR_MSB 0xf03c
350#define F367TER_BER_THRESHOLD_MID 0xf03c00ff
351
352/* BER_THR_LSB */
353#define R367TER_BER_THR_LSB 0xf03d
354#define F367TER_BER_THRESHOLD_LO 0xf03d00ff
355
356/* CCD */
357#define R367TER_CCD 0xf03e
358#define F367TER_CCD_DETECTED 0xf03e0080
359#define F367TER_CCD_RESET 0xf03e0040
360#define F367TER_CCD_THRESHOLD 0xf03e000f
361
362/* SPECTR_CFG */
363#define R367TER_SPECTR_CFG 0xf03f
364#define F367TER_SPECT_CFG 0xf03f0003
365
366/* CONSTMU_MSB */
367#define R367TER_CONSTMU_MSB 0xf040
368#define F367TER_CONSTMU_FREEZE 0xf0400080
369#define F367TER_CONSTNU_FORCE_EN 0xf0400040
370#define F367TER_CONST_MU_MSB 0xf040003f
371
372/* CONSTMU_LSB */
373#define R367TER_CONSTMU_LSB 0xf041
374#define F367TER_CONST_MU_LSB 0xf04100ff
375
376/* CONSTMU_MAX_MSB */
377#define R367TER_CONSTMU_MAX_MSB 0xf042
378#define F367TER_CONST_MU_MAX_MSB 0xf042003f
379
380/* CONSTMU_MAX_LSB */
381#define R367TER_CONSTMU_MAX_LSB 0xf043
382#define F367TER_CONST_MU_MAX_LSB 0xf04300ff
383
384/* ALPHANOISE */
385#define R367TER_ALPHANOISE 0xf044
386#define F367TER_USE_ALLFILTER 0xf0440080
387#define F367TER_INTER_ON 0xf0440040
388#define F367TER_ALPHA_NOISE 0xf044001f
389
390/* MAXGP_MSB */
391#define R367TER_MAXGP_MSB 0xf045
392#define F367TER_MUFILTER_LENGTH 0xf04500f0
393#define F367TER_MAX_GP_MSB 0xf045000f
394
395/* MAXGP_LSB */
396#define R367TER_MAXGP_LSB 0xf046
397#define F367TER_MAX_GP_LSB 0xf04600ff
398
399/* ALPHAMSB */
400#define R367TER_ALPHAMSB 0xf047
401#define F367TER_CHC_DATARATE 0xf04700c0
402#define F367TER_ALPHA_MSB 0xf047003f
403
404/* ALPHALSB */
405#define R367TER_ALPHALSB 0xf048
406#define F367TER_ALPHA_LSB 0xf04800ff
407
408/* PILOT_ACCU */
409#define R367TER_PILOT_ACCU 0xf049
410#define F367TER_USE_SCAT4ADDAPT 0xf0490080
411#define F367TER_PILOT_ACC 0xf049001f
412
413/* PILOTMU_ACCU */
414#define R367TER_PILOTMU_ACCU 0xf04a
415#define F367TER_DISCARD_BAD_SP 0xf04a0080
416#define F367TER_DISCARD_BAD_CP 0xf04a0040
417#define F367TER_PILOT_MU_ACCU 0xf04a001f
418
419/* FILT_CHANNEL_EST */
420#define R367TER_FILT_CHANNEL_EST 0xf04b
421#define F367TER_USE_FILT_PILOT 0xf04b0080
422#define F367TER_FILT_CHANNEL 0xf04b007f
423
424/* ALPHA_NOPISE_FREQ */
425#define R367TER_ALPHA_NOPISE_FREQ 0xf04c
426#define F367TER_NOISE_FREQ_FILT 0xf04c0040
427#define F367TER_ALPHA_NOISE_FREQ 0xf04c003f
428
429/* RATIO_PILOT */
430#define R367TER_RATIO_PILOT 0xf04d
431#define F367TER_RATIO_MEAN_SP 0xf04d00f0
432#define F367TER_RATIO_MEAN_CP 0xf04d000f
433
434/* CHC_CTL */
435#define R367TER_CHC_CTL 0xf04e
436#define F367TER_TRACK_EN 0xf04e0080
437#define F367TER_NOISE_NORM_EN 0xf04e0040
438#define F367TER_FORCE_CHC_RESET 0xf04e0020
439#define F367TER_SHORT_TIME 0xf04e0010
440#define F367TER_FORCE_STATE_EN 0xf04e0008
441#define F367TER_FORCE_STATE 0xf04e0007
442
443/* EPQ_ADJUST */
444#define R367TER_EPQ_ADJUST 0xf04f
445#define F367TER_ADJUST_SCAT_IND 0xf04f00c0
446#define F367TER_ONE_SYMBOL 0xf04f0010
447#define F367TER_EPQ_DECAY 0xf04f000e
448#define F367TER_HOLD_SLOPE 0xf04f0001
449
450/* EPQ_THRES */
451#define R367TER_EPQ_THRES 0xf050
452#define F367TER_EPQ_THR 0xf05000ff
453
454/* OMEGA_CTL */
455#define R367TER_OMEGA_CTL 0xf051
456#define F367TER_OMEGA_RST 0xf0510080
457#define F367TER_FREEZE_OMEGA 0xf0510040
458#define F367TER_OMEGA_SEL 0xf051003f
459
460/* GP_CTL */
461#define R367TER_GP_CTL 0xf052
462#define F367TER_CHC_STATE 0xf05200e0
463#define F367TER_FREEZE_GP 0xf0520010
464#define F367TER_GP_SEL 0xf052000f
465
466/* MUMSB */
467#define R367TER_MUMSB 0xf053
468#define F367TER_MU_MSB 0xf053007f
469
470/* MULSB */
471#define R367TER_MULSB 0xf054
472#define F367TER_MU_LSB 0xf05400ff
473
474/* GPMSB */
475#define R367TER_GPMSB 0xf055
476#define F367TER_CSI_THRESHOLD 0xf05500e0
477#define F367TER_GP_MSB 0xf055000f
478
479/* GPLSB */
480#define R367TER_GPLSB 0xf056
481#define F367TER_GP_LSB 0xf05600ff
482
483/* OMEGAMSB */
484#define R367TER_OMEGAMSB 0xf057
485#define F367TER_OMEGA_MSB 0xf057007f
486
487/* OMEGALSB */
488#define R367TER_OMEGALSB 0xf058
489#define F367TER_OMEGA_LSB 0xf05800ff
490
491/* SCAT_NB */
492#define R367TER_SCAT_NB 0xf059
493#define F367TER_CHC_TEST 0xf05900f8
494#define F367TER_SCAT_NUMB 0xf0590003
495
496/* CHC_DUMMY */
497#define R367TER_CHC_DUMMY 0xf05a
498#define F367TER_CHC_DUM 0xf05a00ff
499
500/* INC_CTL */
501#define R367TER_INC_CTL 0xf05b
502#define F367TER_INC_BYPASS 0xf05b0080
503#define F367TER_INC_NDEPTH 0xf05b000c
504#define F367TER_INC_MADEPTH 0xf05b0003
505
506/* INCTHRES_COR1 */
507#define R367TER_INCTHRES_COR1 0xf05c
508#define F367TER_INC_THRES_COR1 0xf05c00ff
509
510/* INCTHRES_COR2 */
511#define R367TER_INCTHRES_COR2 0xf05d
512#define F367TER_INC_THRES_COR2 0xf05d00ff
513
514/* INCTHRES_DET1 */
515#define R367TER_INCTHRES_DET1 0xf05e
516#define F367TER_INC_THRES_DET1 0xf05e003f
517
518/* INCTHRES_DET2 */
519#define R367TER_INCTHRES_DET2 0xf05f
520#define F367TER_INC_THRES_DET2 0xf05f003f
521
522/* IIR_CELLNB */
523#define R367TER_IIR_CELLNB 0xf060
524#define F367TER_NRST_IIR 0xf0600080
525#define F367TER_IIR_CELL_NB 0xf0600007
526
527/* IIRCX_COEFF1_MSB */
528#define R367TER_IIRCX_COEFF1_MSB 0xf061
529#define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff
530
531/* IIRCX_COEFF1_LSB */
532#define R367TER_IIRCX_COEFF1_LSB 0xf062
533#define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff
534
535/* IIRCX_COEFF2_MSB */
536#define R367TER_IIRCX_COEFF2_MSB 0xf063
537#define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff
538
539/* IIRCX_COEFF2_LSB */
540#define R367TER_IIRCX_COEFF2_LSB 0xf064
541#define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff
542
543/* IIRCX_COEFF3_MSB */
544#define R367TER_IIRCX_COEFF3_MSB 0xf065
545#define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff
546
547/* IIRCX_COEFF3_LSB */
548#define R367TER_IIRCX_COEFF3_LSB 0xf066
549#define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff
550
551/* IIRCX_COEFF4_MSB */
552#define R367TER_IIRCX_COEFF4_MSB 0xf067
553#define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff
554
555/* IIRCX_COEFF4_LSB */
556#define R367TER_IIRCX_COEFF4_LSB 0xf068
557#define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff
558
559/* IIRCX_COEFF5_MSB */
560#define R367TER_IIRCX_COEFF5_MSB 0xf069
561#define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff
562
563/* IIRCX_COEFF5_LSB */
564#define R367TER_IIRCX_COEFF5_LSB 0xf06a
565#define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff
566
567/* FEPATH_CFG */
568#define R367TER_FEPATH_CFG 0xf06b
569#define F367TER_DEMUX_SWAP 0xf06b0004
570#define F367TER_DIGAGC_SWAP 0xf06b0002
571#define F367TER_LONGPATH_IF 0xf06b0001
572
573/* PMC1_FUNC */
574#define R367TER_PMC1_FUNC 0xf06c
575#define F367TER_SOFT_RSTN 0xf06c0080
576#define F367TER_PMC1_AVERAGE_TIME 0xf06c0078
577#define F367TER_PMC1_WAIT_TIME 0xf06c0006
578#define F367TER_PMC1_2N_SEL 0xf06c0001
579
580/* PMC1_FOR */
581#define R367TER_PMC1_FOR 0xf06d
582#define F367TER_PMC1_FORCE 0xf06d0080
583#define F367TER_PMC1_FORCE_VALUE 0xf06d007c
584
585/* PMC2_FUNC */
586#define R367TER_PMC2_FUNC 0xf06e
587#define F367TER_PMC2_SOFT_STN 0xf06e0080
588#define F367TER_PMC2_ACCU_TIME 0xf06e0070
589#define F367TER_PMC2_CMDP_MN 0xf06e0008
590#define F367TER_PMC2_SWAP 0xf06e0004
591
592/* STATUS_ERR_DA */
593#define R367TER_STATUS_ERR_DA 0xf06f
594#define F367TER_COM_USEGAINTRK 0xf06f0080
595#define F367TER_COM_AGCLOCK 0xf06f0040
596#define F367TER_AUT_AGCLOCK 0xf06f0020
597#define F367TER_MIN_ERR_X_LSB 0xf06f000f
598
599/* DIG_AGC_R */
600#define R367TER_DIG_AGC_R 0xf070
601#define F367TER_COM_SOFT_RSTN 0xf0700080
602#define F367TER_COM_AGC_ON 0xf0700040
603#define F367TER_COM_EARLY 0xf0700020
604#define F367TER_AUT_SOFT_RESETN 0xf0700010
605#define F367TER_AUT_AGC_ON 0xf0700008
606#define F367TER_AUT_EARLY 0xf0700004
607#define F367TER_AUT_ROT_EN 0xf0700002
608#define F367TER_LOCK_SOFT_RESETN 0xf0700001
609
610/* COMAGC_TARMSB */
611#define R367TER_COMAGC_TARMSB 0xf071
612#define F367TER_COM_AGC_TARGET_MSB 0xf07100ff
613
614/* COM_AGC_TAR_ENMODE */
615#define R367TER_COM_AGC_TAR_ENMODE 0xf072
616#define F367TER_COM_AGC_TARGET_LSB 0xf07200f0
617#define F367TER_COM_ENMODE 0xf072000f
618
619/* COM_AGC_CFG */
620#define R367TER_COM_AGC_CFG 0xf073
621#define F367TER_COM_N 0xf07300f8
622#define F367TER_COM_STABMODE 0xf0730006
623#define F367TER_ERR_SEL 0xf0730001
624
625/* COM_AGC_GAIN1 */
626#define R367TER_COM_AGC_GAIN1 0xf074
627#define F367TER_COM_GAIN1aCK 0xf07400f0
628#define F367TER_COM_GAIN1TRK 0xf074000f
629
630/* AUT_AGC_TARGETMSB */
631#define R367TER_AUT_AGC_TARGETMSB 0xf075
632#define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff
633
634/* LOCK_DET_MSB */
635#define R367TER_LOCK_DET_MSB 0xf076
636#define F367TER_LOCK_DETECT_MSB 0xf07600ff
637
638/* AGCTAR_LOCK_LSBS */
639#define R367TER_AGCTAR_LOCK_LSBS 0xf077
640#define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0
641#define F367TER_LOCK_DETECT_LSB 0xf077000f
642
643/* AUT_GAIN_EN */
644#define R367TER_AUT_GAIN_EN 0xf078
645#define F367TER_AUT_ENMODE 0xf07800f0
646#define F367TER_AUT_GAIN2 0xf078000f
647
648/* AUT_CFG */
649#define R367TER_AUT_CFG 0xf079
650#define F367TER_AUT_N 0xf07900f8
651#define F367TER_INT_CHOICE 0xf0790006
652#define F367TER_INT_LOAD 0xf0790001
653
654/* LOCKN */
655#define R367TER_LOCKN 0xf07a
656#define F367TER_LOCK_N 0xf07a00f8
657#define F367TER_SEL_IQNTAR 0xf07a0004
658#define F367TER_LOCK_DETECT_CHOICE 0xf07a0003
659
660/* INT_X_3 */
661#define R367TER_INT_X_3 0xf07b
662#define F367TER_INT_X3 0xf07b00ff
663
664/* INT_X_2 */
665#define R367TER_INT_X_2 0xf07c
666#define F367TER_INT_X2 0xf07c00ff
667
668/* INT_X_1 */
669#define R367TER_INT_X_1 0xf07d
670#define F367TER_INT_X1 0xf07d00ff
671
672/* INT_X_0 */
673#define R367TER_INT_X_0 0xf07e
674#define F367TER_INT_X0 0xf07e00ff
675
676/* MIN_ERRX_MSB */
677#define R367TER_MIN_ERRX_MSB 0xf07f
678#define F367TER_MIN_ERR_X_MSB 0xf07f00ff
679
680/* COR_CTL */
681#define R367TER_COR_CTL 0xf080
682#define F367TER_CORE_ACTIVE 0xf0800020
683#define F367TER_HOLD 0xf0800010
684#define F367TER_CORE_STATE_CTL 0xf080000f
685
686/* COR_STAT */
687#define R367TER_COR_STAT 0xf081
688#define F367TER_SCATT_LOCKED 0xf0810080
689#define F367TER_TPS_LOCKED 0xf0810040
690#define F367TER_SYR_LOCKED_COR 0xf0810020
691#define F367TER_AGC_LOCKED_STAT 0xf0810010
692#define F367TER_CORE_STATE_STAT 0xf081000f
693
694/* COR_INTEN */
695#define R367TER_COR_INTEN 0xf082
696#define F367TER_INTEN 0xf0820080
697#define F367TER_INTEN_SYR 0xf0820020
698#define F367TER_INTEN_FFT 0xf0820010
699#define F367TER_INTEN_AGC 0xf0820008
700#define F367TER_INTEN_TPS1 0xf0820004
701#define F367TER_INTEN_TPS2 0xf0820002
702#define F367TER_INTEN_TPS3 0xf0820001
703
704/* COR_INTSTAT */
705#define R367TER_COR_INTSTAT 0xf083
706#define F367TER_INTSTAT_SYR 0xf0830020
707#define F367TER_INTSTAT_FFT 0xf0830010
708#define F367TER_INTSAT_AGC 0xf0830008
709#define F367TER_INTSTAT_TPS1 0xf0830004
710#define F367TER_INTSTAT_TPS2 0xf0830002
711#define F367TER_INTSTAT_TPS3 0xf0830001
712
713/* COR_MODEGUARD */
714#define R367TER_COR_MODEGUARD 0xf084
715#define F367TER_FORCE 0xf0840010
716#define F367TER_MODE 0xf084000c
717#define F367TER_GUARD 0xf0840003
718
719/* AGC_CTL */
720#define R367TER_AGC_CTL 0xf085
721#define F367TER_AGC_TIMING_FACTOR 0xf08500e0
722#define F367TER_AGC_LAST 0xf0850010
723#define F367TER_AGC_GAIN 0xf085000c
724#define F367TER_AGC_NEG 0xf0850002
725#define F367TER_AGC_SET 0xf0850001
726
727/* AGC_MANUAL1 */
728#define R367TER_AGC_MANUAL1 0xf086
729#define F367TER_AGC_VAL_LO 0xf08600ff
730
731/* AGC_MANUAL2 */
732#define R367TER_AGC_MANUAL2 0xf087
733#define F367TER_AGC_VAL_HI 0xf087000f
734
735/* AGC_TARG */
736#define R367TER_AGC_TARG 0xf088
737#define F367TER_AGC_TARGET 0xf08800ff
738
739/* AGC_GAIN1 */
740#define R367TER_AGC_GAIN1 0xf089
741#define F367TER_AGC_GAIN_LO 0xf08900ff
742
743/* AGC_GAIN2 */
744#define R367TER_AGC_GAIN2 0xf08a
745#define F367TER_AGC_LOCKED_GAIN2 0xf08a0010
746#define F367TER_AGC_GAIN_HI 0xf08a000f
747
748/* RESERVED_1 */
749#define R367TER_RESERVED_1 0xf08b
750#define F367TER_RESERVED1 0xf08b00ff
751
752/* RESERVED_2 */
753#define R367TER_RESERVED_2 0xf08c
754#define F367TER_RESERVED2 0xf08c00ff
755
756/* RESERVED_3 */
757#define R367TER_RESERVED_3 0xf08d
758#define F367TER_RESERVED3 0xf08d00ff
759
760/* CAS_CTL */
761#define R367TER_CAS_CTL 0xf08e
762#define F367TER_CCS_ENABLE 0xf08e0080
763#define F367TER_ACS_DISABLE 0xf08e0040
764#define F367TER_DAGC_DIS 0xf08e0020
765#define F367TER_DAGC_GAIN 0xf08e0018
766#define F367TER_CCSMU 0xf08e0007
767
768/* CAS_FREQ */
769#define R367TER_CAS_FREQ 0xf08f
770#define F367TER_CCS_FREQ 0xf08f00ff
771
772/* CAS_DAGCGAIN */
773#define R367TER_CAS_DAGCGAIN 0xf090
774#define F367TER_CAS_DAGC_GAIN 0xf09000ff
775
776/* SYR_CTL */
777#define R367TER_SYR_CTL 0xf091
778#define F367TER_SICTH_ENABLE 0xf0910080
779#define F367TER_LONG_ECHO 0xf0910078
780#define F367TER_AUTO_LE_EN 0xf0910004
781#define F367TER_SYR_BYPASS 0xf0910002
782#define F367TER_SYR_TR_DIS 0xf0910001
783
784/* SYR_STAT */
785#define R367TER_SYR_STAT 0xf092
786#define F367TER_SYR_LOCKED_STAT 0xf0920010
787#define F367TER_SYR_MODE 0xf092000c
788#define F367TER_SYR_GUARD 0xf0920003
789
790/* SYR_NCO1 */
791#define R367TER_SYR_NCO1 0xf093
792#define F367TER_SYR_NCO_LO 0xf09300ff
793
794/* SYR_NCO2 */
795#define R367TER_SYR_NCO2 0xf094
796#define F367TER_SYR_NCO_HI 0xf094003f
797
798/* SYR_OFFSET1 */
799#define R367TER_SYR_OFFSET1 0xf095
800#define F367TER_SYR_OFFSET_LO 0xf09500ff
801
802/* SYR_OFFSET2 */
803#define R367TER_SYR_OFFSET2 0xf096
804#define F367TER_SYR_OFFSET_HI 0xf096003f
805
806/* FFT_CTL */
807#define R367TER_FFT_CTL 0xf097
808#define F367TER_SHIFT_FFT_TRIG 0xf0970018
809#define F367TER_FFT_TRIGGER 0xf0970004
810#define F367TER_FFT_MANUAL 0xf0970002
811#define F367TER_IFFT_MODE 0xf0970001
812
813/* SCR_CTL */
814#define R367TER_SCR_CTL 0xf098
815#define F367TER_SYRADJDECAY 0xf0980070
816#define F367TER_SCR_CPEDIS 0xf0980002
817#define F367TER_SCR_DIS 0xf0980001
818
819/* PPM_CTL1 */
820#define R367TER_PPM_CTL1 0xf099
821#define F367TER_PPM_MAXFREQ 0xf0990030
822#define F367TER_PPM_MAXTIM 0xf0990008
823#define F367TER_PPM_INVSEL 0xf0990004
824#define F367TER_PPM_SCATDIS 0xf0990002
825#define F367TER_PPM_BYP 0xf0990001
826
827/* TRL_CTL */
828#define R367TER_TRL_CTL 0xf09a
829#define F367TER_TRL_NOMRATE_LSB 0xf09a0080
830#define F367TER_TRL_GAIN_FACTOR 0xf09a0078
831#define F367TER_TRL_LOOPGAIN 0xf09a0007
832
833/* TRL_NOMRATE1 */
834#define R367TER_TRL_NOMRATE1 0xf09b
835#define F367TER_TRL_NOMRATE_LO 0xf09b00ff
836
837/* TRL_NOMRATE2 */
838#define R367TER_TRL_NOMRATE2 0xf09c
839#define F367TER_TRL_NOMRATE_HI 0xf09c00ff
840
841/* TRL_TIME1 */
842#define R367TER_TRL_TIME1 0xf09d
843#define F367TER_TRL_TOFFSET_LO 0xf09d00ff
844
845/* TRL_TIME2 */
846#define R367TER_TRL_TIME2 0xf09e
847#define F367TER_TRL_TOFFSET_HI 0xf09e00ff
848
849/* CRL_CTL */
850#define R367TER_CRL_CTL 0xf09f
851#define F367TER_CRL_DIS 0xf09f0080
852#define F367TER_CRL_GAIN_FACTOR 0xf09f0078
853#define F367TER_CRL_LOOPGAIN 0xf09f0007
854
855/* CRL_FREQ1 */
856#define R367TER_CRL_FREQ1 0xf0a0
857#define F367TER_CRL_FOFFSET_LO 0xf0a000ff
858
859/* CRL_FREQ2 */
860#define R367TER_CRL_FREQ2 0xf0a1
861#define F367TER_CRL_FOFFSET_HI 0xf0a100ff
862
863/* CRL_FREQ3 */
864#define R367TER_CRL_FREQ3 0xf0a2
865#define F367TER_CRL_FOFFSET_VHI 0xf0a200ff
866
867/* TPS_SFRAME_CTL */
868#define R367TER_TPS_SFRAME_CTL 0xf0a3
869#define F367TER_TPS_SFRAME_SYNC 0xf0a30001
870
871/* CHC_SNR */
872#define R367TER_CHC_SNR 0xf0a4
873#define F367TER_CHCSNR 0xf0a400ff
874
875/* BDI_CTL */
876#define R367TER_BDI_CTL 0xf0a5
877#define F367TER_BDI_LPSEL 0xf0a50002
878#define F367TER_BDI_SERIAL 0xf0a50001
879
880/* DMP_CTL */
881#define R367TER_DMP_CTL 0xf0a6
882#define F367TER_DMP_SCALING_FACTOR 0xf0a6001e
883#define F367TER_DMP_SDDIS 0xf0a60001
884
885/* TPS_RCVD1 */
886#define R367TER_TPS_RCVD1 0xf0a7
887#define F367TER_TPS_CHANGE 0xf0a70040
888#define F367TER_BCH_OK 0xf0a70020
889#define F367TER_TPS_SYNC 0xf0a70010
890#define F367TER_TPS_FRAME 0xf0a70003
891
892/* TPS_RCVD2 */
893#define R367TER_TPS_RCVD2 0xf0a8
894#define F367TER_TPS_HIERMODE 0xf0a80070
895#define F367TER_TPS_CONST 0xf0a80003
896
897/* TPS_RCVD3 */
898#define R367TER_TPS_RCVD3 0xf0a9
899#define F367TER_TPS_LPCODE 0xf0a90070
900#define F367TER_TPS_HPCODE 0xf0a90007
901
902/* TPS_RCVD4 */
903#define R367TER_TPS_RCVD4 0xf0aa
904#define F367TER_TPS_GUARD 0xf0aa0030
905#define F367TER_TPS_MODE 0xf0aa0003
906
907/* TPS_ID_CELL1 */
908#define R367TER_TPS_ID_CELL1 0xf0ab
909#define F367TER_TPS_ID_CELL_LO 0xf0ab00ff
910
911/* TPS_ID_CELL2 */
912#define R367TER_TPS_ID_CELL2 0xf0ac
913#define F367TER_TPS_ID_CELL_HI 0xf0ac00ff
914
915/* TPS_RCVD5_SET1 */
916#define R367TER_TPS_RCVD5_SET1 0xf0ad
917#define F367TER_TPS_NA 0xf0ad00fC
918#define F367TER_TPS_SETFRAME 0xf0ad0003
919
920/* TPS_SET2 */
921#define R367TER_TPS_SET2 0xf0ae
922#define F367TER_TPS_SETHIERMODE 0xf0ae0070
923#define F367TER_TPS_SETCONST 0xf0ae0003
924
925/* TPS_SET3 */
926#define R367TER_TPS_SET3 0xf0af
927#define F367TER_TPS_SETLPCODE 0xf0af0070
928#define F367TER_TPS_SETHPCODE 0xf0af0007
929
930/* TPS_CTL */
931#define R367TER_TPS_CTL 0xf0b0
932#define F367TER_TPS_IMM 0xf0b00004
933#define F367TER_TPS_BCHDIS 0xf0b00002
934#define F367TER_TPS_UPDDIS 0xf0b00001
935
936/* CTL_FFTOSNUM */
937#define R367TER_CTL_FFTOSNUM 0xf0b1
938#define F367TER_SYMBOL_NUMBER 0xf0b1007f
939
940/* TESTSELECT */
941#define R367TER_TESTSELECT 0xf0b2
942#define F367TER_TEST_SELECT 0xf0b2001f
943
944/* MSC_REV */
945#define R367TER_MSC_REV 0xf0b3
946#define F367TER_REV_NUMBER 0xf0b300ff
947
948/* PIR_CTL */
949#define R367TER_PIR_CTL 0xf0b4
950#define F367TER_FREEZE 0xf0b40001
951
952/* SNR_CARRIER1 */
953#define R367TER_SNR_CARRIER1 0xf0b5
954#define F367TER_SNR_CARRIER_LO 0xf0b500ff
955
956/* SNR_CARRIER2 */
957#define R367TER_SNR_CARRIER2 0xf0b6
958#define F367TER_MEAN 0xf0b600c0
959#define F367TER_SNR_CARRIER_HI 0xf0b6001f
960
961/* PPM_CPAMP */
962#define R367TER_PPM_CPAMP 0xf0b7
963#define F367TER_PPM_CPC 0xf0b700ff
964
965/* TSM_AP0 */
966#define R367TER_TSM_AP0 0xf0b8
967#define F367TER_ADDRESS_BYTE_0 0xf0b800ff
968
969/* TSM_AP1 */
970#define R367TER_TSM_AP1 0xf0b9
971#define F367TER_ADDRESS_BYTE_1 0xf0b900ff
972
973/* TSM_AP2 */
974#define R367TER_TSM_AP2 0xf0bA
975#define F367TER_DATA_BYTE_0 0xf0ba00ff
976
977/* TSM_AP3 */
978#define R367TER_TSM_AP3 0xf0bB
979#define F367TER_DATA_BYTE_1 0xf0bb00ff
980
981/* TSM_AP4 */
982#define R367TER_TSM_AP4 0xf0bC
983#define F367TER_DATA_BYTE_2 0xf0bc00ff
984
985/* TSM_AP5 */
986#define R367TER_TSM_AP5 0xf0bD
987#define F367TER_DATA_BYTE_3 0xf0bd00ff
988
989/* TSM_AP6 */
990#define R367TER_TSM_AP6 0xf0bE
991#define F367TER_TSM_AP_6 0xf0be00ff
992
993/* TSM_AP7 */
994#define R367TER_TSM_AP7 0xf0bF
995#define F367TER_MEM_SELECT_BYTE 0xf0bf00ff
996
997/* TSTRES */
998#define R367TER_TSTRES 0xf0c0
999#define F367TER_FRES_DISPLAY 0xf0c00080
1000#define F367TER_FRES_FIFO_AD 0xf0c00020
1001#define F367TER_FRESRS 0xf0c00010
1002#define F367TER_FRESACS 0xf0c00008
1003#define F367TER_FRESFEC 0xf0c00004
1004#define F367TER_FRES_PRIF 0xf0c00002
1005#define F367TER_FRESCORE 0xf0c00001
1006
1007/* ANACTRL */
1008#define R367TER_ANACTRL 0xf0c1
1009#define F367TER_BYPASS_XTAL 0xf0c10040
1010#define F367TER_BYPASS_PLLXN 0xf0c1000c
1011#define F367TER_DIS_PAD_OSC 0xf0c10002
1012#define F367TER_STDBY_PLLXN 0xf0c10001
1013
1014/* TSTBUS */
1015#define R367TER_TSTBUS 0xf0c2
1016#define F367TER_TS_BYTE_CLK_INV 0xf0c20080
1017#define F367TER_CFG_IP 0xf0c20070
1018#define F367TER_CFG_TST 0xf0c2000f
1019
1020/* TSTRATE */
1021#define R367TER_TSTRATE 0xf0c6
1022#define F367TER_FORCEPHA 0xf0c60080
1023#define F367TER_FNEWPHA 0xf0c60010
1024#define F367TER_FROT90 0xf0c60008
1025#define F367TER_FR 0xf0c60007
1026
1027/* CONSTMODE */
1028#define R367TER_CONSTMODE 0xf0cb
1029#define F367TER_TST_PRIF 0xf0cb00e0
1030#define F367TER_CAR_TYPE 0xf0cb0018
1031#define F367TER_CONST_MODE 0xf0cb0003
1032
1033/* CONSTCARR1 */
1034#define R367TER_CONSTCARR1 0xf0cc
1035#define F367TER_CONST_CARR_LO 0xf0cc00ff
1036
1037/* CONSTCARR2 */
1038#define R367TER_CONSTCARR2 0xf0cd
1039#define F367TER_CONST_CARR_HI 0xf0cd001f
1040
1041/* ICONSTEL */
1042#define R367TER_ICONSTEL 0xf0ce
1043#define F367TER_PICONSTEL 0xf0ce00ff
1044
1045/* QCONSTEL */
1046#define R367TER_QCONSTEL 0xf0cf
1047#define F367TER_PQCONSTEL 0xf0cf00ff
1048
1049/* TSTBISTRES0 */
1050#define R367TER_TSTBISTRES0 0xf0d0
1051#define F367TER_BEND_PPM 0xf0d00080
1052#define F367TER_BBAD_PPM 0xf0d00040
1053#define F367TER_BEND_FFTW 0xf0d00020
1054#define F367TER_BBAD_FFTW 0xf0d00010
1055#define F367TER_BEND_FFT_BUF 0xf0d00008
1056#define F367TER_BBAD_FFT_BUF 0xf0d00004
1057#define F367TER_BEND_SYR 0xf0d00002
1058#define F367TER_BBAD_SYR 0xf0d00001
1059
1060/* TSTBISTRES1 */
1061#define R367TER_TSTBISTRES1 0xf0d1
1062#define F367TER_BEND_CHC_CP 0xf0d10080
1063#define F367TER_BBAD_CHC_CP 0xf0d10040
1064#define F367TER_BEND_CHCI 0xf0d10020
1065#define F367TER_BBAD_CHCI 0xf0d10010
1066#define F367TER_BEND_BDI 0xf0d10008
1067#define F367TER_BBAD_BDI 0xf0d10004
1068#define F367TER_BEND_SDI 0xf0d10002
1069#define F367TER_BBAD_SDI 0xf0d10001
1070
1071/* TSTBISTRES2 */
1072#define R367TER_TSTBISTRES2 0xf0d2
1073#define F367TER_BEND_CHC_INC 0xf0d20080
1074#define F367TER_BBAD_CHC_INC 0xf0d20040
1075#define F367TER_BEND_CHC_SPP 0xf0d20020
1076#define F367TER_BBAD_CHC_SPP 0xf0d20010
1077#define F367TER_BEND_CHC_CPP 0xf0d20008
1078#define F367TER_BBAD_CHC_CPP 0xf0d20004
1079#define F367TER_BEND_CHC_SP 0xf0d20002
1080#define F367TER_BBAD_CHC_SP 0xf0d20001
1081
1082/* TSTBISTRES3 */
1083#define R367TER_TSTBISTRES3 0xf0d3
1084#define F367TER_BEND_QAM 0xf0d30080
1085#define F367TER_BBAD_QAM 0xf0d30040
1086#define F367TER_BEND_SFEC_VIT 0xf0d30020
1087#define F367TER_BBAD_SFEC_VIT 0xf0d30010
1088#define F367TER_BEND_SFEC_DLINE 0xf0d30008
1089#define F367TER_BBAD_SFEC_DLINE 0xf0d30004
1090#define F367TER_BEND_SFEC_HW 0xf0d30002
1091#define F367TER_BBAD_SFEC_HW 0xf0d30001
1092
1093/* RF_AGC1 */
1094#define R367TER_RF_AGC1 0xf0d4
1095#define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff
1096
1097/* RF_AGC2 */
1098#define R367TER_RF_AGC2 0xf0d5
1099#define F367TER_REF_ADGP 0xf0d50080
1100#define F367TER_STDBY_ADCGP 0xf0d50020
1101#define F367TER_CHANNEL_SEL 0xf0d5001c
1102#define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003
1103
1104/* ANADIGCTRL */
1105#define R367TER_ANADIGCTRL 0xf0d7
1106#define F367TER_SEL_CLKDEM 0xf0d70020
1107#define F367TER_EN_BUFFER_Q 0xf0d70010
1108#define F367TER_EN_BUFFER_I 0xf0d70008
1109#define F367TER_ADC_RIS_EGDE 0xf0d70004
1110#define F367TER_SGN_ADC 0xf0d70002
1111#define F367TER_SEL_AD12_SYNC 0xf0d70001
1112
1113/* PLLMDIV */
1114#define R367TER_PLLMDIV 0xf0d8
1115#define F367TER_PLL_MDIV 0xf0d800ff
1116
1117/* PLLNDIV */
1118#define R367TER_PLLNDIV 0xf0d9
1119#define F367TER_PLL_NDIV 0xf0d900ff
1120
1121/* PLLSETUP */
1122#define R367TER_PLLSETUP 0xf0dA
1123#define F367TER_PLL_PDIV 0xf0da0070
1124#define F367TER_PLL_KDIV 0xf0da000f
1125
1126/* DUAL_AD12 */
1127#define R367TER_DUAL_AD12 0xf0dB
1128#define F367TER_FS20M 0xf0db0020
1129#define F367TER_FS50M 0xf0db0010
1130#define F367TER_INMODe0 0xf0db0008
1131#define F367TER_POFFQ 0xf0db0004
1132#define F367TER_POFFI 0xf0db0002
1133#define F367TER_INMODE1 0xf0db0001
1134
1135/* TSTBIST */
1136#define R367TER_TSTBIST 0xf0dC
1137#define F367TER_TST_BYP_CLK 0xf0dc0080
1138#define F367TER_TST_GCLKENA_STD 0xf0dc0040
1139#define F367TER_TST_GCLKENA 0xf0dc0020
1140#define F367TER_TST_MEMBIST 0xf0dc001f
1141
1142/* PAD_COMP_CTRL */
1143#define R367TER_PAD_COMP_CTRL 0xf0dD
1144#define F367TER_COMPTQ 0xf0dd0010
1145#define F367TER_COMPEN 0xf0dd0008
1146#define F367TER_FREEZE2 0xf0dd0004
1147#define F367TER_SLEEP_INHBT 0xf0dd0002
1148#define F367TER_CHIP_SLEEP 0xf0dd0001
1149
1150/* PAD_COMP_WR */
1151#define R367TER_PAD_COMP_WR 0xf0de
1152#define F367TER_WR_ASRC 0xf0de007f
1153
1154/* PAD_COMP_RD */
1155#define R367TER_PAD_COMP_RD 0xf0df
1156#define F367TER_COMPOK 0xf0df0080
1157#define F367TER_RD_ASRC 0xf0df007f
1158
1159/* SYR_TARGET_FFTADJT_MSB */
1160#define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100
1161#define F367TER_SYR_START 0xf1000080
1162#define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f
1163
1164/* SYR_TARGET_FFTADJT_LSB */
1165#define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101
1166#define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff
1167
1168/* SYR_TARGET_CHCADJT_MSB */
1169#define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102
1170#define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f
1171
1172/* SYR_TARGET_CHCADJT_LSB */
1173#define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103
1174#define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff
1175
1176/* SYR_FLAG */
1177#define R367TER_SYR_FLAG 0xf104
1178#define F367TER_TRIG_FLG1 0xf1040080
1179#define F367TER_TRIG_FLG0 0xf1040040
1180#define F367TER_FFT_FLG1 0xf1040008
1181#define F367TER_FFT_FLG0 0xf1040004
1182#define F367TER_CHC_FLG1 0xf1040002
1183#define F367TER_CHC_FLG0 0xf1040001
1184
1185/* CRL_TARGET1 */
1186#define R367TER_CRL_TARGET1 0xf105
1187#define F367TER_CRL_START 0xf1050080
1188#define F367TER_CRL_TARGET_VHI 0xf105000f
1189
1190/* CRL_TARGET2 */
1191#define R367TER_CRL_TARGET2 0xf106
1192#define F367TER_CRL_TARGET_HI 0xf10600ff
1193
1194/* CRL_TARGET3 */
1195#define R367TER_CRL_TARGET3 0xf107
1196#define F367TER_CRL_TARGET_LO 0xf10700ff
1197
1198/* CRL_TARGET4 */
1199#define R367TER_CRL_TARGET4 0xf108
1200#define F367TER_CRL_TARGET_VLO 0xf10800ff
1201
1202/* CRL_FLAG */
1203#define R367TER_CRL_FLAG 0xf109
1204#define F367TER_CRL_FLAG1 0xf1090002
1205#define F367TER_CRL_FLAG0 0xf1090001
1206
1207/* TRL_TARGET1 */
1208#define R367TER_TRL_TARGET1 0xf10a
1209#define F367TER_TRL_TARGET_HI 0xf10a00ff
1210
1211/* TRL_TARGET2 */
1212#define R367TER_TRL_TARGET2 0xf10b
1213#define F367TER_TRL_TARGET_LO 0xf10b00ff
1214
1215/* TRL_CHC */
1216#define R367TER_TRL_CHC 0xf10c
1217#define F367TER_TRL_START 0xf10c0080
1218#define F367TER_CHC_START 0xf10c0040
1219#define F367TER_TRL_FLAG1 0xf10c0002
1220#define F367TER_TRL_FLAG0 0xf10c0001
1221
1222/* CHC_SNR_TARG */
1223#define R367TER_CHC_SNR_TARG 0xf10d
1224#define F367TER_CHC_SNR_TARGET 0xf10d00ff
1225
1226/* TOP_TRACK */
1227#define R367TER_TOP_TRACK 0xf10e
1228#define F367TER_TOP_START 0xf10e0080
1229#define F367TER_FIRST_FLAG 0xf10e0070
1230#define F367TER_TOP_FLAG1 0xf10e0008
1231#define F367TER_TOP_FLAG0 0xf10e0004
1232#define F367TER_CHC_FLAG1 0xf10e0002
1233#define F367TER_CHC_FLAG0 0xf10e0001
1234
1235/* TRACKER_FREE1 */
1236#define R367TER_TRACKER_FREE1 0xf10f
1237#define F367TER_TRACKER_FREE_1 0xf10f00ff
1238
1239/* ERROR_CRL1 */
1240#define R367TER_ERROR_CRL1 0xf110
1241#define F367TER_ERROR_CRL_VHI 0xf11000ff
1242
1243/* ERROR_CRL2 */
1244#define R367TER_ERROR_CRL2 0xf111
1245#define F367TER_ERROR_CRL_HI 0xf11100ff
1246
1247/* ERROR_CRL3 */
1248#define R367TER_ERROR_CRL3 0xf112
1249#define F367TER_ERROR_CRL_LOI 0xf11200ff
1250
1251/* ERROR_CRL4 */
1252#define R367TER_ERROR_CRL4 0xf113
1253#define F367TER_ERROR_CRL_VLO 0xf11300ff
1254
1255/* DEC_NCO1 */
1256#define R367TER_DEC_NCO1 0xf114
1257#define F367TER_DEC_NCO_VHI 0xf11400ff
1258
1259/* DEC_NCO2 */
1260#define R367TER_DEC_NCO2 0xf115
1261#define F367TER_DEC_NCO_HI 0xf11500ff
1262
1263/* DEC_NCO3 */
1264#define R367TER_DEC_NCO3 0xf116
1265#define F367TER_DEC_NCO_LO 0xf11600ff
1266
1267/* SNR */
1268#define R367TER_SNR 0xf117
1269#define F367TER_SNRATIO 0xf11700ff
1270
1271/* SYR_FFTADJ1 */
1272#define R367TER_SYR_FFTADJ1 0xf118
1273#define F367TER_SYR_FFTADJ_HI 0xf11800ff
1274
1275/* SYR_FFTADJ2 */
1276#define R367TER_SYR_FFTADJ2 0xf119
1277#define F367TER_SYR_FFTADJ_LO 0xf11900ff
1278
1279/* SYR_CHCADJ1 */
1280#define R367TER_SYR_CHCADJ1 0xf11a
1281#define F367TER_SYR_CHCADJ_HI 0xf11a00ff
1282
1283/* SYR_CHCADJ2 */
1284#define R367TER_SYR_CHCADJ2 0xf11b
1285#define F367TER_SYR_CHCADJ_LO 0xf11b00ff
1286
1287/* SYR_OFF */
1288#define R367TER_SYR_OFF 0xf11c
1289#define F367TER_SYR_OFFSET 0xf11c00ff
1290
1291/* PPM_OFFSET1 */
1292#define R367TER_PPM_OFFSET1 0xf11d
1293#define F367TER_PPM_OFFSET_HI 0xf11d00ff
1294
1295/* PPM_OFFSET2 */
1296#define R367TER_PPM_OFFSET2 0xf11e
1297#define F367TER_PPM_OFFSET_LO 0xf11e00ff
1298
1299/* TRACKER_FREE2 */
1300#define R367TER_TRACKER_FREE2 0xf11f
1301#define F367TER_TRACKER_FREE_2 0xf11f00ff
1302
1303/* DEBG_LT10 */
1304#define R367TER_DEBG_LT10 0xf120
1305#define F367TER_DEBUG_LT10 0xf12000ff
1306
1307/* DEBG_LT11 */
1308#define R367TER_DEBG_LT11 0xf121
1309#define F367TER_DEBUG_LT11 0xf12100ff
1310
1311/* DEBG_LT12 */
1312#define R367TER_DEBG_LT12 0xf122
1313#define F367TER_DEBUG_LT12 0xf12200ff
1314
1315/* DEBG_LT13 */
1316#define R367TER_DEBG_LT13 0xf123
1317#define F367TER_DEBUG_LT13 0xf12300ff
1318
1319/* DEBG_LT14 */
1320#define R367TER_DEBG_LT14 0xf124
1321#define F367TER_DEBUG_LT14 0xf12400ff
1322
1323/* DEBG_LT15 */
1324#define R367TER_DEBG_LT15 0xf125
1325#define F367TER_DEBUG_LT15 0xf12500ff
1326
1327/* DEBG_LT16 */
1328#define R367TER_DEBG_LT16 0xf126
1329#define F367TER_DEBUG_LT16 0xf12600ff
1330
1331/* DEBG_LT17 */
1332#define R367TER_DEBG_LT17 0xf127
1333#define F367TER_DEBUG_LT17 0xf12700ff
1334
1335/* DEBG_LT18 */
1336#define R367TER_DEBG_LT18 0xf128
1337#define F367TER_DEBUG_LT18 0xf12800ff
1338
1339/* DEBG_LT19 */
1340#define R367TER_DEBG_LT19 0xf129
1341#define F367TER_DEBUG_LT19 0xf12900ff
1342
1343/* DEBG_LT1a */
1344#define R367TER_DEBG_LT1A 0xf12a
1345#define F367TER_DEBUG_LT1A 0xf12a00ff
1346
1347/* DEBG_LT1b */
1348#define R367TER_DEBG_LT1B 0xf12b
1349#define F367TER_DEBUG_LT1B 0xf12b00ff
1350
1351/* DEBG_LT1c */
1352#define R367TER_DEBG_LT1C 0xf12c
1353#define F367TER_DEBUG_LT1C 0xf12c00ff
1354
1355/* DEBG_LT1D */
1356#define R367TER_DEBG_LT1D 0xf12d
1357#define F367TER_DEBUG_LT1D 0xf12d00ff
1358
1359/* DEBG_LT1E */
1360#define R367TER_DEBG_LT1E 0xf12e
1361#define F367TER_DEBUG_LT1E 0xf12e00ff
1362
1363/* DEBG_LT1F */
1364#define R367TER_DEBG_LT1F 0xf12f
1365#define F367TER_DEBUG_LT1F 0xf12f00ff
1366
1367/* RCCFGH */
1368#define R367TER_RCCFGH 0xf200
1369#define F367TER_TSRCFIFO_DVBCI 0xf2000080
1370#define F367TER_TSRCFIFO_SERIAL 0xf2000040
1371#define F367TER_TSRCFIFO_DISABLE 0xf2000020
1372#define F367TER_TSFIFO_2TORC 0xf2000010
1373#define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008
1374#define F367TER_TSRCFIFO_ERRMODE 0xf2000006
1375#define F367TER_RCCFGH_0 0xf2000001
1376
1377/* RCCFGM */
1378#define R367TER_RCCFGM 0xf201
1379#define F367TER_TSRCFIFO_MANSPEED 0xf20100c0
1380#define F367TER_TSRCFIFO_PERMDATA 0xf2010020
1381#define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010
1382#define F367TER_RCBYTE_OVERSAMPLING 0xf201000e
1383#define F367TER_TSRCFIFO_INVDATA 0xf2010001
1384
1385/* RCCFGL */
1386#define R367TER_RCCFGL 0xf202
1387#define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0
1388#define F367TER_RCCFGL_5 0xf2020020
1389#define F367TER_TSRCFIFO_DUTY50 0xf2020010
1390#define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008
1391#define F367TER_TSRCFIFO_DISSERMUX 0xf2020004
1392#define F367TER_RCCFGL_1 0xf2020002
1393#define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001
1394
1395/* RCINSDELH */
1396#define R367TER_RCINSDELH 0xf203
1397#define F367TER_TSRCDEL_SYNCBYTE 0xf2030080
1398#define F367TER_TSRCDEL_XXHEADER 0xf2030040
1399#define F367TER_TSRCDEL_BBHEADER 0xf2030020
1400#define F367TER_TSRCDEL_DATAFIELD 0xf2030010
1401#define F367TER_TSRCINSDEL_ISCR 0xf2030008
1402#define F367TER_TSRCINSDEL_NPD 0xf2030004
1403#define F367TER_TSRCINSDEL_RSPARITY 0xf2030002
1404#define F367TER_TSRCINSDEL_CRC8 0xf2030001
1405
1406/* RCINSDELM */
1407#define R367TER_RCINSDELM 0xf204
1408#define F367TER_TSRCINS_BBPADDING 0xf2040080
1409#define F367TER_TSRCINS_BCHFEC 0xf2040040
1410#define F367TER_TSRCINS_LDPCFEC 0xf2040020
1411#define F367TER_TSRCINS_EMODCOD 0xf2040010
1412#define F367TER_TSRCINS_TOKEN 0xf2040008
1413#define F367TER_TSRCINS_XXXERR 0xf2040004
1414#define F367TER_TSRCINS_MATYPE 0xf2040002
1415#define F367TER_TSRCINS_UPL 0xf2040001
1416
1417/* RCINSDELL */
1418#define R367TER_RCINSDELL 0xf205
1419#define F367TER_TSRCINS_DFL 0xf2050080
1420#define F367TER_TSRCINS_SYNCD 0xf2050040
1421#define F367TER_TSRCINS_BLOCLEN 0xf2050020
1422#define F367TER_TSRCINS_SIGPCOUNT 0xf2050010
1423#define F367TER_TSRCINS_FIFO 0xf2050008
1424#define F367TER_TSRCINS_REALPACK 0xf2050004
1425#define F367TER_TSRCINS_TSCONFIG 0xf2050002
1426#define F367TER_TSRCINS_LATENCY 0xf2050001
1427
1428/* RCSTATUS */
1429#define R367TER_RCSTATUS 0xf206
1430#define F367TER_TSRCFIFO_LINEOK 0xf2060080
1431#define F367TER_TSRCFIFO_ERROR 0xf2060040
1432#define F367TER_TSRCFIFO_DATA7 0xf2060020
1433#define F367TER_RCSTATUS_4 0xf2060010
1434#define F367TER_TSRCFIFO_DEMODSEL 0xf2060008
1435#define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004
1436#define F367TER_RCSTATUS_1 0xf2060002
1437#define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001
1438
1439/* RCSPEED */
1440#define R367TER_RCSPEED 0xf207
1441#define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff
1442
1443/* RCDEBUGM */
1444#define R367TER_RCDEBUGM 0xf208
1445#define F367TER_SD_UNSYNC 0xf2080080
1446#define F367TER_ULFLOCK_DETECTM 0xf2080040
1447#define F367TER_SUL_SELECTOS 0xf2080020
1448#define F367TER_DILUL_NOSCRBLE 0xf2080010
1449#define F367TER_NUL_SCRB 0xf2080008
1450#define F367TER_UL_SCRB 0xf2080004
1451#define F367TER_SCRAULBAD 0xf2080002
1452#define F367TER_SCRAUL_UNSYNC 0xf2080001
1453
1454/* RCDEBUGL */
1455#define R367TER_RCDEBUGL 0xf209
1456#define F367TER_RS_ERR 0xf2090080
1457#define F367TER_LLFLOCK_DETECTM 0xf2090040
1458#define F367TER_NOT_SUL_SELECTOS 0xf2090020
1459#define F367TER_DILLL_NOSCRBLE 0xf2090010
1460#define F367TER_NLL_SCRB 0xf2090008
1461#define F367TER_LL_SCRB 0xf2090004
1462#define F367TER_SCRALLBAD 0xf2090002
1463#define F367TER_SCRALL_UNSYNC 0xf2090001
1464
1465/* RCOBSCFG */
1466#define R367TER_RCOBSCFG 0xf20a
1467#define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff
1468
1469/* RCOBSM */
1470#define R367TER_RCOBSM 0xf20b
1471#define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff
1472
1473/* RCOBSL */
1474#define R367TER_RCOBSL 0xf20c
1475#define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff
1476
1477/* RCFECSPY */
1478#define R367TER_RCFECSPY 0xf210
1479#define F367TER_SPYRC_ENABLE 0xf2100080
1480#define F367TER_RCNO_SYNCBYTE 0xf2100040
1481#define F367TER_RCSERIAL_MODE 0xf2100020
1482#define F367TER_RCUNUSUAL_PACKET 0xf2100010
1483#define F367TER_BERRCMETER_DATAMODE 0xf210000c
1484#define F367TER_BERRCMETER_LMODE 0xf2100002
1485#define F367TER_BERRCMETER_RESET 0xf2100001
1486
1487/* RCFSPYCFG */
1488#define R367TER_RCFSPYCFG 0xf211
1489#define F367TER_FECSPYRC_INPUT 0xf21100c0
1490#define F367TER_RCRST_ON_ERROR 0xf2110020
1491#define F367TER_RCONE_SHOT 0xf2110010
1492#define F367TER_RCI2C_MODE 0xf211000c
1493#define F367TER_SPYRC_HSTERESIS 0xf2110003
1494
1495/* RCFSPYDATA */
1496#define R367TER_RCFSPYDATA 0xf212
1497#define F367TER_SPYRC_STUFFING 0xf2120080
1498#define F367TER_RCNOERR_PKTJITTER 0xf2120040
1499#define F367TER_SPYRC_CNULLPKT 0xf2120020
1500#define F367TER_SPYRC_OUTDATA_MODE 0xf212001f
1501
1502/* RCFSPYOUT */
1503#define R367TER_RCFSPYOUT 0xf213
1504#define F367TER_FSPYRC_DIRECT 0xf2130080
1505#define F367TER_RCFSPYOUT_6 0xf2130040
1506#define F367TER_SPYRC_OUTDATA_BUS 0xf2130038
1507#define F367TER_RCSTUFF_MODE 0xf2130007
1508
1509/* RCFSTATUS */
1510#define R367TER_RCFSTATUS 0xf214
1511#define F367TER_SPYRC_ENDSIM 0xf2140080
1512#define F367TER_RCVALID_SIM 0xf2140040
1513#define F367TER_RCFOUND_SIGNAL 0xf2140020
1514#define F367TER_RCDSS_SYNCBYTE 0xf2140010
1515#define F367TER_RCRESULT_STATE 0xf214000f
1516
1517/* RCFGOODPACK */
1518#define R367TER_RCFGOODPACK 0xf215
1519#define F367TER_RCGOOD_PACKET 0xf21500ff
1520
1521/* RCFPACKCNT */
1522#define R367TER_RCFPACKCNT 0xf216
1523#define F367TER_RCPACKET_COUNTER 0xf21600ff
1524
1525/* RCFSPYMISC */
1526#define R367TER_RCFSPYMISC 0xf217
1527#define F367TER_RCLABEL_COUNTER 0xf21700ff
1528
1529/* RCFBERCPT4 */
1530#define R367TER_RCFBERCPT4 0xf218
1531#define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff
1532
1533/* RCFBERCPT3 */
1534#define R367TER_RCFBERCPT3 0xf219
1535#define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff
1536
1537/* RCFBERCPT2 */
1538#define R367TER_RCFBERCPT2 0xf21a
1539#define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff
1540
1541/* RCFBERCPT1 */
1542#define R367TER_RCFBERCPT1 0xf21b
1543#define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff
1544
1545/* RCFBERCPT0 */
1546#define R367TER_RCFBERCPT0 0xf21c
1547#define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff
1548
1549/* RCFBERERR2 */
1550#define R367TER_RCFBERERR2 0xf21d
1551#define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff
1552
1553/* RCFBERERR1 */
1554#define R367TER_RCFBERERR1 0xf21e
1555#define F367TER_FBERRCMETER_ERR 0xf21e00ff
1556
1557/* RCFBERERR0 */
1558#define R367TER_RCFBERERR0 0xf21f
1559#define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff
1560
1561/* RCFSTATESM */
1562#define R367TER_RCFSTATESM 0xf220
1563#define F367TER_RCRSTATE_F 0xf2200080
1564#define F367TER_RCRSTATE_E 0xf2200040
1565#define F367TER_RCRSTATE_D 0xf2200020
1566#define F367TER_RCRSTATE_C 0xf2200010
1567#define F367TER_RCRSTATE_B 0xf2200008
1568#define F367TER_RCRSTATE_A 0xf2200004
1569#define F367TER_RCRSTATE_9 0xf2200002
1570#define F367TER_RCRSTATE_8 0xf2200001
1571
1572/* RCFSTATESL */
1573#define R367TER_RCFSTATESL 0xf221
1574#define F367TER_RCRSTATE_7 0xf2210080
1575#define F367TER_RCRSTATE_6 0xf2210040
1576#define F367TER_RCRSTATE_5 0xf2210020
1577#define F367TER_RCRSTATE_4 0xf2210010
1578#define F367TER_RCRSTATE_3 0xf2210008
1579#define F367TER_RCRSTATE_2 0xf2210004
1580#define F367TER_RCRSTATE_1 0xf2210002
1581#define F367TER_RCRSTATE_0 0xf2210001
1582
1583/* RCFSPYBER */
1584#define R367TER_RCFSPYBER 0xf222
1585#define F367TER_RCFSPYBER_7 0xf2220080
1586#define F367TER_SPYRCOBS_XORREAD 0xf2220040
1587#define F367TER_FSPYRCBER_OBSMODE 0xf2220020
1588#define F367TER_FSPYRCBER_SYNCBYT 0xf2220010
1589#define F367TER_FSPYRCBER_UNSYNC 0xf2220008
1590#define F367TER_FSPYRCBER_CTIME 0xf2220007
1591
1592/* RCFSPYDISTM */
1593#define R367TER_RCFSPYDISTM 0xf223
1594#define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff
1595
1596/* RCFSPYDISTL */
1597#define R367TER_RCFSPYDISTL 0xf224
1598#define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff
1599
1600/* RCFSPYOBS7 */
1601#define R367TER_RCFSPYOBS7 0xf228
1602#define F367TER_RCSPYOBS_SPYFAIL 0xf2280080
1603#define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040
1604#define F367TER_RCSPYOBS_ERROR 0xf2280020
1605#define F367TER_RCSPYOBS_STROUT 0xf2280010
1606#define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f
1607
1608/* RCFSPYOBS6 */
1609#define R367TER_RCFSPYOBS6 0xf229
1610#define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0
1611#define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f
1612
1613/* RCFSPYOBS5 */
1614#define R367TER_RCFSPYOBS5 0xf22a
1615#define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff
1616
1617/* RCFSPYOBS4 */
1618#define R367TER_RCFSPYOBS4 0xf22b
1619#define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff
1620
1621/* RCFSPYOBS3 */
1622#define R367TER_RCFSPYOBS3 0xf22c
1623#define F367TER_RCSPYOBS_DATA1 0xf22c00ff
1624
1625/* RCFSPYOBS2 */
1626#define R367TER_RCFSPYOBS2 0xf22d
1627#define F367TER_RCSPYOBS_DATa0 0xf22d00ff
1628
1629/* RCFSPYOBS1 */
1630#define R367TER_RCFSPYOBS1 0xf22e
1631#define F367TER_RCSPYOBS_DATAM1 0xf22e00ff
1632
1633/* RCFSPYOBS0 */
1634#define R367TER_RCFSPYOBS0 0xf22f
1635#define F367TER_RCSPYOBS_DATAM2 0xf22f00ff
1636
1637/* TSGENERAL */
1638#define R367TER_TSGENERAL 0xf230
1639#define F367TER_TSGENERAL_7 0xf2300080
1640#define F367TER_TSGENERAL_6 0xf2300040
1641#define F367TER_TSFIFO_BCLK1aLL 0xf2300020
1642#define F367TER_TSGENERAL_4 0xf2300010
1643#define F367TER_MUXSTREAM_OUTMODE 0xf2300008
1644#define F367TER_TSFIFO_PERMPARAL 0xf2300006
1645#define F367TER_RST_REEDSOLO 0xf2300001
1646
1647/* RC1SPEED */
1648#define R367TER_RC1SPEED 0xf231
1649#define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff
1650
1651/* TSGSTATUS */
1652#define R367TER_TSGSTATUS 0xf232
1653#define F367TER_TSGSTATUS_7 0xf2320080
1654#define F367TER_TSGSTATUS_6 0xf2320040
1655#define F367TER_RSMEM_FULL 0xf2320020
1656#define F367TER_RS_MULTCALC 0xf2320010
1657#define F367TER_RSIN_OVERTIME 0xf2320008
1658#define F367TER_TSFIFO3_DEMODSEL 0xf2320004
1659#define F367TER_TSFIFO2_DEMODSEL 0xf2320002
1660#define F367TER_TSFIFO1_DEMODSEL 0xf2320001
1661
1662
1663/* FECM */
1664#define R367TER_FECM 0xf233
1665#define F367TER_DSS_DVB 0xf2330080
1666#define F367TER_DEMOD_BYPASS 0xf2330040
1667#define F367TER_CMP_SLOWMODE 0xf2330020
1668#define F367TER_DSS_SRCH 0xf2330010
1669#define F367TER_FECM_3 0xf2330008
1670#define F367TER_DIFF_MODEVIT 0xf2330004
1671#define F367TER_SYNCVIT 0xf2330002
1672#define F367TER_I2CSYM 0xf2330001
1673
1674/* VTH12 */
1675#define R367TER_VTH12 0xf234
1676#define F367TER_VTH_12 0xf23400ff
1677
1678/* VTH23 */
1679#define R367TER_VTH23 0xf235
1680#define F367TER_VTH_23 0xf23500ff
1681
1682/* VTH34 */
1683#define R367TER_VTH34 0xf236
1684#define F367TER_VTH_34 0xf23600ff
1685
1686/* VTH56 */
1687#define R367TER_VTH56 0xf237
1688#define F367TER_VTH_56 0xf23700ff
1689
1690/* VTH67 */
1691#define R367TER_VTH67 0xf238
1692#define F367TER_VTH_67 0xf23800ff
1693
1694/* VTH78 */
1695#define R367TER_VTH78 0xf239
1696#define F367TER_VTH_78 0xf23900ff
1697
1698/* VITCURPUN */
1699#define R367TER_VITCURPUN 0xf23a
1700#define F367TER_VIT_MAPPING 0xf23a00e0
1701#define F367TER_VIT_CURPUN 0xf23a001f
1702
1703/* VERROR */
1704#define R367TER_VERROR 0xf23b
1705#define F367TER_REGERR_VIT 0xf23b00ff
1706
1707/* PRVIT */
1708#define R367TER_PRVIT 0xf23c
1709#define F367TER_PRVIT_7 0xf23c0080
1710#define F367TER_DIS_VTHLOCK 0xf23c0040
1711#define F367TER_E7_8VIT 0xf23c0020
1712#define F367TER_E6_7VIT 0xf23c0010
1713#define F367TER_E5_6VIT 0xf23c0008
1714#define F367TER_E3_4VIT 0xf23c0004
1715#define F367TER_E2_3VIT 0xf23c0002
1716#define F367TER_E1_2VIT 0xf23c0001
1717
1718/* VAVSRVIT */
1719#define R367TER_VAVSRVIT 0xf23d
1720#define F367TER_AMVIT 0xf23d0080
1721#define F367TER_FROZENVIT 0xf23d0040
1722#define F367TER_SNVIT 0xf23d0030
1723#define F367TER_TOVVIT 0xf23d000c
1724#define F367TER_HYPVIT 0xf23d0003
1725
1726/* VSTATUSVIT */
1727#define R367TER_VSTATUSVIT 0xf23e
1728#define F367TER_VITERBI_ON 0xf23e0080
1729#define F367TER_END_LOOPVIT 0xf23e0040
1730#define F367TER_VITERBI_DEPRF 0xf23e0020
1731#define F367TER_PRFVIT 0xf23e0010
1732#define F367TER_LOCKEDVIT 0xf23e0008
1733#define F367TER_VITERBI_DELOCK 0xf23e0004
1734#define F367TER_VIT_DEMODSEL 0xf23e0002
1735#define F367TER_VITERBI_COMPOUT 0xf23e0001
1736
1737/* VTHINUSE */
1738#define R367TER_VTHINUSE 0xf23f
1739#define F367TER_VIT_INUSE 0xf23f00ff
1740
1741/* KDIV12 */
1742#define R367TER_KDIV12 0xf240
1743#define F367TER_KDIV12_MANUAL 0xf2400080
1744#define F367TER_K_DIVIDER_12 0xf240007f
1745
1746/* KDIV23 */
1747#define R367TER_KDIV23 0xf241
1748#define F367TER_KDIV23_MANUAL 0xf2410080
1749#define F367TER_K_DIVIDER_23 0xf241007f
1750
1751/* KDIV34 */
1752#define R367TER_KDIV34 0xf242
1753#define F367TER_KDIV34_MANUAL 0xf2420080
1754#define F367TER_K_DIVIDER_34 0xf242007f
1755
1756/* KDIV56 */
1757#define R367TER_KDIV56 0xf243
1758#define F367TER_KDIV56_MANUAL 0xf2430080
1759#define F367TER_K_DIVIDER_56 0xf243007f
1760
1761/* KDIV67 */
1762#define R367TER_KDIV67 0xf244
1763#define F367TER_KDIV67_MANUAL 0xf2440080
1764#define F367TER_K_DIVIDER_67 0xf244007f
1765
1766/* KDIV78 */
1767#define R367TER_KDIV78 0xf245
1768#define F367TER_KDIV78_MANUAL 0xf2450080
1769#define F367TER_K_DIVIDER_78 0xf245007f
1770
1771/* SIGPOWER */
1772#define R367TER_SIGPOWER 0xf246
1773#define F367TER_SIGPOWER_MANUAL 0xf2460080
1774#define F367TER_SIG_POWER 0xf246007f
1775
1776/* DEMAPVIT */
1777#define R367TER_DEMAPVIT 0xf247
1778#define F367TER_DEMAPVIT_7 0xf2470080
1779#define F367TER_K_DIVIDER_VIT 0xf247007f
1780
1781/* VITSCALE */
1782#define R367TER_VITSCALE 0xf248
1783#define F367TER_NVTH_NOSRANGE 0xf2480080
1784#define F367TER_VERROR_MAXMODE 0xf2480040
1785#define F367TER_KDIV_MODE 0xf2480030
1786#define F367TER_NSLOWSN_LOCKED 0xf2480008
1787#define F367TER_DELOCK_PRFLOSS 0xf2480004
1788#define F367TER_DIS_RSFLOCK 0xf2480002
1789#define F367TER_VITSCALE_0 0xf2480001
1790
1791/* FFEC1PRG */
1792#define R367TER_FFEC1PRG 0xf249
1793#define F367TER_FDSS_DVB 0xf2490080
1794#define F367TER_FDSS_SRCH 0xf2490040
1795#define F367TER_FFECPROG_5 0xf2490020
1796#define F367TER_FFECPROG_4 0xf2490010
1797#define F367TER_FFECPROG_3 0xf2490008
1798#define F367TER_FFECPROG_2 0xf2490004
1799#define F367TER_FTS1_DISABLE 0xf2490002
1800#define F367TER_FTS2_DISABLE 0xf2490001
1801
1802/* FVITCURPUN */
1803#define R367TER_FVITCURPUN 0xf24a
1804#define F367TER_FVIT_MAPPING 0xf24a00e0
1805#define F367TER_FVIT_CURPUN 0xf24a001f
1806
1807/* FVERROR */
1808#define R367TER_FVERROR 0xf24b
1809#define F367TER_FREGERR_VIT 0xf24b00ff
1810
1811/* FVSTATUSVIT */
1812#define R367TER_FVSTATUSVIT 0xf24c
1813#define F367TER_FVITERBI_ON 0xf24c0080
1814#define F367TER_F1END_LOOPVIT 0xf24c0040
1815#define F367TER_FVITERBI_DEPRF 0xf24c0020
1816#define F367TER_FPRFVIT 0xf24c0010
1817#define F367TER_FLOCKEDVIT 0xf24c0008
1818#define F367TER_FVITERBI_DELOCK 0xf24c0004
1819#define F367TER_FVIT_DEMODSEL 0xf24c0002
1820#define F367TER_FVITERBI_COMPOUT 0xf24c0001
1821
1822/* DEBUG_LT1 */
1823#define R367TER_DEBUG_LT1 0xf24d
1824#define F367TER_DBG_LT1 0xf24d00ff
1825
1826/* DEBUG_LT2 */
1827#define R367TER_DEBUG_LT2 0xf24e
1828#define F367TER_DBG_LT2 0xf24e00ff
1829
1830/* DEBUG_LT3 */
1831#define R367TER_DEBUG_LT3 0xf24f
1832#define F367TER_DBG_LT3 0xf24f00ff
1833
1834/* TSTSFMET */
1835#define R367TER_TSTSFMET 0xf250
1836#define F367TER_TSTSFEC_METRIQUES 0xf25000ff
1837
1838/* SELOUT */
1839#define R367TER_SELOUT 0xf252
1840#define F367TER_EN_SYNC 0xf2520080
1841#define F367TER_EN_TBUSDEMAP 0xf2520040
1842#define F367TER_SELOUT_5 0xf2520020
1843#define F367TER_SELOUT_4 0xf2520010
1844#define F367TER_TSTSYNCHRO_MODE 0xf2520002
1845
1846/* TSYNC */
1847#define R367TER_TSYNC 0xf253
1848#define F367TER_CURPUN_INCMODE 0xf2530080
1849#define F367TER_CERR_TSTMODE 0xf2530040
1850#define F367TER_SHIFTSOF_MODE 0xf2530030
1851#define F367TER_SLOWPHA_MODE 0xf2530008
1852#define F367TER_PXX_BYPALL 0xf2530004
1853#define F367TER_FROTA45_FIRST 0xf2530002
1854#define F367TER_TST_BCHERROR 0xf2530001
1855
1856/* TSTERR */
1857#define R367TER_TSTERR 0xf254
1858#define F367TER_TST_LONGPKT 0xf2540080
1859#define F367TER_TST_ISSYION 0xf2540040
1860#define F367TER_TST_NPDON 0xf2540020
1861#define F367TER_TSTERR_4 0xf2540010
1862#define F367TER_TRACEBACK_MODE 0xf2540008
1863#define F367TER_TST_RSPARITY 0xf2540004
1864#define F367TER_METRIQUE_MODE 0xf2540003
1865
1866/* TSFSYNC */
1867#define R367TER_TSFSYNC 0xf255
1868#define F367TER_EN_SFECSYNC 0xf2550080
1869#define F367TER_EN_SFECDEMAP 0xf2550040
1870#define F367TER_SFCERR_TSTMODE 0xf2550020
1871#define F367TER_SFECPXX_BYPALL 0xf2550010
1872#define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f
1873
1874/* TSTSFERR */
1875#define R367TER_TSTSFERR 0xf256
1876#define F367TER_TSTSTERR_7 0xf2560080
1877#define F367TER_TSTSTERR_6 0xf2560040
1878#define F367TER_TSTSTERR_5 0xf2560020
1879#define F367TER_TSTSTERR_4 0xf2560010
1880#define F367TER_SFECTRACEBACK_MODE 0xf2560008
1881#define F367TER_SFEC_NCONVPROG 0xf2560004
1882#define F367TER_SFECMETRIQUE_MODE 0xf2560003
1883
1884/* TSTTSSF1 */
1885#define R367TER_TSTTSSF1 0xf258
1886#define F367TER_TSTERSSF 0xf2580080
1887#define F367TER_TSTTSSFEN 0xf2580040
1888#define F367TER_SFEC_OUTMODE 0xf2580030
1889#define F367TER_XLSF_NOFTHRESHOLD 0xf2580008
1890#define F367TER_TSTTSSF_STACKSEL 0xf2580007
1891
1892/* TSTTSSF2 */
1893#define R367TER_TSTTSSF2 0xf259
1894#define F367TER_DILSF_DBBHEADER 0xf2590080
1895#define F367TER_TSTTSSF_DISBUG 0xf2590040
1896#define F367TER_TSTTSSF_NOBADSTART 0xf2590020
1897#define F367TER_TSTTSSF_SELECT 0xf259001f
1898
1899/* TSTTSSF3 */
1900#define R367TER_TSTTSSF3 0xf25a
1901#define F367TER_TSTTSSF3_7 0xf25a0080
1902#define F367TER_TSTTSSF3_6 0xf25a0040
1903#define F367TER_TSTTSSF3_5 0xf25a0020
1904#define F367TER_TSTTSSF3_4 0xf25a0010
1905#define F367TER_TSTTSSF3_3 0xf25a0008
1906#define F367TER_TSTTSSF3_2 0xf25a0004
1907#define F367TER_TSTTSSF3_1 0xf25a0002
1908#define F367TER_DISSF_CLKENABLE 0xf25a0001
1909
1910/* TSTTS1 */
1911#define R367TER_TSTTS1 0xf25c
1912#define F367TER_TSTERS 0xf25c0080
1913#define F367TER_TSFIFO_DSSSYNCB 0xf25c0040
1914#define F367TER_TSTTS_FSPYBEFRS 0xf25c0020
1915#define F367TER_NFORCE_SYNCBYTE 0xf25c0010
1916#define F367TER_XL_NOFTHRESHOLD 0xf25c0008
1917#define F367TER_TSTTS_FRFORCEPKT 0xf25c0004
1918#define F367TER_DESCR_NOTAUTO 0xf25c0002
1919#define F367TER_TSTTSEN 0xf25c0001
1920
1921/* TSTTS2 */
1922#define R367TER_TSTTS2 0xf25d
1923#define F367TER_DIL_DBBHEADER 0xf25d0080
1924#define F367TER_TSTTS_NOBADXXX 0xf25d0040
1925#define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020
1926#define F367TER_TSTTS_SELECT 0xf25d001f
1927
1928/* TSTTS3 */
1929#define R367TER_TSTTS3 0xf25e
1930#define F367TER_TSTTS_NOPKTGAIN 0xf25e0080
1931#define F367TER_TSTTS_NOPKTENE 0xf25e0040
1932#define F367TER_TSTTS_ISOLATION 0xf25e0020
1933#define F367TER_TSTTS_DISBUG 0xf25e0010
1934#define F367TER_TSTTS_NOBADSTART 0xf25e0008
1935#define F367TER_TSTTS_STACKSEL 0xf25e0007
1936
1937/* TSTTS4 */
1938#define R367TER_TSTTS4 0xf25f
1939#define F367TER_TSTTS4_7 0xf25f0080
1940#define F367TER_TSTTS4_6 0xf25f0040
1941#define F367TER_TSTTS4_5 0xf25f0020
1942#define F367TER_TSTTS_DISDSTATE 0xf25f0010
1943#define F367TER_TSTTS_FASTNOSYNC 0xf25f0008
1944#define F367TER_EXT_FECSPYIN 0xf25f0004
1945#define F367TER_TSTTS_NODPZERO 0xf25f0002
1946#define F367TER_TSTTS_NODIV3 0xf25f0001
1947
1948/* TSTTSRC */
1949#define R367TER_TSTTSRC 0xf26c
1950#define F367TER_TSTTSRC_7 0xf26c0080
1951#define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040
1952#define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020
1953#define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010
1954#define F367TER_TSTTSRC_NODIV3 0xf26c0008
1955#define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004
1956#define F367TER_SAT25_SDDORIGINE 0xf26c0002
1957#define F367TER_TSTTSRC_INACTIVE 0xf26c0001
1958
1959/* TSTTSRS */
1960#define R367TER_TSTTSRS 0xf26d
1961#define F367TER_TSTTSRS_7 0xf26d0080
1962#define F367TER_TSTTSRS_6 0xf26d0040
1963#define F367TER_TSTTSRS_5 0xf26d0020
1964#define F367TER_TSTTSRS_4 0xf26d0010
1965#define F367TER_TSTTSRS_3 0xf26d0008
1966#define F367TER_TSTTSRS_2 0xf26d0004
1967#define F367TER_TSTRS_DISRS2 0xf26d0002
1968#define F367TER_TSTRS_DISRS1 0xf26d0001
1969
1970/* TSSTATEM */
1971#define R367TER_TSSTATEM 0xf270
1972#define F367TER_TSDIL_ON 0xf2700080
1973#define F367TER_TSSKIPRS_ON 0xf2700040
1974#define F367TER_TSRS_ON 0xf2700020
1975#define F367TER_TSDESCRAMB_ON 0xf2700010
1976#define F367TER_TSFRAME_MODE 0xf2700008
1977#define F367TER_TS_DISABLE 0xf2700004
1978#define F367TER_TSACM_MODE 0xf2700002
1979#define F367TER_TSOUT_NOSYNC 0xf2700001
1980
1981/* TSSTATEL */
1982#define R367TER_TSSTATEL 0xf271
1983#define F367TER_TSNOSYNCBYTE 0xf2710080
1984#define F367TER_TSPARITY_ON 0xf2710040
1985#define F367TER_TSSYNCOUTRS_ON 0xf2710020
1986#define F367TER_TSDVBS2_MODE 0xf2710010
1987#define F367TER_TSISSYI_ON 0xf2710008
1988#define F367TER_TSNPD_ON 0xf2710004
1989#define F367TER_TSCRC8_ON 0xf2710002
1990#define F367TER_TSDSS_PACKET 0xf2710001
1991
1992/* TSCFGH */
1993#define R367TER_TSCFGH 0xf272
1994#define F367TER_TSFIFO_DVBCI 0xf2720080
1995#define F367TER_TSFIFO_SERIAL 0xf2720040
1996#define F367TER_TSFIFO_TEIUPDATE 0xf2720020
1997#define F367TER_TSFIFO_DUTY50 0xf2720010
1998#define F367TER_TSFIFO_HSGNLOUT 0xf2720008
1999#define F367TER_TSFIFO_ERRMODE 0xf2720006
2000#define F367TER_RST_HWARE 0xf2720001
2001
2002/* TSCFGM */
2003#define R367TER_TSCFGM 0xf273
2004#define F367TER_TSFIFO_MANSPEED 0xf27300c0
2005#define F367TER_TSFIFO_PERMDATA 0xf2730020
2006#define F367TER_TSFIFO_NONEWSGNL 0xf2730010
2007#define F367TER_TSFIFO_BITSPEED 0xf2730008
2008#define F367TER_NPD_SPECDVBS2 0xf2730004
2009#define F367TER_TSFIFO_STOPCKDIS 0xf2730002
2010#define F367TER_TSFIFO_INVDATA 0xf2730001
2011
2012/* TSCFGL */
2013#define R367TER_TSCFGL 0xf274
2014#define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0
2015#define F367TER_BCHERROR_MODE 0xf2740030
2016#define F367TER_TSFIFO_NSGNL2dATA 0xf2740008
2017#define F367TER_TSFIFO_EMBINDVB 0xf2740004
2018#define F367TER_TSFIFO_DPUNACT 0xf2740002
2019#define F367TER_TSFIFO_NPDOFF 0xf2740001
2020
2021/* TSSYNC */
2022#define R367TER_TSSYNC 0xf275
2023#define F367TER_TSFIFO_PERMUTE 0xf2750080
2024#define F367TER_TSFIFO_FISCR3B 0xf2750060
2025#define F367TER_TSFIFO_SYNCMODE 0xf2750018
2026#define F367TER_TSFIFO_SYNCSEL 0xf2750007
2027
2028/* TSINSDELH */
2029#define R367TER_TSINSDELH 0xf276
2030#define F367TER_TSDEL_SYNCBYTE 0xf2760080
2031#define F367TER_TSDEL_XXHEADER 0xf2760040
2032#define F367TER_TSDEL_BBHEADER 0xf2760020
2033#define F367TER_TSDEL_DATAFIELD 0xf2760010
2034#define F367TER_TSINSDEL_ISCR 0xf2760008
2035#define F367TER_TSINSDEL_NPD 0xf2760004
2036#define F367TER_TSINSDEL_RSPARITY 0xf2760002
2037#define F367TER_TSINSDEL_CRC8 0xf2760001
2038
2039/* TSINSDELM */
2040#define R367TER_TSINSDELM 0xf277
2041#define F367TER_TSINS_BBPADDING 0xf2770080
2042#define F367TER_TSINS_BCHFEC 0xf2770040
2043#define F367TER_TSINS_LDPCFEC 0xf2770020
2044#define F367TER_TSINS_EMODCOD 0xf2770010
2045#define F367TER_TSINS_TOKEN 0xf2770008
2046#define F367TER_TSINS_XXXERR 0xf2770004
2047#define F367TER_TSINS_MATYPE 0xf2770002
2048#define F367TER_TSINS_UPL 0xf2770001
2049
2050/* TSINSDELL */
2051#define R367TER_TSINSDELL 0xf278
2052#define F367TER_TSINS_DFL 0xf2780080
2053#define F367TER_TSINS_SYNCD 0xf2780040
2054#define F367TER_TSINS_BLOCLEN 0xf2780020
2055#define F367TER_TSINS_SIGPCOUNT 0xf2780010
2056#define F367TER_TSINS_FIFO 0xf2780008
2057#define F367TER_TSINS_REALPACK 0xf2780004
2058#define F367TER_TSINS_TSCONFIG 0xf2780002
2059#define F367TER_TSINS_LATENCY 0xf2780001
2060
2061/* TSDIVN */
2062#define R367TER_TSDIVN 0xf279
2063#define F367TER_TSFIFO_LOWSPEED 0xf2790080
2064#define F367TER_BYTE_OVERSAMPLING 0xf2790070
2065#define F367TER_TSMANUAL_PACKETNBR 0xf279000f
2066
2067/* TSDIVPM */
2068#define R367TER_TSDIVPM 0xf27a
2069#define F367TER_TSMANUAL_P_HI 0xf27a00ff
2070
2071/* TSDIVPL */
2072#define R367TER_TSDIVPL 0xf27b
2073#define F367TER_TSMANUAL_P_LO 0xf27b00ff
2074
2075/* TSDIVQM */
2076#define R367TER_TSDIVQM 0xf27c
2077#define F367TER_TSMANUAL_Q_HI 0xf27c00ff
2078
2079/* TSDIVQL */
2080#define R367TER_TSDIVQL 0xf27d
2081#define F367TER_TSMANUAL_Q_LO 0xf27d00ff
2082
2083/* TSDILSTKM */
2084#define R367TER_TSDILSTKM 0xf27e
2085#define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff
2086
2087/* TSDILSTKL */
2088#define R367TER_TSDILSTKL 0xf27f
2089#define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff
2090
2091/* TSSPEED */
2092#define R367TER_TSSPEED 0xf280
2093#define F367TER_TSFIFO_OUTSPEED 0xf28000ff
2094
2095/* TSSTATUS */
2096#define R367TER_TSSTATUS 0xf281
2097#define F367TER_TSFIFO_LINEOK 0xf2810080
2098#define F367TER_TSFIFO_ERROR 0xf2810040
2099#define F367TER_TSFIFO_DATA7 0xf2810020
2100#define F367TER_TSFIFO_NOSYNC 0xf2810010
2101#define F367TER_ISCR_INITIALIZED 0xf2810008
2102#define F367TER_ISCR_UPDATED 0xf2810004
2103#define F367TER_SOFFIFO_UNREGUL 0xf2810002
2104#define F367TER_DIL_READY 0xf2810001
2105
2106/* TSSTATUS2 */
2107#define R367TER_TSSTATUS2 0xf282
2108#define F367TER_TSFIFO_DEMODSEL 0xf2820080
2109#define F367TER_TSFIFOSPEED_STORE 0xf2820040
2110#define F367TER_DILXX_RESET 0xf2820020
2111#define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010
2112#define F367TER_TSFIFO_UNDERSPEED 0xf2820008
2113#define F367TER_BITSPEED_EVENT 0xf2820004
2114#define F367TER_UL_SCRAMBDETECT 0xf2820002
2115#define F367TER_ULDTV67_FALSELOCK 0xf2820001
2116
2117/* TSBITRATEM */
2118#define R367TER_TSBITRATEM 0xf283
2119#define F367TER_TSFIFO_BITRATE_HI 0xf28300ff
2120
2121/* TSBITRATEL */
2122#define R367TER_TSBITRATEL 0xf284
2123#define F367TER_TSFIFO_BITRATE_LO 0xf28400ff
2124
2125/* TSPACKLENM */
2126#define R367TER_TSPACKLENM 0xf285
2127#define F367TER_TSFIFO_PACKCPT 0xf28500e0
2128#define F367TER_DIL_RPLEN_HI 0xf285001f
2129
2130/* TSPACKLENL */
2131#define R367TER_TSPACKLENL 0xf286
2132#define F367TER_DIL_RPLEN_LO 0xf28600ff
2133
2134/* TSBLOCLENM */
2135#define R367TER_TSBLOCLENM 0xf287
2136#define F367TER_TSFIFO_PFLEN_HI 0xf28700ff
2137
2138/* TSBLOCLENL */
2139#define R367TER_TSBLOCLENL 0xf288
2140#define F367TER_TSFIFO_PFLEN_LO 0xf28800ff
2141
2142/* TSDLYH */
2143#define R367TER_TSDLYH 0xf289
2144#define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080
2145#define F367TER_SOFFIFO_SPEEDUP 0xf2890040
2146#define F367TER_SOFFIFO_STOP 0xf2890020
2147#define F367TER_SOFFIFO_REGULATED 0xf2890010
2148#define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f
2149
2150/* TSDLYM */
2151#define R367TER_TSDLYM 0xf28a
2152#define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff
2153
2154/* TSDLYL */
2155#define R367TER_TSDLYL 0xf28b
2156#define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff
2157
2158/* TSNPDAV */
2159#define R367TER_TSNPDAV 0xf28c
2160#define F367TER_TSNPD_AVERAGE 0xf28c00ff
2161
2162/* TSBUFSTATH */
2163#define R367TER_TSBUFSTATH 0xf28d
2164#define F367TER_TSISCR_3BYTES 0xf28d0080
2165#define F367TER_TSISCR_NEWDATA 0xf28d0040
2166#define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f
2167
2168/* TSBUFSTATM */
2169#define R367TER_TSBUFSTATM 0xf28e
2170#define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff
2171
2172/* TSBUFSTATL */
2173#define R367TER_TSBUFSTATL 0xf28f
2174#define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff
2175
2176/* TSDEBUGM */
2177#define R367TER_TSDEBUGM 0xf290
2178#define F367TER_TSFIFO_ILLPACKET 0xf2900080
2179#define F367TER_DIL_NOSYNC 0xf2900040
2180#define F367TER_DIL_ISCR 0xf2900020
2181#define F367TER_DILOUT_BSYNCB 0xf2900010
2182#define F367TER_TSFIFO_EMPTYPKT 0xf2900008
2183#define F367TER_TSFIFO_EMPTYRD 0xf2900004
2184#define F367TER_SOFFIFO_STOPM 0xf2900002
2185#define F367TER_SOFFIFO_SPEEDUPM 0xf2900001
2186
2187/* TSDEBUGL */
2188#define R367TER_TSDEBUGL 0xf291
2189#define F367TER_TSFIFO_PACKLENFAIL 0xf2910080
2190#define F367TER_TSFIFO_SYNCBFAIL 0xf2910040
2191#define F367TER_TSFIFO_VITLIBRE 0xf2910020
2192#define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010
2193#define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008
2194#define F367TER_TSFIFO_ERROR_EVNT 0xf2910004
2195#define F367TER_TSFIFO_FULL 0xf2910002
2196#define F367TER_TSFIFO_OVERFLOWM 0xf2910001
2197
2198/* TSDLYSETH */
2199#define R367TER_TSDLYSETH 0xf292
2200#define F367TER_SOFFIFO_OFFSET 0xf29200e0
2201#define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f
2202
2203/* TSDLYSETM */
2204#define R367TER_TSDLYSETM 0xf293
2205#define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff
2206
2207/* TSDLYSETL */
2208#define R367TER_TSDLYSETL 0xf294
2209#define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff
2210
2211/* TSOBSCFG */
2212#define R367TER_TSOBSCFG 0xf295
2213#define F367TER_TSFIFO_OBSCFG 0xf29500ff
2214
2215/* TSOBSM */
2216#define R367TER_TSOBSM 0xf296
2217#define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff
2218
2219/* TSOBSL */
2220#define R367TER_TSOBSL 0xf297
2221#define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff
2222
2223/* ERRCTRL1 */
2224#define R367TER_ERRCTRL1 0xf298
2225#define F367TER_ERR_SRC1 0xf29800f0
2226#define F367TER_ERRCTRL1_3 0xf2980008
2227#define F367TER_NUM_EVT1 0xf2980007
2228
2229/* ERRCNT1H */
2230#define R367TER_ERRCNT1H 0xf299
2231#define F367TER_ERRCNT1_OLDVALUE 0xf2990080
2232#define F367TER_ERR_CNT1 0xf299007f
2233
2234/* ERRCNT1M */
2235#define R367TER_ERRCNT1M 0xf29a
2236#define F367TER_ERR_CNT1_HI 0xf29a00ff
2237
2238/* ERRCNT1L */
2239#define R367TER_ERRCNT1L 0xf29b
2240#define F367TER_ERR_CNT1_LO 0xf29b00ff
2241
2242/* ERRCTRL2 */
2243#define R367TER_ERRCTRL2 0xf29c
2244#define F367TER_ERR_SRC2 0xf29c00f0
2245#define F367TER_ERRCTRL2_3 0xf29c0008
2246#define F367TER_NUM_EVT2 0xf29c0007
2247
2248/* ERRCNT2H */
2249#define R367TER_ERRCNT2H 0xf29d
2250#define F367TER_ERRCNT2_OLDVALUE 0xf29d0080
2251#define F367TER_ERR_CNT2_HI 0xf29d007f
2252
2253/* ERRCNT2M */
2254#define R367TER_ERRCNT2M 0xf29e
2255#define F367TER_ERR_CNT2_MED 0xf29e00ff
2256
2257/* ERRCNT2L */
2258#define R367TER_ERRCNT2L 0xf29f
2259#define F367TER_ERR_CNT2_LO 0xf29f00ff
2260
2261/* FECSPY */
2262#define R367TER_FECSPY 0xf2a0
2263#define F367TER_SPY_ENABLE 0xf2a00080
2264#define F367TER_NO_SYNCBYTE 0xf2a00040
2265#define F367TER_SERIAL_MODE 0xf2a00020
2266#define F367TER_UNUSUAL_PACKET 0xf2a00010
2267#define F367TER_BERMETER_DATAMODE 0xf2a0000c
2268#define F367TER_BERMETER_LMODE 0xf2a00002
2269#define F367TER_BERMETER_RESET 0xf2a00001
2270
2271/* FSPYCFG */
2272#define R367TER_FSPYCFG 0xf2a1
2273#define F367TER_FECSPY_INPUT 0xf2a100c0
2274#define F367TER_RST_ON_ERROR 0xf2a10020
2275#define F367TER_ONE_SHOT 0xf2a10010
2276#define F367TER_I2C_MOD 0xf2a1000c
2277#define F367TER_SPY_HYSTERESIS 0xf2a10003
2278
2279/* FSPYDATA */
2280#define R367TER_FSPYDATA 0xf2a2
2281#define F367TER_SPY_STUFFING 0xf2a20080
2282#define F367TER_NOERROR_PKTJITTER 0xf2a20040
2283#define F367TER_SPY_CNULLPKT 0xf2a20020
2284#define F367TER_SPY_OUTDATA_MODE 0xf2a2001f
2285
2286/* FSPYOUT */
2287#define R367TER_FSPYOUT 0xf2a3
2288#define F367TER_FSPY_DIRECT 0xf2a30080
2289#define F367TER_FSPYOUT_6 0xf2a30040
2290#define F367TER_SPY_OUTDATA_BUS 0xf2a30038
2291#define F367TER_STUFF_MODE 0xf2a30007
2292
2293/* FSTATUS */
2294#define R367TER_FSTATUS 0xf2a4
2295#define F367TER_SPY_ENDSIM 0xf2a40080
2296#define F367TER_VALID_SIM 0xf2a40040
2297#define F367TER_FOUND_SIGNAL 0xf2a40020
2298#define F367TER_DSS_SYNCBYTE 0xf2a40010
2299#define F367TER_RESULT_STATE 0xf2a4000f
2300
2301/* FGOODPACK */
2302#define R367TER_FGOODPACK 0xf2a5
2303#define F367TER_FGOOD_PACKET 0xf2a500ff
2304
2305/* FPACKCNT */
2306#define R367TER_FPACKCNT 0xf2a6
2307#define F367TER_FPACKET_COUNTER 0xf2a600ff
2308
2309/* FSPYMISC */
2310#define R367TER_FSPYMISC 0xf2a7
2311#define F367TER_FLABEL_COUNTER 0xf2a700ff
2312
2313/* FBERCPT4 */
2314#define R367TER_FBERCPT4 0xf2a8
2315#define F367TER_FBERMETER_CPT5 0xf2a800ff
2316
2317/* FBERCPT3 */
2318#define R367TER_FBERCPT3 0xf2a9
2319#define F367TER_FBERMETER_CPT4 0xf2a900ff
2320
2321/* FBERCPT2 */
2322#define R367TER_FBERCPT2 0xf2aa
2323#define F367TER_FBERMETER_CPT3 0xf2aa00ff
2324
2325/* FBERCPT1 */
2326#define R367TER_FBERCPT1 0xf2ab
2327#define F367TER_FBERMETER_CPT2 0xf2ab00ff
2328
2329/* FBERCPT0 */
2330#define R367TER_FBERCPT0 0xf2ac
2331#define F367TER_FBERMETER_CPT1 0xf2ac00ff
2332
2333/* FBERERR2 */
2334#define R367TER_FBERERR2 0xf2ad
2335#define F367TER_FBERMETER_ERR_HI 0xf2ad00ff
2336
2337/* FBERERR1 */
2338#define R367TER_FBERERR1 0xf2ae
2339#define F367TER_FBERMETER_ERR_MED 0xf2ae00ff
2340
2341/* FBERERR0 */
2342#define R367TER_FBERERR0 0xf2af
2343#define F367TER_FBERMETER_ERR_LO 0xf2af00ff
2344
2345/* FSTATESM */
2346#define R367TER_FSTATESM 0xf2b0
2347#define F367TER_RSTATE_F 0xf2b00080
2348#define F367TER_RSTATE_E 0xf2b00040
2349#define F367TER_RSTATE_D 0xf2b00020
2350#define F367TER_RSTATE_C 0xf2b00010
2351#define F367TER_RSTATE_B 0xf2b00008
2352#define F367TER_RSTATE_A 0xf2b00004
2353#define F367TER_RSTATE_9 0xf2b00002
2354#define F367TER_RSTATE_8 0xf2b00001
2355
2356/* FSTATESL */
2357#define R367TER_FSTATESL 0xf2b1
2358#define F367TER_RSTATE_7 0xf2b10080
2359#define F367TER_RSTATE_6 0xf2b10040
2360#define F367TER_RSTATE_5 0xf2b10020
2361#define F367TER_RSTATE_4 0xf2b10010
2362#define F367TER_RSTATE_3 0xf2b10008
2363#define F367TER_RSTATE_2 0xf2b10004
2364#define F367TER_RSTATE_1 0xf2b10002
2365#define F367TER_RSTATE_0 0xf2b10001
2366
2367/* FSPYBER */
2368#define R367TER_FSPYBER 0xf2b2
2369#define F367TER_FSPYBER_7 0xf2b20080
2370#define F367TER_FSPYOBS_XORREAD 0xf2b20040
2371#define F367TER_FSPYBER_OBSMODE 0xf2b20020
2372#define F367TER_FSPYBER_SYNCBYTE 0xf2b20010
2373#define F367TER_FSPYBER_UNSYNC 0xf2b20008
2374#define F367TER_FSPYBER_CTIME 0xf2b20007
2375
2376/* FSPYDISTM */
2377#define R367TER_FSPYDISTM 0xf2b3
2378#define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff
2379
2380/* FSPYDISTL */
2381#define R367TER_FSPYDISTL 0xf2b4
2382#define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff
2383
2384/* FSPYOBS7 */
2385#define R367TER_FSPYOBS7 0xf2b8
2386#define F367TER_FSPYOBS_SPYFAIL 0xf2b80080
2387#define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040
2388#define F367TER_FSPYOBS_ERROR 0xf2b80020
2389#define F367TER_FSPYOBS_STROUT 0xf2b80010
2390#define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f
2391
2392/* FSPYOBS6 */
2393#define R367TER_FSPYOBS6 0xf2b9
2394#define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0
2395#define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f
2396
2397/* FSPYOBS5 */
2398#define R367TER_FSPYOBS5 0xf2ba
2399#define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff
2400
2401/* FSPYOBS4 */
2402#define R367TER_FSPYOBS4 0xf2bb
2403#define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff
2404
2405/* FSPYOBS3 */
2406#define R367TER_FSPYOBS3 0xf2bc
2407#define F367TER_FSPYOBS_DATA1 0xf2bc00ff
2408
2409/* FSPYOBS2 */
2410#define R367TER_FSPYOBS2 0xf2bd
2411#define F367TER_FSPYOBS_DATa0 0xf2bd00ff
2412
2413/* FSPYOBS1 */
2414#define R367TER_FSPYOBS1 0xf2be
2415#define F367TER_FSPYOBS_DATAM1 0xf2be00ff
2416
2417/* FSPYOBS0 */
2418#define R367TER_FSPYOBS0 0xf2bf
2419#define F367TER_FSPYOBS_DATAM2 0xf2bf00ff
2420
2421/* SFDEMAP */
2422#define R367TER_SFDEMAP 0xf2c0
2423#define F367TER_SFDEMAP_7 0xf2c00080
2424#define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f
2425
2426/* SFERROR */
2427#define R367TER_SFERROR 0xf2c1
2428#define F367TER_SFEC_REGERR_VIT 0xf2c100ff
2429
2430/* SFAVSR */
2431#define R367TER_SFAVSR 0xf2c2
2432#define F367TER_SFEC_SUMERRORS 0xf2c20080
2433#define F367TER_SERROR_MAXMODE 0xf2c20040
2434#define F367TER_SN_SFEC 0xf2c20030
2435#define F367TER_KDIV_MODE_SFEC 0xf2c2000c
2436#define F367TER_SFAVSR_1 0xf2c20002
2437#define F367TER_SFAVSR_0 0xf2c20001
2438
2439/* SFECSTATUS */
2440#define R367TER_SFECSTATUS 0xf2c3
2441#define F367TER_SFEC_ON 0xf2c30080
2442#define F367TER_SFSTATUS_6 0xf2c30040
2443#define F367TER_SFSTATUS_5 0xf2c30020
2444#define F367TER_SFSTATUS_4 0xf2c30010
2445#define F367TER_LOCKEDSFEC 0xf2c30008
2446#define F367TER_SFEC_DELOCK 0xf2c30004
2447#define F367TER_SFEC_DEMODSEL1 0xf2c30002
2448#define F367TER_SFEC_OVFON 0xf2c30001
2449
2450/* SFKDIV12 */
2451#define R367TER_SFKDIV12 0xf2c4
2452#define F367TER_SFECKDIV12_MAN 0xf2c40080
2453#define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f
2454
2455/* SFKDIV23 */
2456#define R367TER_SFKDIV23 0xf2c5
2457#define F367TER_SFECKDIV23_MAN 0xf2c50080
2458#define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f
2459
2460/* SFKDIV34 */
2461#define R367TER_SFKDIV34 0xf2c6
2462#define F367TER_SFECKDIV34_MAN 0xf2c60080
2463#define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f
2464
2465/* SFKDIV56 */
2466#define R367TER_SFKDIV56 0xf2c7
2467#define F367TER_SFECKDIV56_MAN 0xf2c70080
2468#define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f
2469
2470/* SFKDIV67 */
2471#define R367TER_SFKDIV67 0xf2c8
2472#define F367TER_SFECKDIV67_MAN 0xf2c80080
2473#define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f
2474
2475/* SFKDIV78 */
2476#define R367TER_SFKDIV78 0xf2c9
2477#define F367TER_SFECKDIV78_MAN 0xf2c90080
2478#define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f
2479
2480/* SFDILSTKM */
2481#define R367TER_SFDILSTKM 0xf2ca
2482#define F367TER_SFEC_PACKCPT 0xf2ca00e0
2483#define F367TER_SFEC_DILSTK_HI 0xf2ca001f
2484
2485/* SFDILSTKL */
2486#define R367TER_SFDILSTKL 0xf2cb
2487#define F367TER_SFEC_DILSTK_LO 0xf2cb00ff
2488
2489/* SFSTATUS */
2490#define R367TER_SFSTATUS 0xf2cc
2491#define F367TER_SFEC_LINEOK 0xf2cc0080
2492#define F367TER_SFEC_ERROR 0xf2cc0040
2493#define F367TER_SFEC_DATA7 0xf2cc0020
2494#define F367TER_SFEC_OVERFLOW 0xf2cc0010
2495#define F367TER_SFEC_DEMODSEL2 0xf2cc0008
2496#define F367TER_SFEC_NOSYNC 0xf2cc0004
2497#define F367TER_SFEC_UNREGULA 0xf2cc0002
2498#define F367TER_SFEC_READY 0xf2cc0001
2499
2500/* SFDLYH */
2501#define R367TER_SFDLYH 0xf2cd
2502#define F367TER_SFEC_TSTIMEVALID 0xf2cd0080
2503#define F367TER_SFEC_SPEEDUP 0xf2cd0040
2504#define F367TER_SFEC_STOP 0xf2cd0020
2505#define F367TER_SFEC_REGULATED 0xf2cd0010
2506#define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f
2507
2508/* SFDLYM */
2509#define R367TER_SFDLYM 0xf2ce
2510#define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff
2511
2512/* SFDLYL */
2513#define R367TER_SFDLYL 0xf2cf
2514#define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff
2515
2516/* SFDLYSETH */
2517#define R367TER_SFDLYSETH 0xf2d0
2518#define F367TER_SFEC_OFFSET 0xf2d000e0
2519#define F367TER_SFECDLYSETH_4 0xf2d00010
2520#define F367TER_RST_SFEC 0xf2d00008
2521#define F367TER_SFECDLYSETH_2 0xf2d00004
2522#define F367TER_SFEC_DISABLE 0xf2d00002
2523#define F367TER_SFEC_UNREGUL 0xf2d00001
2524
2525/* SFDLYSETM */
2526#define R367TER_SFDLYSETM 0xf2d1
2527#define F367TER_SFECDLYSETM_7 0xf2d10080
2528#define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f
2529
2530/* SFDLYSETL */
2531#define R367TER_SFDLYSETL 0xf2d2
2532#define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff
2533
2534/* SFOBSCFG */
2535#define R367TER_SFOBSCFG 0xf2d3
2536#define F367TER_SFEC_OBSCFG 0xf2d300ff
2537
2538/* SFOBSM */
2539#define R367TER_SFOBSM 0xf2d4
2540#define F367TER_SFEC_OBSDATA_HI 0xf2d400ff
2541
2542/* SFOBSL */
2543#define R367TER_SFOBSL 0xf2d5
2544#define F367TER_SFEC_OBSDATA_LO 0xf2d500ff
2545
2546/* SFECINFO */
2547#define R367TER_SFECINFO 0xf2d6
2548#define F367TER_SFECINFO_7 0xf2d60080
2549#define F367TER_SFEC_SYNCDLSB 0xf2d60070
2550#define F367TER_SFCE_S1cPHASE 0xf2d6000f
2551
2552/* SFERRCTRL */
2553#define R367TER_SFERRCTRL 0xf2d8
2554#define F367TER_SFEC_ERR_SOURCE 0xf2d800f0
2555#define F367TER_SFERRCTRL_3 0xf2d80008
2556#define F367TER_SFEC_NUM_EVENT 0xf2d80007
2557
2558/* SFERRCNTH */
2559#define R367TER_SFERRCNTH 0xf2d9
2560#define F367TER_SFERRC_OLDVALUE 0xf2d90080
2561#define F367TER_SFEC_ERR_CNT 0xf2d9007f
2562
2563/* SFERRCNTM */
2564#define R367TER_SFERRCNTM 0xf2da
2565#define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff
2566
2567/* SFERRCNTL */
2568#define R367TER_SFERRCNTL 0xf2db
2569#define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff
2570
2571/* SYMBRATEM */
2572#define R367TER_SYMBRATEM 0xf2e0
2573#define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff
2574
2575/* SYMBRATEL */
2576#define R367TER_SYMBRATEL 0xf2e1
2577#define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff
2578
2579/* SYMBSTATUS */
2580#define R367TER_SYMBSTATUS 0xf2e2
2581#define F367TER_SYMBDLINE2_OFF 0xf2e20080
2582#define F367TER_SDDL_REINIT1 0xf2e20040
2583#define F367TER_SDD_REINIT1 0xf2e20020
2584#define F367TER_TOKENID_ERROR 0xf2e20010
2585#define F367TER_SYMBRATE_OVERFLOW 0xf2e20008
2586#define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004
2587#define F367TER_TOKENID_RSTEVENT 0xf2e20002
2588#define F367TER_TOKENID_RESET1 0xf2e20001
2589
2590/* SYMBCFG */
2591#define R367TER_SYMBCFG 0xf2e3
2592#define F367TER_SYMBCFG_7 0xf2e30080
2593#define F367TER_SYMBCFG_6 0xf2e30040
2594#define F367TER_SYMBCFG_5 0xf2e30020
2595#define F367TER_SYMBCFG_4 0xf2e30010
2596#define F367TER_SYMRATE_FSPEED 0xf2e3000c
2597#define F367TER_SYMRATE_SSPEED 0xf2e30003
2598
2599/* SYMBFIFOM */
2600#define R367TER_SYMBFIFOM 0xf2e4
2601#define F367TER_SYMBFIFOM_7 0xf2e40080
2602#define F367TER_SYMBFIFOM_6 0xf2e40040
2603#define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f
2604
2605/* SYMBFIFOL */
2606#define R367TER_SYMBFIFOL 0xf2e5
2607#define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff
2608
2609/* SYMBOFFSM */
2610#define R367TER_SYMBOFFSM 0xf2e6
2611#define F367TER_TOKENID_RESET2 0xf2e60080
2612#define F367TER_SDDL_REINIT2 0xf2e60040
2613#define F367TER_SDD_REINIT2 0xf2e60020
2614#define F367TER_SYMBOFFSM_4 0xf2e60010
2615#define F367TER_SYMBOFFSM_3 0xf2e60008
2616#define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007
2617
2618/* SYMBOFFSL */
2619#define R367TER_SYMBOFFSL 0xf2e7
2620#define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff
2621
2622/* DEBUG_LT4 */
2623#define R367TER_DEBUG_LT4 0xf400
2624#define F367TER_F_DEBUG_LT4 0xf40000ff
2625
2626/* DEBUG_LT5 */
2627#define R367TER_DEBUG_LT5 0xf401
2628#define F367TER_F_DEBUG_LT5 0xf40100ff
2629
2630/* DEBUG_LT6 */
2631#define R367TER_DEBUG_LT6 0xf402
2632#define F367TER_F_DEBUG_LT6 0xf40200ff
2633
2634/* DEBUG_LT7 */
2635#define R367TER_DEBUG_LT7 0xf403
2636#define F367TER_F_DEBUG_LT7 0xf40300ff
2637
2638/* DEBUG_LT8 */
2639#define R367TER_DEBUG_LT8 0xf404
2640#define F367TER_F_DEBUG_LT8 0xf40400ff
2641
2642/* DEBUG_LT9 */
2643#define R367TER_DEBUG_LT9 0xf405
2644#define F367TER_F_DEBUG_LT9 0xf40500ff
2645
2646#define STV0367TER_NBREGS 445
2647
2648/* ID */
2649#define R367CAB_ID 0xf000
2650#define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff
2651
2652/* I2CRPT */
2653#define R367CAB_I2CRPT 0xf001
2654#define F367CAB_I2CT_ON 0xf0010080
2655#define F367CAB_ENARPT_LEVEL 0xf0010070
2656#define F367CAB_SCLT_DELAY 0xf0010008
2657#define F367CAB_SCLT_NOD 0xf0010004
2658#define F367CAB_STOP_ENABLE 0xf0010002
2659#define F367CAB_SDAT_NOD 0xf0010001
2660
2661/* TOPCTRL */
2662#define R367CAB_TOPCTRL 0xf002
2663#define F367CAB_STDBY 0xf0020080
2664#define F367CAB_STDBY_CORE 0xf0020020
2665#define F367CAB_QAM_COFDM 0xf0020010
2666#define F367CAB_TS_DIS 0xf0020008
2667#define F367CAB_DIR_CLK_216 0xf0020004
2668
2669/* IOCFG0 */
2670#define R367CAB_IOCFG0 0xf003
2671#define F367CAB_OP0_SD 0xf0030080
2672#define F367CAB_OP0_VAL 0xf0030040
2673#define F367CAB_OP0_OD 0xf0030020
2674#define F367CAB_OP0_INV 0xf0030010
2675#define F367CAB_OP0_DACVALUE_HI 0xf003000f
2676
2677/* DAc0R */
2678#define R367CAB_DAC0R 0xf004
2679#define F367CAB_OP0_DACVALUE_LO 0xf00400ff
2680
2681/* IOCFG1 */
2682#define R367CAB_IOCFG1 0xf005
2683#define F367CAB_IP0 0xf0050040
2684#define F367CAB_OP1_OD 0xf0050020
2685#define F367CAB_OP1_INV 0xf0050010
2686#define F367CAB_OP1_DACVALUE_HI 0xf005000f
2687
2688/* DAC1R */
2689#define R367CAB_DAC1R 0xf006
2690#define F367CAB_OP1_DACVALUE_LO 0xf00600ff
2691
2692/* IOCFG2 */
2693#define R367CAB_IOCFG2 0xf007
2694#define F367CAB_OP2_LOCK_CONF 0xf00700e0
2695#define F367CAB_OP2_OD 0xf0070010
2696#define F367CAB_OP2_VAL 0xf0070008
2697#define F367CAB_OP1_LOCK_CONF 0xf0070007
2698
2699/* SDFR */
2700#define R367CAB_SDFR 0xf008
2701#define F367CAB_OP0_FREQ 0xf00800f0
2702#define F367CAB_OP1_FREQ 0xf008000f
2703
2704/* AUX_CLK */
2705#define R367CAB_AUX_CLK 0xf00a
2706#define F367CAB_AUXFEC_CTL 0xf00a00c0
2707#define F367CAB_DIS_CKX4 0xf00a0020
2708#define F367CAB_CKSEL 0xf00a0018
2709#define F367CAB_CKDIV_PROG 0xf00a0006
2710#define F367CAB_AUXCLK_ENA 0xf00a0001
2711
2712/* FREESYS1 */
2713#define R367CAB_FREESYS1 0xf00b
2714#define F367CAB_FREESYS_1 0xf00b00ff
2715
2716/* FREESYS2 */
2717#define R367CAB_FREESYS2 0xf00c
2718#define F367CAB_FREESYS_2 0xf00c00ff
2719
2720/* FREESYS3 */
2721#define R367CAB_FREESYS3 0xf00d
2722#define F367CAB_FREESYS_3 0xf00d00ff
2723
2724/* GPIO_CFG */
2725#define R367CAB_GPIO_CFG 0xf00e
2726#define F367CAB_GPIO7_OD 0xf00e0080
2727#define F367CAB_GPIO7_CFG 0xf00e0040
2728#define F367CAB_GPIO6_OD 0xf00e0020
2729#define F367CAB_GPIO6_CFG 0xf00e0010
2730#define F367CAB_GPIO5_OD 0xf00e0008
2731#define F367CAB_GPIO5_CFG 0xf00e0004
2732#define F367CAB_GPIO4_OD 0xf00e0002
2733#define F367CAB_GPIO4_CFG 0xf00e0001
2734
2735/* GPIO_CMD */
2736#define R367CAB_GPIO_CMD 0xf00f
2737#define F367CAB_GPIO7_VAL 0xf00f0008
2738#define F367CAB_GPIO6_VAL 0xf00f0004
2739#define F367CAB_GPIO5_VAL 0xf00f0002
2740#define F367CAB_GPIO4_VAL 0xf00f0001
2741
2742/* TSTRES */
2743#define R367CAB_TSTRES 0xf0c0
2744#define F367CAB_FRES_DISPLAY 0xf0c00080
2745#define F367CAB_FRES_FIFO_AD 0xf0c00020
2746#define F367CAB_FRESRS 0xf0c00010
2747#define F367CAB_FRESACS 0xf0c00008
2748#define F367CAB_FRESFEC 0xf0c00004
2749#define F367CAB_FRES_PRIF 0xf0c00002
2750#define F367CAB_FRESCORE 0xf0c00001
2751
2752/* ANACTRL */
2753#define R367CAB_ANACTRL 0xf0c1
2754#define F367CAB_BYPASS_XTAL 0xf0c10040
2755#define F367CAB_BYPASS_PLLXN 0xf0c1000c
2756#define F367CAB_DIS_PAD_OSC 0xf0c10002
2757#define F367CAB_STDBY_PLLXN 0xf0c10001
2758
2759/* TSTBUS */
2760#define R367CAB_TSTBUS 0xf0c2
2761#define F367CAB_TS_BYTE_CLK_INV 0xf0c20080
2762#define F367CAB_CFG_IP 0xf0c20070
2763#define F367CAB_CFG_TST 0xf0c2000f
2764
2765/* RF_AGC1 */
2766#define R367CAB_RF_AGC1 0xf0d4
2767#define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff
2768
2769/* RF_AGC2 */
2770#define R367CAB_RF_AGC2 0xf0d5
2771#define F367CAB_REF_ADGP 0xf0d50080
2772#define F367CAB_STDBY_ADCGP 0xf0d50020
2773#define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003
2774
2775/* ANADIGCTRL */
2776#define R367CAB_ANADIGCTRL 0xf0d7
2777#define F367CAB_SEL_CLKDEM 0xf0d70020
2778#define F367CAB_EN_BUFFER_Q 0xf0d70010
2779#define F367CAB_EN_BUFFER_I 0xf0d70008
2780#define F367CAB_ADC_RIS_EGDE 0xf0d70004
2781#define F367CAB_SGN_ADC 0xf0d70002
2782#define F367CAB_SEL_AD12_SYNC 0xf0d70001
2783
2784/* PLLMDIV */
2785#define R367CAB_PLLMDIV 0xf0d8
2786#define F367CAB_PLL_MDIV 0xf0d800ff
2787
2788/* PLLNDIV */
2789#define R367CAB_PLLNDIV 0xf0d9
2790#define F367CAB_PLL_NDIV 0xf0d900ff
2791
2792/* PLLSETUP */
2793#define R367CAB_PLLSETUP 0xf0da
2794#define F367CAB_PLL_PDIV 0xf0da0070
2795#define F367CAB_PLL_KDIV 0xf0da000f
2796
2797/* DUAL_AD12 */
2798#define R367CAB_DUAL_AD12 0xf0db
2799#define F367CAB_FS20M 0xf0db0020
2800#define F367CAB_FS50M 0xf0db0010
2801#define F367CAB_INMODe0 0xf0db0008
2802#define F367CAB_POFFQ 0xf0db0004
2803#define F367CAB_POFFI 0xf0db0002
2804#define F367CAB_INMODE1 0xf0db0001
2805
2806/* TSTBIST */
2807#define R367CAB_TSTBIST 0xf0dc
2808#define F367CAB_TST_BYP_CLK 0xf0dc0080
2809#define F367CAB_TST_GCLKENA_STD 0xf0dc0040
2810#define F367CAB_TST_GCLKENA 0xf0dc0020
2811#define F367CAB_TST_MEMBIST 0xf0dc001f
2812
2813/* CTRL_1 */
2814#define R367CAB_CTRL_1 0xf402
2815#define F367CAB_SOFT_RST 0xf4020080
2816#define F367CAB_EQU_RST 0xf4020008
2817#define F367CAB_CRL_RST 0xf4020004
2818#define F367CAB_TRL_RST 0xf4020002
2819#define F367CAB_AGC_RST 0xf4020001
2820
2821/* CTRL_2 */
2822#define R367CAB_CTRL_2 0xf403
2823#define F367CAB_DEINT_RST 0xf4030008
2824#define F367CAB_RS_RST 0xf4030004
2825
2826/* IT_STATUS1 */
2827#define R367CAB_IT_STATUS1 0xf408
2828#define F367CAB_SWEEP_OUT 0xf4080080
2829#define F367CAB_FSM_CRL 0xf4080040
2830#define F367CAB_CRL_LOCK 0xf4080020
2831#define F367CAB_MFSM 0xf4080010
2832#define F367CAB_TRL_LOCK 0xf4080008
2833#define F367CAB_TRL_AGC_LIMIT 0xf4080004
2834#define F367CAB_ADJ_AGC_LOCK 0xf4080002
2835#define F367CAB_AGC_QAM_LOCK 0xf4080001
2836
2837/* IT_STATUS2 */
2838#define R367CAB_IT_STATUS2 0xf409
2839#define F367CAB_TSMF_CNT 0xf4090080
2840#define F367CAB_TSMF_EOF 0xf4090040
2841#define F367CAB_TSMF_RDY 0xf4090020
2842#define F367CAB_FEC_NOCORR 0xf4090010
2843#define F367CAB_SYNCSTATE 0xf4090008
2844#define F367CAB_DEINT_LOCK 0xf4090004
2845#define F367CAB_FADDING_FRZ 0xf4090002
2846#define F367CAB_TAPMON_ALARM 0xf4090001
2847
2848/* IT_EN1 */
2849#define R367CAB_IT_EN1 0xf40a
2850#define F367CAB_SWEEP_OUTE 0xf40a0080
2851#define F367CAB_FSM_CRLE 0xf40a0040
2852#define F367CAB_CRL_LOCKE 0xf40a0020
2853#define F367CAB_MFSME 0xf40a0010
2854#define F367CAB_TRL_LOCKE 0xf40a0008
2855#define F367CAB_TRL_AGC_LIMITE 0xf40a0004
2856#define F367CAB_ADJ_AGC_LOCKE 0xf40a0002
2857#define F367CAB_AGC_LOCKE 0xf40a0001
2858
2859/* IT_EN2 */
2860#define R367CAB_IT_EN2 0xf40b
2861#define F367CAB_TSMF_CNTE 0xf40b0080
2862#define F367CAB_TSMF_EOFE 0xf40b0040
2863#define F367CAB_TSMF_RDYE 0xf40b0020
2864#define F367CAB_FEC_NOCORRE 0xf40b0010
2865#define F367CAB_SYNCSTATEE 0xf40b0008
2866#define F367CAB_DEINT_LOCKE 0xf40b0004
2867#define F367CAB_FADDING_FRZE 0xf40b0002
2868#define F367CAB_TAPMON_ALARME 0xf40b0001
2869
2870/* CTRL_STATUS */
2871#define R367CAB_CTRL_STATUS 0xf40c
2872#define F367CAB_QAMFEC_LOCK 0xf40c0004
2873#define F367CAB_TSMF_LOCK 0xf40c0002
2874#define F367CAB_TSMF_ERROR 0xf40c0001
2875
2876/* TEST_CTL */
2877#define R367CAB_TEST_CTL 0xf40f
2878#define F367CAB_TST_BLK_SEL 0xf40f0060
2879#define F367CAB_TST_BUS_SEL 0xf40f001f
2880
2881/* AGC_CTL */
2882#define R367CAB_AGC_CTL 0xf410
2883#define F367CAB_AGC_LCK_TH 0xf41000f0
2884#define F367CAB_AGC_ACCUMRSTSEL 0xf4100007
2885
2886/* AGC_IF_CFG */
2887#define R367CAB_AGC_IF_CFG 0xf411
2888#define F367CAB_AGC_IF_BWSEL 0xf41100f0
2889#define F367CAB_AGC_IF_FREEZE 0xf4110002
2890
2891/* AGC_RF_CFG */
2892#define R367CAB_AGC_RF_CFG 0xf412
2893#define F367CAB_AGC_RF_BWSEL 0xf4120070
2894#define F367CAB_AGC_RF_FREEZE 0xf4120002
2895
2896/* AGC_PWM_CFG */
2897#define R367CAB_AGC_PWM_CFG 0xf413
2898#define F367CAB_AGC_RF_PWM_TST 0xf4130080
2899#define F367CAB_AGC_RF_PWM_INV 0xf4130040
2900#define F367CAB_AGC_IF_PWM_TST 0xf4130008
2901#define F367CAB_AGC_IF_PWM_INV 0xf4130004
2902#define F367CAB_AGC_PWM_CLKDIV 0xf4130003
2903
2904/* AGC_PWR_REF_L */
2905#define R367CAB_AGC_PWR_REF_L 0xf414
2906#define F367CAB_AGC_PWRREF_LO 0xf41400ff
2907
2908/* AGC_PWR_REF_H */
2909#define R367CAB_AGC_PWR_REF_H 0xf415
2910#define F367CAB_AGC_PWRREF_HI 0xf4150003
2911
2912/* AGC_RF_TH_L */
2913#define R367CAB_AGC_RF_TH_L 0xf416
2914#define F367CAB_AGC_RF_TH_LO 0xf41600ff
2915
2916/* AGC_RF_TH_H */
2917#define R367CAB_AGC_RF_TH_H 0xf417
2918#define F367CAB_AGC_RF_TH_HI 0xf417000f
2919
2920/* AGC_IF_LTH_L */
2921#define R367CAB_AGC_IF_LTH_L 0xf418
2922#define F367CAB_AGC_IF_THLO_LO 0xf41800ff
2923
2924/* AGC_IF_LTH_H */
2925#define R367CAB_AGC_IF_LTH_H 0xf419
2926#define F367CAB_AGC_IF_THLO_HI 0xf419000f
2927
2928/* AGC_IF_HTH_L */
2929#define R367CAB_AGC_IF_HTH_L 0xf41a
2930#define F367CAB_AGC_IF_THHI_LO 0xf41a00ff
2931
2932/* AGC_IF_HTH_H */
2933#define R367CAB_AGC_IF_HTH_H 0xf41b
2934#define F367CAB_AGC_IF_THHI_HI 0xf41b000f
2935
2936/* AGC_PWR_RD_L */
2937#define R367CAB_AGC_PWR_RD_L 0xf41c
2938#define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff
2939
2940/* AGC_PWR_RD_M */
2941#define R367CAB_AGC_PWR_RD_M 0xf41d
2942#define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff
2943
2944/* AGC_PWR_RD_H */
2945#define R367CAB_AGC_PWR_RD_H 0xf41e
2946#define F367CAB_AGC_PWR_WORD_HI 0xf41e0003
2947
2948/* AGC_PWM_IFCMD_L */
2949#define R367CAB_AGC_PWM_IFCMD_L 0xf420
2950#define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff
2951
2952/* AGC_PWM_IFCMD_H */
2953#define R367CAB_AGC_PWM_IFCMD_H 0xf421
2954#define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f
2955
2956/* AGC_PWM_RFCMD_L */
2957#define R367CAB_AGC_PWM_RFCMD_L 0xf422
2958#define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff
2959
2960/* AGC_PWM_RFCMD_H */
2961#define R367CAB_AGC_PWM_RFCMD_H 0xf423
2962#define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f
2963
2964/* IQDEM_CFG */
2965#define R367CAB_IQDEM_CFG 0xf424
2966#define F367CAB_IQDEM_CLK_SEL 0xf4240004
2967#define F367CAB_IQDEM_INVIQ 0xf4240002
2968#define F367CAB_IQDEM_A2dTYPE 0xf4240001
2969
2970/* MIX_NCO_LL */
2971#define R367CAB_MIX_NCO_LL 0xf425
2972#define F367CAB_MIX_NCO_INC_LL 0xf42500ff
2973
2974/* MIX_NCO_HL */
2975#define R367CAB_MIX_NCO_HL 0xf426
2976#define F367CAB_MIX_NCO_INC_HL 0xf42600ff
2977
2978/* MIX_NCO_HH */
2979#define R367CAB_MIX_NCO_HH 0xf427
2980#define F367CAB_MIX_NCO_INVCNST 0xf4270080
2981#define F367CAB_MIX_NCO_INC_HH 0xf427007f
2982
2983/* SRC_NCO_LL */
2984#define R367CAB_SRC_NCO_LL 0xf428
2985#define F367CAB_SRC_NCO_INC_LL 0xf42800ff
2986
2987/* SRC_NCO_LH */
2988#define R367CAB_SRC_NCO_LH 0xf429
2989#define F367CAB_SRC_NCO_INC_LH 0xf42900ff
2990
2991/* SRC_NCO_HL */
2992#define R367CAB_SRC_NCO_HL 0xf42a
2993#define F367CAB_SRC_NCO_INC_HL 0xf42a00ff
2994
2995/* SRC_NCO_HH */
2996#define R367CAB_SRC_NCO_HH 0xf42b
2997#define F367CAB_SRC_NCO_INC_HH 0xf42b007f
2998
2999/* IQDEM_GAIN_SRC_L */
3000#define R367CAB_IQDEM_GAIN_SRC_L 0xf42c
3001#define F367CAB_GAIN_SRC_LO 0xf42c00ff
3002
3003/* IQDEM_GAIN_SRC_H */
3004#define R367CAB_IQDEM_GAIN_SRC_H 0xf42d
3005#define F367CAB_GAIN_SRC_HI 0xf42d0003
3006
3007/* IQDEM_DCRM_CFG_LL */
3008#define R367CAB_IQDEM_DCRM_CFG_LL 0xf430
3009#define F367CAB_DCRM0_DCIN_L 0xf43000ff
3010
3011/* IQDEM_DCRM_CFG_LH */
3012#define R367CAB_IQDEM_DCRM_CFG_LH 0xf431
3013#define F367CAB_DCRM1_I_DCIN_L 0xf43100fc
3014#define F367CAB_DCRM0_DCIN_H 0xf4310003
3015
3016/* IQDEM_DCRM_CFG_HL */
3017#define R367CAB_IQDEM_DCRM_CFG_HL 0xf432
3018#define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0
3019#define F367CAB_DCRM1_I_DCIN_H 0xf432000f
3020
3021/* IQDEM_DCRM_CFG_HH */
3022#define R367CAB_IQDEM_DCRM_CFG_HH 0xf433
3023#define F367CAB_DCRM1_FRZ 0xf4330080
3024#define F367CAB_DCRM0_FRZ 0xf4330040
3025#define F367CAB_DCRM1_Q_DCIN_H 0xf433003f
3026
3027/* IQDEM_ADJ_COEFf0 */
3028#define R367CAB_IQDEM_ADJ_COEFF0 0xf434
3029#define F367CAB_ADJIIR_COEFF10_L 0xf43400ff
3030
3031/* IQDEM_ADJ_COEFF1 */
3032#define R367CAB_IQDEM_ADJ_COEFF1 0xf435
3033#define F367CAB_ADJIIR_COEFF11_L 0xf43500fc
3034#define F367CAB_ADJIIR_COEFF10_H 0xf4350003
3035
3036/* IQDEM_ADJ_COEFF2 */
3037#define R367CAB_IQDEM_ADJ_COEFF2 0xf436
3038#define F367CAB_ADJIIR_COEFF12_L 0xf43600f0
3039#define F367CAB_ADJIIR_COEFF11_H 0xf436000f
3040
3041/* IQDEM_ADJ_COEFF3 */
3042#define R367CAB_IQDEM_ADJ_COEFF3 0xf437
3043#define F367CAB_ADJIIR_COEFF20_L 0xf43700c0
3044#define F367CAB_ADJIIR_COEFF12_H 0xf437003f
3045
3046/* IQDEM_ADJ_COEFF4 */
3047#define R367CAB_IQDEM_ADJ_COEFF4 0xf438
3048#define F367CAB_ADJIIR_COEFF20_H 0xf43800ff
3049
3050/* IQDEM_ADJ_COEFF5 */
3051#define R367CAB_IQDEM_ADJ_COEFF5 0xf439
3052#define F367CAB_ADJIIR_COEFF21_L 0xf43900ff
3053
3054/* IQDEM_ADJ_COEFF6 */
3055#define R367CAB_IQDEM_ADJ_COEFF6 0xf43a
3056#define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc
3057#define F367CAB_ADJIIR_COEFF21_H 0xf43a0003
3058
3059/* IQDEM_ADJ_COEFF7 */
3060#define R367CAB_IQDEM_ADJ_COEFF7 0xf43b
3061#define F367CAB_ADJIIR_COEFF22_H 0xf43b000f
3062
3063/* IQDEM_ADJ_EN */
3064#define R367CAB_IQDEM_ADJ_EN 0xf43c
3065#define F367CAB_ALLPASSFILT_EN 0xf43c0008
3066#define F367CAB_ADJ_AGC_EN 0xf43c0004
3067#define F367CAB_ADJ_COEFF_FRZ 0xf43c0002
3068#define F367CAB_ADJ_EN 0xf43c0001
3069
3070/* IQDEM_ADJ_AGC_REF */
3071#define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d
3072#define F367CAB_ADJ_AGC_REF 0xf43d00ff
3073
3074/* ALLPASSFILT1 */
3075#define R367CAB_ALLPASSFILT1 0xf440
3076#define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff
3077
3078/* ALLPASSFILT2 */
3079#define R367CAB_ALLPASSFILT2 0xf441
3080#define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff
3081
3082/* ALLPASSFILT3 */
3083#define R367CAB_ALLPASSFILT3 0xf442
3084#define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0
3085#define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f
3086
3087/* ALLPASSFILT4 */
3088#define R367CAB_ALLPASSFILT4 0xf443
3089#define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff
3090
3091/* ALLPASSFILT5 */
3092#define R367CAB_ALLPASSFILT5 0xf444
3093#define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff
3094
3095/* ALLPASSFILT6 */
3096#define R367CAB_ALLPASSFILT6 0xf445
3097#define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0
3098#define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f
3099
3100/* ALLPASSFILT7 */
3101#define R367CAB_ALLPASSFILT7 0xf446
3102#define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff
3103
3104/* ALLPASSFILT8 */
3105#define R367CAB_ALLPASSFILT8 0xf447
3106#define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff
3107
3108/* ALLPASSFILT9 */
3109#define R367CAB_ALLPASSFILT9 0xf448
3110#define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc
3111#define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003
3112
3113/* ALLPASSFILT10 */
3114#define R367CAB_ALLPASSFILT10 0xf449
3115#define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff
3116
3117/* ALLPASSFILT11 */
3118#define R367CAB_ALLPASSFILT11 0xf44a
3119#define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff
3120
3121/* TRL_AGC_CFG */
3122#define R367CAB_TRL_AGC_CFG 0xf450
3123#define F367CAB_TRL_AGC_FREEZE 0xf4500080
3124#define F367CAB_TRL_AGC_REF 0xf450007f
3125
3126/* TRL_LPF_CFG */
3127#define R367CAB_TRL_LPF_CFG 0xf454
3128#define F367CAB_NYQPOINT_INV 0xf4540040
3129#define F367CAB_TRL_SHIFT 0xf4540030
3130#define F367CAB_NYQ_COEFF_SEL 0xf454000c
3131#define F367CAB_TRL_LPF_FREEZE 0xf4540002
3132#define F367CAB_TRL_LPF_CRT 0xf4540001
3133
3134/* TRL_LPF_ACQ_GAIN */
3135#define R367CAB_TRL_LPF_ACQ_GAIN 0xf455
3136#define F367CAB_TRL_GDIR_ACQ 0xf4550070
3137#define F367CAB_TRL_GINT_ACQ 0xf4550007
3138
3139/* TRL_LPF_TRK_GAIN */
3140#define R367CAB_TRL_LPF_TRK_GAIN 0xf456
3141#define F367CAB_TRL_GDIR_TRK 0xf4560070
3142#define F367CAB_TRL_GINT_TRK 0xf4560007
3143
3144/* TRL_LPF_OUT_GAIN */
3145#define R367CAB_TRL_LPF_OUT_GAIN 0xf457
3146#define F367CAB_TRL_GAIN_OUT 0xf4570007
3147
3148/* TRL_LOCKDET_LTH */
3149#define R367CAB_TRL_LOCKDET_LTH 0xf458
3150#define F367CAB_TRL_LCK_THLO 0xf4580007
3151
3152/* TRL_LOCKDET_HTH */
3153#define R367CAB_TRL_LOCKDET_HTH 0xf459
3154#define F367CAB_TRL_LCK_THHI 0xf45900ff
3155
3156/* TRL_LOCKDET_TRGVAL */
3157#define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a
3158#define F367CAB_TRL_LCK_TRG 0xf45a00ff
3159
3160/* IQ_QAM */
3161#define R367CAB_IQ_QAM 0xf45c
3162#define F367CAB_IQ_INPUT 0xf45c0008
3163#define F367CAB_DETECT_MODE 0xf45c0007
3164
3165/* FSM_STATE */
3166#define R367CAB_FSM_STATE 0xf460
3167#define F367CAB_CRL_DFE 0xf4600080
3168#define F367CAB_DFE_START 0xf4600040
3169#define F367CAB_CTRLG_START 0xf4600030
3170#define F367CAB_FSM_FORCESTATE 0xf460000f
3171
3172/* FSM_CTL */
3173#define R367CAB_FSM_CTL 0xf461
3174#define F367CAB_FEC2_EN 0xf4610040
3175#define F367CAB_SIT_EN 0xf4610020
3176#define F367CAB_TRL_AHEAD 0xf4610010
3177#define F367CAB_TRL2_EN 0xf4610008
3178#define F367CAB_FSM_EQA1_EN 0xf4610004
3179#define F367CAB_FSM_BKP_DIS 0xf4610002
3180#define F367CAB_FSM_FORCE_EN 0xf4610001
3181
3182/* FSM_STS */
3183#define R367CAB_FSM_STS 0xf462
3184#define F367CAB_FSM_STATUS 0xf462000f
3185
3186/* FSM_SNR0_HTH */
3187#define R367CAB_FSM_SNR0_HTH 0xf463
3188#define F367CAB_SNR0_HTH 0xf46300ff
3189
3190/* FSM_SNR1_HTH */
3191#define R367CAB_FSM_SNR1_HTH 0xf464
3192#define F367CAB_SNR1_HTH 0xf46400ff
3193
3194/* FSM_SNR2_HTH */
3195#define R367CAB_FSM_SNR2_HTH 0xf465
3196#define F367CAB_SNR2_HTH 0xf46500ff
3197
3198/* FSM_SNR0_LTH */
3199#define R367CAB_FSM_SNR0_LTH 0xf466
3200#define F367CAB_SNR0_LTH 0xf46600ff
3201
3202/* FSM_SNR1_LTH */
3203#define R367CAB_FSM_SNR1_LTH 0xf467
3204#define F367CAB_SNR1_LTH 0xf46700ff
3205
3206/* FSM_EQA1_HTH */
3207#define R367CAB_FSM_EQA1_HTH 0xf468
3208#define F367CAB_SNR3_HTH_LO 0xf46800f0
3209#define F367CAB_EQA1_HTH 0xf468000f
3210
3211/* FSM_TEMPO */
3212#define R367CAB_FSM_TEMPO 0xf469
3213#define F367CAB_SIT 0xf46900c0
3214#define F367CAB_WST 0xf4690038
3215#define F367CAB_ELT 0xf4690006
3216#define F367CAB_SNR3_HTH_HI 0xf4690001
3217
3218/* FSM_CONFIG */
3219#define R367CAB_FSM_CONFIG 0xf46a
3220#define F367CAB_FEC2_DFEOFF 0xf46a0004
3221#define F367CAB_PRIT_STATE 0xf46a0002
3222#define F367CAB_MODMAP_STATE 0xf46a0001
3223
3224/* EQU_I_TESTTAP_L */
3225#define R367CAB_EQU_I_TESTTAP_L 0xf474
3226#define F367CAB_I_TEST_TAP_L 0xf47400ff
3227
3228/* EQU_I_TESTTAP_M */
3229#define R367CAB_EQU_I_TESTTAP_M 0xf475
3230#define F367CAB_I_TEST_TAP_M 0xf47500ff
3231
3232/* EQU_I_TESTTAP_H */
3233#define R367CAB_EQU_I_TESTTAP_H 0xf476
3234#define F367CAB_I_TEST_TAP_H 0xf476001f
3235
3236/* EQU_TESTAP_CFG */
3237#define R367CAB_EQU_TESTAP_CFG 0xf477
3238#define F367CAB_TEST_FFE_DFE_SEL 0xf4770040
3239#define F367CAB_TEST_TAP_SELECT 0xf477003f
3240
3241/* EQU_Q_TESTTAP_L */
3242#define R367CAB_EQU_Q_TESTTAP_L 0xf478
3243#define F367CAB_Q_TEST_TAP_L 0xf47800ff
3244
3245/* EQU_Q_TESTTAP_M */
3246#define R367CAB_EQU_Q_TESTTAP_M 0xf479
3247#define F367CAB_Q_TEST_TAP_M 0xf47900ff
3248
3249/* EQU_Q_TESTTAP_H */
3250#define R367CAB_EQU_Q_TESTTAP_H 0xf47a
3251#define F367CAB_Q_TEST_TAP_H 0xf47a001f
3252
3253/* EQU_TAP_CTRL */
3254#define R367CAB_EQU_TAP_CTRL 0xf47b
3255#define F367CAB_MTAP_FRZ 0xf47b0010
3256#define F367CAB_PRE_FREEZE 0xf47b0008
3257#define F367CAB_DFE_TAPMON_EN 0xf47b0004
3258#define F367CAB_FFE_TAPMON_EN 0xf47b0002
3259#define F367CAB_MTAP_ONLY 0xf47b0001
3260
3261/* EQU_CTR_CRL_CONTROL_L */
3262#define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c
3263#define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff
3264
3265/* EQU_CTR_CRL_CONTROL_H */
3266#define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d
3267#define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff
3268
3269/* EQU_CTR_HIPOW_L */
3270#define R367CAB_EQU_CTR_HIPOW_L 0xf47e
3271#define F367CAB_CTR_HIPOW_L 0xf47e00ff
3272
3273/* EQU_CTR_HIPOW_H */
3274#define R367CAB_EQU_CTR_HIPOW_H 0xf47f
3275#define F367CAB_CTR_HIPOW_H 0xf47f00ff
3276
3277/* EQU_I_EQU_LO */
3278#define R367CAB_EQU_I_EQU_LO 0xf480
3279#define F367CAB_EQU_I_EQU_L 0xf48000ff
3280
3281/* EQU_I_EQU_HI */
3282#define R367CAB_EQU_I_EQU_HI 0xf481
3283#define F367CAB_EQU_I_EQU_H 0xf4810003
3284
3285/* EQU_Q_EQU_LO */
3286#define R367CAB_EQU_Q_EQU_LO 0xf482
3287#define F367CAB_EQU_Q_EQU_L 0xf48200ff
3288
3289/* EQU_Q_EQU_HI */
3290#define R367CAB_EQU_Q_EQU_HI 0xf483
3291#define F367CAB_EQU_Q_EQU_H 0xf4830003
3292
3293/* EQU_MAPPER */
3294#define R367CAB_EQU_MAPPER 0xf484
3295#define F367CAB_QUAD_AUTO 0xf4840080
3296#define F367CAB_QUAD_INV 0xf4840040
3297#define F367CAB_QAM_MODE 0xf4840007
3298
3299/* EQU_SWEEP_RATE */
3300#define R367CAB_EQU_SWEEP_RATE 0xf485
3301#define F367CAB_SNR_PER 0xf48500c0
3302#define F367CAB_SWEEP_RATE 0xf485003f
3303
3304/* EQU_SNR_LO */
3305#define R367CAB_EQU_SNR_LO 0xf486
3306#define F367CAB_SNR_LO 0xf48600ff
3307
3308/* EQU_SNR_HI */
3309#define R367CAB_EQU_SNR_HI 0xf487
3310#define F367CAB_SNR_HI 0xf48700ff
3311
3312/* EQU_GAMMA_LO */
3313#define R367CAB_EQU_GAMMA_LO 0xf488
3314#define F367CAB_GAMMA_LO 0xf48800ff
3315
3316/* EQU_GAMMA_HI */
3317#define R367CAB_EQU_GAMMA_HI 0xf489
3318#define F367CAB_GAMMA_ME 0xf48900ff
3319
3320/* EQU_ERR_GAIN */
3321#define R367CAB_EQU_ERR_GAIN 0xf48a
3322#define F367CAB_EQA1MU 0xf48a0070
3323#define F367CAB_CRL2MU 0xf48a000e
3324#define F367CAB_GAMMA_HI 0xf48a0001
3325
3326/* EQU_RADIUS */
3327#define R367CAB_EQU_RADIUS 0xf48b
3328#define F367CAB_RADIUS 0xf48b00ff
3329
3330/* EQU_FFE_MAINTAP */
3331#define R367CAB_EQU_FFE_MAINTAP 0xf48c
3332#define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff
3333
3334/* EQU_FFE_LEAKAGE */
3335#define R367CAB_EQU_FFE_LEAKAGE 0xf48e
3336#define F367CAB_LEAK_PER 0xf48e00f0
3337#define F367CAB_EQU_OUTSEL 0xf48e0002
3338#define F367CAB_PNT2dFE 0xf48e0001
3339
3340/* EQU_FFE_MAINTAP_POS */
3341#define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f
3342#define F367CAB_FFE_LEAK_EN 0xf48f0080
3343#define F367CAB_DFE_LEAK_EN 0xf48f0040
3344#define F367CAB_FFE_MAINTAP_POS 0xf48f003f
3345
3346/* EQU_GAIN_WIDE */
3347#define R367CAB_EQU_GAIN_WIDE 0xf490
3348#define F367CAB_DFE_GAIN_WIDE 0xf49000f0
3349#define F367CAB_FFE_GAIN_WIDE 0xf490000f
3350
3351/* EQU_GAIN_NARROW */
3352#define R367CAB_EQU_GAIN_NARROW 0xf491
3353#define F367CAB_DFE_GAIN_NARROW 0xf49100f0
3354#define F367CAB_FFE_GAIN_NARROW 0xf491000f
3355
3356/* EQU_CTR_LPF_GAIN */
3357#define R367CAB_EQU_CTR_LPF_GAIN 0xf492
3358#define F367CAB_CTR_GTO 0xf4920080
3359#define F367CAB_CTR_GDIR 0xf4920070
3360#define F367CAB_SWEEP_EN 0xf4920008
3361#define F367CAB_CTR_GINT 0xf4920007
3362
3363/* EQU_CRL_LPF_GAIN */
3364#define R367CAB_EQU_CRL_LPF_GAIN 0xf493
3365#define F367CAB_CRL_GTO 0xf4930080
3366#define F367CAB_CRL_GDIR 0xf4930070
3367#define F367CAB_SWEEP_DIR 0xf4930008
3368#define F367CAB_CRL_GINT 0xf4930007
3369
3370/* EQU_GLOBAL_GAIN */
3371#define R367CAB_EQU_GLOBAL_GAIN 0xf494
3372#define F367CAB_CRL_GAIN 0xf49400f8
3373#define F367CAB_CTR_INC_GAIN 0xf4940004
3374#define F367CAB_CTR_FRAC 0xf4940003
3375
3376/* EQU_CRL_LD_SEN */
3377#define R367CAB_EQU_CRL_LD_SEN 0xf495
3378#define F367CAB_CTR_BADPOINT_EN 0xf4950080
3379#define F367CAB_CTR_GAIN 0xf4950070
3380#define F367CAB_LIMANEN 0xf4950008
3381#define F367CAB_CRL_LD_SEN 0xf4950007
3382
3383/* EQU_CRL_LD_VAL */
3384#define R367CAB_EQU_CRL_LD_VAL 0xf496
3385#define F367CAB_CRL_BISTH_LIMIT 0xf4960080
3386#define F367CAB_CARE_EN 0xf4960040
3387#define F367CAB_CRL_LD_PER 0xf4960030
3388#define F367CAB_CRL_LD_WST 0xf496000c
3389#define F367CAB_CRL_LD_TFS 0xf4960003
3390
3391/* EQU_CRL_TFR */
3392#define R367CAB_EQU_CRL_TFR 0xf497
3393#define F367CAB_CRL_LD_TFR 0xf49700ff
3394
3395/* EQU_CRL_BISTH_LO */
3396#define R367CAB_EQU_CRL_BISTH_LO 0xf498
3397#define F367CAB_CRL_BISTH_LO 0xf49800ff
3398
3399/* EQU_CRL_BISTH_HI */
3400#define R367CAB_EQU_CRL_BISTH_HI 0xf499
3401#define F367CAB_CRL_BISTH_HI 0xf49900ff
3402
3403/* EQU_SWEEP_RANGE_LO */
3404#define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a
3405#define F367CAB_SWEEP_RANGE_LO 0xf49a00ff
3406
3407/* EQU_SWEEP_RANGE_HI */
3408#define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b
3409#define F367CAB_SWEEP_RANGE_HI 0xf49b00ff
3410
3411/* EQU_CRL_LIMITER */
3412#define R367CAB_EQU_CRL_LIMITER 0xf49c
3413#define F367CAB_BISECTOR_EN 0xf49c0080
3414#define F367CAB_PHEST128_EN 0xf49c0040
3415#define F367CAB_CRL_LIM 0xf49c003f
3416
3417/* EQU_MODULUS_MAP */
3418#define R367CAB_EQU_MODULUS_MAP 0xf49d
3419#define F367CAB_PNT_DEPTH 0xf49d00e0
3420#define F367CAB_MODULUS_CMP 0xf49d001f
3421
3422/* EQU_PNT_GAIN */
3423#define R367CAB_EQU_PNT_GAIN 0xf49e
3424#define F367CAB_PNT_EN 0xf49e0080
3425#define F367CAB_MODULUSMAP_EN 0xf49e0040
3426#define F367CAB_PNT_GAIN 0xf49e003f
3427
3428/* FEC_AC_CTR_0 */
3429#define R367CAB_FEC_AC_CTR_0 0xf4a8
3430#define F367CAB_BE_BYPASS 0xf4a80020
3431#define F367CAB_REFRESH47 0xf4a80010
3432#define F367CAB_CT_NBST 0xf4a80008
3433#define F367CAB_TEI_ENA 0xf4a80004
3434#define F367CAB_DS_ENA 0xf4a80002
3435#define F367CAB_TSMF_EN 0xf4a80001
3436
3437/* FEC_AC_CTR_1 */
3438#define R367CAB_FEC_AC_CTR_1 0xf4a9
3439#define F367CAB_DEINT_DEPTH 0xf4a900ff
3440
3441/* FEC_AC_CTR_2 */
3442#define R367CAB_FEC_AC_CTR_2 0xf4aa
3443#define F367CAB_DEINT_M 0xf4aa00f8
3444#define F367CAB_DIS_UNLOCK 0xf4aa0004
3445#define F367CAB_DESCR_MODE 0xf4aa0003
3446
3447/* FEC_AC_CTR_3 */
3448#define R367CAB_FEC_AC_CTR_3 0xf4ab
3449#define F367CAB_DI_UNLOCK 0xf4ab0080
3450#define F367CAB_DI_FREEZE 0xf4ab0040
3451#define F367CAB_MISMATCH 0xf4ab0030
3452#define F367CAB_ACQ_MODE 0xf4ab000c
3453#define F367CAB_TRK_MODE 0xf4ab0003
3454
3455/* FEC_STATUS */
3456#define R367CAB_FEC_STATUS 0xf4ac
3457#define F367CAB_DEINT_SMCNTR 0xf4ac00e0
3458#define F367CAB_DEINT_SYNCSTATE 0xf4ac0018
3459#define F367CAB_DEINT_SYNLOST 0xf4ac0004
3460#define F367CAB_DESCR_SYNCSTATE 0xf4ac0002
3461
3462/* RS_COUNTER_0 */
3463#define R367CAB_RS_COUNTER_0 0xf4ae
3464#define F367CAB_BK_CT_L 0xf4ae00ff
3465
3466/* RS_COUNTER_1 */
3467#define R367CAB_RS_COUNTER_1 0xf4af
3468#define F367CAB_BK_CT_H 0xf4af00ff
3469
3470/* RS_COUNTER_2 */
3471#define R367CAB_RS_COUNTER_2 0xf4b0
3472#define F367CAB_CORR_CT_L 0xf4b000ff
3473
3474/* RS_COUNTER_3 */
3475#define R367CAB_RS_COUNTER_3 0xf4b1
3476#define F367CAB_CORR_CT_H 0xf4b100ff
3477
3478/* RS_COUNTER_4 */
3479#define R367CAB_RS_COUNTER_4 0xf4b2
3480#define F367CAB_UNCORR_CT_L 0xf4b200ff
3481
3482/* RS_COUNTER_5 */
3483#define R367CAB_RS_COUNTER_5 0xf4b3
3484#define F367CAB_UNCORR_CT_H 0xf4b300ff
3485
3486/* BERT_0 */
3487#define R367CAB_BERT_0 0xf4b4
3488#define F367CAB_RS_NOCORR 0xf4b40004
3489#define F367CAB_CT_HOLD 0xf4b40002
3490#define F367CAB_CT_CLEAR 0xf4b40001
3491
3492/* BERT_1 */
3493#define R367CAB_BERT_1 0xf4b5
3494#define F367CAB_BERT_ON 0xf4b50020
3495#define F367CAB_BERT_ERR_SRC 0xf4b50010
3496#define F367CAB_BERT_ERR_MODE 0xf4b50008
3497#define F367CAB_BERT_NBYTE 0xf4b50007
3498
3499/* BERT_2 */
3500#define R367CAB_BERT_2 0xf4b6
3501#define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff
3502
3503/* BERT_3 */
3504#define R367CAB_BERT_3 0xf4b7
3505#define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff
3506
3507/* OUTFORMAT_0 */
3508#define R367CAB_OUTFORMAT_0 0xf4b8
3509#define F367CAB_CLK_POLARITY 0xf4b80080
3510#define F367CAB_FEC_TYPE 0xf4b80040
3511#define F367CAB_SYNC_STRIP 0xf4b80008
3512#define F367CAB_TS_SWAP 0xf4b80004
3513#define F367CAB_OUTFORMAT 0xf4b80003
3514
3515/* OUTFORMAT_1 */
3516#define R367CAB_OUTFORMAT_1 0xf4b9
3517#define F367CAB_CI_DIVRANGE 0xf4b900ff
3518
3519/* SMOOTHER_2 */
3520#define R367CAB_SMOOTHER_2 0xf4be
3521#define F367CAB_FIFO_BYPASS 0xf4be0020
3522
3523/* TSMF_CTRL_0 */
3524#define R367CAB_TSMF_CTRL_0 0xf4c0
3525#define F367CAB_TS_NUMBER 0xf4c0001e
3526#define F367CAB_SEL_MODE 0xf4c00001
3527
3528/* TSMF_CTRL_1 */
3529#define R367CAB_TSMF_CTRL_1 0xf4c1
3530#define F367CAB_CHECK_ERROR_BIT 0xf4c10080
3531#define F367CAB_CHCK_F_SYNC 0xf4c10040
3532#define F367CAB_H_MODE 0xf4c10008
3533#define F367CAB_D_V_MODE 0xf4c10004
3534#define F367CAB_MODE 0xf4c10003
3535
3536/* TSMF_CTRL_3 */
3537#define R367CAB_TSMF_CTRL_3 0xf4c3
3538#define F367CAB_SYNC_IN_COUNT 0xf4c300f0
3539#define F367CAB_SYNC_OUT_COUNT 0xf4c3000f
3540
3541/* TS_ON_ID_0 */
3542#define R367CAB_TS_ON_ID_0 0xf4c4
3543#define F367CAB_TS_ID_L 0xf4c400ff
3544
3545/* TS_ON_ID_1 */
3546#define R367CAB_TS_ON_ID_1 0xf4c5
3547#define F367CAB_TS_ID_H 0xf4c500ff
3548
3549/* TS_ON_ID_2 */
3550#define R367CAB_TS_ON_ID_2 0xf4c6
3551#define F367CAB_ON_ID_L 0xf4c600ff
3552
3553/* TS_ON_ID_3 */
3554#define R367CAB_TS_ON_ID_3 0xf4c7
3555#define F367CAB_ON_ID_H 0xf4c700ff
3556
3557/* RE_STATUS_0 */
3558#define R367CAB_RE_STATUS_0 0xf4c8
3559#define F367CAB_RECEIVE_STATUS_L 0xf4c800ff
3560
3561/* RE_STATUS_1 */
3562#define R367CAB_RE_STATUS_1 0xf4c9
3563#define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff
3564
3565/* RE_STATUS_2 */
3566#define R367CAB_RE_STATUS_2 0xf4ca
3567#define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff
3568
3569/* RE_STATUS_3 */
3570#define R367CAB_RE_STATUS_3 0xf4cb
3571#define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f
3572
3573/* TS_STATUS_0 */
3574#define R367CAB_TS_STATUS_0 0xf4cc
3575#define F367CAB_TS_STATUS_L 0xf4cc00ff
3576
3577/* TS_STATUS_1 */
3578#define R367CAB_TS_STATUS_1 0xf4cd
3579#define F367CAB_TS_STATUS_H 0xf4cd007f
3580
3581/* TS_STATUS_2 */
3582#define R367CAB_TS_STATUS_2 0xf4ce
3583#define F367CAB_ERROR 0xf4ce0080
3584#define F367CAB_EMERGENCY 0xf4ce0040
3585#define F367CAB_CRE_TS 0xf4ce0030
3586#define F367CAB_VER 0xf4ce000e
3587#define F367CAB_M_LOCK 0xf4ce0001
3588
3589/* TS_STATUS_3 */
3590#define R367CAB_TS_STATUS_3 0xf4cf
3591#define F367CAB_UPDATE_READY 0xf4cf0080
3592#define F367CAB_END_FRAME_HEADER 0xf4cf0040
3593#define F367CAB_CONTCNT 0xf4cf0020
3594#define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f
3595
3596/* T_O_ID_0 */
3597#define R367CAB_T_O_ID_0 0xf4d0
3598#define F367CAB_ON_ID_I_L 0xf4d000ff
3599
3600/* T_O_ID_1 */
3601#define R367CAB_T_O_ID_1 0xf4d1
3602#define F367CAB_ON_ID_I_H 0xf4d100ff
3603
3604/* T_O_ID_2 */
3605#define R367CAB_T_O_ID_2 0xf4d2
3606#define F367CAB_TS_ID_I_L 0xf4d200ff
3607
3608/* T_O_ID_3 */
3609#define R367CAB_T_O_ID_3 0xf4d3
3610#define F367CAB_TS_ID_I_H 0xf4d300ff
3611
3612#define STV0367CAB_NBREGS 187
3613
3614#endif
diff --git a/drivers/media/dvb/frontends/stv0900.h b/drivers/media/dvb/frontends/stv0900.h
index e3e35d1ce838..91c7ee8b2313 100644
--- a/drivers/media/dvb/frontends/stv0900.h
+++ b/drivers/media/dvb/frontends/stv0900.h
@@ -53,6 +53,8 @@ struct stv0900_config {
53 u8 tun2_type; 53 u8 tun2_type;
54 /* Set device param to start dma */ 54 /* Set device param to start dma */
55 int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured); 55 int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
56 /* Hook for Lock LED */
57 void (*set_lock_led)(struct dvb_frontend *fe, int offon);
56}; 58};
57 59
58#if defined(CONFIG_DVB_STV0900) || (defined(CONFIG_DVB_STV0900_MODULE) \ 60#if defined(CONFIG_DVB_STV0900) || (defined(CONFIG_DVB_STV0900_MODULE) \
diff --git a/drivers/media/dvb/frontends/stv0900_core.c b/drivers/media/dvb/frontends/stv0900_core.c
index 4f5e7d3a0e61..0ca316d6fffa 100644
--- a/drivers/media/dvb/frontends/stv0900_core.c
+++ b/drivers/media/dvb/frontends/stv0900_core.c
@@ -1604,6 +1604,9 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1604 p_search.standard = STV0900_AUTO_SEARCH; 1604 p_search.standard = STV0900_AUTO_SEARCH;
1605 p_search.iq_inversion = STV0900_IQ_AUTO; 1605 p_search.iq_inversion = STV0900_IQ_AUTO;
1606 p_search.search_algo = STV0900_BLIND_SEARCH; 1606 p_search.search_algo = STV0900_BLIND_SEARCH;
1607 /* Speeds up DVB-S searching */
1608 if (c->delivery_system == SYS_DVBS)
1609 p_search.standard = STV0900_SEARCH_DVBS1;
1607 1610
1608 intp->srch_standard[demod] = p_search.standard; 1611 intp->srch_standard[demod] = p_search.standard;
1609 intp->symbol_rate[demod] = p_search.symbol_rate; 1612 intp->symbol_rate[demod] = p_search.symbol_rate;
@@ -1660,8 +1663,14 @@ static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1660 | FE_HAS_VITERBI 1663 | FE_HAS_VITERBI
1661 | FE_HAS_SYNC 1664 | FE_HAS_SYNC
1662 | FE_HAS_LOCK; 1665 | FE_HAS_LOCK;
1663 } else 1666 if (state->config->set_lock_led)
1667 state->config->set_lock_led(fe, 1);
1668 } else {
1669 *status = 0;
1670 if (state->config->set_lock_led)
1671 state->config->set_lock_led(fe, 0);
1664 dprintk("DEMOD LOCK FAIL\n"); 1672 dprintk("DEMOD LOCK FAIL\n");
1673 }
1665 1674
1666 return 0; 1675 return 0;
1667} 1676}
@@ -1831,6 +1840,9 @@ static void stv0900_release(struct dvb_frontend *fe)
1831 1840
1832 dprintk("%s\n", __func__); 1841 dprintk("%s\n", __func__);
1833 1842
1843 if (state->config->set_lock_led)
1844 state->config->set_lock_led(fe, 0);
1845
1834 if ((--(state->internal->dmds_used)) <= 0) { 1846 if ((--(state->internal->dmds_used)) <= 0) {
1835 1847
1836 dprintk("%s: Actually removing\n", __func__); 1848 dprintk("%s: Actually removing\n", __func__);
@@ -1842,6 +1854,18 @@ static void stv0900_release(struct dvb_frontend *fe)
1842 kfree(state); 1854 kfree(state);
1843} 1855}
1844 1856
1857static int stv0900_sleep(struct dvb_frontend *fe)
1858{
1859 struct stv0900_state *state = fe->demodulator_priv;
1860
1861 dprintk("%s\n", __func__);
1862
1863 if (state->config->set_lock_led)
1864 state->config->set_lock_led(fe, 0);
1865
1866 return 0;
1867}
1868
1845static int stv0900_get_frontend(struct dvb_frontend *fe, 1869static int stv0900_get_frontend(struct dvb_frontend *fe,
1846 struct dvb_frontend_parameters *p) 1870 struct dvb_frontend_parameters *p)
1847{ 1871{
@@ -1876,6 +1900,7 @@ static struct dvb_frontend_ops stv0900_ops = {
1876 .release = stv0900_release, 1900 .release = stv0900_release,
1877 .init = stv0900_init, 1901 .init = stv0900_init,
1878 .get_frontend = stv0900_get_frontend, 1902 .get_frontend = stv0900_get_frontend,
1903 .sleep = stv0900_sleep,
1879 .get_frontend_algo = stv0900_frontend_algo, 1904 .get_frontend_algo = stv0900_frontend_algo,
1880 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl, 1905 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
1881 .diseqc_send_master_cmd = stv0900_send_master_cmd, 1906 .diseqc_send_master_cmd = stv0900_send_master_cmd,
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c
index 4e0fc2c8a41c..41d0f0a6655d 100644
--- a/drivers/media/dvb/frontends/stv090x.c
+++ b/drivers/media/dvb/frontends/stv090x.c
@@ -767,8 +767,12 @@ static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
767 * In case of any error, the lock is unlocked and exit within the 767 * In case of any error, the lock is unlocked and exit within the
768 * relevant operations themselves. 768 * relevant operations themselves.
769 */ 769 */
770 if (enable) 770 if (enable) {
771 mutex_lock(&state->internal->tuner_lock); 771 if (state->config->tuner_i2c_lock)
772 state->config->tuner_i2c_lock(&state->frontend, 1);
773 else
774 mutex_lock(&state->internal->tuner_lock);
775 }
772 776
773 reg = STV090x_READ_DEMOD(state, I2CRPT); 777 reg = STV090x_READ_DEMOD(state, I2CRPT);
774 if (enable) { 778 if (enable) {
@@ -784,13 +788,20 @@ static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
784 goto err; 788 goto err;
785 } 789 }
786 790
787 if (!enable) 791 if (!enable) {
788 mutex_unlock(&state->internal->tuner_lock); 792 if (state->config->tuner_i2c_lock)
793 state->config->tuner_i2c_lock(&state->frontend, 0);
794 else
795 mutex_unlock(&state->internal->tuner_lock);
796 }
789 797
790 return 0; 798 return 0;
791err: 799err:
792 dprintk(FE_ERROR, 1, "I/O error"); 800 dprintk(FE_ERROR, 1, "I/O error");
793 mutex_unlock(&state->internal->tuner_lock); 801 if (state->config->tuner_i2c_lock)
802 state->config->tuner_i2c_lock(&state->frontend, 0);
803 else
804 mutex_unlock(&state->internal->tuner_lock);
794 return -1; 805 return -1;
795} 806}
796 807
@@ -2883,10 +2894,12 @@ static int stv090x_optimize_track(struct stv090x_state *state)
2883 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); 2894 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2884 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 2895 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2885 goto err; 2896 goto err;
2886 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0) 2897 if (state->internal->dev_ver >= 0x30) {
2887 goto err; 2898 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2888 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0) 2899 goto err;
2889 goto err; 2900 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2901 goto err;
2902 }
2890 if (state->frame_len == STV090x_LONG_FRAME) { 2903 if (state->frame_len == STV090x_LONG_FRAME) {
2891 reg = STV090x_READ_DEMOD(state, DMDMODCOD); 2904 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2892 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); 2905 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
@@ -3846,6 +3859,7 @@ static int stv090x_sleep(struct dvb_frontend *fe)
3846{ 3859{
3847 struct stv090x_state *state = fe->demodulator_priv; 3860 struct stv090x_state *state = fe->demodulator_priv;
3848 u32 reg; 3861 u32 reg;
3862 u8 full_standby = 0;
3849 3863
3850 if (stv090x_i2c_gate_ctrl(state, 1) < 0) 3864 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3851 goto err; 3865 goto err;
@@ -3858,24 +3872,119 @@ static int stv090x_sleep(struct dvb_frontend *fe)
3858 if (stv090x_i2c_gate_ctrl(state, 0) < 0) 3872 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3859 goto err; 3873 goto err;
3860 3874
3861 dprintk(FE_DEBUG, 1, "Set %s to sleep", 3875 dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep",
3862 state->device == STV0900 ? "STV0900" : "STV0903"); 3876 state->device == STV0900 ? "STV0900" : "STV0903",
3877 state->demod);
3863 3878
3864 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 3879 mutex_lock(&state->internal->demod_lock);
3865 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3866 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3867 goto err;
3868 3880
3869 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 3881 switch (state->demod) {
3870 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); 3882 case STV090x_DEMODULATOR_0:
3871 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 3883 /* power off ADC 1 */
3872 goto err; 3884 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3885 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3886 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3887 goto err;
3888 /* power off DiSEqC 1 */
3889 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
3890 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
3891 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
3892 goto err;
3893
3894 /* check whether path 2 is already sleeping, that is when
3895 ADC2 is off */
3896 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3897 if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
3898 full_standby = 1;
3899
3900 /* stop clocks */
3901 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3902 /* packet delineator 1 clock */
3903 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
3904 /* ADC 1 clock */
3905 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
3906 /* FEC clock is shared between the two paths, only stop it
3907 when full standby is possible */
3908 if (full_standby)
3909 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3910 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3911 goto err;
3912 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
3913 /* sampling 1 clock */
3914 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
3915 /* viterbi 1 clock */
3916 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
3917 /* TS clock is shared between the two paths, only stop it
3918 when full standby is possible */
3919 if (full_standby)
3920 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
3921 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3922 goto err;
3923 break;
3924
3925 case STV090x_DEMODULATOR_1:
3926 /* power off ADC 2 */
3927 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3928 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
3929 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
3930 goto err;
3931 /* power off DiSEqC 2 */
3932 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
3933 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
3934 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
3935 goto err;
3936
3937 /* check whether path 1 is already sleeping, that is when
3938 ADC1 is off */
3939 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3940 if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
3941 full_standby = 1;
3942
3943 /* stop clocks */
3944 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3945 /* packet delineator 2 clock */
3946 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
3947 /* ADC 2 clock */
3948 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
3949 /* FEC clock is shared between the two paths, only stop it
3950 when full standby is possible */
3951 if (full_standby)
3952 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3953 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3954 goto err;
3955 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
3956 /* sampling 2 clock */
3957 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
3958 /* viterbi 2 clock */
3959 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
3960 /* TS clock is shared between the two paths, only stop it
3961 when full standby is possible */
3962 if (full_standby)
3963 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
3964 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3965 goto err;
3966 break;
3873 3967
3968 default:
3969 dprintk(FE_ERROR, 1, "Wrong demodulator!");
3970 break;
3971 }
3972
3973 if (full_standby) {
3974 /* general power off */
3975 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3976 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3977 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3978 goto err;
3979 }
3980
3981 mutex_unlock(&state->internal->demod_lock);
3874 return 0; 3982 return 0;
3875 3983
3876err_gateoff: 3984err_gateoff:
3877 stv090x_i2c_gate_ctrl(state, 0); 3985 stv090x_i2c_gate_ctrl(state, 0);
3878err: 3986err:
3987 mutex_unlock(&state->internal->demod_lock);
3879 dprintk(FE_ERROR, 1, "I/O error"); 3988 dprintk(FE_ERROR, 1, "I/O error");
3880 return -1; 3989 return -1;
3881} 3990}
@@ -3885,21 +3994,94 @@ static int stv090x_wakeup(struct dvb_frontend *fe)
3885 struct stv090x_state *state = fe->demodulator_priv; 3994 struct stv090x_state *state = fe->demodulator_priv;
3886 u32 reg; 3995 u32 reg;
3887 3996
3888 dprintk(FE_DEBUG, 1, "Wake %s from standby", 3997 dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby",
3889 state->device == STV0900 ? "STV0900" : "STV0903"); 3998 state->device == STV0900 ? "STV0900" : "STV0903",
3999 state->demod);
4000
4001 mutex_lock(&state->internal->demod_lock);
3890 4002
4003 /* general power on */
3891 reg = stv090x_read_reg(state, STV090x_SYNTCTRL); 4004 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3892 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); 4005 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3893 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) 4006 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3894 goto err; 4007 goto err;
3895 4008
3896 reg = stv090x_read_reg(state, STV090x_TSTTNR1); 4009 switch (state->demod) {
3897 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); 4010 case STV090x_DEMODULATOR_0:
3898 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) 4011 /* power on ADC 1 */
3899 goto err; 4012 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4013 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
4014 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4015 goto err;
4016 /* power on DiSEqC 1 */
4017 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
4018 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
4019 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
4020 goto err;
4021
4022 /* activate clocks */
4023 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4024 /* packet delineator 1 clock */
4025 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
4026 /* ADC 1 clock */
4027 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
4028 /* FEC clock */
4029 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4030 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4031 goto err;
4032 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4033 /* sampling 1 clock */
4034 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
4035 /* viterbi 1 clock */
4036 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
4037 /* TS clock */
4038 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4039 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4040 goto err;
4041 break;
3900 4042
4043 case STV090x_DEMODULATOR_1:
4044 /* power on ADC 2 */
4045 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4046 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
4047 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4048 goto err;
4049 /* power on DiSEqC 2 */
4050 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
4051 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
4052 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4053 goto err;
4054
4055 /* activate clocks */
4056 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4057 /* packet delineator 2 clock */
4058 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
4059 /* ADC 2 clock */
4060 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
4061 /* FEC clock */
4062 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4063 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4064 goto err;
4065 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4066 /* sampling 2 clock */
4067 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
4068 /* viterbi 2 clock */
4069 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
4070 /* TS clock */
4071 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4072 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4073 goto err;
4074 break;
4075
4076 default:
4077 dprintk(FE_ERROR, 1, "Wrong demodulator!");
4078 break;
4079 }
4080
4081 mutex_unlock(&state->internal->demod_lock);
3901 return 0; 4082 return 0;
3902err: 4083err:
4084 mutex_unlock(&state->internal->demod_lock);
3903 dprintk(FE_ERROR, 1, "I/O error"); 4085 dprintk(FE_ERROR, 1, "I/O error");
3904 return -1; 4086 return -1;
3905} 4087}
@@ -4169,6 +4351,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
4169 switch (state->config->ts1_mode) { 4351 switch (state->config->ts1_mode) {
4170 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4352 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4171 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4353 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4354 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4172 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4355 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4173 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4356 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4174 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4357 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
@@ -4177,6 +4360,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
4177 4360
4178 case STV090x_TSMODE_DVBCI: 4361 case STV090x_TSMODE_DVBCI:
4179 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4362 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4363 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4180 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4364 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4181 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4365 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4182 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4366 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
@@ -4185,6 +4369,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
4185 4369
4186 case STV090x_TSMODE_SERIAL_PUNCTURED: 4370 case STV090x_TSMODE_SERIAL_PUNCTURED:
4187 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4371 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4372 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4188 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4373 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4189 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4374 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4190 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4375 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
@@ -4193,6 +4378,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
4193 4378
4194 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4379 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4195 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); 4380 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4381 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4196 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4382 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4197 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4383 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4198 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) 4384 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
@@ -4206,6 +4392,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
4206 switch (state->config->ts2_mode) { 4392 switch (state->config->ts2_mode) {
4207 case STV090x_TSMODE_PARALLEL_PUNCTURED: 4393 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4208 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4394 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4395 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4209 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4396 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4210 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4397 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4211 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4398 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4214,6 +4401,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
4214 4401
4215 case STV090x_TSMODE_DVBCI: 4402 case STV090x_TSMODE_DVBCI:
4216 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4403 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4404 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4217 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); 4405 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4218 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4406 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4219 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4407 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4222,6 +4410,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
4222 4410
4223 case STV090x_TSMODE_SERIAL_PUNCTURED: 4411 case STV090x_TSMODE_SERIAL_PUNCTURED:
4224 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4412 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4413 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4225 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4414 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4226 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); 4415 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4227 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4416 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4230,6 +4419,7 @@ static int stv090x_set_tspath(struct stv090x_state *state)
4230 4419
4231 case STV090x_TSMODE_SERIAL_CONTINUOUS: 4420 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4232 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); 4421 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4422 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4233 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); 4423 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4234 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); 4424 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4235 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) 4425 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
@@ -4506,16 +4696,26 @@ static int stv090x_setup(struct dvb_frontend *fe)
4506 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0) 4696 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4507 goto err; 4697 goto err;
4508 4698
4509 /* workaround for stuck DiSEqC output */
4510 if (config->diseqc_envelope_mode)
4511 stv090x_send_diseqc_burst(fe, SEC_MINI_A);
4512
4513 return 0; 4699 return 0;
4514err: 4700err:
4515 dprintk(FE_ERROR, 1, "I/O error"); 4701 dprintk(FE_ERROR, 1, "I/O error");
4516 return -1; 4702 return -1;
4517} 4703}
4518 4704
4705int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir, u8 value,
4706 u8 xor_value)
4707{
4708 struct stv090x_state *state = fe->demodulator_priv;
4709 u8 reg = 0;
4710
4711 STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
4712 STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
4713 STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
4714
4715 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
4716}
4717EXPORT_SYMBOL(stv090x_set_gpio);
4718
4519static struct dvb_frontend_ops stv090x_ops = { 4719static struct dvb_frontend_ops stv090x_ops = {
4520 4720
4521 .info = { 4721 .info = {
@@ -4580,39 +4780,35 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4580 state->internal = temp_int->internal; 4780 state->internal = temp_int->internal;
4581 state->internal->num_used++; 4781 state->internal->num_used++;
4582 dprintk(FE_INFO, 1, "Found Internal Structure!"); 4782 dprintk(FE_INFO, 1, "Found Internal Structure!");
4583 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4584 state->device == STV0900 ? "STV0900" : "STV0903",
4585 demod,
4586 state->internal->dev_ver);
4587 return &state->frontend;
4588 } else { 4783 } else {
4589 state->internal = kmalloc(sizeof(struct stv090x_internal), 4784 state->internal = kmalloc(sizeof(struct stv090x_internal),
4590 GFP_KERNEL); 4785 GFP_KERNEL);
4786 if (!state->internal)
4787 goto error;
4591 temp_int = append_internal(state->internal); 4788 temp_int = append_internal(state->internal);
4789 if (!temp_int) {
4790 kfree(state->internal);
4791 goto error;
4792 }
4592 state->internal->num_used = 1; 4793 state->internal->num_used = 1;
4593 state->internal->mclk = 0; 4794 state->internal->mclk = 0;
4594 state->internal->dev_ver = 0; 4795 state->internal->dev_ver = 0;
4595 state->internal->i2c_adap = state->i2c; 4796 state->internal->i2c_adap = state->i2c;
4596 state->internal->i2c_addr = state->config->address; 4797 state->internal->i2c_addr = state->config->address;
4597 dprintk(FE_INFO, 1, "Create New Internal Structure!"); 4798 dprintk(FE_INFO, 1, "Create New Internal Structure!");
4598 }
4599 4799
4600 mutex_init(&state->internal->demod_lock); 4800 mutex_init(&state->internal->demod_lock);
4601 mutex_init(&state->internal->tuner_lock); 4801 mutex_init(&state->internal->tuner_lock);
4602 4802
4603 if (stv090x_sleep(&state->frontend) < 0) { 4803 if (stv090x_setup(&state->frontend) < 0) {
4604 dprintk(FE_ERROR, 1, "Error putting device to sleep"); 4804 dprintk(FE_ERROR, 1, "Error setting up device");
4605 goto error; 4805 goto err_remove;
4806 }
4606 } 4807 }
4607 4808
4608 if (stv090x_setup(&state->frontend) < 0) { 4809 /* workaround for stuck DiSEqC output */
4609 dprintk(FE_ERROR, 1, "Error setting up device"); 4810 if (config->diseqc_envelope_mode)
4610 goto error; 4811 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
4611 }
4612 if (stv090x_wakeup(&state->frontend) < 0) {
4613 dprintk(FE_ERROR, 1, "Error waking device");
4614 goto error;
4615 }
4616 4812
4617 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x", 4813 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4618 state->device == STV0900 ? "STV0900" : "STV0903", 4814 state->device == STV0900 ? "STV0900" : "STV0903",
@@ -4621,6 +4817,9 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4621 4817
4622 return &state->frontend; 4818 return &state->frontend;
4623 4819
4820err_remove:
4821 remove_dev(state->internal);
4822 kfree(state->internal);
4624error: 4823error:
4625 kfree(state); 4824 kfree(state);
4626 return NULL; 4825 return NULL;
diff --git a/drivers/media/dvb/frontends/stv090x.h b/drivers/media/dvb/frontends/stv090x.h
index dd1b93ae4e9d..29cdc2b71314 100644
--- a/drivers/media/dvb/frontends/stv090x.h
+++ b/drivers/media/dvb/frontends/stv090x.h
@@ -78,6 +78,9 @@ struct stv090x_config {
78 u32 ts1_clk; 78 u32 ts1_clk;
79 u32 ts2_clk; 79 u32 ts2_clk;
80 80
81 u8 ts1_tei : 1;
82 u8 ts2_tei : 1;
83
81 enum stv090x_i2crpt repeater_level; 84 enum stv090x_i2crpt repeater_level;
82 85
83 u8 tuner_bbgain; /* default: 10db */ 86 u8 tuner_bbgain; /* default: 10db */
@@ -97,6 +100,7 @@ struct stv090x_config {
97 int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain); 100 int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain);
98 int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk); 101 int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk);
99 int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status); 102 int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status);
103 void (*tuner_i2c_lock) (struct dvb_frontend *fe, int lock);
100}; 104};
101 105
102#if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE)) 106#if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE))
@@ -104,6 +108,11 @@ struct stv090x_config {
104extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, 108extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
105 struct i2c_adapter *i2c, 109 struct i2c_adapter *i2c,
106 enum stv090x_demodulator demod); 110 enum stv090x_demodulator demod);
111
112/* dir = 0 -> output, dir = 1 -> input/open-drain */
113extern int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio,
114 u8 dir, u8 value, u8 xor_value);
115
107#else 116#else
108 117
109static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, 118static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
@@ -113,6 +122,13 @@ static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *c
113 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 122 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
114 return NULL; 123 return NULL;
115} 124}
125
126static inline int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio,
127 u8 opd, u8 value, u8 xor_value)
128{
129 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
130 return -ENODEV;
131}
116#endif /* CONFIG_DVB_STV090x */ 132#endif /* CONFIG_DVB_STV090x */
117 133
118#endif /* __STV090x_H */ 134#endif /* __STV090x_H */
diff --git a/drivers/media/dvb/frontends/stv090x_reg.h b/drivers/media/dvb/frontends/stv090x_reg.h
index 2502855dd784..93741ee14297 100644
--- a/drivers/media/dvb/frontends/stv090x_reg.h
+++ b/drivers/media/dvb/frontends/stv090x_reg.h
@@ -1327,10 +1327,10 @@
1327#define STV090x_WIDTH_Px_NOSPLHT_UNNORMED_FIELD 8 1327#define STV090x_WIDTH_Px_NOSPLHT_UNNORMED_FIELD 8
1328 1328
1329#define STV090x_Px_NOSPLHy(__x, __y) (0xf48f - (__x - 1) * 0x200 - __y * 0x1) 1329#define STV090x_Px_NOSPLHy(__x, __y) (0xf48f - (__x - 1) * 0x200 - __y * 0x1)
1330#define STv090x_P1_NOSPLH0 STV090x_Px_NOSPLHy(1, 0) 1330#define STV090x_P1_NOSPLH0 STV090x_Px_NOSPLHy(1, 0)
1331#define STv090x_P1_NOSPLH1 STV090x_Px_NOSPLHy(1, 1) 1331#define STV090x_P1_NOSPLH1 STV090x_Px_NOSPLHy(1, 1)
1332#define STv090x_P2_NOSPLH0 STV090x_Px_NOSPLHy(2, 0) 1332#define STV090x_P2_NOSPLH0 STV090x_Px_NOSPLHy(2, 0)
1333#define STv090x_P2_NOSPLH1 STV090x_Px_NOSPLHy(2, 1) 1333#define STV090x_P2_NOSPLH1 STV090x_Px_NOSPLHy(2, 1)
1334#define STV090x_OFFST_Px_NOSPLH_UNNORMED_FIELD 0 1334#define STV090x_OFFST_Px_NOSPLH_UNNORMED_FIELD 0
1335#define STV090x_WIDTH_Px_NOSPLH_UNNORMED_FIELD 8 1335#define STV090x_WIDTH_Px_NOSPLH_UNNORMED_FIELD 8
1336 1336
@@ -1406,7 +1406,7 @@
1406 1406
1407#define STV090x_Px_BCLC2S28(__x) (0xf49d - (__x - 1) * 0x200) 1407#define STV090x_Px_BCLC2S28(__x) (0xf49d - (__x - 1) * 0x200)
1408#define STV090x_P1_BCLC2S28 STV090x_Px_BCLC2S28(1) 1408#define STV090x_P1_BCLC2S28 STV090x_Px_BCLC2S28(1)
1409#define STV090x_P2_BCLC2S28 STV090x_Px_BCLC2S28(1) 1409#define STV090x_P2_BCLC2S28 STV090x_Px_BCLC2S28(2)
1410#define STV090x_OFFST_Px_CAR2S2_8_BETA_M_FIELD 4 1410#define STV090x_OFFST_Px_CAR2S2_8_BETA_M_FIELD 4
1411#define STV090x_WIDTH_Px_CAR2S2_8_BETA_M_FIELD 2 1411#define STV090x_WIDTH_Px_CAR2S2_8_BETA_M_FIELD 2
1412#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0 1412#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0
@@ -1414,7 +1414,7 @@
1414 1414
1415#define STV090x_Px_BCLC2S216A(__x) (0xf49e - (__x - 1) * 0x200) 1415#define STV090x_Px_BCLC2S216A(__x) (0xf49e - (__x - 1) * 0x200)
1416#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1) 1416#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1)
1417#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(1) 1417#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(2)
1418#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4 1418#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4
1419#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_M_FIELD 2 1419#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_M_FIELD 2
1420#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0 1420#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0
@@ -1422,7 +1422,7 @@
1422 1422
1423#define STV090x_Px_BCLC2S232A(__x) (0xf49f - (__x - 1) * 0x200) 1423#define STV090x_Px_BCLC2S232A(__x) (0xf49f - (__x - 1) * 0x200)
1424#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1) 1424#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1)
1425#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(1) 1425#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(2)
1426#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4 1426#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4
1427#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_M_FIELD 2 1427#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_M_FIELD 2
1428#define STV090x_OFFST_Px_CAR2S2_32A_BETA_E_FIELD 0 1428#define STV090x_OFFST_Px_CAR2S2_32A_BETA_E_FIELD 0
@@ -1602,7 +1602,7 @@
1602 1602
1603#define STV090x_Px_CCIACC(__x) (0xf4c4 - (__x - 1) * 0x200) 1603#define STV090x_Px_CCIACC(__x) (0xf4c4 - (__x - 1) * 0x200)
1604#define STV090x_P1_CCIACC STV090x_Px_CCIACC(1) 1604#define STV090x_P1_CCIACC STV090x_Px_CCIACC(1)
1605#define STV090x_P2_CCIACC STV090x_Px_CCIACC(1) 1605#define STV090x_P2_CCIACC STV090x_Px_CCIACC(2)
1606#define STV090x_OFFST_Px_CCI_VALUE_FIELD 0 1606#define STV090x_OFFST_Px_CCI_VALUE_FIELD 0
1607#define STV090x_WIDTH_Px_CCI_VALUE_FIELD 8 1607#define STV090x_WIDTH_Px_CCI_VALUE_FIELD 8
1608 1608
diff --git a/drivers/media/dvb/frontends/zl10036.c b/drivers/media/dvb/frontends/zl10036.c
index 4627f491656b..81aa984c551f 100644
--- a/drivers/media/dvb/frontends/zl10036.c
+++ b/drivers/media/dvb/frontends/zl10036.c
@@ -463,16 +463,16 @@ struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
463 const struct zl10036_config *config, 463 const struct zl10036_config *config,
464 struct i2c_adapter *i2c) 464 struct i2c_adapter *i2c)
465{ 465{
466 struct zl10036_state *state = NULL; 466 struct zl10036_state *state;
467 int ret; 467 int ret;
468 468
469 if (NULL == config) { 469 if (!config) {
470 printk(KERN_ERR "%s: no config specified", __func__); 470 printk(KERN_ERR "%s: no config specified", __func__);
471 goto error; 471 return NULL;
472 } 472 }
473 473
474 state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL); 474 state = kzalloc(sizeof(struct zl10036_state), GFP_KERNEL);
475 if (NULL == state) 475 if (!state)
476 return NULL; 476 return NULL;
477 477
478 state->config = config; 478 state->config = config;
@@ -507,7 +507,7 @@ struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe,
507 return fe; 507 return fe;
508 508
509error: 509error:
510 zl10036_release(fe); 510 kfree(state);
511 return NULL; 511 return NULL;
512} 512}
513EXPORT_SYMBOL(zl10036_attach); 513EXPORT_SYMBOL(zl10036_attach);
diff --git a/drivers/media/dvb/ngene/Makefile b/drivers/media/dvb/ngene/Makefile
index 0608aabb14ee..2bc96874d044 100644
--- a/drivers/media/dvb/ngene/Makefile
+++ b/drivers/media/dvb/ngene/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_DVB_NGENE) += ngene.o
9EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ 9EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/
10EXTRA_CFLAGS += -Idrivers/media/dvb/frontends/ 10EXTRA_CFLAGS += -Idrivers/media/dvb/frontends/
11EXTRA_CFLAGS += -Idrivers/media/common/tuners/ 11EXTRA_CFLAGS += -Idrivers/media/common/tuners/
12
13# For the staging CI driver cxd2099
14EXTRA_CFLAGS += -Idrivers/staging/cxd2099/
diff --git a/drivers/media/dvb/ngene/ngene-cards.c b/drivers/media/dvb/ngene/ngene-cards.c
index 4692a41ad95b..fcf4be901ec8 100644
--- a/drivers/media/dvb/ngene/ngene-cards.c
+++ b/drivers/media/dvb/ngene/ngene-cards.c
@@ -48,20 +48,27 @@
48 48
49static int tuner_attach_stv6110(struct ngene_channel *chan) 49static int tuner_attach_stv6110(struct ngene_channel *chan)
50{ 50{
51 struct i2c_adapter *i2c;
51 struct stv090x_config *feconf = (struct stv090x_config *) 52 struct stv090x_config *feconf = (struct stv090x_config *)
52 chan->dev->card_info->fe_config[chan->number]; 53 chan->dev->card_info->fe_config[chan->number];
53 struct stv6110x_config *tunerconf = (struct stv6110x_config *) 54 struct stv6110x_config *tunerconf = (struct stv6110x_config *)
54 chan->dev->card_info->tuner_config[chan->number]; 55 chan->dev->card_info->tuner_config[chan->number];
55 struct stv6110x_devctl *ctl; 56 struct stv6110x_devctl *ctl;
56 57
57 ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf, 58 /* tuner 1+2: i2c adapter #0, tuner 3+4: i2c adapter #1 */
58 &chan->i2c_adapter); 59 if (chan->number < 2)
60 i2c = &chan->dev->channel[0].i2c_adapter;
61 else
62 i2c = &chan->dev->channel[1].i2c_adapter;
63
64 ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf, i2c);
59 if (ctl == NULL) { 65 if (ctl == NULL) {
60 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n"); 66 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
61 return -ENODEV; 67 return -ENODEV;
62 } 68 }
63 69
64 feconf->tuner_init = ctl->tuner_init; 70 feconf->tuner_init = ctl->tuner_init;
71 feconf->tuner_sleep = ctl->tuner_sleep;
65 feconf->tuner_set_mode = ctl->tuner_set_mode; 72 feconf->tuner_set_mode = ctl->tuner_set_mode;
66 feconf->tuner_set_frequency = ctl->tuner_set_frequency; 73 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
67 feconf->tuner_get_frequency = ctl->tuner_get_frequency; 74 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
@@ -78,29 +85,106 @@ static int tuner_attach_stv6110(struct ngene_channel *chan)
78 85
79static int demod_attach_stv0900(struct ngene_channel *chan) 86static int demod_attach_stv0900(struct ngene_channel *chan)
80{ 87{
88 struct i2c_adapter *i2c;
81 struct stv090x_config *feconf = (struct stv090x_config *) 89 struct stv090x_config *feconf = (struct stv090x_config *)
82 chan->dev->card_info->fe_config[chan->number]; 90 chan->dev->card_info->fe_config[chan->number];
83 91
84 chan->fe = dvb_attach(stv090x_attach, 92 /* tuner 1+2: i2c adapter #0, tuner 3+4: i2c adapter #1 */
85 feconf, 93 /* Note: Both adapters share the same i2c bus, but the demod */
86 &chan->i2c_adapter, 94 /* driver requires that each demod has its own i2c adapter */
87 chan->number == 0 ? STV090x_DEMODULATOR_0 : 95 if (chan->number < 2)
88 STV090x_DEMODULATOR_1); 96 i2c = &chan->dev->channel[0].i2c_adapter;
97 else
98 i2c = &chan->dev->channel[1].i2c_adapter;
99
100 chan->fe = dvb_attach(stv090x_attach, feconf, i2c,
101 (chan->number & 1) == 0 ? STV090x_DEMODULATOR_0
102 : STV090x_DEMODULATOR_1);
89 if (chan->fe == NULL) { 103 if (chan->fe == NULL) {
90 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n"); 104 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
91 return -ENODEV; 105 return -ENODEV;
92 } 106 }
93 107
94 if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0, 108 /* store channel info */
109 if (feconf->tuner_i2c_lock)
110 chan->fe->analog_demod_priv = chan;
111
112 if (!dvb_attach(lnbh24_attach, chan->fe, i2c, 0,
95 0, chan->dev->card_info->lnb[chan->number])) { 113 0, chan->dev->card_info->lnb[chan->number])) {
96 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n"); 114 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
97 dvb_frontend_detach(chan->fe); 115 dvb_frontend_detach(chan->fe);
116 chan->fe = NULL;
117 return -ENODEV;
118 }
119
120 return 0;
121}
122
123static void cineS2_tuner_i2c_lock(struct dvb_frontend *fe, int lock)
124{
125 struct ngene_channel *chan = fe->analog_demod_priv;
126
127 if (lock)
128 down(&chan->dev->pll_mutex);
129 else
130 up(&chan->dev->pll_mutex);
131}
132
133static int cineS2_probe(struct ngene_channel *chan)
134{
135 struct i2c_adapter *i2c;
136 struct stv090x_config *fe_conf;
137 u8 buf[3];
138 struct i2c_msg i2c_msg = { .flags = 0, .buf = buf };
139 int rc;
140
141 /* tuner 1+2: i2c adapter #0, tuner 3+4: i2c adapter #1 */
142 if (chan->number < 2)
143 i2c = &chan->dev->channel[0].i2c_adapter;
144 else
145 i2c = &chan->dev->channel[1].i2c_adapter;
146
147 fe_conf = chan->dev->card_info->fe_config[chan->number];
148 i2c_msg.addr = fe_conf->address;
149
150 /* probe demod */
151 i2c_msg.len = 2;
152 buf[0] = 0xf1;
153 buf[1] = 0x00;
154 rc = i2c_transfer(i2c, &i2c_msg, 1);
155 if (rc != 1)
156 return -ENODEV;
157
158 /* demod found, attach it */
159 rc = demod_attach_stv0900(chan);
160 if (rc < 0 || chan->number < 2)
161 return rc;
162
163 /* demod #2: reprogram outputs DPN1 & DPN2 */
164 i2c_msg.len = 3;
165 buf[0] = 0xf1;
166 switch (chan->number) {
167 case 2:
168 buf[1] = 0x5c;
169 buf[2] = 0xc2;
170 break;
171 case 3:
172 buf[1] = 0x61;
173 buf[2] = 0xcc;
174 break;
175 default:
98 return -ENODEV; 176 return -ENODEV;
99 } 177 }
178 rc = i2c_transfer(i2c, &i2c_msg, 1);
179 if (rc != 1) {
180 printk(KERN_ERR DEVICE_NAME ": could not setup DPNx\n");
181 return -EIO;
182 }
100 183
101 return 0; 184 return 0;
102} 185}
103 186
187
104static struct lgdt330x_config aver_m780 = { 188static struct lgdt330x_config aver_m780 = {
105 .demod_address = 0xb2 >> 1, 189 .demod_address = 0xb2 >> 1,
106 .demod_chip = LGDT3303, 190 .demod_chip = LGDT3303,
@@ -151,6 +235,29 @@ static struct stv090x_config fe_cineS2 = {
151 .adc2_range = STV090x_ADC_1Vpp, 235 .adc2_range = STV090x_ADC_1Vpp,
152 236
153 .diseqc_envelope_mode = true, 237 .diseqc_envelope_mode = true,
238
239 .tuner_i2c_lock = cineS2_tuner_i2c_lock,
240};
241
242static struct stv090x_config fe_cineS2_2 = {
243 .device = STV0900,
244 .demod_mode = STV090x_DUAL,
245 .clk_mode = STV090x_CLK_EXT,
246
247 .xtal = 27000000,
248 .address = 0x69,
249
250 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
251 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
252
253 .repeater_level = STV090x_RPTLEVEL_16,
254
255 .adc1_range = STV090x_ADC_1Vpp,
256 .adc2_range = STV090x_ADC_1Vpp,
257
258 .diseqc_envelope_mode = true,
259
260 .tuner_i2c_lock = cineS2_tuner_i2c_lock,
154}; 261};
155 262
156static struct stv6110x_config tuner_cineS2_0 = { 263static struct stv6110x_config tuner_cineS2_0 = {
@@ -175,7 +282,8 @@ static struct ngene_info ngene_info_cineS2 = {
175 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1}, 282 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1},
176 .lnb = {0x0b, 0x08}, 283 .lnb = {0x0b, 0x08},
177 .tsf = {3, 3}, 284 .tsf = {3, 3},
178 .fw_version = 15, 285 .fw_version = 18,
286 .msi_supported = true,
179}; 287};
180 288
181static struct ngene_info ngene_info_satixS2 = { 289static struct ngene_info ngene_info_satixS2 = {
@@ -188,46 +296,54 @@ static struct ngene_info ngene_info_satixS2 = {
188 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1}, 296 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1},
189 .lnb = {0x0b, 0x08}, 297 .lnb = {0x0b, 0x08},
190 .tsf = {3, 3}, 298 .tsf = {3, 3},
191 .fw_version = 15, 299 .fw_version = 18,
300 .msi_supported = true,
192}; 301};
193 302
194static struct ngene_info ngene_info_satixS2v2 = { 303static struct ngene_info ngene_info_satixS2v2 = {
195 .type = NGENE_SIDEWINDER, 304 .type = NGENE_SIDEWINDER,
196 .name = "Mystique SaTiX-S2 Dual (v2)", 305 .name = "Mystique SaTiX-S2 Dual (v2)",
197 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, 306 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
198 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, 307 NGENE_IO_TSOUT},
199 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110}, 308 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900, cineS2_probe, cineS2_probe},
200 .fe_config = {&fe_cineS2, &fe_cineS2}, 309 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110},
201 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1}, 310 .fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
202 .lnb = {0x0a, 0x08}, 311 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
312 .lnb = {0x0a, 0x08, 0x0b, 0x09},
203 .tsf = {3, 3}, 313 .tsf = {3, 3},
204 .fw_version = 15, 314 .fw_version = 18,
315 .msi_supported = true,
205}; 316};
206 317
207static struct ngene_info ngene_info_cineS2v5 = { 318static struct ngene_info ngene_info_cineS2v5 = {
208 .type = NGENE_SIDEWINDER, 319 .type = NGENE_SIDEWINDER,
209 .name = "Linux4Media cineS2 DVB-S2 Twin Tuner (v5)", 320 .name = "Linux4Media cineS2 DVB-S2 Twin Tuner (v5)",
210 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, 321 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
211 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, 322 NGENE_IO_TSOUT},
212 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110}, 323 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900, cineS2_probe, cineS2_probe},
213 .fe_config = {&fe_cineS2, &fe_cineS2}, 324 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110},
214 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1}, 325 .fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
215 .lnb = {0x0a, 0x08}, 326 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
327 .lnb = {0x0a, 0x08, 0x0b, 0x09},
216 .tsf = {3, 3}, 328 .tsf = {3, 3},
217 .fw_version = 15, 329 .fw_version = 18,
330 .msi_supported = true,
218}; 331};
219 332
333
220static struct ngene_info ngene_info_duoFlexS2 = { 334static struct ngene_info ngene_info_duoFlexS2 = {
221 .type = NGENE_SIDEWINDER, 335 .type = NGENE_SIDEWINDER,
222 .name = "Digital Devices DuoFlex S2 miniPCIe", 336 .name = "Digital Devices DuoFlex S2 miniPCIe",
223 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, 337 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN, NGENE_IO_TSIN,
224 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, 338 NGENE_IO_TSOUT},
225 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110}, 339 .demod_attach = {cineS2_probe, cineS2_probe, cineS2_probe, cineS2_probe},
226 .fe_config = {&fe_cineS2, &fe_cineS2}, 340 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110, tuner_attach_stv6110},
227 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1}, 341 .fe_config = {&fe_cineS2, &fe_cineS2, &fe_cineS2_2, &fe_cineS2_2},
228 .lnb = {0x0a, 0x08}, 342 .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1, &tuner_cineS2_0, &tuner_cineS2_1},
343 .lnb = {0x0a, 0x08, 0x0b, 0x09},
229 .tsf = {3, 3}, 344 .tsf = {3, 3},
230 .fw_version = 15, 345 .fw_version = 18,
346 .msi_supported = true,
231}; 347};
232 348
233static struct ngene_info ngene_info_m780 = { 349static struct ngene_info ngene_info_m780 = {
@@ -321,6 +437,7 @@ static struct pci_driver ngene_pci_driver = {
321 .probe = ngene_probe, 437 .probe = ngene_probe,
322 .remove = __devexit_p(ngene_remove), 438 .remove = __devexit_p(ngene_remove),
323 .err_handler = &ngene_errors, 439 .err_handler = &ngene_errors,
440 .shutdown = ngene_shutdown,
324}; 441};
325 442
326static __init int module_init_ngene(void) 443static __init int module_init_ngene(void)
diff --git a/drivers/media/dvb/ngene/ngene-core.c b/drivers/media/dvb/ngene/ngene-core.c
index dc073bdc623a..175a0f6c2a4c 100644
--- a/drivers/media/dvb/ngene/ngene-core.c
+++ b/drivers/media/dvb/ngene/ngene-core.c
@@ -45,6 +45,9 @@ static int one_adapter = 1;
45module_param(one_adapter, int, 0444); 45module_param(one_adapter, int, 0444);
46MODULE_PARM_DESC(one_adapter, "Use only one adapter."); 46MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
47 47
48static int shutdown_workaround;
49module_param(shutdown_workaround, int, 0644);
50MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets.");
48 51
49static int debug; 52static int debug;
50module_param(debug, int, 0444); 53module_param(debug, int, 0444);
@@ -143,7 +146,7 @@ static void demux_tasklet(unsigned long data)
143 } 146 }
144 } else { 147 } else {
145 if (chan->HWState == HWSTATE_RUN) { 148 if (chan->HWState == HWSTATE_RUN) {
146 u32 Flags = 0; 149 u32 Flags = chan->DataFormatFlags;
147 IBufferExchange *exch1 = chan->pBufferExchange; 150 IBufferExchange *exch1 = chan->pBufferExchange;
148 IBufferExchange *exch2 = chan->pBufferExchange2; 151 IBufferExchange *exch2 = chan->pBufferExchange2;
149 if (Cur->ngeneBuffer.SR.Flags & 0x01) 152 if (Cur->ngeneBuffer.SR.Flags & 0x01)
@@ -474,9 +477,9 @@ static u8 SPDIFConfiguration[10] = {
474 477
475/* Set NGENE I2S Config to transport stream compatible mode */ 478/* Set NGENE I2S Config to transport stream compatible mode */
476 479
477static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/ 480static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 };
478 481
479static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 }; 482static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 };
480 483
481static u8 ITUDecoderSetup[4][16] = { 484static u8 ITUDecoderSetup[4][16] = {
482 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */ 485 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
@@ -749,13 +752,11 @@ void set_transfer(struct ngene_channel *chan, int state)
749 if (chan->mode & NGENE_IO_TSOUT) { 752 if (chan->mode & NGENE_IO_TSOUT) {
750 chan->pBufferExchange = tsout_exchange; 753 chan->pBufferExchange = tsout_exchange;
751 /* 0x66666666 = 50MHz *2^33 /250MHz */ 754 /* 0x66666666 = 50MHz *2^33 /250MHz */
752 chan->AudioDTOValue = 0x66666666; 755 chan->AudioDTOValue = 0x80000000;
753 /* set_dto(chan, 38810700+1000); */ 756 chan->AudioDTOUpdated = 1;
754 /* set_dto(chan, 19392658); */
755 } 757 }
756 if (chan->mode & NGENE_IO_TSIN) 758 if (chan->mode & NGENE_IO_TSIN)
757 chan->pBufferExchange = tsin_exchange; 759 chan->pBufferExchange = tsin_exchange;
758 /* ngwritel(0, 0x9310); */
759 spin_unlock_irq(&chan->state_lock); 760 spin_unlock_irq(&chan->state_lock);
760 } else 761 } else
761 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", 762 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
@@ -1168,6 +1169,7 @@ static void ngene_release_buffers(struct ngene *dev)
1168 iounmap(dev->iomem); 1169 iounmap(dev->iomem);
1169 free_common_buffers(dev); 1170 free_common_buffers(dev);
1170 vfree(dev->tsout_buf); 1171 vfree(dev->tsout_buf);
1172 vfree(dev->tsin_buf);
1171 vfree(dev->ain_buf); 1173 vfree(dev->ain_buf);
1172 vfree(dev->vin_buf); 1174 vfree(dev->vin_buf);
1173 vfree(dev); 1175 vfree(dev);
@@ -1184,6 +1186,13 @@ static int ngene_get_buffers(struct ngene *dev)
1184 dvb_ringbuffer_init(&dev->tsout_rbuf, 1186 dvb_ringbuffer_init(&dev->tsout_rbuf,
1185 dev->tsout_buf, TSOUT_BUF_SIZE); 1187 dev->tsout_buf, TSOUT_BUF_SIZE);
1186 } 1188 }
1189 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) {
1190 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE);
1191 if (!dev->tsin_buf)
1192 return -ENOMEM;
1193 dvb_ringbuffer_init(&dev->tsin_rbuf,
1194 dev->tsin_buf, TSIN_BUF_SIZE);
1195 }
1187 if (dev->card_info->io_type[2] & NGENE_IO_AIN) { 1196 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1188 dev->ain_buf = vmalloc(AIN_BUF_SIZE); 1197 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1189 if (!dev->ain_buf) 1198 if (!dev->ain_buf)
@@ -1257,6 +1266,10 @@ static int ngene_load_firm(struct ngene *dev)
1257 fw_name = "ngene_17.fw"; 1266 fw_name = "ngene_17.fw";
1258 dev->cmd_timeout_workaround = true; 1267 dev->cmd_timeout_workaround = true;
1259 break; 1268 break;
1269 case 18:
1270 size = 0;
1271 fw_name = "ngene_18.fw";
1272 break;
1260 } 1273 }
1261 1274
1262 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) { 1275 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
@@ -1266,6 +1279,8 @@ static int ngene_load_firm(struct ngene *dev)
1266 ": Copy %s to your hotplug directory!\n", fw_name); 1279 ": Copy %s to your hotplug directory!\n", fw_name);
1267 return -1; 1280 return -1;
1268 } 1281 }
1282 if (size == 0)
1283 size = fw->size;
1269 if (size != fw->size) { 1284 if (size != fw->size) {
1270 printk(KERN_ERR DEVICE_NAME 1285 printk(KERN_ERR DEVICE_NAME
1271 ": Firmware %s has invalid size!", fw_name); 1286 ": Firmware %s has invalid size!", fw_name);
@@ -1301,6 +1316,35 @@ static void ngene_stop(struct ngene *dev)
1301#endif 1316#endif
1302} 1317}
1303 1318
1319static int ngene_buffer_config(struct ngene *dev)
1320{
1321 int stat;
1322
1323 if (dev->card_info->fw_version >= 17) {
1324 u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 };
1325 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 };
1326 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 };
1327 u8 *bconf = tsin12_config;
1328
1329 if (dev->card_info->io_type[2]&NGENE_IO_TSIN &&
1330 dev->card_info->io_type[3]&NGENE_IO_TSIN) {
1331 bconf = tsin1234_config;
1332 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT &&
1333 dev->ci.en)
1334 bconf = tsio1235_config;
1335 }
1336 stat = ngene_command_config_free_buf(dev, bconf);
1337 } else {
1338 int bconf = BUFFER_CONFIG_4422;
1339
1340 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1341 bconf = BUFFER_CONFIG_3333;
1342 stat = ngene_command_config_buf(dev, bconf);
1343 }
1344 return stat;
1345}
1346
1347
1304static int ngene_start(struct ngene *dev) 1348static int ngene_start(struct ngene *dev)
1305{ 1349{
1306 int stat; 1350 int stat;
@@ -1365,23 +1409,6 @@ static int ngene_start(struct ngene *dev)
1365 if (stat < 0) 1409 if (stat < 0)
1366 goto fail; 1410 goto fail;
1367 1411
1368 if (dev->card_info->fw_version == 17) {
1369 u8 tsin4_config[6] = {
1370 3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
1371 u8 default_config[6] = {
1372 4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
1373 u8 *bconf = default_config;
1374
1375 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1376 bconf = tsin4_config;
1377 dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n");
1378 stat = ngene_command_config_free_buf(dev, bconf);
1379 } else {
1380 int bconf = BUFFER_CONFIG_4422;
1381 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1382 bconf = BUFFER_CONFIG_3333;
1383 stat = ngene_command_config_buf(dev, bconf);
1384 }
1385 if (!stat) 1412 if (!stat)
1386 return stat; 1413 return stat;
1387 1414
@@ -1397,9 +1424,6 @@ fail2:
1397 return stat; 1424 return stat;
1398} 1425}
1399 1426
1400
1401
1402
1403/****************************************************************************/ 1427/****************************************************************************/
1404/****************************************************************************/ 1428/****************************************************************************/
1405/****************************************************************************/ 1429/****************************************************************************/
@@ -1408,20 +1432,25 @@ static void release_channel(struct ngene_channel *chan)
1408{ 1432{
1409 struct dvb_demux *dvbdemux = &chan->demux; 1433 struct dvb_demux *dvbdemux = &chan->demux;
1410 struct ngene *dev = chan->dev; 1434 struct ngene *dev = chan->dev;
1411 struct ngene_info *ni = dev->card_info;
1412 int io = ni->io_type[chan->number];
1413 1435
1414 if (chan->dev->cmd_timeout_workaround && chan->running) 1436 if (chan->running)
1415 set_transfer(chan, 0); 1437 set_transfer(chan, 0);
1416 1438
1417 tasklet_kill(&chan->demux_tasklet); 1439 tasklet_kill(&chan->demux_tasklet);
1418 1440
1419 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 1441 if (chan->ci_dev) {
1420 if (chan->fe) { 1442 dvb_unregister_device(chan->ci_dev);
1421 dvb_unregister_frontend(chan->fe); 1443 chan->ci_dev = NULL;
1422 dvb_frontend_detach(chan->fe); 1444 }
1423 chan->fe = NULL; 1445
1424 } 1446 if (chan->fe) {
1447 dvb_unregister_frontend(chan->fe);
1448 dvb_frontend_detach(chan->fe);
1449 chan->fe = NULL;
1450 }
1451
1452 if (chan->has_demux) {
1453 dvb_net_release(&chan->dvbnet);
1425 dvbdemux->dmx.close(&dvbdemux->dmx); 1454 dvbdemux->dmx.close(&dvbdemux->dmx);
1426 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, 1455 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1427 &chan->hw_frontend); 1456 &chan->hw_frontend);
@@ -1429,9 +1458,12 @@ static void release_channel(struct ngene_channel *chan)
1429 &chan->mem_frontend); 1458 &chan->mem_frontend);
1430 dvb_dmxdev_release(&chan->dmxdev); 1459 dvb_dmxdev_release(&chan->dmxdev);
1431 dvb_dmx_release(&chan->demux); 1460 dvb_dmx_release(&chan->demux);
1461 chan->has_demux = false;
1462 }
1432 1463
1433 if (chan->number == 0 || !one_adapter) 1464 if (chan->has_adapter) {
1434 dvb_unregister_adapter(&dev->adapter[chan->number]); 1465 dvb_unregister_adapter(&dev->adapter[chan->number]);
1466 chan->has_adapter = false;
1435 } 1467 }
1436} 1468}
1437 1469
@@ -1449,9 +1481,27 @@ static int init_channel(struct ngene_channel *chan)
1449 chan->type = io; 1481 chan->type = io;
1450 chan->mode = chan->type; /* for now only one mode */ 1482 chan->mode = chan->type; /* for now only one mode */
1451 1483
1484 if (io & NGENE_IO_TSIN) {
1485 chan->fe = NULL;
1486 if (ni->demod_attach[nr]) {
1487 ret = ni->demod_attach[nr](chan);
1488 if (ret < 0)
1489 goto err;
1490 }
1491 if (chan->fe && ni->tuner_attach[nr]) {
1492 ret = ni->tuner_attach[nr](chan);
1493 if (ret < 0)
1494 goto err;
1495 }
1496 }
1497
1498 if (!dev->ci.en && (io & NGENE_IO_TSOUT))
1499 return 0;
1500
1452 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { 1501 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1453 if (nr >= STREAM_AUDIOIN1) 1502 if (nr >= STREAM_AUDIOIN1)
1454 chan->DataFormatFlags = DF_SWAP32; 1503 chan->DataFormatFlags = DF_SWAP32;
1504
1455 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) { 1505 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1456 adapter = &dev->adapter[nr]; 1506 adapter = &dev->adapter[nr];
1457 ret = dvb_register_adapter(adapter, "nGene", 1507 ret = dvb_register_adapter(adapter, "nGene",
@@ -1459,40 +1509,50 @@ static int init_channel(struct ngene_channel *chan)
1459 &chan->dev->pci_dev->dev, 1509 &chan->dev->pci_dev->dev,
1460 adapter_nr); 1510 adapter_nr);
1461 if (ret < 0) 1511 if (ret < 0)
1462 return ret; 1512 goto err;
1463 if (dev->first_adapter == NULL) 1513 if (dev->first_adapter == NULL)
1464 dev->first_adapter = adapter; 1514 dev->first_adapter = adapter;
1465 } else { 1515 chan->has_adapter = true;
1516 } else
1466 adapter = dev->first_adapter; 1517 adapter = dev->first_adapter;
1467 } 1518 }
1468 1519
1520 if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
1521 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
1522 set_transfer(chan, 1);
1523 set_transfer(&chan->dev->channel[2], 1);
1524 dvb_register_device(adapter, &chan->ci_dev,
1525 &ngene_dvbdev_ci, (void *) chan,
1526 DVB_DEVICE_SEC);
1527 if (!chan->ci_dev)
1528 goto err;
1529 }
1530
1531 if (chan->fe) {
1532 if (dvb_register_frontend(adapter, chan->fe) < 0)
1533 goto err;
1534 chan->has_demux = true;
1535 }
1536
1537 if (chan->has_demux) {
1469 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", 1538 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1470 ngene_start_feed, 1539 ngene_start_feed,
1471 ngene_stop_feed, chan); 1540 ngene_stop_feed, chan);
1472 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux, 1541 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1473 &chan->hw_frontend, 1542 &chan->hw_frontend,
1474 &chan->mem_frontend, adapter); 1543 &chan->mem_frontend, adapter);
1544 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx);
1475 } 1545 }
1476 1546
1477 if (io & NGENE_IO_TSIN) { 1547 return ret;
1548
1549err:
1550 if (chan->fe) {
1551 dvb_frontend_detach(chan->fe);
1478 chan->fe = NULL; 1552 chan->fe = NULL;
1479 if (ni->demod_attach[nr])
1480 ni->demod_attach[nr](chan);
1481 if (chan->fe) {
1482 if (dvb_register_frontend(adapter, chan->fe) < 0) {
1483 if (chan->fe->ops.release)
1484 chan->fe->ops.release(chan->fe);
1485 chan->fe = NULL;
1486 }
1487 }
1488 if (chan->fe && ni->tuner_attach[nr])
1489 if (ni->tuner_attach[nr] (chan) < 0) {
1490 printk(KERN_ERR DEVICE_NAME
1491 ": Tuner attach failed on channel %d!\n",
1492 nr);
1493 }
1494 } 1553 }
1495 return ret; 1554 release_channel(chan);
1555 return 0;
1496} 1556}
1497 1557
1498static int init_channels(struct ngene *dev) 1558static int init_channels(struct ngene *dev)
@@ -1510,6 +1570,57 @@ static int init_channels(struct ngene *dev)
1510 return 0; 1570 return 0;
1511} 1571}
1512 1572
1573static void cxd_attach(struct ngene *dev)
1574{
1575 struct ngene_ci *ci = &dev->ci;
1576
1577 ci->en = cxd2099_attach(0x40, dev, &dev->channel[0].i2c_adapter);
1578 ci->dev = dev;
1579 return;
1580}
1581
1582static void cxd_detach(struct ngene *dev)
1583{
1584 struct ngene_ci *ci = &dev->ci;
1585
1586 dvb_ca_en50221_release(ci->en);
1587 kfree(ci->en);
1588 ci->en = 0;
1589}
1590
1591/***********************************/
1592/* workaround for shutdown failure */
1593/***********************************/
1594
1595static void ngene_unlink(struct ngene *dev)
1596{
1597 struct ngene_command com;
1598
1599 com.cmd.hdr.Opcode = CMD_MEM_WRITE;
1600 com.cmd.hdr.Length = 3;
1601 com.cmd.MemoryWrite.address = 0x910c;
1602 com.cmd.MemoryWrite.data = 0xff;
1603 com.in_len = 3;
1604 com.out_len = 1;
1605
1606 down(&dev->cmd_mutex);
1607 ngwritel(0, NGENE_INT_ENABLE);
1608 ngene_command_mutex(dev, &com);
1609 up(&dev->cmd_mutex);
1610}
1611
1612void ngene_shutdown(struct pci_dev *pdev)
1613{
1614 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
1615
1616 if (!dev || !shutdown_workaround)
1617 return;
1618
1619 printk(KERN_INFO DEVICE_NAME ": shutdown workaround...\n");
1620 ngene_unlink(dev);
1621 pci_disable_device(pdev);
1622}
1623
1513/****************************************************************************/ 1624/****************************************************************************/
1514/* device probe/remove calls ************************************************/ 1625/* device probe/remove calls ************************************************/
1515/****************************************************************************/ 1626/****************************************************************************/
@@ -1522,6 +1633,8 @@ void __devexit ngene_remove(struct pci_dev *pdev)
1522 tasklet_kill(&dev->event_tasklet); 1633 tasklet_kill(&dev->event_tasklet);
1523 for (i = MAX_STREAM - 1; i >= 0; i--) 1634 for (i = MAX_STREAM - 1; i >= 0; i--)
1524 release_channel(&dev->channel[i]); 1635 release_channel(&dev->channel[i]);
1636 if (dev->ci.en)
1637 cxd_detach(dev);
1525 ngene_stop(dev); 1638 ngene_stop(dev);
1526 ngene_release_buffers(dev); 1639 ngene_release_buffers(dev);
1527 pci_set_drvdata(pdev, NULL); 1640 pci_set_drvdata(pdev, NULL);
@@ -1557,6 +1670,13 @@ int __devinit ngene_probe(struct pci_dev *pci_dev,
1557 if (stat < 0) 1670 if (stat < 0)
1558 goto fail1; 1671 goto fail1;
1559 1672
1673 cxd_attach(dev);
1674
1675 stat = ngene_buffer_config(dev);
1676 if (stat < 0)
1677 goto fail1;
1678
1679
1560 dev->i2c_current_bus = -1; 1680 dev->i2c_current_bus = -1;
1561 1681
1562 /* Register DVB adapters and devices for both channels */ 1682 /* Register DVB adapters and devices for both channels */
diff --git a/drivers/media/dvb/ngene/ngene-dvb.c b/drivers/media/dvb/ngene/ngene-dvb.c
index 3832e5983c19..0b4943233166 100644
--- a/drivers/media/dvb/ngene/ngene-dvb.c
+++ b/drivers/media/dvb/ngene/ngene-dvb.c
@@ -47,6 +47,64 @@
47/* COMMAND API interface ****************************************************/ 47/* COMMAND API interface ****************************************************/
48/****************************************************************************/ 48/****************************************************************************/
49 49
50static ssize_t ts_write(struct file *file, const char *buf,
51 size_t count, loff_t *ppos)
52{
53 struct dvb_device *dvbdev = file->private_data;
54 struct ngene_channel *chan = dvbdev->priv;
55 struct ngene *dev = chan->dev;
56
57 if (wait_event_interruptible(dev->tsout_rbuf.queue,
58 dvb_ringbuffer_free
59 (&dev->tsout_rbuf) >= count) < 0)
60 return 0;
61
62 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, count);
63
64 return count;
65}
66
67static ssize_t ts_read(struct file *file, char *buf,
68 size_t count, loff_t *ppos)
69{
70 struct dvb_device *dvbdev = file->private_data;
71 struct ngene_channel *chan = dvbdev->priv;
72 struct ngene *dev = chan->dev;
73 int left, avail;
74
75 left = count;
76 while (left) {
77 if (wait_event_interruptible(
78 dev->tsin_rbuf.queue,
79 dvb_ringbuffer_avail(&dev->tsin_rbuf) > 0) < 0)
80 return -EAGAIN;
81 avail = dvb_ringbuffer_avail(&dev->tsin_rbuf);
82 if (avail > left)
83 avail = left;
84 dvb_ringbuffer_read_user(&dev->tsin_rbuf, buf, avail);
85 left -= avail;
86 buf += avail;
87 }
88 return count;
89}
90
91static const struct file_operations ci_fops = {
92 .owner = THIS_MODULE,
93 .read = ts_read,
94 .write = ts_write,
95 .open = dvb_generic_open,
96 .release = dvb_generic_release,
97};
98
99struct dvb_device ngene_dvbdev_ci = {
100 .priv = 0,
101 .readers = -1,
102 .writers = -1,
103 .users = -1,
104 .fops = &ci_fops,
105};
106
107
50/****************************************************************************/ 108/****************************************************************************/
51/* DVB functions and API interface ******************************************/ 109/* DVB functions and API interface ******************************************/
52/****************************************************************************/ 110/****************************************************************************/
@@ -63,10 +121,21 @@ static void swap_buffer(u32 *p, u32 len)
63void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) 121void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
64{ 122{
65 struct ngene_channel *chan = priv; 123 struct ngene_channel *chan = priv;
124 struct ngene *dev = chan->dev;
66 125
67 126
68 if (chan->users > 0) 127 if (flags & DF_SWAP32)
128 swap_buffer(buf, len);
129 if (dev->ci.en && chan->number == 2) {
130 if (dvb_ringbuffer_free(&dev->tsin_rbuf) > len) {
131 dvb_ringbuffer_write(&dev->tsin_rbuf, buf, len);
132 wake_up_interruptible(&dev->tsin_rbuf.queue);
133 }
134 return 0;
135 }
136 if (chan->users > 0) {
69 dvb_dmx_swfilter(&chan->demux, buf, len); 137 dvb_dmx_swfilter(&chan->demux, buf, len);
138 }
70 return NULL; 139 return NULL;
71} 140}
72 141
diff --git a/drivers/media/dvb/ngene/ngene.h b/drivers/media/dvb/ngene/ngene.h
index 8fb4200f83f8..40fce9e3ae66 100644
--- a/drivers/media/dvb/ngene/ngene.h
+++ b/drivers/media/dvb/ngene/ngene.h
@@ -36,8 +36,11 @@
36#include "dmxdev.h" 36#include "dmxdev.h"
37#include "dvbdev.h" 37#include "dvbdev.h"
38#include "dvb_demux.h" 38#include "dvb_demux.h"
39#include "dvb_ca_en50221.h"
39#include "dvb_frontend.h" 40#include "dvb_frontend.h"
40#include "dvb_ringbuffer.h" 41#include "dvb_ringbuffer.h"
42#include "dvb_net.h"
43#include "cxd2099.h"
41 44
42#define DEVICE_NAME "ngene" 45#define DEVICE_NAME "ngene"
43 46
@@ -636,14 +639,18 @@ struct ngene_channel {
636 int number; 639 int number;
637 int type; 640 int type;
638 int mode; 641 int mode;
642 bool has_adapter;
643 bool has_demux;
639 644
640 struct dvb_frontend *fe; 645 struct dvb_frontend *fe;
641 struct dmxdev dmxdev; 646 struct dmxdev dmxdev;
642 struct dvb_demux demux; 647 struct dvb_demux demux;
648 struct dvb_net dvbnet;
643 struct dmx_frontend hw_frontend; 649 struct dmx_frontend hw_frontend;
644 struct dmx_frontend mem_frontend; 650 struct dmx_frontend mem_frontend;
645 int users; 651 int users;
646 struct video_device *v4l_dev; 652 struct video_device *v4l_dev;
653 struct dvb_device *ci_dev;
647 struct tasklet_struct demux_tasklet; 654 struct tasklet_struct demux_tasklet;
648 655
649 struct SBufferHeader *nextBuffer; 656 struct SBufferHeader *nextBuffer;
@@ -710,6 +717,15 @@ struct ngene_channel {
710 int running; 717 int running;
711}; 718};
712 719
720
721struct ngene_ci {
722 struct device device;
723 struct i2c_adapter i2c_adapter;
724
725 struct ngene *dev;
726 struct dvb_ca_en50221 *en;
727};
728
713struct ngene; 729struct ngene;
714 730
715typedef void (rx_cb_t)(struct ngene *, u32, u8); 731typedef void (rx_cb_t)(struct ngene *, u32, u8);
@@ -774,6 +790,10 @@ struct ngene {
774#define TSOUT_BUF_SIZE (512*188*8) 790#define TSOUT_BUF_SIZE (512*188*8)
775 struct dvb_ringbuffer tsout_rbuf; 791 struct dvb_ringbuffer tsout_rbuf;
776 792
793 u8 *tsin_buf;
794#define TSIN_BUF_SIZE (512*188*8)
795 struct dvb_ringbuffer tsin_rbuf;
796
777 u8 *ain_buf; 797 u8 *ain_buf;
778#define AIN_BUF_SIZE (128*1024) 798#define AIN_BUF_SIZE (128*1024)
779 struct dvb_ringbuffer ain_rbuf; 799 struct dvb_ringbuffer ain_rbuf;
@@ -785,6 +805,8 @@ struct ngene {
785 805
786 unsigned long exp_val; 806 unsigned long exp_val;
787 int prev_cmd; 807 int prev_cmd;
808
809 struct ngene_ci ci;
788}; 810};
789 811
790struct ngene_info { 812struct ngene_info {
@@ -863,6 +885,7 @@ struct ngene_buffer {
863int __devinit ngene_probe(struct pci_dev *pci_dev, 885int __devinit ngene_probe(struct pci_dev *pci_dev,
864 const struct pci_device_id *id); 886 const struct pci_device_id *id);
865void __devexit ngene_remove(struct pci_dev *pdev); 887void __devexit ngene_remove(struct pci_dev *pdev);
888void ngene_shutdown(struct pci_dev *pdev);
866int ngene_command(struct ngene *dev, struct ngene_command *com); 889int ngene_command(struct ngene *dev, struct ngene_command *com);
867int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level); 890int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);
868void set_transfer(struct ngene_channel *chan, int state); 891void set_transfer(struct ngene_channel *chan, int state);
@@ -872,6 +895,7 @@ void FillTSBuffer(void *Buffer, int Length, u32 Flags);
872int ngene_i2c_init(struct ngene *dev, int dev_nr); 895int ngene_i2c_init(struct ngene *dev, int dev_nr);
873 896
874/* Provided by ngene-dvb.c */ 897/* Provided by ngene-dvb.c */
898extern struct dvb_device ngene_dvbdev_ci;
875void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags); 899void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
876void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags); 900void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
877int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed); 901int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);
diff --git a/drivers/media/dvb/siano/sms-cards.c b/drivers/media/dvb/siano/sms-cards.c
index 25b43e587fa6..af121db88ea0 100644
--- a/drivers/media/dvb/siano/sms-cards.c
+++ b/drivers/media/dvb/siano/sms-cards.c
@@ -64,7 +64,7 @@ static struct sms_board sms_boards[] = {
64 .type = SMS_NOVA_B0, 64 .type = SMS_NOVA_B0,
65 .fw[DEVICE_MODE_ISDBT_BDA] = "sms1xxx-hcw-55xxx-isdbt-02.fw", 65 .fw[DEVICE_MODE_ISDBT_BDA] = "sms1xxx-hcw-55xxx-isdbt-02.fw",
66 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw", 66 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw",
67 .rc_codes = RC_MAP_RC5_HAUPPAUGE_NEW, 67 .rc_codes = RC_MAP_HAUPPAUGE,
68 .board_cfg.leds_power = 26, 68 .board_cfg.leds_power = 26,
69 .board_cfg.led0 = 27, 69 .board_cfg.led0 = 27,
70 .board_cfg.led1 = 28, 70 .board_cfg.led1 = 28,
diff --git a/drivers/media/dvb/ttpci/budget-ci.c b/drivers/media/dvb/ttpci/budget-ci.c
index b82756db5bd1..1d79ada864d6 100644
--- a/drivers/media/dvb/ttpci/budget-ci.c
+++ b/drivers/media/dvb/ttpci/budget-ci.c
@@ -26,7 +26,7 @@
26 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html 26 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
27 * 27 *
28 * 28 *
29 * the project's page is at http://www.linuxtv.org/ 29 * the project's page is at http://www.linuxtv.org/
30 */ 30 */
31 31
32#include <linux/module.h> 32#include <linux/module.h>
@@ -102,6 +102,7 @@ struct budget_ci_ir {
102 int rc5_device; 102 int rc5_device;
103 u32 ir_key; 103 u32 ir_key;
104 bool have_command; 104 bool have_command;
105 bool full_rc5; /* Outputs a full RC5 code */
105}; 106};
106 107
107struct budget_ci { 108struct budget_ci {
@@ -154,11 +155,18 @@ static void msp430_ir_interrupt(unsigned long data)
154 return; 155 return;
155 budget_ci->ir.have_command = false; 156 budget_ci->ir.have_command = false;
156 157
157 /* FIXME: We should generate complete scancodes with device info */
158 if (budget_ci->ir.rc5_device != IR_DEVICE_ANY && 158 if (budget_ci->ir.rc5_device != IR_DEVICE_ANY &&
159 budget_ci->ir.rc5_device != (command & 0x1f)) 159 budget_ci->ir.rc5_device != (command & 0x1f))
160 return; 160 return;
161 161
162 if (budget_ci->ir.full_rc5) {
163 rc_keydown(dev,
164 budget_ci->ir.rc5_device <<8 | budget_ci->ir.ir_key,
165 (command & 0x20) ? 1 : 0);
166 return;
167 }
168
169 /* FIXME: We should generate complete scancodes for all devices */
162 rc_keydown(dev, budget_ci->ir.ir_key, (command & 0x20) ? 1 : 0); 170 rc_keydown(dev, budget_ci->ir.ir_key, (command & 0x20) ? 1 : 0);
163} 171}
164 172
@@ -206,7 +214,8 @@ static int msp430_ir_init(struct budget_ci *budget_ci)
206 case 0x1011: 214 case 0x1011:
207 case 0x1012: 215 case 0x1012:
208 /* The hauppauge keymap is a superset of these remotes */ 216 /* The hauppauge keymap is a superset of these remotes */
209 dev->map_name = RC_MAP_HAUPPAUGE_NEW; 217 dev->map_name = RC_MAP_HAUPPAUGE;
218 budget_ci->ir.full_rc5 = true;
210 219
211 if (rc5_device < 0) 220 if (rc5_device < 0)
212 budget_ci->ir.rc5_device = 0x1f; 221 budget_ci->ir.rc5_device = 0x1f;
diff --git a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c
index 40625b26ac10..cbe2f0de1442 100644
--- a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c
+++ b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c
@@ -334,6 +334,7 @@ static int ttusb_boot_dsp(struct ttusb *ttusb)
334 err = ttusb_cmd(ttusb, b, 4, 0); 334 err = ttusb_cmd(ttusb, b, 4, 0);
335 335
336 done: 336 done:
337 release_firmware(fw);
337 if (err) { 338 if (err) {
338 dprintk("%s: usb_bulk_msg() failed, return value %i!\n", 339 dprintk("%s: usb_bulk_msg() failed, return value %i!\n",
339 __func__, err); 340 __func__, err);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 04:11:30 -0500