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-rw-r--r--drivers/media/dvb/Kconfig13
-rw-r--r--drivers/media/dvb/b2c2/Kconfig1
-rw-r--r--drivers/media/dvb/dm1105/dm1105.c3
-rw-r--r--drivers/media/dvb/dvb-core/dvb_frontend.c77
-rw-r--r--drivers/media/dvb/dvb-core/dvb_frontend.h134
-rw-r--r--drivers/media/dvb/dvb-core/dvbdev.c71
-rw-r--r--drivers/media/dvb/dvb-core/dvbdev.h1
-rw-r--r--drivers/media/dvb/dvb-usb/af9015.c33
-rw-r--r--drivers/media/dvb/dvb-usb/af9015.h140
-rw-r--r--drivers/media/dvb/dvb-usb/anysee.c2
-rw-r--r--drivers/media/dvb/dvb-usb/cinergyT2-core.c3
-rw-r--r--drivers/media/dvb/dvb-usb/cinergyT2.h10
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb-ids.h1
-rw-r--r--drivers/media/dvb/dvb-usb/dw2102.c15
-rw-r--r--drivers/media/dvb/dvb-usb/gp8psk-fe.c140
-rw-r--r--drivers/media/dvb/dvb-usb/gp8psk.c16
-rw-r--r--drivers/media/dvb/dvb-usb/gp8psk.h1
-rw-r--r--drivers/media/dvb/dvb-usb/usb-urb.c3
-rw-r--r--drivers/media/dvb/frontends/Kconfig53
-rw-r--r--drivers/media/dvb/frontends/Makefile10
-rw-r--r--drivers/media/dvb/frontends/af9013.c14
-rw-r--r--drivers/media/dvb/frontends/cx24113.c616
-rw-r--r--drivers/media/dvb/frontends/cx24113.h11
-rw-r--r--drivers/media/dvb/frontends/cx24116.c43
-rw-r--r--drivers/media/dvb/frontends/dib7000p.h9
-rw-r--r--drivers/media/dvb/frontends/drx397xD.c12
-rw-r--r--drivers/media/dvb/frontends/drx397xD_fw.h4
-rw-r--r--drivers/media/dvb/frontends/dvb-pll.c2
-rw-r--r--drivers/media/dvb/frontends/lgdt3304.c378
-rw-r--r--drivers/media/dvb/frontends/lgdt3304.h45
-rw-r--r--drivers/media/dvb/frontends/s5h1411.c3
-rw-r--r--drivers/media/dvb/frontends/s921_core.c216
-rw-r--r--drivers/media/dvb/frontends/s921_core.h114
-rw-r--r--drivers/media/dvb/frontends/s921_module.c190
-rw-r--r--drivers/media/dvb/frontends/s921_module.h49
-rw-r--r--drivers/media/dvb/frontends/si21xx.c1
-rw-r--r--drivers/media/dvb/frontends/stb0899_algo.c1519
-rw-r--r--drivers/media/dvb/frontends/stb0899_cfg.h287
-rw-r--r--drivers/media/dvb/frontends/stb0899_drv.c1684
-rw-r--r--drivers/media/dvb/frontends/stb0899_drv.h162
-rw-r--r--drivers/media/dvb/frontends/stb0899_priv.h267
-rw-r--r--drivers/media/dvb/frontends/stb0899_reg.h2027
-rw-r--r--drivers/media/dvb/frontends/stb6100.c545
-rw-r--r--drivers/media/dvb/frontends/stb6100.h115
-rw-r--r--drivers/media/dvb/frontends/stb6100_cfg.h108
-rw-r--r--drivers/media/dvb/frontends/tda8261.c230
-rw-r--r--drivers/media/dvb/frontends/tda8261.h55
-rw-r--r--drivers/media/dvb/frontends/tda8261_cfg.h84
-rw-r--r--drivers/media/dvb/frontends/zl10353.c3
-rw-r--r--drivers/media/dvb/siano/sms-cards.c110
-rw-r--r--drivers/media/dvb/siano/sms-cards.h13
-rw-r--r--drivers/media/dvb/siano/smscoreapi.c78
-rw-r--r--drivers/media/dvb/siano/smscoreapi.h36
-rw-r--r--drivers/media/dvb/siano/smsdvb.c56
-rw-r--r--drivers/media/dvb/siano/smsusb.c45
-rw-r--r--drivers/media/dvb/ttpci/Kconfig4
-rw-r--r--drivers/media/dvb/ttpci/budget-av.c298
-rw-r--r--drivers/media/dvb/ttpci/budget-ci.c311
-rw-r--r--drivers/media/dvb/ttpci/budget.h1
59 files changed, 10364 insertions, 108 deletions
diff --git a/drivers/media/dvb/Kconfig b/drivers/media/dvb/Kconfig
index 0bcd852576d6..40ebde53b3ce 100644
--- a/drivers/media/dvb/Kconfig
+++ b/drivers/media/dvb/Kconfig
@@ -2,6 +2,19 @@
2# DVB device configuration 2# DVB device configuration
3# 3#
4 4
5config DVB_DYNAMIC_MINORS
6 bool "Dynamic DVB minor allocation"
7 depends on DVB_CORE
8 default n
9 help
10 If you say Y here, the DVB subsystem will use dynamic minor
11 allocation for any device that uses the DVB major number.
12 This means that you can have more than 4 of a single type
13 of device (like demuxes and frontends) per adapter, but udev
14 will be required to manage the device nodes.
15
16 If you are unsure about this, say N here.
17
5menuconfig DVB_CAPTURE_DRIVERS 18menuconfig DVB_CAPTURE_DRIVERS
6 bool "DVB/ATSC adapters" 19 bool "DVB/ATSC adapters"
7 depends on DVB_CORE 20 depends on DVB_CORE
diff --git a/drivers/media/dvb/b2c2/Kconfig b/drivers/media/dvb/b2c2/Kconfig
index b34301d56cd2..a8c6249c4099 100644
--- a/drivers/media/dvb/b2c2/Kconfig
+++ b/drivers/media/dvb/b2c2/Kconfig
@@ -14,6 +14,7 @@ config DVB_B2C2_FLEXCOP
14 select DVB_ISL6421 if !DVB_FE_CUSTOMISE 14 select DVB_ISL6421 if !DVB_FE_CUSTOMISE
15 select DVB_CX24123 if !DVB_FE_CUSTOMISE 15 select DVB_CX24123 if !DVB_FE_CUSTOMISE
16 select MEDIA_TUNER_SIMPLE if !MEDIA_TUNER_CUSTOMIZE 16 select MEDIA_TUNER_SIMPLE if !MEDIA_TUNER_CUSTOMIZE
17 select DVB_TUNER_CX24113 if !DVB_FE_CUSTOMISE
17 help 18 help
18 Support for the digital TV receiver chip made by B2C2 Inc. included in 19 Support for the digital TV receiver chip made by B2C2 Inc. included in
19 Technisats PCI cards and USB boxes. 20 Technisats PCI cards and USB boxes.
diff --git a/drivers/media/dvb/dm1105/dm1105.c b/drivers/media/dvb/dm1105/dm1105.c
index a21ce9edcc7e..f48f73aff195 100644
--- a/drivers/media/dvb/dm1105/dm1105.c
+++ b/drivers/media/dvb/dm1105/dm1105.c
@@ -19,7 +19,6 @@
19 * 19 *
20 */ 20 */
21 21
22#include <linux/version.h>
23#include <linux/i2c.h> 22#include <linux/i2c.h>
24#include <linux/init.h> 23#include <linux/init.h>
25#include <linux/kernel.h> 24#include <linux/kernel.h>
@@ -368,7 +367,7 @@ static int __devinit dm1105dvb_dma_map(struct dm1105dvb *dm1105dvb)
368{ 367{
369 dm1105dvb->ts_buf = pci_alloc_consistent(dm1105dvb->pdev, 6*DM1105_DMA_BYTES, &dm1105dvb->dma_addr); 368 dm1105dvb->ts_buf = pci_alloc_consistent(dm1105dvb->pdev, 6*DM1105_DMA_BYTES, &dm1105dvb->dma_addr);
370 369
371 return pci_dma_mapping_error(dm1105dvb->pdev, dm1105dvb->dma_addr); 370 return !dm1105dvb->ts_buf;
372} 371}
373 372
374static void dm1105dvb_dma_unmap(struct dm1105dvb *dm1105dvb) 373static void dm1105dvb_dma_unmap(struct dm1105dvb *dm1105dvb)
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c
index 7a421e9dba5a..171f9ca124f7 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.c
@@ -128,6 +128,7 @@ struct dvb_frontend_private {
128 unsigned int step_size; 128 unsigned int step_size;
129 int quality; 129 int quality;
130 unsigned int check_wrapped; 130 unsigned int check_wrapped;
131 enum dvbfe_search algo_status;
131}; 132};
132 133
133static void dvb_frontend_wakeup(struct dvb_frontend *fe); 134static void dvb_frontend_wakeup(struct dvb_frontend *fe);
@@ -516,6 +517,8 @@ static int dvb_frontend_thread(void *data)
516 struct dvb_frontend_private *fepriv = fe->frontend_priv; 517 struct dvb_frontend_private *fepriv = fe->frontend_priv;
517 unsigned long timeout; 518 unsigned long timeout;
518 fe_status_t s; 519 fe_status_t s;
520 enum dvbfe_algo algo;
521
519 struct dvb_frontend_parameters *params; 522 struct dvb_frontend_parameters *params;
520 523
521 dprintk("%s\n", __func__); 524 dprintk("%s\n", __func__);
@@ -562,23 +565,80 @@ restart:
562 565
563 /* do an iteration of the tuning loop */ 566 /* do an iteration of the tuning loop */
564 if (fe->ops.get_frontend_algo) { 567 if (fe->ops.get_frontend_algo) {
565 if (fe->ops.get_frontend_algo(fe) == FE_ALGO_HW) { 568 algo = fe->ops.get_frontend_algo(fe);
566 /* have we been asked to retune? */ 569 switch (algo) {
567 params = NULL; 570 case DVBFE_ALGO_HW:
571 dprintk("%s: Frontend ALGO = DVBFE_ALGO_HW\n", __func__);
572 params = NULL; /* have we been asked to RETUNE ? */
573
568 if (fepriv->state & FESTATE_RETUNE) { 574 if (fepriv->state & FESTATE_RETUNE) {
575 dprintk("%s: Retune requested, FESTATE_RETUNE\n", __func__);
569 params = &fepriv->parameters; 576 params = &fepriv->parameters;
570 fepriv->state = FESTATE_TUNED; 577 fepriv->state = FESTATE_TUNED;
571 } 578 }
572 579
573 fe->ops.tune(fe, params, fepriv->tune_mode_flags, &fepriv->delay, &s); 580 if (fe->ops.tune)
574 if (s != fepriv->status) { 581 fe->ops.tune(fe, params, fepriv->tune_mode_flags, &fepriv->delay, &s);
582
583 if (s != fepriv->status && !(fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT)) {
584 dprintk("%s: state changed, adding current state\n", __func__);
575 dvb_frontend_add_event(fe, s); 585 dvb_frontend_add_event(fe, s);
576 fepriv->status = s; 586 fepriv->status = s;
577 } 587 }
578 } else 588 break;
589 case DVBFE_ALGO_SW:
590 dprintk("%s: Frontend ALGO = DVBFE_ALGO_SW\n", __func__);
579 dvb_frontend_swzigzag(fe); 591 dvb_frontend_swzigzag(fe);
580 } else 592 break;
593 case DVBFE_ALGO_CUSTOM:
594 params = NULL; /* have we been asked to RETUNE ? */
595 dprintk("%s: Frontend ALGO = DVBFE_ALGO_CUSTOM, state=%d\n", __func__, fepriv->state);
596 if (fepriv->state & FESTATE_RETUNE) {
597 dprintk("%s: Retune requested, FESTAT_RETUNE\n", __func__);
598 params = &fepriv->parameters;
599 fepriv->state = FESTATE_TUNED;
600 }
601 /* Case where we are going to search for a carrier
602 * User asked us to retune again for some reason, possibly
603 * requesting a search with a new set of parameters
604 */
605 if (fepriv->algo_status & DVBFE_ALGO_SEARCH_AGAIN) {
606 if (fe->ops.search) {
607 fepriv->algo_status = fe->ops.search(fe, &fepriv->parameters);
608 /* We did do a search as was requested, the flags are
609 * now unset as well and has the flags wrt to search.
610 */
611 } else {
612 fepriv->algo_status &= ~DVBFE_ALGO_SEARCH_AGAIN;
613 }
614 }
615 /* Track the carrier if the search was successful */
616 if (fepriv->algo_status == DVBFE_ALGO_SEARCH_SUCCESS) {
617 if (fe->ops.track)
618 fe->ops.track(fe, &fepriv->parameters);
619 } else {
620 fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
621 fepriv->delay = HZ / 2;
622 }
623 fe->ops.read_status(fe, &s);
624 if (s != fepriv->status) {
625 dvb_frontend_add_event(fe, s); /* update event list */
626 fepriv->status = s;
627 if (!(s & FE_HAS_LOCK)) {
628 fepriv->delay = HZ / 10;
629 fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
630 } else {
631 fepriv->delay = 60 * HZ;
632 }
633 }
634 break;
635 default:
636 dprintk("%s: UNDEFINED ALGO !\n", __func__);
637 break;
638 }
639 } else {
581 dvb_frontend_swzigzag(fe); 640 dvb_frontend_swzigzag(fe);
641 }
582 } 642 }
583 643
584 if (dvb_powerdown_on_sleep) { 644 if (dvb_powerdown_on_sleep) {
@@ -1226,6 +1286,9 @@ int dtv_property_process_set(struct dvb_frontend *fe, struct dtv_property *tvp,
1226 dprintk("%s() Finalised property cache\n", __func__); 1286 dprintk("%s() Finalised property cache\n", __func__);
1227 dtv_property_cache_submit(fe); 1287 dtv_property_cache_submit(fe);
1228 1288
1289 /* Request the search algorithm to search */
1290 fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
1291
1229 r |= dvb_frontend_ioctl_legacy(inode, file, FE_SET_FRONTEND, 1292 r |= dvb_frontend_ioctl_legacy(inode, file, FE_SET_FRONTEND,
1230 &fepriv->parameters); 1293 &fepriv->parameters);
1231 break; 1294 break;
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.h b/drivers/media/dvb/dvb-core/dvb_frontend.h
index db4a63b0a32e..e176da472d7a 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.h
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.h
@@ -69,6 +69,125 @@ struct analog_parameters {
69 u64 std; 69 u64 std;
70}; 70};
71 71
72enum dvbfe_modcod {
73 DVBFE_MODCOD_DUMMY_PLFRAME = 0,
74 DVBFE_MODCOD_QPSK_1_4,
75 DVBFE_MODCOD_QPSK_1_3,
76 DVBFE_MODCOD_QPSK_2_5,
77 DVBFE_MODCOD_QPSK_1_2,
78 DVBFE_MODCOD_QPSK_3_5,
79 DVBFE_MODCOD_QPSK_2_3,
80 DVBFE_MODCOD_QPSK_3_4,
81 DVBFE_MODCOD_QPSK_4_5,
82 DVBFE_MODCOD_QPSK_5_6,
83 DVBFE_MODCOD_QPSK_8_9,
84 DVBFE_MODCOD_QPSK_9_10,
85 DVBFE_MODCOD_8PSK_3_5,
86 DVBFE_MODCOD_8PSK_2_3,
87 DVBFE_MODCOD_8PSK_3_4,
88 DVBFE_MODCOD_8PSK_5_6,
89 DVBFE_MODCOD_8PSK_8_9,
90 DVBFE_MODCOD_8PSK_9_10,
91 DVBFE_MODCOD_16APSK_2_3,
92 DVBFE_MODCOD_16APSK_3_4,
93 DVBFE_MODCOD_16APSK_4_5,
94 DVBFE_MODCOD_16APSK_5_6,
95 DVBFE_MODCOD_16APSK_8_9,
96 DVBFE_MODCOD_16APSK_9_10,
97 DVBFE_MODCOD_32APSK_3_4,
98 DVBFE_MODCOD_32APSK_4_5,
99 DVBFE_MODCOD_32APSK_5_6,
100 DVBFE_MODCOD_32APSK_8_9,
101 DVBFE_MODCOD_32APSK_9_10,
102 DVBFE_MODCOD_RESERVED_1,
103 DVBFE_MODCOD_BPSK_1_3,
104 DVBFE_MODCOD_BPSK_1_4,
105 DVBFE_MODCOD_RESERVED_2
106};
107
108enum tuner_param {
109 DVBFE_TUNER_FREQUENCY = (1 << 0),
110 DVBFE_TUNER_TUNERSTEP = (1 << 1),
111 DVBFE_TUNER_IFFREQ = (1 << 2),
112 DVBFE_TUNER_BANDWIDTH = (1 << 3),
113 DVBFE_TUNER_REFCLOCK = (1 << 4),
114 DVBFE_TUNER_IQSENSE = (1 << 5),
115 DVBFE_TUNER_DUMMY = (1 << 31)
116};
117
118/*
119 * ALGO_HW: (Hardware Algorithm)
120 * ----------------------------------------------------------------
121 * Devices that support this algorithm do everything in hardware
122 * and no software support is needed to handle them.
123 * Requesting these devices to LOCK is the only thing required,
124 * device is supposed to do everything in the hardware.
125 *
126 * ALGO_SW: (Software Algorithm)
127 * ----------------------------------------------------------------
128 * These are dumb devices, that require software to do everything
129 *
130 * ALGO_CUSTOM: (Customizable Agorithm)
131 * ----------------------------------------------------------------
132 * Devices having this algorithm can be customized to have specific
133 * algorithms in the frontend driver, rather than simply doing a
134 * software zig-zag. In this case the zigzag maybe hardware assisted
135 * or it maybe completely done in hardware. In all cases, usage of
136 * this algorithm, in conjunction with the search and track
137 * callbacks, utilizes the driver specific algorithm.
138 *
139 * ALGO_RECOVERY: (Recovery Algorithm)
140 * ----------------------------------------------------------------
141 * These devices have AUTO recovery capabilities from LOCK failure
142 */
143enum dvbfe_algo {
144 DVBFE_ALGO_HW = (1 << 0),
145 DVBFE_ALGO_SW = (1 << 1),
146 DVBFE_ALGO_CUSTOM = (1 << 2),
147 DVBFE_ALGO_RECOVERY = (1 << 31)
148};
149
150struct tuner_state {
151 u32 frequency;
152 u32 tunerstep;
153 u32 ifreq;
154 u32 bandwidth;
155 u32 iqsense;
156 u32 refclock;
157};
158
159/*
160 * search callback possible return status
161 *
162 * DVBFE_ALGO_SEARCH_SUCCESS
163 * The frontend search algorithm completed and returned succesfully
164 *
165 * DVBFE_ALGO_SEARCH_ASLEEP
166 * The frontend search algorithm is sleeping
167 *
168 * DVBFE_ALGO_SEARCH_FAILED
169 * The frontend search for a signal failed
170 *
171 * DVBFE_ALGO_SEARCH_INVALID
172 * The frontend search algorith was probably supplied with invalid
173 * parameters and the search is an invalid one
174 *
175 * DVBFE_ALGO_SEARCH_ERROR
176 * The frontend search algorithm failed due to some error
177 *
178 * DVBFE_ALGO_SEARCH_AGAIN
179 * The frontend search algorithm was requested to search again
180 */
181enum dvbfe_search {
182 DVBFE_ALGO_SEARCH_SUCCESS = (1 << 0),
183 DVBFE_ALGO_SEARCH_ASLEEP = (1 << 1),
184 DVBFE_ALGO_SEARCH_FAILED = (1 << 2),
185 DVBFE_ALGO_SEARCH_INVALID = (1 << 3),
186 DVBFE_ALGO_SEARCH_AGAIN = (1 << 4),
187 DVBFE_ALGO_SEARCH_ERROR = (1 << 31),
188};
189
190
72struct dvb_tuner_ops { 191struct dvb_tuner_ops {
73 192
74 struct dvb_tuner_info info; 193 struct dvb_tuner_info info;
@@ -99,6 +218,13 @@ struct dvb_tuner_ops {
99 * tuners which require sophisticated tuning loops, controlling each parameter seperately. */ 218 * tuners which require sophisticated tuning loops, controlling each parameter seperately. */
100 int (*set_frequency)(struct dvb_frontend *fe, u32 frequency); 219 int (*set_frequency)(struct dvb_frontend *fe, u32 frequency);
101 int (*set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth); 220 int (*set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth);
221
222 /*
223 * These are provided seperately from set_params in order to facilitate silicon
224 * tuners which require sophisticated tuning loops, controlling each parameter seperately.
225 */
226 int (*set_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state);
227 int (*get_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state);
102}; 228};
103 229
104struct analog_demod_info { 230struct analog_demod_info {
@@ -142,7 +268,7 @@ struct dvb_frontend_ops {
142 unsigned int *delay, 268 unsigned int *delay,
143 fe_status_t *status); 269 fe_status_t *status);
144 /* get frontend tuning algorithm from the module */ 270 /* get frontend tuning algorithm from the module */
145 int (*get_frontend_algo)(struct dvb_frontend *fe); 271 enum dvbfe_algo (*get_frontend_algo)(struct dvb_frontend *fe);
146 272
147 /* these two are only used for the swzigzag code */ 273 /* these two are only used for the swzigzag code */
148 int (*set_frontend)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params); 274 int (*set_frontend)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params);
@@ -167,6 +293,12 @@ struct dvb_frontend_ops {
167 int (*i2c_gate_ctrl)(struct dvb_frontend* fe, int enable); 293 int (*i2c_gate_ctrl)(struct dvb_frontend* fe, int enable);
168 int (*ts_bus_ctrl)(struct dvb_frontend* fe, int acquire); 294 int (*ts_bus_ctrl)(struct dvb_frontend* fe, int acquire);
169 295
296 /* These callbacks are for devices that implement their own
297 * tuning algorithms, rather than a simple swzigzag
298 */
299 enum dvbfe_search (*search)(struct dvb_frontend *fe, struct dvb_frontend_parameters *p);
300 int (*track)(struct dvb_frontend *fe, struct dvb_frontend_parameters *p);
301
170 struct dvb_tuner_ops tuner_ops; 302 struct dvb_tuner_ops tuner_ops;
171 struct analog_demod_ops analog_ops; 303 struct analog_demod_ops analog_ops;
172 304
diff --git a/drivers/media/dvb/dvb-core/dvbdev.c b/drivers/media/dvb/dvb-core/dvbdev.c
index a113744a56cc..6c571d9f011c 100644
--- a/drivers/media/dvb/dvb-core/dvbdev.c
+++ b/drivers/media/dvb/dvb-core/dvbdev.c
@@ -50,33 +50,27 @@ static const char * const dnames[] = {
50 "net", "osd" 50 "net", "osd"
51}; 51};
52 52
53#ifdef CONFIG_DVB_DYNAMIC_MINORS
54#define MAX_DVB_MINORS 256
55#define DVB_MAX_IDS MAX_DVB_MINORS
56#else
53#define DVB_MAX_IDS 4 57#define DVB_MAX_IDS 4
54#define nums2minor(num,type,id) ((num << 6) | (id << 4) | type) 58#define nums2minor(num,type,id) ((num << 6) | (id << 4) | type)
55#define MAX_DVB_MINORS (DVB_MAX_ADAPTERS*64) 59#define MAX_DVB_MINORS (DVB_MAX_ADAPTERS*64)
60#endif
56 61
57static struct class *dvb_class; 62static struct class *dvb_class;
58 63
59static struct dvb_device* dvbdev_find_device (int minor) 64static struct dvb_device *dvb_minors[MAX_DVB_MINORS];
60{ 65static DECLARE_RWSEM(minor_rwsem);
61 struct dvb_adapter *adap;
62
63 list_for_each_entry(adap, &dvb_adapter_list, list_head) {
64 struct dvb_device *dev;
65 list_for_each_entry(dev, &adap->device_list, list_head)
66 if (nums2minor(adap->num, dev->type, dev->id) == minor)
67 return dev;
68 }
69
70 return NULL;
71}
72
73 66
74static int dvb_device_open(struct inode *inode, struct file *file) 67static int dvb_device_open(struct inode *inode, struct file *file)
75{ 68{
76 struct dvb_device *dvbdev; 69 struct dvb_device *dvbdev;
77 70
78 lock_kernel(); 71 lock_kernel();
79 dvbdev = dvbdev_find_device (iminor(inode)); 72 down_read(&minor_rwsem);
73 dvbdev = dvb_minors[iminor(inode)];
80 74
81 if (dvbdev && dvbdev->fops) { 75 if (dvbdev && dvbdev->fops) {
82 int err = 0; 76 int err = 0;
@@ -92,9 +86,11 @@ static int dvb_device_open(struct inode *inode, struct file *file)
92 file->f_op = fops_get(old_fops); 86 file->f_op = fops_get(old_fops);
93 } 87 }
94 fops_put(old_fops); 88 fops_put(old_fops);
89 up_read(&minor_rwsem);
95 unlock_kernel(); 90 unlock_kernel();
96 return err; 91 return err;
97 } 92 }
93 up_read(&minor_rwsem);
98 unlock_kernel(); 94 unlock_kernel();
99 return -ENODEV; 95 return -ENODEV;
100} 96}
@@ -192,6 +188,7 @@ int dvb_register_device(struct dvb_adapter *adap, struct dvb_device **pdvbdev,
192 struct dvb_device *dvbdev; 188 struct dvb_device *dvbdev;
193 struct file_operations *dvbdevfops; 189 struct file_operations *dvbdevfops;
194 struct device *clsdev; 190 struct device *clsdev;
191 int minor;
195 int id; 192 int id;
196 193
197 mutex_lock(&dvbdev_register_lock); 194 mutex_lock(&dvbdev_register_lock);
@@ -231,11 +228,31 @@ int dvb_register_device(struct dvb_adapter *adap, struct dvb_device **pdvbdev,
231 228
232 list_add_tail (&dvbdev->list_head, &adap->device_list); 229 list_add_tail (&dvbdev->list_head, &adap->device_list);
233 230
231 down_write(&minor_rwsem);
232#ifdef CONFIG_DVB_DYNAMIC_MINORS
233 for (minor = 0; minor < MAX_DVB_MINORS; minor++)
234 if (dvb_minors[minor] == NULL)
235 break;
236
237 if (minor == MAX_DVB_MINORS) {
238 kfree(dvbdevfops);
239 kfree(dvbdev);
240 mutex_unlock(&dvbdev_register_lock);
241 return -EINVAL;
242 }
243#else
244 minor = nums2minor(adap->num, type, id);
245#endif
246
247 dvbdev->minor = minor;
248 dvb_minors[minor] = dvbdev;
249 up_write(&minor_rwsem);
250
234 mutex_unlock(&dvbdev_register_lock); 251 mutex_unlock(&dvbdev_register_lock);
235 252
236 clsdev = device_create(dvb_class, adap->device, 253 clsdev = device_create(dvb_class, adap->device,
237 MKDEV(DVB_MAJOR, nums2minor(adap->num, type, id)), 254 MKDEV(DVB_MAJOR, minor),
238 NULL, "dvb%d.%s%d", adap->num, dnames[type], id); 255 dvbdev, "dvb%d.%s%d", adap->num, dnames[type], id);
239 if (IS_ERR(clsdev)) { 256 if (IS_ERR(clsdev)) {
240 printk(KERN_ERR "%s: failed to create device dvb%d.%s%d (%ld)\n", 257 printk(KERN_ERR "%s: failed to create device dvb%d.%s%d (%ld)\n",
241 __func__, adap->num, dnames[type], id, PTR_ERR(clsdev)); 258 __func__, adap->num, dnames[type], id, PTR_ERR(clsdev));
@@ -243,8 +260,7 @@ int dvb_register_device(struct dvb_adapter *adap, struct dvb_device **pdvbdev,
243 } 260 }
244 261
245 dprintk(KERN_DEBUG "DVB: register adapter%d/%s%d @ minor: %i (0x%02x)\n", 262 dprintk(KERN_DEBUG "DVB: register adapter%d/%s%d @ minor: %i (0x%02x)\n",
246 adap->num, dnames[type], id, nums2minor(adap->num, type, id), 263 adap->num, dnames[type], id, minor, minor);
247 nums2minor(adap->num, type, id));
248 264
249 return 0; 265 return 0;
250} 266}
@@ -256,8 +272,11 @@ void dvb_unregister_device(struct dvb_device *dvbdev)
256 if (!dvbdev) 272 if (!dvbdev)
257 return; 273 return;
258 274
259 device_destroy(dvb_class, MKDEV(DVB_MAJOR, nums2minor(dvbdev->adapter->num, 275 down_write(&minor_rwsem);
260 dvbdev->type, dvbdev->id))); 276 dvb_minors[dvbdev->minor] = NULL;
277 up_write(&minor_rwsem);
278
279 device_destroy(dvb_class, MKDEV(DVB_MAJOR, dvbdev->minor));
261 280
262 list_del (&dvbdev->list_head); 281 list_del (&dvbdev->list_head);
263 kfree (dvbdev->fops); 282 kfree (dvbdev->fops);
@@ -413,6 +432,15 @@ out:
413 return err; 432 return err;
414} 433}
415 434
435static int dvb_uevent(struct device *dev, struct kobj_uevent_env *env)
436{
437 struct dvb_device *dvbdev = dev_get_drvdata(dev);
438
439 add_uevent_var(env, "DVB_DEVICE_NUM=%d", dvbdev->id);
440 add_uevent_var(env, "DVB_ADAPTER_NUM=%d", dvbdev->adapter->num);
441 return 0;
442}
443
416static int __init init_dvbdev(void) 444static int __init init_dvbdev(void)
417{ 445{
418 int retval; 446 int retval;
@@ -434,6 +462,7 @@ static int __init init_dvbdev(void)
434 retval = PTR_ERR(dvb_class); 462 retval = PTR_ERR(dvb_class);
435 goto error; 463 goto error;
436 } 464 }
465 dvb_class->dev_uevent = dvb_uevent;
437 return 0; 466 return 0;
438 467
439error: 468error:
diff --git a/drivers/media/dvb/dvb-core/dvbdev.h b/drivers/media/dvb/dvb-core/dvbdev.h
index 574e336bac35..dca49cf962e8 100644
--- a/drivers/media/dvb/dvb-core/dvbdev.h
+++ b/drivers/media/dvb/dvb-core/dvbdev.h
@@ -74,6 +74,7 @@ struct dvb_device {
74 struct file_operations *fops; 74 struct file_operations *fops;
75 struct dvb_adapter *adapter; 75 struct dvb_adapter *adapter;
76 int type; 76 int type;
77 int minor;
77 u32 id; 78 u32 id;
78 79
79 /* in theory, 'users' can vanish now, 80 /* in theory, 'users' can vanish now,
diff --git a/drivers/media/dvb/dvb-usb/af9015.c b/drivers/media/dvb/dvb-usb/af9015.c
index e9ab0249d133..e1e9aa5c6b84 100644
--- a/drivers/media/dvb/dvb-usb/af9015.c
+++ b/drivers/media/dvb/dvb-usb/af9015.c
@@ -733,9 +733,19 @@ static int af9015_read_config(struct usb_device *udev)
733 af9015_config.ir_table_size = 733 af9015_config.ir_table_size =
734 ARRAY_SIZE(af9015_ir_table_mygictv); 734 ARRAY_SIZE(af9015_ir_table_mygictv);
735 break; 735 break;
736 case AF9015_REMOTE_DIGITTRADE_DVB_T:
737 af9015_properties[i].rc_key_map =
738 af9015_rc_keys_digittrade;
739 af9015_properties[i].rc_key_map_size =
740 ARRAY_SIZE(af9015_rc_keys_digittrade);
741 af9015_config.ir_table =
742 af9015_ir_table_digittrade;
743 af9015_config.ir_table_size =
744 ARRAY_SIZE(af9015_ir_table_digittrade);
745 break;
736 } 746 }
737 } else { 747 } else {
738 switch (udev->descriptor.idVendor) { 748 switch (le16_to_cpu(udev->descriptor.idVendor)) {
739 case USB_VID_LEADTEK: 749 case USB_VID_LEADTEK:
740 af9015_properties[i].rc_key_map = 750 af9015_properties[i].rc_key_map =
741 af9015_rc_keys_leadtek; 751 af9015_rc_keys_leadtek;
@@ -748,7 +758,7 @@ static int af9015_read_config(struct usb_device *udev)
748 break; 758 break;
749 case USB_VID_VISIONPLUS: 759 case USB_VID_VISIONPLUS:
750 if (udev->descriptor.idProduct == 760 if (udev->descriptor.idProduct ==
751 USB_PID_AZUREWAVE_AD_TU700) { 761 cpu_to_le16(USB_PID_AZUREWAVE_AD_TU700)) {
752 af9015_properties[i].rc_key_map = 762 af9015_properties[i].rc_key_map =
753 af9015_rc_keys_twinhan; 763 af9015_rc_keys_twinhan;
754 af9015_properties[i].rc_key_map_size = 764 af9015_properties[i].rc_key_map_size =
@@ -800,6 +810,16 @@ static int af9015_read_config(struct usb_device *udev)
800 ARRAY_SIZE(af9015_ir_table_msi); 810 ARRAY_SIZE(af9015_ir_table_msi);
801 } 811 }
802 break; 812 break;
813 case USB_VID_AVERMEDIA:
814 af9015_properties[i].rc_key_map =
815 af9015_rc_keys_avermedia;
816 af9015_properties[i].rc_key_map_size =
817 ARRAY_SIZE(af9015_rc_keys_avermedia);
818 af9015_config.ir_table =
819 af9015_ir_table_avermedia;
820 af9015_config.ir_table_size =
821 ARRAY_SIZE(af9015_ir_table_avermedia);
822 break;
803 } 823 }
804 } 824 }
805 } 825 }
@@ -1191,6 +1211,7 @@ static struct usb_device_id af9015_usb_table[] = {
1191 {USB_DEVICE(USB_VID_TELESTAR, USB_PID_TELESTAR_STARSTICK_2)}, 1211 {USB_DEVICE(USB_VID_TELESTAR, USB_PID_TELESTAR_STARSTICK_2)},
1192 {USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A309)}, 1212 {USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A309)},
1193/* 15 */{USB_DEVICE(USB_VID_MSI_2, USB_PID_MSI_DIGI_VOX_MINI_III)}, 1213/* 15 */{USB_DEVICE(USB_VID_MSI_2, USB_PID_MSI_DIGI_VOX_MINI_III)},
1214 {USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_395U)},
1194 {0}, 1215 {0},
1195}; 1216};
1196MODULE_DEVICE_TABLE(usb, af9015_usb_table); 1217MODULE_DEVICE_TABLE(usb, af9015_usb_table);
@@ -1343,7 +1364,7 @@ static struct dvb_usb_device_properties af9015_properties[] = {
1343 1364
1344 .i2c_algo = &af9015_i2c_algo, 1365 .i2c_algo = &af9015_i2c_algo,
1345 1366
1346 .num_device_descs = 6, 1367 .num_device_descs = 7,
1347 .devices = { 1368 .devices = {
1348 { 1369 {
1349 .name = "Xtensions XD-380", 1370 .name = "Xtensions XD-380",
@@ -1375,6 +1396,12 @@ static struct dvb_usb_device_properties af9015_properties[] = {
1375 .cold_ids = {&af9015_usb_table[15], NULL}, 1396 .cold_ids = {&af9015_usb_table[15], NULL},
1376 .warm_ids = {NULL}, 1397 .warm_ids = {NULL},
1377 }, 1398 },
1399 {
1400 .name = "KWorld USB DVB-T TV Stick II " \
1401 "(VS-DVB-T 395U)",
1402 .cold_ids = {&af9015_usb_table[16], NULL},
1403 .warm_ids = {NULL},
1404 },
1378 } 1405 }
1379 } 1406 }
1380}; 1407};
diff --git a/drivers/media/dvb/dvb-usb/af9015.h b/drivers/media/dvb/dvb-usb/af9015.h
index 6c3c97293316..21c7782f4889 100644
--- a/drivers/media/dvb/dvb-usb/af9015.h
+++ b/drivers/media/dvb/dvb-usb/af9015.h
@@ -123,6 +123,7 @@ enum af9015_remote {
123 AF9015_REMOTE_A_LINK_DTU_M, 123 AF9015_REMOTE_A_LINK_DTU_M,
124 AF9015_REMOTE_MSI_DIGIVOX_MINI_II_V3, 124 AF9015_REMOTE_MSI_DIGIVOX_MINI_II_V3,
125 AF9015_REMOTE_MYGICTV_U718, 125 AF9015_REMOTE_MYGICTV_U718,
126 AF9015_REMOTE_DIGITTRADE_DVB_T,
126}; 127};
127 128
128/* Leadtek WinFast DTV Dongle Gold */ 129/* Leadtek WinFast DTV Dongle Gold */
@@ -520,4 +521,143 @@ static u8 af9015_ir_table_kworld[] = {
520 0x86, 0x6b, 0x23, 0xdc, 0x45, 0x07, 0x00, 521 0x86, 0x6b, 0x23, 0xdc, 0x45, 0x07, 0x00,
521}; 522};
522 523
524/* AverMedia Volar X */
525static struct dvb_usb_rc_key af9015_rc_keys_avermedia[] = {
526 { 0x05, 0x3d, KEY_PROG1 }, /* SOURCE */
527 { 0x05, 0x12, KEY_POWER }, /* POWER */
528 { 0x05, 0x1e, KEY_1 }, /* 1 */
529 { 0x05, 0x1f, KEY_2 }, /* 2 */
530 { 0x05, 0x20, KEY_3 }, /* 3 */
531 { 0x05, 0x21, KEY_4 }, /* 4 */
532 { 0x05, 0x22, KEY_5 }, /* 5 */
533 { 0x05, 0x23, KEY_6 }, /* 6 */
534 { 0x05, 0x24, KEY_7 }, /* 7 */
535 { 0x05, 0x25, KEY_8 }, /* 8 */
536 { 0x05, 0x26, KEY_9 }, /* 9 */
537 { 0x05, 0x3f, KEY_LEFT }, /* L / DISPLAY */
538 { 0x05, 0x27, KEY_0 }, /* 0 */
539 { 0x05, 0x0f, KEY_RIGHT }, /* R / CH RTN */
540 { 0x05, 0x18, KEY_PROG2 }, /* SNAP SHOT */
541 { 0x05, 0x1c, KEY_PROG3 }, /* 16-CH PREV */
542 { 0x05, 0x2d, KEY_VOLUMEDOWN }, /* VOL DOWN */
543 { 0x05, 0x3e, KEY_ZOOM }, /* FULL SCREEN */
544 { 0x05, 0x2e, KEY_VOLUMEUP }, /* VOL UP */
545 { 0x05, 0x10, KEY_MUTE }, /* MUTE */
546 { 0x05, 0x04, KEY_AUDIO }, /* AUDIO */
547 { 0x05, 0x15, KEY_RECORD }, /* RECORD */
548 { 0x05, 0x11, KEY_PLAY }, /* PLAY */
549 { 0x05, 0x16, KEY_STOP }, /* STOP */
550 { 0x05, 0x0c, KEY_PLAYPAUSE }, /* TIMESHIFT / PAUSE */
551 { 0x05, 0x05, KEY_BACK }, /* << / RED */
552 { 0x05, 0x09, KEY_FORWARD }, /* >> / YELLOW */
553 { 0x05, 0x17, KEY_TEXT }, /* TELETEXT */
554 { 0x05, 0x0a, KEY_EPG }, /* EPG */
555 { 0x05, 0x13, KEY_MENU }, /* MENU */
556
557 { 0x05, 0x0e, KEY_CHANNELUP }, /* CH UP */
558 { 0x05, 0x0d, KEY_CHANNELDOWN }, /* CH DOWN */
559 { 0x05, 0x19, KEY_FIRST }, /* |<< / GREEN */
560 { 0x05, 0x08, KEY_LAST }, /* >>| / BLUE */
561};
562
563static u8 af9015_ir_table_avermedia[] = {
564 0x02, 0xfd, 0x00, 0xff, 0x12, 0x05, 0x00,
565 0x02, 0xfd, 0x01, 0xfe, 0x3d, 0x05, 0x00,
566 0x02, 0xfd, 0x03, 0xfc, 0x17, 0x05, 0x00,
567 0x02, 0xfd, 0x04, 0xfb, 0x0a, 0x05, 0x00,
568 0x02, 0xfd, 0x05, 0xfa, 0x1e, 0x05, 0x00,
569 0x02, 0xfd, 0x06, 0xf9, 0x1f, 0x05, 0x00,
570 0x02, 0xfd, 0x07, 0xf8, 0x20, 0x05, 0x00,
571 0x02, 0xfd, 0x09, 0xf6, 0x21, 0x05, 0x00,
572 0x02, 0xfd, 0x0a, 0xf5, 0x22, 0x05, 0x00,
573 0x02, 0xfd, 0x0b, 0xf4, 0x23, 0x05, 0x00,
574 0x02, 0xfd, 0x0d, 0xf2, 0x24, 0x05, 0x00,
575 0x02, 0xfd, 0x0e, 0xf1, 0x25, 0x05, 0x00,
576 0x02, 0xfd, 0x0f, 0xf0, 0x26, 0x05, 0x00,
577 0x02, 0xfd, 0x11, 0xee, 0x27, 0x05, 0x00,
578 0x02, 0xfd, 0x08, 0xf7, 0x04, 0x05, 0x00,
579 0x02, 0xfd, 0x0c, 0xf3, 0x3e, 0x05, 0x00,
580 0x02, 0xfd, 0x10, 0xef, 0x1c, 0x05, 0x00,
581 0x02, 0xfd, 0x12, 0xed, 0x3f, 0x05, 0x00,
582 0x02, 0xfd, 0x13, 0xec, 0x0f, 0x05, 0x00,
583 0x02, 0xfd, 0x14, 0xeb, 0x10, 0x05, 0x00,
584 0x02, 0xfd, 0x15, 0xea, 0x13, 0x05, 0x00,
585 0x02, 0xfd, 0x17, 0xe8, 0x18, 0x05, 0x00,
586 0x02, 0xfd, 0x18, 0xe7, 0x11, 0x05, 0x00,
587 0x02, 0xfd, 0x19, 0xe6, 0x15, 0x05, 0x00,
588 0x02, 0xfd, 0x1a, 0xe5, 0x0c, 0x05, 0x00,
589 0x02, 0xfd, 0x1b, 0xe4, 0x16, 0x05, 0x00,
590 0x02, 0xfd, 0x1c, 0xe3, 0x09, 0x05, 0x00,
591 0x02, 0xfd, 0x1d, 0xe2, 0x05, 0x05, 0x00,
592 0x02, 0xfd, 0x1e, 0xe1, 0x2d, 0x05, 0x00,
593 0x02, 0xfd, 0x1f, 0xe0, 0x2e, 0x05, 0x00,
594 0x03, 0xfc, 0x00, 0xff, 0x08, 0x05, 0x00,
595 0x03, 0xfc, 0x01, 0xfe, 0x19, 0x05, 0x00,
596 0x03, 0xfc, 0x02, 0xfd, 0x0d, 0x05, 0x00,
597 0x03, 0xfc, 0x03, 0xfc, 0x0e, 0x05, 0x00,
598};
599
600/* Digittrade DVB-T USB Stick */
601static struct dvb_usb_rc_key af9015_rc_keys_digittrade[] = {
602 { 0x01, 0x0f, KEY_LAST }, /* RETURN */
603 { 0x05, 0x17, KEY_TEXT }, /* TELETEXT */
604 { 0x01, 0x08, KEY_EPG }, /* EPG */
605 { 0x05, 0x13, KEY_POWER }, /* POWER */
606 { 0x01, 0x09, KEY_ZOOM }, /* FULLSCREEN */
607 { 0x00, 0x40, KEY_AUDIO }, /* DUAL SOUND */
608 { 0x00, 0x2c, KEY_PRINT }, /* SNAPSHOT */
609 { 0x05, 0x16, KEY_SUBTITLE }, /* SUBTITLE */
610 { 0x00, 0x52, KEY_CHANNELUP }, /* CH Up */
611 { 0x00, 0x51, KEY_CHANNELDOWN },/* Ch Dn */
612 { 0x00, 0x57, KEY_VOLUMEUP }, /* Vol Up */
613 { 0x00, 0x56, KEY_VOLUMEDOWN }, /* Vol Dn */
614 { 0x01, 0x10, KEY_MUTE }, /* MUTE */
615 { 0x00, 0x27, KEY_0 },
616 { 0x00, 0x1e, KEY_1 },
617 { 0x00, 0x1f, KEY_2 },
618 { 0x00, 0x20, KEY_3 },
619 { 0x00, 0x21, KEY_4 },
620 { 0x00, 0x22, KEY_5 },
621 { 0x00, 0x23, KEY_6 },
622 { 0x00, 0x24, KEY_7 },
623 { 0x00, 0x25, KEY_8 },
624 { 0x00, 0x26, KEY_9 },
625 { 0x01, 0x17, KEY_PLAYPAUSE }, /* TIMESHIFT */
626 { 0x01, 0x15, KEY_RECORD }, /* RECORD */
627 { 0x03, 0x13, KEY_PLAY }, /* PLAY */
628 { 0x01, 0x16, KEY_STOP }, /* STOP */
629 { 0x01, 0x13, KEY_PAUSE }, /* PAUSE */
630};
631
632static u8 af9015_ir_table_digittrade[] = {
633 0x00, 0xff, 0x06, 0xf9, 0x13, 0x05, 0x00,
634 0x00, 0xff, 0x4d, 0xb2, 0x17, 0x01, 0x00,
635 0x00, 0xff, 0x1f, 0xe0, 0x2c, 0x00, 0x00,
636 0x00, 0xff, 0x0a, 0xf5, 0x15, 0x01, 0x00,
637 0x00, 0xff, 0x0e, 0xf1, 0x16, 0x01, 0x00,
638 0x00, 0xff, 0x09, 0xf6, 0x09, 0x01, 0x00,
639 0x00, 0xff, 0x01, 0xfe, 0x08, 0x01, 0x00,
640 0x00, 0xff, 0x05, 0xfa, 0x10, 0x01, 0x00,
641 0x00, 0xff, 0x02, 0xfd, 0x56, 0x00, 0x00,
642 0x00, 0xff, 0x40, 0xbf, 0x57, 0x00, 0x00,
643 0x00, 0xff, 0x19, 0xe6, 0x52, 0x00, 0x00,
644 0x00, 0xff, 0x17, 0xe8, 0x51, 0x00, 0x00,
645 0x00, 0xff, 0x10, 0xef, 0x0f, 0x01, 0x00,
646 0x00, 0xff, 0x54, 0xab, 0x27, 0x00, 0x00,
647 0x00, 0xff, 0x1b, 0xe4, 0x1e, 0x00, 0x00,
648 0x00, 0xff, 0x11, 0xee, 0x1f, 0x00, 0x00,
649 0x00, 0xff, 0x15, 0xea, 0x20, 0x00, 0x00,
650 0x00, 0xff, 0x12, 0xed, 0x21, 0x00, 0x00,
651 0x00, 0xff, 0x16, 0xe9, 0x22, 0x00, 0x00,
652 0x00, 0xff, 0x4c, 0xb3, 0x23, 0x00, 0x00,
653 0x00, 0xff, 0x48, 0xb7, 0x24, 0x00, 0x00,
654 0x00, 0xff, 0x04, 0xfb, 0x25, 0x00, 0x00,
655 0x00, 0xff, 0x00, 0xff, 0x26, 0x00, 0x00,
656 0x00, 0xff, 0x1e, 0xe1, 0x13, 0x03, 0x00,
657 0x00, 0xff, 0x1a, 0xe5, 0x13, 0x01, 0x00,
658 0x00, 0xff, 0x03, 0xfc, 0x17, 0x05, 0x00,
659 0x00, 0xff, 0x0d, 0xf2, 0x16, 0x05, 0x00,
660 0x00, 0xff, 0x1d, 0xe2, 0x40, 0x00, 0x00,
661};
662
523#endif 663#endif
diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c
index cd2edbcaa097..5017f08b14a6 100644
--- a/drivers/media/dvb/dvb-usb/anysee.c
+++ b/drivers/media/dvb/dvb-usb/anysee.c
@@ -153,7 +153,7 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
153 int num) 153 int num)
154{ 154{
155 struct dvb_usb_device *d = i2c_get_adapdata(adap); 155 struct dvb_usb_device *d = i2c_get_adapdata(adap);
156 int ret, inc, i = 0; 156 int ret = 0, inc, i = 0;
157 157
158 if (mutex_lock_interruptible(&d->i2c_mutex) < 0) 158 if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
159 return -EAGAIN; 159 return -EAGAIN;
diff --git a/drivers/media/dvb/dvb-usb/cinergyT2-core.c b/drivers/media/dvb/dvb-usb/cinergyT2-core.c
index 3ac9f74e9fbf..80e37a0d0892 100644
--- a/drivers/media/dvb/dvb-usb/cinergyT2-core.c
+++ b/drivers/media/dvb/dvb-usb/cinergyT2-core.c
@@ -32,7 +32,6 @@
32 32
33/* debug */ 33/* debug */
34int dvb_usb_cinergyt2_debug; 34int dvb_usb_cinergyt2_debug;
35int disable_remote;
36 35
37module_param_named(debug, dvb_usb_cinergyt2_debug, int, 0644); 36module_param_named(debug, dvb_usb_cinergyt2_debug, int, 0644);
38MODULE_PARM_DESC(debug, "set debugging level (1=info, xfer=2, rc=4 " 37MODULE_PARM_DESC(debug, "set debugging level (1=info, xfer=2, rc=4 "
@@ -45,7 +44,7 @@ struct cinergyt2_state {
45}; 44};
46 45
47/* We are missing a release hook with usb_device data */ 46/* We are missing a release hook with usb_device data */
48struct dvb_usb_device *cinergyt2_usb_device; 47static struct dvb_usb_device *cinergyt2_usb_device;
49 48
50static struct dvb_usb_device_properties cinergyt2_properties; 49static struct dvb_usb_device_properties cinergyt2_properties;
51 50
diff --git a/drivers/media/dvb/dvb-usb/cinergyT2.h b/drivers/media/dvb/dvb-usb/cinergyT2.h
index 11d79eb384c8..84efe03771eb 100644
--- a/drivers/media/dvb/dvb-usb/cinergyT2.h
+++ b/drivers/media/dvb/dvb-usb/cinergyT2.h
@@ -70,11 +70,11 @@ struct dvbt_get_status_msg {
70 uint8_t bandwidth; 70 uint8_t bandwidth;
71 uint16_t tps; 71 uint16_t tps;
72 uint8_t flags; 72 uint8_t flags;
73 uint16_t gain; 73 __le16 gain;
74 uint8_t snr; 74 uint8_t snr;
75 uint32_t viterbi_error_rate; 75 __le32 viterbi_error_rate;
76 uint32_t rs_error_rate; 76 uint32_t rs_error_rate;
77 uint32_t uncorrected_block_count; 77 __le32 uncorrected_block_count;
78 uint8_t lock_bits; 78 uint8_t lock_bits;
79 uint8_t prev_lock_bits; 79 uint8_t prev_lock_bits;
80} __attribute__((packed)); 80} __attribute__((packed));
@@ -82,9 +82,9 @@ struct dvbt_get_status_msg {
82 82
83struct dvbt_set_parameters_msg { 83struct dvbt_set_parameters_msg {
84 uint8_t cmd; 84 uint8_t cmd;
85 uint32_t freq; 85 __le32 freq;
86 uint8_t bandwidth; 86 uint8_t bandwidth;
87 uint16_t tps; 87 __le16 tps;
88 uint8_t flags; 88 uint8_t flags;
89} __attribute__((packed)); 89} __attribute__((packed));
90 90
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index 7380b94b3b36..a4fca3fca5ee 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -96,6 +96,7 @@
96#define USB_PID_GRANDTEC_DVBT_USB_COLD 0x0fa0 96#define USB_PID_GRANDTEC_DVBT_USB_COLD 0x0fa0
97#define USB_PID_GRANDTEC_DVBT_USB_WARM 0x0fa1 97#define USB_PID_GRANDTEC_DVBT_USB_WARM 0x0fa1
98#define USB_PID_KWORLD_399U 0xe399 98#define USB_PID_KWORLD_399U 0xe399
99#define USB_PID_KWORLD_395U 0xe396
99#define USB_PID_KWORLD_PC160_2T 0xc160 100#define USB_PID_KWORLD_PC160_2T 0xc160
100#define USB_PID_KWORLD_VSTREAM_COLD 0x17de 101#define USB_PID_KWORLD_VSTREAM_COLD 0x17de
101#define USB_PID_KWORLD_VSTREAM_WARM 0x17df 102#define USB_PID_KWORLD_VSTREAM_WARM 0x17df
diff --git a/drivers/media/dvb/dvb-usb/dw2102.c b/drivers/media/dvb/dvb-usb/dw2102.c
index 6286fbbe7fb5..c65f273ff313 100644
--- a/drivers/media/dvb/dvb-usb/dw2102.c
+++ b/drivers/media/dvb/dvb-usb/dw2102.c
@@ -9,7 +9,6 @@
9* 9*
10* see Documentation/dvb/README.dvb-usb for more information 10* see Documentation/dvb/README.dvb-usb for more information
11*/ 11*/
12#include <linux/version.h>
13#include "dw2102.h" 12#include "dw2102.h"
14#include "si21xx.h" 13#include "si21xx.h"
15#include "stv0299.h" 14#include "stv0299.h"
@@ -27,6 +26,10 @@
27#define USB_PID_DW2104 0x2104 26#define USB_PID_DW2104 0x2104
28#endif 27#endif
29 28
29#ifndef USB_PID_CINERGY_S
30#define USB_PID_CINERGY_S 0x0064
31#endif
32
30#define DW210X_READ_MSG 0 33#define DW210X_READ_MSG 0
31#define DW210X_WRITE_MSG 1 34#define DW210X_WRITE_MSG 1
32 35
@@ -578,6 +581,7 @@ static struct usb_device_id dw2102_table[] = {
578 {USB_DEVICE(USB_VID_CYPRESS, 0x2101)}, 581 {USB_DEVICE(USB_VID_CYPRESS, 0x2101)},
579 {USB_DEVICE(USB_VID_CYPRESS, 0x2104)}, 582 {USB_DEVICE(USB_VID_CYPRESS, 0x2104)},
580 {USB_DEVICE(0x9022, 0xd650)}, 583 {USB_DEVICE(0x9022, 0xd650)},
584 {USB_DEVICE(USB_VID_TERRATEC, USB_PID_CINERGY_S)},
581 { } 585 { }
582}; 586};
583 587
@@ -647,6 +651,7 @@ static int dw2102_load_firmware(struct usb_device *dev,
647 dw210x_op_rw(dev, 0xbf, 0x0040, 0, &reset, 0, 651 dw210x_op_rw(dev, 0xbf, 0x0040, 0, &reset, 0,
648 DW210X_WRITE_MSG); 652 DW210X_WRITE_MSG);
649 break; 653 break;
654 case USB_PID_CINERGY_S:
650 case USB_PID_DW2102: 655 case USB_PID_DW2102:
651 dw210x_op_rw(dev, 0xbf, 0x0040, 0, &reset, 0, 656 dw210x_op_rw(dev, 0xbf, 0x0040, 0, &reset, 0,
652 DW210X_WRITE_MSG); 657 DW210X_WRITE_MSG);
@@ -655,7 +660,7 @@ static int dw2102_load_firmware(struct usb_device *dev,
655 /* check STV0299 frontend */ 660 /* check STV0299 frontend */
656 dw210x_op_rw(dev, 0xb5, 0, 0, &reset16[0], 2, 661 dw210x_op_rw(dev, 0xb5, 0, 0, &reset16[0], 2,
657 DW210X_READ_MSG); 662 DW210X_READ_MSG);
658 if (reset16[0] == 0xa1) { 663 if ((reset16[0] == 0xa1) || (reset16[0] == 0x80)) {
659 dw2102_properties.i2c_algo = &dw2102_i2c_algo; 664 dw2102_properties.i2c_algo = &dw2102_i2c_algo;
660 dw2102_properties.adapter->tuner_attach = &dw2102_tuner_attach; 665 dw2102_properties.adapter->tuner_attach = &dw2102_tuner_attach;
661 break; 666 break;
@@ -726,7 +731,7 @@ static struct dvb_usb_device_properties dw2102_properties = {
726 }, 731 },
727 } 732 }
728 }, 733 },
729 .num_device_descs = 2, 734 .num_device_descs = 3,
730 .devices = { 735 .devices = {
731 {"DVBWorld DVB-S 2102 USB2.0", 736 {"DVBWorld DVB-S 2102 USB2.0",
732 {&dw2102_table[0], NULL}, 737 {&dw2102_table[0], NULL},
@@ -736,6 +741,10 @@ static struct dvb_usb_device_properties dw2102_properties = {
736 {&dw2102_table[1], NULL}, 741 {&dw2102_table[1], NULL},
737 {NULL}, 742 {NULL},
738 }, 743 },
744 {"TerraTec Cinergy S USB",
745 {&dw2102_table[4], NULL},
746 {NULL},
747 },
739 } 748 }
740}; 749};
741 750
diff --git a/drivers/media/dvb/dvb-usb/gp8psk-fe.c b/drivers/media/dvb/dvb-usb/gp8psk-fe.c
index 262a858c3068..20eadf9318e0 100644
--- a/drivers/media/dvb/dvb-usb/gp8psk-fe.c
+++ b/drivers/media/dvb/dvb-usb/gp8psk-fe.c
@@ -25,6 +25,20 @@ struct gp8psk_fe_state {
25 unsigned long status_check_interval; 25 unsigned long status_check_interval;
26}; 26};
27 27
28static int gp8psk_tuned_to_DCII(struct dvb_frontend *fe)
29{
30 struct gp8psk_fe_state *st = fe->demodulator_priv;
31 u8 status;
32 gp8psk_usb_in_op(st->d, GET_8PSK_CONFIG, 0, 0, &status, 1);
33 return status & bmDCtuned;
34}
35
36static int gp8psk_set_tuner_mode(struct dvb_frontend *fe, int mode)
37{
38 struct gp8psk_fe_state *state = fe->demodulator_priv;
39 return gp8psk_usb_out_op(state->d, SET_8PSK_CONFIG, mode, 0, NULL, 0);
40}
41
28static int gp8psk_fe_update_status(struct gp8psk_fe_state *st) 42static int gp8psk_fe_update_status(struct gp8psk_fe_state *st)
29{ 43{
30 u8 buf[6]; 44 u8 buf[6];
@@ -99,39 +113,114 @@ static int gp8psk_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_front
99 return 0; 113 return 0;
100} 114}
101 115
116static int gp8psk_fe_set_property(struct dvb_frontend *fe,
117 struct dtv_property *tvp)
118{
119 deb_fe("%s(..)\n", __func__);
120 return 0;
121}
122
123static int gp8psk_fe_get_property(struct dvb_frontend *fe,
124 struct dtv_property *tvp)
125{
126 deb_fe("%s(..)\n", __func__);
127 return 0;
128}
129
130
102static int gp8psk_fe_set_frontend(struct dvb_frontend* fe, 131static int gp8psk_fe_set_frontend(struct dvb_frontend* fe,
103 struct dvb_frontend_parameters *fep) 132 struct dvb_frontend_parameters *fep)
104{ 133{
105 struct gp8psk_fe_state *state = fe->demodulator_priv; 134 struct gp8psk_fe_state *state = fe->demodulator_priv;
135 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
106 u8 cmd[10]; 136 u8 cmd[10];
107 u32 freq = fep->frequency * 1000; 137 u32 freq = fep->frequency * 1000;
138 int gp_product_id = le16_to_cpu(state->d->udev->descriptor.idProduct);
139
140 deb_fe("%s()\n", __func__);
108 141
109 cmd[4] = freq & 0xff; 142 cmd[4] = freq & 0xff;
110 cmd[5] = (freq >> 8) & 0xff; 143 cmd[5] = (freq >> 8) & 0xff;
111 cmd[6] = (freq >> 16) & 0xff; 144 cmd[6] = (freq >> 16) & 0xff;
112 cmd[7] = (freq >> 24) & 0xff; 145 cmd[7] = (freq >> 24) & 0xff;
113 146
114 switch(fe->ops.info.type) { 147 switch (c->delivery_system) {
115 case FE_QPSK: 148 case SYS_DVBS:
116 cmd[0] = fep->u.qpsk.symbol_rate & 0xff; 149 /* Only QPSK is supported for DVB-S */
117 cmd[1] = (fep->u.qpsk.symbol_rate >> 8) & 0xff; 150 if (c->modulation != QPSK) {
118 cmd[2] = (fep->u.qpsk.symbol_rate >> 16) & 0xff; 151 deb_fe("%s: unsupported modulation selected (%d)\n",
119 cmd[3] = (fep->u.qpsk.symbol_rate >> 24) & 0xff; 152 __func__, c->modulation);
120 cmd[8] = ADV_MOD_DVB_QPSK; 153 return -EOPNOTSUPP;
121 cmd[9] = 0x03; /*ADV_MOD_FEC_XXX*/ 154 }
155 c->fec_inner = FEC_AUTO;
122 break; 156 break;
157 case SYS_DVBS2:
158 deb_fe("%s: DVB-S2 delivery system selected\n", __func__);
159 break;
160
123 default: 161 default:
124 // other modes are unsuported right now 162 deb_fe("%s: unsupported delivery system selected (%d)\n",
125 cmd[0] = 0; 163 __func__, c->delivery_system);
126 cmd[1] = 0; 164 return -EOPNOTSUPP;
127 cmd[2] = 0; 165 }
128 cmd[3] = 0; 166
129 cmd[8] = 0; 167 cmd[0] = c->symbol_rate & 0xff;
168 cmd[1] = (c->symbol_rate >> 8) & 0xff;
169 cmd[2] = (c->symbol_rate >> 16) & 0xff;
170 cmd[3] = (c->symbol_rate >> 24) & 0xff;
171 switch (c->modulation) {
172 case QPSK:
173 if (gp_product_id == USB_PID_GENPIX_8PSK_REV_1_WARM)
174 if (gp8psk_tuned_to_DCII(fe))
175 gp8psk_bcm4500_reload(state->d);
176 switch (c->fec_inner) {
177 case FEC_1_2:
178 cmd[9] = 0; break;
179 case FEC_2_3:
180 cmd[9] = 1; break;
181 case FEC_3_4:
182 cmd[9] = 2; break;
183 case FEC_5_6:
184 cmd[9] = 3; break;
185 case FEC_7_8:
186 cmd[9] = 4; break;
187 case FEC_AUTO:
188 cmd[9] = 5; break;
189 default:
190 cmd[9] = 5; break;
191 }
192 cmd[8] = ADV_MOD_DVB_QPSK;
193 break;
194 case PSK_8: /* PSK_8 is for compatibility with DN */
195 cmd[8] = ADV_MOD_TURBO_8PSK;
196 switch (c->fec_inner) {
197 case FEC_2_3:
198 cmd[9] = 0; break;
199 case FEC_3_4:
200 cmd[9] = 1; break;
201 case FEC_3_5:
202 cmd[9] = 2; break;
203 case FEC_5_6:
204 cmd[9] = 3; break;
205 case FEC_8_9:
206 cmd[9] = 4; break;
207 default:
208 cmd[9] = 0; break;
209 }
210 break;
211 case QAM_16: /* QAM_16 is for compatibility with DN */
212 cmd[8] = ADV_MOD_TURBO_16QAM;
130 cmd[9] = 0; 213 cmd[9] = 0;
131 break; 214 break;
215 default: /* Unknown modulation */
216 deb_fe("%s: unsupported modulation selected (%d)\n",
217 __func__, c->modulation);
218 return -EOPNOTSUPP;
132 } 219 }
133 220
134 gp8psk_usb_out_op(state->d,TUNE_8PSK,0,0,cmd,10); 221 if (gp_product_id == USB_PID_GENPIX_8PSK_REV_1_WARM)
222 gp8psk_set_tuner_mode(fe, 0);
223 gp8psk_usb_out_op(state->d, TUNE_8PSK, 0, 0, cmd, 10);
135 224
136 state->lock = 0; 225 state->lock = 0;
137 state->next_status_check = jiffies; 226 state->next_status_check = jiffies;
@@ -140,13 +229,6 @@ static int gp8psk_fe_set_frontend(struct dvb_frontend* fe,
140 return 0; 229 return 0;
141} 230}
142 231
143static int gp8psk_fe_get_frontend(struct dvb_frontend* fe,
144 struct dvb_frontend_parameters *fep)
145{
146 return 0;
147}
148
149
150static int gp8psk_fe_send_diseqc_msg (struct dvb_frontend* fe, 232static int gp8psk_fe_send_diseqc_msg (struct dvb_frontend* fe,
151 struct dvb_diseqc_master_cmd *m) 233 struct dvb_diseqc_master_cmd *m)
152{ 234{
@@ -261,9 +343,13 @@ static struct dvb_frontend_ops gp8psk_fe_ops = {
261 .symbol_rate_max = 45000000, 343 .symbol_rate_max = 45000000,
262 .symbol_rate_tolerance = 500, /* ppm */ 344 .symbol_rate_tolerance = 500, /* ppm */
263 .caps = FE_CAN_INVERSION_AUTO | 345 .caps = FE_CAN_INVERSION_AUTO |
264 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 346 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
265 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 347 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
266 FE_CAN_QPSK 348 /*
349 * FE_CAN_QAM_16 is for compatibility
350 * (Myth incorrectly detects Turbo-QPSK as plain QAM-16)
351 */
352 FE_CAN_QPSK | FE_CAN_QAM_16
267 }, 353 },
268 354
269 .release = gp8psk_fe_release, 355 .release = gp8psk_fe_release,
@@ -271,8 +357,10 @@ static struct dvb_frontend_ops gp8psk_fe_ops = {
271 .init = NULL, 357 .init = NULL,
272 .sleep = NULL, 358 .sleep = NULL,
273 359
360 .set_property = gp8psk_fe_set_property,
361 .get_property = gp8psk_fe_get_property,
274 .set_frontend = gp8psk_fe_set_frontend, 362 .set_frontend = gp8psk_fe_set_frontend,
275 .get_frontend = gp8psk_fe_get_frontend, 363
276 .get_tune_settings = gp8psk_fe_get_tune_settings, 364 .get_tune_settings = gp8psk_fe_get_tune_settings,
277 365
278 .read_status = gp8psk_fe_read_status, 366 .read_status = gp8psk_fe_read_status,
diff --git a/drivers/media/dvb/dvb-usb/gp8psk.c b/drivers/media/dvb/dvb-usb/gp8psk.c
index d965a923f391..c1da962cc886 100644
--- a/drivers/media/dvb/dvb-usb/gp8psk.c
+++ b/drivers/media/dvb/dvb-usb/gp8psk.c
@@ -174,6 +174,22 @@ static int gp8psk_power_ctrl(struct dvb_usb_device *d, int onoff)
174 return 0; 174 return 0;
175} 175}
176 176
177int gp8psk_bcm4500_reload(struct dvb_usb_device *d)
178{
179 u8 buf;
180 int gp_product_id = le16_to_cpu(d->udev->descriptor.idProduct);
181 /* Turn off 8psk power */
182 if (gp8psk_usb_in_op(d, BOOT_8PSK, 0, 0, &buf, 1))
183 return -EINVAL;
184 /* Turn On 8psk power */
185 if (gp8psk_usb_in_op(d, BOOT_8PSK, 1, 0, &buf, 1))
186 return -EINVAL;
187 /* load BCM4500 firmware */
188 if (gp_product_id == USB_PID_GENPIX_8PSK_REV_1_WARM)
189 if (gp8psk_load_bcm4500fw(d))
190 return EINVAL;
191 return 0;
192}
177 193
178static int gp8psk_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) 194static int gp8psk_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff)
179{ 195{
diff --git a/drivers/media/dvb/dvb-usb/gp8psk.h b/drivers/media/dvb/dvb-usb/gp8psk.h
index e5cd8149c23d..e83a57506cfa 100644
--- a/drivers/media/dvb/dvb-usb/gp8psk.h
+++ b/drivers/media/dvb/dvb-usb/gp8psk.h
@@ -92,5 +92,6 @@ extern struct dvb_frontend * gp8psk_fe_attach(struct dvb_usb_device *d);
92extern int gp8psk_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen); 92extern int gp8psk_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen);
93extern int gp8psk_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value, 93extern int gp8psk_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value,
94 u16 index, u8 *b, int blen); 94 u16 index, u8 *b, int blen);
95extern int gp8psk_bcm4500_reload(struct dvb_usb_device *d);
95 96
96#endif 97#endif
diff --git a/drivers/media/dvb/dvb-usb/usb-urb.c b/drivers/media/dvb/dvb-usb/usb-urb.c
index da93b9e982c0..9da2cc95ca13 100644
--- a/drivers/media/dvb/dvb-usb/usb-urb.c
+++ b/drivers/media/dvb/dvb-usb/usb-urb.c
@@ -156,7 +156,8 @@ static int usb_bulk_urb_init(struct usb_data_stream *stream)
156 stream->props.u.bulk.buffersize, 156 stream->props.u.bulk.buffersize,
157 usb_urb_complete, stream); 157 usb_urb_complete, stream);
158 158
159 stream->urb_list[i]->transfer_flags = 0; 159 stream->urb_list[i]->transfer_flags = URB_NO_TRANSFER_DMA_MAP;
160 stream->urb_list[i]->transfer_dma = stream->dma_addr[i];
160 stream->urbs_initialized++; 161 stream->urbs_initialized++;
161 } 162 }
162 return 0; 163 return 0;
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 96b93e21a84b..00269560793a 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -12,6 +12,25 @@ config DVB_FE_CUSTOMISE
12 12
13 If unsure say N. 13 If unsure say N.
14 14
15comment "Multistandard (satellite) frontends"
16 depends on DVB_CORE
17
18config DVB_STB0899
19 tristate "STB0899 based"
20 depends on DVB_CORE && I2C
21 default m if DVB_FE_CUSTOMISE
22 help
23 A DVB-S/S2/DSS Multistandard demodulator. Say Y when you want
24 to support this demodulator based frontends
25
26config DVB_STB6100
27 tristate "STB6100 based tuners"
28 depends on DVB_CORE && I2C
29 default m if DVB_FE_CUSTOMISE
30 help
31 A Silicon tuner from ST used in conjunction with the STB0899
32 demodulator. Say Y when you want to support this tuner.
33
15comment "DVB-S (satellite) frontends" 34comment "DVB-S (satellite) frontends"
16 depends on DVB_CORE 35 depends on DVB_CORE
17 36
@@ -78,6 +97,13 @@ config DVB_TDA10086
78 help 97 help
79 A DVB-S tuner module. Say Y when you want to support this frontend. 98 A DVB-S tuner module. Say Y when you want to support this frontend.
80 99
100config DVB_TDA8261
101 tristate "Philips TDA8261 based"
102 depends on DVB_CORE && I2C
103 default m if DVB_FE_CUSTOMISE
104 help
105 A DVB-S tuner module. Say Y when you want to support this frontend.
106
81config DVB_VES1X93 107config DVB_VES1X93
82 tristate "VLSI VES1893 or VES1993 based" 108 tristate "VLSI VES1893 or VES1993 based"
83 depends on DVB_CORE && I2C 109 depends on DVB_CORE && I2C
@@ -92,6 +118,14 @@ config DVB_TUNER_ITD1000
92 help 118 help
93 A DVB-S tuner module. Say Y when you want to support this frontend. 119 A DVB-S tuner module. Say Y when you want to support this frontend.
94 120
121config DVB_TUNER_CX24113
122 tristate "Conexant CX24113/CX24128 tuner for DVB-S/DSS"
123 depends on DVB_CORE && I2C
124 default m if DVB_FE_CUSTOMISE
125 help
126 A DVB-S tuner module. Say Y when you want to support this frontend.
127
128
95config DVB_TDA826X 129config DVB_TDA826X
96 tristate "Philips TDA826X silicon tuner" 130 tristate "Philips TDA826X silicon tuner"
97 depends on DVB_CORE && I2C 131 depends on DVB_CORE && I2C
@@ -345,6 +379,14 @@ config DVB_LGDT330X
345 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want 379 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
346 to support this frontend. 380 to support this frontend.
347 381
382config DVB_LGDT3304
383 tristate "LG Electronics LGDT3304"
384 depends on DVB_CORE && I2C
385 default m if DVB_FE_CUSTOMISE
386 help
387 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
388 to support this frontend.
389
348config DVB_S5H1409 390config DVB_S5H1409
349 tristate "Samsung S5H1409 based" 391 tristate "Samsung S5H1409 based"
350 depends on DVB_CORE && I2C 392 depends on DVB_CORE && I2C
@@ -369,6 +411,17 @@ config DVB_S5H1411
369 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want 411 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
370 to support this frontend. 412 to support this frontend.
371 413
414comment "ISDB-T (terrestrial) frontends"
415 depends on DVB_CORE
416
417config DVB_S921
418 tristate "Sharp S921 tuner"
419 depends on DVB_CORE && I2C
420 default m if DVB_FE_CUSTOMISE
421 help
422 AN ISDB-T DQPSK, QPSK, 16QAM and 64QAM 1seg tuner module.
423 Say Y when you want to support this frontend.
424
372comment "Digital terrestrial only tuners/PLL" 425comment "Digital terrestrial only tuners/PLL"
373 depends on DVB_CORE 426 depends on DVB_CORE
374 427
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index aba79f4a63a7..af7bdf0ad4c7 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -5,8 +5,13 @@
5EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ 5EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/
6EXTRA_CFLAGS += -Idrivers/media/common/tuners/ 6EXTRA_CFLAGS += -Idrivers/media/common/tuners/
7 7
8s921-objs := s921_module.o s921_core.o
9stb0899-objs = stb0899_drv.o stb0899_algo.o
10
8obj-$(CONFIG_DVB_PLL) += dvb-pll.o 11obj-$(CONFIG_DVB_PLL) += dvb-pll.o
9obj-$(CONFIG_DVB_STV0299) += stv0299.o 12obj-$(CONFIG_DVB_STV0299) += stv0299.o
13obj-$(CONFIG_DVB_STB0899) += stb0899.o
14obj-$(CONFIG_DVB_STB6100) += stb6100.o
10obj-$(CONFIG_DVB_SP8870) += sp8870.o 15obj-$(CONFIG_DVB_SP8870) += sp8870.o
11obj-$(CONFIG_DVB_CX22700) += cx22700.o 16obj-$(CONFIG_DVB_CX22700) += cx22700.o
12obj-$(CONFIG_DVB_CX24110) += cx24110.o 17obj-$(CONFIG_DVB_CX24110) += cx24110.o
@@ -35,18 +40,21 @@ obj-$(CONFIG_DVB_OR51132) += or51132.o
35obj-$(CONFIG_DVB_BCM3510) += bcm3510.o 40obj-$(CONFIG_DVB_BCM3510) += bcm3510.o
36obj-$(CONFIG_DVB_S5H1420) += s5h1420.o 41obj-$(CONFIG_DVB_S5H1420) += s5h1420.o
37obj-$(CONFIG_DVB_LGDT330X) += lgdt330x.o 42obj-$(CONFIG_DVB_LGDT330X) += lgdt330x.o
43obj-$(CONFIG_DVB_LGDT3304) += lgdt3304.o
38obj-$(CONFIG_DVB_CX24123) += cx24123.o 44obj-$(CONFIG_DVB_CX24123) += cx24123.o
39obj-$(CONFIG_DVB_LNBP21) += lnbp21.o 45obj-$(CONFIG_DVB_LNBP21) += lnbp21.o
40obj-$(CONFIG_DVB_ISL6405) += isl6405.o 46obj-$(CONFIG_DVB_ISL6405) += isl6405.o
41obj-$(CONFIG_DVB_ISL6421) += isl6421.o 47obj-$(CONFIG_DVB_ISL6421) += isl6421.o
42obj-$(CONFIG_DVB_TDA10086) += tda10086.o 48obj-$(CONFIG_DVB_TDA10086) += tda10086.o
43obj-$(CONFIG_DVB_TDA826X) += tda826x.o 49obj-$(CONFIG_DVB_TDA826X) += tda826x.o
50obj-$(CONFIG_DVB_TDA8261) += tda8261.o
44obj-$(CONFIG_DVB_TUNER_DIB0070) += dib0070.o 51obj-$(CONFIG_DVB_TUNER_DIB0070) += dib0070.o
45obj-$(CONFIG_DVB_TUA6100) += tua6100.o 52obj-$(CONFIG_DVB_TUA6100) += tua6100.o
46obj-$(CONFIG_DVB_S5H1409) += s5h1409.o 53obj-$(CONFIG_DVB_S5H1409) += s5h1409.o
47obj-$(CONFIG_DVB_TUNER_ITD1000) += itd1000.o 54obj-$(CONFIG_DVB_TUNER_ITD1000) += itd1000.o
48obj-$(CONFIG_DVB_AU8522) += au8522.o 55obj-$(CONFIG_DVB_AU8522) += au8522.o
49obj-$(CONFIG_DVB_TDA10048) += tda10048.o 56obj-$(CONFIG_DVB_TDA10048) += tda10048.o
57obj-$(CONFIG_DVB_TUNER_CX24113) += cx24113.o
50obj-$(CONFIG_DVB_S5H1411) += s5h1411.o 58obj-$(CONFIG_DVB_S5H1411) += s5h1411.o
51obj-$(CONFIG_DVB_LGS8GL5) += lgs8gl5.o 59obj-$(CONFIG_DVB_LGS8GL5) += lgs8gl5.o
52obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o 60obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o
@@ -55,3 +63,5 @@ obj-$(CONFIG_DVB_CX24116) += cx24116.o
55obj-$(CONFIG_DVB_SI21XX) += si21xx.o 63obj-$(CONFIG_DVB_SI21XX) += si21xx.o
56obj-$(CONFIG_DVB_STV0288) += stv0288.o 64obj-$(CONFIG_DVB_STV0288) += stv0288.o
57obj-$(CONFIG_DVB_STB6000) += stb6000.o 65obj-$(CONFIG_DVB_STB6000) += stb6000.o
66obj-$(CONFIG_DVB_S921) += s921.o
67
diff --git a/drivers/media/dvb/frontends/af9013.c b/drivers/media/dvb/frontends/af9013.c
index 692b68a9e73b..b2b50fb4cfd3 100644
--- a/drivers/media/dvb/frontends/af9013.c
+++ b/drivers/media/dvb/frontends/af9013.c
@@ -223,12 +223,12 @@ static int af9013_set_coeff(struct af9013_state *state, fe_bandwidth_t bw)
223 int ret = 0; 223 int ret = 0;
224 u8 i = 0; 224 u8 i = 0;
225 u8 buf[24]; 225 u8 buf[24];
226 u32 ns_coeff1_2048nu; 226 u32 uninitialized_var(ns_coeff1_2048nu);
227 u32 ns_coeff1_8191nu; 227 u32 uninitialized_var(ns_coeff1_8191nu);
228 u32 ns_coeff1_8192nu; 228 u32 uninitialized_var(ns_coeff1_8192nu);
229 u32 ns_coeff1_8193nu; 229 u32 uninitialized_var(ns_coeff1_8193nu);
230 u32 ns_coeff2_2k; 230 u32 uninitialized_var(ns_coeff2_2k);
231 u32 ns_coeff2_8k; 231 u32 uninitialized_var(ns_coeff2_8k);
232 232
233 deb_info("%s: adc_clock:%d bw:%d\n", __func__, 233 deb_info("%s: adc_clock:%d bw:%d\n", __func__,
234 state->config.adc_clock, bw); 234 state->config.adc_clock, bw);
@@ -1009,7 +1009,7 @@ static int af9013_update_snr(struct dvb_frontend *fe)
1009 int ret; 1009 int ret;
1010 u8 buf[3], i, len; 1010 u8 buf[3], i, len;
1011 u32 quant = 0; 1011 u32 quant = 0;
1012 struct snr_table *snr_table; 1012 struct snr_table *uninitialized_var(snr_table);
1013 1013
1014 /* check if quantizer ready (for snr) */ 1014 /* check if quantizer ready (for snr) */
1015 ret = af9013_read_reg_bits(state, 0xd2e1, 3, 1, &buf[0]); 1015 ret = af9013_read_reg_bits(state, 0xd2e1, 3, 1, &buf[0]);
diff --git a/drivers/media/dvb/frontends/cx24113.c b/drivers/media/dvb/frontends/cx24113.c
new file mode 100644
index 000000000000..f6e7b0380a5a
--- /dev/null
+++ b/drivers/media/dvb/frontends/cx24113.c
@@ -0,0 +1,616 @@
1/*
2 * Driver for Conexant CX24113/CX24128 Tuner (Satellite)
3 *
4 * Copyright (C) 2007-8 Patrick Boettcher <pb@linuxtv.org>
5 *
6 * Developed for BBTI / Technisat
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 *
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/slab.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/init.h>
28
29#include "dvb_frontend.h"
30#include "cx24113.h"
31
32static int debug;
33
34#define info(args...) do { printk(KERN_INFO "CX24113: " args); } while (0)
35#define err(args...) do { printk(KERN_ERR "CX24113: " args); } while (0)
36
37#define dprintk(args...) \
38 do { \
39 if (debug) { \
40 printk(KERN_DEBUG "CX24113: %s: ", __func__); \
41 printk(args); \
42 } \
43 } while (0)
44
45struct cx24113_state {
46 struct i2c_adapter *i2c;
47 const struct cx24113_config *config;
48
49#define REV_CX24113 0x23
50 u8 rev;
51 u8 ver;
52
53 u8 icp_mode:1;
54
55#define ICP_LEVEL1 0
56#define ICP_LEVEL2 1
57#define ICP_LEVEL3 2
58#define ICP_LEVEL4 3
59 u8 icp_man:2;
60 u8 icp_auto_low:2;
61 u8 icp_auto_mlow:2;
62 u8 icp_auto_mhi:2;
63 u8 icp_auto_hi:2;
64 u8 icp_dig;
65
66#define LNA_MIN_GAIN 0
67#define LNA_MID_GAIN 1
68#define LNA_MAX_GAIN 2
69 u8 lna_gain:2;
70
71 u8 acp_on:1;
72
73 u8 vco_mode:2;
74 u8 vco_shift:1;
75#define VCOBANDSEL_6 0x80
76#define VCOBANDSEL_5 0x01
77#define VCOBANDSEL_4 0x02
78#define VCOBANDSEL_3 0x04
79#define VCOBANDSEL_2 0x08
80#define VCOBANDSEL_1 0x10
81 u8 vco_band;
82
83#define VCODIV4 4
84#define VCODIV2 2
85 u8 vcodiv;
86
87 u8 bs_delay:4;
88 u16 bs_freqcnt:13;
89 u16 bs_rdiv;
90 u8 prescaler_mode:1;
91
92 u8 rfvga_bias_ctrl;
93
94 s16 tuner_gain_thres;
95 u8 gain_level;
96
97 u32 frequency;
98
99 u8 refdiv;
100
101 u8 Fwindow_enabled;
102};
103
104static int cx24113_writereg(struct cx24113_state *state, int reg, int data)
105{
106 u8 buf[] = { reg, data };
107 struct i2c_msg msg = { .addr = state->config->i2c_addr,
108 .flags = 0, .buf = buf, .len = 2 };
109 int err = i2c_transfer(state->i2c, &msg, 1);
110 if (err != 1) {
111 printk(KERN_DEBUG "%s: writereg error(err == %i, reg == 0x%02x,"
112 " data == 0x%02x)\n", __func__, err, reg, data);
113 return err;
114 }
115
116 return 0;
117}
118
119static int cx24113_readreg(struct cx24113_state *state, u8 reg)
120{
121 int ret;
122 u8 b;
123 struct i2c_msg msg[] = {
124 { .addr = state->config->i2c_addr,
125 .flags = 0, .buf = &reg, .len = 1 },
126 { .addr = state->config->i2c_addr,
127 .flags = I2C_M_RD, .buf = &b, .len = 1 }
128 };
129
130 ret = i2c_transfer(state->i2c, msg, 2);
131
132 if (ret != 2) {
133 printk(KERN_DEBUG "%s: reg=0x%x (error=%d)\n",
134 __func__, reg, ret);
135 return ret;
136 }
137
138 return b;
139}
140
141static void cx24113_set_parameters(struct cx24113_state *state)
142{
143 u8 r;
144
145 r = cx24113_readreg(state, 0x10) & 0x82;
146 r |= state->icp_mode;
147 r |= state->icp_man << 4;
148 r |= state->icp_dig << 2;
149 r |= state->prescaler_mode << 5;
150 cx24113_writereg(state, 0x10, r);
151
152 r = (state->icp_auto_low << 0) | (state->icp_auto_mlow << 2)
153 | (state->icp_auto_mhi << 4) | (state->icp_auto_hi << 6);
154 cx24113_writereg(state, 0x11, r);
155
156 if (state->rev == REV_CX24113) {
157 r = cx24113_readreg(state, 0x20) & 0xec;
158 r |= state->lna_gain;
159 r |= state->rfvga_bias_ctrl << 4;
160 cx24113_writereg(state, 0x20, r);
161 }
162
163 r = cx24113_readreg(state, 0x12) & 0x03;
164 r |= state->acp_on << 2;
165 r |= state->bs_delay << 4;
166 cx24113_writereg(state, 0x12, r);
167
168 r = cx24113_readreg(state, 0x18) & 0x40;
169 r |= state->vco_shift;
170 if (state->vco_band == VCOBANDSEL_6)
171 r |= (1 << 7);
172 else
173 r |= (state->vco_band << 1);
174 cx24113_writereg(state, 0x18, r);
175
176 r = cx24113_readreg(state, 0x14) & 0x20;
177 r |= (state->vco_mode << 6) | ((state->bs_freqcnt >> 8) & 0x1f);
178 cx24113_writereg(state, 0x14, r);
179 cx24113_writereg(state, 0x15, (state->bs_freqcnt & 0xff));
180
181 cx24113_writereg(state, 0x16, (state->bs_rdiv >> 4) & 0xff);
182 r = (cx24113_readreg(state, 0x17) & 0x0f) |
183 ((state->bs_rdiv & 0x0f) << 4);
184 cx24113_writereg(state, 0x17, r);
185}
186
187#define VGA_0 0x00
188#define VGA_1 0x04
189#define VGA_2 0x02
190#define VGA_3 0x06
191#define VGA_4 0x01
192#define VGA_5 0x05
193#define VGA_6 0x03
194#define VGA_7 0x07
195
196#define RFVGA_0 0x00
197#define RFVGA_1 0x01
198#define RFVGA_2 0x02
199#define RFVGA_3 0x03
200
201static int cx24113_set_gain_settings(struct cx24113_state *state,
202 s16 power_estimation)
203{
204 u8 ampout = cx24113_readreg(state, 0x1d) & 0xf0,
205 vga = cx24113_readreg(state, 0x1f) & 0x3f,
206 rfvga = cx24113_readreg(state, 0x20) & 0xf3;
207 u8 gain_level = power_estimation >= state->tuner_gain_thres;
208
209 dprintk("power estimation: %d, thres: %d, gain_level: %d/%d\n",
210 power_estimation, state->tuner_gain_thres,
211 state->gain_level, gain_level);
212
213 if (gain_level == state->gain_level)
214 return 0; /* nothing to be done */
215
216 ampout |= 0xf;
217
218 if (gain_level) {
219 rfvga |= RFVGA_0 << 2;
220 vga |= (VGA_7 << 3) | VGA_7;
221 } else {
222 rfvga |= RFVGA_2 << 2;
223 vga |= (VGA_6 << 3) | VGA_2;
224 }
225 state->gain_level = gain_level;
226
227 cx24113_writereg(state, 0x1d, ampout);
228 cx24113_writereg(state, 0x1f, vga);
229 cx24113_writereg(state, 0x20, rfvga);
230
231 return 1; /* did something */
232}
233
234static int cx24113_set_Fref(struct cx24113_state *state, u8 high)
235{
236 u8 xtal = cx24113_readreg(state, 0x02);
237 if (state->rev == 0x43 && state->vcodiv == VCODIV4)
238 high = 1;
239
240 xtal &= ~0x2;
241 if (high)
242 xtal |= high << 1;
243 return cx24113_writereg(state, 0x02, xtal);
244}
245
246static int cx24113_enable(struct cx24113_state *state, u8 enable)
247{
248 u8 r21 = (cx24113_readreg(state, 0x21) & 0xc0) | enable;
249 if (state->rev == REV_CX24113)
250 r21 |= (1 << 1);
251 return cx24113_writereg(state, 0x21, r21);
252}
253
254static int cx24113_set_bandwidth(struct cx24113_state *state, u32 bandwidth_khz)
255{
256 u8 r;
257
258 if (bandwidth_khz <= 19000)
259 r = 0x03 << 6;
260 else if (bandwidth_khz <= 25000)
261 r = 0x02 << 6;
262 else
263 r = 0x01 << 6;
264
265 dprintk("bandwidth to be set: %d\n", bandwidth_khz);
266 bandwidth_khz *= 10;
267 bandwidth_khz -= 10000;
268 bandwidth_khz /= 1000;
269 bandwidth_khz += 5;
270 bandwidth_khz /= 10;
271
272 dprintk("bandwidth: %d %d\n", r >> 6, bandwidth_khz);
273
274 r |= bandwidth_khz & 0x3f;
275
276 return cx24113_writereg(state, 0x1e, r);
277}
278
279static int cx24113_set_clk_inversion(struct cx24113_state *state, u8 on)
280{
281 u8 r = (cx24113_readreg(state, 0x10) & 0x7f) | ((on & 0x1) << 7);
282 return cx24113_writereg(state, 0x10, r);
283}
284
285static int cx24113_get_status(struct dvb_frontend *fe, u32 *status)
286{
287 struct cx24113_state *state = fe->tuner_priv;
288 u8 r = (cx24113_readreg(state, 0x10) & 0x02) >> 1;
289 if (r)
290 *status |= TUNER_STATUS_LOCKED;
291 dprintk("PLL locked: %d\n", r);
292 return 0;
293}
294
295static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv)
296{
297 if (state->rev == 0x43 && state->vcodiv == VCODIV4)
298 refdiv = 2;
299 return state->refdiv = refdiv;
300}
301
302static void cx24113_calc_pll_nf(struct cx24113_state *state, u16 *n, s32 *f)
303{
304 s32 N;
305 s64 F;
306 u8 R, r;
307 u8 vcodiv;
308 u8 factor;
309 s32 freq_hz = state->frequency * 1000;
310
311 if (state->config->xtal_khz < 20000)
312 factor = 1;
313 else
314 factor = 2;
315
316 if (state->rev == REV_CX24113) {
317 if (state->frequency >= 1100000)
318 vcodiv = VCODIV2;
319 else
320 vcodiv = VCODIV4;
321 } else {
322 if (state->frequency >= 1165000)
323 vcodiv = VCODIV2;
324 else
325 vcodiv = VCODIV4;
326 }
327 state->vcodiv = vcodiv;
328
329 dprintk("calculating N/F for %dHz with vcodiv %d\n", freq_hz, vcodiv);
330 R = 0;
331 do {
332 R = cx24113_set_ref_div(state, R + 1);
333
334 /* calculate tuner PLL settings: */
335 N = (freq_hz / 100 * vcodiv) * R;
336 N /= (state->config->xtal_khz) * factor * 2;
337 N += 5; /* For round up. */
338 N /= 10;
339 N -= 32;
340 } while (N < 6 && R < 3);
341
342 if (N < 6) {
343 err("strange frequency: N < 6\n");
344 return;
345 }
346 F = freq_hz;
347 F *= (u64) (R * vcodiv * 262144);
348 dprintk("1 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
349 do_div(F, state->config->xtal_khz*1000 * factor * 2);
350 dprintk("2 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
351 F -= (N + 32) * 262144;
352
353 dprintk("3 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
354
355 if (state->Fwindow_enabled) {
356 if (F > (262144 / 2 - 1638))
357 F = 262144 / 2 - 1638;
358 if (F < (-262144 / 2 + 1638))
359 F = -262144 / 2 + 1638;
360 if ((F < 3277 && F > 0) || (F > -3277 && F < 0)) {
361 F = 0;
362 r = cx24113_readreg(state, 0x10);
363 cx24113_writereg(state, 0x10, r | (1 << 6));
364 }
365 }
366 dprintk("4 N: %d, F: %lld, R: %d\n", N, (long long)F, R);
367
368 *n = (u16) N;
369 *f = (s32) F;
370}
371
372
373static void cx24113_set_nfr(struct cx24113_state *state, u16 n, s32 f, u8 r)
374{
375 u8 reg;
376 cx24113_writereg(state, 0x19, (n >> 1) & 0xff);
377
378 reg = ((n & 0x1) << 7) | ((f >> 11) & 0x7f);
379 cx24113_writereg(state, 0x1a, reg);
380
381 cx24113_writereg(state, 0x1b, (f >> 3) & 0xff);
382
383 reg = cx24113_readreg(state, 0x1c) & 0x1f;
384 cx24113_writereg(state, 0x1c, reg | ((f & 0x7) << 5));
385
386 cx24113_set_Fref(state, r - 1);
387}
388
389static int cx24113_set_frequency(struct cx24113_state *state, u32 frequency)
390{
391 u8 r = 1; /* or 2 */
392 u16 n = 6;
393 s32 f = 0;
394
395 r = cx24113_readreg(state, 0x14);
396 cx24113_writereg(state, 0x14, r & 0x3f);
397
398 r = cx24113_readreg(state, 0x10);
399 cx24113_writereg(state, 0x10, r & 0xbf);
400
401 state->frequency = frequency;
402
403 dprintk("tuning to frequency: %d\n", frequency);
404
405 cx24113_calc_pll_nf(state, &n, &f);
406 cx24113_set_nfr(state, n, f, state->refdiv);
407
408 r = cx24113_readreg(state, 0x18) & 0xbf;
409 if (state->vcodiv != VCODIV2)
410 r |= 1 << 6;
411 cx24113_writereg(state, 0x18, r);
412
413 /* The need for this sleep is not clear. But helps in some cases */
414 msleep(5);
415
416 r = cx24113_readreg(state, 0x1c) & 0xef;
417 cx24113_writereg(state, 0x1c, r | (1 << 4));
418 return 0;
419}
420
421static int cx24113_init(struct dvb_frontend *fe)
422{
423 struct cx24113_state *state = fe->tuner_priv;
424 int ret;
425
426 state->tuner_gain_thres = -50;
427 state->gain_level = 255; /* to force a gain-setting initialization */
428 state->icp_mode = 0;
429
430 if (state->config->xtal_khz < 11000) {
431 state->icp_auto_hi = ICP_LEVEL4;
432 state->icp_auto_mhi = ICP_LEVEL4;
433 state->icp_auto_mlow = ICP_LEVEL3;
434 state->icp_auto_low = ICP_LEVEL3;
435 } else {
436 state->icp_auto_hi = ICP_LEVEL4;
437 state->icp_auto_mhi = ICP_LEVEL4;
438 state->icp_auto_mlow = ICP_LEVEL3;
439 state->icp_auto_low = ICP_LEVEL2;
440 }
441
442 state->icp_dig = ICP_LEVEL3;
443 state->icp_man = ICP_LEVEL1;
444 state->acp_on = 1;
445 state->vco_mode = 0;
446 state->vco_shift = 0;
447 state->vco_band = VCOBANDSEL_1;
448 state->bs_delay = 8;
449 state->bs_freqcnt = 0x0fff;
450 state->bs_rdiv = 0x0fff;
451 state->prescaler_mode = 0;
452 state->lna_gain = LNA_MAX_GAIN;
453 state->rfvga_bias_ctrl = 1;
454 state->Fwindow_enabled = 1;
455
456 cx24113_set_Fref(state, 0);
457 cx24113_enable(state, 0x3d);
458 cx24113_set_parameters(state);
459
460 cx24113_set_gain_settings(state, -30);
461
462 cx24113_set_bandwidth(state, 18025);
463 cx24113_set_clk_inversion(state, 1);
464
465 if (state->config->xtal_khz >= 40000)
466 ret = cx24113_writereg(state, 0x02,
467 (cx24113_readreg(state, 0x02) & 0xfb) | (1 << 2));
468 else
469 ret = cx24113_writereg(state, 0x02,
470 (cx24113_readreg(state, 0x02) & 0xfb) | (0 << 2));
471
472 return ret;
473}
474
475static int cx24113_set_params(struct dvb_frontend *fe,
476 struct dvb_frontend_parameters *p)
477{
478 struct cx24113_state *state = fe->tuner_priv;
479 /* for a ROLL-OFF factor of 0.35, 0.2: 600, 0.25: 625 */
480 u32 roll_off = 675;
481 u32 bw;
482
483 bw = ((p->u.qpsk.symbol_rate/100) * roll_off) / 1000;
484 bw += (10000000/100) + 5;
485 bw /= 10;
486 bw += 1000;
487 cx24113_set_bandwidth(state, bw);
488
489 cx24113_set_frequency(state, p->frequency);
490 msleep(5);
491 return cx24113_get_status(fe, &bw);
492}
493
494static s8 cx24113_agc_table[2][10] = {
495 {-54, -41, -35, -30, -25, -21, -16, -10, -6, -2},
496 {-39, -35, -30, -25, -19, -15, -11, -5, 1, 9},
497};
498
499void cx24113_agc_callback(struct dvb_frontend *fe)
500{
501 struct cx24113_state *state = fe->tuner_priv;
502 s16 s, i;
503 if (!fe->ops.read_signal_strength)
504 return;
505
506 do {
507 /* this only works with the current CX24123 implementation */
508 fe->ops.read_signal_strength(fe, (u16 *) &s);
509 s >>= 8;
510 dprintk("signal strength: %d\n", s);
511 for (i = 0; i < sizeof(cx24113_agc_table[0]); i++)
512 if (cx24113_agc_table[state->gain_level][i] > s)
513 break;
514 s = -25 - i*5;
515 } while (cx24113_set_gain_settings(state, s));
516}
517EXPORT_SYMBOL(cx24113_agc_callback);
518
519static int cx24113_get_frequency(struct dvb_frontend *fe, u32 *frequency)
520{
521 struct cx24113_state *state = fe->tuner_priv;
522 *frequency = state->frequency;
523 return 0;
524}
525
526static int cx24113_release(struct dvb_frontend *fe)
527{
528 struct cx24113_state *state = fe->tuner_priv;
529 dprintk("\n");
530 fe->tuner_priv = NULL;
531 kfree(state);
532 return 0;
533}
534
535static const struct dvb_tuner_ops cx24113_tuner_ops = {
536 .info = {
537 .name = "Conexant CX24113",
538 .frequency_min = 950000,
539 .frequency_max = 2150000,
540 .frequency_step = 125,
541 },
542
543 .release = cx24113_release,
544
545 .init = cx24113_init,
546 .sleep = NULL,
547
548 .set_params = cx24113_set_params,
549 .get_frequency = cx24113_get_frequency,
550 .get_bandwidth = NULL,
551 .get_status = cx24113_get_status,
552};
553
554struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe,
555 const struct cx24113_config *config, struct i2c_adapter *i2c)
556{
557 /* allocate memory for the internal state */
558 struct cx24113_state *state =
559 kzalloc(sizeof(struct cx24113_state), GFP_KERNEL);
560 int rc;
561 if (state == NULL) {
562 err("Unable to kmalloc\n");
563 goto error;
564 }
565
566 /* setup the state */
567 state->config = config;
568 state->i2c = i2c;
569
570 info("trying to detect myself\n");
571
572 /* making a dummy read, because of some expected troubles
573 * after power on */
574 cx24113_readreg(state, 0x00);
575
576 rc = cx24113_readreg(state, 0x00);
577 if (rc < 0) {
578 info("CX24113 not found.\n");
579 goto error;
580 }
581 state->rev = rc;
582
583 switch (rc) {
584 case 0x43:
585 info("detected CX24113 variant\n");
586 break;
587 case REV_CX24113:
588 info("sucessfully detected\n");
589 break;
590 default:
591 err("unsupported device id: %x\n", state->rev);
592 goto error;
593 }
594 state->ver = cx24113_readreg(state, 0x01);
595 info("version: %x\n", state->ver);
596
597 /* create dvb_frontend */
598 memcpy(&fe->ops.tuner_ops, &cx24113_tuner_ops,
599 sizeof(struct dvb_tuner_ops));
600 fe->tuner_priv = state;
601 return fe;
602
603error:
604 kfree(state);
605
606 return NULL;
607}
608EXPORT_SYMBOL(cx24113_attach);
609
610module_param(debug, int, 0644);
611MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
612
613MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
614MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24113/CX24128hardware");
615MODULE_LICENSE("GPL");
616
diff --git a/drivers/media/dvb/frontends/cx24113.h b/drivers/media/dvb/frontends/cx24113.h
index 5ab3dd11076b..5de0f7ffd8d2 100644
--- a/drivers/media/dvb/frontends/cx24113.h
+++ b/drivers/media/dvb/frontends/cx24113.h
@@ -16,7 +16,7 @@
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */ 20 */
21 21
22#ifndef CX24113_H 22#ifndef CX24113_H
@@ -30,9 +30,13 @@ struct cx24113_config {
30 u32 xtal_khz; 30 u32 xtal_khz;
31}; 31};
32 32
33/* TODO: #if defined(CONFIG_DVB_TUNER_CX24113) || \ 33#if defined(CONFIG_DVB_TUNER_CX24113) || \
34 * (defined(CONFIG_DVB_TUNER_CX24113_MODULE) && defined(MODULE)) */ 34 (defined(CONFIG_DVB_TUNER_CX24113_MODULE) && defined(MODULE))
35extern struct dvb_frontend *cx24113_attach(struct dvb_frontend *,
36 const struct cx24113_config *config, struct i2c_adapter *i2c);
35 37
38extern void cx24113_agc_callback(struct dvb_frontend *fe);
39#else
36static inline struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe, 40static inline struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe,
37 const struct cx24113_config *config, struct i2c_adapter *i2c) 41 const struct cx24113_config *config, struct i2c_adapter *i2c)
38{ 42{
@@ -44,5 +48,6 @@ static inline void cx24113_agc_callback(struct dvb_frontend *fe)
44{ 48{
45 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 49 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
46} 50}
51#endif
47 52
48#endif /* CX24113_H */ 53#endif /* CX24113_H */
diff --git a/drivers/media/dvb/frontends/cx24116.c b/drivers/media/dvb/frontends/cx24116.c
index b144b308a4dd..9b6c89e93f16 100644
--- a/drivers/media/dvb/frontends/cx24116.c
+++ b/drivers/media/dvb/frontends/cx24116.c
@@ -106,7 +106,7 @@ MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
106#define CX24116_HAS_SYNCLOCK (0x08) 106#define CX24116_HAS_SYNCLOCK (0x08)
107#define CX24116_HAS_UNKNOWN1 (0x10) 107#define CX24116_HAS_UNKNOWN1 (0x10)
108#define CX24116_HAS_UNKNOWN2 (0x20) 108#define CX24116_HAS_UNKNOWN2 (0x20)
109#define CX24116_STATUS_MASK (0x3f) 109#define CX24116_STATUS_MASK (0x0f)
110#define CX24116_SIGNAL_MASK (0xc0) 110#define CX24116_SIGNAL_MASK (0xc0)
111 111
112#define CX24116_DISEQC_TONEOFF (0) /* toneburst never sent */ 112#define CX24116_DISEQC_TONEOFF (0) /* toneburst never sent */
@@ -160,6 +160,7 @@ struct cx24116_tuning {
160 fe_spectral_inversion_t inversion; 160 fe_spectral_inversion_t inversion;
161 fe_code_rate_t fec; 161 fe_code_rate_t fec;
162 162
163 fe_delivery_system_t delsys;
163 fe_modulation_t modulation; 164 fe_modulation_t modulation;
164 fe_pilot_t pilot; 165 fe_pilot_t pilot;
165 fe_rolloff_t rolloff; 166 fe_rolloff_t rolloff;
@@ -411,14 +412,15 @@ struct cx24116_modfec {
411}; 412};
412 413
413static int cx24116_lookup_fecmod(struct cx24116_state *state, 414static int cx24116_lookup_fecmod(struct cx24116_state *state,
414 fe_modulation_t m, fe_code_rate_t f) 415 fe_delivery_system_t d, fe_modulation_t m, fe_code_rate_t f)
415{ 416{
416 int i, ret = -EOPNOTSUPP; 417 int i, ret = -EOPNOTSUPP;
417 418
418 dprintk("%s(0x%02x,0x%02x)\n", __func__, m, f); 419 dprintk("%s(0x%02x,0x%02x)\n", __func__, m, f);
419 420
420 for (i = 0; i < ARRAY_SIZE(CX24116_MODFEC_MODES); i++) { 421 for (i = 0; i < ARRAY_SIZE(CX24116_MODFEC_MODES); i++) {
421 if ((m == CX24116_MODFEC_MODES[i].modulation) && 422 if ((d == CX24116_MODFEC_MODES[i].delivery_system) &&
423 (m == CX24116_MODFEC_MODES[i].modulation) &&
422 (f == CX24116_MODFEC_MODES[i].fec)) { 424 (f == CX24116_MODFEC_MODES[i].fec)) {
423 ret = i; 425 ret = i;
424 break; 426 break;
@@ -429,13 +431,13 @@ static int cx24116_lookup_fecmod(struct cx24116_state *state,
429} 431}
430 432
431static int cx24116_set_fec(struct cx24116_state *state, 433static int cx24116_set_fec(struct cx24116_state *state,
432 fe_modulation_t mod, fe_code_rate_t fec) 434 fe_delivery_system_t delsys, fe_modulation_t mod, fe_code_rate_t fec)
433{ 435{
434 int ret = 0; 436 int ret = 0;
435 437
436 dprintk("%s(0x%02x,0x%02x)\n", __func__, mod, fec); 438 dprintk("%s(0x%02x,0x%02x)\n", __func__, mod, fec);
437 439
438 ret = cx24116_lookup_fecmod(state, mod, fec); 440 ret = cx24116_lookup_fecmod(state, delsys, mod, fec);
439 441
440 if (ret < 0) 442 if (ret < 0)
441 return ret; 443 return ret;
@@ -679,7 +681,8 @@ static int cx24116_read_status(struct dvb_frontend *fe, fe_status_t *status)
679{ 681{
680 struct cx24116_state *state = fe->demodulator_priv; 682 struct cx24116_state *state = fe->demodulator_priv;
681 683
682 int lock = cx24116_readreg(state, CX24116_REG_SSTATUS); 684 int lock = cx24116_readreg(state, CX24116_REG_SSTATUS) &
685 CX24116_STATUS_MASK;
683 686
684 dprintk("%s: status = 0x%02x\n", __func__, lock); 687 dprintk("%s: status = 0x%02x\n", __func__, lock);
685 688
@@ -1205,7 +1208,7 @@ static int cx24116_set_frontend(struct dvb_frontend *fe,
1205 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1208 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1206 struct cx24116_cmd cmd; 1209 struct cx24116_cmd cmd;
1207 fe_status_t tunerstat; 1210 fe_status_t tunerstat;
1208 int i, status, ret, retune; 1211 int i, status, ret, retune = 1;
1209 1212
1210 dprintk("%s()\n", __func__); 1213 dprintk("%s()\n", __func__);
1211 1214
@@ -1222,7 +1225,6 @@ static int cx24116_set_frontend(struct dvb_frontend *fe,
1222 1225
1223 /* Pilot doesn't exist in DVB-S, turn bit off */ 1226 /* Pilot doesn't exist in DVB-S, turn bit off */
1224 state->dnxt.pilot_val = CX24116_PILOT_OFF; 1227 state->dnxt.pilot_val = CX24116_PILOT_OFF;
1225 retune = 1;
1226 1228
1227 /* DVB-S only supports 0.35 */ 1229 /* DVB-S only supports 0.35 */
1228 if (c->rolloff != ROLLOFF_35) { 1230 if (c->rolloff != ROLLOFF_35) {
@@ -1250,7 +1252,7 @@ static int cx24116_set_frontend(struct dvb_frontend *fe,
1250 case PILOT_AUTO: /* Not supported but emulated */ 1252 case PILOT_AUTO: /* Not supported but emulated */
1251 state->dnxt.pilot_val = (c->modulation == QPSK) 1253 state->dnxt.pilot_val = (c->modulation == QPSK)
1252 ? CX24116_PILOT_OFF : CX24116_PILOT_ON; 1254 ? CX24116_PILOT_OFF : CX24116_PILOT_ON;
1253 retune = 2; 1255 retune++;
1254 break; 1256 break;
1255 case PILOT_OFF: 1257 case PILOT_OFF:
1256 state->dnxt.pilot_val = CX24116_PILOT_OFF; 1258 state->dnxt.pilot_val = CX24116_PILOT_OFF;
@@ -1287,6 +1289,7 @@ static int cx24116_set_frontend(struct dvb_frontend *fe,
1287 __func__, c->delivery_system); 1289 __func__, c->delivery_system);
1288 return -EOPNOTSUPP; 1290 return -EOPNOTSUPP;
1289 } 1291 }
1292 state->dnxt.delsys = c->delivery_system;
1290 state->dnxt.modulation = c->modulation; 1293 state->dnxt.modulation = c->modulation;
1291 state->dnxt.frequency = c->frequency; 1294 state->dnxt.frequency = c->frequency;
1292 state->dnxt.pilot = c->pilot; 1295 state->dnxt.pilot = c->pilot;
@@ -1297,7 +1300,7 @@ static int cx24116_set_frontend(struct dvb_frontend *fe,
1297 return ret; 1300 return ret;
1298 1301
1299 /* FEC_NONE/AUTO for DVB-S2 is not supported and detected here */ 1302 /* FEC_NONE/AUTO for DVB-S2 is not supported and detected here */
1300 ret = cx24116_set_fec(state, c->modulation, c->fec_inner); 1303 ret = cx24116_set_fec(state, c->delivery_system, c->modulation, c->fec_inner);
1301 if (ret != 0) 1304 if (ret != 0)
1302 return ret; 1305 return ret;
1303 1306
@@ -1308,6 +1311,7 @@ static int cx24116_set_frontend(struct dvb_frontend *fe,
1308 /* discard the 'current' tuning parameters and prepare to tune */ 1311 /* discard the 'current' tuning parameters and prepare to tune */
1309 cx24116_clone_params(fe); 1312 cx24116_clone_params(fe);
1310 1313
1314 dprintk("%s: delsys = %d\n", __func__, state->dcur.delsys);
1311 dprintk("%s: modulation = %d\n", __func__, state->dcur.modulation); 1315 dprintk("%s: modulation = %d\n", __func__, state->dcur.modulation);
1312 dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency); 1316 dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency);
1313 dprintk("%s: pilot = %d (val = 0x%02x)\n", __func__, 1317 dprintk("%s: pilot = %d (val = 0x%02x)\n", __func__,
@@ -1427,6 +1431,23 @@ tuned: /* Set/Reset B/W */
1427 return ret; 1431 return ret;
1428} 1432}
1429 1433
1434static int cx24116_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *params,
1435 unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
1436{
1437 *delay = HZ / 5;
1438 if (params) {
1439 int ret = cx24116_set_frontend(fe, params);
1440 if (ret)
1441 return ret;
1442 }
1443 return cx24116_read_status(fe, status);
1444}
1445
1446static int cx24116_get_algo(struct dvb_frontend *fe)
1447{
1448 return DVBFE_ALGO_HW;
1449}
1450
1430static struct dvb_frontend_ops cx24116_ops = { 1451static struct dvb_frontend_ops cx24116_ops = {
1431 1452
1432 .info = { 1453 .info = {
@@ -1458,6 +1479,8 @@ static struct dvb_frontend_ops cx24116_ops = {
1458 .set_voltage = cx24116_set_voltage, 1479 .set_voltage = cx24116_set_voltage,
1459 .diseqc_send_master_cmd = cx24116_send_diseqc_msg, 1480 .diseqc_send_master_cmd = cx24116_send_diseqc_msg,
1460 .diseqc_send_burst = cx24116_diseqc_send_burst, 1481 .diseqc_send_burst = cx24116_diseqc_send_burst,
1482 .get_frontend_algo = cx24116_get_algo,
1483 .tune = cx24116_tune,
1461 1484
1462 .set_property = cx24116_set_property, 1485 .set_property = cx24116_set_property,
1463 .get_property = cx24116_get_property, 1486 .get_property = cx24116_get_property,
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
index 3e8126857127..aab8112e2db2 100644
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ b/drivers/media/dvb/frontends/dib7000p.h
@@ -66,7 +66,8 @@ struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *fe,
66 return NULL; 66 return NULL;
67} 67}
68 68
69extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, 69static inline
70int dib7000p_i2c_enumeration(struct i2c_adapter *i2c,
70 int no_of_demods, u8 default_addr, 71 int no_of_demods, u8 default_addr,
71 struct dib7000p_config cfg[]) 72 struct dib7000p_config cfg[])
72{ 73{
@@ -74,13 +75,15 @@ extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c,
74 return -ENODEV; 75 return -ENODEV;
75} 76}
76 77
77extern int dib7000p_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val) 78static inline
79int dib7000p_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
78{ 80{
79 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 81 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
80 return -ENODEV; 82 return -ENODEV;
81} 83}
82 84
83extern int dib7000p_set_wbd_ref(struct dvb_frontend *fe, u16 value) 85static inline
86int dib7000p_set_wbd_ref(struct dvb_frontend *fe, u16 value)
84{ 87{
85 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 88 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
86 return -ENODEV; 89 return -ENODEV;
diff --git a/drivers/media/dvb/frontends/drx397xD.c b/drivers/media/dvb/frontends/drx397xD.c
index b9ca5c8d2dd9..ec4e08dbc699 100644
--- a/drivers/media/dvb/frontends/drx397xD.c
+++ b/drivers/media/dvb/frontends/drx397xD.c
@@ -39,7 +39,7 @@ static const char mod_name[] = "drx397xD";
39#define F_SET_0D4h 2 39#define F_SET_0D4h 2
40 40
41enum fw_ix { 41enum fw_ix {
42#define _FW_ENTRY(a, b) b 42#define _FW_ENTRY(a, b, c) b
43#include "drx397xD_fw.h" 43#include "drx397xD_fw.h"
44}; 44};
45 45
@@ -72,11 +72,11 @@ static struct {
72 int refcnt; 72 int refcnt;
73 const u8 *data[ARRAY_SIZE(blob_name)]; 73 const u8 *data[ARRAY_SIZE(blob_name)];
74} fw[] = { 74} fw[] = {
75#define _FW_ENTRY(a, b) { \ 75#define _FW_ENTRY(a, b, c) { \
76 .name = a, \ 76 .name = a, \
77 .file = 0, \ 77 .file = 0, \
78 .lock = RW_LOCK_UNLOCKED, \ 78 .lock = __RW_LOCK_UNLOCKED(fw[c].lock), \
79 .refcnt = 0, \ 79 .refcnt = 0, \
80 .data = { } } 80 .data = { } }
81#include "drx397xD_fw.h" 81#include "drx397xD_fw.h"
82}; 82};
diff --git a/drivers/media/dvb/frontends/drx397xD_fw.h b/drivers/media/dvb/frontends/drx397xD_fw.h
index 01de02a81cd4..c8b44c1e807f 100644
--- a/drivers/media/dvb/frontends/drx397xD_fw.h
+++ b/drivers/media/dvb/frontends/drx397xD_fw.h
@@ -18,8 +18,8 @@
18 */ 18 */
19 19
20#ifdef _FW_ENTRY 20#ifdef _FW_ENTRY
21 _FW_ENTRY("drx397xD.A2.fw", DRXD_FW_A2 = 0 ), 21 _FW_ENTRY("drx397xD.A2.fw", DRXD_FW_A2 = 0, DRXD_FW_A2 ),
22 _FW_ENTRY("drx397xD.B1.fw", DRXD_FW_B1 ), 22 _FW_ENTRY("drx397xD.B1.fw", DRXD_FW_B1, DRXD_FW_B1 ),
23#undef _FW_ENTRY 23#undef _FW_ENTRY
24#endif /* _FW_ENTRY */ 24#endif /* _FW_ENTRY */
25 25
diff --git a/drivers/media/dvb/frontends/dvb-pll.c b/drivers/media/dvb/frontends/dvb-pll.c
index ea058153ebfa..9f6349964cda 100644
--- a/drivers/media/dvb/frontends/dvb-pll.c
+++ b/drivers/media/dvb/frontends/dvb-pll.c
@@ -311,7 +311,7 @@ static struct dvb_pll_desc dvb_pll_philips_sd1878_tda8261 = {
311 .count = 4, 311 .count = 4,
312 .entries = { 312 .entries = {
313 { 1250000, 500, 0xc4, 0x00}, 313 { 1250000, 500, 0xc4, 0x00},
314 { 1550000, 500, 0xc4, 0x40}, 314 { 1450000, 500, 0xc4, 0x40},
315 { 2050000, 500, 0xc4, 0x80}, 315 { 2050000, 500, 0xc4, 0x80},
316 { 2150000, 500, 0xc4, 0xc0}, 316 { 2150000, 500, 0xc4, 0xc0},
317 }, 317 },
diff --git a/drivers/media/dvb/frontends/lgdt3304.c b/drivers/media/dvb/frontends/lgdt3304.c
new file mode 100644
index 000000000000..469ace5692c6
--- /dev/null
+++ b/drivers/media/dvb/frontends/lgdt3304.c
@@ -0,0 +1,378 @@
1/*
2 * Driver for LG ATSC lgdt3304 driver
3 *
4 * Copyright (C) 2008 Markus Rechberger <mrechberger@sundtek.de>
5 *
6 */
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/delay.h>
11#include "dvb_frontend.h"
12#include "lgdt3304.h"
13
14static unsigned int debug = 0;
15module_param(debug, int, 0644);
16MODULE_PARM_DESC(debug,"lgdt3304 debugging (default off)");
17
18#define dprintk(fmt, args...) if (debug) do {\
19 printk("lgdt3304 debug: " fmt, ##args); } while (0)
20
21struct lgdt3304_state
22{
23 struct dvb_frontend frontend;
24 fe_modulation_t current_modulation;
25 __u32 snr;
26 __u32 current_frequency;
27 __u8 addr;
28 struct i2c_adapter *i2c;
29};
30
31static int i2c_write_demod_bytes (struct dvb_frontend *fe, __u8 *buf, int len)
32{
33 struct lgdt3304_state *state = fe->demodulator_priv;
34 struct i2c_msg i2cmsgs = {
35 .addr = state->addr,
36 .flags = 0,
37 .len = 3,
38 .buf = buf
39 };
40 int i;
41 int err;
42
43 for (i=0; i<len-1; i+=3){
44 if((err = i2c_transfer(state->i2c, &i2cmsgs, 1))<0) {
45 printk("%s i2c_transfer error %d\n", __FUNCTION__, err);
46 if (err < 0)
47 return err;
48 else
49 return -EREMOTEIO;
50 }
51 i2cmsgs.buf += 3;
52 }
53 return 0;
54}
55
56static int lgdt3304_i2c_read_reg(struct dvb_frontend *fe, unsigned int reg)
57{
58 struct lgdt3304_state *state = fe->demodulator_priv;
59 struct i2c_msg i2cmsgs[2];
60 int ret;
61 __u8 buf;
62
63 __u8 regbuf[2] = { reg>>8, reg&0xff };
64
65 i2cmsgs[0].addr = state->addr;
66 i2cmsgs[0].flags = 0;
67 i2cmsgs[0].len = 2;
68 i2cmsgs[0].buf = regbuf;
69
70 i2cmsgs[1].addr = state->addr;
71 i2cmsgs[1].flags = I2C_M_RD;
72 i2cmsgs[1].len = 1;
73 i2cmsgs[1].buf = &buf;
74
75 if((ret = i2c_transfer(state->i2c, i2cmsgs, 2))<0) {
76 printk("%s i2c_transfer error %d\n", __FUNCTION__, ret);
77 return ret;
78 }
79
80 return buf;
81}
82
83static int lgdt3304_i2c_write_reg(struct dvb_frontend *fe, int reg, int val)
84{
85 struct lgdt3304_state *state = fe->demodulator_priv;
86 char buffer[3] = { reg>>8, reg&0xff, val };
87 int ret;
88
89 struct i2c_msg i2cmsgs = {
90 .addr = state->addr,
91 .flags = 0,
92 .len = 3,
93 .buf=buffer
94 };
95 ret = i2c_transfer(state->i2c, &i2cmsgs, 1);
96 if (ret != 1) {
97 printk("%s i2c_transfer error %d\n", __FUNCTION__, ret);
98 return ret;
99 }
100
101 return 0;
102}
103
104
105static int lgdt3304_soft_Reset(struct dvb_frontend *fe)
106{
107 lgdt3304_i2c_write_reg(fe, 0x0002, 0x9a);
108 lgdt3304_i2c_write_reg(fe, 0x0002, 0x9b);
109 mdelay(200);
110 return 0;
111}
112
113static int lgdt3304_set_parameters(struct dvb_frontend *fe, struct dvb_frontend_parameters *param) {
114 int err = 0;
115
116 static __u8 lgdt3304_vsb8_data[] = {
117 /* 16bit , 8bit */
118 /* regs , val */
119 0x00, 0x00, 0x02,
120 0x00, 0x00, 0x13,
121 0x00, 0x0d, 0x02,
122 0x00, 0x0e, 0x02,
123 0x00, 0x12, 0x32,
124 0x00, 0x13, 0xc4,
125 0x01, 0x12, 0x17,
126 0x01, 0x13, 0x15,
127 0x01, 0x14, 0x18,
128 0x01, 0x15, 0xff,
129 0x01, 0x16, 0x2c,
130 0x02, 0x14, 0x67,
131 0x02, 0x24, 0x8d,
132 0x04, 0x27, 0x12,
133 0x04, 0x28, 0x4f,
134 0x03, 0x08, 0x80,
135 0x03, 0x09, 0x00,
136 0x03, 0x0d, 0x00,
137 0x03, 0x0e, 0x1c,
138 0x03, 0x14, 0xe1,
139 0x05, 0x0e, 0x5b,
140 };
141
142 /* not yet tested .. */
143 static __u8 lgdt3304_qam64_data[] = {
144 /* 16bit , 8bit */
145 /* regs , val */
146 0x00, 0x00, 0x18,
147 0x00, 0x0d, 0x02,
148 //0x00, 0x0e, 0x02,
149 0x00, 0x12, 0x2a,
150 0x00, 0x13, 0x00,
151 0x03, 0x14, 0xe3,
152 0x03, 0x0e, 0x1c,
153 0x03, 0x08, 0x66,
154 0x03, 0x09, 0x66,
155 0x03, 0x0a, 0x08,
156 0x03, 0x0b, 0x9b,
157 0x05, 0x0e, 0x5b,
158 };
159
160
161 /* tested with KWorld a340 */
162 static __u8 lgdt3304_qam256_data[] = {
163 /* 16bit , 8bit */
164 /* regs , val */
165 0x00, 0x00, 0x01, //0x19,
166 0x00, 0x12, 0x2a,
167 0x00, 0x13, 0x80,
168 0x00, 0x0d, 0x02,
169 0x03, 0x14, 0xe3,
170
171 0x03, 0x0e, 0x1c,
172 0x03, 0x08, 0x66,
173 0x03, 0x09, 0x66,
174 0x03, 0x0a, 0x08,
175 0x03, 0x0b, 0x9b,
176
177 0x03, 0x0d, 0x14,
178 //0x05, 0x0e, 0x5b,
179 0x01, 0x06, 0x4a,
180 0x01, 0x07, 0x3d,
181 0x01, 0x08, 0x70,
182 0x01, 0x09, 0xa3,
183
184 0x05, 0x04, 0xfd,
185
186 0x00, 0x0d, 0x82,
187
188 0x05, 0x0e, 0x5b,
189
190 0x05, 0x0e, 0x5b,
191
192 0x00, 0x02, 0x9a,
193
194 0x00, 0x02, 0x9b,
195
196 0x00, 0x00, 0x01,
197 0x00, 0x12, 0x2a,
198 0x00, 0x13, 0x80,
199 0x00, 0x0d, 0x02,
200 0x03, 0x14, 0xe3,
201
202 0x03, 0x0e, 0x1c,
203 0x03, 0x08, 0x66,
204 0x03, 0x09, 0x66,
205 0x03, 0x0a, 0x08,
206 0x03, 0x0b, 0x9b,
207
208 0x03, 0x0d, 0x14,
209 0x01, 0x06, 0x4a,
210 0x01, 0x07, 0x3d,
211 0x01, 0x08, 0x70,
212 0x01, 0x09, 0xa3,
213
214 0x05, 0x04, 0xfd,
215
216 0x00, 0x0d, 0x82,
217
218 0x05, 0x0e, 0x5b,
219 };
220
221 struct lgdt3304_state *state = fe->demodulator_priv;
222 if (state->current_modulation != param->u.vsb.modulation) {
223 switch(param->u.vsb.modulation) {
224 case VSB_8:
225 err = i2c_write_demod_bytes(fe, lgdt3304_vsb8_data,
226 sizeof(lgdt3304_vsb8_data));
227 break;
228 case QAM_64:
229 err = i2c_write_demod_bytes(fe, lgdt3304_qam64_data,
230 sizeof(lgdt3304_qam64_data));
231 break;
232 case QAM_256:
233 err = i2c_write_demod_bytes(fe, lgdt3304_qam256_data,
234 sizeof(lgdt3304_qam256_data));
235 break;
236 default:
237 break;
238 }
239
240 if (err) {
241 printk("%s error setting modulation\n", __FUNCTION__);
242 } else {
243 state->current_modulation = param->u.vsb.modulation;
244 }
245 }
246 state->current_frequency = param->frequency;
247
248 lgdt3304_soft_Reset(fe);
249
250
251 if (fe->ops.tuner_ops.set_params)
252 fe->ops.tuner_ops.set_params(fe, param);
253
254 return 0;
255}
256
257static int lgdt3304_init(struct dvb_frontend *fe) {
258 return 0;
259}
260
261static int lgdt3304_sleep(struct dvb_frontend *fe) {
262 return 0;
263}
264
265
266static int lgdt3304_read_status(struct dvb_frontend *fe, fe_status_t *status)
267{
268 struct lgdt3304_state *state = fe->demodulator_priv;
269 int r011d;
270 int qam_lck;
271
272 *status = 0;
273 dprintk("lgdt read status\n");
274
275 r011d = lgdt3304_i2c_read_reg(fe, 0x011d);
276
277 dprintk("%02x\n", r011d);
278
279 switch(state->current_modulation) {
280 case VSB_8:
281 if (r011d & 0x80) {
282 dprintk("VSB Locked\n");
283 *status |= FE_HAS_CARRIER;
284 *status |= FE_HAS_LOCK;
285 *status |= FE_HAS_SYNC;
286 *status |= FE_HAS_SIGNAL;
287 }
288 break;
289 case QAM_64:
290 case QAM_256:
291 qam_lck = r011d & 0x7;
292 switch(qam_lck) {
293 case 0x0: dprintk("Unlock\n");
294 break;
295 case 0x4: dprintk("1st Lock in acquisition state\n");
296 break;
297 case 0x6: dprintk("2nd Lock in acquisition state\n");
298 break;
299 case 0x7: dprintk("Final Lock in good reception state\n");
300 *status |= FE_HAS_CARRIER;
301 *status |= FE_HAS_LOCK;
302 *status |= FE_HAS_SYNC;
303 *status |= FE_HAS_SIGNAL;
304 break;
305 }
306 break;
307 default:
308 printk("%s unhandled modulation\n", __FUNCTION__);
309 }
310
311
312 return 0;
313}
314
315static int lgdt3304_read_ber(struct dvb_frontend *fe, __u32 *ber)
316{
317 dprintk("read ber\n");
318 return 0;
319}
320
321static int lgdt3304_read_snr(struct dvb_frontend *fe, __u16 *snr)
322{
323 dprintk("read snr\n");
324 return 0;
325}
326
327static int lgdt3304_read_ucblocks(struct dvb_frontend *fe, __u32 *ucblocks)
328{
329 dprintk("read ucblocks\n");
330 return 0;
331}
332
333static void lgdt3304_release(struct dvb_frontend *fe)
334{
335 struct lgdt3304_state *state = (struct lgdt3304_state *)fe->demodulator_priv;
336 kfree(state);
337}
338
339static struct dvb_frontend_ops demod_lgdt3304={
340 .info = {
341 .name = "LG 3304",
342 .type = FE_ATSC,
343 .frequency_min = 54000000,
344 .frequency_max = 858000000,
345 .frequency_stepsize = 62500,
346 .symbol_rate_min = 5056941,
347 .symbol_rate_max = 10762000,
348 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
349 },
350 .init = lgdt3304_init,
351 .sleep = lgdt3304_sleep,
352 .set_frontend = lgdt3304_set_parameters,
353 .read_snr = lgdt3304_read_snr,
354 .read_ber = lgdt3304_read_ber,
355 .read_status = lgdt3304_read_status,
356 .read_ucblocks = lgdt3304_read_ucblocks,
357 .release = lgdt3304_release,
358};
359
360struct dvb_frontend* lgdt3304_attach(const struct lgdt3304_config *config,
361 struct i2c_adapter *i2c)
362{
363
364 struct lgdt3304_state *state;
365 state = kzalloc(sizeof(struct lgdt3304_state), GFP_KERNEL);
366 memset(state, 0x0, sizeof(struct lgdt3304_state));
367 state->addr = config->i2c_address;
368 state->i2c = i2c;
369
370 memcpy(&state->frontend.ops, &demod_lgdt3304, sizeof(struct dvb_frontend_ops));
371 state->frontend.demodulator_priv = state;
372 return &state->frontend;
373}
374
375EXPORT_SYMBOL_GPL(lgdt3304_attach);
376MODULE_AUTHOR("Markus Rechberger <mrechberger@empiatech.com>");
377MODULE_DESCRIPTION("LGE LGDT3304 DVB-T demodulator driver");
378MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/lgdt3304.h b/drivers/media/dvb/frontends/lgdt3304.h
new file mode 100644
index 000000000000..fc409fe59acb
--- /dev/null
+++ b/drivers/media/dvb/frontends/lgdt3304.h
@@ -0,0 +1,45 @@
1/*
2 * Driver for DVB-T lgdt3304 demodulator
3 *
4 * Copyright (C) 2008 Markus Rechberger <mrechberger@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
20 */
21
22#ifndef LGDT3304_H
23#define LGDT3304_H
24
25#include <linux/dvb/frontend.h>
26
27struct lgdt3304_config
28{
29 /* demodulator's I2C address */
30 u8 i2c_address;
31};
32
33#if defined(CONFIG_DVB_LGDT3304) || (defined(CONFIG_DVB_LGDT3304_MODULE) && defined(MODULE))
34extern struct dvb_frontend* lgdt3304_attach(const struct lgdt3304_config *config,
35 struct i2c_adapter *i2c);
36#else
37static inline struct dvb_frontend* lgdt3304_attach(const struct lgdt3304_config *config,
38 struct i2c_adapter *i2c)
39{
40 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
41 return NULL;
42}
43#endif /* CONFIG_DVB_LGDT */
44
45#endif /* LGDT3304_H */
diff --git a/drivers/media/dvb/frontends/s5h1411.c b/drivers/media/dvb/frontends/s5h1411.c
index 40644aacffcb..66e2dd6d6fe4 100644
--- a/drivers/media/dvb/frontends/s5h1411.c
+++ b/drivers/media/dvb/frontends/s5h1411.c
@@ -874,6 +874,9 @@ struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config,
874 /* Note: Leaving the I2C gate open here. */ 874 /* Note: Leaving the I2C gate open here. */
875 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); 875 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
876 876
877 /* Put the device into low-power mode until first use */
878 s5h1411_set_powerstate(&state->frontend, 1);
879
877 return &state->frontend; 880 return &state->frontend;
878 881
879error: 882error:
diff --git a/drivers/media/dvb/frontends/s921_core.c b/drivers/media/dvb/frontends/s921_core.c
new file mode 100644
index 000000000000..974b52be9aea
--- /dev/null
+++ b/drivers/media/dvb/frontends/s921_core.c
@@ -0,0 +1,216 @@
1/*
2 * Driver for Sharp s921 driver
3 *
4 * Copyright (C) 2008 Markus Rechberger <mrechberger@sundtek.de>
5 *
6 */
7
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/delay.h>
12#include "s921_core.h"
13
14static int s921_isdb_init(struct s921_isdb_t *dev);
15static int s921_isdb_set_parameters(struct s921_isdb_t *dev, struct s921_isdb_t_transmission_mode_params *params);
16static int s921_isdb_tune(struct s921_isdb_t *dev, struct s921_isdb_t_tune_params *params);
17static int s921_isdb_get_status(struct s921_isdb_t *dev, void *data);
18
19static u8 init_table[]={ 0x01, 0x40, 0x02, 0x00, 0x03, 0x40, 0x04, 0x01,
20 0x05, 0x00, 0x06, 0x00, 0x07, 0x00, 0x08, 0x00,
21 0x09, 0x00, 0x0a, 0x00, 0x0b, 0x5a, 0x0c, 0x00,
22 0x0d, 0x00, 0x0f, 0x00, 0x13, 0x1b, 0x14, 0x80,
23 0x15, 0x40, 0x17, 0x70, 0x18, 0x01, 0x19, 0x12,
24 0x1a, 0x01, 0x1b, 0x12, 0x1c, 0xa0, 0x1d, 0x00,
25 0x1e, 0x0a, 0x1f, 0x08, 0x20, 0x40, 0x21, 0xff,
26 0x22, 0x4c, 0x23, 0x4e, 0x24, 0x4c, 0x25, 0x00,
27 0x26, 0x00, 0x27, 0xf4, 0x28, 0x60, 0x29, 0x88,
28 0x2a, 0x40, 0x2b, 0x40, 0x2c, 0xff, 0x2d, 0x00,
29 0x2e, 0xff, 0x2f, 0x00, 0x30, 0x20, 0x31, 0x06,
30 0x32, 0x0c, 0x34, 0x0f, 0x37, 0xfe, 0x38, 0x00,
31 0x39, 0x63, 0x3a, 0x10, 0x3b, 0x10, 0x47, 0x00,
32 0x49, 0xe5, 0x4b, 0x00, 0x50, 0xc0, 0x52, 0x20,
33 0x54, 0x5a, 0x55, 0x5b, 0x56, 0x40, 0x57, 0x70,
34 0x5c, 0x50, 0x5d, 0x00, 0x62, 0x17, 0x63, 0x2f,
35 0x64, 0x6f, 0x68, 0x00, 0x69, 0x89, 0x6a, 0x00,
36 0x6b, 0x00, 0x6c, 0x00, 0x6d, 0x00, 0x6e, 0x00,
37 0x70, 0x00, 0x71, 0x00, 0x75, 0x00, 0x76, 0x30,
38 0x77, 0x01, 0xaf, 0x00, 0xb0, 0xa0, 0xb2, 0x3d,
39 0xb3, 0x25, 0xb4, 0x8b, 0xb5, 0x4b, 0xb6, 0x3f,
40 0xb7, 0xff, 0xb8, 0xff, 0xb9, 0xfc, 0xba, 0x00,
41 0xbb, 0x00, 0xbc, 0x00, 0xd0, 0x30, 0xe4, 0x84,
42 0xf0, 0x48, 0xf1, 0x19, 0xf2, 0x5a, 0xf3, 0x8e,
43 0xf4, 0x2d, 0xf5, 0x07, 0xf6, 0x5a, 0xf7, 0xba,
44 0xf8, 0xd7 };
45
46static u8 c_table[]={ 0x58, 0x8a, 0x7b, 0x59, 0x8c, 0x7b, 0x5a, 0x8e, 0x5b,
47 0x5b, 0x90, 0x5b, 0x5c, 0x92, 0x5b, 0x5d, 0x94, 0x5b,
48 0x5e, 0x96, 0x5b, 0x5f, 0x98, 0x3b, 0x60, 0x9a, 0x3b,
49 0x61, 0x9c, 0x3b, 0x62, 0x9e, 0x3b, 0x63, 0xa0, 0x3b,
50 0x64, 0xa2, 0x1b, 0x65, 0xa4, 0x1b, 0x66, 0xa6, 0x1b,
51 0x67, 0xa8, 0x1b, 0x68, 0xaa, 0x1b, 0x69, 0xac, 0x1b,
52 0x6a, 0xae, 0x1b, 0x6b, 0xb0, 0x1b, 0x6c, 0xb2, 0x1b,
53 0x6d, 0xb4, 0xfb, 0x6e, 0xb6, 0xfb, 0x6f, 0xb8, 0xfb,
54 0x70, 0xba, 0xfb, 0x71, 0xbc, 0xdb, 0x72, 0xbe, 0xdb,
55 0x73, 0xc0, 0xdb, 0x74, 0xc2, 0xdb, 0x75, 0xc4, 0xdb,
56 0x76, 0xc6, 0xdb, 0x77, 0xc8, 0xbb, 0x78, 0xca, 0xbb,
57 0x79, 0xcc, 0xbb, 0x7a, 0xce, 0xbb, 0x7b, 0xd0, 0xbb,
58 0x7c, 0xd2, 0xbb, 0x7d, 0xd4, 0xbb, 0x7e, 0xd6, 0xbb,
59 0x7f, 0xd8, 0xbb, 0x80, 0xda, 0x9b, 0x81, 0xdc, 0x9b,
60 0x82, 0xde, 0x9b, 0x83, 0xe0, 0x9b, 0x84, 0xe2, 0x9b,
61 0x85, 0xe4, 0x9b, 0x86, 0xe6, 0x9b, 0x87, 0xe8, 0x9b,
62 0x88, 0xea, 0x9b, 0x89, 0xec, 0x9b };
63
64int s921_isdb_cmd(struct s921_isdb_t *dev, u32 cmd, void *data) {
65 switch(cmd) {
66 case ISDB_T_CMD_INIT:
67 s921_isdb_init(dev);
68 break;
69 case ISDB_T_CMD_SET_PARAM:
70 s921_isdb_set_parameters(dev, data);
71 break;
72 case ISDB_T_CMD_TUNE:
73 s921_isdb_tune(dev, data);
74 break;
75 case ISDB_T_CMD_GET_STATUS:
76 s921_isdb_get_status(dev, data);
77 break;
78 default:
79 printk("unhandled command\n");
80 return -EINVAL;
81 }
82 return 0;
83}
84
85static int s921_isdb_init(struct s921_isdb_t *dev) {
86 unsigned int i;
87 unsigned int ret;
88 printk("isdb_init\n");
89 for (i = 0; i < sizeof(init_table); i+=2) {
90 ret = dev->i2c_write(dev->priv_dev, init_table[i], init_table[i+1]);
91 if (ret != 0) {
92 printk("i2c write failed\n");
93 return ret;
94 }
95 }
96 return 0;
97}
98
99static int s921_isdb_set_parameters(struct s921_isdb_t *dev, struct s921_isdb_t_transmission_mode_params *params) {
100
101 int ret;
102 /* auto is sufficient for now, lateron this should be reflected in an extra interface */
103
104
105
106 ret = dev->i2c_write(dev->priv_dev, 0xb0, 0xa0); //mod_b2);
107 ret = dev->i2c_write(dev->priv_dev, 0xb2, 0x3d); //mod_b2);
108
109 if (ret < 0)
110 return -EINVAL;
111
112 ret = dev->i2c_write(dev->priv_dev, 0xb3, 0x25); //mod_b3);
113 if (ret < 0)
114 return -EINVAL;
115
116 ret = dev->i2c_write(dev->priv_dev, 0xb4, 0x8b); //mod_b4);
117 if (ret < 0)
118 return -EINVAL;
119
120 ret = dev->i2c_write(dev->priv_dev, 0xb5, 0x4b); //mod_b5);
121 if (ret < 0)
122 return -EINVAL;
123
124 ret = dev->i2c_write(dev->priv_dev, 0xb6, 0x3f); //mod_b6);
125 if (ret < 0)
126 return -EINVAL;
127
128 ret = dev->i2c_write(dev->priv_dev, 0xb7, 0x3f); //mod_b7);
129 if (ret < 0)
130 return -EINVAL;
131
132 return E_OK;
133}
134
135static int s921_isdb_tune(struct s921_isdb_t *dev, struct s921_isdb_t_tune_params *params) {
136
137 int ret;
138 int index;
139
140 index = (params->frequency - 473143000)/6000000;
141
142 if (index > 48) {
143 return -EINVAL;
144 }
145
146 dev->i2c_write(dev->priv_dev, 0x47, 0x60);
147
148 ret = dev->i2c_write(dev->priv_dev, 0x68, 0x00);
149 if (ret < 0)
150 return -EINVAL;
151
152 ret = dev->i2c_write(dev->priv_dev, 0x69, 0x89);
153 if (ret < 0)
154 return -EINVAL;
155
156 ret = dev->i2c_write(dev->priv_dev, 0xf0, 0x48);
157 if (ret < 0)
158 return -EINVAL;
159
160 ret = dev->i2c_write(dev->priv_dev, 0xf1, 0x19);
161 if (ret < 0)
162 return -EINVAL;
163
164 ret = dev->i2c_write(dev->priv_dev, 0xf2, c_table[index*3]);
165 if (ret < 0)
166 return -EINVAL;
167
168 ret = dev->i2c_write(dev->priv_dev, 0xf3, c_table[index*3+1]);
169 if (ret < 0)
170 return -EINVAL;
171
172 ret = dev->i2c_write(dev->priv_dev, 0xf4, c_table[index*3+2]);
173 if (ret < 0)
174 return -EINVAL;
175
176 ret = dev->i2c_write(dev->priv_dev, 0xf5, 0xae);
177 if (ret < 0)
178 return -EINVAL;
179
180 ret = dev->i2c_write(dev->priv_dev, 0xf6, 0xb7);
181 if (ret < 0)
182 return -EINVAL;
183
184 ret = dev->i2c_write(dev->priv_dev, 0xf7, 0xba);
185 if (ret < 0)
186 return -EINVAL;
187
188 ret = dev->i2c_write(dev->priv_dev, 0xf8, 0xd7);
189 if (ret < 0)
190 return -EINVAL;
191
192 ret = dev->i2c_write(dev->priv_dev, 0x68, 0x0a);
193 if (ret < 0)
194 return -EINVAL;
195
196 ret = dev->i2c_write(dev->priv_dev, 0x69, 0x09);
197 if (ret < 0)
198 return -EINVAL;
199
200 dev->i2c_write(dev->priv_dev, 0x01, 0x40);
201 return 0;
202}
203
204static int s921_isdb_get_status(struct s921_isdb_t *dev, void *data) {
205 unsigned int *ret = (unsigned int*)data;
206 u8 ifagc_dt;
207 u8 rfagc_dt;
208
209 mdelay(10);
210 ifagc_dt = dev->i2c_read(dev->priv_dev, 0x81);
211 rfagc_dt = dev->i2c_read(dev->priv_dev, 0x82);
212 if (rfagc_dt == 0x40) {
213 *ret = 1;
214 }
215 return 0;
216}
diff --git a/drivers/media/dvb/frontends/s921_core.h b/drivers/media/dvb/frontends/s921_core.h
new file mode 100644
index 000000000000..de2f10a44e72
--- /dev/null
+++ b/drivers/media/dvb/frontends/s921_core.h
@@ -0,0 +1,114 @@
1#ifndef _S921_CORE_H
2#define _S921_CORE_H
3//#define u8 unsigned int
4//#define u32 unsigned int
5
6
7
8//#define EINVAL -1
9#define E_OK 0
10
11struct s921_isdb_t {
12 void *priv_dev;
13 int (*i2c_write)(void *dev, u8 reg, u8 val);
14 int (*i2c_read)(void *dev, u8 reg);
15};
16
17#define ISDB_T_CMD_INIT 0
18#define ISDB_T_CMD_SET_PARAM 1
19#define ISDB_T_CMD_TUNE 2
20#define ISDB_T_CMD_GET_STATUS 3
21
22struct s921_isdb_t_tune_params {
23 u32 frequency;
24};
25
26struct s921_isdb_t_status {
27};
28
29struct s921_isdb_t_transmission_mode_params {
30 u8 mode;
31 u8 layer_a_mode;
32#define ISDB_T_LA_MODE_1 0
33#define ISDB_T_LA_MODE_2 1
34#define ISDB_T_LA_MODE_3 2
35 u8 layer_a_carrier_modulation;
36#define ISDB_T_LA_CM_DQPSK 0
37#define ISDB_T_LA_CM_QPSK 1
38#define ISDB_T_LA_CM_16QAM 2
39#define ISDB_T_LA_CM_64QAM 3
40#define ISDB_T_LA_CM_NOLAYER 4
41 u8 layer_a_code_rate;
42#define ISDB_T_LA_CR_1_2 0
43#define ISDB_T_LA_CR_2_3 1
44#define ISDB_T_LA_CR_3_4 2
45#define ISDB_T_LA_CR_5_6 4
46#define ISDB_T_LA_CR_7_8 8
47#define ISDB_T_LA_CR_NOLAYER 16
48 u8 layer_a_time_interleave;
49#define ISDB_T_LA_TI_0 0
50#define ISDB_T_LA_TI_1 1
51#define ISDB_T_LA_TI_2 2
52#define ISDB_T_LA_TI_4 4
53#define ISDB_T_LA_TI_8 8
54#define ISDB_T_LA_TI_16 16
55#define ISDB_T_LA_TI_32 32
56 u8 layer_a_nseg;
57
58 u8 layer_b_mode;
59#define ISDB_T_LB_MODE_1 0
60#define ISDB_T_LB_MODE_2 1
61#define ISDB_T_LB_MODE_3 2
62 u8 layer_b_carrier_modulation;
63#define ISDB_T_LB_CM_DQPSK 0
64#define ISDB_T_LB_CM_QPSK 1
65#define ISDB_T_LB_CM_16QAM 2
66#define ISDB_T_LB_CM_64QAM 3
67#define ISDB_T_LB_CM_NOLAYER 4
68 u8 layer_b_code_rate;
69#define ISDB_T_LB_CR_1_2 0
70#define ISDB_T_LB_CR_2_3 1
71#define ISDB_T_LB_CR_3_4 2
72#define ISDB_T_LB_CR_5_6 4
73#define ISDB_T_LB_CR_7_8 8
74#define ISDB_T_LB_CR_NOLAYER 16
75 u8 layer_b_time_interleave;
76#define ISDB_T_LB_TI_0 0
77#define ISDB_T_LB_TI_1 1
78#define ISDB_T_LB_TI_2 2
79#define ISDB_T_LB_TI_4 4
80#define ISDB_T_LB_TI_8 8
81#define ISDB_T_LB_TI_16 16
82#define ISDB_T_LB_TI_32 32
83 u8 layer_b_nseg;
84
85 u8 layer_c_mode;
86#define ISDB_T_LC_MODE_1 0
87#define ISDB_T_LC_MODE_2 1
88#define ISDB_T_LC_MODE_3 2
89 u8 layer_c_carrier_modulation;
90#define ISDB_T_LC_CM_DQPSK 0
91#define ISDB_T_LC_CM_QPSK 1
92#define ISDB_T_LC_CM_16QAM 2
93#define ISDB_T_LC_CM_64QAM 3
94#define ISDB_T_LC_CM_NOLAYER 4
95 u8 layer_c_code_rate;
96#define ISDB_T_LC_CR_1_2 0
97#define ISDB_T_LC_CR_2_3 1
98#define ISDB_T_LC_CR_3_4 2
99#define ISDB_T_LC_CR_5_6 4
100#define ISDB_T_LC_CR_7_8 8
101#define ISDB_T_LC_CR_NOLAYER 16
102 u8 layer_c_time_interleave;
103#define ISDB_T_LC_TI_0 0
104#define ISDB_T_LC_TI_1 1
105#define ISDB_T_LC_TI_2 2
106#define ISDB_T_LC_TI_4 4
107#define ISDB_T_LC_TI_8 8
108#define ISDB_T_LC_TI_16 16
109#define ISDB_T_LC_TI_32 32
110 u8 layer_c_nseg;
111};
112
113int s921_isdb_cmd(struct s921_isdb_t *dev, u32 cmd, void *data);
114#endif
diff --git a/drivers/media/dvb/frontends/s921_module.c b/drivers/media/dvb/frontends/s921_module.c
new file mode 100644
index 000000000000..3cbb9cb2cf47
--- /dev/null
+++ b/drivers/media/dvb/frontends/s921_module.c
@@ -0,0 +1,190 @@
1/*
2 * Driver for Sharp s921 driver
3 *
4 * Copyright (C) 2008 Markus Rechberger <mrechberger@sundtek.de>
5 *
6 * All rights reserved.
7 *
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/delay.h>
13#include "dvb_frontend.h"
14#include "s921_module.h"
15#include "s921_core.h"
16
17static unsigned int debug = 0;
18module_param(debug, int, 0644);
19MODULE_PARM_DESC(debug,"s921 debugging (default off)");
20
21#define dprintk(fmt, args...) if (debug) do {\
22 printk("s921 debug: " fmt, ##args); } while (0)
23
24struct s921_state
25{
26 struct dvb_frontend frontend;
27 fe_modulation_t current_modulation;
28 __u32 snr;
29 __u32 current_frequency;
30 __u8 addr;
31 struct s921_isdb_t dev;
32 struct i2c_adapter *i2c;
33};
34
35static int s921_set_parameters(struct dvb_frontend *fe, struct dvb_frontend_parameters *param) {
36 struct s921_state *state = (struct s921_state *)fe->demodulator_priv;
37 struct s921_isdb_t_transmission_mode_params params;
38 struct s921_isdb_t_tune_params tune_params;
39
40 tune_params.frequency = param->frequency;
41 s921_isdb_cmd(&state->dev, ISDB_T_CMD_SET_PARAM, &params);
42 s921_isdb_cmd(&state->dev, ISDB_T_CMD_TUNE, &tune_params);
43 mdelay(100);
44 return 0;
45}
46
47static int s921_init(struct dvb_frontend *fe) {
48 printk("s921 init\n");
49 return 0;
50}
51
52static int s921_sleep(struct dvb_frontend *fe) {
53 printk("s921 sleep\n");
54 return 0;
55}
56
57static int s921_read_status(struct dvb_frontend *fe, fe_status_t *status)
58{
59 struct s921_state *state = (struct s921_state *)fe->demodulator_priv;
60 unsigned int ret;
61 mdelay(5);
62 s921_isdb_cmd(&state->dev, ISDB_T_CMD_GET_STATUS, &ret);
63 *status = 0;
64
65 printk("status: %02x\n", ret);
66 if (ret == 1) {
67 *status |= FE_HAS_CARRIER;
68 *status |= FE_HAS_VITERBI;
69 *status |= FE_HAS_LOCK;
70 *status |= FE_HAS_SYNC;
71 *status |= FE_HAS_SIGNAL;
72 }
73
74 return 0;
75}
76
77static int s921_read_ber(struct dvb_frontend *fe, __u32 *ber)
78{
79 dprintk("read ber\n");
80 return 0;
81}
82
83static int s921_read_snr(struct dvb_frontend *fe, __u16 *snr)
84{
85 dprintk("read snr\n");
86 return 0;
87}
88
89static int s921_read_ucblocks(struct dvb_frontend *fe, __u32 *ucblocks)
90{
91 dprintk("read ucblocks\n");
92 return 0;
93}
94
95static void s921_release(struct dvb_frontend *fe)
96{
97 struct s921_state *state = (struct s921_state *)fe->demodulator_priv;
98 kfree(state);
99}
100
101static struct dvb_frontend_ops demod_s921={
102 .info = {
103 .name = "SHARP S921",
104 .type = FE_OFDM,
105 .frequency_min = 473143000,
106 .frequency_max = 767143000,
107 .frequency_stepsize = 6000000,
108 .frequency_tolerance = 0,
109 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
110 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
111 FE_CAN_FEC_AUTO |
112 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
113 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
114 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
115 FE_CAN_MUTE_TS
116 },
117 .init = s921_init,
118 .sleep = s921_sleep,
119 .set_frontend = s921_set_parameters,
120 .read_snr = s921_read_snr,
121 .read_ber = s921_read_ber,
122 .read_status = s921_read_status,
123 .read_ucblocks = s921_read_ucblocks,
124 .release = s921_release,
125};
126
127static int s921_write(void *dev, u8 reg, u8 val) {
128 struct s921_state *state = dev;
129 char buf[2]={reg,val};
130 int err;
131 struct i2c_msg i2cmsgs = {
132 .addr = state->addr,
133 .flags = 0,
134 .len = 2,
135 .buf = buf
136 };
137
138 if((err = i2c_transfer(state->i2c, &i2cmsgs, 1))<0) {
139 printk("%s i2c_transfer error %d\n", __FUNCTION__, err);
140 if (err < 0)
141 return err;
142 else
143 return -EREMOTEIO;
144 }
145
146 return 0;
147}
148
149static int s921_read(void *dev, u8 reg) {
150 struct s921_state *state = dev;
151 u8 b1;
152 int ret;
153 struct i2c_msg msg[2] = { { .addr = state->addr,
154 .flags = 0,
155 .buf = &reg, .len = 1 },
156 { .addr = state->addr,
157 .flags = I2C_M_RD,
158 .buf = &b1, .len = 1 } };
159
160 ret = i2c_transfer(state->i2c, msg, 2);
161 if (ret != 2)
162 return ret;
163 return b1;
164}
165
166struct dvb_frontend* s921_attach(const struct s921_config *config,
167 struct i2c_adapter *i2c)
168{
169
170 struct s921_state *state;
171 state = kzalloc(sizeof(struct s921_state), GFP_KERNEL);
172 memset(state, 0x0, sizeof(struct s921_state));
173
174 state->addr = config->i2c_address;
175 state->i2c = i2c;
176 state->dev.i2c_write = &s921_write;
177 state->dev.i2c_read = &s921_read;
178 state->dev.priv_dev = state;
179
180 s921_isdb_cmd(&state->dev, ISDB_T_CMD_INIT, NULL);
181
182 memcpy(&state->frontend.ops, &demod_s921, sizeof(struct dvb_frontend_ops));
183 state->frontend.demodulator_priv = state;
184 return &state->frontend;
185}
186
187EXPORT_SYMBOL_GPL(s921_attach);
188MODULE_AUTHOR("Markus Rechberger <mrechberger@empiatech.com>");
189MODULE_DESCRIPTION("Sharp S921 ISDB-T 1Seg");
190MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/s921_module.h b/drivers/media/dvb/frontends/s921_module.h
new file mode 100644
index 000000000000..78660424ba95
--- /dev/null
+++ b/drivers/media/dvb/frontends/s921_module.h
@@ -0,0 +1,49 @@
1/*
2 * Driver for DVB-T s921 demodulator
3 *
4 * Copyright (C) 2008 Markus Rechberger <mrechberger@sundtek.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
20 */
21
22#ifndef S921_MODULE_H
23#define S921_MODULE_H
24
25#include <linux/dvb/frontend.h>
26#include "s921_core.h"
27
28int s921_isdb_init(struct s921_isdb_t *dev);
29int s921_isdb_cmd(struct s921_isdb_t *dev, u32 cmd, void *data);
30
31struct s921_config
32{
33 /* demodulator's I2C address */
34 u8 i2c_address;
35};
36
37#if defined(CONFIG_DVB_S921) || (defined(CONFIG_DVB_S921_MODULE) && defined(MODULE))
38extern struct dvb_frontend* s921_attach(const struct s921_config *config,
39 struct i2c_adapter *i2c);
40#else
41static inline struct dvb_frontend* s921_attach(const struct s921_config *config,
42 struct i2c_adapter *i2c)
43{
44 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
45 return NULL;
46}
47#endif /* CONFIG_DVB_S921 */
48
49#endif /* S921_H */
diff --git a/drivers/media/dvb/frontends/si21xx.c b/drivers/media/dvb/frontends/si21xx.c
index 3ddbe69c45ce..0bd16af8a6cd 100644
--- a/drivers/media/dvb/frontends/si21xx.c
+++ b/drivers/media/dvb/frontends/si21xx.c
@@ -8,7 +8,6 @@
8* (at your option) any later version. 8* (at your option) any later version.
9* 9*
10*/ 10*/
11#include <linux/version.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/kernel.h> 12#include <linux/kernel.h>
14#include <linux/module.h> 13#include <linux/module.h>
diff --git a/drivers/media/dvb/frontends/stb0899_algo.c b/drivers/media/dvb/frontends/stb0899_algo.c
new file mode 100644
index 000000000000..ced9b7ae7d50
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_algo.c
@@ -0,0 +1,1519 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include "stb0899_drv.h"
23#include "stb0899_priv.h"
24#include "stb0899_reg.h"
25
26inline u32 stb0899_do_div(u64 n, u32 d)
27{
28 /* wrap do_div() for ease of use */
29
30 do_div(n, d);
31 return n;
32}
33
34/*
35 * stb0899_calc_srate
36 * Compute symbol rate
37 */
38static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
39{
40 u64 tmp;
41
42 /* srate = (SFR * master_clk) >> 20 */
43
44 /* sfr is of size 20 bit, stored with an offset of 4 bit */
45 tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
46 tmp &= ~0xf;
47 tmp *= master_clk;
48 tmp >>= 24;
49
50 return tmp;
51}
52
53/*
54 * stb0899_get_srate
55 * Get the current symbol rate
56 */
57u32 stb0899_get_srate(struct stb0899_state *state)
58{
59 struct stb0899_internal *internal = &state->internal;
60 u8 sfr[3];
61
62 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
63
64 return stb0899_calc_srate(internal->master_clk, sfr);
65}
66
67/*
68 * stb0899_set_srate
69 * Set symbol frequency
70 * MasterClock: master clock frequency (hz)
71 * SymbolRate: symbol rate (bauds)
72 * return symbol frequency
73 */
74static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
75{
76 u32 tmp;
77 u8 sfr[3];
78
79 dprintk(state->verbose, FE_DEBUG, 1, "-->");
80 /*
81 * in order to have the maximum precision, the symbol rate entered into
82 * the chip is computed as the closest value of the "true value".
83 * In this purpose, the symbol rate value is rounded (1 is added on the bit
84 * below the LSB )
85 *
86 * srate = (SFR * master_clk) >> 20
87 * <=>
88 * SFR = srate << 20 / master_clk
89 *
90 * rounded:
91 * SFR = (srate << 21 + master_clk) / (2 * master_clk)
92 *
93 * stored as 20 bit number with an offset of 4 bit:
94 * sfr = SFR << 4;
95 */
96
97 tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
98 tmp <<= 4;
99
100 sfr[0] = tmp >> 16;
101 sfr[1] = tmp >> 8;
102 sfr[2] = tmp;
103
104 stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
105
106 return srate;
107}
108
109/*
110 * stb0899_calc_derot_time
111 * Compute the amount of time needed by the derotator to lock
112 * SymbolRate: Symbol rate
113 * return: derotator time constant (ms)
114 */
115static long stb0899_calc_derot_time(long srate)
116{
117 if (srate > 0)
118 return (100000 / (srate / 1000));
119 else
120 return 0;
121}
122
123/*
124 * stb0899_carr_width
125 * Compute the width of the carrier
126 * return: width of carrier (kHz or Mhz)
127 */
128long stb0899_carr_width(struct stb0899_state *state)
129{
130 struct stb0899_internal *internal = &state->internal;
131
132 return (internal->srate + (internal->srate * internal->rolloff) / 100);
133}
134
135/*
136 * stb0899_first_subrange
137 * Compute the first subrange of the search
138 */
139static void stb0899_first_subrange(struct stb0899_state *state)
140{
141 struct stb0899_internal *internal = &state->internal;
142 struct stb0899_params *params = &state->params;
143 struct stb0899_config *config = state->config;
144
145 int range = 0;
146 u32 bandwidth = 0;
147
148 if (config->tuner_get_bandwidth) {
149 stb0899_i2c_gate_ctrl(&state->frontend, 1);
150 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
151 stb0899_i2c_gate_ctrl(&state->frontend, 0);
152 range = bandwidth - stb0899_carr_width(state) / 2;
153 }
154
155 if (range > 0)
156 internal->sub_range = MIN(internal->srch_range, range);
157 else
158 internal->sub_range = 0;
159
160 internal->freq = params->freq;
161 internal->tuner_offst = 0L;
162 internal->sub_dir = 1;
163}
164
165/*
166 * stb0899_check_tmg
167 * check for timing lock
168 * internal.Ttiming: time to wait for loop lock
169 */
170static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
171{
172 struct stb0899_internal *internal = &state->internal;
173 int lock;
174 u8 reg;
175 s8 timing;
176
177 msleep(internal->t_derot);
178
179 stb0899_write_reg(state, STB0899_RTF, 0xf2);
180 reg = stb0899_read_reg(state, STB0899_TLIR);
181 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
182 timing = stb0899_read_reg(state, STB0899_RTF);
183
184 if (lock >= 42) {
185 if ((lock > 48) && (ABS(timing) >= 110)) {
186 internal->status = ANALOGCARRIER;
187 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
188 } else {
189 internal->status = TIMINGOK;
190 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
191 }
192 } else {
193 internal->status = NOTIMING;
194 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
195 }
196 return internal->status;
197}
198
199/*
200 * stb0899_search_tmg
201 * perform a fs/2 zig-zag to find timing
202 */
203static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
204{
205 struct stb0899_internal *internal = &state->internal;
206 struct stb0899_params *params = &state->params;
207
208 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
209 int index = 0;
210 u8 cfr[2];
211
212 internal->status = NOTIMING;
213
214 /* timing loop computation & symbol rate optimisation */
215 derot_limit = (internal->sub_range / 2L) / internal->mclk;
216 derot_step = (params->srate / 2L) / internal->mclk;
217
218 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
219 index++;
220 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
221
222 if (ABS(derot_freq) > derot_limit)
223 next_loop--;
224
225 if (next_loop) {
226 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
227 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
228 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
229 }
230 internal->direction = -internal->direction; /* Change zigzag direction */
231 }
232
233 if (internal->status == TIMINGOK) {
234 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
235 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
236 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
237 }
238
239 return internal->status;
240}
241
242/*
243 * stb0899_check_carrier
244 * Check for carrier found
245 */
246static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
247{
248 struct stb0899_internal *internal = &state->internal;
249 u8 reg;
250
251 msleep(internal->t_derot); /* wait for derotator ok */
252
253 reg = stb0899_read_reg(state, STB0899_CFD);
254 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
255 stb0899_write_reg(state, STB0899_CFD, reg);
256
257 reg = stb0899_read_reg(state, STB0899_DSTATUS);
258 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
259 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
260 internal->status = CARRIEROK;
261 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
262 } else {
263 internal->status = NOCARRIER;
264 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
265 }
266
267 return internal->status;
268}
269
270/*
271 * stb0899_search_carrier
272 * Search for a QPSK carrier with the derotator
273 */
274static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
275{
276 struct stb0899_internal *internal = &state->internal;
277
278 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
279 int index = 0;
280 u8 cfr[2];
281 u8 reg;
282
283 internal->status = NOCARRIER;
284 derot_limit = (internal->sub_range / 2L) / internal->mclk;
285 derot_freq = internal->derot_freq;
286
287 reg = stb0899_read_reg(state, STB0899_CFD);
288 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
289 stb0899_write_reg(state, STB0899_CFD, reg);
290
291 do {
292 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
293 if (stb0899_check_carrier(state) == NOCARRIER) {
294 index++;
295 last_derot_freq = derot_freq;
296 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
297
298 if(ABS(derot_freq) > derot_limit)
299 next_loop--;
300
301 if (next_loop) {
302 reg = stb0899_read_reg(state, STB0899_CFD);
303 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
304 stb0899_write_reg(state, STB0899_CFD, reg);
305
306 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
307 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
308 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
309 }
310 }
311
312 internal->direction = -internal->direction; /* Change zigzag direction */
313 } while ((internal->status != CARRIEROK) && next_loop);
314
315 if (internal->status == CARRIEROK) {
316 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
317 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
318 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
319 } else {
320 internal->derot_freq = last_derot_freq;
321 }
322
323 return internal->status;
324}
325
326/*
327 * stb0899_check_data
328 * Check for data found
329 */
330static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
331{
332 struct stb0899_internal *internal = &state->internal;
333 struct stb0899_params *params = &state->params;
334
335 int lock = 0, index = 0, dataTime = 500, loop;
336 u8 reg;
337
338 internal->status = NODATA;
339
340 /* RESET FEC */
341 reg = stb0899_read_reg(state, STB0899_TSTRES);
342 STB0899_SETFIELD_VAL(FRESACS, reg, 1);
343 stb0899_write_reg(state, STB0899_TSTRES, reg);
344 msleep(1);
345 reg = stb0899_read_reg(state, STB0899_TSTRES);
346 STB0899_SETFIELD_VAL(FRESACS, reg, 0);
347 stb0899_write_reg(state, STB0899_TSTRES, reg);
348
349 if (params->srate <= 2000000)
350 dataTime = 2000;
351 else if (params->srate <= 5000000)
352 dataTime = 1500;
353 else if (params->srate <= 15000000)
354 dataTime = 1000;
355 else
356 dataTime = 500;
357
358 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
359 while (1) {
360 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
361 reg = stb0899_read_reg(state, STB0899_VSTATUS);
362 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
363 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
364
365 if (lock || loop || (index > dataTime))
366 break;
367 index++;
368 }
369
370 if (lock) { /* DATA LOCK indicator */
371 internal->status = DATAOK;
372 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
373 }
374
375 return internal->status;
376}
377
378/*
379 * stb0899_search_data
380 * Search for a QPSK carrier with the derotator
381 */
382static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
383{
384 short int derot_freq, derot_step, derot_limit, next_loop = 3;
385 u8 cfr[2];
386 u8 reg;
387 int index = 1;
388
389 struct stb0899_internal *internal = &state->internal;
390 struct stb0899_params *params = &state->params;
391
392 derot_step = (params->srate / 4L) / internal->mclk;
393 derot_limit = (internal->sub_range / 2L) / internal->mclk;
394 derot_freq = internal->derot_freq;
395
396 do {
397 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
398
399 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
400 if (ABS(derot_freq) > derot_limit)
401 next_loop--;
402
403 if (next_loop) {
404 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
405 reg = stb0899_read_reg(state, STB0899_CFD);
406 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
407 stb0899_write_reg(state, STB0899_CFD, reg);
408
409 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
410 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
411 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
412
413 stb0899_check_carrier(state);
414 index++;
415 }
416 }
417 internal->direction = -internal->direction; /* change zig zag direction */
418 } while ((internal->status != DATAOK) && next_loop);
419
420 if (internal->status == DATAOK) {
421 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
422 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
423 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
424 }
425
426 return internal->status;
427}
428
429/*
430 * stb0899_check_range
431 * check if the found frequency is in the correct range
432 */
433static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
434{
435 struct stb0899_internal *internal = &state->internal;
436 struct stb0899_params *params = &state->params;
437
438 int range_offst, tp_freq;
439
440 range_offst = internal->srch_range / 2000;
441 tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
442
443 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
444 internal->status = RANGEOK;
445 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
446 } else {
447 internal->status = OUTOFRANGE;
448 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
449 }
450
451 return internal->status;
452}
453
454/*
455 * NextSubRange
456 * Compute the next subrange of the search
457 */
458static void next_sub_range(struct stb0899_state *state)
459{
460 struct stb0899_internal *internal = &state->internal;
461 struct stb0899_params *params = &state->params;
462
463 long old_sub_range;
464
465 if (internal->sub_dir > 0) {
466 old_sub_range = internal->sub_range;
467 internal->sub_range = MIN((internal->srch_range / 2) -
468 (internal->tuner_offst + internal->sub_range / 2),
469 internal->sub_range);
470
471 if (internal->sub_range < 0)
472 internal->sub_range = 0;
473
474 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
475 }
476
477 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
478 internal->sub_dir = -internal->sub_dir;
479}
480
481/*
482 * stb0899_dvbs_algo
483 * Search for a signal, timing, carrier and data for a
484 * given frequency in a given range
485 */
486enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
487{
488 struct stb0899_params *params = &state->params;
489 struct stb0899_internal *internal = &state->internal;
490 struct stb0899_config *config = state->config;
491
492 u8 bclc, reg;
493 u8 cfr[2];
494 u8 eq_const[10];
495 s32 clnI = 3;
496 u32 bandwidth = 0;
497
498 /* BETA values rated @ 99MHz */
499 s32 betaTab[5][4] = {
500 /* 5 10 20 30MBps */
501 { 37, 34, 32, 31 }, /* QPSK 1/2 */
502 { 37, 35, 33, 31 }, /* QPSK 2/3 */
503 { 37, 35, 33, 31 }, /* QPSK 3/4 */
504 { 37, 36, 33, 32 }, /* QPSK 5/6 */
505 { 37, 36, 33, 32 } /* QPSK 7/8 */
506 };
507
508 internal->direction = 1;
509
510 stb0899_set_srate(state, internal->master_clk, params->srate);
511 /* Carrier loop optimization versus symbol rate for acquisition*/
512 if (params->srate <= 5000000) {
513 stb0899_write_reg(state, STB0899_ACLC, 0x89);
514 bclc = stb0899_read_reg(state, STB0899_BCLC);
515 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
516 stb0899_write_reg(state, STB0899_BCLC, bclc);
517 clnI = 0;
518 } else if (params->srate <= 15000000) {
519 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
520 bclc = stb0899_read_reg(state, STB0899_BCLC);
521 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
522 stb0899_write_reg(state, STB0899_BCLC, bclc);
523 clnI = 1;
524 } else if(params->srate <= 25000000) {
525 stb0899_write_reg(state, STB0899_ACLC, 0x89);
526 bclc = stb0899_read_reg(state, STB0899_BCLC);
527 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
528 stb0899_write_reg(state, STB0899_BCLC, bclc);
529 clnI = 2;
530 } else {
531 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
532 bclc = stb0899_read_reg(state, STB0899_BCLC);
533 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
534 stb0899_write_reg(state, STB0899_BCLC, bclc);
535 clnI = 3;
536 }
537
538 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
539 /* Set the timing loop to acquisition */
540 stb0899_write_reg(state, STB0899_RTC, 0x46);
541 stb0899_write_reg(state, STB0899_CFD, 0xee);
542
543 /* !! WARNING !!
544 * Do not read any status variables while acquisition,
545 * If any needed, read before the acquisition starts
546 * querying status while acquiring causes the
547 * acquisition to go bad and hence no locks.
548 */
549 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
550 internal->derot_percent, params->srate, internal->mclk);
551
552 /* Initial calculations */
553 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
554 internal->t_derot = stb0899_calc_derot_time(params->srate);
555 internal->t_data = 500;
556
557 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
558 /* RESET Stream merger */
559 reg = stb0899_read_reg(state, STB0899_TSTRES);
560 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
561 stb0899_write_reg(state, STB0899_TSTRES, reg);
562
563 /*
564 * Set KDIVIDER to an intermediate value between
565 * 1/2 and 7/8 for acquisition
566 */
567 reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
568 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
569 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
570
571 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
572 stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
573
574 stb0899_first_subrange(state);
575 do {
576 /* Initialisations */
577 cfr[0] = cfr[1] = 0;
578 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
579
580 stb0899_write_reg(state, STB0899_RTF, 0);
581 reg = stb0899_read_reg(state, STB0899_CFD);
582 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
583 stb0899_write_reg(state, STB0899_CFD, reg);
584
585 internal->derot_freq = 0;
586 internal->status = NOAGC1;
587
588 /* enable tuner I/O */
589 stb0899_i2c_gate_ctrl(&state->frontend, 1);
590
591 /* Move tuner to frequency */
592 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
593 if (state->config->tuner_set_frequency)
594 state->config->tuner_set_frequency(&state->frontend, internal->freq);
595
596 if (state->config->tuner_get_frequency)
597 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
598
599 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */
600 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
601 internal->status = AGC1OK;
602
603 /* There is signal in the band */
604 if (config->tuner_get_bandwidth)
605 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
606
607 /* disable tuner I/O */
608 stb0899_i2c_gate_ctrl(&state->frontend, 0);
609
610 if (params->srate <= bandwidth / 2)
611 stb0899_search_tmg(state); /* For low rates (SCPC) */
612 else
613 stb0899_check_tmg(state); /* For high rates (MCPC) */
614
615 if (internal->status == TIMINGOK) {
616 dprintk(state->verbose, FE_DEBUG, 1,
617 "TIMING OK ! Derot freq=%d, mclk=%d",
618 internal->derot_freq, internal->mclk);
619
620 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
621 dprintk(state->verbose, FE_DEBUG, 1,
622 "CARRIER OK ! Derot freq=%d, mclk=%d",
623 internal->derot_freq, internal->mclk);
624
625 if (stb0899_search_data(state) == DATAOK) { /* Check for data */
626 dprintk(state->verbose, FE_DEBUG, 1,
627 "DATA OK ! Derot freq=%d, mclk=%d",
628 internal->derot_freq, internal->mclk);
629
630 if (stb0899_check_range(state) == RANGEOK) {
631 dprintk(state->verbose, FE_DEBUG, 1,
632 "RANGE OK ! derot freq=%d, mclk=%d",
633 internal->derot_freq, internal->mclk);
634
635 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
636 reg = stb0899_read_reg(state, STB0899_PLPARM);
637 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
638 dprintk(state->verbose, FE_DEBUG, 1,
639 "freq=%d, internal resultant freq=%d",
640 params->freq, internal->freq);
641
642 dprintk(state->verbose, FE_DEBUG, 1,
643 "internal puncture rate=%d",
644 internal->fecrate);
645 }
646 }
647 }
648 }
649 if (internal->status != RANGEOK)
650 next_sub_range(state);
651
652 } while (internal->sub_range && internal->status != RANGEOK);
653
654 /* Set the timing loop to tracking */
655 stb0899_write_reg(state, STB0899_RTC, 0x33);
656 stb0899_write_reg(state, STB0899_CFD, 0xf7);
657 /* if locked and range ok, set Kdiv */
658 if (internal->status == RANGEOK) {
659 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
660 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
661 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
662
663 /*
664 * Carrier loop optimization versus
665 * symbol Rate/Puncture Rate for Tracking
666 */
667 reg = stb0899_read_reg(state, STB0899_BCLC);
668 switch (internal->fecrate) {
669 case STB0899_FEC_1_2: /* 13 */
670 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
671 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
672 stb0899_write_reg(state, STB0899_BCLC, reg);
673 break;
674 case STB0899_FEC_2_3: /* 18 */
675 stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
676 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
677 stb0899_write_reg(state, STB0899_BCLC, reg);
678 break;
679 case STB0899_FEC_3_4: /* 21 */
680 stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
681 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
682 stb0899_write_reg(state, STB0899_BCLC, reg);
683 break;
684 case STB0899_FEC_5_6: /* 24 */
685 stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
686 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
687 stb0899_write_reg(state, STB0899_BCLC, reg);
688 break;
689 case STB0899_FEC_6_7: /* 25 */
690 stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
691 stb0899_write_reg(state, STB0899_ACLC, 0x88);
692 stb0899_write_reg(state, STB0899_BCLC, 0x9a);
693 break;
694 case STB0899_FEC_7_8: /* 26 */
695 stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
696 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
697 stb0899_write_reg(state, STB0899_BCLC, reg);
698 break;
699 default:
700 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
701 break;
702 }
703 /* release stream merger RESET */
704 reg = stb0899_read_reg(state, STB0899_TSTRES);
705 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
706 stb0899_write_reg(state, STB0899_TSTRES, reg);
707
708 /* disable carrier detector */
709 reg = stb0899_read_reg(state, STB0899_CFD);
710 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
711 stb0899_write_reg(state, STB0899_CFD, reg);
712
713 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
714 }
715
716 return internal->status;
717}
718
719/*
720 * stb0899_dvbs2_config_uwp
721 * Configure UWP state machine
722 */
723static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
724{
725 struct stb0899_internal *internal = &state->internal;
726 struct stb0899_config *config = state->config;
727 u32 uwp1, uwp2, uwp3, reg;
728
729 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
730 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
731 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
732
733 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
734 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
735 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
736
737 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
738 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
739 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
740
741 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
742 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
743
744 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
745 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
746 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
747
748 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
749 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
750 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
751}
752
753/*
754 * stb0899_dvbs2_config_csm_auto
755 * Set CSM to AUTO mode
756 */
757static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
758{
759 u32 reg;
760
761 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
762 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
763 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
764}
765
766long Log2Int(int number)
767{
768 int i;
769
770 i = 0;
771 while ((1 << i) <= ABS(number))
772 i++;
773
774 if (number == 0)
775 i = 1;
776
777 return i - 1;
778}
779
780/*
781 * stb0899_dvbs2_calc_srate
782 * compute BTR_NOM_FREQ for the symbol rate
783 */
784static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
785{
786 struct stb0899_internal *internal = &state->internal;
787 struct stb0899_config *config = state->config;
788
789 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
790 u32 master_clk, srate;
791
792 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
793 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
794 dec_rate = Log2Int(dec_ratio);
795 decim = 1 << dec_rate;
796 master_clk = internal->master_clk / 1000;
797 srate = internal->srate / 1000;
798
799 if (decim <= 4) {
800 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
801 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
802 } else {
803 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
804 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
805 }
806 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
807
808 return btr_nom_freq;
809}
810
811/*
812 * stb0899_dvbs2_calc_dev
813 * compute the correction to be applied to symbol rate
814 */
815static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
816{
817 struct stb0899_internal *internal = &state->internal;
818 u32 dec_ratio, correction, master_clk, srate;
819
820 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
821 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
822
823 master_clk = internal->master_clk / 1000; /* for integer Caculation*/
824 srate = internal->srate / 1000; /* for integer Caculation*/
825 correction = (512 * master_clk) / (2 * dec_ratio * srate);
826
827 return correction;
828}
829
830/*
831 * stb0899_dvbs2_set_srate
832 * Set DVBS2 symbol rate
833 */
834static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
835{
836 struct stb0899_internal *internal = &state->internal;
837
838 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
839 u32 correction, freq_adj, band_lim, decim_cntrl, reg;
840 u8 anti_alias;
841
842 /*set decimation to 1*/
843 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
844 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
845 dec_rate = Log2Int(dec_ratio);
846
847 win_sel = 0;
848 if (dec_rate >= 5)
849 win_sel = dec_rate - 4;
850
851 decim = (1 << dec_rate);
852 /* (FSamp/Fsymbol *100) for integer Caculation */
853 f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
854
855 if (f_sym <= 2250) /* don't band limit signal going into btr block*/
856 band_lim = 1;
857 else
858 band_lim = 0; /* band limit signal going into btr block*/
859
860 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
861 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
862
863 if (f_sym <= 3450)
864 anti_alias = 0;
865 else if (f_sym <= 4250)
866 anti_alias = 1;
867 else
868 anti_alias = 2;
869
870 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
871 btr_nom_freq = stb0899_dvbs2_calc_srate(state);
872 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
873
874 correction = stb0899_dvbs2_calc_dev(state);
875 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
876 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
877 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
878
879 /* scale UWP+CSM frequency to sample rate*/
880 freq_adj = internal->srate / (internal->master_clk / 4096);
881 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
882}
883
884/*
885 * stb0899_dvbs2_set_btr_loopbw
886 * set bit timing loop bandwidth as a percentage of the symbol rate
887 */
888static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
889{
890 struct stb0899_internal *internal = &state->internal;
891 struct stb0899_config *config = state->config;
892
893 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
894 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
895 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
896 u32 decim, K, wn, k_direct, k_indirect;
897 u32 reg;
898
899 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
900 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
901 dec_rate = Log2Int(dec_ratio);
902 decim = (1 << dec_rate);
903
904 sym_peak *= 576000;
905 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
906 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
907
908 if (K != 0) {
909 K = sym_peak / K;
910 wn = (4 * zeta * zeta) + 1000000;
911 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
912
913 k_indirect = (wn * wn) / K;
914 k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/
915 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
916 k_direct *= 100;
917
918 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
919 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
920 k_btr1 = k_direct / (1 << k_direct_shift);
921 k_btr1 /= 10000;
922
923 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
924 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
925 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
926 k_btr0 /= 1000000;
927
928 k_btr2_rshft = 0;
929 if (k_btr0_rshft > 15) {
930 k_btr2_rshft = k_btr0_rshft - 15;
931 k_btr0_rshft = 15;
932 }
933 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
934 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
935 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
936 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
937 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
938 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
939 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
940 } else
941 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
942}
943
944/*
945 * stb0899_dvbs2_set_carr_freq
946 * set nominal frequency for carrier search
947 */
948static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
949{
950 struct stb0899_config *config = state->config;
951 s32 crl_nom_freq;
952 u32 reg;
953
954 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
955 crl_nom_freq *= carr_freq;
956 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
957 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
958 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
959}
960
961/*
962 * stb0899_dvbs2_init_calc
963 * Initialize DVBS2 UWP, CSM, carrier and timing loops
964 */
965static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
966{
967 struct stb0899_internal *internal = &state->internal;
968 s32 steps, step_size;
969 u32 range, reg;
970
971 /* config uwp and csm */
972 stb0899_dvbs2_config_uwp(state);
973 stb0899_dvbs2_config_csm_auto(state);
974
975 /* initialize BTR */
976 stb0899_dvbs2_set_srate(state);
977 stb0899_dvbs2_set_btr_loopbw(state);
978
979 if (internal->srate / 1000000 >= 15)
980 step_size = (1 << 17) / 5;
981 else if (internal->srate / 1000000 >= 10)
982 step_size = (1 << 17) / 7;
983 else if (internal->srate / 1000000 >= 5)
984 step_size = (1 << 17) / 10;
985 else
986 step_size = (1 << 17) / 4;
987
988 range = internal->srch_range / 1000000;
989 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
990 steps = (steps + 6) / 10;
991 steps = (steps == 0) ? 1 : steps;
992 if (steps % 2 == 0)
993 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
994 (internal->step_size * (internal->srate / 20000000)),
995 (internal->master_clk) / 1000000);
996 else
997 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
998
999 /*Set Carrier Search params (zigzag, num steps and freq step size*/
1000 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1001 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1002 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1003 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1004 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1005}
1006
1007/*
1008 * stb0899_dvbs2_btr_init
1009 * initialize the timing loop
1010 */
1011static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1012{
1013 u32 reg;
1014
1015 /* set enable BTR loopback */
1016 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1017 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1018 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1019 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1020
1021 /* fix btr freq accum at 0 */
1022 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1023 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1024
1025 /* fix btr freq accum at 0 */
1026 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1027 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1028}
1029
1030/*
1031 * stb0899_dvbs2_reacquire
1032 * trigger a DVB-S2 acquisition
1033 */
1034static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1035{
1036 u32 reg = 0;
1037
1038 /* demod soft reset */
1039 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1040 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1041
1042 /*Reset Timing Loop */
1043 stb0899_dvbs2_btr_init(state);
1044
1045 /* reset Carrier loop */
1046 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1047 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1048 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1049 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1050 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1051
1052 /*release demod soft reset */
1053 reg = 0;
1054 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1055 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1056
1057 /* start acquisition process */
1058 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1059 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1060
1061 /* equalizer Init */
1062 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1063
1064 /*Start equilizer */
1065 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1066
1067 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1068 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1069 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1070 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1071 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1072 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1073
1074 /* RESET Packet delineator */
1075 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1076}
1077
1078/*
1079 * stb0899_dvbs2_get_dmd_status
1080 * get DVB-S2 Demod LOCK status
1081 */
1082static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1083{
1084 int time = -10, lock = 0, uwp, csm;
1085 u32 reg;
1086
1087 do {
1088 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1089 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1090 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1091 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1092 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1093 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1094 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1095 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1096 if (uwp && csm)
1097 lock = 1;
1098
1099 time += 10;
1100 msleep(10);
1101
1102 } while ((!lock) && (time <= timeout));
1103
1104 if (lock) {
1105 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1106 return DVBS2_DEMOD_LOCK;
1107 } else {
1108 return DVBS2_DEMOD_NOLOCK;
1109 }
1110}
1111
1112/*
1113 * stb0899_dvbs2_get_data_lock
1114 * get FEC status
1115 */
1116static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1117{
1118 int time = 0, lock = 0;
1119 u8 reg;
1120
1121 while ((!lock) && (time < timeout)) {
1122 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1123 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1124 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1125 time++;
1126 }
1127
1128 return lock;
1129}
1130
1131/*
1132 * stb0899_dvbs2_get_fec_status
1133 * get DVB-S2 FEC LOCK status
1134 */
1135static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1136{
1137 int time = 0, Locked;
1138
1139 do {
1140 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1141 time++;
1142 msleep(1);
1143
1144 } while ((!Locked) && (time < timeout));
1145
1146 if (Locked) {
1147 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1148 return DVBS2_FEC_LOCK;
1149 } else {
1150 return DVBS2_FEC_NOLOCK;
1151 }
1152}
1153
1154
1155/*
1156 * stb0899_dvbs2_init_csm
1157 * set parameters for manual mode
1158 */
1159static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1160{
1161 struct stb0899_internal *internal = &state->internal;
1162
1163 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1164 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1165 u32 csm1, csm2, csm3, csm4;
1166
1167 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1168 switch (modcod) {
1169 case STB0899_QPSK_12:
1170 gamma_acq = 25;
1171 gamma_rho_acq = 2700;
1172 gamma_trk = 12;
1173 gamma_rho_trk = 180;
1174 lock_count_thr = 8;
1175 break;
1176 case STB0899_QPSK_35:
1177 gamma_acq = 38;
1178 gamma_rho_acq = 7182;
1179 gamma_trk = 14;
1180 gamma_rho_trk = 308;
1181 lock_count_thr = 8;
1182 break;
1183 case STB0899_QPSK_23:
1184 gamma_acq = 42;
1185 gamma_rho_acq = 9408;
1186 gamma_trk = 17;
1187 gamma_rho_trk = 476;
1188 lock_count_thr = 8;
1189 break;
1190 case STB0899_QPSK_34:
1191 gamma_acq = 53;
1192 gamma_rho_acq = 16642;
1193 gamma_trk = 19;
1194 gamma_rho_trk = 646;
1195 lock_count_thr = 8;
1196 break;
1197 case STB0899_QPSK_45:
1198 gamma_acq = 53;
1199 gamma_rho_acq = 17119;
1200 gamma_trk = 22;
1201 gamma_rho_trk = 880;
1202 lock_count_thr = 8;
1203 break;
1204 case STB0899_QPSK_56:
1205 gamma_acq = 55;
1206 gamma_rho_acq = 19250;
1207 gamma_trk = 23;
1208 gamma_rho_trk = 989;
1209 lock_count_thr = 8;
1210 break;
1211 case STB0899_QPSK_89:
1212 gamma_acq = 60;
1213 gamma_rho_acq = 24240;
1214 gamma_trk = 24;
1215 gamma_rho_trk = 1176;
1216 lock_count_thr = 8;
1217 break;
1218 case STB0899_QPSK_910:
1219 gamma_acq = 66;
1220 gamma_rho_acq = 29634;
1221 gamma_trk = 24;
1222 gamma_rho_trk = 1176;
1223 lock_count_thr = 8;
1224 break;
1225 default:
1226 gamma_acq = 66;
1227 gamma_rho_acq = 29634;
1228 gamma_trk = 24;
1229 gamma_rho_trk = 1176;
1230 lock_count_thr = 8;
1231 break;
1232 }
1233
1234 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1235 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1236 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1237
1238 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1239 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1240 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1241 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1242
1243 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1244 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1245 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1246 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1247 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1248 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1249 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1250 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1251 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1252 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1253 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1254
1255 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1256 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1257 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1258 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1259 }
1260}
1261
1262/*
1263 * stb0899_dvbs2_get_srate
1264 * get DVB-S2 Symbol Rate
1265 */
1266static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1267{
1268 struct stb0899_internal *internal = &state->internal;
1269 struct stb0899_config *config = state->config;
1270
1271 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1272 int div1, div2, rem1, rem2;
1273
1274 div1 = config->btr_nco_bits / 2;
1275 div2 = config->btr_nco_bits - div1 - 1;
1276
1277 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1278
1279 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1280 decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1281 decimRate = (1 << decimRate);
1282
1283 intval1 = internal->master_clk / (1 << div1);
1284 intval2 = bTrNomFreq / (1 << div2);
1285
1286 rem1 = internal->master_clk % (1 << div1);
1287 rem2 = bTrNomFreq % (1 << div2);
1288 /* only for integer calculation */
1289 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1290 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1291
1292 return srate;
1293}
1294
1295/*
1296 * stb0899_dvbs2_algo
1297 * Search for signal, timing, carrier and data for a given
1298 * frequency in a given range
1299 */
1300enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1301{
1302 struct stb0899_internal *internal = &state->internal;
1303 enum stb0899_modcod modcod;
1304
1305 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1306 int i = 0;
1307 u32 reg, csm1;
1308
1309 if (internal->srate <= 2000000) {
1310 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
1311 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
1312 } else if (internal->srate <= 5000000) {
1313 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
1314 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
1315 } else if (internal->srate <= 10000000) {
1316 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
1317 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
1318 } else if (internal->srate <= 15000000) {
1319 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
1320 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
1321 } else if (internal->srate <= 20000000) {
1322 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
1323 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
1324 } else if (internal->srate <= 25000000) {
1325 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
1326 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1327 } else {
1328 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
1329 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1330 }
1331
1332 /* Maintain Stream Merger in reset during acquisition */
1333 reg = stb0899_read_reg(state, STB0899_TSTRES);
1334 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1335 stb0899_write_reg(state, STB0899_TSTRES, reg);
1336
1337 /* enable tuner I/O */
1338 stb0899_i2c_gate_ctrl(&state->frontend, 1);
1339
1340 /* Move tuner to frequency */
1341 if (state->config->tuner_set_frequency)
1342 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1343 if (state->config->tuner_get_frequency)
1344 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1345
1346 /* disable tuner I/O */
1347 stb0899_i2c_gate_ctrl(&state->frontend, 0);
1348
1349 /* Set IF AGC to acquisition */
1350 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1351 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
1352 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1353 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1354
1355 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1356 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1357 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1358
1359 /* Initialisation */
1360 stb0899_dvbs2_init_calc(state);
1361
1362 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1363 switch (internal->inversion) {
1364 case IQ_SWAP_OFF:
1365 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1366 break;
1367 case IQ_SWAP_ON:
1368 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1369 break;
1370 case IQ_SWAP_AUTO: /* use last successful search first */
1371 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1372 break;
1373 }
1374 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1375 stb0899_dvbs2_reacquire(state);
1376
1377 /* Wait for demod lock (UWP and CSM) */
1378 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1379
1380 if (internal->status == DVBS2_DEMOD_LOCK) {
1381 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1382 i = 0;
1383 /* Demod Locked, check FEC status */
1384 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1385
1386 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1387 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1388 /* Read the frequency offset*/
1389 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1390
1391 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1392 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1393 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1394 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1395 stb0899_dvbs2_reacquire(state);
1396 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1397 i++;
1398 }
1399 }
1400
1401 if (internal->status != DVBS2_FEC_LOCK) {
1402 if (internal->inversion == IQ_SWAP_AUTO) {
1403 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1404 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1405 /* IQ Spectrum Inversion */
1406 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1407 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1408 /* start acquistion process */
1409 stb0899_dvbs2_reacquire(state);
1410
1411 /* Wait for demod lock (UWP and CSM) */
1412 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1413 if (internal->status == DVBS2_DEMOD_LOCK) {
1414 i = 0;
1415 /* Demod Locked, check FEC */
1416 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1417 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */
1418 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1419 /* Read the frequency offset*/
1420 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1421
1422 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1423 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1424 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1425 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1426
1427 stb0899_dvbs2_reacquire(state);
1428 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1429 i++;
1430 }
1431 }
1432/*
1433 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1434 pParams->IQLocked = !iqSpectrum;
1435*/
1436 }
1437 }
1438 if (internal->status == DVBS2_FEC_LOCK) {
1439 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1440 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1441 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1442 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1443
1444 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1445 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1446 (pilots == 1)) {
1447
1448 stb0899_dvbs2_init_csm(state, pilots, modcod);
1449 /* Wait for UWP,CSM and data LOCK 20ms max */
1450 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1451
1452 i = 0;
1453 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1454 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1455 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1456 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1457 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1458 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1459 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1460
1461 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1462 i++;
1463 }
1464 }
1465
1466 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1467 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1468 (pilots == 1)) {
1469
1470 /* Equalizer Disable update */
1471 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1472 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1473 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1474 }
1475
1476 /* slow down the Equalizer once locked */
1477 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1478 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1479 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1480
1481 /* Store signal parameters */
1482 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1483
1484 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1485 offsetfreq *= (internal->master_clk / 1000000);
1486 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1487 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1488 offsetfreq *= -1;
1489
1490 internal->freq = internal->freq - offsetfreq;
1491 internal->srate = stb0899_dvbs2_get_srate(state);
1492
1493 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1494 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1495 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1496 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1497
1498 /* Set IF AGC to tracking */
1499 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1500 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
1501
1502 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1503 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1504 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1505
1506 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1507
1508 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1509 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1510 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1511 }
1512
1513 /* Release Stream Merger Reset */
1514 reg = stb0899_read_reg(state, STB0899_TSTRES);
1515 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1516 stb0899_write_reg(state, STB0899_TSTRES, reg);
1517
1518 return internal->status;
1519}
diff --git a/drivers/media/dvb/frontends/stb0899_cfg.h b/drivers/media/dvb/frontends/stb0899_cfg.h
new file mode 100644
index 000000000000..0867906d3ff3
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_cfg.h
@@ -0,0 +1,287 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STB0899_CFG_H
23#define __STB0899_CFG_H
24
25static const struct stb0899_s2_reg stb0899_s2_init_2[] = {
26
27 { STB0899_OFF0_DMD_STATUS , STB0899_BASE_DMD_STATUS , 0x00000103 }, /* DMDSTATUS */
28 { STB0899_OFF0_CRL_FREQ , STB0899_BASE_CRL_FREQ , 0x3ed1da56 }, /* CRLFREQ */
29 { STB0899_OFF0_BTR_FREQ , STB0899_BASE_BTR_FREQ , 0x00004000 }, /* BTRFREQ */
30 { STB0899_OFF0_IF_AGC_GAIN , STB0899_BASE_IF_AGC_GAIN , 0x00002ade }, /* IFAGCGAIN */
31 { STB0899_OFF0_BB_AGC_GAIN , STB0899_BASE_BB_AGC_GAIN , 0x000001bc }, /* BBAGCGAIN */
32 { STB0899_OFF0_DC_OFFSET , STB0899_BASE_DC_OFFSET , 0x00000200 }, /* DCOFFSET */
33 { STB0899_OFF0_DMD_CNTRL , STB0899_BASE_DMD_CNTRL , 0x0000000f }, /* DMDCNTRL */
34
35 { STB0899_OFF0_IF_AGC_CNTRL , STB0899_BASE_IF_AGC_CNTRL , 0x03fb4a20 }, /* IFAGCCNTRL */
36 { STB0899_OFF0_BB_AGC_CNTRL , STB0899_BASE_BB_AGC_CNTRL , 0x00200c97 }, /* BBAGCCNTRL */
37
38 { STB0899_OFF0_CRL_CNTRL , STB0899_BASE_CRL_CNTRL , 0x00000016 }, /* CRLCNTRL */
39 { STB0899_OFF0_CRL_PHS_INIT , STB0899_BASE_CRL_PHS_INIT , 0x00000000 }, /* CRLPHSINIT */
40 { STB0899_OFF0_CRL_FREQ_INIT , STB0899_BASE_CRL_FREQ_INIT , 0x00000000 }, /* CRLFREQINIT */
41 { STB0899_OFF0_CRL_LOOP_GAIN , STB0899_BASE_CRL_LOOP_GAIN , 0x00000000 }, /* CRLLOOPGAIN */
42 { STB0899_OFF0_CRL_NOM_FREQ , STB0899_BASE_CRL_NOM_FREQ , 0x3ed097b6 }, /* CRLNOMFREQ */
43 { STB0899_OFF0_CRL_SWP_RATE , STB0899_BASE_CRL_SWP_RATE , 0x00000000 }, /* CRLSWPRATE */
44 { STB0899_OFF0_CRL_MAX_SWP , STB0899_BASE_CRL_MAX_SWP , 0x00000000 }, /* CRLMAXSWP */
45 { STB0899_OFF0_CRL_LK_CNTRL , STB0899_BASE_CRL_LK_CNTRL , 0x0f6cdc01 }, /* CRLLKCNTRL */
46 { STB0899_OFF0_DECIM_CNTRL , STB0899_BASE_DECIM_CNTRL , 0x00000000 }, /* DECIMCNTRL */
47 { STB0899_OFF0_BTR_CNTRL , STB0899_BASE_BTR_CNTRL , 0x00003993 }, /* BTRCNTRL */
48 { STB0899_OFF0_BTR_LOOP_GAIN , STB0899_BASE_BTR_LOOP_GAIN , 0x000d3c6f }, /* BTRLOOPGAIN */
49 { STB0899_OFF0_BTR_PHS_INIT , STB0899_BASE_BTR_PHS_INIT , 0x00000000 }, /* BTRPHSINIT */
50 { STB0899_OFF0_BTR_FREQ_INIT , STB0899_BASE_BTR_FREQ_INIT , 0x00000000 }, /* BTRFREQINIT */
51 { STB0899_OFF0_BTR_NOM_FREQ , STB0899_BASE_BTR_NOM_FREQ , 0x0238e38e }, /* BTRNOMFREQ */
52 { STB0899_OFF0_BTR_LK_CNTRL , STB0899_BASE_BTR_LK_CNTRL , 0x00000000 }, /* BTRLKCNTRL */
53 { STB0899_OFF0_DECN_CNTRL , STB0899_BASE_DECN_CNTRL , 0x00000000 }, /* DECNCNTRL */
54 { STB0899_OFF0_TP_CNTRL , STB0899_BASE_TP_CNTRL , 0x00000000 }, /* TPCNTRL */
55 { STB0899_OFF0_TP_BUF_STATUS , STB0899_BASE_TP_BUF_STATUS , 0x00000000 }, /* TPBUFSTATUS */
56 { STB0899_OFF0_DC_ESTIM , STB0899_BASE_DC_ESTIM , 0x00000000 }, /* DCESTIM */
57 { STB0899_OFF0_FLL_CNTRL , STB0899_BASE_FLL_CNTRL , 0x00000000 }, /* FLLCNTRL */
58 { STB0899_OFF0_FLL_FREQ_WD , STB0899_BASE_FLL_FREQ_WD , 0x40070000 }, /* FLLFREQWD */
59 { STB0899_OFF0_ANTI_ALIAS_SEL , STB0899_BASE_ANTI_ALIAS_SEL , 0x00000001 }, /* ANTIALIASSEL */
60 { STB0899_OFF0_RRC_ALPHA , STB0899_BASE_RRC_ALPHA , 0x00000002 }, /* RRCALPHA */
61 { STB0899_OFF0_DC_ADAPT_LSHFT , STB0899_BASE_DC_ADAPT_LSHFT , 0x00000000 }, /* DCADAPTISHFT */
62 { STB0899_OFF0_IMB_OFFSET , STB0899_BASE_IMB_OFFSET , 0x0000fe01 }, /* IMBOFFSET */
63 { STB0899_OFF0_IMB_ESTIMATE , STB0899_BASE_IMB_ESTIMATE , 0x00000000 }, /* IMBESTIMATE */
64 { STB0899_OFF0_IMB_CNTRL , STB0899_BASE_IMB_CNTRL , 0x00000001 }, /* IMBCNTRL */
65 { STB0899_OFF0_IF_AGC_CNTRL2 , STB0899_BASE_IF_AGC_CNTRL2 , 0x00005007 }, /* IFAGCCNTRL2 */
66 { STB0899_OFF0_DMD_CNTRL2 , STB0899_BASE_DMD_CNTRL2 , 0x00000002 }, /* DMDCNTRL2 */
67 { STB0899_OFF0_TP_BUFFER , STB0899_BASE_TP_BUFFER , 0x00000000 }, /* TPBUFFER */
68 { STB0899_OFF0_TP_BUFFER1 , STB0899_BASE_TP_BUFFER1 , 0x00000000 }, /* TPBUFFER1 */
69 { STB0899_OFF0_TP_BUFFER2 , STB0899_BASE_TP_BUFFER2 , 0x00000000 }, /* TPBUFFER2 */
70 { STB0899_OFF0_TP_BUFFER3 , STB0899_BASE_TP_BUFFER3 , 0x00000000 }, /* TPBUFFER3 */
71 { STB0899_OFF0_TP_BUFFER4 , STB0899_BASE_TP_BUFFER4 , 0x00000000 }, /* TPBUFFER4 */
72 { STB0899_OFF0_TP_BUFFER5 , STB0899_BASE_TP_BUFFER5 , 0x00000000 }, /* TPBUFFER5 */
73 { STB0899_OFF0_TP_BUFFER6 , STB0899_BASE_TP_BUFFER6 , 0x00000000 }, /* TPBUFFER6 */
74 { STB0899_OFF0_TP_BUFFER7 , STB0899_BASE_TP_BUFFER7 , 0x00000000 }, /* TPBUFFER7 */
75 { STB0899_OFF0_TP_BUFFER8 , STB0899_BASE_TP_BUFFER8 , 0x00000000 }, /* TPBUFFER8 */
76 { STB0899_OFF0_TP_BUFFER9 , STB0899_BASE_TP_BUFFER9 , 0x00000000 }, /* TPBUFFER9 */
77 { STB0899_OFF0_TP_BUFFER10 , STB0899_BASE_TP_BUFFER10 , 0x00000000 }, /* TPBUFFER10 */
78 { STB0899_OFF0_TP_BUFFER11 , STB0899_BASE_TP_BUFFER11 , 0x00000000 }, /* TPBUFFER11 */
79 { STB0899_OFF0_TP_BUFFER12 , STB0899_BASE_TP_BUFFER12 , 0x00000000 }, /* TPBUFFER12 */
80 { STB0899_OFF0_TP_BUFFER13 , STB0899_BASE_TP_BUFFER13 , 0x00000000 }, /* TPBUFFER13 */
81 { STB0899_OFF0_TP_BUFFER14 , STB0899_BASE_TP_BUFFER14 , 0x00000000 }, /* TPBUFFER14 */
82 { STB0899_OFF0_TP_BUFFER15 , STB0899_BASE_TP_BUFFER15 , 0x00000000 }, /* TPBUFFER15 */
83 { STB0899_OFF0_TP_BUFFER16 , STB0899_BASE_TP_BUFFER16 , 0x0000ff00 }, /* TPBUFFER16 */
84 { STB0899_OFF0_TP_BUFFER17 , STB0899_BASE_TP_BUFFER17 , 0x00000100 }, /* TPBUFFER17 */
85 { STB0899_OFF0_TP_BUFFER18 , STB0899_BASE_TP_BUFFER18 , 0x0000fe01 }, /* TPBUFFER18 */
86 { STB0899_OFF0_TP_BUFFER19 , STB0899_BASE_TP_BUFFER19 , 0x000004fe }, /* TPBUFFER19 */
87 { STB0899_OFF0_TP_BUFFER20 , STB0899_BASE_TP_BUFFER20 , 0x0000cfe7 }, /* TPBUFFER20 */
88 { STB0899_OFF0_TP_BUFFER21 , STB0899_BASE_TP_BUFFER21 , 0x0000bec6 }, /* TPBUFFER21 */
89 { STB0899_OFF0_TP_BUFFER22 , STB0899_BASE_TP_BUFFER22 , 0x0000c2bf }, /* TPBUFFER22 */
90 { STB0899_OFF0_TP_BUFFER23 , STB0899_BASE_TP_BUFFER23 , 0x0000c1c1 }, /* TPBUFFER23 */
91 { STB0899_OFF0_TP_BUFFER24 , STB0899_BASE_TP_BUFFER24 , 0x0000c1c1 }, /* TPBUFFER24 */
92 { STB0899_OFF0_TP_BUFFER25 , STB0899_BASE_TP_BUFFER25 , 0x0000c1c1 }, /* TPBUFFER25 */
93 { STB0899_OFF0_TP_BUFFER26 , STB0899_BASE_TP_BUFFER26 , 0x0000c1c1 }, /* TPBUFFER26 */
94 { STB0899_OFF0_TP_BUFFER27 , STB0899_BASE_TP_BUFFER27 , 0x0000c1c0 }, /* TPBUFFER27 */
95 { STB0899_OFF0_TP_BUFFER28 , STB0899_BASE_TP_BUFFER28 , 0x0000c0c0 }, /* TPBUFFER28 */
96 { STB0899_OFF0_TP_BUFFER29 , STB0899_BASE_TP_BUFFER29 , 0x0000c1c1 }, /* TPBUFFER29 */
97 { STB0899_OFF0_TP_BUFFER30 , STB0899_BASE_TP_BUFFER30 , 0x0000c1c1 }, /* TPBUFFER30 */
98 { STB0899_OFF0_TP_BUFFER31 , STB0899_BASE_TP_BUFFER31 , 0x0000c0c1 }, /* TPBUFFER31 */
99 { STB0899_OFF0_TP_BUFFER32 , STB0899_BASE_TP_BUFFER32 , 0x0000c0c1 }, /* TPBUFFER32 */
100 { STB0899_OFF0_TP_BUFFER33 , STB0899_BASE_TP_BUFFER33 , 0x0000c1c1 }, /* TPBUFFER33 */
101 { STB0899_OFF0_TP_BUFFER34 , STB0899_BASE_TP_BUFFER34 , 0x0000c1c1 }, /* TPBUFFER34 */
102 { STB0899_OFF0_TP_BUFFER35 , STB0899_BASE_TP_BUFFER35 , 0x0000c0c1 }, /* TPBUFFER35 */
103 { STB0899_OFF0_TP_BUFFER36 , STB0899_BASE_TP_BUFFER36 , 0x0000c1c1 }, /* TPBUFFER36 */
104 { STB0899_OFF0_TP_BUFFER37 , STB0899_BASE_TP_BUFFER37 , 0x0000c0c1 }, /* TPBUFFER37 */
105 { STB0899_OFF0_TP_BUFFER38 , STB0899_BASE_TP_BUFFER38 , 0x0000c1c1 }, /* TPBUFFER38 */
106 { STB0899_OFF0_TP_BUFFER39 , STB0899_BASE_TP_BUFFER39 , 0x0000c0c0 }, /* TPBUFFER39 */
107 { STB0899_OFF0_TP_BUFFER40 , STB0899_BASE_TP_BUFFER40 , 0x0000c1c0 }, /* TPBUFFER40 */
108 { STB0899_OFF0_TP_BUFFER41 , STB0899_BASE_TP_BUFFER41 , 0x0000c1c1 }, /* TPBUFFER41 */
109 { STB0899_OFF0_TP_BUFFER42 , STB0899_BASE_TP_BUFFER42 , 0x0000c0c0 }, /* TPBUFFER42 */
110 { STB0899_OFF0_TP_BUFFER43 , STB0899_BASE_TP_BUFFER43 , 0x0000c1c0 }, /* TPBUFFER43 */
111 { STB0899_OFF0_TP_BUFFER44 , STB0899_BASE_TP_BUFFER44 , 0x0000c0c1 }, /* TPBUFFER44 */
112 { STB0899_OFF0_TP_BUFFER45 , STB0899_BASE_TP_BUFFER45 , 0x0000c1be }, /* TPBUFFER45 */
113 { STB0899_OFF0_TP_BUFFER46 , STB0899_BASE_TP_BUFFER46 , 0x0000c1c9 }, /* TPBUFFER46 */
114 { STB0899_OFF0_TP_BUFFER47 , STB0899_BASE_TP_BUFFER47 , 0x0000c0da }, /* TPBUFFER47 */
115 { STB0899_OFF0_TP_BUFFER48 , STB0899_BASE_TP_BUFFER48 , 0x0000c0ba }, /* TPBUFFER48 */
116 { STB0899_OFF0_TP_BUFFER49 , STB0899_BASE_TP_BUFFER49 , 0x0000c1c4 }, /* TPBUFFER49 */
117 { STB0899_OFF0_TP_BUFFER50 , STB0899_BASE_TP_BUFFER50 , 0x0000c1bf }, /* TPBUFFER50 */
118 { STB0899_OFF0_TP_BUFFER51 , STB0899_BASE_TP_BUFFER51 , 0x0000c0c1 }, /* TPBUFFER51 */
119 { STB0899_OFF0_TP_BUFFER52 , STB0899_BASE_TP_BUFFER52 , 0x0000c1c0 }, /* TPBUFFER52 */
120 { STB0899_OFF0_TP_BUFFER53 , STB0899_BASE_TP_BUFFER53 , 0x0000c0c1 }, /* TPBUFFER53 */
121 { STB0899_OFF0_TP_BUFFER54 , STB0899_BASE_TP_BUFFER54 , 0x0000c1c1 }, /* TPBUFFER54 */
122 { STB0899_OFF0_TP_BUFFER55 , STB0899_BASE_TP_BUFFER55 , 0x0000c1c1 }, /* TPBUFFER55 */
123 { STB0899_OFF0_TP_BUFFER56 , STB0899_BASE_TP_BUFFER56 , 0x0000c1c1 }, /* TPBUFFER56 */
124 { STB0899_OFF0_TP_BUFFER57 , STB0899_BASE_TP_BUFFER57 , 0x0000c1c1 }, /* TPBUFFER57 */
125 { STB0899_OFF0_TP_BUFFER58 , STB0899_BASE_TP_BUFFER58 , 0x0000c1c1 }, /* TPBUFFER58 */
126 { STB0899_OFF0_TP_BUFFER59 , STB0899_BASE_TP_BUFFER59 , 0x0000c1c1 }, /* TPBUFFER59 */
127 { STB0899_OFF0_TP_BUFFER60 , STB0899_BASE_TP_BUFFER60 , 0x0000c1c1 }, /* TPBUFFER60 */
128 { STB0899_OFF0_TP_BUFFER61 , STB0899_BASE_TP_BUFFER61 , 0x0000c1c1 }, /* TPBUFFER61 */
129 { STB0899_OFF0_TP_BUFFER62 , STB0899_BASE_TP_BUFFER62 , 0x0000c1c1 }, /* TPBUFFER62 */
130 { STB0899_OFF0_TP_BUFFER63 , STB0899_BASE_TP_BUFFER63 , 0x0000c1c0 }, /* TPBUFFER63 */
131 { STB0899_OFF0_RESET_CNTRL , STB0899_BASE_RESET_CNTRL , 0x00000001 }, /* RESETCNTRL */
132 { STB0899_OFF0_ACM_ENABLE , STB0899_BASE_ACM_ENABLE , 0x00005654 }, /* ACMENABLE */
133 { STB0899_OFF0_DESCR_CNTRL , STB0899_BASE_DESCR_CNTRL , 0x00000000 }, /* DESCRCNTRL */
134 { STB0899_OFF0_CSM_CNTRL1 , STB0899_BASE_CSM_CNTRL1 , 0x00020019 }, /* CSMCNTRL1 */
135 { STB0899_OFF0_CSM_CNTRL2 , STB0899_BASE_CSM_CNTRL2 , 0x004b3237 }, /* CSMCNTRL2 */
136 { STB0899_OFF0_CSM_CNTRL3 , STB0899_BASE_CSM_CNTRL3 , 0x0003dd17 }, /* CSMCNTRL3 */
137 { STB0899_OFF0_CSM_CNTRL4 , STB0899_BASE_CSM_CNTRL4 , 0x00008008 }, /* CSMCNTRL4 */
138 { STB0899_OFF0_UWP_CNTRL1 , STB0899_BASE_UWP_CNTRL1 , 0x002a3106 }, /* UWPCNTRL1 */
139 { STB0899_OFF0_UWP_CNTRL2 , STB0899_BASE_UWP_CNTRL2 , 0x0006140a }, /* UWPCNTRL2 */
140 { STB0899_OFF0_UWP_STAT1 , STB0899_BASE_UWP_STAT1 , 0x00008000 }, /* UWPSTAT1 */
141 { STB0899_OFF0_UWP_STAT2 , STB0899_BASE_UWP_STAT2 , 0x00000000 }, /* UWPSTAT2 */
142 { STB0899_OFF0_DMD_STAT2 , STB0899_BASE_DMD_STAT2 , 0x00000000 }, /* DMDSTAT2 */
143 { STB0899_OFF0_FREQ_ADJ_SCALE , STB0899_BASE_FREQ_ADJ_SCALE , 0x00000471 }, /* FREQADJSCALE */
144 { STB0899_OFF0_UWP_CNTRL3 , STB0899_BASE_UWP_CNTRL3 , 0x017b0465 }, /* UWPCNTRL3 */
145 { STB0899_OFF0_SYM_CLK_SEL , STB0899_BASE_SYM_CLK_SEL , 0x00000002 }, /* SYMCLKSEL */
146 { STB0899_OFF0_SOF_SRCH_TO , STB0899_BASE_SOF_SRCH_TO , 0x00196464 }, /* SOFSRCHTO */
147 { STB0899_OFF0_ACQ_CNTRL1 , STB0899_BASE_ACQ_CNTRL1 , 0x00000603 }, /* ACQCNTRL1 */
148 { STB0899_OFF0_ACQ_CNTRL2 , STB0899_BASE_ACQ_CNTRL2 , 0x02046666 }, /* ACQCNTRL2 */
149 { STB0899_OFF0_ACQ_CNTRL3 , STB0899_BASE_ACQ_CNTRL3 , 0x10046583 }, /* ACQCNTRL3 */
150 { STB0899_OFF0_FE_SETTLE , STB0899_BASE_FE_SETTLE , 0x00010404 }, /* FESETTLE */
151 { STB0899_OFF0_AC_DWELL , STB0899_BASE_AC_DWELL , 0x0002aa8a }, /* ACDWELL */
152 { STB0899_OFF0_ACQUIRE_TRIG , STB0899_BASE_ACQUIRE_TRIG , 0x00000000 }, /* ACQUIRETRIG */
153 { STB0899_OFF0_LOCK_LOST , STB0899_BASE_LOCK_LOST , 0x00000001 }, /* LOCKLOST */
154 { STB0899_OFF0_ACQ_STAT1 , STB0899_BASE_ACQ_STAT1 , 0x00000500 }, /* ACQSTAT1 */
155 { STB0899_OFF0_ACQ_TIMEOUT , STB0899_BASE_ACQ_TIMEOUT , 0x0028a0a0 }, /* ACQTIMEOUT */
156 { STB0899_OFF0_ACQ_TIME , STB0899_BASE_ACQ_TIME , 0x00000000 }, /* ACQTIME */
157 { STB0899_OFF0_FINAL_AGC_CNTRL , STB0899_BASE_FINAL_AGC_CNTRL , 0x00800c17 }, /* FINALAGCCNTRL*/
158 { STB0899_OFF0_FINAL_AGC_GAIN , STB0899_BASE_FINAL_AGC_GAIN , 0x00000000 }, /* FINALAGCCGAIN*/
159 { STB0899_OFF0_EQUALIZER_INIT , STB0899_BASE_EQUALIZER_INIT , 0x00000000 }, /* EQUILIZERINIT*/
160 { STB0899_OFF0_EQ_CNTRL , STB0899_BASE_EQ_CNTRL , 0x00054802 }, /* EQCNTL */
161 { STB0899_OFF0_EQ_I_INIT_COEFF_0, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF0 */
162 { STB0899_OFF1_EQ_I_INIT_COEFF_1, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF1 */
163 { STB0899_OFF2_EQ_I_INIT_COEFF_2, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF2 */
164 { STB0899_OFF3_EQ_I_INIT_COEFF_3, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF3 */
165 { STB0899_OFF4_EQ_I_INIT_COEFF_4, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF4 */
166 { STB0899_OFF5_EQ_I_INIT_COEFF_5, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000400 }, /* EQIINITCOEFF5 */
167 { STB0899_OFF6_EQ_I_INIT_COEFF_6, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF6 */
168 { STB0899_OFF7_EQ_I_INIT_COEFF_7, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF7 */
169 { STB0899_OFF8_EQ_I_INIT_COEFF_8, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF8 */
170 { STB0899_OFF9_EQ_I_INIT_COEFF_9, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF9 */
171 { STB0899_OFFa_EQ_I_INIT_COEFF_10,STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF10*/
172 { STB0899_OFF0_EQ_Q_INIT_COEFF_0, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF0 */
173 { STB0899_OFF1_EQ_Q_INIT_COEFF_1, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF1 */
174 { STB0899_OFF2_EQ_Q_INIT_COEFF_2, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF2 */
175 { STB0899_OFF3_EQ_Q_INIT_COEFF_3, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF3 */
176 { STB0899_OFF4_EQ_Q_INIT_COEFF_4, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF4 */
177 { STB0899_OFF5_EQ_Q_INIT_COEFF_5, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF5 */
178 { STB0899_OFF6_EQ_Q_INIT_COEFF_6, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF6 */
179 { STB0899_OFF7_EQ_Q_INIT_COEFF_7, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF7 */
180 { STB0899_OFF8_EQ_Q_INIT_COEFF_8, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF8 */
181 { STB0899_OFF9_EQ_Q_INIT_COEFF_9, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF9 */
182 { STB0899_OFFa_EQ_Q_INIT_COEFF_10,STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF10*/
183 { STB0899_OFF0_EQ_I_OUT_COEFF_0 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT0 */
184 { STB0899_OFF1_EQ_I_OUT_COEFF_1 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT1 */
185 { STB0899_OFF2_EQ_I_OUT_COEFF_2 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT2 */
186 { STB0899_OFF3_EQ_I_OUT_COEFF_3 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT3 */
187 { STB0899_OFF4_EQ_I_OUT_COEFF_4 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT4 */
188 { STB0899_OFF5_EQ_I_OUT_COEFF_5 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT5 */
189 { STB0899_OFF6_EQ_I_OUT_COEFF_6 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT6 */
190 { STB0899_OFF7_EQ_I_OUT_COEFF_7 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT7 */
191 { STB0899_OFF8_EQ_I_OUT_COEFF_8 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT8 */
192 { STB0899_OFF9_EQ_I_OUT_COEFF_9 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT9 */
193 { STB0899_OFFa_EQ_I_OUT_COEFF_10,STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT10*/
194 { STB0899_OFF0_EQ_Q_OUT_COEFF_0 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT0 */
195 { STB0899_OFF1_EQ_Q_OUT_COEFF_1 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT1 */
196 { STB0899_OFF2_EQ_Q_OUT_COEFF_2 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT2 */
197 { STB0899_OFF3_EQ_Q_OUT_COEFF_3 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT3 */
198 { STB0899_OFF4_EQ_Q_OUT_COEFF_4 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT4 */
199 { STB0899_OFF5_EQ_Q_OUT_COEFF_5 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT5 */
200 { STB0899_OFF6_EQ_Q_OUT_COEFF_6 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT6 */
201 { STB0899_OFF7_EQ_Q_OUT_COEFF_7 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT7 */
202 { STB0899_OFF8_EQ_Q_OUT_COEFF_8 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT8 */
203 { STB0899_OFF9_EQ_Q_OUT_COEFF_9 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT9 */
204 { STB0899_OFFa_EQ_Q_OUT_COEFF_10, STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT10*/
205 { 0xffff , 0xffffffff , 0xffffffff },
206};
207static const struct stb0899_s2_reg stb0899_s2_init_4[] = {
208 { STB0899_OFF0_BLOCK_LNGTH , STB0899_BASE_BLOCK_LNGTH , 0x00000008 }, /* BLOCKLNGTH */
209 { STB0899_OFF0_ROW_STR , STB0899_BASE_ROW_STR , 0x000000b4 }, /* ROWSTR */
210 { STB0899_OFF0_BN_END_ADDR , STB0899_BASE_BN_END_ADDR , 0x000004b5 }, /* BNANDADDR */
211 { STB0899_OFF0_CN_END_ADDR , STB0899_BASE_CN_END_ADDR , 0x00000b4b }, /* CNANDADDR */
212 { STB0899_OFF0_INFO_LENGTH , STB0899_BASE_INFO_LENGTH , 0x00000078 }, /* INFOLENGTH */
213 { STB0899_OFF0_BOT_ADDR , STB0899_BASE_BOT_ADDR , 0x000001e0 }, /* BOT_ADDR */
214 { STB0899_OFF0_BCH_BLK_LN , STB0899_BASE_BCH_BLK_LN , 0x0000a8c0 }, /* BCHBLKLN */
215 { STB0899_OFF0_BCH_T , STB0899_BASE_BCH_T , 0x0000000c }, /* BCHT */
216 { STB0899_OFF0_CNFG_MODE , STB0899_BASE_CNFG_MODE , 0x00000001 }, /* CNFGMODE */
217 { STB0899_OFF0_LDPC_STAT , STB0899_BASE_LDPC_STAT , 0x0000000d }, /* LDPCSTAT */
218 { STB0899_OFF0_ITER_SCALE , STB0899_BASE_ITER_SCALE , 0x00000040 }, /* ITERSCALE */
219 { STB0899_OFF0_INPUT_MODE , STB0899_BASE_INPUT_MODE , 0x00000000 }, /* INPUTMODE */
220 { STB0899_OFF0_LDPCDECRST , STB0899_BASE_LDPCDECRST , 0x00000000 }, /* LDPCDECRST */
221 { STB0899_OFF0_CLK_PER_BYTE_RW , STB0899_BASE_CLK_PER_BYTE_RW , 0x00000008 }, /* CLKPERBYTE */
222 { STB0899_OFF0_BCH_ERRORS , STB0899_BASE_BCH_ERRORS , 0x00000000 }, /* BCHERRORS */
223 { STB0899_OFF0_LDPC_ERRORS , STB0899_BASE_LDPC_ERRORS , 0x00000000 }, /* LDPCERRORS */
224 { STB0899_OFF0_BCH_MODE , STB0899_BASE_BCH_MODE , 0x00000000 }, /* BCHMODE */
225 { STB0899_OFF0_ERR_ACC_PER , STB0899_BASE_ERR_ACC_PER , 0x00000008 }, /* ERRACCPER */
226 { STB0899_OFF0_BCH_ERR_ACC , STB0899_BASE_BCH_ERR_ACC , 0x00000000 }, /* BCHERRACC */
227 { STB0899_OFF0_FEC_TP_SEL , STB0899_BASE_FEC_TP_SEL , 0x00000000 }, /* FECTPSEL */
228 { 0xffff , 0xffffffff , 0xffffffff },
229};
230
231static const struct stb0899_s1_reg stb0899_s1_init_5[] = {
232 { STB0899_TSTCK , 0x00 },
233 { STB0899_TSTRES , 0x00 },
234 { STB0899_TSTOUT , 0x00 },
235 { STB0899_TSTIN , 0x00 },
236 { STB0899_TSTSYS , 0x00 },
237 { STB0899_TSTCHIP , 0x00 },
238 { STB0899_TSTFREE , 0x00 },
239 { STB0899_TSTI2C , 0x00 },
240 { STB0899_BITSPEEDM , 0x00 },
241 { STB0899_BITSPEEDL , 0x00 },
242 { STB0899_TBUSBIT , 0x00 },
243 { STB0899_TSTDIS , 0x00 },
244 { STB0899_TSTDISRX , 0x00 },
245 { STB0899_TSTJETON , 0x00 },
246 { STB0899_TSTDCADJ , 0x00 },
247 { STB0899_TSTAGC1 , 0x00 },
248 { STB0899_TSTAGC1N , 0x00 },
249 { STB0899_TSTPOLYPH , 0x00 },
250 { STB0899_TSTR , 0x00 },
251 { STB0899_TSTAGC2 , 0x00 },
252 { STB0899_TSTCTL1 , 0x00 },
253 { STB0899_TSTCTL2 , 0x00 },
254 { STB0899_TSTCTL3 , 0x00 },
255 { STB0899_TSTDEMAP , 0x00 },
256 { STB0899_TSTDEMAP2 , 0x00 },
257 { STB0899_TSTDEMMON , 0x00 },
258 { STB0899_TSTRATE , 0x00 },
259 { STB0899_TSTSELOUT , 0x00 },
260 { STB0899_TSYNC , 0x00 },
261 { STB0899_TSTERR , 0x00 },
262 { STB0899_TSTRAM1 , 0x00 },
263 { STB0899_TSTVSELOUT , 0x00 },
264 { STB0899_TSTFORCEIN , 0x00 },
265 { STB0899_TSTRS1 , 0x00 },
266 { STB0899_TSTRS2 , 0x00 },
267 { STB0899_TSTRS3 , 0x00 },
268 { STB0899_GHOSTREG , 0x81 },
269 { 0xffff , 0xff },
270};
271
272#define STB0899_DVBS2_ESNO_AVE 3
273#define STB0899_DVBS2_ESNO_QUANT 32
274#define STB0899_DVBS2_AVFRAMES_COARSE 10
275#define STB0899_DVBS2_AVFRAMES_FINE 20
276#define STB0899_DVBS2_MISS_THRESHOLD 6
277#define STB0899_DVBS2_UWP_THRESHOLD_ACQ 1125
278#define STB0899_DVBS2_UWP_THRESHOLD_TRACK 758
279#define STB0899_DVBS2_UWP_THRESHOLD_SOF 1350
280#define STB0899_DVBS2_SOF_SEARCH_TIMEOUT 1664100
281
282#define STB0899_DVBS2_BTR_NCO_BITS 28
283#define STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET 15
284#define STB0899_DVBS2_CRL_NCO_BITS 30
285#define STB0899_DVBS2_LDPC_MAX_ITER 70
286
287#endif //__STB0899_CFG_H
diff --git a/drivers/media/dvb/frontends/stb0899_drv.c b/drivers/media/dvb/frontends/stb0899_drv.c
new file mode 100644
index 000000000000..528820170228
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_drv.c
@@ -0,0 +1,1684 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26
27#include <linux/dvb/frontend.h>
28#include "dvb_frontend.h"
29
30#include "stb0899_drv.h"
31#include "stb0899_priv.h"
32#include "stb0899_reg.h"
33
34static unsigned int verbose = 0;//1;
35module_param(verbose, int, 0644);
36
37/* C/N in dB/10, NIRM/NIRL */
38static const struct stb0899_tab stb0899_cn_tab[] = {
39 { 200, 2600 },
40 { 190, 2700 },
41 { 180, 2860 },
42 { 170, 3020 },
43 { 160, 3210 },
44 { 150, 3440 },
45 { 140, 3710 },
46 { 130, 4010 },
47 { 120, 4360 },
48 { 110, 4740 },
49 { 100, 5190 },
50 { 90, 5670 },
51 { 80, 6200 },
52 { 70, 6770 },
53 { 60, 7360 },
54 { 50, 7970 },
55 { 40, 8250 },
56 { 30, 9000 },
57 { 20, 9450 },
58 { 15, 9600 },
59};
60
61/* DVB-S AGCIQ_VALUE vs. signal level in dBm/10.
62 * As measured, connected to a modulator.
63 * -8.0 to -50.0 dBm directly connected,
64 * -52.0 to -74.8 with extra attenuation.
65 * Cut-off to AGCIQ_VALUE = 0x80 below -74.8dBm.
66 * Crude linear extrapolation below -84.8dBm and above -8.0dBm.
67 */
68static const struct stb0899_tab stb0899_dvbsrf_tab[] = {
69 { -950, -128 },
70 { -748, -94 },
71 { -745, -92 },
72 { -735, -90 },
73 { -720, -87 },
74 { -670, -77 },
75 { -640, -70 },
76 { -610, -62 },
77 { -600, -60 },
78 { -590, -56 },
79 { -560, -41 },
80 { -540, -25 },
81 { -530, -17 },
82 { -520, -11 },
83 { -500, 1 },
84 { -490, 6 },
85 { -480, 10 },
86 { -440, 22 },
87 { -420, 27 },
88 { -400, 31 },
89 { -380, 34 },
90 { -340, 40 },
91 { -320, 43 },
92 { -280, 48 },
93 { -250, 52 },
94 { -230, 55 },
95 { -180, 61 },
96 { -140, 66 },
97 { -90, 73 },
98 { -80, 74 },
99 { 500, 127 }
100};
101
102/* DVB-S2 IF_AGC_GAIN vs. signal level in dBm/10.
103 * As measured, connected to a modulator.
104 * -8.0 to -50.1 dBm directly connected,
105 * -53.0 to -76.6 with extra attenuation.
106 * Cut-off to IF_AGC_GAIN = 0x3fff below -76.6dBm.
107 * Crude linear extrapolation below -76.6dBm and above -8.0dBm.
108 */
109static const struct stb0899_tab stb0899_dvbs2rf_tab[] = {
110 { 700, 0 },
111 { -80, 3217 },
112 { -150, 3893 },
113 { -190, 4217 },
114 { -240, 4621 },
115 { -280, 4945 },
116 { -320, 5273 },
117 { -350, 5545 },
118 { -370, 5741 },
119 { -410, 6147 },
120 { -450, 6671 },
121 { -490, 7413 },
122 { -501, 7665 },
123 { -530, 8767 },
124 { -560, 10219 },
125 { -580, 10939 },
126 { -590, 11518 },
127 { -600, 11723 },
128 { -650, 12659 },
129 { -690, 13219 },
130 { -730, 13645 },
131 { -750, 13909 },
132 { -766, 14153 },
133 { -999, 16383 }
134};
135
136/* DVB-S2 Es/N0 quant in dB/100 vs read value * 100*/
137struct stb0899_tab stb0899_quant_tab[] = {
138 { 0, 0 },
139 { 0, 100 },
140 { 600, 200 },
141 { 950, 299 },
142 { 1200, 398 },
143 { 1400, 501 },
144 { 1560, 603 },
145 { 1690, 700 },
146 { 1810, 804 },
147 { 1910, 902 },
148 { 2000, 1000 },
149 { 2080, 1096 },
150 { 2160, 1202 },
151 { 2230, 1303 },
152 { 2350, 1496 },
153 { 2410, 1603 },
154 { 2460, 1698 },
155 { 2510, 1799 },
156 { 2600, 1995 },
157 { 2650, 2113 },
158 { 2690, 2213 },
159 { 2720, 2291 },
160 { 2760, 2399 },
161 { 2800, 2512 },
162 { 2860, 2692 },
163 { 2930, 2917 },
164 { 2960, 3020 },
165 { 3010, 3199 },
166 { 3040, 3311 },
167 { 3060, 3388 },
168 { 3120, 3631 },
169 { 3190, 3936 },
170 { 3400, 5012 },
171 { 3610, 6383 },
172 { 3800, 7943 },
173 { 4210, 12735 },
174 { 4500, 17783 },
175 { 4690, 22131 },
176 { 4810, 25410 }
177};
178
179/* DVB-S2 Es/N0 estimate in dB/100 vs read value */
180struct stb0899_tab stb0899_est_tab[] = {
181 { 0, 0 },
182 { 0, 1 },
183 { 301, 2 },
184 { 1204, 16 },
185 { 1806, 64 },
186 { 2408, 256 },
187 { 2709, 512 },
188 { 3010, 1023 },
189 { 3311, 2046 },
190 { 3612, 4093 },
191 { 3823, 6653 },
192 { 3913, 8185 },
193 { 4010, 10233 },
194 { 4107, 12794 },
195 { 4214, 16368 },
196 { 4266, 18450 },
197 { 4311, 20464 },
198 { 4353, 22542 },
199 { 4391, 24604 },
200 { 4425, 26607 },
201 { 4457, 28642 },
202 { 4487, 30690 },
203 { 4515, 32734 },
204 { 4612, 40926 },
205 { 4692, 49204 },
206 { 4816, 65464 },
207 { 4913, 81846 },
208 { 4993, 98401 },
209 { 5060, 114815 },
210 { 5118, 131220 },
211 { 5200, 158489 },
212 { 5300, 199526 },
213 { 5400, 251189 },
214 { 5500, 316228 },
215 { 5600, 398107 },
216 { 5720, 524807 },
217 { 5721, 526017 },
218};
219
220int _stb0899_read_reg(struct stb0899_state *state, unsigned int reg)
221{
222 int ret;
223
224 u8 b0[] = { reg >> 8, reg & 0xff };
225 u8 buf;
226
227 struct i2c_msg msg[] = {
228 {
229 .addr = state->config->demod_address,
230 .flags = 0,
231 .buf = b0,
232 .len = 2
233 },{
234 .addr = state->config->demod_address,
235 .flags = I2C_M_RD,
236 .buf = &buf,
237 .len = 1
238 }
239 };
240
241 ret = i2c_transfer(state->i2c, msg, 2);
242 if (ret != 2) {
243 if (ret != -ERESTARTSYS)
244 dprintk(state->verbose, FE_ERROR, 1,
245 "Read error, Reg=[0x%02x], Status=%d",
246 reg, ret);
247
248 return ret < 0 ? ret : -EREMOTEIO;
249 }
250 if (unlikely(*state->verbose >= FE_DEBUGREG))
251 dprintk(state->verbose, FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
252 reg, buf);
253
254 return (unsigned int)buf;
255}
256
257int stb0899_read_reg(struct stb0899_state *state, unsigned int reg)
258{
259 int result;
260
261 result = _stb0899_read_reg(state, reg);
262 /*
263 * Bug ID 9:
264 * access to 0xf2xx/0xf6xx
265 * must be followed by read from 0xf2ff/0xf6ff.
266 */
267 if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
268 (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
269 _stb0899_read_reg(state, (reg | 0x00ff));
270
271 return result;
272}
273
274u32 _stb0899_read_s2reg(struct stb0899_state *state,
275 u32 stb0899_i2cdev,
276 u32 stb0899_base_addr,
277 u16 stb0899_reg_offset)
278{
279 int status;
280 u32 data;
281 u8 buf[7] = { 0 };
282 u16 tmpaddr;
283
284 u8 buf_0[] = {
285 GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */
286 GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */
287 GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */
288 GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */
289 GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */
290 GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */
291 };
292 u8 buf_1[] = {
293 0x00, /* 0xf3 Reg Offset */
294 0x00, /* 0x44 Reg Offset */
295 };
296
297 struct i2c_msg msg_0 = {
298 .addr = state->config->demod_address,
299 .flags = 0,
300 .buf = buf_0,
301 .len = 6
302 };
303
304 struct i2c_msg msg_1 = {
305 .addr = state->config->demod_address,
306 .flags = 0,
307 .buf = buf_1,
308 .len = 2
309 };
310
311 struct i2c_msg msg_r = {
312 .addr = state->config->demod_address,
313 .flags = I2C_M_RD,
314 .buf = buf,
315 .len = 4
316 };
317
318 tmpaddr = stb0899_reg_offset & 0xff00;
319 if (!(stb0899_reg_offset & 0x8))
320 tmpaddr = stb0899_reg_offset | 0x20;
321
322 buf_1[0] = GETBYTE(tmpaddr, BYTE1);
323 buf_1[1] = GETBYTE(tmpaddr, BYTE0);
324
325 status = i2c_transfer(state->i2c, &msg_0, 1);
326 if (status < 1) {
327 if (status != -ERESTARTSYS)
328 printk(KERN_ERR "%s ERR(1), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
329 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
330
331 goto err;
332 }
333
334 /* Dummy */
335 status = i2c_transfer(state->i2c, &msg_1, 1);
336 if (status < 1)
337 goto err;
338
339 status = i2c_transfer(state->i2c, &msg_r, 1);
340 if (status < 1)
341 goto err;
342
343 buf_1[0] = GETBYTE(stb0899_reg_offset, BYTE1);
344 buf_1[1] = GETBYTE(stb0899_reg_offset, BYTE0);
345
346 /* Actual */
347 status = i2c_transfer(state->i2c, &msg_1, 1);
348 if (status < 1) {
349 if (status != -ERESTARTSYS)
350 printk(KERN_ERR "%s ERR(2), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
351 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
352 goto err;
353 }
354
355 status = i2c_transfer(state->i2c, &msg_r, 1);
356 if (status < 1) {
357 if (status != -ERESTARTSYS)
358 printk(KERN_ERR "%s ERR(3), Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Status=%d\n",
359 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, status);
360 return status < 0 ? status : -EREMOTEIO;
361 }
362
363 data = MAKEWORD32(buf[3], buf[2], buf[1], buf[0]);
364 if (unlikely(*state->verbose >= FE_DEBUGREG))
365 printk(KERN_DEBUG "%s Device=[0x%04x], Base address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n",
366 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, data);
367
368 return data;
369
370err:
371 return status < 0 ? status : -EREMOTEIO;
372}
373
374int stb0899_write_s2reg(struct stb0899_state *state,
375 u32 stb0899_i2cdev,
376 u32 stb0899_base_addr,
377 u16 stb0899_reg_offset,
378 u32 stb0899_data)
379{
380 int status;
381
382 /* Base Address Setup */
383 u8 buf_0[] = {
384 GETBYTE(stb0899_i2cdev, BYTE1), /* 0xf3 S2 Base Address (MSB) */
385 GETBYTE(stb0899_i2cdev, BYTE0), /* 0xfc S2 Base Address (LSB) */
386 GETBYTE(stb0899_base_addr, BYTE0), /* 0x00 Base Address (LSB) */
387 GETBYTE(stb0899_base_addr, BYTE1), /* 0x04 Base Address (LSB) */
388 GETBYTE(stb0899_base_addr, BYTE2), /* 0x00 Base Address (MSB) */
389 GETBYTE(stb0899_base_addr, BYTE3), /* 0x00 Base Address (MSB) */
390 };
391 u8 buf_1[] = {
392 0x00, /* 0xf3 Reg Offset */
393 0x00, /* 0x44 Reg Offset */
394 0x00, /* data */
395 0x00, /* data */
396 0x00, /* data */
397 0x00, /* data */
398 };
399
400 struct i2c_msg msg_0 = {
401 .addr = state->config->demod_address,
402 .flags = 0,
403 .buf = buf_0,
404 .len = 6
405 };
406
407 struct i2c_msg msg_1 = {
408 .addr = state->config->demod_address,
409 .flags = 0,
410 .buf = buf_1,
411 .len = 6
412 };
413
414 buf_1[0] = GETBYTE(stb0899_reg_offset, BYTE1);
415 buf_1[1] = GETBYTE(stb0899_reg_offset, BYTE0);
416 buf_1[2] = GETBYTE(stb0899_data, BYTE0);
417 buf_1[3] = GETBYTE(stb0899_data, BYTE1);
418 buf_1[4] = GETBYTE(stb0899_data, BYTE2);
419 buf_1[5] = GETBYTE(stb0899_data, BYTE3);
420
421 if (unlikely(*state->verbose >= FE_DEBUGREG))
422 printk(KERN_DEBUG "%s Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x]\n",
423 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data);
424
425 status = i2c_transfer(state->i2c, &msg_0, 1);
426 if (unlikely(status < 1)) {
427 if (status != -ERESTARTSYS)
428 printk(KERN_ERR "%s ERR (1), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n",
429 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data, status);
430 goto err;
431 }
432 status = i2c_transfer(state->i2c, &msg_1, 1);
433 if (unlikely(status < 1)) {
434 if (status != -ERESTARTSYS)
435 printk(KERN_ERR "%s ERR (2), Device=[0x%04x], Base Address=[0x%08x], Offset=[0x%04x], Data=[0x%08x], status=%d\n",
436 __func__, stb0899_i2cdev, stb0899_base_addr, stb0899_reg_offset, stb0899_data, status);
437
438 return status < 0 ? status : -EREMOTEIO;
439 }
440
441 return 0;
442
443err:
444 return status < 0 ? status : -EREMOTEIO;
445}
446
447int stb0899_read_regs(struct stb0899_state *state, unsigned int reg, u8 *buf, u32 count)
448{
449 int status;
450
451 u8 b0[] = { reg >> 8, reg & 0xff };
452
453 struct i2c_msg msg[] = {
454 {
455 .addr = state->config->demod_address,
456 .flags = 0,
457 .buf = b0,
458 .len = 2
459 },{
460 .addr = state->config->demod_address,
461 .flags = I2C_M_RD,
462 .buf = buf,
463 .len = count
464 }
465 };
466
467 status = i2c_transfer(state->i2c, msg, 2);
468 if (status != 2) {
469 if (status != -ERESTARTSYS)
470 printk(KERN_ERR "%s Read error, Reg=[0x%04x], Count=%u, Status=%d\n",
471 __func__, reg, count, status);
472 goto err;
473 }
474 /*
475 * Bug ID 9:
476 * access to 0xf2xx/0xf6xx
477 * must be followed by read from 0xf2ff/0xf6ff.
478 */
479 if ((reg != 0xf2ff) && (reg != 0xf6ff) &&
480 (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
481 _stb0899_read_reg(state, (reg | 0x00ff));
482
483 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
484 int i;
485
486 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
487 for (i = 0; i < count; i++) {
488 printk(" %02x", buf[i]);
489 }
490 printk("\n");
491 }
492
493 return 0;
494err:
495 return status < 0 ? status : -EREMOTEIO;
496}
497
498int stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, u32 count)
499{
500 int ret;
501 u8 buf[2 + count];
502 struct i2c_msg i2c_msg = {
503 .addr = state->config->demod_address,
504 .flags = 0,
505 .buf = buf,
506 .len = 2 + count
507 };
508
509 buf[0] = reg >> 8;
510 buf[1] = reg & 0xff;
511 memcpy(&buf[2], data, count);
512
513 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
514 int i;
515
516 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
517 for (i = 0; i < count; i++)
518 printk(" %02x", data[i]);
519 printk("\n");
520 }
521 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
522
523 /*
524 * Bug ID 9:
525 * access to 0xf2xx/0xf6xx
526 * must be followed by read from 0xf2ff/0xf6ff.
527 */
528 if ((((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600)))
529 stb0899_read_reg(state, (reg | 0x00ff));
530
531 if (ret != 1) {
532 if (ret != -ERESTARTSYS)
533 dprintk(state->verbose, FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
534 reg, data[0], count, ret);
535 return ret < 0 ? ret : -EREMOTEIO;
536 }
537
538 return 0;
539}
540
541int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data)
542{
543 return stb0899_write_regs(state, reg, &data, 1);
544}
545
546/*
547 * stb0899_get_mclk
548 * Get STB0899 master clock frequency
549 * ExtClk: external clock frequency (Hz)
550 */
551static u32 stb0899_get_mclk(struct stb0899_state *state)
552{
553 u32 mclk = 0, div = 0;
554
555 div = stb0899_read_reg(state, STB0899_NCOARSE);
556 mclk = (div + 1) * state->config->xtal_freq / 6;
557 dprintk(state->verbose, FE_DEBUG, 1, "div=%d, mclk=%d", div, mclk);
558
559 return mclk;
560}
561
562/*
563 * stb0899_set_mclk
564 * Set STB0899 master Clock frequency
565 * Mclk: demodulator master clock
566 * ExtClk: external clock frequency (Hz)
567 */
568static void stb0899_set_mclk(struct stb0899_state *state, u32 Mclk)
569{
570 struct stb0899_internal *internal = &state->internal;
571 u8 mdiv = 0;
572
573 dprintk(state->verbose, FE_DEBUG, 1, "state->config=%p", state->config);
574 mdiv = ((6 * Mclk) / state->config->xtal_freq) - 1;
575 dprintk(state->verbose, FE_DEBUG, 1, "mdiv=%d", mdiv);
576
577 stb0899_write_reg(state, STB0899_NCOARSE, mdiv);
578 internal->master_clk = stb0899_get_mclk(state);
579
580 dprintk(state->verbose, FE_DEBUG, 1, "MasterCLOCK=%d", internal->master_clk);
581}
582
583static int stb0899_postproc(struct stb0899_state *state, u8 ctl, int enable)
584{
585 struct stb0899_config *config = state->config;
586 const struct stb0899_postproc *postproc = config->postproc;
587
588 /* post process event */
589 if (postproc) {
590 if (enable) {
591 if (postproc[ctl].level == STB0899_GPIOPULLUP)
592 stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
593 else
594 stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
595 } else {
596 if (postproc[ctl].level == STB0899_GPIOPULLUP)
597 stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
598 else
599 stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
600 }
601 }
602 return 0;
603}
604
605static void stb0899_release(struct dvb_frontend *fe)
606{
607 struct stb0899_state *state = fe->demodulator_priv;
608
609 dprintk(state->verbose, FE_DEBUG, 1, "Release Frontend");
610 /* post process event */
611 stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 0);
612 kfree(state);
613}
614
615/*
616 * stb0899_get_alpha
617 * return: rolloff
618 */
619static int stb0899_get_alpha(struct stb0899_state *state)
620{
621 u8 mode_coeff;
622
623 mode_coeff = stb0899_read_reg(state, STB0899_DEMOD);
624
625 if (STB0899_GETFIELD(MODECOEFF, mode_coeff) == 1)
626 return 20;
627 else
628 return 35;
629}
630
631/*
632 * stb0899_init_calc
633 */
634static void stb0899_init_calc(struct stb0899_state *state)
635{
636 struct stb0899_internal *internal = &state->internal;
637 int master_clk;
638 u8 agc[2];
639 u8 agc1cn;
640 u32 reg;
641
642 /* Read registers (in burst mode) */
643 agc1cn = stb0899_read_reg(state, STB0899_AGC1CN);
644 stb0899_read_regs(state, STB0899_AGC1REF, agc, 2); /* AGC1R and AGC2O */
645
646 /* Initial calculations */
647 master_clk = stb0899_get_mclk(state);
648 internal->t_agc1 = 0;
649 internal->t_agc2 = 0;
650 internal->master_clk = master_clk;
651 internal->mclk = master_clk / 65536L;
652 internal->rolloff = stb0899_get_alpha(state);
653
654 /* DVBS2 Initial calculations */
655 /* Set AGC value to the middle */
656 internal->agc_gain = 8154;
657 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
658 STB0899_SETFIELD_VAL(IF_GAIN_INIT, reg, internal->agc_gain);
659 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
660
661 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, RRC_ALPHA);
662 internal->rrc_alpha = STB0899_GETFIELD(RRC_ALPHA, reg);
663
664 internal->center_freq = 0;
665 internal->av_frame_coarse = 10;
666 internal->av_frame_fine = 20;
667 internal->step_size = 2;
668/*
669 if ((pParams->SpectralInv == FE_IQ_NORMAL) || (pParams->SpectralInv == FE_IQ_AUTO))
670 pParams->IQLocked = 0;
671 else
672 pParams->IQLocked = 1;
673*/
674}
675
676static int stb0899_wait_diseqc_fifo_empty(struct stb0899_state *state, int timeout)
677{
678 u8 reg = 0;
679 unsigned long start = jiffies;
680
681 while (1) {
682 reg = stb0899_read_reg(state, STB0899_DISSTATUS);
683 if (!STB0899_GETFIELD(FIFOFULL, reg))
684 break;
685 if ((jiffies - start) > timeout) {
686 dprintk(state->verbose, FE_ERROR, 1, "timed out !!");
687 return -ETIMEDOUT;
688 }
689 }
690
691 return 0;
692}
693
694static int stb0899_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
695{
696 struct stb0899_state *state = fe->demodulator_priv;
697 u8 reg, i;
698
699 if (cmd->msg_len > 8)
700 return -EINVAL;
701
702 /* enable FIFO precharge */
703 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
704 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 1);
705 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
706 for (i = 0; i < cmd->msg_len; i++) {
707 /* wait for FIFO empty */
708 if (stb0899_wait_diseqc_fifo_empty(state, 10) < 0)
709 return -ETIMEDOUT;
710
711 stb0899_write_reg(state, STB0899_DISFIFO, cmd->msg[i]);
712 }
713 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
714 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0);
715 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
716
717 return 0;
718}
719
720static int stb0899_wait_diseqc_rxidle(struct stb0899_state *state, int timeout)
721{
722 u8 reg = 0;
723 unsigned long start = jiffies;
724
725 while (!STB0899_GETFIELD(RXEND, reg)) {
726 reg = stb0899_read_reg(state, STB0899_DISRX_ST0);
727 if (jiffies - start > timeout) {
728 dprintk(state->verbose, FE_ERROR, 1, "timed out!!");
729 return -ETIMEDOUT;
730 }
731 msleep(10);
732 }
733
734 return 0;
735}
736
737static int stb0899_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
738{
739 struct stb0899_state *state = fe->demodulator_priv;
740 u8 reg, length = 0, i;
741 int result;
742
743 if (stb0899_wait_diseqc_rxidle(state, 100) < 0)
744 return -ETIMEDOUT;
745
746 reg = stb0899_read_reg(state, STB0899_DISRX_ST0);
747 if (STB0899_GETFIELD(RXEND, reg)) {
748
749 reg = stb0899_read_reg(state, STB0899_DISRX_ST1);
750 length = STB0899_GETFIELD(FIFOBYTENBR, reg);
751
752 if (length > sizeof (reply->msg)) {
753 result = -EOVERFLOW;
754 goto exit;
755 }
756 reply->msg_len = length;
757
758 /* extract data */
759 for (i = 0; i < length; i++)
760 reply->msg[i] = stb0899_read_reg(state, STB0899_DISFIFO);
761 }
762
763 return 0;
764exit:
765
766 return result;
767}
768
769static int stb0899_wait_diseqc_txidle(struct stb0899_state *state, int timeout)
770{
771 u8 reg = 0;
772 unsigned long start = jiffies;
773
774 while (!STB0899_GETFIELD(TXIDLE, reg)) {
775 reg = stb0899_read_reg(state, STB0899_DISSTATUS);
776 if (jiffies - start > timeout) {
777 dprintk(state->verbose, FE_ERROR, 1, "timed out!!");
778 return -ETIMEDOUT;
779 }
780 msleep(10);
781 }
782 return 0;
783}
784
785static int stb0899_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
786{
787 struct stb0899_state *state = fe->demodulator_priv;
788 u8 reg, old_state;
789
790 /* wait for diseqc idle */
791 if (stb0899_wait_diseqc_txidle(state, 100) < 0)
792 return -ETIMEDOUT;
793
794 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
795 old_state = reg;
796 /* set to burst mode */
797 STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x02);
798 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01);
799 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
800 switch (burst) {
801 case SEC_MINI_A:
802 /* unmodulated */
803 stb0899_write_reg(state, STB0899_DISFIFO, 0x00);
804 break;
805 case SEC_MINI_B:
806 /* modulated */
807 stb0899_write_reg(state, STB0899_DISFIFO, 0xff);
808 break;
809 }
810 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
811 STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x00);
812 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
813 /* wait for diseqc idle */
814 if (stb0899_wait_diseqc_txidle(state, 100) < 0)
815 return -ETIMEDOUT;
816
817 /* restore state */
818 stb0899_write_reg(state, STB0899_DISCNTRL1, old_state);
819
820 return 0;
821}
822
823static int stb0899_diseqc_init(struct stb0899_state *state)
824{
825 struct dvb_diseqc_master_cmd tx_data;
826/*
827 struct dvb_diseqc_slave_reply rx_data;
828*/
829 u8 f22_tx, f22_rx, reg;
830
831 u32 mclk, tx_freq = 22000;/* count = 0, i; */
832 tx_data.msg[0] = 0xe2;
833 tx_data.msg_len = 3;
834 reg = stb0899_read_reg(state, STB0899_DISCNTRL2);
835 STB0899_SETFIELD_VAL(ONECHIP_TRX, reg, 0);
836 stb0899_write_reg(state, STB0899_DISCNTRL2, reg);
837
838 /* disable Tx spy */
839 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
840 STB0899_SETFIELD_VAL(DISEQCRESET, reg, 1);
841 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
842
843 reg = stb0899_read_reg(state, STB0899_DISCNTRL1);
844 STB0899_SETFIELD_VAL(DISEQCRESET, reg, 0);
845 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
846
847 mclk = stb0899_get_mclk(state);
848 f22_tx = mclk / (tx_freq * 32);
849 stb0899_write_reg(state, STB0899_DISF22, f22_tx); /* DiSEqC Tx freq */
850 state->rx_freq = 20000;
851 f22_rx = mclk / (state->rx_freq * 32);
852
853 return 0;
854}
855
856static int stb0899_sleep(struct dvb_frontend *fe)
857{
858 struct stb0899_state *state = fe->demodulator_priv;
859/*
860 u8 reg;
861*/
862 dprintk(state->verbose, FE_DEBUG, 1, "Going to Sleep .. (Really tired .. :-))");
863 /* post process event */
864 stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 0);
865
866 return 0;
867}
868
869static int stb0899_wakeup(struct dvb_frontend *fe)
870{
871 int rc;
872 struct stb0899_state *state = fe->demodulator_priv;
873
874 if ((rc = stb0899_write_reg(state, STB0899_SYNTCTRL, STB0899_SELOSCI)))
875 return rc;
876 /* Activate all clocks; DVB-S2 registers are inaccessible otherwise. */
877 if ((rc = stb0899_write_reg(state, STB0899_STOPCLK1, 0x00)))
878 return rc;
879 if ((rc = stb0899_write_reg(state, STB0899_STOPCLK2, 0x00)))
880 return rc;
881
882 /* post process event */
883 stb0899_postproc(state, STB0899_POSTPROC_GPIO_POWER, 1);
884
885 return 0;
886}
887
888static int stb0899_init(struct dvb_frontend *fe)
889{
890 int i;
891 struct stb0899_state *state = fe->demodulator_priv;
892 struct stb0899_config *config = state->config;
893
894 dprintk(state->verbose, FE_DEBUG, 1, "Initializing STB0899 ... ");
895
896 /* init device */
897 dprintk(state->verbose, FE_DEBUG, 1, "init device");
898 for (i = 0; config->init_dev[i].address != 0xffff; i++)
899 stb0899_write_reg(state, config->init_dev[i].address, config->init_dev[i].data);
900
901 dprintk(state->verbose, FE_DEBUG, 1, "init S2 demod");
902 /* init S2 demod */
903 for (i = 0; config->init_s2_demod[i].offset != 0xffff; i++)
904 stb0899_write_s2reg(state, STB0899_S2DEMOD,
905 config->init_s2_demod[i].base_address,
906 config->init_s2_demod[i].offset,
907 config->init_s2_demod[i].data);
908
909 dprintk(state->verbose, FE_DEBUG, 1, "init S1 demod");
910 /* init S1 demod */
911 for (i = 0; config->init_s1_demod[i].address != 0xffff; i++)
912 stb0899_write_reg(state, config->init_s1_demod[i].address, config->init_s1_demod[i].data);
913
914 dprintk(state->verbose, FE_DEBUG, 1, "init S2 FEC");
915 /* init S2 fec */
916 for (i = 0; config->init_s2_fec[i].offset != 0xffff; i++)
917 stb0899_write_s2reg(state, STB0899_S2FEC,
918 config->init_s2_fec[i].base_address,
919 config->init_s2_fec[i].offset,
920 config->init_s2_fec[i].data);
921
922 dprintk(state->verbose, FE_DEBUG, 1, "init TST");
923 /* init test */
924 for (i = 0; config->init_tst[i].address != 0xffff; i++)
925 stb0899_write_reg(state, config->init_tst[i].address, config->init_tst[i].data);
926
927 stb0899_init_calc(state);
928 stb0899_diseqc_init(state);
929
930 return 0;
931}
932
933static int stb0899_table_lookup(const struct stb0899_tab *tab, int max, int val)
934{
935 int res = 0;
936 int min = 0, med;
937
938 if (val < tab[min].read)
939 res = tab[min].real;
940 else if (val >= tab[max].read)
941 res = tab[max].real;
942 else {
943 while ((max - min) > 1) {
944 med = (max + min) / 2;
945 if (val >= tab[min].read && val < tab[med].read)
946 max = med;
947 else
948 min = med;
949 }
950 res = ((val - tab[min].read) *
951 (tab[max].real - tab[min].real) /
952 (tab[max].read - tab[min].read)) +
953 tab[min].real;
954 }
955
956 return res;
957}
958
959static int stb0899_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
960{
961 struct stb0899_state *state = fe->demodulator_priv;
962 struct stb0899_internal *internal = &state->internal;
963
964 int val;
965 u32 reg;
966 switch (state->delsys) {
967 case SYS_DVBS:
968 case SYS_DSS:
969 if (internal->lock) {
970 reg = stb0899_read_reg(state, STB0899_VSTATUS);
971 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
972
973 reg = stb0899_read_reg(state, STB0899_AGCIQIN);
974 val = (s32)(s8)STB0899_GETFIELD(AGCIQVALUE, reg);
975
976 *strength = stb0899_table_lookup(stb0899_dvbsrf_tab, ARRAY_SIZE(stb0899_dvbsrf_tab) - 1, val);
977 *strength += 750;
978 dprintk(state->verbose, FE_DEBUG, 1, "AGCIQVALUE = 0x%02x, C = %d * 0.1 dBm",
979 val & 0xff, *strength);
980 }
981 }
982 break;
983 case SYS_DVBS2:
984 if (internal->lock) {
985 reg = STB0899_READ_S2REG(STB0899_DEMOD, IF_AGC_GAIN);
986 val = STB0899_GETFIELD(IF_AGC_GAIN, reg);
987
988 *strength = stb0899_table_lookup(stb0899_dvbs2rf_tab, ARRAY_SIZE(stb0899_dvbs2rf_tab) - 1, val);
989 *strength += 750;
990 dprintk(state->verbose, FE_DEBUG, 1, "IF_AGC_GAIN = 0x%04x, C = %d * 0.1 dBm",
991 val & 0x3fff, *strength);
992 }
993 break;
994 default:
995 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
996 return -EINVAL;
997 }
998
999 return 0;
1000}
1001
1002static int stb0899_read_snr(struct dvb_frontend *fe, u16 *snr)
1003{
1004 struct stb0899_state *state = fe->demodulator_priv;
1005 struct stb0899_internal *internal = &state->internal;
1006
1007 unsigned int val, quant, quantn = -1, est, estn = -1;
1008 u8 buf[2];
1009 u32 reg;
1010
1011 reg = stb0899_read_reg(state, STB0899_VSTATUS);
1012 switch (state->delsys) {
1013 case SYS_DVBS:
1014 case SYS_DSS:
1015 if (internal->lock) {
1016 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
1017
1018 stb0899_read_regs(state, STB0899_NIRM, buf, 2);
1019 val = MAKEWORD16(buf[0], buf[1]);
1020
1021 *snr = stb0899_table_lookup(stb0899_cn_tab, ARRAY_SIZE(stb0899_cn_tab) - 1, val);
1022 dprintk(state->verbose, FE_DEBUG, 1, "NIR = 0x%02x%02x = %u, C/N = %d * 0.1 dBm\n",
1023 buf[0], buf[1], val, *snr);
1024 }
1025 }
1026 break;
1027 case SYS_DVBS2:
1028 if (internal->lock) {
1029 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
1030 quant = STB0899_GETFIELD(UWP_ESN0_QUANT, reg);
1031 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1032 est = STB0899_GETFIELD(ESN0_EST, reg);
1033 if (est == 1)
1034 val = 301; /* C/N = 30.1 dB */
1035 else if (est == 2)
1036 val = 270; /* C/N = 27.0 dB */
1037 else {
1038 /* quantn = 100 * log(quant^2) */
1039 quantn = stb0899_table_lookup(stb0899_quant_tab, ARRAY_SIZE(stb0899_quant_tab) - 1, quant * 100);
1040 /* estn = 100 * log(est) */
1041 estn = stb0899_table_lookup(stb0899_est_tab, ARRAY_SIZE(stb0899_est_tab) - 1, est);
1042 /* snr(dBm/10) = -10*(log(est)-log(quant^2)) => snr(dBm/10) = (100*log(quant^2)-100*log(est))/10 */
1043 val = (quantn - estn) / 10;
1044 }
1045 *snr = val;
1046 dprintk(state->verbose, FE_DEBUG, 1, "Es/N0 quant = %d (%d) estimate = %u (%d), C/N = %d * 0.1 dBm",
1047 quant, quantn, est, estn, val);
1048 }
1049 break;
1050 default:
1051 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
1052 return -EINVAL;
1053 }
1054
1055 return 0;
1056}
1057
1058static int stb0899_read_status(struct dvb_frontend *fe, enum fe_status *status)
1059{
1060 struct stb0899_state *state = fe->demodulator_priv;
1061 struct stb0899_internal *internal = &state->internal;
1062 u8 reg;
1063 *status = 0;
1064
1065 switch (state->delsys) {
1066 case SYS_DVBS:
1067 case SYS_DSS:
1068 dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S/DSS");
1069 if (internal->lock) {
1070 reg = stb0899_read_reg(state, STB0899_VSTATUS);
1071 if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) {
1072 dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_CARRIER | FE_HAS_LOCK");
1073 *status |= FE_HAS_CARRIER | FE_HAS_LOCK;
1074
1075 reg = stb0899_read_reg(state, STB0899_PLPARM);
1076 if (STB0899_GETFIELD(VITCURPUN, reg)) {
1077 dprintk(state->verbose, FE_DEBUG, 1, "--------> FE_HAS_VITERBI | FE_HAS_SYNC");
1078 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
1079 /* post process event */
1080 stb0899_postproc(state, STB0899_POSTPROC_GPIO_LOCK, 1);
1081 }
1082 }
1083 }
1084 break;
1085 case SYS_DVBS2:
1086 dprintk(state->verbose, FE_DEBUG, 1, "Delivery system DVB-S2");
1087 if (internal->lock) {
1088 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1089 if (STB0899_GETFIELD(UWP_LOCK, reg) && STB0899_GETFIELD(CSM_LOCK, reg)) {
1090 *status |= FE_HAS_CARRIER;
1091 dprintk(state->verbose, FE_DEBUG, 1,
1092 "UWP & CSM Lock ! ---> DVB-S2 FE_HAS_CARRIER");
1093
1094 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1095 if (STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg)) {
1096 *status |= FE_HAS_LOCK;
1097 dprintk(state->verbose, FE_DEBUG, 1,
1098 "Packet Delineator Locked ! -----> DVB-S2 FE_HAS_LOCK");
1099
1100 }
1101 if (STB0899_GETFIELD(CONTINUOUS_STREAM, reg)) {
1102 *status |= FE_HAS_VITERBI;
1103 dprintk(state->verbose, FE_DEBUG, 1,
1104 "Packet Delineator found VITERBI ! -----> DVB-S2 FE_HAS_VITERBI");
1105 }
1106 if (STB0899_GETFIELD(ACCEPTED_STREAM, reg)) {
1107 *status |= FE_HAS_SYNC;
1108 dprintk(state->verbose, FE_DEBUG, 1,
1109 "Packet Delineator found SYNC ! -----> DVB-S2 FE_HAS_SYNC");
1110 /* post process event */
1111 stb0899_postproc(state, STB0899_POSTPROC_GPIO_LOCK, 1);
1112 }
1113 }
1114 }
1115 break;
1116 default:
1117 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
1118 return -EINVAL;
1119 }
1120 return 0;
1121}
1122
1123/*
1124 * stb0899_get_error
1125 * viterbi error for DVB-S/DSS
1126 * packet error for DVB-S2
1127 * Bit Error Rate or Packet Error Rate * 10 ^ 7
1128 */
1129static int stb0899_read_ber(struct dvb_frontend *fe, u32 *ber)
1130{
1131 struct stb0899_state *state = fe->demodulator_priv;
1132 struct stb0899_internal *internal = &state->internal;
1133
1134 u8 lsb, msb;
1135 u32 i;
1136
1137 *ber = 0;
1138
1139 switch (state->delsys) {
1140 case SYS_DVBS:
1141 case SYS_DSS:
1142 if (internal->lock) {
1143 /* average 5 BER values */
1144 for (i = 0; i < 5; i++) {
1145 msleep(100);
1146 lsb = stb0899_read_reg(state, STB0899_ECNT1L);
1147 msb = stb0899_read_reg(state, STB0899_ECNT1M);
1148 *ber += MAKEWORD16(msb, lsb);
1149 }
1150 *ber /= 5;
1151 /* Viterbi Check */
1152 if (STB0899_GETFIELD(VSTATUS_PRFVIT, internal->v_status)) {
1153 /* Error Rate */
1154 *ber *= 9766;
1155 /* ber = ber * 10 ^ 7 */
1156 *ber /= (-1 + (1 << (2 * STB0899_GETFIELD(NOE, internal->err_ctrl))));
1157 *ber /= 8;
1158 }
1159 }
1160 break;
1161 case SYS_DVBS2:
1162 if (internal->lock) {
1163 /* Average 5 PER values */
1164 for (i = 0; i < 5; i++) {
1165 msleep(100);
1166 lsb = stb0899_read_reg(state, STB0899_ECNT1L);
1167 msb = stb0899_read_reg(state, STB0899_ECNT1M);
1168 *ber += MAKEWORD16(msb, lsb);
1169 }
1170 /* ber = ber * 10 ^ 7 */
1171 *ber *= 10000000;
1172 *ber /= (-1 + (1 << (4 + 2 * STB0899_GETFIELD(NOE, internal->err_ctrl))));
1173 }
1174 break;
1175 default:
1176 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported delivery system");
1177 return -EINVAL;
1178 }
1179
1180 return 0;
1181}
1182
1183static int stb0899_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
1184{
1185 struct stb0899_state *state = fe->demodulator_priv;
1186
1187 switch (voltage) {
1188 case SEC_VOLTAGE_13:
1189 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
1190 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
1191 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x00);
1192 break;
1193 case SEC_VOLTAGE_18:
1194 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x02);
1195 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
1196 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
1197 break;
1198 case SEC_VOLTAGE_OFF:
1199 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
1200 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x82);
1201 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
1202 break;
1203 default:
1204 return -EINVAL;
1205 }
1206
1207 return 0;
1208}
1209
1210static int stb0899_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
1211{
1212 struct stb0899_state *state = fe->demodulator_priv;
1213 struct stb0899_internal *internal = &state->internal;
1214
1215 u8 div, reg;
1216
1217 /* wait for diseqc idle */
1218 if (stb0899_wait_diseqc_txidle(state, 100) < 0)
1219 return -ETIMEDOUT;
1220
1221 switch (tone) {
1222 case SEC_TONE_ON:
1223 div = (internal->master_clk / 100) / 5632;
1224 div = (div + 5) / 10;
1225 stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x66);
1226 reg = stb0899_read_reg(state, STB0899_ACRPRESC);
1227 STB0899_SETFIELD_VAL(ACRPRESC, reg, 0x03);
1228 stb0899_write_reg(state, STB0899_ACRPRESC, reg);
1229 stb0899_write_reg(state, STB0899_ACRDIV1, div);
1230 break;
1231 case SEC_TONE_OFF:
1232 stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x20);
1233 break;
1234 default:
1235 return -EINVAL;
1236 }
1237 return 0;
1238}
1239
1240int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
1241{
1242 int i2c_stat;
1243 struct stb0899_state *state = fe->demodulator_priv;
1244
1245 i2c_stat = stb0899_read_reg(state, STB0899_I2CRPT);
1246 if (i2c_stat < 0)
1247 goto err;
1248
1249 if (enable) {
1250 dprintk(state->verbose, FE_DEBUG, 1, "Enabling I2C Repeater ...");
1251 i2c_stat |= STB0899_I2CTON;
1252 if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
1253 goto err;
1254 } else {
1255 dprintk(state->verbose, FE_DEBUG, 1, "Disabling I2C Repeater ...");
1256 i2c_stat &= ~STB0899_I2CTON;
1257 if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
1258 goto err;
1259 }
1260 return 0;
1261err:
1262 dprintk(state->verbose, FE_ERROR, 1, "I2C Repeater control failed");
1263 return -EREMOTEIO;
1264}
1265
1266
1267static inline void CONVERT32(u32 x, char *str)
1268{
1269 *str++ = (x >> 24) & 0xff;
1270 *str++ = (x >> 16) & 0xff;
1271 *str++ = (x >> 8) & 0xff;
1272 *str++ = (x >> 0) & 0xff;
1273 *str = '\0';
1274}
1275
1276int stb0899_get_dev_id(struct stb0899_state *state)
1277{
1278 u8 chip_id, release;
1279 u16 id;
1280 u32 demod_ver = 0, fec_ver = 0;
1281 char demod_str[5] = { 0 };
1282 char fec_str[5] = { 0 };
1283
1284 id = stb0899_read_reg(state, STB0899_DEV_ID);
1285 dprintk(state->verbose, FE_DEBUG, 1, "ID reg=[0x%02x]", id);
1286 chip_id = STB0899_GETFIELD(CHIP_ID, id);
1287 release = STB0899_GETFIELD(CHIP_REL, id);
1288
1289 dprintk(state->verbose, FE_ERROR, 1, "Device ID=[%d], Release=[%d]",
1290 chip_id, release);
1291
1292 CONVERT32(STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CORE_ID), (char *)&demod_str);
1293
1294 demod_ver = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_VERSION_ID);
1295 dprintk(state->verbose, FE_ERROR, 1, "Demodulator Core ID=[%s], Version=[%d]", (char *) &demod_str, demod_ver);
1296 CONVERT32(STB0899_READ_S2REG(STB0899_S2FEC, FEC_CORE_ID_REG), (char *)&fec_str);
1297 fec_ver = STB0899_READ_S2REG(STB0899_S2FEC, FEC_VER_ID_REG);
1298 if (! (chip_id > 0)) {
1299 dprintk(state->verbose, FE_ERROR, 1, "couldn't find a STB 0899");
1300
1301 return -ENODEV;
1302 }
1303 dprintk(state->verbose, FE_ERROR, 1, "FEC Core ID=[%s], Version=[%d]", (char*) &fec_str, fec_ver);
1304
1305 return 0;
1306}
1307
1308static void stb0899_set_delivery(struct stb0899_state *state)
1309{
1310 u8 reg;
1311 u8 stop_clk[2];
1312
1313 stop_clk[0] = stb0899_read_reg(state, STB0899_STOPCLK1);
1314 stop_clk[1] = stb0899_read_reg(state, STB0899_STOPCLK2);
1315
1316 switch (state->delsys) {
1317 case SYS_DVBS:
1318 dprintk(state->verbose, FE_DEBUG, 1, "Delivery System -- DVB-S");
1319 /* FECM/Viterbi ON */
1320 reg = stb0899_read_reg(state, STB0899_FECM);
1321 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0);
1322 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1);
1323 stb0899_write_reg(state, STB0899_FECM, reg);
1324
1325 stb0899_write_reg(state, STB0899_RSULC, 0xb1);
1326 stb0899_write_reg(state, STB0899_TSULC, 0x40);
1327 stb0899_write_reg(state, STB0899_RSLLC, 0x42);
1328 stb0899_write_reg(state, STB0899_TSLPL, 0x12);
1329
1330 reg = stb0899_read_reg(state, STB0899_TSTRES);
1331 STB0899_SETFIELD_VAL(FRESLDPC, reg, 1);
1332 stb0899_write_reg(state, STB0899_TSTRES, reg);
1333
1334 STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1335 STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 1);
1336 STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 1);
1337
1338 STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 1);
1339 STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 1);
1340
1341 STB0899_SETFIELD_VAL(STOP_CKINTBUF216, stop_clk[0], 1);
1342 STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
1343
1344 STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 1);
1345 break;
1346 case SYS_DVBS2:
1347 /* FECM/Viterbi OFF */
1348 reg = stb0899_read_reg(state, STB0899_FECM);
1349 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0);
1350 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 0);
1351 stb0899_write_reg(state, STB0899_FECM, reg);
1352
1353 stb0899_write_reg(state, STB0899_RSULC, 0xb1);
1354 stb0899_write_reg(state, STB0899_TSULC, 0x42);
1355 stb0899_write_reg(state, STB0899_RSLLC, 0x40);
1356 stb0899_write_reg(state, STB0899_TSLPL, 0x02);
1357
1358 reg = stb0899_read_reg(state, STB0899_TSTRES);
1359 STB0899_SETFIELD_VAL(FRESLDPC, reg, 0);
1360 stb0899_write_reg(state, STB0899_TSTRES, reg);
1361
1362 STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1363 STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 0);
1364 STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 0);
1365
1366 STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 0);
1367 STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 0);
1368
1369 STB0899_SETFIELD_VAL(STOP_CKINTBUF216, stop_clk[0], 0);
1370 STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
1371
1372 STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 0);
1373 break;
1374 case SYS_DSS:
1375 /* FECM/Viterbi ON */
1376 reg = stb0899_read_reg(state, STB0899_FECM);
1377 STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 1);
1378 STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1);
1379 stb0899_write_reg(state, STB0899_FECM, reg);
1380
1381 stb0899_write_reg(state, STB0899_RSULC, 0xa1);
1382 stb0899_write_reg(state, STB0899_TSULC, 0x61);
1383 stb0899_write_reg(state, STB0899_RSLLC, 0x42);
1384
1385 reg = stb0899_read_reg(state, STB0899_TSTRES);
1386 STB0899_SETFIELD_VAL(FRESLDPC, reg, 1);
1387 stb0899_write_reg(state, STB0899_TSTRES, reg);
1388
1389 STB0899_SETFIELD_VAL(STOP_CHK8PSK, stop_clk[0], 1);
1390 STB0899_SETFIELD_VAL(STOP_CKFEC108, stop_clk[0], 1);
1391 STB0899_SETFIELD_VAL(STOP_CKFEC216, stop_clk[0], 1);
1392
1393 STB0899_SETFIELD_VAL(STOP_CKPKDLIN108, stop_clk[1], 1);
1394 STB0899_SETFIELD_VAL(STOP_CKPKDLIN216, stop_clk[1], 1);
1395
1396 STB0899_SETFIELD_VAL(STOP_CKCORE216, stop_clk[0], 0);
1397
1398 STB0899_SETFIELD_VAL(STOP_CKS2DMD108, stop_clk[1], 1);
1399 break;
1400 default:
1401 dprintk(state->verbose, FE_ERROR, 1, "Unsupported delivery system");
1402 break;
1403 }
1404 STB0899_SETFIELD_VAL(STOP_CKADCI108, stop_clk[0], 0);
1405 stb0899_write_regs(state, STB0899_STOPCLK1, stop_clk, 2);
1406}
1407
1408/*
1409 * stb0899_set_iterations
1410 * set the LDPC iteration scale function
1411 */
1412static void stb0899_set_iterations(struct stb0899_state *state)
1413{
1414 struct stb0899_internal *internal = &state->internal;
1415 struct stb0899_config *config = state->config;
1416
1417 s32 iter_scale;
1418 u32 reg;
1419
1420 iter_scale = 17 * (internal->master_clk / 1000);
1421 iter_scale += 410000;
1422 iter_scale /= (internal->srate / 1000000);
1423 iter_scale /= 1000;
1424
1425 if (iter_scale > config->ldpc_max_iter)
1426 iter_scale = config->ldpc_max_iter;
1427
1428 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, MAX_ITER);
1429 STB0899_SETFIELD_VAL(MAX_ITERATIONS, reg, iter_scale);
1430 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg);
1431}
1432
1433static enum dvbfe_search stb0899_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
1434{
1435 struct stb0899_state *state = fe->demodulator_priv;
1436 struct stb0899_params *i_params = &state->params;
1437 struct stb0899_internal *internal = &state->internal;
1438 struct stb0899_config *config = state->config;
1439 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
1440
1441 u32 SearchRange, gain;
1442
1443 i_params->freq = p->frequency;
1444 i_params->srate = p->u.qpsk.symbol_rate;
1445 state->delsys = props->delivery_system;
1446 dprintk(state->verbose, FE_DEBUG, 1, "delivery system=%d", state->delsys);
1447
1448 SearchRange = 10000000;
1449 dprintk(state->verbose, FE_DEBUG, 1, "Frequency=%d, Srate=%d", i_params->freq, i_params->srate);
1450 /* checking Search Range is meaningless for a fixed 3 Mhz */
1451 if (INRANGE(i_params->srate, 1000000, 45000000)) {
1452 dprintk(state->verbose, FE_DEBUG, 1, "Parameters IN RANGE");
1453 stb0899_set_delivery(state);
1454
1455 if (state->config->tuner_set_rfsiggain) {
1456 if (internal->srate > 15000000)
1457 gain = 8; /* 15Mb < srate < 45Mb, gain = 8dB */
1458 else if (internal->srate > 5000000)
1459 gain = 12; /* 5Mb < srate < 15Mb, gain = 12dB */
1460 else
1461 gain = 14; /* 1Mb < srate < 5Mb, gain = 14db */
1462 state->config->tuner_set_rfsiggain(fe, gain);
1463 }
1464
1465 if (i_params->srate <= 5000000)
1466 stb0899_set_mclk(state, config->lo_clk);
1467 else
1468 stb0899_set_mclk(state, config->hi_clk);
1469
1470 switch (state->delsys) {
1471 case SYS_DVBS:
1472 case SYS_DSS:
1473 dprintk(state->verbose, FE_DEBUG, 1, "DVB-S delivery system");
1474 internal->freq = i_params->freq;
1475 internal->srate = i_params->srate;
1476 /*
1477 * search = user search range +
1478 * 500Khz +
1479 * 2 * Tuner_step_size +
1480 * 10% of the symbol rate
1481 */
1482 internal->srch_range = SearchRange + 1500000 + (i_params->srate / 5);
1483 internal->derot_percent = 30;
1484
1485 /* What to do for tuners having no bandwidth setup ? */
1486 /* enable tuner I/O */
1487 stb0899_i2c_gate_ctrl(&state->frontend, 1);
1488
1489 if (state->config->tuner_set_bandwidth)
1490 state->config->tuner_set_bandwidth(fe, (13 * (stb0899_carr_width(state) + SearchRange)) / 10);
1491 if (state->config->tuner_get_bandwidth)
1492 state->config->tuner_get_bandwidth(fe, &internal->tuner_bw);
1493
1494 /* disable tuner I/O */
1495 stb0899_i2c_gate_ctrl(&state->frontend, 0);
1496
1497 /* Set DVB-S1 AGC */
1498 stb0899_write_reg(state, STB0899_AGCRFCFG, 0x11);
1499
1500 /* Run the search algorithm */
1501 dprintk(state->verbose, FE_DEBUG, 1, "running DVB-S search algo ..");
1502 if (stb0899_dvbs_algo(state) == RANGEOK) {
1503 internal->lock = 1;
1504 dprintk(state->verbose, FE_DEBUG, 1,
1505 "-------------------------------------> DVB-S LOCK !");
1506
1507// stb0899_write_reg(state, STB0899_ERRCTRL1, 0x3d); /* Viterbi Errors */
1508// internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS);
1509// internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1);
1510// dprintk(state->verbose, FE_DEBUG, 1, "VSTATUS=0x%02x", internal->v_status);
1511// dprintk(state->verbose, FE_DEBUG, 1, "ERR_CTRL=0x%02x", internal->err_ctrl);
1512
1513 return DVBFE_ALGO_SEARCH_SUCCESS;
1514 } else {
1515 internal->lock = 0;
1516
1517 return DVBFE_ALGO_SEARCH_FAILED;
1518 }
1519 break;
1520 case SYS_DVBS2:
1521 internal->freq = i_params->freq;
1522 internal->srate = i_params->srate;
1523 internal->srch_range = SearchRange;
1524
1525 /* enable tuner I/O */
1526 stb0899_i2c_gate_ctrl(&state->frontend, 1);
1527
1528 if (state->config->tuner_set_bandwidth)
1529 state->config->tuner_set_bandwidth(fe, (stb0899_carr_width(state) + SearchRange));
1530 if (state->config->tuner_get_bandwidth)
1531 state->config->tuner_get_bandwidth(fe, &internal->tuner_bw);
1532
1533 /* disable tuner I/O */
1534 stb0899_i2c_gate_ctrl(&state->frontend, 0);
1535
1536// pParams->SpectralInv = pSearch->IQ_Inversion;
1537
1538 /* Set DVB-S2 AGC */
1539 stb0899_write_reg(state, STB0899_AGCRFCFG, 0x1c);
1540
1541 /* Set IterScale =f(MCLK,SYMB) */
1542 stb0899_set_iterations(state);
1543
1544 /* Run the search algorithm */
1545 dprintk(state->verbose, FE_DEBUG, 1, "running DVB-S2 search algo ..");
1546 if (stb0899_dvbs2_algo(state) == DVBS2_FEC_LOCK) {
1547 internal->lock = 1;
1548 dprintk(state->verbose, FE_DEBUG, 1,
1549 "-------------------------------------> DVB-S2 LOCK !");
1550
1551// stb0899_write_reg(state, STB0899_ERRCTRL1, 0xb6); /* Packet Errors */
1552// internal->v_status = stb0899_read_reg(state, STB0899_VSTATUS);
1553// internal->err_ctrl = stb0899_read_reg(state, STB0899_ERRCTRL1);
1554
1555 return DVBFE_ALGO_SEARCH_SUCCESS;
1556 } else {
1557 internal->lock = 0;
1558
1559 return DVBFE_ALGO_SEARCH_FAILED;
1560 }
1561 break;
1562 default:
1563 dprintk(state->verbose, FE_ERROR, 1, "Unsupported delivery system");
1564 return DVBFE_ALGO_SEARCH_INVALID;
1565 }
1566 }
1567
1568 return DVBFE_ALGO_SEARCH_ERROR;
1569}
1570/*
1571 * stb0899_track
1572 * periodically check the signal level against a specified
1573 * threshold level and perform derotator centering.
1574 * called once we have a lock from a succesful search
1575 * event.
1576 *
1577 * Will be called periodically called to maintain the
1578 * lock.
1579 *
1580 * Will be used to get parameters as well as info from
1581 * the decoded baseband header
1582 *
1583 * Once a new lock has established, the internal state
1584 * frequency (internal->freq) is updated
1585 */
1586static int stb0899_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
1587{
1588 return 0;
1589}
1590
1591static int stb0899_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
1592{
1593 struct stb0899_state *state = fe->demodulator_priv;
1594 struct stb0899_internal *internal = &state->internal;
1595
1596 dprintk(state->verbose, FE_DEBUG, 1, "Get params");
1597 p->u.qpsk.symbol_rate = internal->srate;
1598
1599 return 0;
1600}
1601
1602static enum dvbfe_algo stb0899_frontend_algo(struct dvb_frontend *fe)
1603{
1604 return DVBFE_ALGO_CUSTOM;
1605}
1606
1607static struct dvb_frontend_ops stb0899_ops = {
1608
1609 .info = {
1610 .name = "STB0899 Multistandard",
1611 .type = FE_QPSK,
1612 .frequency_min = 950000,
1613 .frequency_max = 2150000,
1614 .frequency_stepsize = 0,
1615 .frequency_tolerance = 0,
1616 .symbol_rate_min = 5000000,
1617 .symbol_rate_max = 45000000,
1618
1619 .caps = FE_CAN_INVERSION_AUTO |
1620 FE_CAN_FEC_AUTO |
1621 FE_CAN_QPSK
1622 },
1623
1624 .release = stb0899_release,
1625 .init = stb0899_init,
1626 .sleep = stb0899_sleep,
1627// .wakeup = stb0899_wakeup,
1628
1629 .i2c_gate_ctrl = stb0899_i2c_gate_ctrl,
1630
1631 .get_frontend_algo = stb0899_frontend_algo,
1632 .search = stb0899_search,
1633 .track = stb0899_track,
1634 .get_frontend = stb0899_get_frontend,
1635
1636
1637 .read_status = stb0899_read_status,
1638 .read_snr = stb0899_read_snr,
1639 .read_signal_strength = stb0899_read_signal_strength,
1640 .read_ber = stb0899_read_ber,
1641
1642 .set_voltage = stb0899_set_voltage,
1643 .set_tone = stb0899_set_tone,
1644
1645 .diseqc_send_master_cmd = stb0899_send_diseqc_msg,
1646 .diseqc_recv_slave_reply = stb0899_recv_slave_reply,
1647 .diseqc_send_burst = stb0899_send_diseqc_burst,
1648};
1649
1650struct dvb_frontend *stb0899_attach(struct stb0899_config *config, struct i2c_adapter *i2c)
1651{
1652 struct stb0899_state *state = NULL;
1653 enum stb0899_inversion inversion;
1654
1655 state = kzalloc(sizeof (struct stb0899_state), GFP_KERNEL);
1656 if (state == NULL)
1657 goto error;
1658
1659 inversion = config->inversion;
1660 state->verbose = &verbose;
1661 state->config = config;
1662 state->i2c = i2c;
1663 state->frontend.ops = stb0899_ops;
1664 state->frontend.demodulator_priv = state;
1665 state->internal.inversion = inversion;
1666
1667 stb0899_wakeup(&state->frontend);
1668 if (stb0899_get_dev_id(state) == -ENODEV) {
1669 printk("%s: Exiting .. !\n", __func__);
1670 goto error;
1671 }
1672
1673 printk("%s: Attaching STB0899 \n", __func__);
1674 return &state->frontend;
1675
1676error:
1677 kfree(state);
1678 return NULL;
1679}
1680EXPORT_SYMBOL(stb0899_attach);
1681MODULE_PARM_DESC(verbose, "Set Verbosity level");
1682MODULE_AUTHOR("Manu Abraham");
1683MODULE_DESCRIPTION("STB0899 Multi-Std frontend");
1684MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stb0899_drv.h b/drivers/media/dvb/frontends/stb0899_drv.h
new file mode 100644
index 000000000000..98b200ce0c34
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_drv.h
@@ -0,0 +1,162 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STB0899_DRV_H
23#define __STB0899_DRV_H
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27
28#include "dvb_frontend.h"
29
30#define STB0899_TSMODE_SERIAL 1
31#define STB0899_CLKPOL_FALLING 2
32#define STB0899_CLKNULL_PARITY 3
33#define STB0899_SYNC_FORCED 4
34#define STB0899_FECMODE_DSS 5
35
36struct stb0899_s1_reg {
37 u16 address;
38 u8 data;
39};
40
41struct stb0899_s2_reg {
42 u16 offset;
43 u32 base_address;
44 u32 data;
45};
46
47enum stb0899_inversion {
48 IQ_SWAP_OFF = 0,
49 IQ_SWAP_ON,
50 IQ_SWAP_AUTO
51};
52
53#define STB0899_GPIO00 0xf140
54#define STB0899_GPIO01 0xf141
55#define STB0899_GPIO02 0xf142
56#define STB0899_GPIO03 0xf143
57#define STB0899_GPIO04 0xf144
58#define STB0899_GPIO05 0xf145
59#define STB0899_GPIO06 0xf146
60#define STB0899_GPIO07 0xf147
61#define STB0899_GPIO08 0xf148
62#define STB0899_GPIO09 0xf149
63#define STB0899_GPIO10 0xf14a
64#define STB0899_GPIO11 0xf14b
65#define STB0899_GPIO12 0xf14c
66#define STB0899_GPIO13 0xf14d
67#define STB0899_GPIO14 0xf14e
68#define STB0899_GPIO15 0xf14f
69#define STB0899_GPIO16 0xf150
70#define STB0899_GPIO17 0xf151
71#define STB0899_GPIO18 0xf152
72#define STB0899_GPIO19 0xf153
73#define STB0899_GPIO20 0xf154
74
75#define STB0899_GPIOPULLUP 0x01 /* Output device is connected to Vdd */
76#define STB0899_GPIOPULLDN 0x00 /* Output device is connected to Vss */
77
78#define STB0899_POSTPROC_GPIO_POWER 0x00
79#define STB0899_POSTPROC_GPIO_LOCK 0x01
80
81/*
82 * Post process output configuration control
83 * 1. POWER ON/OFF (index 0)
84 * 2. FE_HAS_LOCK/LOCK_LOSS (index 1)
85 *
86 * @gpio = one of the above listed GPIO's
87 * @level = output state: pulled up or low
88 */
89struct stb0899_postproc {
90 u16 gpio;
91 u8 level;
92};
93
94struct stb0899_config {
95 const struct stb0899_s1_reg *init_dev;
96 const struct stb0899_s2_reg *init_s2_demod;
97 const struct stb0899_s1_reg *init_s1_demod;
98 const struct stb0899_s2_reg *init_s2_fec;
99 const struct stb0899_s1_reg *init_tst;
100
101 const struct stb0899_postproc *postproc;
102
103 enum stb0899_inversion inversion;
104
105 u32 xtal_freq;
106
107 u8 demod_address;
108 u8 ts_output_mode;
109 u8 block_sync_mode;
110 u8 ts_pfbit_toggle;
111
112 u8 clock_polarity;
113 u8 data_clk_parity;
114 u8 fec_mode;
115 u8 data_output_ctl;
116 u8 data_fifo_mode;
117 u8 out_rate_comp;
118 u8 i2c_repeater;
119// int inversion;
120 int lo_clk;
121 int hi_clk;
122
123 u32 esno_ave;
124 u32 esno_quant;
125 u32 avframes_coarse;
126 u32 avframes_fine;
127 u32 miss_threshold;
128 u32 uwp_threshold_acq;
129 u32 uwp_threshold_track;
130 u32 uwp_threshold_sof;
131 u32 sof_search_timeout;
132
133 u32 btr_nco_bits;
134 u32 btr_gain_shift_offset;
135 u32 crl_nco_bits;
136 u32 ldpc_max_iter;
137
138 int (*tuner_set_frequency)(struct dvb_frontend *fe, u32 frequency);
139 int (*tuner_get_frequency)(struct dvb_frontend *fe, u32 *frequency);
140 int (*tuner_set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth);
141 int (*tuner_get_bandwidth)(struct dvb_frontend *fe, u32 *bandwidth);
142 int (*tuner_set_rfsiggain)(struct dvb_frontend *fe, u32 rf_gain);
143};
144
145#if defined(CONFIG_DVB_STB0899) || (defined(CONFIG_DVB_STB0899_MODULE) && defined(MODULE))
146
147extern struct dvb_frontend *stb0899_attach(struct stb0899_config *config,
148 struct i2c_adapter *i2c);
149
150#else
151
152static inline struct dvb_frontend *stb0899_attach(struct stb0899_config *config,
153 struct i2c_adapter *i2c)
154{
155 printk(KERN_WARNING "%s: Driver disabled by Kconfig\n", __func__);
156 return NULL;
157}
158
159#endif //CONFIG_DVB_STB0899
160
161
162#endif
diff --git a/drivers/media/dvb/frontends/stb0899_priv.h b/drivers/media/dvb/frontends/stb0899_priv.h
new file mode 100644
index 000000000000..24619e3689db
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_priv.h
@@ -0,0 +1,267 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STB0899_PRIV_H
23#define __STB0899_PRIV_H
24
25#include "dvb_frontend.h"
26#include "stb0899_drv.h"
27
28#define FE_ERROR 0
29#define FE_NOTICE 1
30#define FE_INFO 2
31#define FE_DEBUG 3
32#define FE_DEBUGREG 4
33
34#define dprintk(x, y, z, format, arg...) do { \
35 if (z) { \
36 if ((*x > FE_ERROR) && (*x > y)) \
37 printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
38 else if ((*x > FE_NOTICE) && (*x > y)) \
39 printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
40 else if ((*x > FE_INFO) && (*x > y)) \
41 printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
42 else if ((*x > FE_DEBUG) && (*x > y)) \
43 printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
44 } else { \
45 if (*x > y) \
46 printk(format, ##arg); \
47 } \
48} while(0)
49
50#define INRANGE(val, x, y) (((x <= val) && (val <= y)) || \
51 ((y <= val) && (val <= x)) ? 1 : 0)
52
53#define BYTE0 0
54#define BYTE1 8
55#define BYTE2 16
56#define BYTE3 24
57
58#define GETBYTE(x, y) (((x) >> (y)) & 0xff)
59#define MAKEWORD32(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
60#define MAKEWORD16(a, b) (((a) << 8) | (b))
61
62#define MIN(x, y) ((x) <= (y) ? (x) : (y))
63#define MAX(x, y) ((x) >= (y) ? (x) : (y))
64#define ABS(x) ((x) >= 0 ? (x) : -(x))
65
66#define LSB(x) ((x & 0xff))
67#define MSB(y) ((y >> 8) & 0xff)
68
69
70#define STB0899_GETFIELD(bitf, val) ((val >> STB0899_OFFST_##bitf) & ((1 << STB0899_WIDTH_##bitf) - 1))
71
72
73#define STB0899_SETFIELD(mask, val, width, offset) (mask & (~(((1 << width) - 1) << \
74 offset))) | ((val & \
75 ((1 << width) - 1)) << offset)
76
77#define STB0899_SETFIELD_VAL(bitf, mask, val) (mask = (mask & (~(((1 << STB0899_WIDTH_##bitf) - 1) <<\
78 STB0899_OFFST_##bitf))) | \
79 (val << STB0899_OFFST_##bitf))
80
81
82enum stb0899_status {
83 NOAGC1 = 0,
84 AGC1OK,
85 NOTIMING,
86 ANALOGCARRIER,
87 TIMINGOK,
88 NOAGC2,
89 AGC2OK,
90 NOCARRIER,
91 CARRIEROK,
92 NODATA,
93 FALSELOCK,
94 DATAOK,
95 OUTOFRANGE,
96 RANGEOK,
97 DVBS2_DEMOD_LOCK,
98 DVBS2_DEMOD_NOLOCK,
99 DVBS2_FEC_LOCK,
100 DVBS2_FEC_NOLOCK
101};
102
103enum stb0899_modcod {
104 STB0899_DUMMY_PLF,
105 STB0899_QPSK_14,
106 STB0899_QPSK_13,
107 STB0899_QPSK_25,
108 STB0899_QPSK_12,
109 STB0899_QPSK_35,
110 STB0899_QPSK_23,
111 STB0899_QPSK_34,
112 STB0899_QPSK_45,
113 STB0899_QPSK_56,
114 STB0899_QPSK_89,
115 STB0899_QPSK_910,
116 STB0899_8PSK_35,
117 STB0899_8PSK_23,
118 STB0899_8PSK_34,
119 STB0899_8PSK_56,
120 STB0899_8PSK_89,
121 STB0899_8PSK_910,
122 STB0899_16APSK_23,
123 STB0899_16APSK_34,
124 STB0899_16APSK_45,
125 STB0899_16APSK_56,
126 STB0899_16APSK_89,
127 STB0899_16APSK_910,
128 STB0899_32APSK_34,
129 STB0899_32APSK_45,
130 STB0899_32APSK_56,
131 STB0899_32APSK_89,
132 STB0899_32APSK_910
133};
134
135enum stb0899_frame {
136 STB0899_LONG_FRAME,
137 STB0899_SHORT_FRAME
138};
139
140enum stb0899_alpha {
141 RRC_20,
142 RRC_25,
143 RRC_35
144};
145
146struct stb0899_tab {
147 s32 real;
148 s32 read;
149};
150
151enum stb0899_fec {
152 STB0899_FEC_1_2 = 13,
153 STB0899_FEC_2_3 = 18,
154 STB0899_FEC_3_4 = 21,
155 STB0899_FEC_5_6 = 24,
156 STB0899_FEC_6_7 = 25,
157 STB0899_FEC_7_8 = 26
158};
159
160struct stb0899_params {
161 u32 freq; /* Frequency */
162 u32 srate; /* Symbol rate */
163 enum fe_code_rate fecrate;
164};
165
166struct stb0899_internal {
167 u32 master_clk;
168 u32 freq; /* Demod internal Frequency */
169 u32 srate; /* Demod internal Symbol rate */
170 enum stb0899_fec fecrate; /* Demod internal FEC rate */
171 u32 srch_range; /* Demod internal Search Range */
172 u32 sub_range; /* Demod current sub range (Hz) */
173 u32 tuner_step; /* Tuner step (Hz) */
174 u32 tuner_offst; /* Relative offset to carrier (Hz) */
175 u32 tuner_bw; /* Current bandwidth of the tuner (Hz) */
176
177 s32 mclk; /* Masterclock Divider factor (binary) */
178 s32 rolloff; /* Current RollOff of the filter (x100) */
179
180 s16 derot_freq; /* Current derotator frequency (Hz) */
181 s16 derot_percent;
182
183 s16 direction; /* Current derotator search direction */
184 s16 derot_step; /* Derotator step (binary value) */
185 s16 t_derot; /* Derotator time constant (ms) */
186 s16 t_data; /* Data recovery time constant (ms) */
187 s16 sub_dir; /* Direction of the next sub range */
188
189 s16 t_agc1; /* Agc1 time constant (ms) */
190 s16 t_agc2; /* Agc2 time constant (ms) */
191
192 u32 lock; /* Demod internal lock state */
193 enum stb0899_status status; /* Demod internal status */
194
195 /* DVB-S2 */
196 s32 agc_gain; /* RF AGC Gain */
197 s32 center_freq; /* Nominal carrier frequency */
198 s32 av_frame_coarse; /* Coarse carrier freq search frames */
199 s32 av_frame_fine; /* Fine carrier freq search frames */
200
201 s16 step_size; /* Carrier frequency search step size */
202
203 enum stb0899_alpha rrc_alpha;
204 enum stb0899_inversion inversion;
205 enum stb0899_modcod modcod;
206 u8 pilots; /* Pilots found */
207
208 enum stb0899_frame frame_length;
209 u8 v_status; /* VSTATUS */
210 u8 err_ctrl; /* ERRCTRLn */
211};
212
213struct stb0899_state {
214 struct i2c_adapter *i2c;
215 struct stb0899_config *config;
216 struct dvb_frontend frontend;
217
218 u32 *verbose; /* Cached module verbosity level */
219
220 struct stb0899_internal internal; /* Device internal parameters */
221
222 /* cached params from API */
223 enum fe_delivery_system delsys;
224 struct stb0899_params params;
225
226 u32 rx_freq; /* DiSEqC 2.0 receiver freq */
227 struct mutex search_lock;
228};
229/* stb0899.c */
230extern int stb0899_read_reg(struct stb0899_state *state,
231 unsigned int reg);
232
233extern u32 _stb0899_read_s2reg(struct stb0899_state *state,
234 u32 stb0899_i2cdev,
235 u32 stb0899_base_addr,
236 u16 stb0899_reg_offset);
237
238extern int stb0899_read_regs(struct stb0899_state *state,
239 unsigned int reg, u8 *buf,
240 u32 count);
241
242extern int stb0899_write_regs(struct stb0899_state *state,
243 unsigned int reg, u8 *data,
244 u32 count);
245
246extern int stb0899_write_reg(struct stb0899_state *state,
247 unsigned int reg,
248 u8 data);
249
250extern int stb0899_write_s2reg(struct stb0899_state *state,
251 u32 stb0899_i2cdev,
252 u32 stb0899_base_addr,
253 u16 stb0899_reg_offset,
254 u32 stb0899_data);
255
256extern int stb0899_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);
257
258
259#define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG))
260//#define STB0899_WRITE_S2REG(DEVICE, REG, DATA) (_stb0899_write_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG, DATA))
261
262/* stb0899_algo.c */
263extern enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state);
264extern enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state);
265extern long stb0899_carr_width(struct stb0899_state *state);
266
267#endif //__STB0899_PRIV_H
diff --git a/drivers/media/dvb/frontends/stb0899_reg.h b/drivers/media/dvb/frontends/stb0899_reg.h
new file mode 100644
index 000000000000..ba1ed56304a0
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb0899_reg.h
@@ -0,0 +1,2027 @@
1/*
2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STB0899_REG_H
23#define __STB0899_REG_H
24
25/* S1 */
26#define STB0899_DEV_ID 0xf000
27#define STB0899_CHIP_ID (0x0f << 4)
28#define STB0899_OFFST_CHIP_ID 4
29#define STB0899_WIDTH_CHIP_ID 4
30#define STB0899_CHIP_REL (0x0f << 0)
31#define STB0899_OFFST_CHIP_REL 0
32#define STB0899_WIDTH_CHIP_REL 4
33
34#define STB0899_DEMOD 0xf40e
35#define STB0899_MODECOEFF (0x01 << 0)
36#define STB0899_OFFST_MODECOEFF 0
37#define STB0899_WIDTH_MODECOEFF 1
38
39#define STB0899_RCOMPC 0xf410
40#define STB0899_AGC1CN 0xf412
41#define STB0899_AGC1REF 0xf413
42#define STB0899_RTC 0xf417
43#define STB0899_TMGCFG 0xf418
44#define STB0899_AGC2REF 0xf419
45#define STB0899_TLSR 0xf41a
46
47#define STB0899_CFD 0xf41b
48#define STB0899_CFD_ON (0x01 << 7)
49#define STB0899_OFFST_CFD_ON 7
50#define STB0899_WIDTH_CFD_ON 1
51
52#define STB0899_ACLC 0xf41c
53
54#define STB0899_BCLC 0xf41d
55#define STB0899_OFFST_ALGO 6
56#define STB0899_WIDTH_ALGO_QPSK2 2
57#define STB0899_ALGO_QPSK2 (2 << 6)
58#define STB0899_ALGO_QPSK1 (1 << 6)
59#define STB0899_ALGO_BPSK (0 << 6)
60#define STB0899_OFFST_BETA 0
61#define STB0899_WIDTH_BETA 6
62
63#define STB0899_EQON 0xf41e
64#define STB0899_LDT 0xf41f
65#define STB0899_LDT2 0xf420
66#define STB0899_EQUALREF 0xf425
67#define STB0899_TMGRAMP 0xf426
68#define STB0899_TMGTHD 0xf427
69#define STB0899_IDCCOMP 0xf428
70#define STB0899_QDCCOMP 0xf429
71#define STB0899_POWERI 0xf42a
72#define STB0899_POWERQ 0xf42b
73#define STB0899_RCOMP 0xf42c
74
75#define STB0899_AGCIQIN 0xf42e
76#define STB0899_AGCIQVALUE (0xff << 0)
77#define STB0899_OFFST_AGCIQVALUE 0
78#define STB0899_WIDTH_AGCIQVALUE 8
79
80#define STB0899_AGC2I1 0xf436
81#define STB0899_AGC2I2 0xf437
82
83#define STB0899_TLIR 0xf438
84#define STB0899_TLIR_TMG_LOCK_IND (0xff << 0)
85#define STB0899_OFFST_TLIR_TMG_LOCK_IND 0
86#define STB0899_WIDTH_TLIR_TMG_LOCK_IND 8
87
88#define STB0899_RTF 0xf439
89#define STB0899_RTF_TIMING_LOOP_FREQ (0xff << 0)
90#define STB0899_OFFST_RTF_TIMING_LOOP_FREQ 0
91#define STB0899_WIDTH_RTF_TIMING_LOOP_FREQ 8
92
93#define STB0899_DSTATUS 0xf43a
94#define STB0899_CARRIER_FOUND (0x01 << 7)
95#define STB0899_OFFST_CARRIER_FOUND 7
96#define STB0899_WIDTH_CARRIER_FOUND 1
97#define STB0899_TMG_LOCK (0x01 << 6)
98#define STB0899_OFFST_TMG_LOCK 6
99#define STB0899_WIDTH_TMG_LOCK 1
100#define STB0899_DEMOD_LOCK (0x01 << 5)
101#define STB0899_OFFST_DEMOD_LOCK 5
102#define STB0899_WIDTH_DEMOD_LOCK 1
103#define STB0899_TMG_AUTO (0x01 << 4)
104#define STB0899_OFFST_TMG_AUTO 4
105#define STB0899_WIDTH_TMG_AUTO 1
106#define STB0899_END_MAIN (0x01 << 3)
107#define STB0899_OFFST_END_MAIN 3
108#define STB0899_WIDTH_END_MAIN 1
109
110#define STB0899_LDI 0xf43b
111#define STB0899_OFFST_LDI 0
112#define STB0899_WIDTH_LDI 8
113
114#define STB0899_CFRM 0xf43e
115#define STB0899_OFFST_CFRM 0
116#define STB0899_WIDTH_CFRM 8
117
118#define STB0899_CFRL 0xf43f
119#define STB0899_OFFST_CFRL 0
120#define STB0899_WIDTH_CFRL 8
121
122#define STB0899_NIRM 0xf440
123#define STB0899_OFFST_NIRM 0
124#define STB0899_WIDTH_NIRM 8
125
126#define STB0899_NIRL 0xf441
127#define STB0899_OFFST_NIRL 0
128#define STB0899_WIDTH_NIRL 8
129
130#define STB0899_ISYMB 0xf444
131#define STB0899_QSYMB 0xf445
132
133#define STB0899_SFRH 0xf446
134#define STB0899_OFFST_SFRH 0
135#define STB0899_WIDTH_SFRH 8
136
137#define STB0899_SFRM 0xf447
138#define STB0899_OFFST_SFRM 0
139#define STB0899_WIDTH_SFRM 8
140
141#define STB0899_SFRL 0xf448
142#define STB0899_OFFST_SFRL 4
143#define STB0899_WIDTH_SFRL 4
144
145#define STB0899_SFRUPH 0xf44c
146#define STB0899_SFRUPM 0xf44d
147#define STB0899_SFRUPL 0xf44e
148
149#define STB0899_EQUAI1 0xf4e0
150#define STB0899_EQUAQ1 0xf4e1
151#define STB0899_EQUAI2 0xf4e2
152#define STB0899_EQUAQ2 0xf4e3
153#define STB0899_EQUAI3 0xf4e4
154#define STB0899_EQUAQ3 0xf4e5
155#define STB0899_EQUAI4 0xf4e6
156#define STB0899_EQUAQ4 0xf4e7
157#define STB0899_EQUAI5 0xf4e8
158#define STB0899_EQUAQ5 0xf4e9
159
160#define STB0899_DSTATUS2 0xf50c
161#define STB0899_DS2_TMG_AUTOSRCH (0x01 << 7)
162#define STB8999_OFFST_DS2_TMG_AUTOSRCH 7
163#define STB0899_WIDTH_DS2_TMG_AUTOSRCH 1
164#define STB0899_DS2_END_MAINLOOP (0x01 << 6)
165#define STB0899_OFFST_DS2_END_MAINLOOP 6
166#define STB0899_WIDTH_DS2_END_MAINLOOP 1
167#define STB0899_DS2_CFSYNC (0x01 << 5)
168#define STB0899_OFFST_DS2_CFSYNC 5
169#define STB0899_WIDTH_DS2_CFSYNC 1
170#define STB0899_DS2_TMGLOCK (0x01 << 4)
171#define STB0899_OFFST_DS2_TMGLOCK 4
172#define STB0899_WIDTH_DS2_TMGLOCK 1
173#define STB0899_DS2_DEMODWAIT (0x01 << 3)
174#define STB0899_OFFST_DS2_DEMODWAIT 3
175#define STB0899_WIDTH_DS2_DEMODWAIT 1
176#define STB0899_DS2_FECON (0x01 << 1)
177#define STB0899_OFFST_DS2_FECON 1
178#define STB0899_WIDTH_DS2_FECON 1
179
180/* S1 FEC */
181#define STB0899_VSTATUS 0xf50d
182#define STB0899_VSTATUS_VITERBI_ON (0x01 << 7)
183#define STB0899_OFFST_VSTATUS_VITERBI_ON 7
184#define STB0899_WIDTH_VSTATUS_VITERBI_ON 1
185#define STB0899_VSTATUS_END_LOOPVIT (0x01 << 6)
186#define STB0899_OFFST_VSTATUS_END_LOOPVIT 6
187#define STB0899_WIDTH_VSTATUS_END_LOOPVIT 1
188#define STB0899_VSTATUS_PRFVIT (0x01 << 4)
189#define STB0899_OFFST_VSTATUS_PRFVIT 4
190#define STB0899_WIDTH_VSTATUS_PRFVIT 1
191#define STB0899_VSTATUS_LOCKEDVIT (0x01 << 3)
192#define STB0899_OFFST_VSTATUS_LOCKEDVIT 3
193#define STB0899_WIDTH_VSTATUS_LOCKEDVIT 1
194
195#define STB0899_VERROR 0xf50f
196
197#define STB0899_IQSWAP 0xf523
198#define STB0899_SYM (0x01 << 3)
199#define STB0899_OFFST_SYM 3
200#define STB0899_WIDTH_SYM 1
201
202#define STB0899_FECAUTO1 0xf530
203#define STB0899_DSSSRCH (0x01 << 3)
204#define STB0899_OFFST_DSSSRCH 3
205#define STB0899_WIDTH_DSSSRCH 1
206#define STB0899_SYMSRCH (0x01 << 2)
207#define STB0899_OFFST_SYMSRCH 2
208#define STB0899_WIDTH_SYMSRCH 1
209#define STB0899_QPSKSRCH (0x01 << 1)
210#define STB0899_OFFST_QPSKSRCH 1
211#define STB0899_WIDTH_QPSKSRCH 1
212#define STB0899_BPSKSRCH (0x01 << 0)
213#define STB0899_OFFST_BPSKSRCH 0
214#define STB0899_WIDTH_BPSKSRCH 1
215
216#define STB0899_FECM 0xf533
217#define STB0899_FECM_NOT_DVB (0x01 << 7)
218#define STB0899_OFFST_FECM_NOT_DVB 7
219#define STB0899_WIDTH_FECM_NOT_DVB 1
220#define STB0899_FECM_RSVD1 (0x07 << 4)
221#define STB0899_OFFST_FECM_RSVD1 4
222#define STB0899_WIDTH_FECM_RSVD1 3
223#define STB0899_FECM_VITERBI_ON (0x01 << 3)
224#define STB0899_OFFST_FECM_VITERBI_ON 3
225#define STB0899_WIDTH_FECM_VITERBI_ON 1
226#define STB0899_FECM_RSVD0 (0x01 << 2)
227#define STB0899_OFFST_FECM_RSVD0 2
228#define STB0899_WIDTH_FECM_RSVD0 1
229#define STB0899_FECM_SYNCDIS (0x01 << 1)
230#define STB0899_OFFST_FECM_SYNCDIS 1
231#define STB0899_WIDTH_FECM_SYNCDIS 1
232#define STB0899_FECM_SYMI (0x01 << 0)
233#define STB0899_OFFST_FECM_SYMI 0
234#define STB0899_WIDTH_FECM_SYMI 1
235
236#define STB0899_VTH12 0xf534
237#define STB0899_VTH23 0xf535
238#define STB0899_VTH34 0xf536
239#define STB0899_VTH56 0xf537
240#define STB0899_VTH67 0xf538
241#define STB0899_VTH78 0xf539
242
243#define STB0899_PRVIT 0xf53c
244#define STB0899_PR_7_8 (0x01 << 5)
245#define STB0899_OFFST_PR_7_8 5
246#define STB0899_WIDTH_PR_7_8 1
247#define STB0899_PR_6_7 (0x01 << 4)
248#define STB0899_OFFST_PR_6_7 4
249#define STB0899_WIDTH_PR_6_7 1
250#define STB0899_PR_5_6 (0x01 << 3)
251#define STB0899_OFFST_PR_5_6 3
252#define STB0899_WIDTH_PR_5_6 1
253#define STB0899_PR_3_4 (0x01 << 2)
254#define STB0899_OFFST_PR_3_4 2
255#define STB0899_WIDTH_PR_3_4 1
256#define STB0899_PR_2_3 (0x01 << 1)
257#define STB0899_OFFST_PR_2_3 1
258#define STB0899_WIDTH_PR_2_3 1
259#define STB0899_PR_1_2 (0x01 << 0)
260#define STB0899_OFFST_PR_1_2 0
261#define STB0899_WIDTH_PR_1_2 1
262
263#define STB0899_VITSYNC 0xf53d
264#define STB0899_AM (0x01 << 7)
265#define STB0899_OFFST_AM 7
266#define STB0899_WIDTH_AM 1
267#define STB0899_FREEZE (0x01 << 6)
268#define STB0899_OFFST_FREEZE 6
269#define STB0899_WIDTH_FREEZE 1
270#define STB0899_SN_65536 (0x03 << 4)
271#define STB0899_OFFST_SN_65536 4
272#define STB0899_WIDTH_SN_65536 2
273#define STB0899_SN_16384 (0x01 << 5)
274#define STB0899_OFFST_SN_16384 5
275#define STB0899_WIDTH_SN_16384 1
276#define STB0899_SN_4096 (0x01 << 4)
277#define STB0899_OFFST_SN_4096 4
278#define STB0899_WIDTH_SN_4096 1
279#define STB0899_SN_1024 (0x00 << 4)
280#define STB0899_OFFST_SN_1024 4
281#define STB0899_WIDTH_SN_1024 0
282#define STB0899_TO_128 (0x03 << 2)
283#define STB0899_OFFST_TO_128 2
284#define STB0899_WIDTH_TO_128 2
285#define STB0899_TO_64 (0x01 << 3)
286#define STB0899_OFFST_TO_64 3
287#define STB0899_WIDTH_TO_64 1
288#define STB0899_TO_32 (0x01 << 2)
289#define STB0899_OFFST_TO_32 2
290#define STB0899_WIDTH_TO_32 1
291#define STB0899_TO_16 (0x00 << 2)
292#define STB0899_OFFST_TO_16 2
293#define STB0899_WIDTH_TO_16 0
294#define STB0899_HYST_128 (0x03 << 1)
295#define STB0899_OFFST_HYST_128 1
296#define STB0899_WIDTH_HYST_128 2
297#define STB0899_HYST_64 (0x01 << 1)
298#define STB0899_OFFST_HYST_64 1
299#define STB0899_WIDTH_HYST_64 1
300#define STB0899_HYST_32 (0x01 << 0)
301#define STB0899_OFFST_HYST_32 0
302#define STB0899_WIDTH_HYST_32 1
303#define STB0899_HYST_16 (0x00 << 0)
304#define STB0899_OFFST_HYST_16 0
305#define STB0899_WIDTH_HYST_16 0
306
307#define STB0899_RSULC 0xf548
308#define STB0899_ULDIL_ON (0x01 << 7)
309#define STB0899_OFFST_ULDIL_ON 7
310#define STB0899_WIDTH_ULDIL_ON 1
311#define STB0899_ULAUTO_ON (0x01 << 6)
312#define STB0899_OFFST_ULAUTO_ON 6
313#define STB0899_WIDTH_ULAUTO_ON 1
314#define STB0899_ULRS_ON (0x01 << 5)
315#define STB0899_OFFST_ULRS_ON 5
316#define STB0899_WIDTH_ULRS_ON 1
317#define STB0899_ULDESCRAM_ON (0x01 << 4)
318#define STB0899_OFFST_ULDESCRAM_ON 4
319#define STB0899_WIDTH_ULDESCRAM_ON 1
320#define STB0899_UL_DISABLE (0x01 << 2)
321#define STB0899_OFFST_UL_DISABLE 2
322#define STB0899_WIDTH_UL_DISABLE 1
323#define STB0899_NOFTHRESHOLD (0x01 << 0)
324#define STB0899_OFFST_NOFTHRESHOLD 0
325#define STB0899_WIDTH_NOFTHRESHOLD 1
326
327#define STB0899_RSLLC 0xf54a
328#define STB0899_DEMAPVIT 0xf583
329#define STB0899_DEMAPVIT_RSVD (0x01 << 7)
330#define STB0899_OFFST_DEMAPVIT_RSVD 7
331#define STB0899_WIDTH_DEMAPVIT_RSVD 1
332#define STB0899_DEMAPVIT_KDIVIDER (0x7f << 0)
333#define STB0899_OFFST_DEMAPVIT_KDIVIDER 0
334#define STB0899_WIDTH_DEMAPVIT_KDIVIDER 7
335
336#define STB0899_PLPARM 0xf58c
337#define STB0899_VITMAPPING (0x07 << 5)
338#define STB0899_OFFST_VITMAPPING 5
339#define STB0899_WIDTH_VITMAPPING 3
340#define STB0899_VITMAPPING_BPSK (0x01 << 5)
341#define STB0899_OFFST_VITMAPPING_BPSK 5
342#define STB0899_WIDTH_VITMAPPING_BPSK 1
343#define STB0899_VITMAPPING_QPSK (0x00 << 5)
344#define STB0899_OFFST_VITMAPPING_QPSK 5
345#define STB0899_WIDTH_VITMAPPING_QPSK 0
346#define STB0899_VITCURPUN (0x1f << 0)
347#define STB0899_OFFST_VITCURPUN 0
348#define STB0899_WIDTH_VITCURPUN 5
349#define STB0899_VITCURPUN_1_2 (0x0d << 0)
350#define STB0899_VITCURPUN_2_3 (0x12 << 0)
351#define STB0899_VITCURPUN_3_4 (0x15 << 0)
352#define STB0899_VITCURPUN_5_6 (0x18 << 0)
353#define STB0899_VITCURPUN_6_7 (0x19 << 0)
354#define STB0899_VITCURPUN_7_8 (0x1a << 0)
355
356/* S2 DEMOD */
357#define STB0899_OFF0_DMD_STATUS 0xf300
358#define STB0899_BASE_DMD_STATUS 0x00000000
359#define STB0899_IF_AGC_LOCK (0x01 << 8)
360#define STB0899_OFFST_IF_AGC_LOCK 0
361#define STB0899_WIDTH_IF_AGC_LOCK 1
362
363#define STB0899_OFF0_CRL_FREQ 0xf304
364#define STB0899_BASE_CRL_FREQ 0x00000000
365#define STB0899_CARR_FREQ (0x3fffffff << 0)
366#define STB0899_OFFST_CARR_FREQ 0
367#define STB0899_WIDTH_CARR_FREQ 30
368
369#define STB0899_OFF0_BTR_FREQ 0xf308
370#define STB0899_BASE_BTR_FREQ 0x00000000
371#define STB0899_BTR_FREQ (0xfffffff << 0)
372#define STB0899_OFFST_BTR_FREQ 0
373#define STB0899_WIDTH_BTR_FREQ 28
374
375#define STB0899_OFF0_IF_AGC_GAIN 0xf30c
376#define STB0899_BASE_IF_AGC_GAIN 0x00000000
377#define STB0899_IF_AGC_GAIN (0x3fff < 0)
378#define STB0899_OFFST_IF_AGC_GAIN 0
379#define STB0899_WIDTH_IF_AGC_GAIN 14
380
381#define STB0899_OFF0_BB_AGC_GAIN 0xf310
382#define STB0899_BASE_BB_AGC_GAIN 0x00000000
383#define STB0899_BB_AGC_GAIN (0x3fff < 0)
384#define STB0899_OFFST_BB_AGC_GAIN 0
385#define STB0899_WIDTH_BB_AGC_GAIN 14
386
387#define STB0899_OFF0_DC_OFFSET 0xf314
388#define STB0899_BASE_DC_OFFSET 0x00000000
389#define STB0899_I (0xff < 8)
390#define STB0899_OFFST_I 8
391#define STB0899_WIDTH_I 8
392#define STB0899_Q (0xff < 0)
393#define STB0899_OFFST_Q 8
394#define STB0899_WIDTH_Q 8
395
396#define STB0899_OFF0_DMD_CNTRL 0xf31c
397#define STB0899_BASE_DMD_CNTRL 0x00000000
398#define STB0899_ADC0_PINS1IN (0x01 << 6)
399#define STB0899_OFFST_ADC0_PINS1IN 6
400#define STB0899_WIDTH_ADC0_PINS1IN 1
401#define STB0899_IN2COMP1_OFFBIN0 (0x01 << 3)
402#define STB0899_OFFST_IN2COMP1_OFFBIN0 3
403#define STB0899_WIDTH_IN2COMP1_OFFBIN0 1
404#define STB0899_DC_COMP (0x01 << 2)
405#define STB0899_OFFST_DC_COMP 2
406#define STB0899_WIDTH_DC_COMP 1
407#define STB0899_MODMODE (0x03 << 0)
408#define STB0899_OFFST_MODMODE 0
409#define STB0899_WIDTH_MODMODE 2
410
411#define STB0899_OFF0_IF_AGC_CNTRL 0xf320
412#define STB0899_BASE_IF_AGC_CNTRL 0x00000000
413#define STB0899_IF_GAIN_INIT (0x3fff << 13)
414#define STB0899_OFFST_IF_GAIN_INIT 13
415#define STB0899_WIDTH_IF_GAIN_INIT 14
416#define STB0899_IF_GAIN_SENSE (0x01 << 12)
417#define STB0899_OFFST_IF_GAIN_SENSE 12
418#define STB0899_WIDTH_IF_GAIN_SENSE 1
419#define STB0899_IF_LOOP_GAIN (0x0f << 8)
420#define STB0899_OFFST_IF_LOOP_GAIN 8
421#define STB0899_WIDTH_IF_LOOP_GAIN 4
422#define STB0899_IF_LD_GAIN_INIT (0x01 << 7)
423#define STB0899_OFFST_IF_LD_GAIN_INIT 7
424#define STB0899_WIDTH_IF_LD_GAIN_INIT 1
425#define STB0899_IF_AGC_REF (0x7f << 0)
426#define STB0899_OFFST_IF_AGC_REF 0
427#define STB0899_WIDTH_IF_AGC_REF 7
428
429#define STB0899_OFF0_BB_AGC_CNTRL 0xf324
430#define STB0899_BASE_BB_AGC_CNTRL 0x00000000
431#define STB0899_BB_GAIN_INIT (0x3fff << 12)
432#define STB0899_OFFST_BB_GAIN_INIT 12
433#define STB0899_WIDTH_BB_GAIN_INIT 14
434#define STB0899_BB_LOOP_GAIN (0x0f << 8)
435#define STB0899_OFFST_BB_LOOP_GAIN 8
436#define STB0899_WIDTH_BB_LOOP_GAIN 4
437#define STB0899_BB_LD_GAIN_INIT (0x01 << 7)
438#define STB0899_OFFST_BB_LD_GAIN_INIT 7
439#define STB0899_WIDTH_BB_LD_GAIN_INIT 1
440#define STB0899_BB_AGC_REF (0x7f << 0)
441#define STB0899_OFFST_BB_AGC_REF 0
442#define STB0899_WIDTH_BB_AGC_REF 7
443
444#define STB0899_OFF0_CRL_CNTRL 0xf328
445#define STB0899_BASE_CRL_CNTRL 0x00000000
446#define STB0899_CRL_LOCK_CLEAR (0x01 << 5)
447#define STB0899_OFFST_CRL_LOCK_CLEAR 5
448#define STB0899_WIDTH_CRL_LOCK_CLEAR 1
449#define STB0899_CRL_SWPR_CLEAR (0x01 << 4)
450#define STB0899_OFFST_CRL_SWPR_CLEAR 4
451#define STB0899_WIDTH_CRL_SWPR_CLEAR 1
452#define STB0899_CRL_SWP_ENA (0x01 << 3)
453#define STB0899_OFFST_CRL_SWP_ENA 3
454#define STB0899_WIDTH_CRL_SWP_ENA 1
455#define STB0899_CRL_DET_SEL (0x01 << 2)
456#define STB0899_OFFST_CRL_DET_SEL 2
457#define STB0899_WIDTH_CRL_DET_SEL 1
458#define STB0899_CRL_SENSE (0x01 << 1)
459#define STB0899_OFFST_CRL_SENSE 1
460#define STB0899_WIDTH_CRL_SENSE 1
461#define STB0899_CRL_PHSERR_CLEAR (0x01 << 0)
462#define STB0899_OFFST_CRL_PHSERR_CLEAR 0
463#define STB0899_WIDTH_CRL_PHSERR_CLEAR 1
464
465#define STB0899_OFF0_CRL_PHS_INIT 0xf32c
466#define STB0899_BASE_CRL_PHS_INIT 0x00000000
467#define STB0899_CRL_PHS_INIT_31 (0x1 << 30)
468#define STB0899_OFFST_CRL_PHS_INIT_31 30
469#define STB0899_WIDTH_CRL_PHS_INIT_31 1
470#define STB0899_CRL_LD_INIT_PHASE (0x1 << 24)
471#define STB0899_OFFST_CRL_LD_INIT_PHASE 24
472#define STB0899_WIDTH_CRL_LD_INIT_PHASE 1
473#define STB0899_CRL_INIT_PHASE (0xffffff << 0)
474#define STB0899_OFFST_CRL_INIT_PHASE 0
475#define STB0899_WIDTH_CRL_INIT_PHASE 24
476
477#define STB0899_OFF0_CRL_FREQ_INIT 0xf330
478#define STB0899_BASE_CRL_FREQ_INIT 0x00000000
479#define STB0899_CRL_FREQ_INIT_31 (0x1 << 30)
480#define STB0899_OFFST_CRL_FREQ_INIT_31 30
481#define STB0899_WIDTH_CRL_FREQ_INIT_31 1
482#define STB0899_CRL_LD_FREQ_INIT (0x1 << 24)
483#define STB0899_OFFST_CRL_LD_FREQ_INIT 24
484#define STB0899_WIDTH_CRL_LD_FREQ_INIT 1
485#define STB0899_CRL_FREQ_INIT (0xffffff << 0)
486#define STB0899_OFFST_CRL_FREQ_INIT 0
487#define STB0899_WIDTH_CRL_FREQ_INIT 24
488
489#define STB0899_OFF0_CRL_LOOP_GAIN 0xf334
490#define STB0899_BASE_CRL_LOOP_GAIN 0x00000000
491#define STB0899_KCRL2_RSHFT (0xf << 16)
492#define STB0899_OFFST_KCRL2_RSHFT 16
493#define STB0899_WIDTH_KCRL2_RSHFT 4
494#define STB0899_KCRL1 (0xf << 12)
495#define STB0899_OFFST_KCRL1 12
496#define STB0899_WIDTH_KCRL1 4
497#define STB0899_KCRL1_RSHFT (0xf << 8)
498#define STB0899_OFFST_KCRL1_RSHFT 8
499#define STB0899_WIDTH_KCRL1_RSHFT 4
500#define STB0899_KCRL0 (0xf << 4)
501#define STB0899_OFFST_KCRL0 4
502#define STB0899_WIDTH_KCRL0 4
503#define STB0899_KCRL0_RSHFT (0xf << 0)
504#define STB0899_OFFST_KCRL0_RSHFT 0
505#define STB0899_WIDTH_KCRL0_RSHFT 4
506
507#define STB0899_OFF0_CRL_NOM_FREQ 0xf338
508#define STB0899_BASE_CRL_NOM_FREQ 0x00000000
509#define STB0899_CRL_NOM_FREQ (0x3fffffff << 0)
510#define STB0899_OFFST_CRL_NOM_FREQ 0
511#define STB0899_WIDTH_CRL_NOM_FREQ 30
512
513#define STB0899_OFF0_CRL_SWP_RATE 0xf33c
514#define STB0899_BASE_CRL_SWP_RATE 0x00000000
515#define STB0899_CRL_SWP_RATE (0x3fffffff << 0)
516#define STB0899_OFFST_CRL_SWP_RATE 0
517#define STB0899_WIDTH_CRL_SWP_RATE 30
518
519#define STB0899_OFF0_CRL_MAX_SWP 0xf340
520#define STB0899_BASE_CRL_MAX_SWP 0x00000000
521#define STB0899_CRL_MAX_SWP (0x3fffffff << 0)
522#define STB0899_OFFST_CRL_MAX_SWP 0
523#define STB0899_WIDTH_CRL_MAX_SWP 30
524
525#define STB0899_OFF0_CRL_LK_CNTRL 0xf344
526#define STB0899_BASE_CRL_LK_CNTRL 0x00000000
527
528#define STB0899_OFF0_DECIM_CNTRL 0xf348
529#define STB0899_BASE_DECIM_CNTRL 0x00000000
530#define STB0899_BAND_LIMIT_B (0x01 << 5)
531#define STB0899_OFFST_BAND_LIMIT_B 5
532#define STB0899_WIDTH_BAND_LIMIT_B 1
533#define STB0899_WIN_SEL (0x03 << 3)
534#define STB0899_OFFST_WIN_SEL 3
535#define STB0899_WIDTH_WIN_SEL 2
536#define STB0899_DECIM_RATE (0x07 << 0)
537#define STB0899_OFFST_DECIM_RATE 0
538#define STB0899_WIDTH_DECIM_RATE 3
539
540#define STB0899_OFF0_BTR_CNTRL 0xf34c
541#define STB0899_BASE_BTR_CNTRL 0x00000000
542#define STB0899_BTR_FREQ_CORR (0x7ff << 4)
543#define STB0899_OFFST_BTR_FREQ_CORR 4
544#define STB0899_WIDTH_BTR_FREQ_CORR 11
545#define STB0899_BTR_CLR_LOCK (0x01 << 3)
546#define STB0899_OFFST_BTR_CLR_LOCK 3
547#define STB0899_WIDTH_BTR_CLR_LOCK 1
548#define STB0899_BTR_SENSE (0x01 << 2)
549#define STB0899_OFFST_BTR_SENSE 2
550#define STB0899_WIDTH_BTR_SENSE 1
551#define STB0899_BTR_ERR_ENA (0x01 << 1)
552#define STB0899_OFFST_BTR_ERR_ENA 1
553#define STB0899_WIDTH_BTR_ERR_ENA 1
554#define STB0899_INTRP_PHS_SENSE (0x01 << 0)
555#define STB0899_OFFST_INTRP_PHS_SENSE 0
556#define STB0899_WIDTH_INTRP_PHS_SENSE 1
557
558#define STB0899_OFF0_BTR_LOOP_GAIN 0xf350
559#define STB0899_BASE_BTR_LOOP_GAIN 0x00000000
560#define STB0899_KBTR2_RSHFT (0x0f << 16)
561#define STB0899_OFFST_KBTR2_RSHFT 16
562#define STB0899_WIDTH_KBTR2_RSHFT 4
563#define STB0899_KBTR1 (0x0f << 12)
564#define STB0899_OFFST_KBTR1 12
565#define STB0899_WIDTH_KBTR1 4
566#define STB0899_KBTR1_RSHFT (0x0f << 8)
567#define STB0899_OFFST_KBTR1_RSHFT 8
568#define STB0899_WIDTH_KBTR1_RSHFT 4
569#define STB0899_KBTR0 (0x0f << 4)
570#define STB0899_OFFST_KBTR0 4
571#define STB0899_WIDTH_KBTR0 4
572#define STB0899_KBTR0_RSHFT (0x0f << 0)
573#define STB0899_OFFST_KBTR0_RSHFT 0
574#define STB0899_WIDTH_KBTR0_RSHFT 4
575
576#define STB0899_OFF0_BTR_PHS_INIT 0xf354
577#define STB0899_BASE_BTR_PHS_INIT 0x00000000
578#define STB0899_BTR_LD_PHASE_INIT (0x01 << 28)
579#define STB0899_OFFST_BTR_LD_PHASE_INIT 28
580#define STB0899_WIDTH_BTR_LD_PHASE_INIT 1
581#define STB0899_BTR_INIT_PHASE (0xfffffff << 0)
582#define STB0899_OFFST_BTR_INIT_PHASE 0
583#define STB0899_WIDTH_BTR_INIT_PHASE 28
584
585#define STB0899_OFF0_BTR_FREQ_INIT 0xf358
586#define STB0899_BASE_BTR_FREQ_INIT 0x00000000
587#define STB0899_BTR_LD_FREQ_INIT (1 << 28)
588#define STB0899_OFFST_BTR_LD_FREQ_INIT 28
589#define STB0899_WIDTH_BTR_LD_FREQ_INIT 1
590#define STB0899_BTR_FREQ_INIT (0xfffffff << 0)
591#define STB0899_OFFST_BTR_FREQ_INIT 0
592#define STB0899_WIDTH_BTR_FREQ_INIT 28
593
594#define STB0899_OFF0_BTR_NOM_FREQ 0xf35c
595#define STB0899_BASE_BTR_NOM_FREQ 0x00000000
596#define STB0899_BTR_NOM_FREQ (0xfffffff << 0)
597#define STB0899_OFFST_BTR_NOM_FREQ 0
598#define STB0899_WIDTH_BTR_NOM_FREQ 28
599
600#define STB0899_OFF0_BTR_LK_CNTRL 0xf360
601#define STB0899_BASE_BTR_LK_CNTRL 0x00000000
602#define STB0899_BTR_MIN_ENERGY (0x0f << 24)
603#define STB0899_OFFST_BTR_MIN_ENERGY 24
604#define STB0899_WIDTH_BTR_MIN_ENERGY 4
605#define STB0899_BTR_LOCK_TH_LO (0xff << 16)
606#define STB0899_OFFST_BTR_LOCK_TH_LO 16
607#define STB0899_WIDTH_BTR_LOCK_TH_LO 8
608#define STB0899_BTR_LOCK_TH_HI (0xff << 8)
609#define STB0899_OFFST_BTR_LOCK_TH_HI 8
610#define STB0899_WIDTH_BTR_LOCK_TH_HI 8
611#define STB0899_BTR_LOCK_GAIN (0x03 << 6)
612#define STB0899_OFFST_BTR_LOCK_GAIN 6
613#define STB0899_WIDTH_BTR_LOCK_GAIN 2
614#define STB0899_BTR_LOCK_LEAK (0x3f << 0)
615#define STB0899_OFFST_BTR_LOCK_LEAK 0
616#define STB0899_WIDTH_BTR_LOCK_LEAK 6
617
618#define STB0899_OFF0_DECN_CNTRL 0xf364
619#define STB0899_BASE_DECN_CNTRL 0x00000000
620
621#define STB0899_OFF0_TP_CNTRL 0xf368
622#define STB0899_BASE_TP_CNTRL 0x00000000
623
624#define STB0899_OFF0_TP_BUF_STATUS 0xf36c
625#define STB0899_BASE_TP_BUF_STATUS 0x00000000
626#define STB0899_TP_BUFFER_FULL (1 << 0)
627
628#define STB0899_OFF0_DC_ESTIM 0xf37c
629#define STB0899_BASE_DC_ESTIM 0x0000
630#define STB0899_I_DC_ESTIMATE (0xff << 8)
631#define STB0899_OFFST_I_DC_ESTIMATE 8
632#define STB0899_WIDTH_I_DC_ESTIMATE 8
633#define STB0899_Q_DC_ESTIMATE (0xff << 0)
634#define STB0899_OFFST_Q_DC_ESTIMATE 0
635#define STB0899_WIDTH_Q_DC_ESTIMATE 8
636
637#define STB0899_OFF0_FLL_CNTRL 0xf310
638#define STB0899_BASE_FLL_CNTRL 0x00000020
639#define STB0899_CRL_FLL_ACC (0x01 << 4)
640#define STB0899_OFFST_CRL_FLL_ACC 4
641#define STB0899_WIDTH_CRL_FLL_ACC 1
642#define STB0899_FLL_AVG_PERIOD (0x0f << 0)
643#define STB0899_OFFST_FLL_AVG_PERIOD 0
644#define STB0899_WIDTH_FLL_AVG_PERIOD 4
645
646#define STB0899_OFF0_FLL_FREQ_WD 0xf314
647#define STB0899_BASE_FLL_FREQ_WD 0x00000020
648#define STB0899_FLL_FREQ_WD (0xffffffff << 0)
649#define STB0899_OFFST_FLL_FREQ_WD 0
650#define STB0899_WIDTH_FLL_FREQ_WD 32
651
652#define STB0899_OFF0_ANTI_ALIAS_SEL 0xf358
653#define STB0899_BASE_ANTI_ALIAS_SEL 0x00000020
654#define STB0899_ANTI_ALIAS_SELB (0x03 << 0)
655#define STB0899_OFFST_ANTI_ALIAS_SELB 0
656#define STB0899_WIDTH_ANTI_ALIAS_SELB 2
657
658#define STB0899_OFF0_RRC_ALPHA 0xf35c
659#define STB0899_BASE_RRC_ALPHA 0x00000020
660#define STB0899_RRC_ALPHA (0x03 << 0)
661#define STB0899_OFFST_RRC_ALPHA 0
662#define STB0899_WIDTH_RRC_ALPHA 2
663
664#define STB0899_OFF0_DC_ADAPT_LSHFT 0xf360
665#define STB0899_BASE_DC_ADAPT_LSHFT 0x00000020
666#define STB0899_DC_ADAPT_LSHFT (0x077 << 0)
667#define STB0899_OFFST_DC_ADAPT_LSHFT 0
668#define STB0899_WIDTH_DC_ADAPT_LSHFT 3
669
670#define STB0899_OFF0_IMB_OFFSET 0xf364
671#define STB0899_BASE_IMB_OFFSET 0x00000020
672#define STB0899_PHS_IMB_COMP (0xff << 8)
673#define STB0899_OFFST_PHS_IMB_COMP 8
674#define STB0899_WIDTH_PHS_IMB_COMP 8
675#define STB0899_AMPL_IMB_COMP (0xff << 0)
676#define STB0899_OFFST_AMPL_IMB_COMP 0
677#define STB0899_WIDTH_AMPL_IMB_COMP 8
678
679#define STB0899_OFF0_IMB_ESTIMATE 0xf368
680#define STB0899_BASE_IMB_ESTIMATE 0x00000020
681#define STB0899_PHS_IMB_ESTIMATE (0xff << 8)
682#define STB0899_OFFST_PHS_IMB_ESTIMATE 8
683#define STB0899_WIDTH_PHS_IMB_ESTIMATE 8
684#define STB0899_AMPL_IMB_ESTIMATE (0xff << 0)
685#define STB0899_OFFST_AMPL_IMB_ESTIMATE 0
686#define STB0899_WIDTH_AMPL_IMB_ESTIMATE 8
687
688#define STB0899_OFF0_IMB_CNTRL 0xf36c
689#define STB0899_BASE_IMB_CNTRL 0x00000020
690#define STB0899_PHS_ADAPT_LSHFT (0x07 << 4)
691#define STB0899_OFFST_PHS_ADAPT_LSHFT 4
692#define STB0899_WIDTH_PHS_ADAPT_LSHFT 3
693#define STB0899_AMPL_ADAPT_LSHFT (0x07 << 1)
694#define STB0899_OFFST_AMPL_ADAPT_LSHFT 1
695#define STB0899_WIDTH_AMPL_ADAPT_LSHFT 3
696#define STB0899_IMB_COMP (0x01 << 0)
697#define STB0899_OFFST_IMB_COMP 0
698#define STB0899_WIDTH_IMB_COMP 1
699
700#define STB0899_OFF0_IF_AGC_CNTRL2 0xf374
701#define STB0899_BASE_IF_AGC_CNTRL2 0x00000020
702#define STB0899_IF_AGC_LOCK_TH (0xff << 11)
703#define STB0899_OFFST_IF_AGC_LOCK_TH 11
704#define STB0899_WIDTH_IF_AGC_LOCK_TH 8
705#define STB0899_IF_AGC_SD_DIV (0xff << 3)
706#define STB0899_OFFST_IF_AGC_SD_DIV 3
707#define STB0899_WIDTH_IF_AGC_SD_DIV 8
708#define STB0899_IF_AGC_DUMP_PER (0x07 << 0)
709#define STB0899_OFFST_IF_AGC_DUMP_PER 0
710#define STB0899_WIDTH_IF_AGC_DUMP_PER 3
711
712#define STB0899_OFF0_DMD_CNTRL2 0xf378
713#define STB0899_BASE_DMD_CNTRL2 0x00000020
714#define STB0899_SPECTRUM_INVERT (0x01 << 2)
715#define STB0899_OFFST_SPECTRUM_INVERT 2
716#define STB0899_WIDTH_SPECTRUM_INVERT 1
717#define STB0899_AGC_MODE (0x01 << 1)
718#define STB0899_OFFST_AGC_MODE 1
719#define STB0899_WIDTH_AGC_MODE 1
720#define STB0899_CRL_FREQ_ADJ (0x01 << 0)
721#define STB0899_OFFST_CRL_FREQ_ADJ 0
722#define STB0899_WIDTH_CRL_FREQ_ADJ 1
723
724#define STB0899_OFF0_TP_BUFFER 0xf300
725#define STB0899_BASE_TP_BUFFER 0x00000040
726#define STB0899_TP_BUFFER_IN (0xffff << 0)
727#define STB0899_OFFST_TP_BUFFER_IN 0
728#define STB0899_WIDTH_TP_BUFFER_IN 16
729
730#define STB0899_OFF0_TP_BUFFER1 0xf304
731#define STB0899_BASE_TP_BUFFER1 0x00000040
732#define STB0899_OFF0_TP_BUFFER2 0xf308
733#define STB0899_BASE_TP_BUFFER2 0x00000040
734#define STB0899_OFF0_TP_BUFFER3 0xf30c
735#define STB0899_BASE_TP_BUFFER3 0x00000040
736#define STB0899_OFF0_TP_BUFFER4 0xf310
737#define STB0899_BASE_TP_BUFFER4 0x00000040
738#define STB0899_OFF0_TP_BUFFER5 0xf314
739#define STB0899_BASE_TP_BUFFER5 0x00000040
740#define STB0899_OFF0_TP_BUFFER6 0xf318
741#define STB0899_BASE_TP_BUFFER6 0x00000040
742#define STB0899_OFF0_TP_BUFFER7 0xf31c
743#define STB0899_BASE_TP_BUFFER7 0x00000040
744#define STB0899_OFF0_TP_BUFFER8 0xf320
745#define STB0899_BASE_TP_BUFFER8 0x00000040
746#define STB0899_OFF0_TP_BUFFER9 0xf324
747#define STB0899_BASE_TP_BUFFER9 0x00000040
748#define STB0899_OFF0_TP_BUFFER10 0xf328
749#define STB0899_BASE_TP_BUFFER10 0x00000040
750#define STB0899_OFF0_TP_BUFFER11 0xf32c
751#define STB0899_BASE_TP_BUFFER11 0x00000040
752#define STB0899_OFF0_TP_BUFFER12 0xf330
753#define STB0899_BASE_TP_BUFFER12 0x00000040
754#define STB0899_OFF0_TP_BUFFER13 0xf334
755#define STB0899_BASE_TP_BUFFER13 0x00000040
756#define STB0899_OFF0_TP_BUFFER14 0xf338
757#define STB0899_BASE_TP_BUFFER14 0x00000040
758#define STB0899_OFF0_TP_BUFFER15 0xf33c
759#define STB0899_BASE_TP_BUFFER15 0x00000040
760#define STB0899_OFF0_TP_BUFFER16 0xf340
761#define STB0899_BASE_TP_BUFFER16 0x00000040
762#define STB0899_OFF0_TP_BUFFER17 0xf344
763#define STB0899_BASE_TP_BUFFER17 0x00000040
764#define STB0899_OFF0_TP_BUFFER18 0xf348
765#define STB0899_BASE_TP_BUFFER18 0x00000040
766#define STB0899_OFF0_TP_BUFFER19 0xf34c
767#define STB0899_BASE_TP_BUFFER19 0x00000040
768#define STB0899_OFF0_TP_BUFFER20 0xf350
769#define STB0899_BASE_TP_BUFFER20 0x00000040
770#define STB0899_OFF0_TP_BUFFER21 0xf354
771#define STB0899_BASE_TP_BUFFER21 0x00000040
772#define STB0899_OFF0_TP_BUFFER22 0xf358
773#define STB0899_BASE_TP_BUFFER22 0x00000040
774#define STB0899_OFF0_TP_BUFFER23 0xf35c
775#define STB0899_BASE_TP_BUFFER23 0x00000040
776#define STB0899_OFF0_TP_BUFFER24 0xf360
777#define STB0899_BASE_TP_BUFFER24 0x00000040
778#define STB0899_OFF0_TP_BUFFER25 0xf364
779#define STB0899_BASE_TP_BUFFER25 0x00000040
780#define STB0899_OFF0_TP_BUFFER26 0xf368
781#define STB0899_BASE_TP_BUFFER26 0x00000040
782#define STB0899_OFF0_TP_BUFFER27 0xf36c
783#define STB0899_BASE_TP_BUFFER27 0x00000040
784#define STB0899_OFF0_TP_BUFFER28 0xf370
785#define STB0899_BASE_TP_BUFFER28 0x00000040
786#define STB0899_OFF0_TP_BUFFER29 0xf374
787#define STB0899_BASE_TP_BUFFER29 0x00000040
788#define STB0899_OFF0_TP_BUFFER30 0xf378
789#define STB0899_BASE_TP_BUFFER30 0x00000040
790#define STB0899_OFF0_TP_BUFFER31 0xf37c
791#define STB0899_BASE_TP_BUFFER31 0x00000040
792#define STB0899_OFF0_TP_BUFFER32 0xf300
793#define STB0899_BASE_TP_BUFFER32 0x00000060
794#define STB0899_OFF0_TP_BUFFER33 0xf304
795#define STB0899_BASE_TP_BUFFER33 0x00000060
796#define STB0899_OFF0_TP_BUFFER34 0xf308
797#define STB0899_BASE_TP_BUFFER34 0x00000060
798#define STB0899_OFF0_TP_BUFFER35 0xf30c
799#define STB0899_BASE_TP_BUFFER35 0x00000060
800#define STB0899_OFF0_TP_BUFFER36 0xf310
801#define STB0899_BASE_TP_BUFFER36 0x00000060
802#define STB0899_OFF0_TP_BUFFER37 0xf314
803#define STB0899_BASE_TP_BUFFER37 0x00000060
804#define STB0899_OFF0_TP_BUFFER38 0xf318
805#define STB0899_BASE_TP_BUFFER38 0x00000060
806#define STB0899_OFF0_TP_BUFFER39 0xf31c
807#define STB0899_BASE_TP_BUFFER39 0x00000060
808#define STB0899_OFF0_TP_BUFFER40 0xf320
809#define STB0899_BASE_TP_BUFFER40 0x00000060
810#define STB0899_OFF0_TP_BUFFER41 0xf324
811#define STB0899_BASE_TP_BUFFER41 0x00000060
812#define STB0899_OFF0_TP_BUFFER42 0xf328
813#define STB0899_BASE_TP_BUFFER42 0x00000060
814#define STB0899_OFF0_TP_BUFFER43 0xf32c
815#define STB0899_BASE_TP_BUFFER43 0x00000060
816#define STB0899_OFF0_TP_BUFFER44 0xf330
817#define STB0899_BASE_TP_BUFFER44 0x00000060
818#define STB0899_OFF0_TP_BUFFER45 0xf334
819#define STB0899_BASE_TP_BUFFER45 0x00000060
820#define STB0899_OFF0_TP_BUFFER46 0xf338
821#define STB0899_BASE_TP_BUFFER46 0x00000060
822#define STB0899_OFF0_TP_BUFFER47 0xf33c
823#define STB0899_BASE_TP_BUFFER47 0x00000060
824#define STB0899_OFF0_TP_BUFFER48 0xf340
825#define STB0899_BASE_TP_BUFFER48 0x00000060
826#define STB0899_OFF0_TP_BUFFER49 0xf344
827#define STB0899_BASE_TP_BUFFER49 0x00000060
828#define STB0899_OFF0_TP_BUFFER50 0xf348
829#define STB0899_BASE_TP_BUFFER50 0x00000060
830#define STB0899_OFF0_TP_BUFFER51 0xf34c
831#define STB0899_BASE_TP_BUFFER51 0x00000060
832#define STB0899_OFF0_TP_BUFFER52 0xf350
833#define STB0899_BASE_TP_BUFFER52 0x00000060
834#define STB0899_OFF0_TP_BUFFER53 0xf354
835#define STB0899_BASE_TP_BUFFER53 0x00000060
836#define STB0899_OFF0_TP_BUFFER54 0xf358
837#define STB0899_BASE_TP_BUFFER54 0x00000060
838#define STB0899_OFF0_TP_BUFFER55 0xf35c
839#define STB0899_BASE_TP_BUFFER55 0x00000060
840#define STB0899_OFF0_TP_BUFFER56 0xf360
841#define STB0899_BASE_TP_BUFFER56 0x00000060
842#define STB0899_OFF0_TP_BUFFER57 0xf364
843#define STB0899_BASE_TP_BUFFER57 0x00000060
844#define STB0899_OFF0_TP_BUFFER58 0xf368
845#define STB0899_BASE_TP_BUFFER58 0x00000060
846#define STB0899_OFF0_TP_BUFFER59 0xf36c
847#define STB0899_BASE_TP_BUFFER59 0x00000060
848#define STB0899_OFF0_TP_BUFFER60 0xf370
849#define STB0899_BASE_TP_BUFFER60 0x00000060
850#define STB0899_OFF0_TP_BUFFER61 0xf374
851#define STB0899_BASE_TP_BUFFER61 0x00000060
852#define STB0899_OFF0_TP_BUFFER62 0xf378
853#define STB0899_BASE_TP_BUFFER62 0x00000060
854#define STB0899_OFF0_TP_BUFFER63 0xf37c
855#define STB0899_BASE_TP_BUFFER63 0x00000060
856
857#define STB0899_OFF0_RESET_CNTRL 0xf300
858#define STB0899_BASE_RESET_CNTRL 0x00000400
859#define STB0899_DVBS2_RESET (0x01 << 0)
860#define STB0899_OFFST_DVBS2_RESET 0
861#define STB0899_WIDTH_DVBS2_RESET 1
862
863#define STB0899_OFF0_ACM_ENABLE 0xf304
864#define STB0899_BASE_ACM_ENABLE 0x00000400
865#define STB0899_ACM_ENABLE 1
866
867#define STB0899_OFF0_DESCR_CNTRL 0xf30c
868#define STB0899_BASE_DESCR_CNTRL 0x00000400
869#define STB0899_OFFST_DESCR_CNTRL 0
870#define STB0899_WIDTH_DESCR_CNTRL 16
871
872#define STB0899_OFF0_UWP_CNTRL1 0xf320
873#define STB0899_BASE_UWP_CNTRL1 0x00000400
874#define STB0899_UWP_TH_SOF (0x7fff << 11)
875#define STB0899_OFFST_UWP_TH_SOF 11
876#define STB0899_WIDTH_UWP_TH_SOF 15
877#define STB0899_UWP_ESN0_QUANT (0xff << 3)
878#define STB0899_OFFST_UWP_ESN0_QUANT 3
879#define STB0899_WIDTH_UWP_ESN0_QUANT 8
880#define STB0899_UWP_ESN0_AVE (0x03 << 1)
881#define STB0899_OFFST_UWP_ESN0_AVE 1
882#define STB0899_WIDTH_UWP_ESN0_AVE 2
883#define STB0899_UWP_START (0x01 << 0)
884#define STB0899_OFFST_UWP_START 0
885#define STB0899_WIDTH_UWP_START 1
886
887#define STB0899_OFF0_UWP_CNTRL2 0xf324
888#define STB0899_BASE_UWP_CNTRL2 0x00000400
889#define STB0899_UWP_MISS_TH (0xff << 16)
890#define STB0899_OFFST_UWP_MISS_TH 16
891#define STB0899_WIDTH_UWP_MISS_TH 8
892#define STB0899_FE_FINE_TRK (0xff << 8)
893#define STB0899_OFFST_FE_FINE_TRK 8
894#define STB0899_WIDTH_FE_FINE_TRK 8
895#define STB0899_FE_COARSE_TRK (0xff << 0)
896#define STB0899_OFFST_FE_COARSE_TRK 0
897#define STB0899_WIDTH_FE_COARSE_TRK 8
898
899#define STB0899_OFF0_UWP_STAT1 0xf328
900#define STB0899_BASE_UWP_STAT1 0x00000400
901#define STB0899_UWP_STATE (0x03ff << 15)
902#define STB0899_OFFST_UWP_STATE 15
903#define STB0899_WIDTH_UWP_STATE 10
904#define STB0899_UW_MAX_PEAK (0x7fff << 0)
905#define STB0899_OFFST_UW_MAX_PEAK 0
906#define STB0899_WIDTH_UW_MAX_PEAK 15
907
908#define STB0899_OFF0_UWP_STAT2 0xf32c
909#define STB0899_BASE_UWP_STAT2 0x00000400
910#define STB0899_ESNO_EST (0x07ffff << 7)
911#define STB0899_OFFST_ESN0_EST 7
912#define STB0899_WIDTH_ESN0_EST 19
913#define STB0899_UWP_DECODE_MOD (0x7f << 0)
914#define STB0899_OFFST_UWP_DECODE_MOD 0
915#define STB0899_WIDTH_UWP_DECODE_MOD 7
916
917#define STB0899_OFF0_DMD_CORE_ID 0xf334
918#define STB0899_BASE_DMD_CORE_ID 0x00000400
919#define STB0899_CORE_ID (0xffffffff << 0)
920#define STB0899_OFFST_CORE_ID 0
921#define STB0899_WIDTH_CORE_ID 32
922
923#define STB0899_OFF0_DMD_VERSION_ID 0xf33c
924#define STB0899_BASE_DMD_VERSION_ID 0x00000400
925#define STB0899_VERSION_ID (0xff << 0)
926#define STB0899_OFFST_VERSION_ID 0
927#define STB0899_WIDTH_VERSION_ID 8
928
929#define STB0899_OFF0_DMD_STAT2 0xf340
930#define STB0899_BASE_DMD_STAT2 0x00000400
931#define STB0899_CSM_LOCK (0x01 << 1)
932#define STB0899_OFFST_CSM_LOCK 1
933#define STB0899_WIDTH_CSM_LOCK 1
934#define STB0899_UWP_LOCK (0x01 << 0)
935#define STB0899_OFFST_UWP_LOCK 0
936#define STB0899_WIDTH_UWP_LOCK 1
937
938#define STB0899_OFF0_FREQ_ADJ_SCALE 0xf344
939#define STB0899_BASE_FREQ_ADJ_SCALE 0x00000400
940#define STB0899_FREQ_ADJ_SCALE (0x0fff << 0)
941#define STB0899_OFFST_FREQ_ADJ_SCALE 0
942#define STB0899_WIDTH_FREQ_ADJ_SCALE 12
943
944#define STB0899_OFF0_UWP_CNTRL3 0xf34c
945#define STB0899_BASE_UWP_CNTRL3 0x00000400
946#define STB0899_UWP_TH_TRACK (0x7fff << 15)
947#define STB0899_OFFST_UWP_TH_TRACK 15
948#define STB0899_WIDTH_UWP_TH_TRACK 15
949#define STB0899_UWP_TH_ACQ (0x7fff << 0)
950#define STB0899_OFFST_UWP_TH_ACQ 0
951#define STB0899_WIDTH_UWP_TH_ACQ 15
952
953#define STB0899_OFF0_SYM_CLK_SEL 0xf350
954#define STB0899_BASE_SYM_CLK_SEL 0x00000400
955#define STB0899_SYM_CLK_SEL (0x03 << 0)
956#define STB0899_OFFST_SYM_CLK_SEL 0
957#define STB0899_WIDTH_SYM_CLK_SEL 2
958
959#define STB0899_OFF0_SOF_SRCH_TO 0xf354
960#define STB0899_BASE_SOF_SRCH_TO 0x00000400
961#define STB0899_SOF_SEARCH_TIMEOUT (0x3fffff << 0)
962#define STB0899_OFFST_SOF_SEARCH_TIMEOUT 0
963#define STB0899_WIDTH_SOF_SEARCH_TIMEOUT 22
964
965#define STB0899_OFF0_ACQ_CNTRL1 0xf358
966#define STB0899_BASE_ACQ_CNTRL1 0x00000400
967#define STB0899_FE_FINE_ACQ (0xff << 8)
968#define STB0899_OFFST_FE_FINE_ACQ 8
969#define STB0899_WIDTH_FE_FINE_ACQ 8
970#define STB0899_FE_COARSE_ACQ (0xff << 0)
971#define STB0899_OFFST_FE_COARSE_ACQ 0
972#define STB0899_WIDTH_FE_COARSE_ACQ 8
973
974#define STB0899_OFF0_ACQ_CNTRL2 0xf35c
975#define STB0899_BASE_ACQ_CNTRL2 0x00000400
976#define STB0899_ZIGZAG (0x01 << 25)
977#define STB0899_OFFST_ZIGZAG 25
978#define STB0899_WIDTH_ZIGZAG 1
979#define STB0899_NUM_STEPS (0xff << 17)
980#define STB0899_OFFST_NUM_STEPS 17
981#define STB0899_WIDTH_NUM_STEPS 8
982#define STB0899_FREQ_STEPSIZE (0x1ffff << 0)
983#define STB0899_OFFST_FREQ_STEPSIZE 0
984#define STB0899_WIDTH_FREQ_STEPSIZE 17
985
986#define STB0899_OFF0_ACQ_CNTRL3 0xf360
987#define STB0899_BASE_ACQ_CNTRL3 0x00000400
988#define STB0899_THRESHOLD_SCL (0x3f << 23)
989#define STB0899_OFFST_THRESHOLD_SCL 23
990#define STB0899_WIDTH_THRESHOLD_SCL 6
991#define STB0899_UWP_TH_SRCH (0x7fff << 8)
992#define STB0899_OFFST_UWP_TH_SRCH 8
993#define STB0899_WIDTH_UWP_TH_SRCH 15
994#define STB0899_AUTO_REACQUIRE (0x01 << 7)
995#define STB0899_OFFST_AUTO_REACQUIRE 7
996#define STB0899_WIDTH_AUTO_REACQUIRE 1
997#define STB0899_TRACK_LOCK_SEL (0x01 << 6)
998#define STB0899_OFFST_TRACK_LOCK_SEL 6
999#define STB0899_WIDTH_TRACK_LOCK_SEL 1
1000#define STB0899_ACQ_SEARCH_MODE (0x03 << 4)
1001#define STB0899_OFFST_ACQ_SEARCH_MODE 4
1002#define STB0899_WIDTH_ACQ_SEARCH_MODE 2
1003#define STB0899_CONFIRM_FRAMES (0x0f << 0)
1004#define STB0899_OFFST_CONFIRM_FRAMES 0
1005#define STB0899_WIDTH_CONFIRM_FRAMES 4
1006
1007#define STB0899_OFF0_FE_SETTLE 0xf364
1008#define STB0899_BASE_FE_SETTLE 0x00000400
1009#define STB0899_SETTLING_TIME (0x3fffff << 0)
1010#define STB0899_OFFST_SETTLING_TIME 0
1011#define STB0899_WIDTH_SETTLING_TIME 22
1012
1013#define STB0899_OFF0_AC_DWELL 0xf368
1014#define STB0899_BASE_AC_DWELL 0x00000400
1015#define STB0899_DWELL_TIME (0x3fffff << 0)
1016#define STB0899_OFFST_DWELL_TIME 0
1017#define STB0899_WIDTH_DWELL_TIME 22
1018
1019#define STB0899_OFF0_ACQUIRE_TRIG 0xf36c
1020#define STB0899_BASE_ACQUIRE_TRIG 0x00000400
1021#define STB0899_ACQUIRE (0x01 << 0)
1022#define STB0899_OFFST_ACQUIRE 0
1023#define STB0899_WIDTH_ACQUIRE 1
1024
1025#define STB0899_OFF0_LOCK_LOST 0xf370
1026#define STB0899_BASE_LOCK_LOST 0x00000400
1027#define STB0899_LOCK_LOST (0x01 << 0)
1028#define STB0899_OFFST_LOCK_LOST 0
1029#define STB0899_WIDTH_LOCK_LOST 1
1030
1031#define STB0899_OFF0_ACQ_STAT1 0xf374
1032#define STB0899_BASE_ACQ_STAT1 0x00000400
1033#define STB0899_STEP_FREQ (0x1fffff << 11)
1034#define STB0899_OFFST_STEP_FREQ 11
1035#define STB0899_WIDTH_STEP_FREQ 21
1036#define STB0899_ACQ_STATE (0x07 << 8)
1037#define STB0899_OFFST_ACQ_STATE 8
1038#define STB0899_WIDTH_ACQ_STATE 3
1039#define STB0899_UW_DETECT_COUNT (0xff << 0)
1040#define STB0899_OFFST_UW_DETECT_COUNT 0
1041#define STB0899_WIDTH_UW_DETECT_COUNT 8
1042
1043#define STB0899_OFF0_ACQ_TIMEOUT 0xf378
1044#define STB0899_BASE_ACQ_TIMEOUT 0x00000400
1045#define STB0899_ACQ_TIMEOUT (0x3fffff << 0)
1046#define STB0899_OFFST_ACQ_TIMEOUT 0
1047#define STB0899_WIDTH_ACQ_TIMEOUT 22
1048
1049#define STB0899_OFF0_ACQ_TIME 0xf37c
1050#define STB0899_BASE_ACQ_TIME 0x00000400
1051#define STB0899_ACQ_TIME_SYM (0xffffff << 0)
1052#define STB0899_OFFST_ACQ_TIME_SYM 0
1053#define STB0899_WIDTH_ACQ_TIME_SYM 24
1054
1055#define STB0899_OFF0_FINAL_AGC_CNTRL 0xf308
1056#define STB0899_BASE_FINAL_AGC_CNTRL 0x00000440
1057#define STB0899_FINAL_GAIN_INIT (0x3fff << 12)
1058#define STB0899_OFFST_FINAL_GAIN_INIT 12
1059#define STB0899_WIDTH_FINAL_GAIN_INIT 14
1060#define STB0899_FINAL_LOOP_GAIN (0x0f << 8)
1061#define STB0899_OFFST_FINAL_LOOP_GAIN 8
1062#define STB0899_WIDTH_FINAL_LOOP_GAIN 4
1063#define STB0899_FINAL_LD_GAIN_INIT (0x01 << 7)
1064#define STB0899_OFFST_FINAL_LD_GAIN_INIT 7
1065#define STB0899_WIDTH_FINAL_LD_GAIN_INIT 1
1066#define STB0899_FINAL_AGC_REF (0x7f << 0)
1067#define STB0899_OFFST_FINAL_AGC_REF 0
1068#define STB0899_WIDTH_FINAL_AGC_REF 7
1069
1070#define STB0899_OFF0_FINAL_AGC_GAIN 0xf30c
1071#define STB0899_BASE_FINAL_AGC_GAIN 0x00000440
1072#define STB0899_FINAL_AGC_GAIN (0x3fff << 0)
1073#define STB0899_OFFST_FINAL_AGC_GAIN 0
1074#define STB0899_WIDTH_FINAL_AGC_GAIN 14
1075
1076#define STB0899_OFF0_EQUALIZER_INIT 0xf310
1077#define STB0899_BASE_EQUALIZER_INIT 0x00000440
1078#define STB0899_EQ_SRST (0x01 << 1)
1079#define STB0899_OFFST_EQ_SRST 1
1080#define STB0899_WIDTH_EQ_SRST 1
1081#define STB0899_EQ_INIT (0x01 << 0)
1082#define STB0899_OFFST_EQ_INIT 0
1083#define STB0899_WIDTH_EQ_INIT 1
1084
1085#define STB0899_OFF0_EQ_CNTRL 0xf314
1086#define STB0899_BASE_EQ_CNTRL 0x00000440
1087#define STB0899_EQ_ADAPT_MODE (0x01 << 18)
1088#define STB0899_OFFST_EQ_ADAPT_MODE 18
1089#define STB0899_WIDTH_EQ_ADAPT_MODE 1
1090#define STB0899_EQ_DELAY (0x0f << 14)
1091#define STB0899_OFFST_EQ_DELAY 14
1092#define STB0899_WIDTH_EQ_DELAY 4
1093#define STB0899_EQ_QUANT_LEVEL (0xff << 6)
1094#define STB0899_OFFST_EQ_QUANT_LEVEL 6
1095#define STB0899_WIDTH_EQ_QUANT_LEVEL 8
1096#define STB0899_EQ_DISABLE_UPDATE (0x01 << 5)
1097#define STB0899_OFFST_EQ_DISABLE_UPDATE 5
1098#define STB0899_WIDTH_EQ_DISABLE_UPDATE 1
1099#define STB0899_EQ_BYPASS (0x01 << 4)
1100#define STB0899_OFFST_EQ_BYPASS 4
1101#define STB0899_WIDTH_EQ_BYPASS 1
1102#define STB0899_EQ_SHIFT (0x0f << 0)
1103#define STB0899_OFFST_EQ_SHIFT 0
1104#define STB0899_WIDTH_EQ_SHIFT 4
1105
1106#define STB0899_OFF0_EQ_I_INIT_COEFF_0 0xf320
1107#define STB0899_OFF1_EQ_I_INIT_COEFF_1 0xf324
1108#define STB0899_OFF2_EQ_I_INIT_COEFF_2 0xf328
1109#define STB0899_OFF3_EQ_I_INIT_COEFF_3 0xf32c
1110#define STB0899_OFF4_EQ_I_INIT_COEFF_4 0xf330
1111#define STB0899_OFF5_EQ_I_INIT_COEFF_5 0xf334
1112#define STB0899_OFF6_EQ_I_INIT_COEFF_6 0xf338
1113#define STB0899_OFF7_EQ_I_INIT_COEFF_7 0xf33c
1114#define STB0899_OFF8_EQ_I_INIT_COEFF_8 0xf340
1115#define STB0899_OFF9_EQ_I_INIT_COEFF_9 0xf344
1116#define STB0899_OFFa_EQ_I_INIT_COEFF_10 0xf348
1117#define STB0899_BASE_EQ_I_INIT_COEFF_N 0x00000440
1118#define STB0899_EQ_I_INIT_COEFF_N (0x0fff << 0)
1119#define STB0899_OFFST_EQ_I_INIT_COEFF_N 0
1120#define STB0899_WIDTH_EQ_I_INIT_COEFF_N 12
1121
1122#define STB0899_OFF0_EQ_Q_INIT_COEFF_0 0xf350
1123#define STB0899_OFF1_EQ_Q_INIT_COEFF_1 0xf354
1124#define STB0899_OFF2_EQ_Q_INIT_COEFF_2 0xf358
1125#define STB0899_OFF3_EQ_Q_INIT_COEFF_3 0xf35c
1126#define STB0899_OFF4_EQ_Q_INIT_COEFF_4 0xf360
1127#define STB0899_OFF5_EQ_Q_INIT_COEFF_5 0xf364
1128#define STB0899_OFF6_EQ_Q_INIT_COEFF_6 0xf368
1129#define STB0899_OFF7_EQ_Q_INIT_COEFF_7 0xf36c
1130#define STB0899_OFF8_EQ_Q_INIT_COEFF_8 0xf370
1131#define STB0899_OFF9_EQ_Q_INIT_COEFF_9 0xf374
1132#define STB0899_OFFa_EQ_Q_INIT_COEFF_10 0xf378
1133#define STB0899_BASE_EQ_Q_INIT_COEFF_N 0x00000440
1134#define STB0899_EQ_Q_INIT_COEFF_N (0x0fff << 0)
1135#define STB0899_OFFST_EQ_Q_INIT_COEFF_N 0
1136#define STB0899_WIDTH_EQ_Q_INIT_COEFF_N 12
1137
1138#define STB0899_OFF0_EQ_I_OUT_COEFF_0 0xf300
1139#define STB0899_OFF1_EQ_I_OUT_COEFF_1 0xf304
1140#define STB0899_OFF2_EQ_I_OUT_COEFF_2 0xf308
1141#define STB0899_OFF3_EQ_I_OUT_COEFF_3 0xf30c
1142#define STB0899_OFF4_EQ_I_OUT_COEFF_4 0xf310
1143#define STB0899_OFF5_EQ_I_OUT_COEFF_5 0xf314
1144#define STB0899_OFF6_EQ_I_OUT_COEFF_6 0xf318
1145#define STB0899_OFF7_EQ_I_OUT_COEFF_7 0xf31c
1146#define STB0899_OFF8_EQ_I_OUT_COEFF_8 0xf320
1147#define STB0899_OFF9_EQ_I_OUT_COEFF_9 0xf324
1148#define STB0899_OFFa_EQ_I_OUT_COEFF_10 0xf328
1149#define STB0899_BASE_EQ_I_OUT_COEFF_N 0x00000460
1150#define STB0899_EQ_I_OUT_COEFF_N (0x0fff << 0)
1151#define STB0899_OFFST_EQ_I_OUT_COEFF_N 0
1152#define STB0899_WIDTH_EQ_I_OUT_COEFF_N 12
1153
1154#define STB0899_OFF0_EQ_Q_OUT_COEFF_0 0xf330
1155#define STB0899_OFF1_EQ_Q_OUT_COEFF_1 0xf334
1156#define STB0899_OFF2_EQ_Q_OUT_COEFF_2 0xf338
1157#define STB0899_OFF3_EQ_Q_OUT_COEFF_3 0xf33c
1158#define STB0899_OFF4_EQ_Q_OUT_COEFF_4 0xf340
1159#define STB0899_OFF5_EQ_Q_OUT_COEFF_5 0xf344
1160#define STB0899_OFF6_EQ_Q_OUT_COEFF_6 0xf348
1161#define STB0899_OFF7_EQ_Q_OUT_COEFF_7 0xf34c
1162#define STB0899_OFF8_EQ_Q_OUT_COEFF_8 0xf350
1163#define STB0899_OFF9_EQ_Q_OUT_COEFF_9 0xf354
1164#define STB0899_OFFa_EQ_Q_OUT_COEFF_10 0xf358
1165#define STB0899_BASE_EQ_Q_OUT_COEFF_N 0x00000460
1166#define STB0899_EQ_Q_OUT_COEFF_N (0x0fff << 0)
1167#define STB0899_OFFST_EQ_Q_OUT_COEFF_N 0
1168#define STB0899_WIDTH_EQ_Q_OUT_COEFF_N 12
1169
1170/* S2 FEC */
1171#define STB0899_OFF0_BLOCK_LNGTH 0xfa04
1172#define STB0899_BASE_BLOCK_LNGTH 0x00000000
1173#define STB0899_BLOCK_LENGTH (0xff << 0)
1174#define STB0899_OFFST_BLOCK_LENGTH 0
1175#define STB0899_WIDTH_BLOCK_LENGTH 8
1176
1177#define STB0899_OFF0_ROW_STR 0xfa08
1178#define STB0899_BASE_ROW_STR 0x00000000
1179#define STB0899_ROW_STRIDE (0xff << 0)
1180#define STB0899_OFFST_ROW_STRIDE 0
1181#define STB0899_WIDTH_ROW_STRIDE 8
1182
1183#define STB0899_OFF0_MAX_ITER 0xfa0c
1184#define STB0899_BASE_MAX_ITER 0x00000000
1185#define STB0899_MAX_ITERATIONS (0xff << 0)
1186#define STB0899_OFFST_MAX_ITERATIONS 0
1187#define STB0899_WIDTH_MAX_ITERATIONS 8
1188
1189#define STB0899_OFF0_BN_END_ADDR 0xfa10
1190#define STB0899_BASE_BN_END_ADDR 0x00000000
1191#define STB0899_BN_END_ADDR (0x0fff << 0)
1192#define STB0899_OFFST_BN_END_ADDR 0
1193#define STB0899_WIDTH_BN_END_ADDR 12
1194
1195#define STB0899_OFF0_CN_END_ADDR 0xfa14
1196#define STB0899_BASE_CN_END_ADDR 0x00000000
1197#define STB0899_CN_END_ADDR (0x0fff << 0)
1198#define STB0899_OFFST_CN_END_ADDR 0
1199#define STB0899_WIDTH_CN_END_ADDR 12
1200
1201#define STB0899_OFF0_INFO_LENGTH 0xfa1c
1202#define STB0899_BASE_INFO_LENGTH 0x00000000
1203#define STB0899_INFO_LENGTH (0xff << 0)
1204#define STB0899_OFFST_INFO_LENGTH 0
1205#define STB0899_WIDTH_INFO_LENGTH 8
1206
1207#define STB0899_OFF0_BOT_ADDR 0xfa20
1208#define STB0899_BASE_BOT_ADDR 0x00000000
1209#define STB0899_BOTTOM_BASE_ADDR (0x03ff << 0)
1210#define STB0899_OFFST_BOTTOM_BASE_ADDR 0
1211#define STB0899_WIDTH_BOTTOM_BASE_ADDR 10
1212
1213#define STB0899_OFF0_BCH_BLK_LN 0xfa24
1214#define STB0899_BASE_BCH_BLK_LN 0x00000000
1215#define STB0899_BCH_BLOCK_LENGTH (0xffff << 0)
1216#define STB0899_OFFST_BCH_BLOCK_LENGTH 0
1217#define STB0899_WIDTH_BCH_BLOCK_LENGTH 16
1218
1219#define STB0899_OFF0_BCH_T 0xfa28
1220#define STB0899_BASE_BCH_T 0x00000000
1221#define STB0899_BCH_T (0x0f << 0)
1222#define STB0899_OFFST_BCH_T 0
1223#define STB0899_WIDTH_BCH_T 4
1224
1225#define STB0899_OFF0_CNFG_MODE 0xfa00
1226#define STB0899_BASE_CNFG_MODE 0x00000800
1227#define STB0899_MODCOD (0x1f << 2)
1228#define STB0899_OFFST_MODCOD 2
1229#define STB0899_WIDTH_MODCOD 5
1230#define STB0899_MODCOD_SEL (0x01 << 1)
1231#define STB0899_OFFST_MODCOD_SEL 1
1232#define STB0899_WIDTH_MODCOD_SEL 1
1233#define STB0899_CONFIG_MODE (0x01 << 0)
1234#define STB0899_OFFST_CONFIG_MODE 0
1235#define STB0899_WIDTH_CONFIG_MODE 1
1236
1237#define STB0899_OFF0_LDPC_STAT 0xfa04
1238#define STB0899_BASE_LDPC_STAT 0x00000800
1239#define STB0899_ITERATION (0xff << 3)
1240#define STB0899_OFFST_ITERATION 3
1241#define STB0899_WIDTH_ITERATION 8
1242#define STB0899_LDPC_DEC_STATE (0x07 << 0)
1243#define STB0899_OFFST_LDPC_DEC_STATE 0
1244#define STB0899_WIDTH_LDPC_DEC_STATE 3
1245
1246#define STB0899_OFF0_ITER_SCALE 0xfa08
1247#define STB0899_BASE_ITER_SCALE 0x00000800
1248#define STB0899_ITERATION_SCALE (0xff << 0)
1249#define STB0899_OFFST_ITERATION_SCALE 0
1250#define STB0899_WIDTH_ITERATION_SCALE 8
1251
1252#define STB0899_OFF0_INPUT_MODE 0xfa0c
1253#define STB0899_BASE_INPUT_MODE 0x00000800
1254#define STB0899_SD_BLOCK1_STREAM0 (0x01 << 0)
1255#define STB0899_OFFST_SD_BLOCK1_STREAM0 0
1256#define STB0899_WIDTH_SD_BLOCK1_STREAM0 1
1257
1258#define STB0899_OFF0_LDPCDECRST 0xfa10
1259#define STB0899_BASE_LDPCDECRST 0x00000800
1260#define STB0899_LDPC_DEC_RST (0x01 << 0)
1261#define STB0899_OFFST_LDPC_DEC_RST 0
1262#define STB0899_WIDTH_LDPC_DEC_RST 1
1263
1264#define STB0899_OFF0_CLK_PER_BYTE_RW 0xfa14
1265#define STB0899_BASE_CLK_PER_BYTE_RW 0x00000800
1266#define STB0899_CLKS_PER_BYTE (0x0f << 0)
1267#define STB0899_OFFST_CLKS_PER_BYTE 0
1268#define STB0899_WIDTH_CLKS_PER_BYTE 5
1269
1270#define STB0899_OFF0_BCH_ERRORS 0xfa18
1271#define STB0899_BASE_BCH_ERRORS 0x00000800
1272#define STB0899_BCH_ERRORS (0x0f << 0)
1273#define STB0899_OFFST_BCH_ERRORS 0
1274#define STB0899_WIDTH_BCH_ERRORS 4
1275
1276#define STB0899_OFF0_LDPC_ERRORS 0xfa1c
1277#define STB0899_BASE_LDPC_ERRORS 0x00000800
1278#define STB0899_LDPC_ERRORS (0xffff << 0)
1279#define STB0899_OFFST_LDPC_ERRORS 0
1280#define STB0899_WIDTH_LDPC_ERRORS 16
1281
1282#define STB0899_OFF0_BCH_MODE 0xfa20
1283#define STB0899_BASE_BCH_MODE 0x00000800
1284#define STB0899_BCH_CORRECT_N (0x01 << 1)
1285#define STB0899_OFFST_BCH_CORRECT_N 1
1286#define STB0899_WIDTH_BCH_CORRECT_N 1
1287#define STB0899_FULL_BYPASS (0x01 << 0)
1288#define STB0899_OFFST_FULL_BYPASS 0
1289#define STB0899_WIDTH_FULL_BYPASS 1
1290
1291#define STB0899_OFF0_ERR_ACC_PER 0xfa24
1292#define STB0899_BASE_ERR_ACC_PER 0x00000800
1293#define STB0899_BCH_ERR_ACC_PERIOD (0x0f << 0)
1294#define STB0899_OFFST_BCH_ERR_ACC_PERIOD 0
1295#define STB0899_WIDTH_BCH_ERR_ACC_PERIOD 4
1296
1297#define STB0899_OFF0_BCH_ERR_ACC 0xfa28
1298#define STB0899_BASE_BCH_ERR_ACC 0x00000800
1299#define STB0899_BCH_ERR_ACCUM (0xff << 0)
1300#define STB0899_OFFST_BCH_ERR_ACCUM 0
1301#define STB0899_WIDTH_BCH_ERR_ACCUM 8
1302
1303#define STB0899_OFF0_FEC_CORE_ID_REG 0xfa2c
1304#define STB0899_BASE_FEC_CORE_ID_REG 0x00000800
1305#define STB0899_FEC_CORE_ID (0xffffffff << 0)
1306#define STB0899_OFFST_FEC_CORE_ID 0
1307#define STB0899_WIDTH_FEC_CORE_ID 32
1308
1309#define STB0899_OFF0_FEC_VER_ID_REG 0xfa34
1310#define STB0899_BASE_FEC_VER_ID_REG 0x00000800
1311#define STB0899_FEC_VER_ID (0xff << 0)
1312#define STB0899_OFFST_FEC_VER_ID 0
1313#define STB0899_WIDTH_FEC_VER_ID 8
1314
1315#define STB0899_OFF0_FEC_TP_SEL 0xfa38
1316#define STB0899_BASE_FEC_TP_SEL 0x00000800
1317
1318#define STB0899_OFF0_CSM_CNTRL1 0xf310
1319#define STB0899_BASE_CSM_CNTRL1 0x00000400
1320#define STB0899_CSM_FORCE_FREQLOCK (0x01 << 19)
1321#define STB0899_OFFST_CSM_FORCE_FREQLOCK 19
1322#define STB0899_WIDTH_CSM_FORCE_FREQLOCK 1
1323#define STB0899_CSM_FREQ_LOCKSTATE (0x01 << 18)
1324#define STB0899_OFFST_CSM_FREQ_LOCKSTATE 18
1325#define STB0899_WIDTH_CSM_FREQ_LOCKSTATE 1
1326#define STB0899_CSM_AUTO_PARAM (0x01 << 17)
1327#define STB0899_OFFST_CSM_AUTO_PARAM 17
1328#define STB0899_WIDTH_CSM_AUTO_PARAM 1
1329#define STB0899_FE_LOOP_SHIFT (0x07 << 14)
1330#define STB0899_OFFST_FE_LOOP_SHIFT 14
1331#define STB0899_WIDTH_FE_LOOP_SHIFT 3
1332#define STB0899_CSM_AGC_SHIFT (0x07 << 11)
1333#define STB0899_OFFST_CSM_AGC_SHIFT 11
1334#define STB0899_WIDTH_CSM_AGC_SHIFT 3
1335#define STB0899_CSM_AGC_GAIN (0x1ff << 2)
1336#define STB0899_OFFST_CSM_AGC_GAIN 2
1337#define STB0899_WIDTH_CSM_AGC_GAIN 9
1338#define STB0899_CSM_TWO_PASS (0x01 << 1)
1339#define STB0899_OFFST_CSM_TWO_PASS 1
1340#define STB0899_WIDTH_CSM_TWO_PASS 1
1341#define STB0899_CSM_DVT_TABLE (0x01 << 0)
1342#define STB0899_OFFST_CSM_DVT_TABLE 0
1343#define STB0899_WIDTH_CSM_DVT_TABLE 1
1344
1345#define STB0899_OFF0_CSM_CNTRL2 0xf314
1346#define STB0899_BASE_CSM_CNTRL2 0x00000400
1347#define STB0899_CSM_GAMMA_RHO_ACQ (0x1ff << 9)
1348#define STB0899_OFFST_CSM_GAMMA_RHOACQ 9
1349#define STB0899_WIDTH_CSM_GAMMA_RHOACQ 9
1350#define STB0899_CSM_GAMMA_ACQ (0x1ff << 0)
1351#define STB0899_OFFST_CSM_GAMMA_ACQ 0
1352#define STB0899_WIDTH_CSM_GAMMA_ACQ 9
1353
1354#define STB0899_OFF0_CSM_CNTRL3 0xf318
1355#define STB0899_BASE_CSM_CNTRL3 0x00000400
1356#define STB0899_CSM_GAMMA_RHO_TRACK (0x1ff << 9)
1357#define STB0899_OFFST_CSM_GAMMA_RHOTRACK 9
1358#define STB0899_WIDTH_CSM_GAMMA_RHOTRACK 9
1359#define STB0899_CSM_GAMMA_TRACK (0x1ff << 0)
1360#define STB0899_OFFST_CSM_GAMMA_TRACK 0
1361#define STB0899_WIDTH_CSM_GAMMA_TRACK 9
1362
1363#define STB0899_OFF0_CSM_CNTRL4 0xf31c
1364#define STB0899_BASE_CSM_CNTRL4 0x00000400
1365#define STB0899_CSM_PHASEDIFF_THRESH (0x0f << 8)
1366#define STB0899_OFFST_CSM_PHASEDIFF_THRESH 8
1367#define STB0899_WIDTH_CSM_PHASEDIFF_THRESH 4
1368#define STB0899_CSM_LOCKCOUNT_THRESH (0xff << 0)
1369#define STB0899_OFFST_CSM_LOCKCOUNT_THRESH 0
1370#define STB0899_WIDTH_CSM_LOCKCOUNT_THRESH 8
1371
1372/* Check on chapter 8 page 42 */
1373#define STB0899_ERRCTRL1 0xf574
1374#define STB0899_ERRCTRL2 0xf575
1375#define STB0899_ERRCTRL3 0xf576
1376#define STB0899_ERR_SRC_S1 (0x1f << 3)
1377#define STB0899_OFFST_ERR_SRC_S1 3
1378#define STB0899_WIDTH_ERR_SRC_S1 5
1379#define STB0899_ERR_SRC_S2 (0x0f << 0)
1380#define STB0899_OFFST_ERR_SRC_S2 0
1381#define STB0899_WIDTH_ERR_SRC_S2 4
1382#define STB0899_NOE (0x07 << 0)
1383#define STB0899_OFFST_NOE 0
1384#define STB0899_WIDTH_NOE 3
1385
1386#define STB0899_ECNT1M 0xf524
1387#define STB0899_ECNT1L 0xf525
1388#define STB0899_ECNT2M 0xf526
1389#define STB0899_ECNT2L 0xf527
1390#define STB0899_ECNT3M 0xf528
1391#define STB0899_ECNT3L 0xf529
1392
1393#define STB0899_DMONMSK1 0xf57b
1394#define STB0899_DMONMSK1_WAIT_1STEP (1 << 7)
1395#define STB0899_DMONMSK1_FREE_14 (1 << 6)
1396#define STB0899_DMONMSK1_AVRGVIT_CALC (1 << 5)
1397#define STB0899_DMONMSK1_FREE_12 (1 << 4)
1398#define STB0899_DMONMSK1_FREE_11 (1 << 3)
1399#define STB0899_DMONMSK1_B0DIV_CALC (1 << 2)
1400#define STB0899_DMONMSK1_KDIVB1_CALC (1 << 1)
1401#define STB0899_DMONMSK1_KDIVB2_CALC (1 << 0)
1402
1403#define STB0899_DMONMSK0 0xf57c
1404#define STB0899_DMONMSK0_SMOTTH_CALC (1 << 7)
1405#define STB0899_DMONMSK0_FREE_6 (1 << 6)
1406#define STB0899_DMONMSK0_SIGPOWER_CALC (1 << 5)
1407#define STB0899_DMONMSK0_QSEUIL_CALC (1 << 4)
1408#define STB0899_DMONMSK0_FREE_3 (1 << 3)
1409#define STB0899_DMONMSK0_FREE_2 (1 << 2)
1410#define STB0899_DMONMSK0_KVDIVB1_CALC (1 << 1)
1411#define STB0899_DMONMSK0_KVDIVB2_CALC (1 << 0)
1412
1413#define STB0899_TSULC 0xf549
1414#define STB0899_ULNOSYNCBYTES (0x01 << 7)
1415#define STB0899_OFFST_ULNOSYNCBYTES 7
1416#define STB0899_WIDTH_ULNOSYNCBYTES 1
1417#define STB0899_ULPARITY_ON (0x01 << 6)
1418#define STB0899_OFFST_ULPARITY_ON 6
1419#define STB0899_WIDTH_ULPARITY_ON 1
1420#define STB0899_ULSYNCOUTRS (0x01 << 5)
1421#define STB0899_OFFST_ULSYNCOUTRS 5
1422#define STB0899_WIDTH_ULSYNCOUTRS 1
1423#define STB0899_ULDSS_PACKETS (0x01 << 0)
1424#define STB0899_OFFST_ULDSS_PACKETS 0
1425#define STB0899_WIDTH_ULDSS_PACKETS 1
1426
1427#define STB0899_TSLPL 0xf54b
1428#define STB0899_LLDVBS2_MODE (0x01 << 4)
1429#define STB0899_OFFST_LLDVBS2_MODE 4
1430#define STB0899_WIDTH_LLDVBS2_MODE 1
1431#define STB0899_LLISSYI_ON (0x01 << 3)
1432#define STB0899_OFFST_LLISSYI_ON 3
1433#define STB0899_WIDTH_LLISSYI_ON 1
1434#define STB0899_LLNPD_ON (0x01 << 2)
1435#define STB0899_OFFST_LLNPD_ON 2
1436#define STB0899_WIDTH_LLNPD_ON 1
1437#define STB0899_LLCRC8_ON (0x01 << 1)
1438#define STB0899_OFFST_LLCRC8_ON 1
1439#define STB0899_WIDTH_LLCRC8_ON 1
1440
1441#define STB0899_TSCFGH 0xf54c
1442#define STB0899_OUTRS_PS (0x01 << 6)
1443#define STB0899_OFFST_OUTRS_PS 6
1444#define STB0899_WIDTH_OUTRS_PS 1
1445#define STB0899_SYNCBYTE (0x01 << 5)
1446#define STB0899_OFFST_SYNCBYTE 5
1447#define STB0899_WIDTH_SYNCBYTE 1
1448#define STB0899_PFBIT (0x01 << 4)
1449#define STB0899_OFFST_PFBIT 4
1450#define STB0899_WIDTH_PFBIT 1
1451#define STB0899_ERR_BIT (0x01 << 3)
1452#define STB0899_OFFST_ERR_BIT 3
1453#define STB0899_WIDTH_ERR_BIT 1
1454#define STB0899_MPEG (0x01 << 2)
1455#define STB0899_OFFST_MPEG 2
1456#define STB0899_WIDTH_MPEG 1
1457#define STB0899_CLK_POL (0x01 << 1)
1458#define STB0899_OFFST_CLK_POL 1
1459#define STB0899_WIDTH_CLK_POL 1
1460#define STB0899_FORCE0 (0x01 << 0)
1461#define STB0899_OFFST_FORCE0 0
1462#define STB0899_WIDTH_FORCE0 1
1463
1464#define STB0899_TSCFGM 0xf54d
1465#define STB0899_LLPRIORITY (0x01 << 3)
1466#define STB0899_OFFST_LLPRIORIY 3
1467#define STB0899_WIDTH_LLPRIORITY 1
1468#define STB0899_EN188 (0x01 << 2)
1469#define STB0899_OFFST_EN188 2
1470#define STB0899_WIDTH_EN188 1
1471
1472#define STB0899_TSCFGL 0xf54e
1473#define STB0899_DEL_ERRPCK (0x01 << 7)
1474#define STB0899_OFFST_DEL_ERRPCK 7
1475#define STB0899_WIDTH_DEL_ERRPCK 1
1476#define STB0899_ERRFLAGSTD (0x01 << 5)
1477#define STB0899_OFFST_ERRFLAGSTD 5
1478#define STB0899_WIDTH_ERRFLAGSTD 1
1479#define STB0899_MPEGERR (0x01 << 4)
1480#define STB0899_OFFST_MPEGERR 4
1481#define STB0899_WIDTH_MPEGERR 1
1482#define STB0899_BCH_CHK (0x01 << 3)
1483#define STB0899_OFFST_BCH_CHK 5
1484#define STB0899_WIDTH_BCH_CHK 1
1485#define STB0899_CRC8CHK (0x01 << 2)
1486#define STB0899_OFFST_CRC8CHK 2
1487#define STB0899_WIDTH_CRC8CHK 1
1488#define STB0899_SPEC_INFO (0x01 << 1)
1489#define STB0899_OFFST_SPEC_INFO 1
1490#define STB0899_WIDTH_SPEC_INFO 1
1491#define STB0899_LOW_PRIO_CLK (0x01 << 0)
1492#define STB0899_OFFST_LOW_PRIO_CLK 0
1493#define STB0899_WIDTH_LOW_PRIO_CLK 1
1494#define STB0899_ERROR_NORM (0x00 << 0)
1495#define STB0899_OFFST_ERROR_NORM 0
1496#define STB0899_WIDTH_ERROR_NORM 0
1497
1498#define STB0899_TSOUT 0xf54f
1499#define STB0899_RSSYNCDEL 0xf550
1500#define STB0899_TSINHDELH 0xf551
1501#define STB0899_TSINHDELM 0xf552
1502#define STB0899_TSINHDELL 0xf553
1503#define STB0899_TSLLSTKM 0xf55a
1504#define STB0899_TSLLSTKL 0xf55b
1505#define STB0899_TSULSTKM 0xf55c
1506#define STB0899_TSULSTKL 0xf55d
1507#define STB0899_TSSTATUS 0xf561
1508
1509#define STB0899_PDELCTRL 0xf600
1510#define STB0899_INVERT_RES (0x01 << 7)
1511#define STB0899_OFFST_INVERT_RES 7
1512#define STB0899_WIDTH_INVERT_RES 1
1513#define STB0899_FORCE_ACCEPTED (0x01 << 6)
1514#define STB0899_OFFST_FORCE_ACCEPTED 6
1515#define STB0899_WIDTH_FORCE_ACCEPTED 1
1516#define STB0899_FILTER_EN (0x01 << 5)
1517#define STB0899_OFFST_FILTER_EN 5
1518#define STB0899_WIDTH_FILTER_EN 1
1519#define STB0899_LOCKFALL_THRESH (0x01 << 4)
1520#define STB0899_OFFST_LOCKFALL_THRESH 4
1521#define STB0899_WIDTH_LOCKFALL_THRESH 1
1522#define STB0899_HYST_EN (0x01 << 3)
1523#define STB0899_OFFST_HYST_EN 3
1524#define STB0899_WIDTH_HYST_EN 1
1525#define STB0899_HYST_SWRST (0x01 << 2)
1526#define STB0899_OFFST_HYST_SWRST 2
1527#define STB0899_WIDTH_HYST_SWRST 1
1528#define STB0899_ALGO_EN (0x01 << 1)
1529#define STB0899_OFFST_ALGO_EN 1
1530#define STB0899_WIDTH_ALGO_EN 1
1531#define STB0899_ALGO_SWRST (0x01 << 0)
1532#define STB0899_OFFST_ALGO_SWRST 0
1533#define STB0899_WIDTH_ALGO_SWRST 1
1534
1535#define STB0899_PDELCTRL2 0xf601
1536#define STB0899_BBHCTRL1 0xf602
1537#define STB0899_BBHCTRL2 0xf603
1538#define STB0899_HYSTTHRESH 0xf604
1539
1540#define STB0899_MATCSTM 0xf605
1541#define STB0899_MATCSTL 0xf606
1542#define STB0899_UPLCSTM 0xf607
1543#define STB0899_UPLCSTL 0xf608
1544#define STB0899_DFLCSTM 0xf609
1545#define STB0899_DFLCSTL 0xf60a
1546#define STB0899_SYNCCST 0xf60b
1547#define STB0899_SYNCDCSTM 0xf60c
1548#define STB0899_SYNCDCSTL 0xf60d
1549#define STB0899_ISI_ENTRY 0xf60e
1550#define STB0899_ISI_BIT_EN 0xf60f
1551#define STB0899_MATSTRM 0xf610
1552#define STB0899_MATSTRL 0xf611
1553#define STB0899_UPLSTRM 0xf612
1554#define STB0899_UPLSTRL 0xf613
1555#define STB0899_DFLSTRM 0xf614
1556#define STB0899_DFLSTRL 0xf615
1557#define STB0899_SYNCSTR 0xf616
1558#define STB0899_SYNCDSTRM 0xf617
1559#define STB0899_SYNCDSTRL 0xf618
1560
1561#define STB0899_CFGPDELSTATUS1 0xf619
1562#define STB0899_BADDFL (0x01 << 6)
1563#define STB0899_OFFST_BADDFL 6
1564#define STB0899_WIDTH_BADDFL 1
1565#define STB0899_CONTINUOUS_STREAM (0x01 << 5)
1566#define STB0899_OFFST_CONTINUOUS_STREAM 5
1567#define STB0899_WIDTH_CONTINUOUS_STREAM 1
1568#define STB0899_ACCEPTED_STREAM (0x01 << 4)
1569#define STB0899_OFFST_ACCEPTED_STREAM 4
1570#define STB0899_WIDTH_ACCEPTED_STREAM 1
1571#define STB0899_BCH_ERRFLAG (0x01 << 3)
1572#define STB0899_OFFST_BCH_ERRFLAG 3
1573#define STB0899_WIDTH_BCH_ERRFLAG 1
1574#define STB0899_CRCRES (0x01 << 2)
1575#define STB0899_OFFST_CRCRES 2
1576#define STB0899_WIDTH_CRCRES 1
1577#define STB0899_CFGPDELSTATUS_LOCK (0x01 << 1)
1578#define STB0899_OFFST_CFGPDELSTATUS_LOCK 1
1579#define STB0899_WIDTH_CFGPDELSTATUS_LOCK 1
1580#define STB0899_1STLOCK (0x01 << 0)
1581#define STB0899_OFFST_1STLOCK 0
1582#define STB0899_WIDTH_1STLOCK 1
1583
1584#define STB0899_CFGPDELSTATUS2 0xf61a
1585#define STB0899_BBFERRORM 0xf61b
1586#define STB0899_BBFERRORL 0xf61c
1587#define STB0899_UPKTERRORM 0xf61d
1588#define STB0899_UPKTERRORL 0xf61e
1589
1590#define STB0899_TSTCK 0xff10
1591
1592#define STB0899_TSTRES 0xff11
1593#define STB0899_FRESLDPC (0x01 << 7)
1594#define STB0899_OFFST_FRESLDPC 7
1595#define STB0899_WIDTH_FRESLDPC 1
1596#define STB0899_FRESRS (0x01 << 6)
1597#define STB0899_OFFST_FRESRS 6
1598#define STB0899_WIDTH_FRESRS 1
1599#define STB0899_FRESVIT (0x01 << 5)
1600#define STB0899_OFFST_FRESVIT 5
1601#define STB0899_WIDTH_FRESVIT 1
1602#define STB0899_FRESMAS1_2 (0x01 << 4)
1603#define STB0899_OFFST_FRESMAS1_2 4
1604#define STB0899_WIDTH_FRESMAS1_2 1
1605#define STB0899_FRESACS (0x01 << 3)
1606#define STB0899_OFFST_FRESACS 3
1607#define STB0899_WIDTH_FRESACS 1
1608#define STB0899_FRESSYM (0x01 << 2)
1609#define STB0899_OFFST_FRESSYM 2
1610#define STB0899_WIDTH_FRESSYM 1
1611#define STB0899_FRESMAS (0x01 << 1)
1612#define STB0899_OFFST_FRESMAS 1
1613#define STB0899_WIDTH_FRESMAS 1
1614#define STB0899_FRESINT (0x01 << 0)
1615#define STB0899_OFFST_FRESINIT 0
1616#define STB0899_WIDTH_FRESINIT 1
1617
1618#define STB0899_TSTOUT 0xff12
1619#define STB0899_EN_SIGNATURE (0x01 << 7)
1620#define STB0899_OFFST_EN_SIGNATURE 7
1621#define STB0899_WIDTH_EN_SIGNATURE 1
1622#define STB0899_BCLK_CLK (0x01 << 6)
1623#define STB0899_OFFST_BCLK_CLK 6
1624#define STB0899_WIDTH_BCLK_CLK 1
1625#define STB0899_SGNL_OUT (0x01 << 5)
1626#define STB0899_OFFST_SGNL_OUT 5
1627#define STB0899_WIDTH_SGNL_OUT 1
1628#define STB0899_TS (0x01 << 4)
1629#define STB0899_OFFST_TS 4
1630#define STB0899_WIDTH_TS 1
1631#define STB0899_CTEST (0x01 << 0)
1632#define STB0899_OFFST_CTEST 0
1633#define STB0899_WIDTH_CTEST 1
1634
1635#define STB0899_TSTIN 0xff13
1636#define STB0899_TEST_IN (0x01 << 7)
1637#define STB0899_OFFST_TEST_IN 7
1638#define STB0899_WIDTH_TEST_IN 1
1639#define STB0899_EN_ADC (0x01 << 6)
1640#define STB0899_OFFST_EN_ADC 6
1641#define STB0899_WIDTH_ENADC 1
1642#define STB0899_SGN_ADC (0x01 << 5)
1643#define STB0899_OFFST_SGN_ADC 5
1644#define STB0899_WIDTH_SGN_ADC 1
1645#define STB0899_BCLK_IN (0x01 << 4)
1646#define STB0899_OFFST_BCLK_IN 4
1647#define STB0899_WIDTH_BCLK_IN 1
1648#define STB0899_JETONIN_MODE (0x01 << 3)
1649#define STB0899_OFFST_JETONIN_MODE 3
1650#define STB0899_WIDTH_JETONIN_MODE 1
1651#define STB0899_BCLK_VALUE (0x01 << 2)
1652#define STB0899_OFFST_BCLK_VALUE 2
1653#define STB0899_WIDTH_BCLK_VALUE 1
1654#define STB0899_SGNRST_T12 (0x01 << 1)
1655#define STB0899_OFFST_SGNRST_T12 1
1656#define STB0899_WIDTH_SGNRST_T12 1
1657#define STB0899_LOWSP_ENAX (0x01 << 0)
1658#define STB0899_OFFST_LOWSP_ENAX 0
1659#define STB0899_WIDTH_LOWSP_ENAX 1
1660
1661#define STB0899_TSTSYS 0xff14
1662#define STB0899_TSTCHIP 0xff15
1663#define STB0899_TSTFREE 0xff16
1664#define STB0899_TSTI2C 0xff17
1665#define STB0899_BITSPEEDM 0xff1c
1666#define STB0899_BITSPEEDL 0xff1d
1667#define STB0899_TBUSBIT 0xff1e
1668#define STB0899_TSTDIS 0xff24
1669#define STB0899_TSTDISRX 0xff25
1670#define STB0899_TSTJETON 0xff28
1671#define STB0899_TSTDCADJ 0xff40
1672#define STB0899_TSTAGC1 0xff41
1673#define STB0899_TSTAGC1N 0xff42
1674#define STB0899_TSTPOLYPH 0xff48
1675#define STB0899_TSTR 0xff49
1676#define STB0899_TSTAGC2 0xff4a
1677#define STB0899_TSTCTL1 0xff4b
1678#define STB0899_TSTCTL2 0xff4c
1679#define STB0899_TSTCTL3 0xff4d
1680#define STB0899_TSTDEMAP 0xff50
1681#define STB0899_TSTDEMAP2 0xff51
1682#define STB0899_TSTDEMMON 0xff52
1683#define STB0899_TSTRATE 0xff53
1684#define STB0899_TSTSELOUT 0xff54
1685#define STB0899_TSYNC 0xff55
1686#define STB0899_TSTERR 0xff56
1687#define STB0899_TSTRAM1 0xff58
1688#define STB0899_TSTVSELOUT 0xff59
1689#define STB0899_TSTFORCEIN 0xff5a
1690#define STB0899_TSTRS1 0xff5c
1691#define STB0899_TSTRS2 0xff5d
1692#define STB0899_TSTRS3 0xff53
1693
1694#define STB0899_INTBUFSTATUS 0xf200
1695#define STB0899_INTBUFCTRL 0xf201
1696#define STB0899_PCKLENUL 0xf55e
1697#define STB0899_PCKLENLL 0xf55f
1698#define STB0899_RSPCKLEN 0xf560
1699
1700/* 2 registers */
1701#define STB0899_SYNCDCST 0xf60c
1702
1703/* DiSEqC */
1704#define STB0899_DISCNTRL1 0xf0a0
1705#define STB0899_TIMOFF (0x01 << 7)
1706#define STB0899_OFFST_TIMOFF 7
1707#define STB0899_WIDTH_TIMOFF 1
1708#define STB0899_DISEQCRESET (0x01 << 6)
1709#define STB0899_OFFST_DISEQCRESET 6
1710#define STB0899_WIDTH_DISEQCRESET 1
1711#define STB0899_TIMCMD (0x03 << 4)
1712#define STB0899_OFFST_TIMCMD 4
1713#define STB0899_WIDTH_TIMCMD 2
1714#define STB0899_DISPRECHARGE (0x01 << 2)
1715#define STB0899_OFFST_DISPRECHARGE 2
1716#define STB0899_WIDTH_DISPRECHARGE 1
1717#define STB0899_DISEQCMODE (0x03 << 0)
1718#define STB0899_OFFST_DISEQCMODE 0
1719#define STB0899_WIDTH_DISEQCMODE 2
1720
1721#define STB0899_DISCNTRL2 0xf0a1
1722#define STB0899_RECEIVER_ON (0x01 << 7)
1723#define STB0899_OFFST_RECEIVER_ON 7
1724#define STB0899_WIDTH_RECEIVER_ON 1
1725#define STB0899_IGNO_SHORT_22K (0x01 << 6)
1726#define STB0899_OFFST_IGNO_SHORT_22K 6
1727#define STB0899_WIDTH_IGNO_SHORT_22K 1
1728#define STB0899_ONECHIP_TRX (0x01 << 5)
1729#define STB0899_OFFST_ONECHIP_TRX 5
1730#define STB0899_WIDTH_ONECHIP_TRX 1
1731#define STB0899_EXT_ENVELOP (0x01 << 4)
1732#define STB0899_OFFST_EXT_ENVELOP 4
1733#define STB0899_WIDTH_EXT_ENVELOP 1
1734#define STB0899_PIN_SELECT (0x03 << 2)
1735#define STB0899_OFFST_PIN_SELCT 2
1736#define STB0899_WIDTH_PIN_SELCT 2
1737#define STB0899_IRQ_RXEND (0x01 << 1)
1738#define STB0899_OFFST_IRQ_RXEND 1
1739#define STB0899_WIDTH_IRQ_RXEND 1
1740#define STB0899_IRQ_4NBYTES (0x01 << 0)
1741#define STB0899_OFFST_IRQ_4NBYTES 0
1742#define STB0899_WIDTH_IRQ_4NBYTES 1
1743
1744#define STB0899_DISRX_ST0 0xf0a4
1745#define STB0899_RXEND (0x01 << 7)
1746#define STB0899_OFFST_RXEND 7
1747#define STB0899_WIDTH_RXEND 1
1748#define STB0899_RXACTIVE (0x01 << 6)
1749#define STB0899_OFFST_RXACTIVE 6
1750#define STB0899_WIDTH_RXACTIVE 1
1751#define STB0899_SHORT22K (0x01 << 5)
1752#define STB0899_OFFST_SHORT22K 5
1753#define STB0899_WIDTH_SHORT22K 1
1754#define STB0899_CONTTONE (0x01 << 4)
1755#define STB0899_OFFST_CONTTONE 4
1756#define STB0899_WIDTH_CONTONE 1
1757#define STB0899_4BFIFOREDY (0x01 << 3)
1758#define STB0899_OFFST_4BFIFOREDY 3
1759#define STB0899_WIDTH_4BFIFOREDY 1
1760#define STB0899_FIFOEMPTY (0x01 << 2)
1761#define STB0899_OFFST_FIFOEMPTY 2
1762#define STB0899_WIDTH_FIFOEMPTY 1
1763#define STB0899_ABORTTRX (0x01 << 0)
1764#define STB0899_OFFST_ABORTTRX 0
1765#define STB0899_WIDTH_ABORTTRX 1
1766
1767#define STB0899_DISRX_ST1 0xf0a5
1768#define STB0899_RXFAIL (0x01 << 7)
1769#define STB0899_OFFST_RXFAIL 7
1770#define STB0899_WIDTH_RXFAIL 1
1771#define STB0899_FIFOPFAIL (0x01 << 6)
1772#define STB0899_OFFST_FIFOPFAIL 6
1773#define STB0899_WIDTH_FIFOPFAIL 1
1774#define STB0899_RXNONBYTES (0x01 << 5)
1775#define STB0899_OFFST_RXNONBYTES 5
1776#define STB0899_WIDTH_RXNONBYTES 1
1777#define STB0899_FIFOOVF (0x01 << 4)
1778#define STB0899_OFFST_FIFOOVF 4
1779#define STB0899_WIDTH_FIFOOVF 1
1780#define STB0899_FIFOBYTENBR (0x0f << 0)
1781#define STB0899_OFFST_FIFOBYTENBR 0
1782#define STB0899_WIDTH_FIFOBYTENBR 4
1783
1784#define STB0899_DISPARITY 0xf0a6
1785
1786#define STB0899_DISFIFO 0xf0a7
1787
1788#define STB0899_DISSTATUS 0xf0a8
1789#define STB0899_FIFOFULL (0x01 << 6)
1790#define STB0899_OFFST_FIFOFULL 6
1791#define STB0899_WIDTH_FIFOFULL 1
1792#define STB0899_TXIDLE (0x01 << 5)
1793#define STB0899_OFFST_TXIDLE 5
1794#define STB0899_WIDTH_TXIDLE 1
1795#define STB0899_GAPBURST (0x01 << 4)
1796#define STB0899_OFFST_GAPBURST 4
1797#define STB0899_WIDTH_GAPBURST 1
1798#define STB0899_TXFIFOBYTES (0x0f << 0)
1799#define STB0899_OFFST_TXFIFOBYTES 0
1800#define STB0899_WIDTH_TXFIFOBYTES 4
1801#define STB0899_DISF22 0xf0a9
1802
1803#define STB0899_DISF22RX 0xf0aa
1804
1805/* General Purpose */
1806#define STB0899_SYSREG 0xf101
1807#define STB0899_ACRPRESC 0xf110
1808#define STB0899_OFFST_RSVD2 7
1809#define STB0899_WIDTH_RSVD2 1
1810#define STB0899_OFFST_ACRPRESC 4
1811#define STB0899_WIDTH_ACRPRESC 3
1812#define STB0899_OFFST_RSVD1 3
1813#define STB0899_WIDTH_RSVD1 1
1814#define STB0899_OFFST_ACRPRESC2 0
1815#define STB0899_WIDTH_ACRPRESC2 3
1816
1817#define STB0899_ACRDIV1 0xf111
1818#define STB0899_ACRDIV2 0xf112
1819#define STB0899_DACR1 0xf113
1820#define STB0899_DACR2 0xf114
1821#define STB0899_OUTCFG 0xf11c
1822#define STB0899_MODECFG 0xf11d
1823#define STB0899_NCOARSE 0xf1b3
1824
1825#define STB0899_SYNTCTRL 0xf1b6
1826#define STB0899_STANDBY (0x01 << 7)
1827#define STB0899_OFFST_STANDBY 7
1828#define STB0899_WIDTH_STANDBY 1
1829#define STB0899_BYPASSPLL (0x01 << 6)
1830#define STB0899_OFFST_BYPASSPLL 6
1831#define STB0899_WIDTH_BYPASSPLL 1
1832#define STB0899_SEL1XRATIO (0x01 << 5)
1833#define STB0899_OFFST_SEL1XRATIO 5
1834#define STB0899_WIDTH_SEL1XRATIO 1
1835#define STB0899_SELOSCI (0x01 << 1)
1836#define STB0899_OFFST_SELOSCI 1
1837#define STB0899_WIDTH_SELOSCI 1
1838
1839#define STB0899_FILTCTRL 0xf1b7
1840#define STB0899_SYSCTRL 0xf1b8
1841
1842#define STB0899_STOPCLK1 0xf1c2
1843#define STB0899_STOP_CKINTBUF108 (0x01 << 7)
1844#define STB0899_OFFST_STOP_CKINTBUF108 7
1845#define STB0899_WIDTH_STOP_CKINTBUF108 1
1846#define STB0899_STOP_CKINTBUF216 (0x01 << 6)
1847#define STB0899_OFFST_STOP_CKINTBUF216 6
1848#define STB0899_WIDTH_STOP_CKINTBUF216 1
1849#define STB0899_STOP_CHK8PSK (0x01 << 5)
1850#define STB0899_OFFST_STOP_CHK8PSK 5
1851#define STB0899_WIDTH_STOP_CHK8PSK 1
1852#define STB0899_STOP_CKFEC108 (0x01 << 4)
1853#define STB0899_OFFST_STOP_CKFEC108 4
1854#define STB0899_WIDTH_STOP_CKFEC108 1
1855#define STB0899_STOP_CKFEC216 (0x01 << 3)
1856#define STB0899_OFFST_STOP_CKFEC216 3
1857#define STB0899_WIDTH_STOP_CKFEC216 1
1858#define STB0899_STOP_CKCORE216 (0x01 << 2)
1859#define STB0899_OFFST_STOP_CKCORE216 2
1860#define STB0899_WIDTH_STOP_CKCORE216 1
1861#define STB0899_STOP_CKADCI108 (0x01 << 1)
1862#define STB0899_OFFST_STOP_CKADCI108 1
1863#define STB0899_WIDTH_STOP_CKADCI108 1
1864#define STB0899_STOP_INVCKADCI108 (0x01 << 0)
1865#define STB0899_OFFST_STOP_INVCKADCI108 0
1866#define STB0899_WIDTH_STOP_INVCKADCI108 1
1867
1868#define STB0899_STOPCLK2 0xf1c3
1869#define STB0899_STOP_CKS2DMD108 (0x01 << 2)
1870#define STB0899_OFFST_STOP_CKS2DMD108 2
1871#define STB0899_WIDTH_STOP_CKS2DMD108 1
1872#define STB0899_STOP_CKPKDLIN108 (0x01 << 1)
1873#define STB0899_OFFST_STOP_CKPKDLIN108 1
1874#define STB0899_WIDTH_STOP_CKPKDLIN108 1
1875#define STB0899_STOP_CKPKDLIN216 (0x01 << 0)
1876#define STB0899_OFFST_STOP_CKPKDLIN216 0
1877#define STB0899_WIDTH_STOP_CKPKDLIN216 1
1878
1879#define STB0899_TSTTNR1 0xf1e0
1880#define STB0899_BYPASS_ADC (0x01 << 7)
1881#define STB0899_OFFST_BYPASS_ADC 7
1882#define STB0899_WIDTH_BYPASS_ADC 1
1883#define STB0899_INVADCICKOUT (0x01 << 6)
1884#define STB0899_OFFST_INVADCICKOUT 6
1885#define STB0899_WIDTH_INVADCICKOUT 1
1886#define STB0899_ADCTEST_VOLTAGE (0x03 << 4)
1887#define STB0899_OFFST_ADCTEST_VOLTAGE 4
1888#define STB0899_WIDTH_ADCTEST_VOLTAGE 1
1889#define STB0899_ADC_RESET (0x01 << 3)
1890#define STB0899_OFFST_ADC_RESET 3
1891#define STB0899_WIDTH_ADC_RESET 1
1892#define STB0899_TSTTNR1_2 (0x01 << 2)
1893#define STB0899_OFFST_TSTTNR1_2 2
1894#define STB0899_WIDTH_TSTTNR1_2 1
1895#define STB0899_ADCPON (0x01 << 1)
1896#define STB0899_OFFST_ADCPON 1
1897#define STB0899_WIDTH_ADCPON 1
1898#define STB0899_ADCIN_MODE (0x01 << 0)
1899#define STB0899_OFFST_ADCIN_MODE 0
1900#define STB0899_WIDTH_ADCIN_MODE 1
1901
1902#define STB0899_TSTTNR2 0xf1e1
1903#define STB0899_TSTTNR2_7 (0x01 << 7)
1904#define STB0899_OFFST_TSTTNR2_7 7
1905#define STB0899_WIDTH_TSTTNR2_7 1
1906#define STB0899_NOT_DISRX_WIRED (0x01 << 6)
1907#define STB0899_OFFST_NOT_DISRX_WIRED 6
1908#define STB0899_WIDTH_NOT_DISRX_WIRED 1
1909#define STB0899_DISEQC_DCURRENT (0x01 << 5)
1910#define STB0899_OFFST_DISEQC_DCURRENT 5
1911#define STB0899_WIDTH_DISEQC_DCURRENT 1
1912#define STB0899_DISEQC_ZCURRENT (0x01 << 4)
1913#define STB0899_OFFST_DISEQC_ZCURRENT 4
1914#define STB0899_WIDTH_DISEQC_ZCURRENT 1
1915#define STB0899_DISEQC_SINC_SOURCE (0x03 << 2)
1916#define STB0899_OFFST_DISEQC_SINC_SOURCE 2
1917#define STB0899_WIDTH_DISEQC_SINC_SOURCE 2
1918#define STB0899_SELIQSRC (0x03 << 0)
1919#define STB0899_OFFST_SELIQSRC 0
1920#define STB0899_WIDTH_SELIQSRC 2
1921
1922#define STB0899_TSTTNR3 0xf1e2
1923
1924#define STB0899_I2CCFG 0xf129
1925#define STB0899_I2CCFGRSVD (0x0f << 4)
1926#define STB0899_OFFST_I2CCFGRSVD 4
1927#define STB0899_WIDTH_I2CCFGRSVD 4
1928#define STB0899_I2CFASTMODE (0x01 << 3)
1929#define STB0899_OFFST_I2CFASTMODE 3
1930#define STB0899_WIDTH_I2CFASTMODE 1
1931#define STB0899_STATUSWR (0x01 << 2)
1932#define STB0899_OFFST_STATUSWR 2
1933#define STB0899_WIDTH_STATUSWR 1
1934#define STB0899_I2CADDRINC (0x03 << 0)
1935#define STB0899_OFFST_I2CADDRINC 0
1936#define STB0899_WIDTH_I2CADDRINC 2
1937
1938#define STB0899_I2CRPT 0xf12a
1939#define STB0899_I2CTON (0x01 << 7)
1940#define STB0899_OFFST_I2CTON 7
1941#define STB0899_WIDTH_I2CTON 1
1942#define STB0899_ENARPTLEVEL (0x01 << 6)
1943#define STB0899_OFFST_ENARPTLEVEL 6
1944#define STB0899_WIDTH_ENARPTLEVEL 2
1945#define STB0899_SCLTDELAY (0x01 << 3)
1946#define STB0899_OFFST_SCLTDELAY 3
1947#define STB0899_WIDTH_SCLTDELAY 1
1948#define STB0899_STOPENA (0x01 << 2)
1949#define STB0899_OFFST_STOPENA 2
1950#define STB0899_WIDTH_STOPENA 1
1951#define STB0899_STOPSDAT2SDA (0x01 << 1)
1952#define STB0899_OFFST_STOPSDAT2SDA 1
1953#define STB0899_WIDTH_STOPSDAT2SDA 1
1954
1955#define STB0899_IOPVALUE8 0xf136
1956#define STB0899_IOPVALUE7 0xf137
1957#define STB0899_IOPVALUE6 0xf138
1958#define STB0899_IOPVALUE5 0xf139
1959#define STB0899_IOPVALUE4 0xf13a
1960#define STB0899_IOPVALUE3 0xf13b
1961#define STB0899_IOPVALUE2 0xf13c
1962#define STB0899_IOPVALUE1 0xf13d
1963#define STB0899_IOPVALUE0 0xf13e
1964
1965#define STB0899_GPIO00CFG 0xf140
1966
1967#define STB0899_GPIO01CFG 0xf141
1968#define STB0899_GPIO02CFG 0xf142
1969#define STB0899_GPIO03CFG 0xf143
1970#define STB0899_GPIO04CFG 0xf144
1971#define STB0899_GPIO05CFG 0xf145
1972#define STB0899_GPIO06CFG 0xf146
1973#define STB0899_GPIO07CFG 0xf147
1974#define STB0899_GPIO08CFG 0xf148
1975#define STB0899_GPIO09CFG 0xf149
1976#define STB0899_GPIO10CFG 0xf14a
1977#define STB0899_GPIO11CFG 0xf14b
1978#define STB0899_GPIO12CFG 0xf14c
1979#define STB0899_GPIO13CFG 0xf14d
1980#define STB0899_GPIO14CFG 0xf14e
1981#define STB0899_GPIO15CFG 0xf14f
1982#define STB0899_GPIO16CFG 0xf150
1983#define STB0899_GPIO17CFG 0xf151
1984#define STB0899_GPIO18CFG 0xf152
1985#define STB0899_GPIO19CFG 0xf153
1986#define STB0899_GPIO20CFG 0xf154
1987
1988#define STB0899_SDATCFG 0xf155
1989#define STB0899_SCLTCFG 0xf156
1990#define STB0899_AGCRFCFG 0xf157
1991#define STB0899_GPIO22 0xf158 /* AGCBB2CFG */
1992#define STB0899_GPIO21 0xf159 /* AGCBB1CFG */
1993#define STB0899_DIRCLKCFG 0xf15a
1994#define STB0899_CLKOUT27CFG 0xf15b
1995#define STB0899_STDBYCFG 0xf15c
1996#define STB0899_CS0CFG 0xf15d
1997#define STB0899_CS1CFG 0xf15e
1998#define STB0899_DISEQCOCFG 0xf15f
1999
2000#define STB0899_GPIO32CFG 0xf160
2001#define STB0899_GPIO33CFG 0xf161
2002#define STB0899_GPIO34CFG 0xf162
2003#define STB0899_GPIO35CFG 0xf163
2004#define STB0899_GPIO36CFG 0xf164
2005#define STB0899_GPIO37CFG 0xf165
2006#define STB0899_GPIO38CFG 0xf166
2007#define STB0899_GPIO39CFG 0xf167
2008
2009#define STB0899_IRQSTATUS_3 0xf120
2010#define STB0899_IRQSTATUS_2 0xf121
2011#define STB0899_IRQSTATUS_1 0xf122
2012#define STB0899_IRQSTATUS_0 0xf123
2013
2014#define STB0899_IRQMSK_3 0xf124
2015#define STB0899_IRQMSK_2 0xf125
2016#define STB0899_IRQMSK_1 0xf126
2017#define STB0899_IRQMSK_0 0xf127
2018
2019#define STB0899_IRQCFG 0xf128
2020
2021#define STB0899_GHOSTREG 0xf000
2022
2023#define STB0899_S2DEMOD 0xf3fc
2024#define STB0899_S2FEC 0xfafc
2025
2026
2027#endif
diff --git a/drivers/media/dvb/frontends/stb6100.c b/drivers/media/dvb/frontends/stb6100.c
new file mode 100644
index 000000000000..ff39275ab49c
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb6100.c
@@ -0,0 +1,545 @@
1/*
2 STB6100 Silicon Tuner
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26
27#include "dvb_frontend.h"
28#include "stb6100.h"
29
30static unsigned int verbose;
31module_param(verbose, int, 0644);
32
33
34#define FE_ERROR 0
35#define FE_NOTICE 1
36#define FE_INFO 2
37#define FE_DEBUG 3
38
39#define dprintk(x, y, z, format, arg...) do { \
40 if (z) { \
41 if ((x > FE_ERROR) && (x > y)) \
42 printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
43 else if ((x > FE_NOTICE) && (x > y)) \
44 printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
45 else if ((x > FE_INFO) && (x > y)) \
46 printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
47 else if ((x > FE_DEBUG) && (x > y)) \
48 printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
49 } else { \
50 if (x > y) \
51 printk(format, ##arg); \
52 } \
53} while(0)
54
55struct stb6100_lkup {
56 u32 val_low;
57 u32 val_high;
58 u8 reg;
59};
60
61static int stb6100_release(struct dvb_frontend *fe);
62
63static const struct stb6100_lkup lkup[] = {
64 { 0, 950000, 0x0a },
65 { 950000, 1000000, 0x0a },
66 { 1000000, 1075000, 0x0c },
67 { 1075000, 1200000, 0x00 },
68 { 1200000, 1300000, 0x01 },
69 { 1300000, 1370000, 0x02 },
70 { 1370000, 1470000, 0x04 },
71 { 1470000, 1530000, 0x05 },
72 { 1530000, 1650000, 0x06 },
73 { 1650000, 1800000, 0x08 },
74 { 1800000, 1950000, 0x0a },
75 { 1950000, 2150000, 0x0c },
76 { 2150000, 9999999, 0x0c },
77 { 0, 0, 0x00 }
78};
79
80/* Register names for easy debugging. */
81static const char *stb6100_regnames[] = {
82 [STB6100_LD] = "LD",
83 [STB6100_VCO] = "VCO",
84 [STB6100_NI] = "NI",
85 [STB6100_NF_LSB] = "NF",
86 [STB6100_K] = "K",
87 [STB6100_G] = "G",
88 [STB6100_F] = "F",
89 [STB6100_DLB] = "DLB",
90 [STB6100_TEST1] = "TEST1",
91 [STB6100_FCCK] = "FCCK",
92 [STB6100_LPEN] = "LPEN",
93 [STB6100_TEST3] = "TEST3",
94};
95
96/* Template for normalisation, i.e. setting unused or undocumented
97 * bits as required according to the documentation.
98 */
99struct stb6100_regmask {
100 u8 mask;
101 u8 set;
102};
103
104static const struct stb6100_regmask stb6100_template[] = {
105 [STB6100_LD] = { 0xff, 0x00 },
106 [STB6100_VCO] = { 0xff, 0x00 },
107 [STB6100_NI] = { 0xff, 0x00 },
108 [STB6100_NF_LSB] = { 0xff, 0x00 },
109 [STB6100_K] = { 0xc7, 0x38 },
110 [STB6100_G] = { 0xef, 0x10 },
111 [STB6100_F] = { 0x1f, 0xc0 },
112 [STB6100_DLB] = { 0x38, 0xc4 },
113 [STB6100_TEST1] = { 0x00, 0x8f },
114 [STB6100_FCCK] = { 0x40, 0x0d },
115 [STB6100_LPEN] = { 0xf0, 0x0b },
116 [STB6100_TEST3] = { 0x00, 0xde },
117};
118
119static void stb6100_normalise_regs(u8 regs[])
120{
121 int i;
122
123 for (i = 0; i < STB6100_NUMREGS; i++)
124 regs[i] = (regs[i] & stb6100_template[i].mask) | stb6100_template[i].set;
125}
126
127static int stb6100_read_regs(struct stb6100_state *state, u8 regs[])
128{
129 int rc;
130 struct i2c_msg msg = {
131 .addr = state->config->tuner_address,
132 .flags = I2C_M_RD,
133 .buf = regs,
134 .len = STB6100_NUMREGS
135 };
136
137 rc = i2c_transfer(state->i2c, &msg, 1);
138 if (unlikely(rc != 1)) {
139 dprintk(verbose, FE_ERROR, 1, "Read (0x%x) err, rc=[%d]",
140 state->config->tuner_address, rc);
141
142 return -EREMOTEIO;
143 }
144 if (unlikely(verbose > FE_DEBUG)) {
145 int i;
146
147 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address);
148 for (i = 0; i < STB6100_NUMREGS; i++)
149 dprintk(verbose, FE_DEBUG, 1, " %s: 0x%02x", stb6100_regnames[i], regs[i]);
150 }
151 return 0;
152}
153
154static int stb6100_read_reg(struct stb6100_state *state, u8 reg)
155{
156 u8 regs[STB6100_NUMREGS];
157 int rc;
158
159 if (unlikely(reg >= STB6100_NUMREGS)) {
160 dprintk(verbose, FE_ERROR, 1, "Invalid register offset 0x%x", reg);
161 return -EINVAL;
162 }
163 if ((rc = stb6100_read_regs(state, regs)) < 0)
164 return rc;
165 return (unsigned int)regs[reg];
166}
167
168static int stb6100_write_reg_range(struct stb6100_state *state, u8 buf[], int start, int len)
169{
170 int rc;
171 u8 cmdbuf[len + 1];
172 struct i2c_msg msg = {
173 .addr = state->config->tuner_address,
174 .flags = 0,
175 .buf = cmdbuf,
176 .len = len + 1
177 };
178
179 if (unlikely(start < 1 || start + len > STB6100_NUMREGS)) {
180 dprintk(verbose, FE_ERROR, 1, "Invalid register range %d:%d",
181 start, len);
182 return -EINVAL;
183 }
184 memcpy(&cmdbuf[1], buf, len);
185 cmdbuf[0] = start;
186
187 if (unlikely(verbose > FE_DEBUG)) {
188 int i;
189
190 dprintk(verbose, FE_DEBUG, 1, " Write @ 0x%02x: [%d:%d]", state->config->tuner_address, start, len);
191 for (i = 0; i < len; i++)
192 dprintk(verbose, FE_DEBUG, 1, " %s: 0x%02x", stb6100_regnames[start + i], buf[i]);
193 }
194 rc = i2c_transfer(state->i2c, &msg, 1);
195 if (unlikely(rc != 1)) {
196 dprintk(verbose, FE_ERROR, 1, "(0x%x) write err [%d:%d], rc=[%d]",
197 (unsigned int)state->config->tuner_address, start, len, rc);
198 return -EREMOTEIO;
199 }
200 return 0;
201}
202
203static int stb6100_write_reg(struct stb6100_state *state, u8 reg, u8 data)
204{
205 if (unlikely(reg >= STB6100_NUMREGS)) {
206 dprintk(verbose, FE_ERROR, 1, "Invalid register offset 0x%x", reg);
207 return -EREMOTEIO;
208 }
209 data = (data & stb6100_template[reg].mask) | stb6100_template[reg].set;
210 return stb6100_write_reg_range(state, &data, reg, 1);
211}
212
213static int stb6100_write_regs(struct stb6100_state *state, u8 regs[])
214{
215 stb6100_normalise_regs(regs);
216 return stb6100_write_reg_range(state, &regs[1], 1, STB6100_NUMREGS - 1);
217}
218
219static int stb6100_get_status(struct dvb_frontend *fe, u32 *status)
220{
221 int rc;
222 struct stb6100_state *state = fe->tuner_priv;
223
224 if ((rc = stb6100_read_reg(state, STB6100_LD)) < 0)
225 return rc;
226
227 return (rc & STB6100_LD_LOCK) ? TUNER_STATUS_LOCKED : 0;
228}
229
230static int stb6100_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
231{
232 int rc;
233 u8 f;
234 struct stb6100_state *state = fe->tuner_priv;
235
236 if ((rc = stb6100_read_reg(state, STB6100_F)) < 0)
237 return rc;
238 f = rc & STB6100_F_F;
239
240 state->status.bandwidth = (f + 5) * 2000; /* x2 for ZIF */
241
242 *bandwidth = state->bandwidth = state->status.bandwidth * 1000;
243 dprintk(verbose, FE_DEBUG, 1, "bandwidth = %u Hz", state->bandwidth);
244 return 0;
245}
246
247static int stb6100_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
248{
249 u32 tmp;
250 int rc;
251 struct stb6100_state *state = fe->tuner_priv;
252
253 dprintk(verbose, FE_DEBUG, 1, "set bandwidth to %u Hz", bandwidth);
254
255 bandwidth /= 2; /* ZIF */
256
257 if (bandwidth >= 36000000) /* F[4:0] BW/2 max =31+5=36 mhz for F=31 */
258 tmp = 31;
259 else if (bandwidth <= 5000000) /* bw/2 min = 5Mhz for F=0 */
260 tmp = 0;
261 else /* if 5 < bw/2 < 36 */
262 tmp = (bandwidth + 500000) / 1000000 - 5;
263
264 /* Turn on LPF bandwidth setting clock control,
265 * set bandwidth, wait 10ms, turn off.
266 */
267 if ((rc = stb6100_write_reg(state, STB6100_FCCK, 0x0d | STB6100_FCCK_FCCK)) < 0)
268 return rc;
269 if ((rc = stb6100_write_reg(state, STB6100_F, 0xc0 | tmp)) < 0)
270 return rc;
271 msleep(1);
272 if ((rc = stb6100_write_reg(state, STB6100_FCCK, 0x0d)) < 0)
273 return rc;
274
275 return 0;
276}
277
278static int stb6100_get_frequency(struct dvb_frontend *fe, u32 *frequency)
279{
280 int rc;
281 u32 nint, nfrac, fvco;
282 int psd2, odiv;
283 struct stb6100_state *state = fe->tuner_priv;
284 u8 regs[STB6100_NUMREGS];
285
286 if ((rc = stb6100_read_regs(state, regs)) < 0)
287 return rc;
288
289 odiv = (regs[STB6100_VCO] & STB6100_VCO_ODIV) >> STB6100_VCO_ODIV_SHIFT;
290 psd2 = (regs[STB6100_K] & STB6100_K_PSD2) >> STB6100_K_PSD2_SHIFT;
291 nint = regs[STB6100_NI];
292 nfrac = ((regs[STB6100_K] & STB6100_K_NF_MSB) << 8) | regs[STB6100_NF_LSB];
293 fvco = (nfrac * state->reference >> (9 - psd2)) + (nint * state->reference << psd2);
294 *frequency = state->frequency = fvco >> (odiv + 1);
295
296 dprintk(verbose, FE_DEBUG, 1,
297 "frequency = %u kHz, odiv = %u, psd2 = %u, fxtal = %u kHz, fvco = %u kHz, N(I) = %u, N(F) = %u",
298 state->frequency, odiv, psd2, state->reference, fvco, nint, nfrac);
299 return 0;
300}
301
302
303static int stb6100_set_frequency(struct dvb_frontend *fe, u32 frequency)
304{
305 int rc;
306 const struct stb6100_lkup *ptr;
307 struct stb6100_state *state = fe->tuner_priv;
308 struct dvb_frontend_parameters p;
309
310 u32 srate = 0, fvco, nint, nfrac;
311 u8 regs[STB6100_NUMREGS];
312 u8 g, psd2, odiv;
313
314 if ((rc = stb6100_read_regs(state, regs)) < 0)
315 return rc;
316
317 if (fe->ops.get_frontend) {
318 dprintk(verbose, FE_DEBUG, 1, "Get frontend parameters");
319 fe->ops.get_frontend(fe, &p);
320 }
321 srate = p.u.qpsk.symbol_rate;
322
323 regs[STB6100_DLB] = 0xdc;
324 /* Disable LPEN */
325 regs[STB6100_LPEN] &= ~STB6100_LPEN_LPEN; /* PLL Loop disabled */
326
327 if ((rc = stb6100_write_regs(state, regs)) < 0)
328 return rc;
329
330 /* Baseband gain. */
331 if (srate >= 15000000)
332 g = 9; // +4 dB
333 else if (srate >= 5000000)
334 g = 11; // +8 dB
335 else
336 g = 14; // +14 dB
337
338 regs[STB6100_G] = (regs[STB6100_G] & ~STB6100_G_G) | g;
339 regs[STB6100_G] &= ~STB6100_G_GCT; /* mask GCT */
340 regs[STB6100_G] |= (1 << 5); /* 2Vp-p Mode */
341
342 /* VCO divide ratio (LO divide ratio, VCO prescaler enable). */
343 if (frequency <= 1075000)
344 odiv = 1;
345 else
346 odiv = 0;
347 regs[STB6100_VCO] = (regs[STB6100_VCO] & ~STB6100_VCO_ODIV) | (odiv << STB6100_VCO_ODIV_SHIFT);
348
349 if ((frequency > 1075000) && (frequency <= 1325000))
350 psd2 = 0;
351 else
352 psd2 = 1;
353 regs[STB6100_K] = (regs[STB6100_K] & ~STB6100_K_PSD2) | (psd2 << STB6100_K_PSD2_SHIFT);
354
355 /* OSM */
356 for (ptr = lkup;
357 (ptr->val_high != 0) && !CHKRANGE(frequency, ptr->val_low, ptr->val_high);
358 ptr++);
359 if (ptr->val_high == 0) {
360 printk(KERN_ERR "%s: frequency out of range: %u kHz\n", __func__, frequency);
361 return -EINVAL;
362 }
363 regs[STB6100_VCO] = (regs[STB6100_VCO] & ~STB6100_VCO_OSM) | ptr->reg;
364
365 /* F(VCO) = F(LO) * (ODIV == 0 ? 2 : 4) */
366 fvco = frequency << (1 + odiv);
367 /* N(I) = floor(f(VCO) / (f(XTAL) * (PSD2 ? 2 : 1))) */
368 nint = fvco / (state->reference << psd2);
369 /* N(F) = round(f(VCO) / f(XTAL) * (PSD2 ? 2 : 1) - N(I)) * 2 ^ 9 */
370 nfrac = (((fvco - (nint * state->reference << psd2)) << (9 - psd2)) + state->reference / 2) / state->reference;
371 dprintk(verbose, FE_DEBUG, 1,
372 "frequency = %u, srate = %u, g = %u, odiv = %u, psd2 = %u, fxtal = %u, osm = %u, fvco = %u, N(I) = %u, N(F) = %u",
373 frequency, srate, (unsigned int)g, (unsigned int)odiv,
374 (unsigned int)psd2, state->reference,
375 ptr->reg, fvco, nint, nfrac);
376 regs[STB6100_NI] = nint;
377 regs[STB6100_NF_LSB] = nfrac;
378 regs[STB6100_K] = (regs[STB6100_K] & ~STB6100_K_NF_MSB) | ((nfrac >> 8) & STB6100_K_NF_MSB);
379 regs[STB6100_VCO] |= STB6100_VCO_OSCH; /* VCO search enabled */
380 regs[STB6100_VCO] |= STB6100_VCO_OCK; /* VCO search clock off */
381 regs[STB6100_FCCK] |= STB6100_FCCK_FCCK; /* LPF BW setting clock enabled */
382 regs[STB6100_LPEN] &= ~STB6100_LPEN_LPEN; /* PLL loop disabled */
383 /* Power up. */
384 regs[STB6100_LPEN] |= STB6100_LPEN_SYNP | STB6100_LPEN_OSCP | STB6100_LPEN_BEN;
385
386 msleep(2);
387 if ((rc = stb6100_write_regs(state, regs)) < 0)
388 return rc;
389
390 msleep(2);
391 regs[STB6100_LPEN] |= STB6100_LPEN_LPEN; /* PLL loop enabled */
392 if ((rc = stb6100_write_reg(state, STB6100_LPEN, regs[STB6100_LPEN])) < 0)
393 return rc;
394
395 regs[STB6100_VCO] &= ~STB6100_VCO_OCK; /* VCO fast search */
396 if ((rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO])) < 0)
397 return rc;
398
399 msleep(10); /* wait for LO to lock */
400 regs[STB6100_VCO] &= ~STB6100_VCO_OSCH; /* vco search disabled */
401 regs[STB6100_VCO] |= STB6100_VCO_OCK; /* search clock off */
402 if ((rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO])) < 0)
403 return rc;
404 regs[STB6100_FCCK] &= ~STB6100_FCCK_FCCK; /* LPF BW clock disabled */
405 stb6100_normalise_regs(regs);
406 if ((rc = stb6100_write_reg_range(state, &regs[1], 1, STB6100_NUMREGS - 3)) < 0)
407 return rc;
408
409 msleep(100);
410
411 return 0;
412}
413
414static int stb6100_sleep(struct dvb_frontend *fe)
415{
416 /* TODO: power down */
417 return 0;
418}
419
420static int stb6100_init(struct dvb_frontend *fe)
421{
422 struct stb6100_state *state = fe->tuner_priv;
423 struct tuner_state *status = &state->status;
424
425 status->tunerstep = 125000;
426 status->ifreq = 0;
427 status->refclock = 27000000; /* Hz */
428 status->iqsense = 1;
429 status->bandwidth = 36000; /* kHz */
430 state->bandwidth = status->bandwidth * 1000; /* MHz */
431 state->reference = status->refclock / 1000; /* kHz */
432
433 /* Set default bandwidth. */
434 return stb6100_set_bandwidth(fe, status->bandwidth);
435}
436
437static int stb6100_get_state(struct dvb_frontend *fe,
438 enum tuner_param param,
439 struct tuner_state *state)
440{
441 switch (param) {
442 case DVBFE_TUNER_FREQUENCY:
443 stb6100_get_frequency(fe, &state->frequency);
444 break;
445 case DVBFE_TUNER_TUNERSTEP:
446 break;
447 case DVBFE_TUNER_IFFREQ:
448 break;
449 case DVBFE_TUNER_BANDWIDTH:
450 stb6100_get_bandwidth(fe, &state->bandwidth);
451 break;
452 case DVBFE_TUNER_REFCLOCK:
453 break;
454 default:
455 break;
456 }
457
458 return 0;
459}
460
461static int stb6100_set_state(struct dvb_frontend *fe,
462 enum tuner_param param,
463 struct tuner_state *state)
464{
465 struct stb6100_state *tstate = fe->tuner_priv;
466
467 switch (param) {
468 case DVBFE_TUNER_FREQUENCY:
469 stb6100_set_frequency(fe, state->frequency);
470 tstate->frequency = state->frequency;
471 break;
472 case DVBFE_TUNER_TUNERSTEP:
473 break;
474 case DVBFE_TUNER_IFFREQ:
475 break;
476 case DVBFE_TUNER_BANDWIDTH:
477 stb6100_set_bandwidth(fe, state->bandwidth);
478 tstate->bandwidth = state->bandwidth;
479 break;
480 case DVBFE_TUNER_REFCLOCK:
481 break;
482 default:
483 break;
484 }
485
486 return 0;
487}
488
489static struct dvb_tuner_ops stb6100_ops = {
490 .info = {
491 .name = "STB6100 Silicon Tuner",
492 .frequency_min = 950000,
493 .frequency_max = 2150000,
494 .frequency_step = 0,
495 },
496
497 .init = stb6100_init,
498 .sleep = stb6100_sleep,
499 .get_status = stb6100_get_status,
500 .get_state = stb6100_get_state,
501 .set_state = stb6100_set_state,
502 .release = stb6100_release
503};
504
505struct dvb_frontend *stb6100_attach(struct dvb_frontend *fe,
506 struct stb6100_config *config,
507 struct i2c_adapter *i2c)
508{
509 struct stb6100_state *state = NULL;
510
511 state = kzalloc(sizeof (struct stb6100_state), GFP_KERNEL);
512 if (state == NULL)
513 goto error;
514
515 state->config = config;
516 state->i2c = i2c;
517 state->frontend = fe;
518 state->reference = config->refclock / 1000; /* kHz */
519 fe->tuner_priv = state;
520 fe->ops.tuner_ops = stb6100_ops;
521
522 printk("%s: Attaching STB6100 \n", __func__);
523 return fe;
524
525error:
526 kfree(state);
527 return NULL;
528}
529
530static int stb6100_release(struct dvb_frontend *fe)
531{
532 struct stb6100_state *state = fe->tuner_priv;
533
534 fe->tuner_priv = NULL;
535 kfree(state);
536
537 return 0;
538}
539
540EXPORT_SYMBOL(stb6100_attach);
541MODULE_PARM_DESC(verbose, "Set Verbosity level");
542
543MODULE_AUTHOR("Manu Abraham");
544MODULE_DESCRIPTION("STB6100 Silicon tuner");
545MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stb6100.h b/drivers/media/dvb/frontends/stb6100.h
new file mode 100644
index 000000000000..395d056599a6
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb6100.h
@@ -0,0 +1,115 @@
1/*
2 STB6100 Silicon Tuner
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STB_6100_REG_H
23#define __STB_6100_REG_H
24
25#include <linux/dvb/frontend.h>
26#include "dvb_frontend.h"
27
28#define STB6100_LD 0x00
29#define STB6100_LD_LOCK (1 << 0)
30
31#define STB6100_VCO 0x01
32#define STB6100_VCO_OSCH (0x01 << 7)
33#define STB6100_VCO_OSCH_SHIFT 7
34#define STB6100_VCO_OCK (0x03 << 5)
35#define STB6100_VCO_OCK_SHIFT 5
36#define STB6100_VCO_ODIV (0x01 << 4)
37#define STB6100_VCO_ODIV_SHIFT 4
38#define STB6100_VCO_OSM (0x0f << 0)
39
40#define STB6100_NI 0x02
41#define STB6100_NF_LSB 0x03
42
43#define STB6100_K 0x04
44#define STB6100_K_PSD2 (0x01 << 2)
45#define STB6100_K_PSD2_SHIFT 2
46#define STB6100_K_NF_MSB (0x03 << 0)
47
48#define STB6100_G 0x05
49#define STB6100_G_G (0x0f << 0)
50#define STB6100_G_GCT (0x07 << 5)
51
52#define STB6100_F 0x06
53#define STB6100_F_F (0x1f << 0)
54
55#define STB6100_DLB 0x07
56
57#define STB6100_TEST1 0x08
58
59#define STB6100_FCCK 0x09
60#define STB6100_FCCK_FCCK (0x01 << 6)
61
62#define STB6100_LPEN 0x0a
63#define STB6100_LPEN_LPEN (0x01 << 4)
64#define STB6100_LPEN_SYNP (0x01 << 5)
65#define STB6100_LPEN_OSCP (0x01 << 6)
66#define STB6100_LPEN_BEN (0x01 << 7)
67
68#define STB6100_TEST3 0x0b
69
70#define STB6100_NUMREGS 0x0c
71
72
73#define INRANGE(val, x, y) (((x <= val) && (val <= y)) || \
74 ((y <= val) && (val <= x)) ? 1 : 0)
75
76#define CHKRANGE(val, x, y) (((val >= x) && (val < y)) ? 1 : 0)
77
78struct stb6100_config {
79 u8 tuner_address;
80 u32 refclock;
81};
82
83struct stb6100_state {
84 struct i2c_adapter *i2c;
85
86 const struct stb6100_config *config;
87 struct dvb_tuner_ops ops;
88 struct dvb_frontend *frontend;
89 struct tuner_state status;
90
91 u32 frequency;
92 u32 srate;
93 u32 bandwidth;
94 u32 reference;
95};
96
97#if defined(CONFIG_DVB_STB6100) || (defined(CONFIG_DVB_STB6100_MODULE) && defined(MODULE))
98
99extern struct dvb_frontend *stb6100_attach(struct dvb_frontend *fe,
100 struct stb6100_config *config,
101 struct i2c_adapter *i2c);
102
103#else
104
105static inline struct dvb_frontend *stb6100_attach(struct dvb_frontend *fe,
106 struct stb6100_config *config,
107 struct i2c_adapter *i2c)
108{
109 printk(KERN_WARNING "%s: Driver disabled by Kconfig\n", __func__);
110 return NULL;
111}
112
113#endif //CONFIG_DVB_STB6100
114
115#endif
diff --git a/drivers/media/dvb/frontends/stb6100_cfg.h b/drivers/media/dvb/frontends/stb6100_cfg.h
new file mode 100644
index 000000000000..d3133405dc03
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb6100_cfg.h
@@ -0,0 +1,108 @@
1/*
2 STB6100 Silicon Tuner
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22static int stb6100_get_frequency(struct dvb_frontend *fe, u32 *frequency)
23{
24 struct dvb_frontend_ops *frontend_ops = NULL;
25 struct dvb_tuner_ops *tuner_ops = NULL;
26 struct tuner_state t_state;
27 int err = 0;
28
29 if (&fe->ops)
30 frontend_ops = &fe->ops;
31 if (&frontend_ops->tuner_ops)
32 tuner_ops = &frontend_ops->tuner_ops;
33 if (tuner_ops->get_state) {
34 if ((err = tuner_ops->get_state(fe, DVBFE_TUNER_FREQUENCY, &t_state)) < 0) {
35 printk("%s: Invalid parameter\n", __func__);
36 return err;
37 }
38 *frequency = t_state.frequency;
39 printk("%s: Frequency=%d\n", __func__, t_state.frequency);
40 }
41 return 0;
42}
43
44static int stb6100_set_frequency(struct dvb_frontend *fe, u32 frequency)
45{
46 struct dvb_frontend_ops *frontend_ops = NULL;
47 struct dvb_tuner_ops *tuner_ops = NULL;
48 struct tuner_state t_state;
49 int err = 0;
50
51 t_state.frequency = frequency;
52 if (&fe->ops)
53 frontend_ops = &fe->ops;
54 if (&frontend_ops->tuner_ops)
55 tuner_ops = &frontend_ops->tuner_ops;
56 if (tuner_ops->set_state) {
57 if ((err = tuner_ops->set_state(fe, DVBFE_TUNER_FREQUENCY, &t_state)) < 0) {
58 printk("%s: Invalid parameter\n", __func__);
59 return err;
60 }
61 }
62 printk("%s: Frequency=%d\n", __func__, t_state.frequency);
63 return 0;
64}
65
66static int stb6100_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
67{
68 struct dvb_frontend_ops *frontend_ops = &fe->ops;
69 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
70 struct tuner_state t_state;
71 int err = 0;
72
73 if (&fe->ops)
74 frontend_ops = &fe->ops;
75 if (&frontend_ops->tuner_ops)
76 tuner_ops = &frontend_ops->tuner_ops;
77 if (tuner_ops->get_state) {
78 if ((err = tuner_ops->get_state(fe, DVBFE_TUNER_BANDWIDTH, &t_state)) < 0) {
79 printk("%s: Invalid parameter\n", __func__);
80 return err;
81 }
82 *bandwidth = t_state.bandwidth;
83 }
84 printk("%s: Bandwidth=%d\n", __func__, t_state.bandwidth);
85 return 0;
86}
87
88static int stb6100_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
89{
90 struct dvb_frontend_ops *frontend_ops = NULL;
91 struct dvb_tuner_ops *tuner_ops = NULL;
92 struct tuner_state t_state;
93 int err = 0;
94
95 t_state.bandwidth = bandwidth;
96 if (&fe->ops)
97 frontend_ops = &fe->ops;
98 if (&frontend_ops->tuner_ops)
99 tuner_ops = &frontend_ops->tuner_ops;
100 if (tuner_ops->set_state) {
101 if ((err = tuner_ops->set_state(fe, DVBFE_TUNER_BANDWIDTH, &t_state)) < 0) {
102 printk("%s: Invalid parameter\n", __func__);
103 return err;
104 }
105 }
106 printk("%s: Bandwidth=%d\n", __func__, t_state.bandwidth);
107 return 0;
108}
diff --git a/drivers/media/dvb/frontends/tda8261.c b/drivers/media/dvb/frontends/tda8261.c
new file mode 100644
index 000000000000..b6d177799104
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda8261.c
@@ -0,0 +1,230 @@
1/*
2 TDA8261 8PSK/QPSK tuner driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18*/
19
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24
25#include "dvb_frontend.h"
26#include "tda8261.h"
27
28struct tda8261_state {
29 struct dvb_frontend *fe;
30 struct i2c_adapter *i2c;
31 const struct tda8261_config *config;
32
33 /* state cache */
34 u32 frequency;
35 u32 bandwidth;
36};
37
38static int tda8261_read(struct tda8261_state *state, u8 *buf)
39{
40 const struct tda8261_config *config = state->config;
41 int err = 0;
42 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD,.buf = buf, .len = 2 };
43
44 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1)
45 printk("%s: read error, err=%d\n", __func__, err);
46
47 return err;
48}
49
50static int tda8261_write(struct tda8261_state *state, u8 *buf)
51{
52 const struct tda8261_config *config = state->config;
53 int err = 0;
54 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 };
55
56 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1)
57 printk("%s: write error, err=%d\n", __func__, err);
58
59 return err;
60}
61
62static int tda8261_get_status(struct dvb_frontend *fe, u32 *status)
63{
64 struct tda8261_state *state = fe->tuner_priv;
65 u8 result = 0;
66 int err = 0;
67
68 *status = 0;
69
70 if ((err = tda8261_read(state, &result)) < 0) {
71 printk("%s: I/O Error\n", __func__);
72 return err;
73 }
74 if ((result >> 6) & 0x01) {
75 printk("%s: Tuner Phase Locked\n", __func__);
76 *status = 1;
77 }
78
79 return err;
80}
81
82static const u32 div_tab[] = { 2000, 1000, 500, 250, 125 }; /* kHz */
83static const u8 ref_div[] = { 0x00, 0x01, 0x02, 0x05, 0x07 };
84
85static int tda8261_get_state(struct dvb_frontend *fe,
86 enum tuner_param param,
87 struct tuner_state *tstate)
88{
89 struct tda8261_state *state = fe->tuner_priv;
90 int err = 0;
91
92 switch (param) {
93 case DVBFE_TUNER_FREQUENCY:
94 tstate->frequency = state->frequency;
95 break;
96 case DVBFE_TUNER_BANDWIDTH:
97 tstate->bandwidth = 40000000; /* FIXME! need to calculate Bandwidth */
98 break;
99 default:
100 printk("%s: Unknown parameter (param=%d)\n", __func__, param);
101 err = -EINVAL;
102 break;
103 }
104
105 return err;
106}
107
108static int tda8261_set_state(struct dvb_frontend *fe,
109 enum tuner_param param,
110 struct tuner_state *tstate)
111{
112 struct tda8261_state *state = fe->tuner_priv;
113 const struct tda8261_config *config = state->config;
114 u32 frequency, N, status = 0;
115 u8 buf[4];
116 int err = 0;
117
118 if (param & DVBFE_TUNER_FREQUENCY) {
119 /**
120 * N = Max VCO Frequency / Channel Spacing
121 * Max VCO Frequency = VCO frequency + (channel spacing - 1)
122 * (to account for half channel spacing on either side)
123 */
124 frequency = tstate->frequency;
125 if ((frequency < 950000) || (frequency > 2150000)) {
126 printk("%s: Frequency beyond limits, frequency=%d\n", __func__, frequency);
127 return -EINVAL;
128 }
129 N = (frequency + (div_tab[config->step_size] - 1)) / div_tab[config->step_size];
130 printk("%s: Step size=%d, Divider=%d, PG=0x%02x (%d)\n",
131 __func__, config->step_size, div_tab[config->step_size], N, N);
132
133 buf[0] = (N >> 8) & 0xff;
134 buf[1] = N & 0xff;
135 buf[2] = (0x01 << 7) | ((ref_div[config->step_size] & 0x07) << 1);
136
137 if (frequency < 1450000)
138 buf[3] = 0x00;
139 if (frequency < 2000000)
140 buf[3] = 0x40;
141 if (frequency < 2150000)
142 buf[3] = 0x80;
143
144 /* Set params */
145 if ((err = tda8261_write(state, buf)) < 0) {
146 printk("%s: I/O Error\n", __func__);
147 return err;
148 }
149 /* sleep for some time */
150 printk("%s: Waiting to Phase LOCK\n", __func__);
151 msleep(20);
152 /* check status */
153 if ((err = tda8261_get_status(fe, &status)) < 0) {
154 printk("%s: I/O Error\n", __func__);
155 return err;
156 }
157 if (status == 1) {
158 printk("%s: Tuner Phase locked: status=%d\n", __func__, status);
159 state->frequency = frequency; /* cache successful state */
160 } else {
161 printk("%s: No Phase lock: status=%d\n", __func__, status);
162 }
163 } else {
164 printk("%s: Unknown parameter (param=%d)\n", __func__, param);
165 return -EINVAL;
166 }
167
168 return 0;
169}
170
171static int tda8261_release(struct dvb_frontend *fe)
172{
173 struct tda8261_state *state = fe->tuner_priv;
174
175 fe->tuner_priv = NULL;
176 kfree(state);
177 return 0;
178}
179
180static struct dvb_tuner_ops tda8261_ops = {
181
182 .info = {
183 .name = "TDA8261",
184// .tuner_name = NULL,
185 .frequency_min = 950000,
186 .frequency_max = 2150000,
187 .frequency_step = 0
188 },
189
190 .set_state = tda8261_set_state,
191 .get_state = tda8261_get_state,
192 .get_status = tda8261_get_status,
193 .release = tda8261_release
194};
195
196struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe,
197 const struct tda8261_config *config,
198 struct i2c_adapter *i2c)
199{
200 struct tda8261_state *state = NULL;
201
202 if ((state = kzalloc(sizeof (struct tda8261_state), GFP_KERNEL)) == NULL)
203 goto exit;
204
205 state->config = config;
206 state->i2c = i2c;
207 state->fe = fe;
208 fe->tuner_priv = state;
209 fe->ops.tuner_ops = tda8261_ops;
210
211 fe->ops.tuner_ops.info.frequency_step = div_tab[config->step_size];
212// fe->ops.tuner_ops.tuner_name = &config->buf;
213
214// printk("%s: Attaching %s TDA8261 8PSK/QPSK tuner\n",
215// __func__, fe->ops.tuner_ops.tuner_name);
216 printk("%s: Attaching TDA8261 8PSK/QPSK tuner\n", __func__);
217
218 return fe;
219
220exit:
221 kfree(state);
222 return NULL;
223}
224
225EXPORT_SYMBOL(tda8261_attach);
226MODULE_PARM_DESC(verbose, "Set verbosity level");
227
228MODULE_AUTHOR("Manu Abraham");
229MODULE_DESCRIPTION("TDA8261 8PSK/QPSK Tuner");
230MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/tda8261.h b/drivers/media/dvb/frontends/tda8261.h
new file mode 100644
index 000000000000..006e45351b94
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda8261.h
@@ -0,0 +1,55 @@
1/*
2 TDA8261 8PSK/QPSK tuner driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18*/
19
20#ifndef __TDA8261_H
21#define __TDA8261_H
22
23enum tda8261_step {
24 TDA8261_STEP_2000 = 0, /* 2000 kHz */
25 TDA8261_STEP_1000, /* 1000 kHz */
26 TDA8261_STEP_500, /* 500 kHz */
27 TDA8261_STEP_250, /* 250 kHz */
28 TDA8261_STEP_125 /* 125 kHz */
29};
30
31struct tda8261_config {
32// u8 buf[16];
33 u8 addr;
34 enum tda8261_step step_size;
35};
36
37#if defined(CONFIG_DVB_TDA8261) || (defined(CONFIG_DVB_TDA8261_MODULE) && defined(MODULE))
38
39extern struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe,
40 const struct tda8261_config *config,
41 struct i2c_adapter *i2c);
42
43#else
44
45static inline struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe,
46 const struct tda8261_config *config,
47 struct i2c_adapter *i2c)
48{
49 printk(KERN_WARNING "%s: Driver disabled by Kconfig\n", __func__);
50 return NULL;
51}
52
53#endif //CONFIG_DVB_TDA8261
54
55#endif// __TDA8261_H
diff --git a/drivers/media/dvb/frontends/tda8261_cfg.h b/drivers/media/dvb/frontends/tda8261_cfg.h
new file mode 100644
index 000000000000..1af1ee49b542
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda8261_cfg.h
@@ -0,0 +1,84 @@
1/*
2 TDA8261 8PSK/QPSK tuner driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18*/
19
20static int tda8261_get_frequency(struct dvb_frontend *fe, u32 *frequency)
21{
22 struct dvb_frontend_ops *frontend_ops = NULL;
23 struct dvb_tuner_ops *tuner_ops = NULL;
24 struct tuner_state t_state;
25 int err = 0;
26
27 if (&fe->ops)
28 frontend_ops = &fe->ops;
29 if (&frontend_ops->tuner_ops)
30 tuner_ops = &frontend_ops->tuner_ops;
31 if (tuner_ops->get_state) {
32 if ((err = tuner_ops->get_state(fe, DVBFE_TUNER_FREQUENCY, &t_state)) < 0) {
33 printk("%s: Invalid parameter\n", __func__);
34 return err;
35 }
36 *frequency = t_state.frequency;
37 printk("%s: Frequency=%d\n", __func__, t_state.frequency);
38 }
39 return 0;
40}
41
42static int tda8261_set_frequency(struct dvb_frontend *fe, u32 frequency)
43{
44 struct dvb_frontend_ops *frontend_ops = NULL;
45 struct dvb_tuner_ops *tuner_ops = NULL;
46 struct tuner_state t_state;
47 int err = 0;
48
49 t_state.frequency = frequency;
50 if (&fe->ops)
51 frontend_ops = &fe->ops;
52 if (&frontend_ops->tuner_ops)
53 tuner_ops = &frontend_ops->tuner_ops;
54 if (tuner_ops->set_state) {
55 if ((err = tuner_ops->set_state(fe, DVBFE_TUNER_FREQUENCY, &t_state)) < 0) {
56 printk("%s: Invalid parameter\n", __func__);
57 return err;
58 }
59 }
60 printk("%s: Frequency=%d\n", __func__, t_state.frequency);
61 return 0;
62}
63
64static int tda8261_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
65{
66 struct dvb_frontend_ops *frontend_ops = &fe->ops;
67 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
68 struct tuner_state t_state;
69 int err = 0;
70
71 if (&fe->ops)
72 frontend_ops = &fe->ops;
73 if (&frontend_ops->tuner_ops)
74 tuner_ops = &frontend_ops->tuner_ops;
75 if (tuner_ops->get_state) {
76 if ((err = tuner_ops->get_state(fe, DVBFE_TUNER_BANDWIDTH, &t_state)) < 0) {
77 printk("%s: Invalid parameter\n", __func__);
78 return err;
79 }
80 *bandwidth = t_state.bandwidth;
81 }
82 printk("%s: Bandwidth=%d\n", __func__, t_state.bandwidth);
83 return 0;
84}
diff --git a/drivers/media/dvb/frontends/zl10353.c b/drivers/media/dvb/frontends/zl10353.c
index 36a5a1c101d5..5506f80e180e 100644
--- a/drivers/media/dvb/frontends/zl10353.c
+++ b/drivers/media/dvb/frontends/zl10353.c
@@ -220,15 +220,18 @@ static int zl10353_set_parameters(struct dvb_frontend *fe,
220 /* These are extrapolated from the 7 and 8MHz values */ 220 /* These are extrapolated from the 7 and 8MHz values */
221 zl10353_single_write(fe, MCLK_RATIO, 0x97); 221 zl10353_single_write(fe, MCLK_RATIO, 0x97);
222 zl10353_single_write(fe, 0x64, 0x34); 222 zl10353_single_write(fe, 0x64, 0x34);
223 zl10353_single_write(fe, 0xcc, 0xdd);
223 break; 224 break;
224 case BANDWIDTH_7_MHZ: 225 case BANDWIDTH_7_MHZ:
225 zl10353_single_write(fe, MCLK_RATIO, 0x86); 226 zl10353_single_write(fe, MCLK_RATIO, 0x86);
226 zl10353_single_write(fe, 0x64, 0x35); 227 zl10353_single_write(fe, 0x64, 0x35);
228 zl10353_single_write(fe, 0xcc, 0x73);
227 break; 229 break;
228 case BANDWIDTH_8_MHZ: 230 case BANDWIDTH_8_MHZ:
229 default: 231 default:
230 zl10353_single_write(fe, MCLK_RATIO, 0x75); 232 zl10353_single_write(fe, MCLK_RATIO, 0x75);
231 zl10353_single_write(fe, 0x64, 0x36); 233 zl10353_single_write(fe, 0x64, 0x36);
234 zl10353_single_write(fe, 0xcc, 0x73);
232 } 235 }
233 236
234 zl10353_calc_nominal_rate(fe, op->bandwidth, &nominal_rate); 237 zl10353_calc_nominal_rate(fe, op->bandwidth, &nominal_rate);
diff --git a/drivers/media/dvb/siano/sms-cards.c b/drivers/media/dvb/siano/sms-cards.c
index e98d6caf2c23..fd62e0b85621 100644
--- a/drivers/media/dvb/siano/sms-cards.c
+++ b/drivers/media/dvb/siano/sms-cards.c
@@ -38,6 +38,16 @@ struct usb_device_id smsusb_id_table[] = {
38 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_OKEMO_A }, 38 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_OKEMO_A },
39 { USB_DEVICE(0x2040, 0x1801), 39 { USB_DEVICE(0x2040, 0x1801),
40 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_OKEMO_B }, 40 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_OKEMO_B },
41 { USB_DEVICE(0x2040, 0x2000),
42 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD },
43 { USB_DEVICE(0x2040, 0x2009),
44 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2 },
45 { USB_DEVICE(0x2040, 0x200a),
46 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD },
47 { USB_DEVICE(0x2040, 0x2010),
48 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD },
49 { USB_DEVICE(0x2040, 0x2019),
50 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD },
41 { USB_DEVICE(0x2040, 0x5500), 51 { USB_DEVICE(0x2040, 0x5500),
42 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_WINDHAM }, 52 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_WINDHAM },
43 { USB_DEVICE(0x2040, 0x5510), 53 { USB_DEVICE(0x2040, 0x5510),
@@ -96,6 +106,21 @@ static struct sms_board sms_boards[] = {
96 .name = "Hauppauge WinTV MiniStick", 106 .name = "Hauppauge WinTV MiniStick",
97 .type = SMS_NOVA_B0, 107 .type = SMS_NOVA_B0,
98 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw", 108 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw",
109 .led_power = 26,
110 .led_lo = 27,
111 .led_hi = 28,
112 },
113 [SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD] = {
114 .name = "Hauppauge WinTV MiniCard",
115 .type = SMS_NOVA_B0,
116 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw",
117 .lna_ctrl = 29,
118 },
119 [SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2] = {
120 .name = "Hauppauge WinTV MiniCard",
121 .type = SMS_NOVA_B0,
122 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw",
123 .lna_ctrl = 1,
99 }, 124 },
100}; 125};
101 126
@@ -106,3 +131,88 @@ struct sms_board *sms_get_board(int id)
106 return &sms_boards[id]; 131 return &sms_boards[id];
107} 132}
108 133
134static int sms_set_gpio(struct smscore_device_t *coredev, u32 pin, int enable)
135{
136 int ret;
137 struct smscore_gpio_config gpioconfig = {
138 .direction = SMS_GPIO_DIRECTION_OUTPUT,
139 .pullupdown = SMS_GPIO_PULLUPDOWN_NONE,
140 .inputcharacteristics = SMS_GPIO_INPUTCHARACTERISTICS_NORMAL,
141 .outputslewrate = SMS_GPIO_OUTPUTSLEWRATE_FAST,
142 .outputdriving = SMS_GPIO_OUTPUTDRIVING_4mA,
143 };
144
145 if (pin == 0)
146 return -EINVAL;
147
148 ret = smscore_configure_gpio(coredev, pin, &gpioconfig);
149
150 if (ret < 0)
151 return ret;
152
153 return smscore_set_gpio(coredev, pin, enable);
154}
155
156int sms_board_setup(struct smscore_device_t *coredev)
157{
158 int board_id = smscore_get_board_id(coredev);
159 struct sms_board *board = sms_get_board(board_id);
160
161 switch (board_id) {
162 case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
163 /* turn off all LEDs */
164 sms_set_gpio(coredev, board->led_power, 0);
165 sms_set_gpio(coredev, board->led_hi, 0);
166 sms_set_gpio(coredev, board->led_lo, 0);
167 break;
168 case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2:
169 case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD:
170 /* turn off LNA */
171 sms_set_gpio(coredev, board->lna_ctrl, 0);
172 break;
173 }
174 return 0;
175}
176
177int sms_board_power(struct smscore_device_t *coredev, int onoff)
178{
179 int board_id = smscore_get_board_id(coredev);
180 struct sms_board *board = sms_get_board(board_id);
181
182 switch (board_id) {
183 case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
184 /* power LED */
185 sms_set_gpio(coredev,
186 board->led_power, onoff ? 1 : 0);
187 break;
188 case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2:
189 case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD:
190 /* LNA */
191 sms_set_gpio(coredev,
192 board->lna_ctrl, onoff ? 1 : 0);
193 break;
194 }
195 return 0;
196}
197
198int sms_board_led_feedback(struct smscore_device_t *coredev, int led)
199{
200 int board_id = smscore_get_board_id(coredev);
201 struct sms_board *board = sms_get_board(board_id);
202
203 /* dont touch GPIO if LEDs are already set */
204 if (smscore_led_state(coredev, -1) == led)
205 return 0;
206
207 switch (board_id) {
208 case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
209 sms_set_gpio(coredev,
210 board->led_lo, (led & SMS_LED_LO) ? 1 : 0);
211 sms_set_gpio(coredev,
212 board->led_hi, (led & SMS_LED_HI) ? 1 : 0);
213
214 smscore_led_state(coredev, led);
215 break;
216 }
217 return 0;
218}
diff --git a/drivers/media/dvb/siano/sms-cards.h b/drivers/media/dvb/siano/sms-cards.h
index c8f3da6f9bc1..8e0fe9fd2610 100644
--- a/drivers/media/dvb/siano/sms-cards.h
+++ b/drivers/media/dvb/siano/sms-cards.h
@@ -32,14 +32,27 @@
32#define SMS1XXX_BOARD_HAUPPAUGE_OKEMO_A 6 32#define SMS1XXX_BOARD_HAUPPAUGE_OKEMO_A 6
33#define SMS1XXX_BOARD_HAUPPAUGE_OKEMO_B 7 33#define SMS1XXX_BOARD_HAUPPAUGE_OKEMO_B 7
34#define SMS1XXX_BOARD_HAUPPAUGE_WINDHAM 8 34#define SMS1XXX_BOARD_HAUPPAUGE_WINDHAM 8
35#define SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD 9
36#define SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2 10
35 37
36struct sms_board { 38struct sms_board {
37 enum sms_device_type_st type; 39 enum sms_device_type_st type;
38 char *name, *fw[DEVICE_MODE_MAX]; 40 char *name, *fw[DEVICE_MODE_MAX];
41
42 /* gpios */
43 int led_power, led_hi, led_lo, lna_ctrl;
39}; 44};
40 45
41struct sms_board *sms_get_board(int id); 46struct sms_board *sms_get_board(int id);
42 47
48int sms_board_setup(struct smscore_device_t *coredev);
49
50#define SMS_LED_OFF 0
51#define SMS_LED_LO 1
52#define SMS_LED_HI 2
53int sms_board_led_feedback(struct smscore_device_t *coredev, int led);
54int sms_board_power(struct smscore_device_t *coredev, int onoff);
55
43extern struct usb_device_id smsusb_id_table[]; 56extern struct usb_device_id smsusb_id_table[];
44 57
45#endif /* __SMS_CARDS_H__ */ 58#endif /* __SMS_CARDS_H__ */
diff --git a/drivers/media/dvb/siano/smscoreapi.c b/drivers/media/dvb/siano/smscoreapi.c
index 6576fbb40fc6..cf613f22fb8d 100644
--- a/drivers/media/dvb/siano/smscoreapi.c
+++ b/drivers/media/dvb/siano/smscoreapi.c
@@ -91,6 +91,7 @@ struct smscore_device_t {
91 struct completion init_device_done, reload_start_done, resume_done; 91 struct completion init_device_done, reload_start_done, resume_done;
92 92
93 int board_id; 93 int board_id;
94 int led_state;
94}; 95};
95 96
96void smscore_set_board_id(struct smscore_device_t *core, int id) 97void smscore_set_board_id(struct smscore_device_t *core, int id)
@@ -98,6 +99,13 @@ void smscore_set_board_id(struct smscore_device_t *core, int id)
98 core->board_id = id; 99 core->board_id = id;
99} 100}
100 101
102int smscore_led_state(struct smscore_device_t *core, int led)
103{
104 if (led >= 0)
105 core->led_state = led;
106 return core->led_state;
107}
108
101int smscore_get_board_id(struct smscore_device_t *core) 109int smscore_get_board_id(struct smscore_device_t *core)
102{ 110{
103 return core->board_id; 111 return core->board_id;
@@ -1187,6 +1195,76 @@ int smsclient_sendrequest(struct smscore_client_t *client,
1187} 1195}
1188 1196
1189 1197
1198int smscore_configure_gpio(struct smscore_device_t *coredev, u32 pin,
1199 struct smscore_gpio_config *pinconfig)
1200{
1201 struct {
1202 struct SmsMsgHdr_ST hdr;
1203 u32 data[6];
1204 } msg;
1205
1206 if (coredev->device_flags & SMS_DEVICE_FAMILY2) {
1207 msg.hdr.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
1208 msg.hdr.msgDstId = HIF_TASK;
1209 msg.hdr.msgFlags = 0;
1210 msg.hdr.msgType = MSG_SMS_GPIO_CONFIG_EX_REQ;
1211 msg.hdr.msgLength = sizeof(msg);
1212
1213 msg.data[0] = pin;
1214 msg.data[1] = pinconfig->pullupdown;
1215
1216 /* Convert slew rate for Nova: Fast(0) = 3 / Slow(1) = 0; */
1217 msg.data[2] = pinconfig->outputslewrate == 0 ? 3 : 0;
1218
1219 switch (pinconfig->outputdriving) {
1220 case SMS_GPIO_OUTPUTDRIVING_16mA:
1221 msg.data[3] = 7; /* Nova - 16mA */
1222 break;
1223 case SMS_GPIO_OUTPUTDRIVING_12mA:
1224 msg.data[3] = 5; /* Nova - 11mA */
1225 break;
1226 case SMS_GPIO_OUTPUTDRIVING_8mA:
1227 msg.data[3] = 3; /* Nova - 7mA */
1228 break;
1229 case SMS_GPIO_OUTPUTDRIVING_4mA:
1230 default:
1231 msg.data[3] = 2; /* Nova - 4mA */
1232 break;
1233 }
1234
1235 msg.data[4] = pinconfig->direction;
1236 msg.data[5] = 0;
1237 } else /* TODO: SMS_DEVICE_FAMILY1 */
1238 return -EINVAL;
1239
1240 return coredev->sendrequest_handler(coredev->context,
1241 &msg, sizeof(msg));
1242}
1243
1244int smscore_set_gpio(struct smscore_device_t *coredev, u32 pin, int level)
1245{
1246 struct {
1247 struct SmsMsgHdr_ST hdr;
1248 u32 data[3];
1249 } msg;
1250
1251 if (pin > MAX_GPIO_PIN_NUMBER)
1252 return -EINVAL;
1253
1254 msg.hdr.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
1255 msg.hdr.msgDstId = HIF_TASK;
1256 msg.hdr.msgFlags = 0;
1257 msg.hdr.msgType = MSG_SMS_GPIO_SET_LEVEL_REQ;
1258 msg.hdr.msgLength = sizeof(msg);
1259
1260 msg.data[0] = pin;
1261 msg.data[1] = level ? 1 : 0;
1262 msg.data[2] = 0;
1263
1264 return coredev->sendrequest_handler(coredev->context,
1265 &msg, sizeof(msg));
1266}
1267
1190static int __init smscore_module_init(void) 1268static int __init smscore_module_init(void)
1191{ 1269{
1192 int rc = 0; 1270 int rc = 0;
diff --git a/drivers/media/dvb/siano/smscoreapi.h b/drivers/media/dvb/siano/smscoreapi.h
index 8d973f726fb8..760e233fcbc5 100644
--- a/drivers/media/dvb/siano/smscoreapi.h
+++ b/drivers/media/dvb/siano/smscoreapi.h
@@ -186,6 +186,8 @@ struct smsclient_params_t {
186#define MSG_SW_RELOAD_EXEC_REQ 704 186#define MSG_SW_RELOAD_EXEC_REQ 704
187#define MSG_SW_RELOAD_EXEC_RES 705 187#define MSG_SW_RELOAD_EXEC_RES 705
188#define MSG_SMS_SPI_INT_LINE_SET_REQ 710 188#define MSG_SMS_SPI_INT_LINE_SET_REQ 710
189#define MSG_SMS_GPIO_CONFIG_EX_REQ 712
190#define MSG_SMS_GPIO_CONFIG_EX_RES 713
189#define MSG_SMS_ISDBT_TUNE_REQ 776 191#define MSG_SMS_ISDBT_TUNE_REQ 776
190#define MSG_SMS_ISDBT_TUNE_RES 777 192#define MSG_SMS_ISDBT_TUNE_RES 777
191 193
@@ -341,6 +343,32 @@ struct SmsMsgStatisticsInfo_ST {
341}; 343};
342 344
343 345
346struct smscore_gpio_config {
347#define SMS_GPIO_DIRECTION_INPUT 0
348#define SMS_GPIO_DIRECTION_OUTPUT 1
349 u8 direction;
350
351#define SMS_GPIO_PULLUPDOWN_NONE 0
352#define SMS_GPIO_PULLUPDOWN_PULLDOWN 1
353#define SMS_GPIO_PULLUPDOWN_PULLUP 2
354#define SMS_GPIO_PULLUPDOWN_KEEPER 3
355 u8 pullupdown;
356
357#define SMS_GPIO_INPUTCHARACTERISTICS_NORMAL 0
358#define SMS_GPIO_INPUTCHARACTERISTICS_SCHMITT 1
359 u8 inputcharacteristics;
360
361#define SMS_GPIO_OUTPUTSLEWRATE_FAST 0
362#define SMS_GPIO_OUTPUTSLEWRATE_SLOW 1
363 u8 outputslewrate;
364
365#define SMS_GPIO_OUTPUTDRIVING_4mA 0
366#define SMS_GPIO_OUTPUTDRIVING_8mA 1
367#define SMS_GPIO_OUTPUTDRIVING_12mA 2
368#define SMS_GPIO_OUTPUTDRIVING_16mA 3
369 u8 outputdriving;
370};
371
344struct smsdvb_client_t { 372struct smsdvb_client_t {
345 struct list_head entry; 373 struct list_head entry;
346 374
@@ -353,7 +381,7 @@ struct smsdvb_client_t {
353 struct dvb_frontend frontend; 381 struct dvb_frontend frontend;
354 382
355 fe_status_t fe_status; 383 fe_status_t fe_status;
356 int fe_ber, fe_snr, fe_signal_strength; 384 int fe_ber, fe_snr, fe_unc, fe_signal_strength;
357 385
358 struct completion tune_done, stat_done; 386 struct completion tune_done, stat_done;
359 387
@@ -396,9 +424,15 @@ struct smscore_buffer_t *smscore_getbuffer(struct smscore_device_t *coredev);
396extern void smscore_putbuffer(struct smscore_device_t *coredev, 424extern void smscore_putbuffer(struct smscore_device_t *coredev,
397 struct smscore_buffer_t *cb); 425 struct smscore_buffer_t *cb);
398 426
427int smscore_configure_gpio(struct smscore_device_t *coredev, u32 pin,
428 struct smscore_gpio_config *pinconfig);
429int smscore_set_gpio(struct smscore_device_t *coredev, u32 pin, int level);
430
399void smscore_set_board_id(struct smscore_device_t *core, int id); 431void smscore_set_board_id(struct smscore_device_t *core, int id);
400int smscore_get_board_id(struct smscore_device_t *core); 432int smscore_get_board_id(struct smscore_device_t *core);
401 433
434int smscore_led_state(struct smscore_device_t *core, int led);
435
402/* smsdvb.c */ 436/* smsdvb.c */
403int smsdvb_register(void); 437int smsdvb_register(void);
404void smsdvb_unregister(void); 438void smsdvb_unregister(void);
diff --git a/drivers/media/dvb/siano/smsdvb.c b/drivers/media/dvb/siano/smsdvb.c
index 8d490e133f35..2da953a4f4f5 100644
--- a/drivers/media/dvb/siano/smsdvb.c
+++ b/drivers/media/dvb/siano/smsdvb.c
@@ -60,6 +60,7 @@ static int smsdvb_onresponse(void *context, struct smscore_buffer_t *cb)
60 60
61 client->fe_snr = p->Stat.SNR; 61 client->fe_snr = p->Stat.SNR;
62 client->fe_ber = p->Stat.BER; 62 client->fe_ber = p->Stat.BER;
63 client->fe_unc = p->Stat.BERErrorCount;
63 64
64 if (p->Stat.InBandPwr < -95) 65 if (p->Stat.InBandPwr < -95)
65 client->fe_signal_strength = 0; 66 client->fe_signal_strength = 0;
@@ -72,6 +73,7 @@ static int smsdvb_onresponse(void *context, struct smscore_buffer_t *cb)
72 client->fe_status = 0; 73 client->fe_status = 0;
73 client->fe_snr = 74 client->fe_snr =
74 client->fe_ber = 75 client->fe_ber =
76 client->fe_unc =
75 client->fe_signal_strength = 0; 77 client->fe_signal_strength = 0;
76 } 78 }
77 79
@@ -165,8 +167,18 @@ static int smsdvb_send_statistics_request(struct smsdvb_client_t *client)
165 struct SmsMsgHdr_ST Msg = { MSG_SMS_GET_STATISTICS_REQ, 167 struct SmsMsgHdr_ST Msg = { MSG_SMS_GET_STATISTICS_REQ,
166 DVBT_BDA_CONTROL_MSG_ID, 168 DVBT_BDA_CONTROL_MSG_ID,
167 HIF_TASK, sizeof(struct SmsMsgHdr_ST), 0 }; 169 HIF_TASK, sizeof(struct SmsMsgHdr_ST), 0 };
168 return smsdvb_sendrequest_and_wait(client, &Msg, sizeof(Msg), 170 int ret = smsdvb_sendrequest_and_wait(client, &Msg, sizeof(Msg),
169 &client->stat_done); 171 &client->stat_done);
172 if (ret < 0)
173 return ret;
174
175 if (client->fe_status & FE_HAS_LOCK)
176 sms_board_led_feedback(client->coredev,
177 (client->fe_unc == 0) ?
178 SMS_LED_HI : SMS_LED_LO);
179 else
180 sms_board_led_feedback(client->coredev, SMS_LED_OFF);
181 return ret;
170} 182}
171 183
172static int smsdvb_read_status(struct dvb_frontend *fe, fe_status_t *stat) 184static int smsdvb_read_status(struct dvb_frontend *fe, fe_status_t *stat)
@@ -217,6 +229,18 @@ static int smsdvb_read_snr(struct dvb_frontend *fe, u16 *snr)
217 return rc; 229 return rc;
218} 230}
219 231
232static int smsdvb_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
233{
234 struct smsdvb_client_t *client =
235 container_of(fe, struct smsdvb_client_t, frontend);
236 int rc = smsdvb_send_statistics_request(client);
237
238 if (!rc)
239 *ucblocks = client->fe_unc;
240
241 return rc;
242}
243
220static int smsdvb_get_tune_settings(struct dvb_frontend *fe, 244static int smsdvb_get_tune_settings(struct dvb_frontend *fe,
221 struct dvb_frontend_tune_settings *tune) 245 struct dvb_frontend_tune_settings *tune)
222{ 246{
@@ -273,6 +297,28 @@ static int smsdvb_get_frontend(struct dvb_frontend *fe,
273 /* todo: */ 297 /* todo: */
274 memcpy(fep, &client->fe_params, 298 memcpy(fep, &client->fe_params,
275 sizeof(struct dvb_frontend_parameters)); 299 sizeof(struct dvb_frontend_parameters));
300
301 return 0;
302}
303
304static int smsdvb_init(struct dvb_frontend *fe)
305{
306 struct smsdvb_client_t *client =
307 container_of(fe, struct smsdvb_client_t, frontend);
308
309 sms_board_power(client->coredev, 1);
310
311 return 0;
312}
313
314static int smsdvb_sleep(struct dvb_frontend *fe)
315{
316 struct smsdvb_client_t *client =
317 container_of(fe, struct smsdvb_client_t, frontend);
318
319 sms_board_led_feedback(client->coredev, SMS_LED_OFF);
320 sms_board_power(client->coredev, 0);
321
276 return 0; 322 return 0;
277} 323}
278 324
@@ -308,6 +354,10 @@ static struct dvb_frontend_ops smsdvb_fe_ops = {
308 .read_ber = smsdvb_read_ber, 354 .read_ber = smsdvb_read_ber,
309 .read_signal_strength = smsdvb_read_signal_strength, 355 .read_signal_strength = smsdvb_read_signal_strength,
310 .read_snr = smsdvb_read_snr, 356 .read_snr = smsdvb_read_snr,
357 .read_ucblocks = smsdvb_read_ucblocks,
358
359 .init = smsdvb_init,
360 .sleep = smsdvb_sleep,
311}; 361};
312 362
313static int smsdvb_hotplug(struct smscore_device_t *coredev, 363static int smsdvb_hotplug(struct smscore_device_t *coredev,
@@ -402,6 +452,8 @@ static int smsdvb_hotplug(struct smscore_device_t *coredev,
402 452
403 sms_info("success"); 453 sms_info("success");
404 454
455 sms_board_setup(coredev);
456
405 return 0; 457 return 0;
406 458
407client_error: 459client_error:
diff --git a/drivers/media/dvb/siano/smsusb.c b/drivers/media/dvb/siano/smsusb.c
index 87a3c24454b9..5d7ca3417719 100644
--- a/drivers/media/dvb/siano/smsusb.c
+++ b/drivers/media/dvb/siano/smsusb.c
@@ -432,11 +432,56 @@ static void smsusb_disconnect(struct usb_interface *intf)
432 smsusb_term_device(intf); 432 smsusb_term_device(intf);
433} 433}
434 434
435static int smsusb_suspend(struct usb_interface *intf, pm_message_t msg)
436{
437 struct smsusb_device_t *dev =
438 (struct smsusb_device_t *)usb_get_intfdata(intf);
439 printk(KERN_INFO "%s Entering status %d.\n", __func__, msg.event);
440 smsusb_stop_streaming(dev);
441 return 0;
442}
443
444static int smsusb_resume(struct usb_interface *intf)
445{
446 int rc, i;
447 struct smsusb_device_t *dev =
448 (struct smsusb_device_t *)usb_get_intfdata(intf);
449 struct usb_device *udev = interface_to_usbdev(intf);
450
451 printk(KERN_INFO "%s Entering.\n", __func__);
452 usb_clear_halt(udev, usb_rcvbulkpipe(udev, 0x81));
453 usb_clear_halt(udev, usb_rcvbulkpipe(udev, 0x02));
454
455 for (i = 0; i < intf->cur_altsetting->desc.bNumEndpoints; i++)
456 printk(KERN_INFO "endpoint %d %02x %02x %d\n", i,
457 intf->cur_altsetting->endpoint[i].desc.bEndpointAddress,
458 intf->cur_altsetting->endpoint[i].desc.bmAttributes,
459 intf->cur_altsetting->endpoint[i].desc.wMaxPacketSize);
460
461 if (intf->num_altsetting > 0) {
462 rc = usb_set_interface(udev,
463 intf->cur_altsetting->desc.
464 bInterfaceNumber, 0);
465 if (rc < 0) {
466 printk(KERN_INFO
467 "%s usb_set_interface failed, rc %d\n",
468 __func__, rc);
469 return rc;
470 }
471 }
472
473 smsusb_start_streaming(dev);
474 return 0;
475}
476
435static struct usb_driver smsusb_driver = { 477static struct usb_driver smsusb_driver = {
436 .name = "sms1xxx", 478 .name = "sms1xxx",
437 .probe = smsusb_probe, 479 .probe = smsusb_probe,
438 .disconnect = smsusb_disconnect, 480 .disconnect = smsusb_disconnect,
439 .id_table = smsusb_id_table, 481 .id_table = smsusb_id_table,
482
483 .suspend = smsusb_suspend,
484 .resume = smsusb_resume,
440}; 485};
441 486
442int smsusb_register(void) 487int smsusb_register(void)
diff --git a/drivers/media/dvb/ttpci/Kconfig b/drivers/media/dvb/ttpci/Kconfig
index 401a04effc06..ab0bcd208c78 100644
--- a/drivers/media/dvb/ttpci/Kconfig
+++ b/drivers/media/dvb/ttpci/Kconfig
@@ -104,6 +104,8 @@ config DVB_BUDGET_CI
104 select DVB_STV0297 if !DVB_FE_CUSTOMISE 104 select DVB_STV0297 if !DVB_FE_CUSTOMISE
105 select DVB_STV0299 if !DVB_FE_CUSTOMISE 105 select DVB_STV0299 if !DVB_FE_CUSTOMISE
106 select DVB_TDA1004X if !DVB_FE_CUSTOMISE 106 select DVB_TDA1004X if !DVB_FE_CUSTOMISE
107 select DVB_STB0899 if !DVB_FE_CUSTOMISE
108 select DVB_STB6100 if !DVB_FE_CUSTOMISE
107 select DVB_LNBP21 if !DVB_FE_CUSTOMISE 109 select DVB_LNBP21 if !DVB_FE_CUSTOMISE
108 select DVB_TDA10023 if !DVB_FE_CUSTOMISE 110 select DVB_TDA10023 if !DVB_FE_CUSTOMISE
109 select MEDIA_TUNER_TDA827X if !MEDIA_TUNER_CUSTOMIZE 111 select MEDIA_TUNER_TDA827X if !MEDIA_TUNER_CUSTOMIZE
@@ -131,6 +133,8 @@ config DVB_BUDGET_AV
131 select DVB_TDA1004X if !DVB_FE_CUSTOMISE 133 select DVB_TDA1004X if !DVB_FE_CUSTOMISE
132 select DVB_TDA10021 if !DVB_FE_CUSTOMISE 134 select DVB_TDA10021 if !DVB_FE_CUSTOMISE
133 select DVB_TDA10023 if !DVB_FE_CUSTOMISE 135 select DVB_TDA10023 if !DVB_FE_CUSTOMISE
136 select DVB_STB0899 if !DVB_FE_CUSTOMISE
137 select DVB_TDA8261 if !DVB_FE_CUSTOMISE
134 select DVB_TUA6100 if !DVB_FE_CUSTOMISE 138 select DVB_TUA6100 if !DVB_FE_CUSTOMISE
135 help 139 help
136 Support for simple SAA7146 based DVB cards 140 Support for simple SAA7146 based DVB cards
diff --git a/drivers/media/dvb/ttpci/budget-av.c b/drivers/media/dvb/ttpci/budget-av.c
index 1032ea77837e..f996cef79ec1 100644
--- a/drivers/media/dvb/ttpci/budget-av.c
+++ b/drivers/media/dvb/ttpci/budget-av.c
@@ -35,6 +35,11 @@
35 35
36#include "budget.h" 36#include "budget.h"
37#include "stv0299.h" 37#include "stv0299.h"
38#include "stb0899_drv.h"
39#include "stb0899_reg.h"
40#include "stb0899_cfg.h"
41#include "tda8261.h"
42#include "tda8261_cfg.h"
38#include "tda1002x.h" 43#include "tda1002x.h"
39#include "tda1004x.h" 44#include "tda1004x.h"
40#include "tua6100.h" 45#include "tua6100.h"
@@ -882,6 +887,281 @@ static struct stv0299_config philips_sd1878_config = {
882 .set_symbol_rate = philips_sd1878_ci_set_symbol_rate, 887 .set_symbol_rate = philips_sd1878_ci_set_symbol_rate,
883}; 888};
884 889
890/* KNC1 DVB-S (STB0899) Inittab */
891static const struct stb0899_s1_reg knc1_stb0899_s1_init_1[] = {
892
893 { STB0899_DEV_ID , 0x81 },
894 { STB0899_DISCNTRL1 , 0x32 },
895 { STB0899_DISCNTRL2 , 0x80 },
896 { STB0899_DISRX_ST0 , 0x04 },
897 { STB0899_DISRX_ST1 , 0x00 },
898 { STB0899_DISPARITY , 0x00 },
899 { STB0899_DISFIFO , 0x00 },
900 { STB0899_DISSTATUS , 0x20 },
901 { STB0899_DISF22 , 0x8c },
902 { STB0899_DISF22RX , 0x9a },
903 { STB0899_SYSREG , 0x0b },
904 { STB0899_ACRPRESC , 0x11 },
905 { STB0899_ACRDIV1 , 0x0a },
906 { STB0899_ACRDIV2 , 0x05 },
907 { STB0899_DACR1 , 0x00 },
908 { STB0899_DACR2 , 0x00 },
909 { STB0899_OUTCFG , 0x00 },
910 { STB0899_MODECFG , 0x00 },
911 { STB0899_IRQSTATUS_3 , 0x30 },
912 { STB0899_IRQSTATUS_2 , 0x00 },
913 { STB0899_IRQSTATUS_1 , 0x00 },
914 { STB0899_IRQSTATUS_0 , 0x00 },
915 { STB0899_IRQMSK_3 , 0xf3 },
916 { STB0899_IRQMSK_2 , 0xfc },
917 { STB0899_IRQMSK_1 , 0xff },
918 { STB0899_IRQMSK_0 , 0xff },
919 { STB0899_IRQCFG , 0x00 },
920 { STB0899_I2CCFG , 0x88 },
921 { STB0899_I2CRPT , 0x58 }, /* Repeater=8, Stop=disabled */
922 { STB0899_IOPVALUE5 , 0x00 },
923 { STB0899_IOPVALUE4 , 0x20 },
924 { STB0899_IOPVALUE3 , 0xc9 },
925 { STB0899_IOPVALUE2 , 0x90 },
926 { STB0899_IOPVALUE1 , 0x40 },
927 { STB0899_IOPVALUE0 , 0x00 },
928 { STB0899_GPIO00CFG , 0x82 },
929 { STB0899_GPIO01CFG , 0x82 },
930 { STB0899_GPIO02CFG , 0x82 },
931 { STB0899_GPIO03CFG , 0x82 },
932 { STB0899_GPIO04CFG , 0x82 },
933 { STB0899_GPIO05CFG , 0x82 },
934 { STB0899_GPIO06CFG , 0x82 },
935 { STB0899_GPIO07CFG , 0x82 },
936 { STB0899_GPIO08CFG , 0x82 },
937 { STB0899_GPIO09CFG , 0x82 },
938 { STB0899_GPIO10CFG , 0x82 },
939 { STB0899_GPIO11CFG , 0x82 },
940 { STB0899_GPIO12CFG , 0x82 },
941 { STB0899_GPIO13CFG , 0x82 },
942 { STB0899_GPIO14CFG , 0x82 },
943 { STB0899_GPIO15CFG , 0x82 },
944 { STB0899_GPIO16CFG , 0x82 },
945 { STB0899_GPIO17CFG , 0x82 },
946 { STB0899_GPIO18CFG , 0x82 },
947 { STB0899_GPIO19CFG , 0x82 },
948 { STB0899_GPIO20CFG , 0x82 },
949 { STB0899_SDATCFG , 0xb8 },
950 { STB0899_SCLTCFG , 0xba },
951 { STB0899_AGCRFCFG , 0x08 }, /* 0x1c */
952 { STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */
953 { STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */
954 { STB0899_DIRCLKCFG , 0x82 },
955 { STB0899_CLKOUT27CFG , 0x7e },
956 { STB0899_STDBYCFG , 0x82 },
957 { STB0899_CS0CFG , 0x82 },
958 { STB0899_CS1CFG , 0x82 },
959 { STB0899_DISEQCOCFG , 0x20 },
960 { STB0899_GPIO32CFG , 0x82 },
961 { STB0899_GPIO33CFG , 0x82 },
962 { STB0899_GPIO34CFG , 0x82 },
963 { STB0899_GPIO35CFG , 0x82 },
964 { STB0899_GPIO36CFG , 0x82 },
965 { STB0899_GPIO37CFG , 0x82 },
966 { STB0899_GPIO38CFG , 0x82 },
967 { STB0899_GPIO39CFG , 0x82 },
968 { STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
969 { STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
970 { STB0899_FILTCTRL , 0x00 },
971 { STB0899_SYSCTRL , 0x00 },
972 { STB0899_STOPCLK1 , 0x20 },
973 { STB0899_STOPCLK2 , 0x00 },
974 { STB0899_INTBUFSTATUS , 0x00 },
975 { STB0899_INTBUFCTRL , 0x0a },
976 { 0xffff , 0xff },
977};
978
979static const struct stb0899_s1_reg knc1_stb0899_s1_init_3[] = {
980 { STB0899_DEMOD , 0x00 },
981 { STB0899_RCOMPC , 0xc9 },
982 { STB0899_AGC1CN , 0x41 },
983 { STB0899_AGC1REF , 0x08 },
984 { STB0899_RTC , 0x7a },
985 { STB0899_TMGCFG , 0x4e },
986 { STB0899_AGC2REF , 0x33 },
987 { STB0899_TLSR , 0x84 },
988 { STB0899_CFD , 0xee },
989 { STB0899_ACLC , 0x87 },
990 { STB0899_BCLC , 0x94 },
991 { STB0899_EQON , 0x41 },
992 { STB0899_LDT , 0xdd },
993 { STB0899_LDT2 , 0xc9 },
994 { STB0899_EQUALREF , 0xb4 },
995 { STB0899_TMGRAMP , 0x10 },
996 { STB0899_TMGTHD , 0x30 },
997 { STB0899_IDCCOMP , 0xfb },
998 { STB0899_QDCCOMP , 0x03 },
999 { STB0899_POWERI , 0x3b },
1000 { STB0899_POWERQ , 0x3d },
1001 { STB0899_RCOMP , 0x81 },
1002 { STB0899_AGCIQIN , 0x80 },
1003 { STB0899_AGC2I1 , 0x04 },
1004 { STB0899_AGC2I2 , 0xf5 },
1005 { STB0899_TLIR , 0x25 },
1006 { STB0899_RTF , 0x80 },
1007 { STB0899_DSTATUS , 0x00 },
1008 { STB0899_LDI , 0xca },
1009 { STB0899_CFRM , 0xf1 },
1010 { STB0899_CFRL , 0xf3 },
1011 { STB0899_NIRM , 0x2a },
1012 { STB0899_NIRL , 0x05 },
1013 { STB0899_ISYMB , 0x17 },
1014 { STB0899_QSYMB , 0xfa },
1015 { STB0899_SFRH , 0x2f },
1016 { STB0899_SFRM , 0x68 },
1017 { STB0899_SFRL , 0x40 },
1018 { STB0899_SFRUPH , 0x2f },
1019 { STB0899_SFRUPM , 0x68 },
1020 { STB0899_SFRUPL , 0x40 },
1021 { STB0899_EQUAI1 , 0xfd },
1022 { STB0899_EQUAQ1 , 0x04 },
1023 { STB0899_EQUAI2 , 0x0f },
1024 { STB0899_EQUAQ2 , 0xff },
1025 { STB0899_EQUAI3 , 0xdf },
1026 { STB0899_EQUAQ3 , 0xfa },
1027 { STB0899_EQUAI4 , 0x37 },
1028 { STB0899_EQUAQ4 , 0x0d },
1029 { STB0899_EQUAI5 , 0xbd },
1030 { STB0899_EQUAQ5 , 0xf7 },
1031 { STB0899_DSTATUS2 , 0x00 },
1032 { STB0899_VSTATUS , 0x00 },
1033 { STB0899_VERROR , 0xff },
1034 { STB0899_IQSWAP , 0x2a },
1035 { STB0899_ECNT1M , 0x00 },
1036 { STB0899_ECNT1L , 0x00 },
1037 { STB0899_ECNT2M , 0x00 },
1038 { STB0899_ECNT2L , 0x00 },
1039 { STB0899_ECNT3M , 0x00 },
1040 { STB0899_ECNT3L , 0x00 },
1041 { STB0899_FECAUTO1 , 0x06 },
1042 { STB0899_FECM , 0x01 },
1043 { STB0899_VTH12 , 0xf0 },
1044 { STB0899_VTH23 , 0xa0 },
1045 { STB0899_VTH34 , 0x78 },
1046 { STB0899_VTH56 , 0x4e },
1047 { STB0899_VTH67 , 0x48 },
1048 { STB0899_VTH78 , 0x38 },
1049 { STB0899_PRVIT , 0xff },
1050 { STB0899_VITSYNC , 0x19 },
1051 { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
1052 { STB0899_TSULC , 0x42 },
1053 { STB0899_RSLLC , 0x40 },
1054 { STB0899_TSLPL , 0x12 },
1055 { STB0899_TSCFGH , 0x0c },
1056 { STB0899_TSCFGM , 0x00 },
1057 { STB0899_TSCFGL , 0x0c },
1058 { STB0899_TSOUT , 0x0d }, /* 0x0d for CAM */
1059 { STB0899_RSSYNCDEL , 0x00 },
1060 { STB0899_TSINHDELH , 0x02 },
1061 { STB0899_TSINHDELM , 0x00 },
1062 { STB0899_TSINHDELL , 0x00 },
1063 { STB0899_TSLLSTKM , 0x00 },
1064 { STB0899_TSLLSTKL , 0x00 },
1065 { STB0899_TSULSTKM , 0x00 },
1066 { STB0899_TSULSTKL , 0xab },
1067 { STB0899_PCKLENUL , 0x00 },
1068 { STB0899_PCKLENLL , 0xcc },
1069 { STB0899_RSPCKLEN , 0xcc },
1070 { STB0899_TSSTATUS , 0x80 },
1071 { STB0899_ERRCTRL1 , 0xb6 },
1072 { STB0899_ERRCTRL2 , 0x96 },
1073 { STB0899_ERRCTRL3 , 0x89 },
1074 { STB0899_DMONMSK1 , 0x27 },
1075 { STB0899_DMONMSK0 , 0x03 },
1076 { STB0899_DEMAPVIT , 0x5c },
1077 { STB0899_PLPARM , 0x1f },
1078 { STB0899_PDELCTRL , 0x48 },
1079 { STB0899_PDELCTRL2 , 0x00 },
1080 { STB0899_BBHCTRL1 , 0x00 },
1081 { STB0899_BBHCTRL2 , 0x00 },
1082 { STB0899_HYSTTHRESH , 0x77 },
1083 { STB0899_MATCSTM , 0x00 },
1084 { STB0899_MATCSTL , 0x00 },
1085 { STB0899_UPLCSTM , 0x00 },
1086 { STB0899_UPLCSTL , 0x00 },
1087 { STB0899_DFLCSTM , 0x00 },
1088 { STB0899_DFLCSTL , 0x00 },
1089 { STB0899_SYNCCST , 0x00 },
1090 { STB0899_SYNCDCSTM , 0x00 },
1091 { STB0899_SYNCDCSTL , 0x00 },
1092 { STB0899_ISI_ENTRY , 0x00 },
1093 { STB0899_ISI_BIT_EN , 0x00 },
1094 { STB0899_MATSTRM , 0x00 },
1095 { STB0899_MATSTRL , 0x00 },
1096 { STB0899_UPLSTRM , 0x00 },
1097 { STB0899_UPLSTRL , 0x00 },
1098 { STB0899_DFLSTRM , 0x00 },
1099 { STB0899_DFLSTRL , 0x00 },
1100 { STB0899_SYNCSTR , 0x00 },
1101 { STB0899_SYNCDSTRM , 0x00 },
1102 { STB0899_SYNCDSTRL , 0x00 },
1103 { STB0899_CFGPDELSTATUS1 , 0x10 },
1104 { STB0899_CFGPDELSTATUS2 , 0x00 },
1105 { STB0899_BBFERRORM , 0x00 },
1106 { STB0899_BBFERRORL , 0x00 },
1107 { STB0899_UPKTERRORM , 0x00 },
1108 { STB0899_UPKTERRORL , 0x00 },
1109 { 0xffff , 0xff },
1110};
1111
1112/* STB0899 demodulator config for the KNC1 and clones */
1113static struct stb0899_config knc1_dvbs2_config = {
1114 .init_dev = knc1_stb0899_s1_init_1,
1115 .init_s2_demod = stb0899_s2_init_2,
1116 .init_s1_demod = knc1_stb0899_s1_init_3,
1117 .init_s2_fec = stb0899_s2_init_4,
1118 .init_tst = stb0899_s1_init_5,
1119
1120 .postproc = NULL,
1121
1122 .demod_address = 0x68,
1123// .ts_output_mode = STB0899_OUT_PARALLEL, /* types = SERIAL/PARALLEL */
1124 .block_sync_mode = STB0899_SYNC_FORCED, /* DSS, SYNC_FORCED/UNSYNCED */
1125// .ts_pfbit_toggle = STB0899_MPEG_NORMAL, /* DirecTV, MPEG toggling seq */
1126
1127 .xtal_freq = 27000000,
1128 .inversion = IQ_SWAP_OFF, /* 1 */
1129
1130 .lo_clk = 76500000,
1131 .hi_clk = 90000000,
1132
1133 .esno_ave = STB0899_DVBS2_ESNO_AVE,
1134 .esno_quant = STB0899_DVBS2_ESNO_QUANT,
1135 .avframes_coarse = STB0899_DVBS2_AVFRAMES_COARSE,
1136 .avframes_fine = STB0899_DVBS2_AVFRAMES_FINE,
1137 .miss_threshold = STB0899_DVBS2_MISS_THRESHOLD,
1138 .uwp_threshold_acq = STB0899_DVBS2_UWP_THRESHOLD_ACQ,
1139 .uwp_threshold_track = STB0899_DVBS2_UWP_THRESHOLD_TRACK,
1140 .uwp_threshold_sof = STB0899_DVBS2_UWP_THRESHOLD_SOF,
1141 .sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT,
1142
1143 .btr_nco_bits = STB0899_DVBS2_BTR_NCO_BITS,
1144 .btr_gain_shift_offset = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET,
1145 .crl_nco_bits = STB0899_DVBS2_CRL_NCO_BITS,
1146 .ldpc_max_iter = STB0899_DVBS2_LDPC_MAX_ITER,
1147
1148 .tuner_get_frequency = tda8261_get_frequency,
1149 .tuner_set_frequency = tda8261_set_frequency,
1150 .tuner_set_bandwidth = NULL,
1151 .tuner_get_bandwidth = tda8261_get_bandwidth,
1152 .tuner_set_rfsiggain = NULL
1153};
1154
1155/*
1156 * SD1878/SHA tuner config
1157 * 1F, Single I/P, Horizontal mount, High Sensitivity
1158 */
1159static const struct tda8261_config sd1878c_config = {
1160// .name = "SD1878/SHA",
1161 .addr = 0x60,
1162 .step_size = TDA8261_STEP_1000 /* kHz */
1163};
1164
885static u8 read_pwm(struct budget_av *budget_av) 1165static u8 read_pwm(struct budget_av *budget_av)
886{ 1166{
887 u8 b = 0xff; 1167 u8 b = 0xff;
@@ -905,8 +1185,11 @@ static u8 read_pwm(struct budget_av *budget_av)
905#define SUBID_DVBS_TV_STAR 0x0014 1185#define SUBID_DVBS_TV_STAR 0x0014
906#define SUBID_DVBS_TV_STAR_PLUS_X4 0x0015 1186#define SUBID_DVBS_TV_STAR_PLUS_X4 0x0015
907#define SUBID_DVBS_TV_STAR_CI 0x0016 1187#define SUBID_DVBS_TV_STAR_CI 0x0016
1188#define SUBID_DVBS2_KNC1 0x0018
1189#define SUBID_DVBS2_KNC1_OEM 0x0019
908#define SUBID_DVBS_EASYWATCH_1 0x001a 1190#define SUBID_DVBS_EASYWATCH_1 0x001a
909#define SUBID_DVBS_EASYWATCH_2 0x001b 1191#define SUBID_DVBS_EASYWATCH_2 0x001b
1192#define SUBID_DVBS2_EASYWATCH 0x001d
910#define SUBID_DVBS_EASYWATCH 0x001e 1193#define SUBID_DVBS_EASYWATCH 0x001e
911 1194
912#define SUBID_DVBC_EASYWATCH 0x002a 1195#define SUBID_DVBC_EASYWATCH 0x002a
@@ -941,6 +1224,9 @@ static void frontend_init(struct budget_av *budget_av)
941 case SUBID_DVBT_KNC1_PLUS: 1224 case SUBID_DVBT_KNC1_PLUS:
942 case SUBID_DVBC_EASYWATCH: 1225 case SUBID_DVBC_EASYWATCH:
943 case SUBID_DVBC_KNC1_PLUS_MK3: 1226 case SUBID_DVBC_KNC1_PLUS_MK3:
1227 case SUBID_DVBS2_KNC1:
1228 case SUBID_DVBS2_KNC1_OEM:
1229 case SUBID_DVBS2_EASYWATCH:
944 saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTHI); 1230 saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTHI);
945 break; 1231 break;
946 } 1232 }
@@ -993,7 +1279,14 @@ static void frontend_init(struct budget_av *budget_av)
993 fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params; 1279 fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params;
994 } 1280 }
995 break; 1281 break;
1282 case SUBID_DVBS2_KNC1:
1283 case SUBID_DVBS2_KNC1_OEM:
1284 case SUBID_DVBS2_EASYWATCH:
1285 budget_av->reinitialise_demod = 1;
1286 if ((fe = dvb_attach(stb0899_attach, &knc1_dvbs2_config, &budget_av->budget.i2c_adap)))
1287 dvb_attach(tda8261_attach, fe, &sd1878c_config, &budget_av->budget.i2c_adap);
996 1288
1289 break;
997 case SUBID_DVBS_CINERGY1200: 1290 case SUBID_DVBS_CINERGY1200:
998 fe = dvb_attach(stv0299_attach, &cinergy_1200s_config, 1291 fe = dvb_attach(stv0299_attach, &cinergy_1200s_config,
999 &budget_av->budget.i2c_adap); 1292 &budget_av->budget.i2c_adap);
@@ -1260,6 +1553,8 @@ static struct saa7146_ext_vv vv_data = {
1260static struct saa7146_extension budget_extension; 1553static struct saa7146_extension budget_extension;
1261 1554
1262MAKE_BUDGET_INFO(knc1s, "KNC1 DVB-S", BUDGET_KNC1S); 1555MAKE_BUDGET_INFO(knc1s, "KNC1 DVB-S", BUDGET_KNC1S);
1556MAKE_BUDGET_INFO(knc1s2,"KNC1 DVB-S2", BUDGET_KNC1S2);
1557MAKE_BUDGET_INFO(sates2,"Satelco EasyWatch DVB-S2", BUDGET_KNC1S2);
1263MAKE_BUDGET_INFO(knc1c, "KNC1 DVB-C", BUDGET_KNC1C); 1558MAKE_BUDGET_INFO(knc1c, "KNC1 DVB-C", BUDGET_KNC1C);
1264MAKE_BUDGET_INFO(knc1t, "KNC1 DVB-T", BUDGET_KNC1T); 1559MAKE_BUDGET_INFO(knc1t, "KNC1 DVB-T", BUDGET_KNC1T);
1265MAKE_BUDGET_INFO(kncxs, "KNC TV STAR DVB-S", BUDGET_TVSTAR); 1560MAKE_BUDGET_INFO(kncxs, "KNC TV STAR DVB-S", BUDGET_TVSTAR);
@@ -1290,6 +1585,9 @@ static struct pci_device_id pci_tbl[] = {
1290 MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0014), 1585 MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0014),
1291 MAKE_EXTENSION_PCI(knc1spx4, 0x1894, 0x0015), 1586 MAKE_EXTENSION_PCI(knc1spx4, 0x1894, 0x0015),
1292 MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0016), 1587 MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0016),
1588 MAKE_EXTENSION_PCI(knc1s2, 0x1894, 0x0018),
1589 MAKE_EXTENSION_PCI(knc1s2, 0x1894, 0x0019),
1590 MAKE_EXTENSION_PCI(sates2, 0x1894, 0x001d),
1293 MAKE_EXTENSION_PCI(satewpls, 0x1894, 0x001e), 1591 MAKE_EXTENSION_PCI(satewpls, 0x1894, 0x001e),
1294 MAKE_EXTENSION_PCI(satewpls1, 0x1894, 0x001a), 1592 MAKE_EXTENSION_PCI(satewpls1, 0x1894, 0x001a),
1295 MAKE_EXTENSION_PCI(satewps, 0x1894, 0x001b), 1593 MAKE_EXTENSION_PCI(satewps, 0x1894, 0x001b),
diff --git a/drivers/media/dvb/ttpci/budget-ci.c b/drivers/media/dvb/ttpci/budget-ci.c
index 0a5aad45435d..3507463fdac9 100644
--- a/drivers/media/dvb/ttpci/budget-ci.c
+++ b/drivers/media/dvb/ttpci/budget-ci.c
@@ -43,6 +43,11 @@
43#include "stv0299.h" 43#include "stv0299.h"
44#include "stv0297.h" 44#include "stv0297.h"
45#include "tda1004x.h" 45#include "tda1004x.h"
46#include "stb0899_drv.h"
47#include "stb0899_reg.h"
48#include "stb0899_cfg.h"
49#include "stb6100.h"
50#include "stb6100_cfg.h"
46#include "lnbp21.h" 51#include "lnbp21.h"
47#include "bsbe1.h" 52#include "bsbe1.h"
48#include "bsru6.h" 53#include "bsru6.h"
@@ -1071,7 +1076,271 @@ static struct tda10023_config tda10023_config = {
1071 .deltaf = 0xa511, 1076 .deltaf = 0xa511,
1072}; 1077};
1073 1078
1079/* TT S2-3200 DVB-S (STB0899) Inittab */
1080static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
1081
1082 { STB0899_DEV_ID , 0x81 },
1083 { STB0899_DISCNTRL1 , 0x32 },
1084 { STB0899_DISCNTRL2 , 0x80 },
1085 { STB0899_DISRX_ST0 , 0x04 },
1086 { STB0899_DISRX_ST1 , 0x00 },
1087 { STB0899_DISPARITY , 0x00 },
1088 { STB0899_DISFIFO , 0x00 },
1089 { STB0899_DISSTATUS , 0x20 },
1090 { STB0899_DISF22 , 0x8c },
1091 { STB0899_DISF22RX , 0x9a },
1092 { STB0899_SYSREG , 0x0b },
1093 { STB0899_ACRPRESC , 0x11 },
1094 { STB0899_ACRDIV1 , 0x0a },
1095 { STB0899_ACRDIV2 , 0x05 },
1096 { STB0899_DACR1 , 0x00 },
1097 { STB0899_DACR2 , 0x00 },
1098 { STB0899_OUTCFG , 0x00 },
1099 { STB0899_MODECFG , 0x00 },
1100 { STB0899_IRQSTATUS_3 , 0x30 },
1101 { STB0899_IRQSTATUS_2 , 0x00 },
1102 { STB0899_IRQSTATUS_1 , 0x00 },
1103 { STB0899_IRQSTATUS_0 , 0x00 },
1104 { STB0899_IRQMSK_3 , 0xf3 },
1105 { STB0899_IRQMSK_2 , 0xfc },
1106 { STB0899_IRQMSK_1 , 0xff },
1107 { STB0899_IRQMSK_0 , 0xff },
1108 { STB0899_IRQCFG , 0x00 },
1109 { STB0899_I2CCFG , 0x88 },
1110 { STB0899_I2CRPT , 0x48 }, /* 12k Pullup, Repeater=16, Stop=disabled */
1111 { STB0899_IOPVALUE5 , 0x00 },
1112 { STB0899_IOPVALUE4 , 0x20 },
1113 { STB0899_IOPVALUE3 , 0xc9 },
1114 { STB0899_IOPVALUE2 , 0x90 },
1115 { STB0899_IOPVALUE1 , 0x40 },
1116 { STB0899_IOPVALUE0 , 0x00 },
1117 { STB0899_GPIO00CFG , 0x82 },
1118 { STB0899_GPIO01CFG , 0x82 },
1119 { STB0899_GPIO02CFG , 0x82 },
1120 { STB0899_GPIO03CFG , 0x82 },
1121 { STB0899_GPIO04CFG , 0x82 },
1122 { STB0899_GPIO05CFG , 0x82 },
1123 { STB0899_GPIO06CFG , 0x82 },
1124 { STB0899_GPIO07CFG , 0x82 },
1125 { STB0899_GPIO08CFG , 0x82 },
1126 { STB0899_GPIO09CFG , 0x82 },
1127 { STB0899_GPIO10CFG , 0x82 },
1128 { STB0899_GPIO11CFG , 0x82 },
1129 { STB0899_GPIO12CFG , 0x82 },
1130 { STB0899_GPIO13CFG , 0x82 },
1131 { STB0899_GPIO14CFG , 0x82 },
1132 { STB0899_GPIO15CFG , 0x82 },
1133 { STB0899_GPIO16CFG , 0x82 },
1134 { STB0899_GPIO17CFG , 0x82 },
1135 { STB0899_GPIO18CFG , 0x82 },
1136 { STB0899_GPIO19CFG , 0x82 },
1137 { STB0899_GPIO20CFG , 0x82 },
1138 { STB0899_SDATCFG , 0xb8 },
1139 { STB0899_SCLTCFG , 0xba },
1140 { STB0899_AGCRFCFG , 0x1c }, /* 0x11 */
1141 { STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */
1142 { STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */
1143 { STB0899_DIRCLKCFG , 0x82 },
1144 { STB0899_CLKOUT27CFG , 0x7e },
1145 { STB0899_STDBYCFG , 0x82 },
1146 { STB0899_CS0CFG , 0x82 },
1147 { STB0899_CS1CFG , 0x82 },
1148 { STB0899_DISEQCOCFG , 0x20 },
1149 { STB0899_GPIO32CFG , 0x82 },
1150 { STB0899_GPIO33CFG , 0x82 },
1151 { STB0899_GPIO34CFG , 0x82 },
1152 { STB0899_GPIO35CFG , 0x82 },
1153 { STB0899_GPIO36CFG , 0x82 },
1154 { STB0899_GPIO37CFG , 0x82 },
1155 { STB0899_GPIO38CFG , 0x82 },
1156 { STB0899_GPIO39CFG , 0x82 },
1157 { STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
1158 { STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
1159 { STB0899_FILTCTRL , 0x00 },
1160 { STB0899_SYSCTRL , 0x00 },
1161 { STB0899_STOPCLK1 , 0x20 },
1162 { STB0899_STOPCLK2 , 0x00 },
1163 { STB0899_INTBUFSTATUS , 0x00 },
1164 { STB0899_INTBUFCTRL , 0x0a },
1165 { 0xffff , 0xff },
1166};
1167
1168static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = {
1169 { STB0899_DEMOD , 0x00 },
1170 { STB0899_RCOMPC , 0xc9 },
1171 { STB0899_AGC1CN , 0x41 },
1172 { STB0899_AGC1REF , 0x10 },
1173 { STB0899_RTC , 0x7a },
1174 { STB0899_TMGCFG , 0x4e },
1175 { STB0899_AGC2REF , 0x34 },
1176 { STB0899_TLSR , 0x84 },
1177 { STB0899_CFD , 0xc7 },
1178 { STB0899_ACLC , 0x87 },
1179 { STB0899_BCLC , 0x94 },
1180 { STB0899_EQON , 0x41 },
1181 { STB0899_LDT , 0xdd },
1182 { STB0899_LDT2 , 0xc9 },
1183 { STB0899_EQUALREF , 0xb4 },
1184 { STB0899_TMGRAMP , 0x10 },
1185 { STB0899_TMGTHD , 0x30 },
1186 { STB0899_IDCCOMP , 0xfb },
1187 { STB0899_QDCCOMP , 0x03 },
1188 { STB0899_POWERI , 0x3b },
1189 { STB0899_POWERQ , 0x3d },
1190 { STB0899_RCOMP , 0x81 },
1191 { STB0899_AGCIQIN , 0x80 },
1192 { STB0899_AGC2I1 , 0x04 },
1193 { STB0899_AGC2I2 , 0xf5 },
1194 { STB0899_TLIR , 0x25 },
1195 { STB0899_RTF , 0x80 },
1196 { STB0899_DSTATUS , 0x00 },
1197 { STB0899_LDI , 0xca },
1198 { STB0899_CFRM , 0xf1 },
1199 { STB0899_CFRL , 0xf3 },
1200 { STB0899_NIRM , 0x2a },
1201 { STB0899_NIRL , 0x05 },
1202 { STB0899_ISYMB , 0x17 },
1203 { STB0899_QSYMB , 0xfa },
1204 { STB0899_SFRH , 0x2f },
1205 { STB0899_SFRM , 0x68 },
1206 { STB0899_SFRL , 0x40 },
1207 { STB0899_SFRUPH , 0x2f },
1208 { STB0899_SFRUPM , 0x68 },
1209 { STB0899_SFRUPL , 0x40 },
1210 { STB0899_EQUAI1 , 0xfd },
1211 { STB0899_EQUAQ1 , 0x04 },
1212 { STB0899_EQUAI2 , 0x0f },
1213 { STB0899_EQUAQ2 , 0xff },
1214 { STB0899_EQUAI3 , 0xdf },
1215 { STB0899_EQUAQ3 , 0xfa },
1216 { STB0899_EQUAI4 , 0x37 },
1217 { STB0899_EQUAQ4 , 0x0d },
1218 { STB0899_EQUAI5 , 0xbd },
1219 { STB0899_EQUAQ5 , 0xf7 },
1220 { STB0899_DSTATUS2 , 0x00 },
1221 { STB0899_VSTATUS , 0x00 },
1222 { STB0899_VERROR , 0xff },
1223 { STB0899_IQSWAP , 0x2a },
1224 { STB0899_ECNT1M , 0x00 },
1225 { STB0899_ECNT1L , 0x00 },
1226 { STB0899_ECNT2M , 0x00 },
1227 { STB0899_ECNT2L , 0x00 },
1228 { STB0899_ECNT3M , 0x00 },
1229 { STB0899_ECNT3L , 0x00 },
1230 { STB0899_FECAUTO1 , 0x06 },
1231 { STB0899_FECM , 0x01 },
1232 { STB0899_VTH12 , 0xf0 },
1233 { STB0899_VTH23 , 0xa0 },
1234 { STB0899_VTH34 , 0x78 },
1235 { STB0899_VTH56 , 0x4e },
1236 { STB0899_VTH67 , 0x48 },
1237 { STB0899_VTH78 , 0x38 },
1238 { STB0899_PRVIT , 0xff },
1239 { STB0899_VITSYNC , 0x19 },
1240 { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
1241 { STB0899_TSULC , 0x42 },
1242 { STB0899_RSLLC , 0x40 },
1243 { STB0899_TSLPL , 0x12 },
1244 { STB0899_TSCFGH , 0x0c },
1245 { STB0899_TSCFGM , 0x00 },
1246 { STB0899_TSCFGL , 0x0c },
1247 { STB0899_TSOUT , 0x0d }, /* 0x0d for CAM */
1248 { STB0899_RSSYNCDEL , 0x00 },
1249 { STB0899_TSINHDELH , 0x02 },
1250 { STB0899_TSINHDELM , 0x00 },
1251 { STB0899_TSINHDELL , 0x00 },
1252 { STB0899_TSLLSTKM , 0x00 },
1253 { STB0899_TSLLSTKL , 0x00 },
1254 { STB0899_TSULSTKM , 0x00 },
1255 { STB0899_TSULSTKL , 0xab },
1256 { STB0899_PCKLENUL , 0x00 },
1257 { STB0899_PCKLENLL , 0xcc },
1258 { STB0899_RSPCKLEN , 0xcc },
1259 { STB0899_TSSTATUS , 0x80 },
1260 { STB0899_ERRCTRL1 , 0xb6 },
1261 { STB0899_ERRCTRL2 , 0x96 },
1262 { STB0899_ERRCTRL3 , 0x89 },
1263 { STB0899_DMONMSK1 , 0x27 },
1264 { STB0899_DMONMSK0 , 0x03 },
1265 { STB0899_DEMAPVIT , 0x5c },
1266 { STB0899_PLPARM , 0x1f },
1267 { STB0899_PDELCTRL , 0x48 },
1268 { STB0899_PDELCTRL2 , 0x00 },
1269 { STB0899_BBHCTRL1 , 0x00 },
1270 { STB0899_BBHCTRL2 , 0x00 },
1271 { STB0899_HYSTTHRESH , 0x77 },
1272 { STB0899_MATCSTM , 0x00 },
1273 { STB0899_MATCSTL , 0x00 },
1274 { STB0899_UPLCSTM , 0x00 },
1275 { STB0899_UPLCSTL , 0x00 },
1276 { STB0899_DFLCSTM , 0x00 },
1277 { STB0899_DFLCSTL , 0x00 },
1278 { STB0899_SYNCCST , 0x00 },
1279 { STB0899_SYNCDCSTM , 0x00 },
1280 { STB0899_SYNCDCSTL , 0x00 },
1281 { STB0899_ISI_ENTRY , 0x00 },
1282 { STB0899_ISI_BIT_EN , 0x00 },
1283 { STB0899_MATSTRM , 0x00 },
1284 { STB0899_MATSTRL , 0x00 },
1285 { STB0899_UPLSTRM , 0x00 },
1286 { STB0899_UPLSTRL , 0x00 },
1287 { STB0899_DFLSTRM , 0x00 },
1288 { STB0899_DFLSTRL , 0x00 },
1289 { STB0899_SYNCSTR , 0x00 },
1290 { STB0899_SYNCDSTRM , 0x00 },
1291 { STB0899_SYNCDSTRL , 0x00 },
1292 { STB0899_CFGPDELSTATUS1 , 0x10 },
1293 { STB0899_CFGPDELSTATUS2 , 0x00 },
1294 { STB0899_BBFERRORM , 0x00 },
1295 { STB0899_BBFERRORL , 0x00 },
1296 { STB0899_UPKTERRORM , 0x00 },
1297 { STB0899_UPKTERRORL , 0x00 },
1298 { 0xffff , 0xff },
1299};
1074 1300
1301static struct stb0899_config tt3200_config = {
1302 .init_dev = tt3200_stb0899_s1_init_1,
1303 .init_s2_demod = stb0899_s2_init_2,
1304 .init_s1_demod = tt3200_stb0899_s1_init_3,
1305 .init_s2_fec = stb0899_s2_init_4,
1306 .init_tst = stb0899_s1_init_5,
1307
1308 .postproc = NULL,
1309
1310 .demod_address = 0x68,
1311
1312 .xtal_freq = 27000000,
1313 .inversion = IQ_SWAP_ON, /* 1 */
1314
1315 .lo_clk = 76500000,
1316 .hi_clk = 99000000,
1317
1318 .esno_ave = STB0899_DVBS2_ESNO_AVE,
1319 .esno_quant = STB0899_DVBS2_ESNO_QUANT,
1320 .avframes_coarse = STB0899_DVBS2_AVFRAMES_COARSE,
1321 .avframes_fine = STB0899_DVBS2_AVFRAMES_FINE,
1322 .miss_threshold = STB0899_DVBS2_MISS_THRESHOLD,
1323 .uwp_threshold_acq = STB0899_DVBS2_UWP_THRESHOLD_ACQ,
1324 .uwp_threshold_track = STB0899_DVBS2_UWP_THRESHOLD_TRACK,
1325 .uwp_threshold_sof = STB0899_DVBS2_UWP_THRESHOLD_SOF,
1326 .sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT,
1327
1328 .btr_nco_bits = STB0899_DVBS2_BTR_NCO_BITS,
1329 .btr_gain_shift_offset = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET,
1330 .crl_nco_bits = STB0899_DVBS2_CRL_NCO_BITS,
1331 .ldpc_max_iter = STB0899_DVBS2_LDPC_MAX_ITER,
1332
1333 .tuner_get_frequency = stb6100_get_frequency,
1334 .tuner_set_frequency = stb6100_set_frequency,
1335 .tuner_set_bandwidth = stb6100_set_bandwidth,
1336 .tuner_get_bandwidth = stb6100_get_bandwidth,
1337 .tuner_set_rfsiggain = NULL
1338};
1339
1340struct stb6100_config tt3200_stb6100_config = {
1341 .tuner_address = 0x60,
1342 .refclock = 27000000,
1343};
1075 1344
1076static void frontend_init(struct budget_ci *budget_ci) 1345static void frontend_init(struct budget_ci *budget_ci)
1077{ 1346{
@@ -1152,6 +1421,46 @@ static void frontend_init(struct budget_ci *budget_ci)
1152 } 1421 }
1153 } 1422 }
1154 break; 1423 break;
1424
1425 case 0x1019: // TT S2-3200 PCI
1426 /*
1427 * NOTE! on some STB0899 versions, the internal PLL takes a longer time
1428 * to settle, aka LOCK. On the older revisions of the chip, we don't see
1429 * this, as a result on the newer chips the entire clock tree, will not
1430 * be stable after a freshly POWER 'ed up situation.
1431 * In this case, we should RESET the STB0899 (Active LOW) and wait for
1432 * PLL stabilization.
1433 *
1434 * On the TT S2 3200 and clones, the STB0899 demodulator's RESETB is
1435 * connected to the SAA7146 GPIO, GPIO2, Pin 142
1436 */
1437 /* Reset Demodulator */
1438 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO);
1439 /* Wait for everything to die */
1440 msleep(50);
1441 /* Pull it up out of Reset state */
1442 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI);
1443 /* Wait for PLL to stabilize */
1444 msleep(250);
1445 /*
1446 * PLL state should be stable now. Ideally, we should check
1447 * for PLL LOCK status. But well, never mind!
1448 */
1449 budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap);
1450 if (budget_ci->budget.dvb_frontend) {
1451 if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) {
1452 if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) {
1453 printk("%s: No LNBP21 found!\n", __FUNCTION__);
1454 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1455 budget_ci->budget.dvb_frontend = NULL;
1456 }
1457 } else {
1458 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1459 budget_ci->budget.dvb_frontend = NULL;
1460 }
1461 }
1462 break;
1463
1155 } 1464 }
1156 1465
1157 if (budget_ci->budget.dvb_frontend == NULL) { 1466 if (budget_ci->budget.dvb_frontend == NULL) {
@@ -1242,6 +1551,7 @@ MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T PCI", BUDGET_TT);
1242MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT); 1551MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT);
1243MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT); 1552MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
1244MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT); 1553MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT);
1554MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT);
1245 1555
1246static struct pci_device_id pci_tbl[] = { 1556static struct pci_device_id pci_tbl[] = {
1247 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c), 1557 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
@@ -1251,6 +1561,7 @@ static struct pci_device_id pci_tbl[] = {
1251 MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012), 1561 MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012),
1252 MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017), 1562 MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
1253 MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a), 1563 MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a),
1564 MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
1254 { 1565 {
1255 .vendor = 0, 1566 .vendor = 0,
1256 } 1567 }
diff --git a/drivers/media/dvb/ttpci/budget.h b/drivers/media/dvb/ttpci/budget.h
index 86435bf16260..3ad0c6789ba7 100644
--- a/drivers/media/dvb/ttpci/budget.h
+++ b/drivers/media/dvb/ttpci/budget.h
@@ -103,6 +103,7 @@ static struct saa7146_pci_extension_data x_var = { \
103#define BUDGET_CIN1200C_MK3 15 103#define BUDGET_CIN1200C_MK3 15
104#define BUDGET_KNC1C_MK3 16 104#define BUDGET_KNC1C_MK3 16
105#define BUDGET_KNC1CP_MK3 17 105#define BUDGET_KNC1CP_MK3 17
106#define BUDGET_KNC1S2 18
106 107
107#define BUDGET_VIDEO_PORTA 0 108#define BUDGET_VIDEO_PORTA 0
108#define BUDGET_VIDEO_PORTB 1 109#define BUDGET_VIDEO_PORTB 1
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 10:46:10 -0500