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-rw-r--r--drivers/media/dvb/bt8xx/Kconfig2
-rw-r--r--drivers/media/dvb/dvb-usb/Kconfig10
-rw-r--r--drivers/media/dvb/dvb-usb/Makefile3
-rw-r--r--drivers/media/dvb/dvb-usb/anysee.c2
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb-ids.h1
-rw-r--r--drivers/media/dvb/dvb-usb/dw2102.c425
-rw-r--r--drivers/media/dvb/dvb-usb/dw2102.h9
-rw-r--r--drivers/media/dvb/frontends/Kconfig38
-rw-r--r--drivers/media/dvb/frontends/Makefile1
-rw-r--r--drivers/media/dvb/frontends/drx397xD.c1504
-rw-r--r--drivers/media/dvb/frontends/drx397xD.h130
-rw-r--r--drivers/media/dvb/frontends/drx397xD_fw.h40
-rw-r--r--drivers/media/dvb/frontends/z0194a.h97
-rw-r--r--drivers/media/dvb/siano/smscoreapi.c14
-rw-r--r--drivers/media/dvb/siano/smsdvb.c4
-rw-r--r--drivers/media/dvb/ttpci/Kconfig4
-rw-r--r--drivers/media/dvb/ttusb-dec/Kconfig2
17 files changed, 2250 insertions, 36 deletions
diff --git a/drivers/media/dvb/bt8xx/Kconfig b/drivers/media/dvb/bt8xx/Kconfig
index 7588db1319d0..7e9c090fc04e 100644
--- a/drivers/media/dvb/bt8xx/Kconfig
+++ b/drivers/media/dvb/bt8xx/Kconfig
@@ -1,7 +1,6 @@
1config DVB_BT8XX 1config DVB_BT8XX
2 tristate "BT8xx based PCI cards" 2 tristate "BT8xx based PCI cards"
3 depends on DVB_CORE && PCI && I2C && VIDEO_BT848 3 depends on DVB_CORE && PCI && I2C && VIDEO_BT848
4 depends on HOTPLUG # due to FW_LOADER
5 select DVB_MT352 if !DVB_FE_CUSTOMISE 4 select DVB_MT352 if !DVB_FE_CUSTOMISE
6 select DVB_SP887X if !DVB_FE_CUSTOMISE 5 select DVB_SP887X if !DVB_FE_CUSTOMISE
7 select DVB_NXT6000 if !DVB_FE_CUSTOMISE 6 select DVB_NXT6000 if !DVB_FE_CUSTOMISE
@@ -10,7 +9,6 @@ config DVB_BT8XX
10 select DVB_LGDT330X if !DVB_FE_CUSTOMISE 9 select DVB_LGDT330X if !DVB_FE_CUSTOMISE
11 select DVB_ZL10353 if !DVB_FE_CUSTOMISE 10 select DVB_ZL10353 if !DVB_FE_CUSTOMISE
12 select MEDIA_TUNER_SIMPLE if !DVB_FE_CUSTOMISE 11 select MEDIA_TUNER_SIMPLE if !DVB_FE_CUSTOMISE
13 select FW_LOADER
14 help 12 help
15 Support for PCI cards based on the Bt8xx PCI bridge. Examples are 13 Support for PCI cards based on the Bt8xx PCI bridge. Examples are
16 the Nebula cards, the Pinnacle PCTV cards, the Twinhan DST cards, 14 the Nebula cards, the Pinnacle PCTV cards, the Twinhan DST cards,
diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
index a577c0f89f67..e84152b7576d 100644
--- a/drivers/media/dvb/dvb-usb/Kconfig
+++ b/drivers/media/dvb/dvb-usb/Kconfig
@@ -1,8 +1,6 @@
1config DVB_USB 1config DVB_USB
2 tristate "Support for various USB DVB devices" 2 tristate "Support for various USB DVB devices"
3 depends on DVB_CORE && USB && I2C && INPUT 3 depends on DVB_CORE && USB && I2C && INPUT
4 depends on HOTPLUG # due to FW_LOADER
5 select FW_LOADER
6 help 4 help
7 By enabling this you will be able to choose the various supported 5 By enabling this you will be able to choose the various supported
8 USB1.1 and USB2.0 DVB devices. 6 USB1.1 and USB2.0 DVB devices.
@@ -246,6 +244,14 @@ config DVB_USB_AF9005_REMOTE
246 Say Y here to support the default remote control decoding for the 244 Say Y here to support the default remote control decoding for the
247 Afatech AF9005 based receiver. 245 Afatech AF9005 based receiver.
248 246
247config DVB_USB_DW2102
248 tristate "DvbWorld 2102 DVB-S USB2.0 receiver"
249 depends on DVB_USB
250 select DVB_STV0299 if !DVB_FE_CUSTOMISE
251 select DVB_PLL if !DVB_FE_CUSTOMISE
252 help
253 Say Y here to support the DvbWorld 2102 DVB-S USB2.0 receiver.
254
249config DVB_USB_ANYSEE 255config DVB_USB_ANYSEE
250 tristate "Anysee DVB-T/C USB2.0 support" 256 tristate "Anysee DVB-T/C USB2.0 support"
251 depends on DVB_USB 257 depends on DVB_USB
diff --git a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Makefile
index 44c11e45e564..e206f1ea0027 100644
--- a/drivers/media/dvb/dvb-usb/Makefile
+++ b/drivers/media/dvb/dvb-usb/Makefile
@@ -64,6 +64,9 @@ obj-$(CONFIG_DVB_USB_AF9005_REMOTE) += dvb-usb-af9005-remote.o
64dvb-usb-anysee-objs = anysee.o 64dvb-usb-anysee-objs = anysee.o
65obj-$(CONFIG_DVB_USB_ANYSEE) += dvb-usb-anysee.o 65obj-$(CONFIG_DVB_USB_ANYSEE) += dvb-usb-anysee.o
66 66
67dvb-usb-dw2102-objs = dw2102.o
68obj-$(CONFIG_DVB_USB_DW2102) += dvb-usb-dw2102.o
69
67EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/ 70EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/
68# due to tuner-xc3028 71# due to tuner-xc3028
69EXTRA_CFLAGS += -Idrivers/media/common/tuners 72EXTRA_CFLAGS += -Idrivers/media/common/tuners
diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c
index adfd4fc82efd..2f408d2e1ef3 100644
--- a/drivers/media/dvb/dvb-usb/anysee.c
+++ b/drivers/media/dvb/dvb-usb/anysee.c
@@ -43,7 +43,7 @@ module_param_named(debug, dvb_usb_anysee_debug, int, 0644);
43MODULE_PARM_DESC(debug, "set debugging level" DVB_USB_DEBUG_STATUS); 43MODULE_PARM_DESC(debug, "set debugging level" DVB_USB_DEBUG_STATUS);
44DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 44DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
45 45
46struct mutex anysee_usb_mutex; 46static struct mutex anysee_usb_mutex;
47 47
48static int anysee_ctrl_msg(struct dvb_usb_device *d, u8 *sbuf, u8 slen, 48static int anysee_ctrl_msg(struct dvb_usb_device *d, u8 *sbuf, u8 slen,
49 u8 *rbuf, u8 rlen) 49 u8 *rbuf, u8 rlen)
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index e5238b31e946..029b437caf9a 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -204,5 +204,6 @@
204#define USB_PID_ASUS_U3000 0x171f 204#define USB_PID_ASUS_U3000 0x171f
205#define USB_PID_ASUS_U3100 0x173f 205#define USB_PID_ASUS_U3100 0x173f
206#define USB_PID_YUAN_EC372S 0x1edc 206#define USB_PID_YUAN_EC372S 0x1edc
207#define USB_PID_DW2102 0x2102
207 208
208#endif 209#endif
diff --git a/drivers/media/dvb/dvb-usb/dw2102.c b/drivers/media/dvb/dvb-usb/dw2102.c
new file mode 100644
index 000000000000..a4d898b44e55
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/dw2102.c
@@ -0,0 +1,425 @@
1/* DVB USB framework compliant Linux driver for the DVBWorld DVB-S 2102 Card
2*
3* Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
4*
5* This program is free software; you can redistribute it and/or modify it
6* under the terms of the GNU General Public License as published by the
7* Free Software Foundation, version 2.
8*
9* see Documentation/dvb/README.dvb-usb for more information
10*/
11#include <linux/version.h>
12#include "dw2102.h"
13#include "stv0299.h"
14#include "z0194a.h"
15
16#ifndef USB_PID_DW2102
17#define USB_PID_DW2102 0x2102
18#endif
19
20#define DW2102_READ_MSG 0
21#define DW2102_WRITE_MSG 1
22
23#define REG_1F_SYMBOLRATE_BYTE0 0x1f
24#define REG_20_SYMBOLRATE_BYTE1 0x20
25#define REG_21_SYMBOLRATE_BYTE2 0x21
26
27#define DW2102_VOLTAGE_CTRL (0x1800)
28#define DW2102_RC_QUERY (0x1a00)
29
30struct dw2102_state {
31 u32 last_key_pressed;
32};
33struct dw2102_rc_keys {
34 u32 keycode;
35 u32 event;
36};
37
38DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
39
40static int dw2102_op_rw(struct usb_device *dev, u8 request, u16 value,
41 u8 *data, u16 len, int flags)
42{
43 int ret;
44 u8 u8buf[len];
45
46 unsigned int pipe = (flags == DW2102_READ_MSG) ?
47 usb_rcvctrlpipe(dev, 0) : usb_sndctrlpipe(dev, 0);
48 u8 request_type = (flags == DW2102_READ_MSG) ? USB_DIR_IN : USB_DIR_OUT;
49
50 if (flags == DW2102_WRITE_MSG)
51 memcpy(u8buf, data, len);
52 ret = usb_control_msg(dev, pipe, request,
53 request_type | USB_TYPE_VENDOR, value, 0 , u8buf, len, 2000);
54
55 if (flags == DW2102_READ_MSG)
56 memcpy(data, u8buf, len);
57 return ret;
58}
59
60/* I2C */
61
62static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
63 int num)
64{
65struct dvb_usb_device *d = i2c_get_adapdata(adap);
66 int i = 0, ret = 0;
67 u8 buf6[] = {0x2c, 0x05, 0xc0, 0, 0, 0, 0};
68 u8 request;
69 u16 value;
70
71 if (!d)
72 return -ENODEV;
73 if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
74 return -EAGAIN;
75
76 switch (num) {
77 case 2:
78 /* read stv0299 register */
79 request = 0xb5;
80 value = msg[0].buf[0];/* register */
81 for (i = 0; i < msg[1].len; i++) {
82 value = value + i;
83 ret = dw2102_op_rw(d->udev, 0xb5,
84 value, buf6, 2, DW2102_READ_MSG);
85 msg[1].buf[i] = buf6[0];
86
87 }
88 break;
89 case 1:
90 switch (msg[0].addr) {
91 case 0x68:
92 /* write to stv0299 register */
93 buf6[0] = 0x2a;
94 buf6[1] = msg[0].buf[0];
95 buf6[2] = msg[0].buf[1];
96 ret = dw2102_op_rw(d->udev, 0xb2,
97 0, buf6, 3, DW2102_WRITE_MSG);
98 break;
99 case 0x60:
100 if (msg[0].flags == 0) {
101 /* write to tuner pll */
102 buf6[0] = 0x2c;
103 buf6[1] = 5;
104 buf6[2] = 0xc0;
105 buf6[3] = msg[0].buf[0];
106 buf6[4] = msg[0].buf[1];
107 buf6[5] = msg[0].buf[2];
108 buf6[6] = msg[0].buf[3];
109 ret = dw2102_op_rw(d->udev, 0xb2,
110 0, buf6, 7, DW2102_WRITE_MSG);
111 } else {
112 /* write to tuner pll */
113 ret = dw2102_op_rw(d->udev, 0xb5,
114 0, buf6, 1, DW2102_READ_MSG);
115 msg[0].buf[0] = buf6[0];
116 }
117 break;
118 case (DW2102_RC_QUERY):
119 ret = dw2102_op_rw(d->udev, 0xb8,
120 0, buf6, 2, DW2102_READ_MSG);
121 msg[0].buf[0] = buf6[0];
122 msg[0].buf[1] = buf6[1];
123 break;
124 case (DW2102_VOLTAGE_CTRL):
125 buf6[0] = 0x30;
126 buf6[1] = msg[0].buf[0];
127 ret = dw2102_op_rw(d->udev, 0xb2,
128 0, buf6, 2, DW2102_WRITE_MSG);
129 break;
130 }
131
132 break;
133 }
134
135 mutex_unlock(&d->i2c_mutex);
136 return num;
137}
138
139static u32 dw2102_i2c_func(struct i2c_adapter *adapter)
140{
141 return I2C_FUNC_I2C;
142}
143
144static struct i2c_algorithm dw2102_i2c_algo = {
145 .master_xfer = dw2102_i2c_transfer,
146 .functionality = dw2102_i2c_func,
147};
148
149static int dw2102_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
150{
151 static u8 command_13v[1] = {0x00};
152 static u8 command_18v[1] = {0x01};
153 struct i2c_msg msg[] = {
154 {.addr = DW2102_VOLTAGE_CTRL, .flags = 0,
155 .buf = command_13v, .len = 1},
156 };
157
158 struct dvb_usb_adapter *udev_adap =
159 (struct dvb_usb_adapter *)(fe->dvb->priv);
160 if (voltage == SEC_VOLTAGE_18)
161 msg[0].buf = command_18v;
162 i2c_transfer(&udev_adap->dev->i2c_adap, msg, 1);
163 return 0;
164}
165
166static int dw2102_frontend_attach(struct dvb_usb_adapter *d)
167{
168 d->fe = dvb_attach(stv0299_attach, &sharp_z0194a_config,
169 &d->dev->i2c_adap);
170 if (d->fe != NULL) {
171 d->fe->ops.set_voltage = dw2102_set_voltage;
172 info("Attached stv0299!\n");
173 return 0;
174 }
175 return -EIO;
176}
177
178static int dw2102_tuner_attach(struct dvb_usb_adapter *adap)
179{
180 dvb_attach(dvb_pll_attach, adap->fe, 0x60,
181 &adap->dev->i2c_adap, DVB_PLL_OPERA1);
182 return 0;
183}
184
185static struct dvb_usb_rc_key dw2102_rc_keys[] = {
186 { 0xf8, 0x0a, KEY_Q }, /*power*/
187 { 0xf8, 0x0c, KEY_M }, /*mute*/
188 { 0xf8, 0x11, KEY_1 },
189 { 0xf8, 0x12, KEY_2 },
190 { 0xf8, 0x13, KEY_3 },
191 { 0xf8, 0x14, KEY_4 },
192 { 0xf8, 0x15, KEY_5 },
193 { 0xf8, 0x16, KEY_6 },
194 { 0xf8, 0x17, KEY_7 },
195 { 0xf8, 0x18, KEY_8 },
196 { 0xf8, 0x19, KEY_9 },
197 { 0xf8, 0x10, KEY_0 },
198 { 0xf8, 0x1c, KEY_PAGEUP }, /*ch+*/
199 { 0xf8, 0x0f, KEY_PAGEDOWN }, /*ch-*/
200 { 0xf8, 0x1a, KEY_O }, /*vol+*/
201 { 0xf8, 0x0e, KEY_Z }, /*vol-*/
202 { 0xf8, 0x04, KEY_R }, /*rec*/
203 { 0xf8, 0x09, KEY_D }, /*fav*/
204 { 0xf8, 0x08, KEY_BACKSPACE }, /*rewind*/
205 { 0xf8, 0x07, KEY_A }, /*fast*/
206 { 0xf8, 0x0b, KEY_P }, /*pause*/
207 { 0xf8, 0x02, KEY_ESC }, /*cancel*/
208 { 0xf8, 0x03, KEY_G }, /*tab*/
209 { 0xf8, 0x00, KEY_UP }, /*up*/
210 { 0xf8, 0x1f, KEY_ENTER }, /*ok*/
211 { 0xf8, 0x01, KEY_DOWN }, /*down*/
212 { 0xf8, 0x05, KEY_C }, /*cap*/
213 { 0xf8, 0x06, KEY_S }, /*stop*/
214 { 0xf8, 0x40, KEY_F }, /*full*/
215 { 0xf8, 0x1e, KEY_W }, /*tvmode*/
216 { 0xf8, 0x1b, KEY_B }, /*recall*/
217
218};
219
220
221
222static int dw2102_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
223{
224 struct dw2102_state *st = d->priv;
225 u8 key[2];
226 struct i2c_msg msg[] = {
227 {.addr = DW2102_RC_QUERY, .flags = I2C_M_RD, .buf = key,
228 .len = 2},
229 };
230 int i;
231
232 *state = REMOTE_NO_KEY_PRESSED;
233 if (dw2102_i2c_transfer(&d->i2c_adap, msg, 1) == 1) {
234 for (i = 0; i < ARRAY_SIZE(dw2102_rc_keys); i++) {
235 if (dw2102_rc_keys[i].data == msg[0].buf[0]) {
236 *state = REMOTE_KEY_PRESSED;
237 *event = dw2102_rc_keys[i].event;
238 st->last_key_pressed =
239 dw2102_rc_keys[i].event;
240 break;
241 }
242 st->last_key_pressed = 0;
243 }
244 }
245 /* info("key: %x %x\n",key[0],key[1]); */
246 return 0;
247}
248
249static struct usb_device_id dw2102_table[] = {
250 {USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW2102)},
251 {USB_DEVICE(USB_VID_CYPRESS, 0x2101)},
252 { }
253};
254
255MODULE_DEVICE_TABLE(usb, dw2102_table);
256
257static int dw2102_load_firmware(struct usb_device *dev,
258 const struct firmware *frmwr)
259{
260 u8 *b, *p;
261 int ret = 0, i;
262 u8 reset;
263 u8 reset16 [] = {0, 0, 0, 0, 0, 0, 0};
264 const struct firmware *fw;
265 const char *filename = "dvb-usb-dw2101.fw";
266 switch (dev->descriptor.idProduct) {
267 case 0x2101:
268 ret = request_firmware(&fw, filename, &dev->dev);
269 if (ret != 0) {
270 err("did not find the firmware file. (%s) "
271 "Please see linux/Documentation/dvb/ for more details "
272 "on firmware-problems.", filename);
273 return ret;
274 }
275 break;
276 case USB_PID_DW2102:
277 fw = frmwr;
278 break;
279 }
280 info("start downloading DW2102 firmware");
281 p = kmalloc(fw->size, GFP_KERNEL);
282 reset = 1;
283 /*stop the CPU*/
284 dw2102_op_rw(dev, 0xa0, 0x7f92, &reset, 1, DW2102_WRITE_MSG);
285 dw2102_op_rw(dev, 0xa0, 0xe600, &reset, 1, DW2102_WRITE_MSG);
286
287 if (p != NULL) {
288 memcpy(p, fw->data, fw->size);
289 for (i = 0; i < fw->size; i += 0x40) {
290 b = (u8 *) p + i;
291 if (dw2102_op_rw
292 (dev, 0xa0, i, b , 0x40,
293 DW2102_WRITE_MSG) != 0x40
294 ) {
295 err("error while transferring firmware");
296 ret = -EINVAL;
297 break;
298 }
299 }
300 /* restart the CPU */
301 reset = 0;
302 if (ret || dw2102_op_rw
303 (dev, 0xa0, 0x7f92, &reset, 1,
304 DW2102_WRITE_MSG) != 1) {
305 err("could not restart the USB controller CPU.");
306 ret = -EINVAL;
307 }
308 if (ret || dw2102_op_rw
309 (dev, 0xa0, 0xe600, &reset, 1,
310 DW2102_WRITE_MSG) != 1) {
311 err("could not restart the USB controller CPU.");
312 ret = -EINVAL;
313 }
314 /* init registers */
315 switch (dev->descriptor.idProduct) {
316 case USB_PID_DW2102:
317 dw2102_op_rw
318 (dev, 0xbf, 0x0040, &reset, 0,
319 DW2102_WRITE_MSG);
320 dw2102_op_rw
321 (dev, 0xb9, 0x0000, &reset16[0], 2,
322 DW2102_READ_MSG);
323 break;
324 case 0x2101:
325 dw2102_op_rw
326 (dev, 0xbc, 0x0030, &reset16[0], 2,
327 DW2102_READ_MSG);
328 dw2102_op_rw
329 (dev, 0xba, 0x0000, &reset16[0], 7,
330 DW2102_READ_MSG);
331 dw2102_op_rw
332 (dev, 0xba, 0x0000, &reset16[0], 7,
333 DW2102_READ_MSG);
334 dw2102_op_rw
335 (dev, 0xb9, 0x0000, &reset16[0], 2,
336 DW2102_READ_MSG);
337 break;
338 }
339 kfree(p);
340 }
341 return ret;
342}
343
344static struct dvb_usb_device_properties dw2102_properties = {
345 .caps = DVB_USB_IS_AN_I2C_ADAPTER,
346 .usb_ctrl = DEVICE_SPECIFIC,
347 .firmware = "dvb-usb-dw2102.fw",
348 .size_of_priv = sizeof(struct dw2102_state),
349 .no_reconnect = 1,
350
351 .i2c_algo = &dw2102_i2c_algo,
352 .rc_key_map = dw2102_rc_keys,
353 .rc_key_map_size = ARRAY_SIZE(dw2102_rc_keys),
354 .rc_interval = 150,
355 .rc_query = dw2102_rc_query,
356
357 .generic_bulk_ctrl_endpoint = 0x81,
358 /* parameter for the MPEG2-data transfer */
359 .num_adapters = 1,
360 .download_firmware = dw2102_load_firmware,
361 .adapter = {
362 {
363 .frontend_attach = dw2102_frontend_attach,
364 .streaming_ctrl = NULL,
365 .tuner_attach = dw2102_tuner_attach,
366 .stream = {
367 .type = USB_BULK,
368 .count = 8,
369 .endpoint = 0x82,
370 .u = {
371 .bulk = {
372 .buffersize = 4096,
373 }
374 }
375 },
376 }
377 },
378 .num_device_descs = 2,
379 .devices = {
380 {"DVBWorld DVB-S 2102 USB2.0",
381 {&dw2102_table[0], NULL},
382 {NULL},
383 },
384 {"DVBWorld DVB-S 2101 USB2.0",
385 {&dw2102_table[1], NULL},
386 {NULL},
387 },
388 }
389};
390
391static int dw2102_probe(struct usb_interface *intf,
392 const struct usb_device_id *id)
393{
394 return dvb_usb_device_init(intf, &dw2102_properties,
395 THIS_MODULE, NULL, adapter_nr);
396}
397
398static struct usb_driver dw2102_driver = {
399 .name = "dw2102",
400 .probe = dw2102_probe,
401 .disconnect = dvb_usb_device_exit,
402 .id_table = dw2102_table,
403};
404
405static int __init dw2102_module_init(void)
406{
407 int ret = usb_register(&dw2102_driver);
408 if (ret)
409 err("usb_register failed. Error number %d", ret);
410
411 return ret;
412}
413
414static void __exit dw2102_module_exit(void)
415{
416 usb_deregister(&dw2102_driver);
417}
418
419module_init(dw2102_module_init);
420module_exit(dw2102_module_exit);
421
422MODULE_AUTHOR("Igor M. Liplianin (c) liplianin@me.by");
423MODULE_DESCRIPTION("Driver for DVBWorld DVB-S 2101 2102 USB2.0 device");
424MODULE_VERSION("0.1");
425MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/dw2102.h b/drivers/media/dvb/dvb-usb/dw2102.h
new file mode 100644
index 000000000000..7a310f906837
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/dw2102.h
@@ -0,0 +1,9 @@
1#ifndef _DW2102_H_
2#define _DW2102_H_
3
4#define DVB_USB_LOG_PREFIX "dw2102"
5#include "dvb-usb.h"
6
7extern int dvb_usb_dw2102_debug;
8#define deb_xfer(args...) dprintk(dvb_usb_dw2102_debug, 0x02, args)
9#endif
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index c20553c4da1f..574dffe91b68 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -97,9 +97,8 @@ comment "DVB-T (terrestrial) frontends"
97 97
98config DVB_SP8870 98config DVB_SP8870
99 tristate "Spase sp8870 based" 99 tristate "Spase sp8870 based"
100 depends on DVB_CORE && I2C && HOTPLUG 100 depends on DVB_CORE && I2C
101 default m if DVB_FE_CUSTOMISE 101 default m if DVB_FE_CUSTOMISE
102 select FW_LOADER
103 help 102 help
104 A DVB-T tuner module. Say Y when you want to support this frontend. 103 A DVB-T tuner module. Say Y when you want to support this frontend.
105 104
@@ -110,9 +109,8 @@ config DVB_SP8870
110 109
111config DVB_SP887X 110config DVB_SP887X
112 tristate "Spase sp887x based" 111 tristate "Spase sp887x based"
113 depends on DVB_CORE && I2C && HOTPLUG 112 depends on DVB_CORE && I2C
114 default m if DVB_FE_CUSTOMISE 113 default m if DVB_FE_CUSTOMISE
115 select FW_LOADER
116 help 114 help
117 A DVB-T tuner module. Say Y when you want to support this frontend. 115 A DVB-T tuner module. Say Y when you want to support this frontend.
118 116
@@ -135,6 +133,20 @@ config DVB_CX22702
135 help 133 help
136 A DVB-T tuner module. Say Y when you want to support this frontend. 134 A DVB-T tuner module. Say Y when you want to support this frontend.
137 135
136config DVB_DRX397XD
137 tristate "Micronas DRX3975D/DRX3977D based"
138 depends on DVB_CORE && I2C && HOTPLUG
139 default m if DVB_FE_CUSTOMISE
140 select FW_LOADER
141 help
142 A DVB-T tuner module. Say Y when you want to support this frontend.
143
144 TODO:
145 This driver needs external firmware. Please use the command
146 "<kerneldir>/Documentation/dvb/get_dvb_firmware drx397xD" to
147 download/extract them, and then copy them to /usr/lib/hotplug/firmware
148 or /lib/firmware (depending on configuration of firmware hotplug).
149
138config DVB_L64781 150config DVB_L64781
139 tristate "LSI L64781" 151 tristate "LSI L64781"
140 depends on DVB_CORE && I2C 152 depends on DVB_CORE && I2C
@@ -144,9 +156,8 @@ config DVB_L64781
144 156
145config DVB_TDA1004X 157config DVB_TDA1004X
146 tristate "Philips TDA10045H/TDA10046H based" 158 tristate "Philips TDA10045H/TDA10046H based"
147 depends on DVB_CORE && I2C && HOTPLUG 159 depends on DVB_CORE && I2C
148 default m if DVB_FE_CUSTOMISE 160 default m if DVB_FE_CUSTOMISE
149 select FW_LOADER
150 help 161 help
151 A DVB-T tuner module. Say Y when you want to support this frontend. 162 A DVB-T tuner module. Say Y when you want to support this frontend.
152 163
@@ -211,9 +222,8 @@ config DVB_DIB7000P
211 222
212config DVB_TDA10048 223config DVB_TDA10048
213 tristate "Philips TDA10048HN based" 224 tristate "Philips TDA10048HN based"
214 depends on DVB_CORE && I2C && HOTPLUG 225 depends on DVB_CORE && I2C
215 default m if DVB_FE_CUSTOMISE 226 default m if DVB_FE_CUSTOMISE
216 select FW_LOADER
217 help 227 help
218 A DVB-T tuner module. Say Y when you want to support this frontend. 228 A DVB-T tuner module. Say Y when you want to support this frontend.
219 229
@@ -253,9 +263,8 @@ comment "ATSC (North American/Korean Terrestrial/Cable DTV) frontends"
253 263
254config DVB_NXT200X 264config DVB_NXT200X
255 tristate "NxtWave Communications NXT2002/NXT2004 based" 265 tristate "NxtWave Communications NXT2002/NXT2004 based"
256 depends on DVB_CORE && I2C && HOTPLUG 266 depends on DVB_CORE && I2C
257 default m if DVB_FE_CUSTOMISE 267 default m if DVB_FE_CUSTOMISE
258 select FW_LOADER
259 help 268 help
260 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want 269 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
261 to support this frontend. 270 to support this frontend.
@@ -268,9 +277,8 @@ config DVB_NXT200X
268 277
269config DVB_OR51211 278config DVB_OR51211
270 tristate "Oren OR51211 based" 279 tristate "Oren OR51211 based"
271 depends on DVB_CORE && I2C && HOTPLUG 280 depends on DVB_CORE && I2C
272 default m if DVB_FE_CUSTOMISE 281 default m if DVB_FE_CUSTOMISE
273 select FW_LOADER
274 help 282 help
275 An ATSC 8VSB tuner module. Say Y when you want to support this frontend. 283 An ATSC 8VSB tuner module. Say Y when you want to support this frontend.
276 284
@@ -281,9 +289,8 @@ config DVB_OR51211
281 289
282config DVB_OR51132 290config DVB_OR51132
283 tristate "Oren OR51132 based" 291 tristate "Oren OR51132 based"
284 depends on DVB_CORE && I2C && HOTPLUG 292 depends on DVB_CORE && I2C
285 default m if DVB_FE_CUSTOMISE 293 default m if DVB_FE_CUSTOMISE
286 select FW_LOADER
287 help 294 help
288 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want 295 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
289 to support this frontend. 296 to support this frontend.
@@ -297,9 +304,8 @@ config DVB_OR51132
297 304
298config DVB_BCM3510 305config DVB_BCM3510
299 tristate "Broadcom BCM3510" 306 tristate "Broadcom BCM3510"
300 depends on DVB_CORE && I2C && HOTPLUG 307 depends on DVB_CORE && I2C
301 default m if DVB_FE_CUSTOMISE 308 default m if DVB_FE_CUSTOMISE
302 select FW_LOADER
303 help 309 help
304 An ATSC 8VSB/16VSB and QAM64/256 tuner module. Say Y when you want to 310 An ATSC 8VSB/16VSB and QAM64/256 tuner module. Say Y when you want to
305 support this frontend. 311 support this frontend.
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index a89dc0fc4c6f..028da55611c0 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_DVB_NXT6000) += nxt6000.o
25obj-$(CONFIG_DVB_MT352) += mt352.o 25obj-$(CONFIG_DVB_MT352) += mt352.o
26obj-$(CONFIG_DVB_ZL10353) += zl10353.o 26obj-$(CONFIG_DVB_ZL10353) += zl10353.o
27obj-$(CONFIG_DVB_CX22702) += cx22702.o 27obj-$(CONFIG_DVB_CX22702) += cx22702.o
28obj-$(CONFIG_DVB_DRX397XD) += drx397xD.o
28obj-$(CONFIG_DVB_TDA10021) += tda10021.o 29obj-$(CONFIG_DVB_TDA10021) += tda10021.o
29obj-$(CONFIG_DVB_TDA10023) += tda10023.o 30obj-$(CONFIG_DVB_TDA10023) += tda10023.o
30obj-$(CONFIG_DVB_STV0297) += stv0297.o 31obj-$(CONFIG_DVB_STV0297) += stv0297.o
diff --git a/drivers/media/dvb/frontends/drx397xD.c b/drivers/media/dvb/frontends/drx397xD.c
new file mode 100644
index 000000000000..3cbed874a6f8
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx397xD.c
@@ -0,0 +1,1504 @@
1/*
2 * Driver for Micronas drx397xD demodulator
3 *
4 * Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DEBUG /* uncomment if you want debugging output */
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/device.h>
26#include <linux/delay.h>
27#include <linux/string.h>
28#include <linux/firmware.h>
29#include <asm/div64.h>
30
31#include "dvb_frontend.h"
32#include "drx397xD.h"
33
34static const char mod_name[] = "drx397xD";
35
36#define MAX_CLOCK_DRIFT 200 /* maximal 200 PPM allowed */
37
38#define F_SET_0D0h 1
39#define F_SET_0D4h 2
40
41typedef enum fw_ix {
42#define _FW_ENTRY(a, b) b
43#include "drx397xD_fw.h"
44} fw_ix_t;
45
46/* chip specifics */
47struct drx397xD_state {
48 struct i2c_adapter *i2c;
49 struct dvb_frontend frontend;
50 struct drx397xD_config config;
51 fw_ix_t chip_rev;
52 int flags;
53 u32 bandwidth_parm; /* internal bandwidth conversions */
54 u32 f_osc; /* w90: actual osc frequency [Hz] */
55};
56
57/*******************************************************************************
58 * Firmware
59 ******************************************************************************/
60
61static const char *blob_name[] = {
62#define _BLOB_ENTRY(a, b) a
63#include "drx397xD_fw.h"
64};
65
66typedef enum blob_ix {
67#define _BLOB_ENTRY(a, b) b
68#include "drx397xD_fw.h"
69} blob_ix_t;
70
71static struct {
72 const char *name;
73 const struct firmware *file;
74 rwlock_t lock;
75 int refcnt;
76 const u8 *data[ARRAY_SIZE(blob_name)];
77} fw[] = {
78#define _FW_ENTRY(a, b) { \
79 .name = a, \
80 .file = 0, \
81 .lock = RW_LOCK_UNLOCKED, \
82 .refcnt = 0, \
83 .data = { } }
84#include "drx397xD_fw.h"
85};
86
87/* use only with writer lock aquired */
88static void _drx_release_fw(struct drx397xD_state *s, fw_ix_t ix)
89{
90 memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
91 if (fw[ix].file)
92 release_firmware(fw[ix].file);
93}
94
95static void drx_release_fw(struct drx397xD_state *s)
96{
97 fw_ix_t ix = s->chip_rev;
98
99 pr_debug("%s\n", __FUNCTION__);
100
101 write_lock(&fw[ix].lock);
102 if (fw[ix].refcnt) {
103 fw[ix].refcnt--;
104 if (fw[ix].refcnt == 0)
105 _drx_release_fw(s, ix);
106 }
107 write_unlock(&fw[ix].lock);
108}
109
110static int drx_load_fw(struct drx397xD_state *s, fw_ix_t ix)
111{
112 const u8 *data;
113 size_t size, len;
114 int i = 0, j, rc = -EINVAL;
115
116 pr_debug("%s\n", __FUNCTION__);
117
118 if (ix < 0 || ix >= ARRAY_SIZE(fw))
119 return -EINVAL;
120 s->chip_rev = ix;
121
122 write_lock(&fw[ix].lock);
123 if (fw[ix].file) {
124 rc = 0;
125 goto exit_ok;
126 }
127 memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
128
129 if (request_firmware(&fw[ix].file, fw[ix].name, &s->i2c->dev) != 0) {
130 printk(KERN_ERR "%s: Firmware \"%s\" not available\n",
131 mod_name, fw[ix].name);
132 rc = -ENOENT;
133 goto exit_err;
134 }
135
136 if (!fw[ix].file->data || fw[ix].file->size < 10)
137 goto exit_corrupt;
138
139 data = fw[ix].file->data;
140 size = fw[ix].file->size;
141
142 if (data[i++] != 2) /* check firmware version */
143 goto exit_corrupt;
144
145 do {
146 switch (data[i++]) {
147 case 0x00: /* bytecode */
148 if (i >= size)
149 break;
150 i += data[i];
151 case 0x01: /* reset */
152 case 0x02: /* sleep */
153 i++;
154 break;
155 case 0xfe: /* name */
156 len = strnlen(&data[i], size - i);
157 if (i + len + 1 >= size)
158 goto exit_corrupt;
159 if (data[i + len + 1] != 0)
160 goto exit_corrupt;
161 for (j = 0; j < ARRAY_SIZE(blob_name); j++) {
162 if (strcmp(blob_name[j], &data[i]) == 0) {
163 fw[ix].data[j] = &data[i + len + 1];
164 pr_debug("Loading %s\n", blob_name[j]);
165 }
166 }
167 i += len + 1;
168 break;
169 case 0xff: /* file terminator */
170 if (i == size) {
171 rc = 0;
172 goto exit_ok;
173 }
174 default:
175 goto exit_corrupt;
176 }
177 } while (i < size);
178 exit_corrupt:
179 printk(KERN_ERR "%s: Firmware is corrupt\n", mod_name);
180 exit_err:
181 _drx_release_fw(s, ix);
182 fw[ix].refcnt--;
183 exit_ok:
184 fw[ix].refcnt++;
185 write_unlock(&fw[ix].lock);
186 return rc;
187}
188
189/*******************************************************************************
190 * i2c bus IO
191 ******************************************************************************/
192
193static int write_fw(struct drx397xD_state *s, blob_ix_t ix)
194{
195 struct i2c_msg msg = {.addr = s->config.demod_address,.flags = 0 };
196 const u8 *data;
197 int len, rc = 0, i = 0;
198
199 if (ix < 0 || ix >= ARRAY_SIZE(blob_name)) {
200 pr_debug("%s drx_fw_ix_t out of range\n", __FUNCTION__);
201 return -EINVAL;
202 }
203 pr_debug("%s %s\n", __FUNCTION__, blob_name[ix]);
204
205 read_lock(&fw[s->chip_rev].lock);
206 data = fw[s->chip_rev].data[ix];
207 if (!data) {
208 rc = -EINVAL;
209 goto exit_rc;
210 }
211
212 for (;;) {
213 switch (data[i++]) {
214 case 0: /* bytecode */
215 len = data[i++];
216 msg.len = len;
217 msg.buf = (__u8 *) &data[i];
218 if (i2c_transfer(s->i2c, &msg, 1) != 1) {
219 rc = -EIO;
220 goto exit_rc;
221 }
222 i += len;
223 break;
224 case 1: /* reset */
225 case 2: /* sleep */
226 i++;
227 break;
228 default:
229 goto exit_rc;
230 }
231 }
232 exit_rc:
233 read_unlock(&fw[s->chip_rev].lock);
234 return 0;
235}
236
237/* Function is not endian safe, use the RD16 wrapper below */
238static int _read16(struct drx397xD_state *s, u32 i2c_adr)
239{
240 int rc;
241 u8 a[4];
242 u16 v;
243 struct i2c_msg msg[2] = {
244 {
245 .addr = s->config.demod_address,
246 .flags = 0,
247 .buf = a,
248 .len = sizeof(a)
249 }
250 , {
251 .addr = s->config.demod_address,
252 .flags = I2C_M_RD,
253 .buf = (u8 *) & v,
254 .len = sizeof(v)
255 }
256 };
257
258 *(u32 *) a = i2c_adr;
259
260 rc = i2c_transfer(s->i2c, msg, 2);
261 if (rc != 2)
262 return -EIO;
263
264 return le16_to_cpu(v);
265}
266
267/* Function is not endian safe, use the WR16.. wrappers below */
268static int _write16(struct drx397xD_state *s, u32 i2c_adr, u16 val)
269{
270 u8 a[6];
271 int rc;
272 struct i2c_msg msg = {
273 .addr = s->config.demod_address,
274 .flags = 0,
275 .buf = a,
276 .len = sizeof(a)
277 };
278
279 *(u32 *) a = i2c_adr;
280 *(u16 *) & a[4] = val;
281
282 rc = i2c_transfer(s->i2c, &msg, 1);
283 if (rc != 1)
284 return -EIO;
285 return 0;
286}
287
288#define WR16(ss,adr, val) \
289 _write16(ss, I2C_ADR_C0(adr), cpu_to_le16(val))
290#define WR16_E0(ss,adr, val) \
291 _write16(ss, I2C_ADR_E0(adr), cpu_to_le16(val))
292#define RD16(ss,adr) \
293 _read16(ss, I2C_ADR_C0(adr))
294
295#define EXIT_RC( cmd ) if ( (rc = (cmd)) < 0) goto exit_rc
296
297/*******************************************************************************
298 * Tuner callback
299 ******************************************************************************/
300
301static int PLL_Set(struct drx397xD_state *s,
302 struct dvb_frontend_parameters *fep, int *df_tuner)
303{
304 struct dvb_frontend *fe = &s->frontend;
305 u32 f_tuner, f = fep->frequency;
306 int rc;
307
308 pr_debug("%s\n", __FUNCTION__);
309
310 if ((f > s->frontend.ops.tuner_ops.info.frequency_max) ||
311 (f < s->frontend.ops.tuner_ops.info.frequency_min))
312 return -EINVAL;
313
314 *df_tuner = 0;
315 if (!s->frontend.ops.tuner_ops.set_params ||
316 !s->frontend.ops.tuner_ops.get_frequency)
317 return -ENOSYS;
318
319 rc = s->frontend.ops.tuner_ops.set_params(fe, fep);
320 if (rc < 0)
321 return rc;
322
323 rc = s->frontend.ops.tuner_ops.get_frequency(fe, &f_tuner);
324 if (rc < 0)
325 return rc;
326
327 *df_tuner = f_tuner - f;
328 pr_debug("%s requested %d [Hz] tuner %d [Hz]\n", __FUNCTION__, f,
329 f_tuner);
330
331 return 0;
332}
333
334/*******************************************************************************
335 * Demodulator helper functions
336 ******************************************************************************/
337
338static int SC_WaitForReady(struct drx397xD_state *s)
339{
340 int cnt = 1000;
341 int rc;
342
343 pr_debug("%s\n", __FUNCTION__);
344
345 while (cnt--) {
346 rc = RD16(s, 0x820043);
347 if (rc == 0)
348 return 0;
349 }
350 return -1;
351}
352
353static int SC_SendCommand(struct drx397xD_state *s, int cmd)
354{
355 int rc;
356
357 pr_debug("%s\n", __FUNCTION__);
358
359 WR16(s, 0x820043, cmd);
360 SC_WaitForReady(s);
361 rc = RD16(s, 0x820042);
362 if ((rc & 0xffff) == 0xffff)
363 return -1;
364 return 0;
365}
366
367static int HI_Command(struct drx397xD_state *s, u16 cmd)
368{
369 int rc, cnt = 1000;
370
371 pr_debug("%s\n", __FUNCTION__);
372
373 rc = WR16(s, 0x420032, cmd);
374 if (rc < 0)
375 return rc;
376
377 do {
378 rc = RD16(s, 0x420032);
379 if (rc == 0) {
380 rc = RD16(s, 0x420031);
381 return rc;
382 }
383 if (rc < 0)
384 return rc;
385 } while (--cnt);
386 return rc;
387}
388
389static int HI_CfgCommand(struct drx397xD_state *s)
390{
391
392 pr_debug("%s\n", __FUNCTION__);
393
394 WR16(s, 0x420033, 0x3973);
395 WR16(s, 0x420034, s->config.w50); // code 4, log 4
396 WR16(s, 0x420035, s->config.w52); // code 15, log 9
397 WR16(s, 0x420036, s->config.demod_address << 1);
398 WR16(s, 0x420037, s->config.w56); // code (set_i2c ?? initX 1 ), log 1
399// WR16(s, 0x420033, 0x3973);
400 if ((s->config.w56 & 8) == 0)
401 return HI_Command(s, 3);
402 return WR16(s, 0x420032, 0x3);
403}
404
405static const u8 fastIncrDecLUT_15273[] = {
406 0x0e, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x12, 0x13, 0x14,
407 0x15, 0x16, 0x17, 0x18, 0x1a, 0x1b, 0x1c, 0x1d, 0x1f
408};
409
410static const u8 slowIncrDecLUT_15272[] = {
411 3, 4, 4, 5, 6
412};
413
414static int SetCfgIfAgc(struct drx397xD_state *s, struct drx397xD_CfgIfAgc *agc)
415{
416 u16 w06 = agc->w06;
417 u16 w08 = agc->w08;
418 u16 w0A = agc->w0A;
419 u16 w0C = agc->w0C;
420 int quot, rem, i, rc = -EINVAL;
421
422 pr_debug("%s\n", __FUNCTION__);
423
424 if (agc->w04 > 0x3ff)
425 goto exit_rc;
426
427 if (agc->d00 == 1) {
428 EXIT_RC(RD16(s, 0x0c20010));
429 rc &= ~0x10;
430 EXIT_RC(WR16(s, 0x0c20010, rc));
431 return WR16(s, 0x0c20030, agc->w04 & 0x7ff);
432 }
433
434 if (agc->d00 != 0)
435 goto exit_rc;
436 if (w0A < w08)
437 goto exit_rc;
438 if (w0A > 0x3ff)
439 goto exit_rc;
440 if (w0C > 0x3ff)
441 goto exit_rc;
442 if (w06 > 0x3ff)
443 goto exit_rc;
444
445 EXIT_RC(RD16(s, 0x0c20010));
446 rc |= 0x10;
447 EXIT_RC(WR16(s, 0x0c20010, rc));
448
449 EXIT_RC(WR16(s, 0x0c20025, (w06 >> 1) & 0x1ff));
450 EXIT_RC(WR16(s, 0x0c20031, (w0A - w08) >> 1));
451 EXIT_RC(WR16(s, 0x0c20032, ((w0A + w08) >> 1) - 0x1ff));
452
453 quot = w0C / 113;
454 rem = w0C % 113;
455 if (quot <= 8) {
456 quot = 8 - quot;
457 } else {
458 quot = 0;
459 rem += 113;
460 }
461
462 EXIT_RC(WR16(s, 0x0c20024, quot));
463
464 i = fastIncrDecLUT_15273[rem / 8];
465 EXIT_RC(WR16(s, 0x0c2002d, i));
466 EXIT_RC(WR16(s, 0x0c2002e, i));
467
468 i = slowIncrDecLUT_15272[rem / 28];
469 EXIT_RC(WR16(s, 0x0c2002b, i));
470 rc = WR16(s, 0x0c2002c, i);
471 exit_rc:
472 return rc;
473}
474
475static int SetCfgRfAgc(struct drx397xD_state *s, struct drx397xD_CfgRfAgc *agc)
476{
477 u16 w04 = agc->w04;
478 u16 w06 = agc->w06;
479 int rc = -1;
480
481 pr_debug("%s %d 0x%x 0x%x\n", __FUNCTION__, agc->d00, w04, w06);
482
483 if (w04 > 0x3ff)
484 goto exit_rc;
485
486 switch (agc->d00) {
487 case 1:
488 if (w04 == 0x3ff)
489 w04 = 0x400;
490
491 EXIT_RC(WR16(s, 0x0c20036, w04));
492 s->config.w9C &= ~2;
493 EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
494 EXIT_RC(RD16(s, 0x0c20010));
495 rc &= 0xbfdf;
496 EXIT_RC(WR16(s, 0x0c20010, rc));
497 EXIT_RC(RD16(s, 0x0c20013));
498 rc &= ~2;
499 break;
500 case 0:
501 // loc_8000659
502 s->config.w9C &= ~2;
503 EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
504 EXIT_RC(RD16(s, 0x0c20010));
505 rc &= 0xbfdf;
506 rc |= 0x4000;
507 EXIT_RC(WR16(s, 0x0c20010, rc));
508 EXIT_RC(WR16(s, 0x0c20051, (w06 >> 4) & 0x3f));
509 EXIT_RC(RD16(s, 0x0c20013));
510 rc &= ~2;
511 break;
512 default:
513 s->config.w9C |= 2;
514 EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
515 EXIT_RC(RD16(s, 0x0c20010));
516 rc &= 0xbfdf;
517 EXIT_RC(WR16(s, 0x0c20010, rc));
518
519 EXIT_RC(WR16(s, 0x0c20036, 0));
520
521 EXIT_RC(RD16(s, 0x0c20013));
522 rc |= 2;
523 }
524 rc = WR16(s, 0x0c20013, rc);
525 exit_rc:
526 return rc;
527}
528
529static int GetLockStatus(struct drx397xD_state *s, int *lockstat)
530{
531 int rc;
532
533 *lockstat = 0;
534
535 rc = RD16(s, 0x082004b);
536 if (rc < 0)
537 return rc;
538
539 if (s->config.d60 != 2)
540 return 0;
541
542 if ((rc & 7) == 7)
543 *lockstat |= 1;
544 if ((rc & 3) == 3)
545 *lockstat |= 2;
546 if (rc & 1)
547 *lockstat |= 4;
548 return 0;
549}
550
551static int CorrectSysClockDeviation(struct drx397xD_state *s)
552{
553 int rc = -EINVAL;
554 int lockstat;
555 u32 clk, clk_limit;
556
557 pr_debug("%s\n", __FUNCTION__);
558
559 if (s->config.d5C == 0) {
560 EXIT_RC(WR16(s, 0x08200e8, 0x010));
561 EXIT_RC(WR16(s, 0x08200e9, 0x113));
562 s->config.d5C = 1;
563 return rc;
564 }
565 if (s->config.d5C != 1)
566 goto exit_rc;
567
568 rc = RD16(s, 0x0820048);
569
570 rc = GetLockStatus(s, &lockstat);
571 if (rc < 0)
572 goto exit_rc;
573 if ((lockstat & 1) == 0)
574 goto exit_rc;
575
576 EXIT_RC(WR16(s, 0x0420033, 0x200));
577 EXIT_RC(WR16(s, 0x0420034, 0xc5));
578 EXIT_RC(WR16(s, 0x0420035, 0x10));
579 EXIT_RC(WR16(s, 0x0420036, 0x1));
580 EXIT_RC(WR16(s, 0x0420037, 0xa));
581 EXIT_RC(HI_Command(s, 6));
582 EXIT_RC(RD16(s, 0x0420040));
583 clk = rc;
584 EXIT_RC(RD16(s, 0x0420041));
585 clk |= rc << 16;
586
587 if (clk <= 0x26ffff)
588 goto exit_rc;
589 if (clk > 0x610000)
590 goto exit_rc;
591
592 if (!s->bandwidth_parm)
593 return -EINVAL;
594
595 /* round & convert to Hz */
596 clk = ((u64) (clk + 0x800000) * s->bandwidth_parm + (1 << 20)) >> 21;
597 clk_limit = s->config.f_osc * MAX_CLOCK_DRIFT / 1000;
598
599 if (clk - s->config.f_osc * 1000 + clk_limit <= 2 * clk_limit) {
600 s->f_osc = clk;
601 pr_debug("%s: osc %d %d [Hz]\n", __FUNCTION__,
602 s->config.f_osc * 1000, clk - s->config.f_osc * 1000);
603 }
604 rc = WR16(s, 0x08200e8, 0);
605 exit_rc:
606 return rc;
607}
608
609static int ConfigureMPEGOutput(struct drx397xD_state *s, int type)
610{
611 int rc, si, bp;
612
613 pr_debug("%s\n", __FUNCTION__);
614
615 si = s->config.wA0;
616 if (s->config.w98 == 0) {
617 si |= 1;
618 bp = 0;
619 } else {
620 si &= ~1;
621 bp = 0x200;
622 }
623 if (s->config.w9A == 0) {
624 si |= 0x80;
625 } else {
626 si &= ~0x80;
627 }
628
629 EXIT_RC(WR16(s, 0x2150045, 0));
630 EXIT_RC(WR16(s, 0x2150010, si));
631 EXIT_RC(WR16(s, 0x2150011, bp));
632 rc = WR16(s, 0x2150012, (type == 0 ? 0xfff : 0));
633 exit_rc:
634 return rc;
635}
636
637static int drx_tune(struct drx397xD_state *s,
638 struct dvb_frontend_parameters *fep)
639{
640 u16 v22 = 0;
641 u16 v1C = 0;
642 u16 v1A = 0;
643 u16 v18 = 0;
644 u32 edi = 0, ebx = 0, ebp = 0, edx = 0;
645 u16 v20 = 0, v1E = 0, v16 = 0, v14 = 0, v12 = 0, v10 = 0, v0E = 0;
646
647 int rc, df_tuner;
648 int a, b, c, d;
649 pr_debug("%s %d\n", __FUNCTION__, s->config.d60);
650
651 if (s->config.d60 != 2)
652 goto set_tuner;
653 rc = CorrectSysClockDeviation(s);
654 if (rc < 0)
655 goto set_tuner;
656
657 s->config.d60 = 1;
658 rc = ConfigureMPEGOutput(s, 0);
659 if (rc < 0)
660 goto set_tuner;
661 set_tuner:
662
663 rc = PLL_Set(s, fep, &df_tuner);
664 if (rc < 0) {
665 printk(KERN_ERR "Error in pll_set\n");
666 goto exit_rc;
667 }
668 msleep(200);
669
670 a = rc = RD16(s, 0x2150016);
671 if (rc < 0)
672 goto exit_rc;
673 b = rc = RD16(s, 0x2150010);
674 if (rc < 0)
675 goto exit_rc;
676 c = rc = RD16(s, 0x2150034);
677 if (rc < 0)
678 goto exit_rc;
679 d = rc = RD16(s, 0x2150035);
680 if (rc < 0)
681 goto exit_rc;
682 rc = WR16(s, 0x2150014, c);
683 rc = WR16(s, 0x2150015, d);
684 rc = WR16(s, 0x2150010, 0);
685 rc = WR16(s, 0x2150000, 2);
686 rc = WR16(s, 0x2150036, 0x0fff);
687 rc = WR16(s, 0x2150016, a);
688
689 rc = WR16(s, 0x2150010, 2);
690 rc = WR16(s, 0x2150007, 0);
691 rc = WR16(s, 0x2150000, 1);
692 rc = WR16(s, 0x2110000, 0);
693 rc = WR16(s, 0x0800000, 0);
694 rc = WR16(s, 0x2800000, 0);
695 rc = WR16(s, 0x2110010, 0x664);
696
697 rc = write_fw(s, DRXD_ResetECRAM);
698 rc = WR16(s, 0x2110000, 1);
699
700 rc = write_fw(s, DRXD_InitSC);
701 if (rc < 0)
702 goto exit_rc;
703
704 rc = SetCfgIfAgc(s, &s->config.ifagc);
705 if (rc < 0)
706 goto exit_rc;
707
708 rc = SetCfgRfAgc(s, &s->config.rfagc);
709 if (rc < 0)
710 goto exit_rc;
711
712 if (fep->u.ofdm.transmission_mode != TRANSMISSION_MODE_2K)
713 v22 = 1;
714 switch (fep->u.ofdm.transmission_mode) {
715 case TRANSMISSION_MODE_8K:
716 edi = 1;
717 if (s->chip_rev == DRXD_FW_B1)
718 break;
719
720 rc = WR16(s, 0x2010010, 0);
721 if (rc < 0)
722 break;
723 v1C = 0x63;
724 v1A = 0x53;
725 v18 = 0x43;
726 break;
727 default:
728 edi = 0;
729 if (s->chip_rev == DRXD_FW_B1)
730 break;
731
732 rc = WR16(s, 0x2010010, 1);
733 if (rc < 0)
734 break;
735
736 v1C = 0x61;
737 v1A = 0x47;
738 v18 = 0x41;
739 }
740
741 switch (fep->u.ofdm.guard_interval) {
742 case GUARD_INTERVAL_1_4:
743 edi |= 0x0c;
744 break;
745 case GUARD_INTERVAL_1_8:
746 edi |= 0x08;
747 break;
748 case GUARD_INTERVAL_1_16:
749 edi |= 0x04;
750 break;
751 case GUARD_INTERVAL_1_32:
752 break;
753 default:
754 v22 |= 2;
755 }
756
757 ebx = 0;
758 ebp = 0;
759 v20 = 0;
760 v1E = 0;
761 v16 = 0;
762 v14 = 0;
763 v12 = 0;
764 v10 = 0;
765 v0E = 0;
766
767 switch (fep->u.ofdm.hierarchy_information) {
768 case HIERARCHY_1:
769 edi |= 0x40;
770 if (s->chip_rev == DRXD_FW_B1)
771 break;
772 rc = WR16(s, 0x1c10047, 1);
773 if (rc < 0)
774 goto exit_rc;
775 rc = WR16(s, 0x2010012, 1);
776 if (rc < 0)
777 goto exit_rc;
778 ebx = 0x19f;
779 ebp = 0x1fb;
780 v20 = 0x0c0;
781 v1E = 0x195;
782 v16 = 0x1d6;
783 v14 = 0x1ef;
784 v12 = 4;
785 v10 = 5;
786 v0E = 5;
787 break;
788 case HIERARCHY_2:
789 edi |= 0x80;
790 if (s->chip_rev == DRXD_FW_B1)
791 break;
792 rc = WR16(s, 0x1c10047, 2);
793 if (rc < 0)
794 goto exit_rc;
795 rc = WR16(s, 0x2010012, 2);
796 if (rc < 0)
797 goto exit_rc;
798 ebx = 0x08f;
799 ebp = 0x12f;
800 v20 = 0x0c0;
801 v1E = 0x11e;
802 v16 = 0x1d6;
803 v14 = 0x15e;
804 v12 = 4;
805 v10 = 5;
806 v0E = 5;
807 break;
808 case HIERARCHY_4:
809 edi |= 0xc0;
810 if (s->chip_rev == DRXD_FW_B1)
811 break;
812 rc = WR16(s, 0x1c10047, 3);
813 if (rc < 0)
814 goto exit_rc;
815 rc = WR16(s, 0x2010012, 3);
816 if (rc < 0)
817 goto exit_rc;
818 ebx = 0x14d;
819 ebp = 0x197;
820 v20 = 0x0c0;
821 v1E = 0x1ce;
822 v16 = 0x1d6;
823 v14 = 0x11a;
824 v12 = 4;
825 v10 = 6;
826 v0E = 5;
827 break;
828 default:
829 v22 |= 8;
830 if (s->chip_rev == DRXD_FW_B1)
831 break;
832 rc = WR16(s, 0x1c10047, 0);
833 if (rc < 0)
834 goto exit_rc;
835 rc = WR16(s, 0x2010012, 0);
836 if (rc < 0)
837 goto exit_rc;
838 // QPSK QAM16 QAM64
839 ebx = 0x19f; // 62
840 ebp = 0x1fb; // 15
841 v20 = 0x16a; // 62
842 v1E = 0x195; // 62
843 v16 = 0x1bb; // 15
844 v14 = 0x1ef; // 15
845 v12 = 5; // 16
846 v10 = 5; // 16
847 v0E = 5; // 16
848 }
849
850 switch (fep->u.ofdm.constellation) {
851 default:
852 v22 |= 4;
853 case QPSK:
854 if (s->chip_rev == DRXD_FW_B1)
855 break;
856
857 rc = WR16(s, 0x1c10046, 0);
858 if (rc < 0)
859 goto exit_rc;
860 rc = WR16(s, 0x2010011, 0);
861 if (rc < 0)
862 goto exit_rc;
863 rc = WR16(s, 0x201001a, 0x10);
864 if (rc < 0)
865 goto exit_rc;
866 rc = WR16(s, 0x201001b, 0);
867 if (rc < 0)
868 goto exit_rc;
869 rc = WR16(s, 0x201001c, 0);
870 if (rc < 0)
871 goto exit_rc;
872 rc = WR16(s, 0x1c10062, v20);
873 if (rc < 0)
874 goto exit_rc;
875 rc = WR16(s, 0x1c1002a, v1C);
876 if (rc < 0)
877 goto exit_rc;
878 rc = WR16(s, 0x1c10015, v16);
879 if (rc < 0)
880 goto exit_rc;
881 rc = WR16(s, 0x1c10016, v12);
882 if (rc < 0)
883 goto exit_rc;
884 break;
885 case QAM_16:
886 edi |= 0x10;
887 if (s->chip_rev == DRXD_FW_B1)
888 break;
889
890 rc = WR16(s, 0x1c10046, 1);
891 if (rc < 0)
892 goto exit_rc;
893 rc = WR16(s, 0x2010011, 1);
894 if (rc < 0)
895 goto exit_rc;
896 rc = WR16(s, 0x201001a, 0x10);
897 if (rc < 0)
898 goto exit_rc;
899 rc = WR16(s, 0x201001b, 4);
900 if (rc < 0)
901 goto exit_rc;
902 rc = WR16(s, 0x201001c, 0);
903 if (rc < 0)
904 goto exit_rc;
905 rc = WR16(s, 0x1c10062, v1E);
906 if (rc < 0)
907 goto exit_rc;
908 rc = WR16(s, 0x1c1002a, v1A);
909 if (rc < 0)
910 goto exit_rc;
911 rc = WR16(s, 0x1c10015, v14);
912 if (rc < 0)
913 goto exit_rc;
914 rc = WR16(s, 0x1c10016, v10);
915 if (rc < 0)
916 goto exit_rc;
917 break;
918 case QAM_64:
919 edi |= 0x20;
920 rc = WR16(s, 0x1c10046, 2);
921 if (rc < 0)
922 goto exit_rc;
923 rc = WR16(s, 0x2010011, 2);
924 if (rc < 0)
925 goto exit_rc;
926 rc = WR16(s, 0x201001a, 0x20);
927 if (rc < 0)
928 goto exit_rc;
929 rc = WR16(s, 0x201001b, 8);
930 if (rc < 0)
931 goto exit_rc;
932 rc = WR16(s, 0x201001c, 2);
933 if (rc < 0)
934 goto exit_rc;
935 rc = WR16(s, 0x1c10062, ebx);
936 if (rc < 0)
937 goto exit_rc;
938 rc = WR16(s, 0x1c1002a, v18);
939 if (rc < 0)
940 goto exit_rc;
941 rc = WR16(s, 0x1c10015, ebp);
942 if (rc < 0)
943 goto exit_rc;
944 rc = WR16(s, 0x1c10016, v0E);
945 if (rc < 0)
946 goto exit_rc;
947 break;
948 }
949
950 if (s->config.s20d24 == 1) {
951 rc = WR16(s, 0x2010013, 0);
952 } else {
953 rc = WR16(s, 0x2010013, 1);
954 edi |= 0x1000;
955 }
956
957 switch (fep->u.ofdm.code_rate_HP) {
958 default:
959 v22 |= 0x10;
960 case FEC_1_2:
961 if (s->chip_rev == DRXD_FW_B1)
962 break;
963 rc = WR16(s, 0x2090011, 0);
964 break;
965 case FEC_2_3:
966 edi |= 0x200;
967 if (s->chip_rev == DRXD_FW_B1)
968 break;
969 rc = WR16(s, 0x2090011, 1);
970 break;
971 case FEC_3_4:
972 edi |= 0x400;
973 if (s->chip_rev == DRXD_FW_B1)
974 break;
975 rc = WR16(s, 0x2090011, 2);
976 break;
977 case FEC_5_6: /* 5 */
978 edi |= 0x600;
979 if (s->chip_rev == DRXD_FW_B1)
980 break;
981 rc = WR16(s, 0x2090011, 3);
982 break;
983 case FEC_7_8: /* 7 */
984 edi |= 0x800;
985 if (s->chip_rev == DRXD_FW_B1)
986 break;
987 rc = WR16(s, 0x2090011, 4);
988 break;
989 };
990 if (rc < 0)
991 goto exit_rc;
992
993 switch (fep->u.ofdm.bandwidth) {
994 default:
995 rc = -EINVAL;
996 goto exit_rc;
997 case BANDWIDTH_8_MHZ: /* 0 */
998 case BANDWIDTH_AUTO:
999 rc = WR16(s, 0x0c2003f, 0x32);
1000 s->bandwidth_parm = ebx = 0x8b8249; // 9142857
1001 edx = 0;
1002 break;
1003 case BANDWIDTH_7_MHZ:
1004 rc = WR16(s, 0x0c2003f, 0x3b);
1005 s->bandwidth_parm = ebx = 0x7a1200; // 8000000
1006 edx = 0x4807;
1007 break;
1008 case BANDWIDTH_6_MHZ:
1009 rc = WR16(s, 0x0c2003f, 0x47);
1010 s->bandwidth_parm = ebx = 0x68a1b6; // 6857142
1011 edx = 0x0f07;
1012 break;
1013 };
1014
1015 if (rc < 0)
1016 goto exit_rc;
1017
1018 rc = WR16(s, 0x08200ec, edx);
1019 if (rc < 0)
1020 goto exit_rc;
1021
1022 rc = RD16(s, 0x0820050);
1023 if (rc < 0)
1024 goto exit_rc;
1025 rc = WR16(s, 0x0820050, rc);
1026
1027 {
1028 /* Configure bandwidth specific factor */
1029 ebx = div64_u64(((u64) (s->f_osc) << 21) + (ebx >> 1),
1030 (u64)ebx) - 0x800000;
1031 EXIT_RC(WR16(s, 0x0c50010, ebx & 0xffff));
1032 EXIT_RC(WR16(s, 0x0c50011, ebx >> 16));
1033
1034 /* drx397xD oscillator calibration */
1035 ebx = div64_u64(((u64) (s->config.f_if + df_tuner) << 28) +
1036 (s->f_osc >> 1), (u64)s->f_osc);
1037 }
1038 ebx &= 0xfffffff;
1039 if (fep->inversion == INVERSION_ON)
1040 ebx = 0x10000000 - ebx;
1041
1042 EXIT_RC(WR16(s, 0x0c30010, ebx & 0xffff));
1043 EXIT_RC(WR16(s, 0x0c30011, ebx >> 16));
1044
1045 EXIT_RC(WR16(s, 0x0800000, 1));
1046 EXIT_RC(RD16(s, 0x0800000));
1047
1048
1049 EXIT_RC(SC_WaitForReady(s));
1050 EXIT_RC(WR16(s, 0x0820042, 0));
1051 EXIT_RC(WR16(s, 0x0820041, v22));
1052 EXIT_RC(WR16(s, 0x0820040, edi));
1053 EXIT_RC(SC_SendCommand(s, 3));
1054
1055 rc = RD16(s, 0x0800000);
1056
1057 SC_WaitForReady(s);
1058 WR16(s, 0x0820042, 0);
1059 WR16(s, 0x0820041, 1);
1060 WR16(s, 0x0820040, 1);
1061 SC_SendCommand(s, 1);
1062
1063// rc = WR16(s, 0x2150000, 1);
1064// if (rc < 0) goto exit_rc;
1065
1066 rc = WR16(s, 0x2150000, 2);
1067 rc = WR16(s, 0x2150016, a);
1068 rc = WR16(s, 0x2150010, 4);
1069 rc = WR16(s, 0x2150036, 0);
1070 rc = WR16(s, 0x2150000, 1);
1071 s->config.d60 = 2;
1072 exit_rc:
1073 return rc;
1074}
1075
1076/*******************************************************************************
1077 * DVB interface
1078 ******************************************************************************/
1079
1080static int drx397x_init(struct dvb_frontend *fe)
1081{
1082 struct drx397xD_state *s = fe->demodulator_priv;
1083 int rc;
1084
1085 pr_debug("%s\n", __FUNCTION__);
1086
1087 s->config.rfagc.d00 = 2; /* 0x7c */
1088 s->config.rfagc.w04 = 0;
1089 s->config.rfagc.w06 = 0x3ff;
1090
1091 s->config.ifagc.d00 = 0; /* 0x68 */
1092 s->config.ifagc.w04 = 0;
1093 s->config.ifagc.w06 = 140;
1094 s->config.ifagc.w08 = 0;
1095 s->config.ifagc.w0A = 0x3ff;
1096 s->config.ifagc.w0C = 0x388;
1097
1098 /* for signal strenght calculations */
1099 s->config.ss76 = 820;
1100 s->config.ss78 = 2200;
1101 s->config.ss7A = 150;
1102
1103 /* HI_CfgCommand */
1104 s->config.w50 = 4;
1105 s->config.w52 = 9; // 0xf;
1106
1107 s->config.f_if = 42800000; /* d14: intermediate frequency [Hz] */
1108 s->config.f_osc = 48000; /* s66 : oscillator frequency [kHz] */
1109 s->config.w92 = 12000; // 20000;
1110
1111 s->config.w9C = 0x000e;
1112 s->config.w9E = 0x0000;
1113
1114 /* ConfigureMPEGOutput params */
1115 s->config.wA0 = 4;
1116 s->config.w98 = 1; // 0;
1117 s->config.w9A = 1;
1118
1119 /* get chip revision */
1120 rc = RD16(s, 0x2410019);
1121 if (rc < 0)
1122 return -ENODEV;
1123
1124 if (rc == 0) {
1125 printk(KERN_INFO "%s: chip revision A2\n", mod_name);
1126 rc = drx_load_fw(s, DRXD_FW_A2);
1127 } else {
1128
1129 rc = (rc >> 12) - 3;
1130 switch (rc) {
1131 case 1:
1132 s->flags |= F_SET_0D4h;
1133 case 0:
1134 case 4:
1135 s->flags |= F_SET_0D0h;
1136 break;
1137 case 2:
1138 case 5:
1139 break;
1140 case 3:
1141 s->flags |= F_SET_0D4h;
1142 break;
1143 default:
1144 return -ENODEV;
1145 };
1146 printk(KERN_INFO "%s: chip revision B1.%d\n", mod_name, rc);
1147 rc = drx_load_fw(s, DRXD_FW_B1);
1148 }
1149 if (rc < 0)
1150 goto error;
1151
1152 rc = WR16(s, 0x0420033, 0x3973);
1153 if (rc < 0)
1154 goto error;
1155
1156 rc = HI_Command(s, 2);
1157
1158 msleep(1);
1159
1160 if (s->chip_rev == DRXD_FW_A2) {
1161 rc = WR16(s, 0x043012d, 0x47F);
1162 if (rc < 0)
1163 goto error;
1164 }
1165 rc = WR16_E0(s, 0x0400000, 0);
1166 if (rc < 0)
1167 goto error;
1168
1169 if (s->config.w92 > 20000 || s->config.w92 % 4000) {
1170 printk(KERN_ERR "%s: invalid osc frequency\n", mod_name);
1171 rc = -1;
1172 goto error;
1173 }
1174
1175 rc = WR16(s, 0x2410010, 1);
1176 if (rc < 0)
1177 goto error;
1178 rc = WR16(s, 0x2410011, 0x15);
1179 if (rc < 0)
1180 goto error;
1181 rc = WR16(s, 0x2410012, s->config.w92 / 4000);
1182 if (rc < 0)
1183 goto error;
1184#ifdef ORIG_FW
1185 rc = WR16(s, 0x2410015, 2);
1186 if (rc < 0)
1187 goto error;
1188#endif
1189 rc = WR16(s, 0x2410017, 0x3973);
1190 if (rc < 0)
1191 goto error;
1192
1193 s->f_osc = s->config.f_osc * 1000; /* initial estimator */
1194
1195 s->config.w56 = 1;
1196
1197 rc = HI_CfgCommand(s);
1198 if (rc < 0)
1199 goto error;
1200
1201 rc = write_fw(s, DRXD_InitAtomicRead);
1202 if (rc < 0)
1203 goto error;
1204
1205 if (s->chip_rev == DRXD_FW_A2) {
1206 rc = WR16(s, 0x2150013, 0);
1207 if (rc < 0)
1208 goto error;
1209 }
1210
1211 rc = WR16_E0(s, 0x0400002, 0);
1212 if (rc < 0)
1213 goto error;
1214 rc = WR16(s, 0x0400002, 0);
1215 if (rc < 0)
1216 goto error;
1217
1218 if (s->chip_rev == DRXD_FW_A2) {
1219 rc = write_fw(s, DRXD_ResetCEFR);
1220 if (rc < 0)
1221 goto error;
1222 }
1223 rc = write_fw(s, DRXD_microcode);
1224 if (rc < 0)
1225 goto error;
1226
1227 s->config.w9C = 0x0e;
1228 if (s->flags & F_SET_0D0h) {
1229 s->config.w9C = 0;
1230 rc = RD16(s, 0x0c20010);
1231 if (rc < 0)
1232 goto write_DRXD_InitFE_1;
1233
1234 rc &= ~0x1000;
1235 rc = WR16(s, 0x0c20010, rc);
1236 if (rc < 0)
1237 goto write_DRXD_InitFE_1;
1238
1239 rc = RD16(s, 0x0c20011);
1240 if (rc < 0)
1241 goto write_DRXD_InitFE_1;
1242
1243 rc &= ~0x8;
1244 rc = WR16(s, 0x0c20011, rc);
1245 if (rc < 0)
1246 goto write_DRXD_InitFE_1;
1247
1248 rc = WR16(s, 0x0c20012, 1);
1249 }
1250
1251 write_DRXD_InitFE_1:
1252
1253 rc = write_fw(s, DRXD_InitFE_1);
1254 if (rc < 0)
1255 goto error;
1256
1257 rc = 1;
1258 if (s->chip_rev == DRXD_FW_B1) {
1259 if (s->flags & F_SET_0D0h)
1260 rc = 0;
1261 } else {
1262 if (s->flags & F_SET_0D0h)
1263 rc = 4;
1264 }
1265
1266 rc = WR16(s, 0x0C20012, rc);
1267 if (rc < 0)
1268 goto error;
1269
1270 rc = WR16(s, 0x0C20013, s->config.w9E);
1271 if (rc < 0)
1272 goto error;
1273 rc = WR16(s, 0x0C20015, s->config.w9C);
1274 if (rc < 0)
1275 goto error;
1276
1277 rc = write_fw(s, DRXD_InitFE_2);
1278 if (rc < 0)
1279 goto error;
1280 rc = write_fw(s, DRXD_InitFT);
1281 if (rc < 0)
1282 goto error;
1283 rc = write_fw(s, DRXD_InitCP);
1284 if (rc < 0)
1285 goto error;
1286 rc = write_fw(s, DRXD_InitCE);
1287 if (rc < 0)
1288 goto error;
1289 rc = write_fw(s, DRXD_InitEQ);
1290 if (rc < 0)
1291 goto error;
1292 rc = write_fw(s, DRXD_InitEC);
1293 if (rc < 0)
1294 goto error;
1295 rc = write_fw(s, DRXD_InitSC);
1296 if (rc < 0)
1297 goto error;
1298
1299 rc = SetCfgIfAgc(s, &s->config.ifagc);
1300 if (rc < 0)
1301 goto error;
1302
1303 rc = SetCfgRfAgc(s, &s->config.rfagc);
1304 if (rc < 0)
1305 goto error;
1306
1307 rc = ConfigureMPEGOutput(s, 1);
1308 rc = WR16(s, 0x08201fe, 0x0017);
1309 rc = WR16(s, 0x08201ff, 0x0101);
1310
1311 s->config.d5C = 0;
1312 s->config.d60 = 1;
1313 s->config.d48 = 1;
1314 error:
1315 return rc;
1316}
1317
1318static int drx397x_get_frontend(struct dvb_frontend *fe,
1319 struct dvb_frontend_parameters *params)
1320{
1321 return 0;
1322}
1323
1324static int drx397x_set_frontend(struct dvb_frontend *fe,
1325 struct dvb_frontend_parameters *params)
1326{
1327 struct drx397xD_state *s = fe->demodulator_priv;
1328
1329 s->config.s20d24 = 1; // 0;
1330 return drx_tune(s, params);
1331}
1332
1333static int drx397x_get_tune_settings(struct dvb_frontend *fe,
1334 struct dvb_frontend_tune_settings
1335 *fe_tune_settings)
1336{
1337 fe_tune_settings->min_delay_ms = 10000;
1338 fe_tune_settings->step_size = 0;
1339 fe_tune_settings->max_drift = 0;
1340 return 0;
1341}
1342
1343static int drx397x_read_status(struct dvb_frontend *fe, fe_status_t * status)
1344{
1345 struct drx397xD_state *s = fe->demodulator_priv;
1346 int lockstat;
1347
1348 GetLockStatus(s, &lockstat);
1349 /* TODO */
1350// if (lockstat & 1)
1351// CorrectSysClockDeviation(s);
1352
1353 *status = 0;
1354 if (lockstat & 2) {
1355 CorrectSysClockDeviation(s);
1356 ConfigureMPEGOutput(s, 1);
1357 *status = FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI;
1358 }
1359 if (lockstat & 4) {
1360 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
1361 }
1362
1363 return 0;
1364}
1365
1366static int drx397x_read_ber(struct dvb_frontend *fe, unsigned int *ber)
1367{
1368 *ber = 0;
1369 return 0;
1370}
1371
1372static int drx397x_read_snr(struct dvb_frontend *fe, u16 * snr)
1373{
1374 *snr = 0;
1375 return 0;
1376}
1377
1378static int drx397x_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
1379{
1380 struct drx397xD_state *s = fe->demodulator_priv;
1381 int rc;
1382
1383 if (s->config.ifagc.d00 == 2) {
1384 *strength = 0xffff;
1385 return 0;
1386 }
1387 rc = RD16(s, 0x0c20035);
1388 if (rc < 0) {
1389 *strength = 0;
1390 return 0;
1391 }
1392 rc &= 0x3ff;
1393 /* Signal strength is calculated using the following formula:
1394 *
1395 * a = 2200 * 150 / (2200 + 150);
1396 * a = a * 3300 / (a + 820);
1397 * b = 2200 * 3300 / (2200 + 820);
1398 * c = (((b-a) * rc) >> 10 + a) << 4;
1399 * strength = ~c & 0xffff;
1400 *
1401 * The following does the same but with less rounding errors:
1402 */
1403 *strength = ~(7720 + (rc * 30744 >> 10));
1404 return 0;
1405}
1406
1407static int drx397x_read_ucblocks(struct dvb_frontend *fe,
1408 unsigned int *ucblocks)
1409{
1410 *ucblocks = 0;
1411 return 0;
1412}
1413
1414static int drx397x_sleep(struct dvb_frontend *fe)
1415{
1416 return 0;
1417}
1418
1419static void drx397x_release(struct dvb_frontend *fe)
1420{
1421 struct drx397xD_state *s = fe->demodulator_priv;
1422 printk(KERN_INFO "%s: release demodulator\n", mod_name);
1423 if (s) {
1424 drx_release_fw(s);
1425 kfree(s);
1426 }
1427
1428}
1429
1430static struct dvb_frontend_ops drx397x_ops = {
1431
1432 .info = {
1433 .name = "Micronas DRX397xD DVB-T Frontend",
1434 .type = FE_OFDM,
1435 .frequency_min = 47125000,
1436 .frequency_max = 855250000,
1437 .frequency_stepsize = 166667,
1438 .frequency_tolerance = 0,
1439 .caps = /* 0x0C01B2EAE */
1440 FE_CAN_FEC_1_2 | // = 0x2,
1441 FE_CAN_FEC_2_3 | // = 0x4,
1442 FE_CAN_FEC_3_4 | // = 0x8,
1443 FE_CAN_FEC_5_6 | // = 0x20,
1444 FE_CAN_FEC_7_8 | // = 0x80,
1445 FE_CAN_FEC_AUTO | // = 0x200,
1446 FE_CAN_QPSK | // = 0x400,
1447 FE_CAN_QAM_16 | // = 0x800,
1448 FE_CAN_QAM_64 | // = 0x2000,
1449 FE_CAN_QAM_AUTO | // = 0x10000,
1450 FE_CAN_TRANSMISSION_MODE_AUTO | // = 0x20000,
1451 FE_CAN_GUARD_INTERVAL_AUTO | // = 0x80000,
1452 FE_CAN_HIERARCHY_AUTO | // = 0x100000,
1453 FE_CAN_RECOVER | // = 0x40000000,
1454 FE_CAN_MUTE_TS // = 0x80000000
1455 },
1456
1457 .release = drx397x_release,
1458 .init = drx397x_init,
1459 .sleep = drx397x_sleep,
1460
1461 .set_frontend = drx397x_set_frontend,
1462 .get_tune_settings = drx397x_get_tune_settings,
1463 .get_frontend = drx397x_get_frontend,
1464
1465 .read_status = drx397x_read_status,
1466 .read_snr = drx397x_read_snr,
1467 .read_signal_strength = drx397x_read_signal_strength,
1468 .read_ber = drx397x_read_ber,
1469 .read_ucblocks = drx397x_read_ucblocks,
1470};
1471
1472struct dvb_frontend *drx397xD_attach(const struct drx397xD_config *config,
1473 struct i2c_adapter *i2c)
1474{
1475 struct drx397xD_state *s = NULL;
1476
1477 /* allocate memory for the internal state */
1478 s = kzalloc(sizeof(struct drx397xD_state), GFP_KERNEL);
1479 if (s == NULL)
1480 goto error;
1481
1482 /* setup the state */
1483 s->i2c = i2c;
1484 memcpy(&s->config, config, sizeof(struct drx397xD_config));
1485
1486 /* check if the demod is there */
1487 if (RD16(s, 0x2410019) < 0)
1488 goto error;
1489
1490 /* create dvb_frontend */
1491 memcpy(&s->frontend.ops, &drx397x_ops, sizeof(struct dvb_frontend_ops));
1492 s->frontend.demodulator_priv = s;
1493
1494 return &s->frontend;
1495 error:
1496 kfree(s);
1497 return NULL;
1498}
1499
1500MODULE_DESCRIPTION("Micronas DRX397xD DVB-T Frontend");
1501MODULE_AUTHOR("Henk Vergonet");
1502MODULE_LICENSE("GPL");
1503
1504EXPORT_SYMBOL(drx397xD_attach);
diff --git a/drivers/media/dvb/frontends/drx397xD.h b/drivers/media/dvb/frontends/drx397xD.h
new file mode 100644
index 000000000000..ddc7a07971b7
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx397xD.h
@@ -0,0 +1,130 @@
1/*
2 * Driver for Micronas DVB-T drx397xD demodulator
3 *
4 * Copyright (C) 2007 Henk vergonet <Henk.Vergonet@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
20 */
21
22#ifndef _DRX397XD_H_INCLUDED
23#define _DRX397XD_H_INCLUDED
24
25#include <linux/dvb/frontend.h>
26
27#define DRX_F_STEPSIZE 166667
28#define DRX_F_OFFSET 36000000
29
30#define I2C_ADR_C0(x) \
31( (u32)cpu_to_le32( \
32 (u32)( \
33 (((u32)(x) & (u32)0x000000ffUL) ) | \
34 (((u32)(x) & (u32)0x0000ff00UL) << 16) | \
35 (((u32)(x) & (u32)0x0fff0000UL) >> 8) | \
36 ( (u32)0x00c00000UL) \
37 )) \
38)
39
40#define I2C_ADR_E0(x) \
41( (u32)cpu_to_le32( \
42 (u32)( \
43 (((u32)(x) & (u32)0x000000ffUL) ) | \
44 (((u32)(x) & (u32)0x0000ff00UL) << 16) | \
45 (((u32)(x) & (u32)0x0fff0000UL) >> 8) | \
46 ( (u32)0x00e00000UL) \
47 )) \
48)
49
50struct drx397xD_CfgRfAgc /* 0x7c */
51{
52 int d00; /* 2 */
53 u16 w04;
54 u16 w06;
55};
56
57struct drx397xD_CfgIfAgc /* 0x68 */
58{
59 int d00; /* 0 */
60 u16 w04; /* 0 */
61 u16 w06;
62 u16 w08;
63 u16 w0A;
64 u16 w0C;
65};
66
67struct drx397xD_s20 {
68 int d04;
69 u32 d18;
70 u32 d1C;
71 u32 d20;
72 u32 d14;
73 u32 d24;
74 u32 d0C;
75 u32 d08;
76};
77
78struct drx397xD_config
79{
80 /* demodulator's I2C address */
81 u8 demod_address; /* 0x0f */
82
83 struct drx397xD_CfgIfAgc ifagc; /* 0x68 */
84 struct drx397xD_CfgRfAgc rfagc; /* 0x7c */
85 u32 s20d24;
86
87 /* HI_CfgCommand parameters */
88 u16 w50, w52, /* w54, */ w56;
89
90 int d5C;
91 int d60;
92 int d48;
93 int d28;
94
95 u32 f_if; /* d14: intermediate frequency [Hz] */
96 /* 36000000 on Cinergy 2400i DT */
97 /* 42800000 on Pinnacle Hybrid PRO 330e */
98
99 u16 f_osc; /* s66: 48000 oscillator frequency [kHz] */
100
101 u16 w92; /* 20000 */
102
103 u16 wA0;
104 u16 w98;
105 u16 w9A;
106
107 u16 w9C; /* 0xe0 */
108 u16 w9E; /* 0x00 */
109
110 /* used for signal strength calculations in
111 drx397x_read_signal_strength
112 */
113 u16 ss78; // 2200
114 u16 ss7A; // 150
115 u16 ss76; // 820
116};
117
118#if defined(CONFIG_DVB_DRX397XD) || (defined(CONFIG_DVB_DRX397XD_MODULE) && defined(MODULE))
119extern struct dvb_frontend* drx397xD_attach(const struct drx397xD_config *config,
120 struct i2c_adapter *i2c);
121#else
122static inline struct dvb_frontend* drx397xD_attach(const struct drx397xD_config *config,
123 struct i2c_adapter *i2c)
124{
125 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __FUNCTION__);
126 return NULL;
127}
128#endif /* CONFIG_DVB_DRX397XD */
129
130#endif /* _DRX397XD_H_INCLUDED */
diff --git a/drivers/media/dvb/frontends/drx397xD_fw.h b/drivers/media/dvb/frontends/drx397xD_fw.h
new file mode 100644
index 000000000000..01de02a81cd4
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx397xD_fw.h
@@ -0,0 +1,40 @@
1/*
2 * Firmware definitions for Micronas drx397xD
3 *
4 * Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifdef _FW_ENTRY
21 _FW_ENTRY("drx397xD.A2.fw", DRXD_FW_A2 = 0 ),
22 _FW_ENTRY("drx397xD.B1.fw", DRXD_FW_B1 ),
23#undef _FW_ENTRY
24#endif /* _FW_ENTRY */
25
26#ifdef _BLOB_ENTRY
27 _BLOB_ENTRY("InitAtomicRead", DRXD_InitAtomicRead = 0 ),
28 _BLOB_ENTRY("InitCE", DRXD_InitCE ),
29 _BLOB_ENTRY("InitCP", DRXD_InitCP ),
30 _BLOB_ENTRY("InitEC", DRXD_InitEC ),
31 _BLOB_ENTRY("InitEQ", DRXD_InitEQ ),
32 _BLOB_ENTRY("InitFE_1", DRXD_InitFE_1 ),
33 _BLOB_ENTRY("InitFE_2", DRXD_InitFE_2 ),
34 _BLOB_ENTRY("InitFT", DRXD_InitFT ),
35 _BLOB_ENTRY("InitSC", DRXD_InitSC ),
36 _BLOB_ENTRY("ResetCEFR", DRXD_ResetCEFR ),
37 _BLOB_ENTRY("ResetECRAM", DRXD_ResetECRAM ),
38 _BLOB_ENTRY("microcode", DRXD_microcode ),
39#undef _BLOB_ENTRY
40#endif /* _BLOB_ENTRY */
diff --git a/drivers/media/dvb/frontends/z0194a.h b/drivers/media/dvb/frontends/z0194a.h
new file mode 100644
index 000000000000..d2876d2e1769
--- /dev/null
+++ b/drivers/media/dvb/frontends/z0194a.h
@@ -0,0 +1,97 @@
1/* z0194a.h Sharp z0194a tuner support
2*
3* Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
4*
5* This program is free software; you can redistribute it and/or modify it
6* under the terms of the GNU General Public License as published by the
7* Free Software Foundation, version 2.
8*
9* see Documentation/dvb/README.dvb-usb for more information
10*/
11
12#ifndef Z0194A
13#define Z0194A
14
15static int sharp_z0194a__set_symbol_rate(struct dvb_frontend *fe,
16 u32 srate, u32 ratio)
17{
18 u8 aclk = 0;
19 u8 bclk = 0;
20
21 if (srate < 1500000) {
22 aclk = 0xb7; bclk = 0x47; }
23 else if (srate < 3000000) {
24 aclk = 0xb7; bclk = 0x4b; }
25 else if (srate < 7000000) {
26 aclk = 0xb7; bclk = 0x4f; }
27 else if (srate < 14000000) {
28 aclk = 0xb7; bclk = 0x53; }
29 else if (srate < 30000000) {
30 aclk = 0xb6; bclk = 0x53; }
31 else if (srate < 45000000) {
32 aclk = 0xb4; bclk = 0x51; }
33
34 stv0299_writereg(fe, 0x13, aclk);
35 stv0299_writereg(fe, 0x14, bclk);
36 stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
37 stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
38 stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
39
40 return 0;
41}
42
43static u8 sharp_z0194a__inittab[] = {
44 0x01, 0x15,
45 0x02, 0x00,
46 0x03, 0x00,
47 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
48 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
49 0x06, 0x40, /* DAC not used, set to high impendance mode */
50 0x07, 0x00, /* DAC LSB */
51 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
52 0x09, 0x00, /* FIFO */
53 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
54 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
55 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
56 0x10, 0x3f, /* AGC2 0x3d */
57 0x11, 0x84,
58 0x12, 0xb9,
59 0x15, 0xc9, /* lock detector threshold */
60 0x16, 0x00,
61 0x17, 0x00,
62 0x18, 0x00,
63 0x19, 0x00,
64 0x1a, 0x00,
65 0x1f, 0x50,
66 0x20, 0x00,
67 0x21, 0x00,
68 0x22, 0x00,
69 0x23, 0x00,
70 0x28, 0x00, /* out imp: normal out type: parallel FEC mode:0 */
71 0x29, 0x1e, /* 1/2 threshold */
72 0x2a, 0x14, /* 2/3 threshold */
73 0x2b, 0x0f, /* 3/4 threshold */
74 0x2c, 0x09, /* 5/6 threshold */
75 0x2d, 0x05, /* 7/8 threshold */
76 0x2e, 0x01,
77 0x31, 0x1f, /* test all FECs */
78 0x32, 0x19, /* viterbi and synchro search */
79 0x33, 0xfc, /* rs control */
80 0x34, 0x93, /* error control */
81 0x0f, 0x52,
82 0xff, 0xff
83};
84
85static struct stv0299_config sharp_z0194a_config = {
86 .demod_address = 0x68,
87 .inittab = sharp_z0194a__inittab,
88 .mclk = 88000000UL,
89 .invert = 1,
90 .skip_reinit = 0,
91 .lock_output = STV0299_LOCKOUTPUT_1,
92 .volt13_op0_op1 = STV0299_VOLT13_OP1,
93 .min_delay_ms = 100,
94 .set_symbol_rate = sharp_z0194a__set_symbol_rate,
95};
96
97#endif
diff --git a/drivers/media/dvb/siano/smscoreapi.c b/drivers/media/dvb/siano/smscoreapi.c
index b4b8ed795c95..c5f45fed69dc 100644
--- a/drivers/media/dvb/siano/smscoreapi.c
+++ b/drivers/media/dvb/siano/smscoreapi.c
@@ -110,12 +110,12 @@ struct smscore_registry_entry_t {
110 enum sms_device_type_st type; 110 enum sms_device_type_st type;
111}; 111};
112 112
113struct list_head g_smscore_notifyees; 113static struct list_head g_smscore_notifyees;
114struct list_head g_smscore_devices; 114static struct list_head g_smscore_devices;
115struct mutex g_smscore_deviceslock; 115static struct mutex g_smscore_deviceslock;
116 116
117struct list_head g_smscore_registry; 117static struct list_head g_smscore_registry;
118struct mutex g_smscore_registrylock; 118static struct mutex g_smscore_registrylock;
119 119
120static int default_mode = 4; 120static int default_mode = 4;
121 121
@@ -1187,7 +1187,7 @@ int smsclient_sendrequest(struct smscore_client_t *client,
1187} 1187}
1188 1188
1189 1189
1190int smscore_module_init(void) 1190static int __init smscore_module_init(void)
1191{ 1191{
1192 int rc = 0; 1192 int rc = 0;
1193 1193
@@ -1209,7 +1209,7 @@ int smscore_module_init(void)
1209 return rc; 1209 return rc;
1210} 1210}
1211 1211
1212void smscore_module_exit(void) 1212static void __exit smscore_module_exit(void)
1213{ 1213{
1214 1214
1215 kmutex_lock(&g_smscore_deviceslock); 1215 kmutex_lock(&g_smscore_deviceslock);
diff --git a/drivers/media/dvb/siano/smsdvb.c b/drivers/media/dvb/siano/smsdvb.c
index 6f9c18563867..229274a14110 100644
--- a/drivers/media/dvb/siano/smsdvb.c
+++ b/drivers/media/dvb/siano/smsdvb.c
@@ -27,8 +27,8 @@
27 27
28DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); 28DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
29 29
30struct list_head g_smsdvb_clients; 30static struct list_head g_smsdvb_clients;
31struct mutex g_smsdvb_clientslock; 31static struct mutex g_smsdvb_clientslock;
32 32
33static int smsdvb_onresponse(void *context, struct smscore_buffer_t *cb) 33static int smsdvb_onresponse(void *context, struct smscore_buffer_t *cb)
34{ 34{
diff --git a/drivers/media/dvb/ttpci/Kconfig b/drivers/media/dvb/ttpci/Kconfig
index 87c973ac668b..41b5a988b619 100644
--- a/drivers/media/dvb/ttpci/Kconfig
+++ b/drivers/media/dvb/ttpci/Kconfig
@@ -5,8 +5,6 @@ config TTPCI_EEPROM
5config DVB_AV7110 5config DVB_AV7110
6 tristate "AV7110 cards" 6 tristate "AV7110 cards"
7 depends on DVB_CORE && PCI && I2C 7 depends on DVB_CORE && PCI && I2C
8 depends on HOTPLUG
9 select FW_LOADER if !DVB_AV7110_FIRMWARE
10 select TTPCI_EEPROM 8 select TTPCI_EEPROM
11 select VIDEO_SAA7146_VV 9 select VIDEO_SAA7146_VV
12 depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV 10 depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV
@@ -127,14 +125,12 @@ config DVB_BUDGET_AV
127 depends on DVB_BUDGET_CORE && I2C 125 depends on DVB_BUDGET_CORE && I2C
128 select VIDEO_SAA7146_VV 126 select VIDEO_SAA7146_VV
129 depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV 127 depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV
130 depends on HOTPLUG # dependency of FW_LOADER
131 select DVB_PLL if !DVB_FE_CUSTOMISE 128 select DVB_PLL if !DVB_FE_CUSTOMISE
132 select DVB_STV0299 if !DVB_FE_CUSTOMISE 129 select DVB_STV0299 if !DVB_FE_CUSTOMISE
133 select DVB_TDA1004X if !DVB_FE_CUSTOMISE 130 select DVB_TDA1004X if !DVB_FE_CUSTOMISE
134 select DVB_TDA10021 if !DVB_FE_CUSTOMISE 131 select DVB_TDA10021 if !DVB_FE_CUSTOMISE
135 select DVB_TDA10023 if !DVB_FE_CUSTOMISE 132 select DVB_TDA10023 if !DVB_FE_CUSTOMISE
136 select DVB_TUA6100 if !DVB_FE_CUSTOMISE 133 select DVB_TUA6100 if !DVB_FE_CUSTOMISE
137 select FW_LOADER
138 help 134 help
139 Support for simple SAA7146 based DVB cards 135 Support for simple SAA7146 based DVB cards
140 (so called Budget- or Nova-PCI cards) without onboard 136 (so called Budget- or Nova-PCI cards) without onboard
diff --git a/drivers/media/dvb/ttusb-dec/Kconfig b/drivers/media/dvb/ttusb-dec/Kconfig
index a23cc0aa17d3..d5f48a3102bd 100644
--- a/drivers/media/dvb/ttusb-dec/Kconfig
+++ b/drivers/media/dvb/ttusb-dec/Kconfig
@@ -1,8 +1,6 @@
1config DVB_TTUSB_DEC 1config DVB_TTUSB_DEC
2 tristate "Technotrend/Hauppauge USB DEC devices" 2 tristate "Technotrend/Hauppauge USB DEC devices"
3 depends on DVB_CORE && USB && INPUT 3 depends on DVB_CORE && USB && INPUT
4 depends on HOTPLUG # due to FW_LOADER
5 select FW_LOADER
6 select CRC32 4 select CRC32
7 help 5 help
8 Support for external USB adapters designed by Technotrend and 6 Support for external USB adapters designed by Technotrend and
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 06:12:41 -0500