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-rw-r--r--drivers/media/dvb/frontends/Kconfig21
-rw-r--r--drivers/media/dvb/frontends/Makefile3
-rw-r--r--drivers/media/dvb/frontends/atbm8830.c495
-rw-r--r--drivers/media/dvb/frontends/atbm8830.h76
-rw-r--r--drivers/media/dvb/frontends/atbm8830_priv.h75
-rw-r--r--drivers/media/dvb/frontends/au8522_decoder.c22
-rw-r--r--drivers/media/dvb/frontends/au8522_priv.h2
-rw-r--r--drivers/media/dvb/frontends/dib7000p.c33
-rw-r--r--drivers/media/dvb/frontends/dib7000p.h13
-rw-r--r--drivers/media/dvb/frontends/dib8000.c23
-rw-r--r--drivers/media/dvb/frontends/dib8000.h14
-rw-r--r--drivers/media/dvb/frontends/ds3000.c1367
-rw-r--r--drivers/media/dvb/frontends/ds3000.h45
-rw-r--r--drivers/media/dvb/frontends/ec100.c335
-rw-r--r--drivers/media/dvb/frontends/ec100.h46
-rw-r--r--drivers/media/dvb/frontends/ec100_priv.h39
-rw-r--r--drivers/media/dvb/frontends/s5h1409.c149
-rw-r--r--drivers/media/dvb/frontends/s5h1409.h7
-rw-r--r--drivers/media/dvb/frontends/stb6100_proc.h138
-rw-r--r--drivers/media/dvb/frontends/stv0900.h3
-rw-r--r--drivers/media/dvb/frontends/stv0900_core.c1560
-rw-r--r--drivers/media/dvb/frontends/stv0900_init.h257
-rw-r--r--drivers/media/dvb/frontends/stv0900_priv.h81
-rw-r--r--drivers/media/dvb/frontends/stv0900_reg.h5000
-rw-r--r--drivers/media/dvb/frontends/stv0900_sw.c3171
-rw-r--r--drivers/media/dvb/frontends/stv090x.c242
-rw-r--r--drivers/media/dvb/frontends/stv090x_priv.h3
-rw-r--r--drivers/media/dvb/frontends/stv090x_reg.h70
-rw-r--r--drivers/media/dvb/frontends/stv6110.c13
-rw-r--r--drivers/media/dvb/frontends/stv6110.h1
-rw-r--r--drivers/media/dvb/frontends/stv6110x.c6
31 files changed, 7759 insertions, 5551 deletions
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index d7c4837fa71c..58aac018f109 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -201,6 +201,13 @@ config DVB_SI21XX
201 help 201 help
202 A DVB-S tuner module. Say Y when you want to support this frontend. 202 A DVB-S tuner module. Say Y when you want to support this frontend.
203 203
204config DVB_DS3000
205 tristate "Montage Tehnology DS3000 based"
206 depends on DVB_CORE && I2C
207 default m if DVB_FE_CUSTOMISE
208 help
209 A DVB-S/S2 tuner module. Say Y when you want to support this frontend.
210
204comment "DVB-T (terrestrial) frontends" 211comment "DVB-T (terrestrial) frontends"
205 depends on DVB_CORE 212 depends on DVB_CORE
206 213
@@ -342,6 +349,13 @@ config DVB_AF9013
342 help 349 help
343 Say Y when you want to support this frontend. 350 Say Y when you want to support this frontend.
344 351
352config DVB_EC100
353 tristate "E3C EC100"
354 depends on DVB_CORE && I2C
355 default m if DVB_FE_CUSTOMISE
356 help
357 Say Y when you want to support this frontend.
358
345comment "DVB-C (cable) frontends" 359comment "DVB-C (cable) frontends"
346 depends on DVB_CORE 360 depends on DVB_CORE
347 361
@@ -557,6 +571,13 @@ config DVB_LGS8GXX
557 help 571 help
558 A DMB-TH tuner module. Say Y when you want to support this frontend. 572 A DMB-TH tuner module. Say Y when you want to support this frontend.
559 573
574config DVB_ATBM8830
575 tristate "AltoBeam ATBM8830/8831 DMB-TH demodulator"
576 depends on DVB_CORE && I2C
577 default m if DVB_FE_CUSTOMISE
578 help
579 A DMB-TH tuner module. Say Y when you want to support this frontend.
580
560comment "Tools to develop new frontends" 581comment "Tools to develop new frontends"
561 582
562config DVB_DUMMY_FE 583config DVB_DUMMY_FE
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index 3523767e7a76..823482535d11 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_DVB_TUNER_CX24113) += cx24113.o
64obj-$(CONFIG_DVB_S5H1411) += s5h1411.o 64obj-$(CONFIG_DVB_S5H1411) += s5h1411.o
65obj-$(CONFIG_DVB_LGS8GL5) += lgs8gl5.o 65obj-$(CONFIG_DVB_LGS8GL5) += lgs8gl5.o
66obj-$(CONFIG_DVB_LGS8GXX) += lgs8gxx.o 66obj-$(CONFIG_DVB_LGS8GXX) += lgs8gxx.o
67obj-$(CONFIG_DVB_ATBM8830) += atbm8830.o
67obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o 68obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o
68obj-$(CONFIG_DVB_AF9013) += af9013.o 69obj-$(CONFIG_DVB_AF9013) += af9013.o
69obj-$(CONFIG_DVB_CX24116) += cx24116.o 70obj-$(CONFIG_DVB_CX24116) += cx24116.o
@@ -76,3 +77,5 @@ obj-$(CONFIG_DVB_STV0900) += stv0900.o
76obj-$(CONFIG_DVB_STV090x) += stv090x.o 77obj-$(CONFIG_DVB_STV090x) += stv090x.o
77obj-$(CONFIG_DVB_STV6110x) += stv6110x.o 78obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
78obj-$(CONFIG_DVB_ISL6423) += isl6423.o 79obj-$(CONFIG_DVB_ISL6423) += isl6423.o
80obj-$(CONFIG_DVB_EC100) += ec100.o
81obj-$(CONFIG_DVB_DS3000) += ds3000.o
diff --git a/drivers/media/dvb/frontends/atbm8830.c b/drivers/media/dvb/frontends/atbm8830.c
new file mode 100644
index 000000000000..59881a5944eb
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830.c
@@ -0,0 +1,495 @@
1/*
2 * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
3 * ATBM8830, ATBM8831
4 *
5 * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <asm/div64.h>
23#include "dvb_frontend.h"
24
25#include "atbm8830.h"
26#include "atbm8830_priv.h"
27
28#define dprintk(args...) \
29 do { \
30 if (debug) \
31 printk(KERN_DEBUG "atbm8830: " args); \
32 } while (0)
33
34static int debug;
35
36module_param(debug, int, 0644);
37MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
38
39static int atbm8830_write_reg(struct atbm_state *priv, u16 reg, u8 data)
40{
41 int ret = 0;
42 u8 dev_addr;
43 u8 buf1[] = { reg >> 8, reg & 0xFF };
44 u8 buf2[] = { data };
45 struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
46 struct i2c_msg msg2 = { .flags = 0, .buf = buf2, .len = 1 };
47
48 dev_addr = priv->config->demod_address;
49 msg1.addr = dev_addr;
50 msg2.addr = dev_addr;
51
52 if (debug >= 2)
53 printk(KERN_DEBUG "%s: reg=0x%04X, data=0x%02X\n",
54 __func__, reg, data);
55
56 ret = i2c_transfer(priv->i2c, &msg1, 1);
57 if (ret != 1)
58 return -EIO;
59
60 ret = i2c_transfer(priv->i2c, &msg2, 1);
61 return (ret != 1) ? -EIO : 0;
62}
63
64static int atbm8830_read_reg(struct atbm_state *priv, u16 reg, u8 *p_data)
65{
66 int ret;
67 u8 dev_addr;
68
69 u8 buf1[] = { reg >> 8, reg & 0xFF };
70 u8 buf2[] = { 0 };
71 struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
72 struct i2c_msg msg2 = { .flags = I2C_M_RD, .buf = buf2, .len = 1 };
73
74 dev_addr = priv->config->demod_address;
75 msg1.addr = dev_addr;
76 msg2.addr = dev_addr;
77
78 ret = i2c_transfer(priv->i2c, &msg1, 1);
79 if (ret != 1) {
80 dprintk(KERN_DEBUG "%s: error reg=0x%04x, ret=%i\n",
81 __func__, reg, ret);
82 return -EIO;
83 }
84
85 ret = i2c_transfer(priv->i2c, &msg2, 1);
86 if (ret != 1)
87 return -EIO;
88
89 *p_data = buf2[0];
90 if (debug >= 2)
91 printk(KERN_DEBUG "%s: reg=0x%04X, data=0x%02X\n",
92 __func__, reg, buf2[0]);
93
94 return 0;
95}
96
97/* Lock register latch so that multi-register read is atomic */
98static inline int atbm8830_reglatch_lock(struct atbm_state *priv, int lock)
99{
100 return atbm8830_write_reg(priv, REG_READ_LATCH, lock ? 1 : 0);
101}
102
103static int set_osc_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
104{
105 u32 val;
106 u64 t;
107
108 /* 0x100000 * freq / 30.4MHz */
109 t = (u64)0x100000 * freq;
110 do_div(t, 30400);
111 val = t;
112
113 atbm8830_write_reg(priv, REG_OSC_CLK, val);
114 atbm8830_write_reg(priv, REG_OSC_CLK + 1, val >> 8);
115 atbm8830_write_reg(priv, REG_OSC_CLK + 2, val >> 16);
116
117 return 0;
118}
119
120static int set_if_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
121{
122
123 u32 fs = priv->config->osc_clk_freq;
124 u64 t;
125 u32 val;
126 u8 dat;
127
128 if (freq != 0) {
129 /* 2 * PI * (freq - fs) / fs * (2 ^ 22) */
130 t = (u64) 2 * 31416 * (freq - fs);
131 t <<= 22;
132 do_div(t, fs);
133 do_div(t, 1000);
134 val = t;
135
136 atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 1);
137 atbm8830_write_reg(priv, REG_IF_FREQ, val);
138 atbm8830_write_reg(priv, REG_IF_FREQ+1, val >> 8);
139 atbm8830_write_reg(priv, REG_IF_FREQ+2, val >> 16);
140
141 atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
142 dat &= 0xFC;
143 atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
144 } else {
145 /* Zero IF */
146 atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 0);
147
148 atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
149 dat &= 0xFC;
150 dat |= 0x02;
151 atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
152
153 if (priv->config->zif_swap_iq)
154 atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x03);
155 else
156 atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x01);
157 }
158
159 return 0;
160}
161
162static int is_locked(struct atbm_state *priv, u8 *locked)
163{
164 u8 status;
165
166 atbm8830_read_reg(priv, REG_LOCK_STATUS, &status);
167
168 if (locked != NULL)
169 *locked = (status == 1);
170 return 0;
171}
172
173
174static int set_static_channel_mode(struct atbm_state *priv)
175{
176 int i;
177
178 for (i = 0; i < 5; i++)
179 atbm8830_write_reg(priv, 0x099B + i, 0x08);
180
181 atbm8830_write_reg(priv, 0x095B, 0x7F);
182 atbm8830_write_reg(priv, 0x09CB, 0x01);
183 atbm8830_write_reg(priv, 0x09CC, 0x7F);
184 atbm8830_write_reg(priv, 0x09CD, 0x7F);
185 atbm8830_write_reg(priv, 0x0E01, 0x20);
186
187 /* For single carrier */
188 atbm8830_write_reg(priv, 0x0B03, 0x0A);
189 atbm8830_write_reg(priv, 0x0935, 0x10);
190 atbm8830_write_reg(priv, 0x0936, 0x08);
191 atbm8830_write_reg(priv, 0x093E, 0x08);
192 atbm8830_write_reg(priv, 0x096E, 0x06);
193
194 /* frame_count_max0 */
195 atbm8830_write_reg(priv, 0x0B09, 0x00);
196 /* frame_count_max1 */
197 atbm8830_write_reg(priv, 0x0B0A, 0x08);
198
199 return 0;
200}
201
202static int set_ts_config(struct atbm_state *priv)
203{
204 const struct atbm8830_config *cfg = priv->config;
205
206 /*Set parallel/serial ts mode*/
207 atbm8830_write_reg(priv, REG_TS_SERIAL, cfg->serial_ts ? 1 : 0);
208 atbm8830_write_reg(priv, REG_TS_CLK_MODE, cfg->serial_ts ? 1 : 0);
209 /*Set ts sampling edge*/
210 atbm8830_write_reg(priv, REG_TS_SAMPLE_EDGE,
211 cfg->ts_sampling_edge ? 1 : 0);
212 /*Set ts clock freerun*/
213 atbm8830_write_reg(priv, REG_TS_CLK_FREERUN,
214 cfg->ts_clk_gated ? 0 : 1);
215
216 return 0;
217}
218
219static int atbm8830_init(struct dvb_frontend *fe)
220{
221 struct atbm_state *priv = fe->demodulator_priv;
222 const struct atbm8830_config *cfg = priv->config;
223
224 /*Set oscillator frequency*/
225 set_osc_freq(priv, cfg->osc_clk_freq);
226
227 /*Set IF frequency*/
228 set_if_freq(priv, cfg->if_freq);
229
230
231 /*Set static channel mode*/
232 set_static_channel_mode(priv);
233
234 set_ts_config(priv);
235 /*Turn off DSP reset*/
236 atbm8830_write_reg(priv, 0x000A, 0);
237
238 /*SW version test*/
239 atbm8830_write_reg(priv, 0x020C, 11);
240
241 /* Run */
242 atbm8830_write_reg(priv, REG_DEMOD_RUN, 1);
243
244 return 0;
245}
246
247
248static void atbm8830_release(struct dvb_frontend *fe)
249{
250 struct atbm_state *state = fe->demodulator_priv;
251 dprintk("%s\n", __func__);
252
253 kfree(state);
254}
255
256static int atbm8830_set_fe(struct dvb_frontend *fe,
257 struct dvb_frontend_parameters *fe_params)
258{
259 struct atbm_state *priv = fe->demodulator_priv;
260 int i;
261 u8 locked = 0;
262 dprintk("%s\n", __func__);
263
264 /* set frequency */
265 if (fe->ops.tuner_ops.set_params) {
266 if (fe->ops.i2c_gate_ctrl)
267 fe->ops.i2c_gate_ctrl(fe, 1);
268 fe->ops.tuner_ops.set_params(fe, fe_params);
269 if (fe->ops.i2c_gate_ctrl)
270 fe->ops.i2c_gate_ctrl(fe, 0);
271 }
272
273 /* start auto lock */
274 for (i = 0; i < 10; i++) {
275 mdelay(100);
276 dprintk("Try %d\n", i);
277 is_locked(priv, &locked);
278 if (locked != 0) {
279 dprintk("ATBM8830 locked!\n");
280 break;
281 }
282 }
283
284 return 0;
285}
286
287static int atbm8830_get_fe(struct dvb_frontend *fe,
288 struct dvb_frontend_parameters *fe_params)
289{
290 dprintk("%s\n", __func__);
291
292 /* TODO: get real readings from device */
293 /* inversion status */
294 fe_params->inversion = INVERSION_OFF;
295
296 /* bandwidth */
297 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
298
299 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
300 fe_params->u.ofdm.code_rate_LP = FEC_AUTO;
301
302 fe_params->u.ofdm.constellation = QAM_AUTO;
303
304 /* transmission mode */
305 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
306
307 /* guard interval */
308 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
309
310 /* hierarchy */
311 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
312
313 return 0;
314}
315
316static int atbm8830_get_tune_settings(struct dvb_frontend *fe,
317 struct dvb_frontend_tune_settings *fesettings)
318{
319 fesettings->min_delay_ms = 0;
320 fesettings->step_size = 0;
321 fesettings->max_drift = 0;
322 return 0;
323}
324
325static int atbm8830_read_status(struct dvb_frontend *fe, fe_status_t *fe_status)
326{
327 struct atbm_state *priv = fe->demodulator_priv;
328 u8 locked = 0;
329 u8 agc_locked = 0;
330
331 dprintk("%s\n", __func__);
332 *fe_status = 0;
333
334 is_locked(priv, &locked);
335 if (locked) {
336 *fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
337 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
338 }
339 dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
340
341 atbm8830_read_reg(priv, REG_AGC_LOCK, &agc_locked);
342 dprintk("AGC Lock: %d\n", agc_locked);
343
344 return 0;
345}
346
347static int atbm8830_read_ber(struct dvb_frontend *fe, u32 *ber)
348{
349 struct atbm_state *priv = fe->demodulator_priv;
350 u32 frame_err;
351 u8 t;
352
353 dprintk("%s\n", __func__);
354
355 atbm8830_reglatch_lock(priv, 1);
356
357 atbm8830_read_reg(priv, REG_FRAME_ERR_CNT + 1, &t);
358 frame_err = t & 0x7F;
359 frame_err <<= 8;
360 atbm8830_read_reg(priv, REG_FRAME_ERR_CNT, &t);
361 frame_err |= t;
362
363 atbm8830_reglatch_lock(priv, 0);
364
365 *ber = frame_err * 100 / 32767;
366
367 dprintk("%s: ber=0x%x\n", __func__, *ber);
368 return 0;
369}
370
371static int atbm8830_read_signal_strength(struct dvb_frontend *fe, u16 *signal)
372{
373 struct atbm_state *priv = fe->demodulator_priv;
374 u32 pwm;
375 u8 t;
376
377 dprintk("%s\n", __func__);
378 atbm8830_reglatch_lock(priv, 1);
379
380 atbm8830_read_reg(priv, REG_AGC_PWM_VAL + 1, &t);
381 pwm = t & 0x03;
382 pwm <<= 8;
383 atbm8830_read_reg(priv, REG_AGC_PWM_VAL, &t);
384 pwm |= t;
385
386 atbm8830_reglatch_lock(priv, 0);
387
388 dprintk("AGC PWM = 0x%02X\n", pwm);
389 pwm = 0x400 - pwm;
390
391 *signal = pwm * 0x10000 / 0x400;
392
393 return 0;
394}
395
396static int atbm8830_read_snr(struct dvb_frontend *fe, u16 *snr)
397{
398 dprintk("%s\n", __func__);
399 *snr = 0;
400 return 0;
401}
402
403static int atbm8830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
404{
405 dprintk("%s\n", __func__);
406 *ucblocks = 0;
407 return 0;
408}
409
410static int atbm8830_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
411{
412 struct atbm_state *priv = fe->demodulator_priv;
413
414 return atbm8830_write_reg(priv, REG_I2C_GATE, enable ? 1 : 0);
415}
416
417static struct dvb_frontend_ops atbm8830_ops = {
418 .info = {
419 .name = "AltoBeam ATBM8830/8831 DMB-TH",
420 .type = FE_OFDM,
421 .frequency_min = 474000000,
422 .frequency_max = 858000000,
423 .frequency_stepsize = 10000,
424 .caps =
425 FE_CAN_FEC_AUTO |
426 FE_CAN_QAM_AUTO |
427 FE_CAN_TRANSMISSION_MODE_AUTO |
428 FE_CAN_GUARD_INTERVAL_AUTO
429 },
430
431 .release = atbm8830_release,
432
433 .init = atbm8830_init,
434 .sleep = NULL,
435 .write = NULL,
436 .i2c_gate_ctrl = atbm8830_i2c_gate_ctrl,
437
438 .set_frontend = atbm8830_set_fe,
439 .get_frontend = atbm8830_get_fe,
440 .get_tune_settings = atbm8830_get_tune_settings,
441
442 .read_status = atbm8830_read_status,
443 .read_ber = atbm8830_read_ber,
444 .read_signal_strength = atbm8830_read_signal_strength,
445 .read_snr = atbm8830_read_snr,
446 .read_ucblocks = atbm8830_read_ucblocks,
447};
448
449struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
450 struct i2c_adapter *i2c)
451{
452 struct atbm_state *priv = NULL;
453 u8 data = 0;
454
455 dprintk("%s()\n", __func__);
456
457 if (config == NULL || i2c == NULL)
458 return NULL;
459
460 priv = kzalloc(sizeof(struct atbm_state), GFP_KERNEL);
461 if (priv == NULL)
462 goto error_out;
463
464 priv->config = config;
465 priv->i2c = i2c;
466
467 /* check if the demod is there */
468 if (atbm8830_read_reg(priv, REG_CHIP_ID, &data) != 0) {
469 dprintk("%s atbm8830/8831 not found at i2c addr 0x%02X\n",
470 __func__, priv->config->demod_address);
471 goto error_out;
472 }
473 dprintk("atbm8830 chip id: 0x%02X\n", data);
474
475 memcpy(&priv->frontend.ops, &atbm8830_ops,
476 sizeof(struct dvb_frontend_ops));
477 priv->frontend.demodulator_priv = priv;
478
479 atbm8830_init(&priv->frontend);
480
481 atbm8830_i2c_gate_ctrl(&priv->frontend, 1);
482
483 return &priv->frontend;
484
485error_out:
486 dprintk("%s() error_out\n", __func__);
487 kfree(priv);
488 return NULL;
489
490}
491EXPORT_SYMBOL(atbm8830_attach);
492
493MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver");
494MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
495MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/atbm8830.h b/drivers/media/dvb/frontends/atbm8830.h
new file mode 100644
index 000000000000..e8149f393300
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830.h
@@ -0,0 +1,76 @@
1/*
2 * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
3 * ATBM8830, ATBM8831
4 *
5 * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __ATBM8830_H__
23#define __ATBM8830_H__
24
25#include <linux/dvb/frontend.h>
26#include <linux/i2c.h>
27
28#define ATBM8830_PROD_8830 0
29#define ATBM8830_PROD_8831 1
30
31struct atbm8830_config {
32
33 /* product type */
34 u8 prod;
35
36 /* the demodulator's i2c address */
37 u8 demod_address;
38
39 /* parallel or serial transport stream */
40 u8 serial_ts;
41
42 /* transport stream clock output only when receving valid stream */
43 u8 ts_clk_gated;
44
45 /* Decoder sample TS data at rising edge of clock */
46 u8 ts_sampling_edge;
47
48 /* Oscillator clock frequency */
49 u32 osc_clk_freq; /* in kHz */
50
51 /* IF frequency */
52 u32 if_freq; /* in kHz */
53
54 /* Swap I/Q for zero IF */
55 u8 zif_swap_iq;
56
57 /* Tuner AGC settings */
58 u8 agc_min;
59 u8 agc_max;
60 u8 agc_hold_loop;
61};
62
63#if defined(CONFIG_DVB_ATBM8830) || \
64 (defined(CONFIG_DVB_ATBM8830_MODULE) && defined(MODULE))
65extern struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
66 struct i2c_adapter *i2c);
67#else
68static inline
69struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
70 struct i2c_adapter *i2c) {
71 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
72 return NULL;
73}
74#endif /* CONFIG_DVB_ATBM8830 */
75
76#endif /* __ATBM8830_H__ */
diff --git a/drivers/media/dvb/frontends/atbm8830_priv.h b/drivers/media/dvb/frontends/atbm8830_priv.h
new file mode 100644
index 000000000000..ce960f76092a
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830_priv.h
@@ -0,0 +1,75 @@
1/*
2 * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
3 * ATBM8830, ATBM8831
4 *
5 * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __ATBM8830_PRIV_H
23#define __ATBM8830_PRIV_H
24
25struct atbm_state {
26 struct i2c_adapter *i2c;
27 /* configuration settings */
28 const struct atbm8830_config *config;
29 struct dvb_frontend frontend;
30};
31
32#define REG_CHIP_ID 0x0000
33#define REG_TUNER_BASEBAND 0x0001
34#define REG_DEMOD_RUN 0x0004
35#define REG_DSP_RESET 0x0005
36#define REG_RAM_RESET 0x0006
37#define REG_ADC_RESET 0x0007
38#define REG_TSPORT_RESET 0x0008
39#define REG_BLKERR_POL 0x000C
40#define REG_I2C_GATE 0x0103
41#define REG_TS_SAMPLE_EDGE 0x0301
42#define REG_TS_PKT_LEN_204 0x0302
43#define REG_TS_PKT_LEN_AUTO 0x0303
44#define REG_TS_SERIAL 0x0305
45#define REG_TS_CLK_FREERUN 0x0306
46#define REG_TS_VALID_MODE 0x0307
47#define REG_TS_CLK_MODE 0x030B /* 1 for serial, 0 for parallel */
48
49#define REG_TS_ERRBIT_USE 0x030C
50#define REG_LOCK_STATUS 0x030D
51#define REG_ADC_CONFIG 0x0602
52#define REG_CARRIER_OFFSET 0x0827 /* 0x0827-0x0829 little endian */
53#define REG_DETECTED_PN_MODE 0x082D
54#define REG_READ_LATCH 0x084D
55#define REG_IF_FREQ 0x0A00 /* 0x0A00-0x0A02 little endian */
56#define REG_OSC_CLK 0x0A03 /* 0x0A03-0x0A05 little endian */
57#define REG_BYPASS_CCI 0x0A06
58#define REG_ANALOG_LUMA_DETECTED 0x0A25
59#define REG_ANALOG_AUDIO_DETECTED 0x0A26
60#define REG_ANALOG_CHROMA_DETECTED 0x0A39
61#define REG_FRAME_ERR_CNT 0x0B04
62#define REG_USE_EXT_ADC 0x0C00
63#define REG_SWAP_I_Q 0x0C01
64#define REG_TPS_MANUAL 0x0D01
65#define REG_TPS_CONFIG 0x0D02
66#define REG_BYPASS_DEINTERLEAVER 0x0E00
67#define REG_AGC_TARGET 0x1003 /* 0x1003-0x1005 little endian */
68#define REG_AGC_MIN 0x1020
69#define REG_AGC_MAX 0x1023
70#define REG_AGC_LOCK 0x1027
71#define REG_AGC_PWM_VAL 0x1028 /* 0x1028-0x1029 little endian */
72#define REG_AGC_HOLD_LOOP 0x1031
73
74#endif
75
diff --git a/drivers/media/dvb/frontends/au8522_decoder.c b/drivers/media/dvb/frontends/au8522_decoder.c
index 7c6431fe33e0..2dc2723b724a 100644
--- a/drivers/media/dvb/frontends/au8522_decoder.c
+++ b/drivers/media/dvb/frontends/au8522_decoder.c
@@ -23,7 +23,6 @@
23/* Developer notes: 23/* Developer notes:
24 * 24 *
25 * VBI support is not yet working 25 * VBI support is not yet working
26 * Saturation and hue setting are not yet working
27 * Enough is implemented here for CVBS and S-Video inputs, but the actual 26 * Enough is implemented here for CVBS and S-Video inputs, but the actual
28 * analog demodulator code isn't implemented (not needed for xc5000 since it 27 * analog demodulator code isn't implemented (not needed for xc5000 since it
29 * has its own demodulator and outputs CVBS) 28 * has its own demodulator and outputs CVBS)
@@ -236,8 +235,10 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
236 state->contrast = 0x79; 235 state->contrast = 0x79;
237 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80); 236 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
238 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80); 237 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
238 state->saturation = 0x80;
239 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00); 239 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
240 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00); 240 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
241 state->hue = 0x00;
241 242
242 /* Other decoder registers */ 243 /* Other decoder registers */
243 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00); 244 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
@@ -504,7 +505,19 @@ static int au8522_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
504 ctrl->value); 505 ctrl->value);
505 break; 506 break;
506 case V4L2_CID_SATURATION: 507 case V4L2_CID_SATURATION:
508 state->saturation = ctrl->value;
509 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
510 ctrl->value);
511 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
512 ctrl->value);
513 break;
507 case V4L2_CID_HUE: 514 case V4L2_CID_HUE:
515 state->hue = ctrl->value;
516 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
517 ctrl->value >> 8);
518 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
519 ctrl->value & 0xFF);
520 break;
508 case V4L2_CID_AUDIO_VOLUME: 521 case V4L2_CID_AUDIO_VOLUME:
509 case V4L2_CID_AUDIO_BASS: 522 case V4L2_CID_AUDIO_BASS:
510 case V4L2_CID_AUDIO_TREBLE: 523 case V4L2_CID_AUDIO_TREBLE:
@@ -534,7 +547,11 @@ static int au8522_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
534 ctrl->value = state->contrast; 547 ctrl->value = state->contrast;
535 break; 548 break;
536 case V4L2_CID_SATURATION: 549 case V4L2_CID_SATURATION:
550 ctrl->value = state->saturation;
551 break;
537 case V4L2_CID_HUE: 552 case V4L2_CID_HUE:
553 ctrl->value = state->hue;
554 break;
538 case V4L2_CID_AUDIO_VOLUME: 555 case V4L2_CID_AUDIO_VOLUME:
539 case V4L2_CID_AUDIO_BASS: 556 case V4L2_CID_AUDIO_BASS:
540 case V4L2_CID_AUDIO_TREBLE: 557 case V4L2_CID_AUDIO_TREBLE:
@@ -632,8 +649,9 @@ static int au8522_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
632 case V4L2_CID_BRIGHTNESS: 649 case V4L2_CID_BRIGHTNESS:
633 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); 650 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
634 case V4L2_CID_SATURATION: 651 case V4L2_CID_SATURATION:
652 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
635 case V4L2_CID_HUE: 653 case V4L2_CID_HUE:
636 /* Not yet implemented */ 654 return v4l2_ctrl_query_fill(qc, -32768, 32768, 1, 0);
637 default: 655 default:
638 break; 656 break;
639 } 657 }
diff --git a/drivers/media/dvb/frontends/au8522_priv.h b/drivers/media/dvb/frontends/au8522_priv.h
index f328f2b3ad3d..c74c4e72fe91 100644
--- a/drivers/media/dvb/frontends/au8522_priv.h
+++ b/drivers/media/dvb/frontends/au8522_priv.h
@@ -62,6 +62,8 @@ struct au8522_state {
62 u32 rev; 62 u32 rev;
63 u8 brightness; 63 u8 brightness;
64 u8 contrast; 64 u8 contrast;
65 u8 saturation;
66 s16 hue;
65}; 67};
66 68
67/* These are routines shared by both the VSB/QAM demodulator and the analog 69/* These are routines shared by both the VSB/QAM demodulator and the analog
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index 0781f94e05d2..750ae61a20f4 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -108,7 +108,7 @@ static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
108 108
109 outreg = 0; 109 outreg = 0;
110 fifo_threshold = 1792; 110 fifo_threshold = 1792;
111 smo_mode = (dib7000p_read_word(state, 235) & 0x0010) | (1 << 1); 111 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
112 112
113 dprintk( "setting output mode for demod %p to %d", 113 dprintk( "setting output mode for demod %p to %d",
114 &state->demod, mode); 114 &state->demod, mode);
@@ -162,18 +162,19 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
162 if (state->div_force_off) { 162 if (state->div_force_off) {
163 dprintk( "diversity combination deactivated - forced by COFDM parameters"); 163 dprintk( "diversity combination deactivated - forced by COFDM parameters");
164 onoff = 0; 164 onoff = 0;
165 } 165 dib7000p_write_word(state, 207, 0);
166 } else
167 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
168
166 state->div_state = (u8)onoff; 169 state->div_state = (u8)onoff;
167 170
168 if (onoff) { 171 if (onoff) {
169 dib7000p_write_word(state, 204, 6); 172 dib7000p_write_word(state, 204, 6);
170 dib7000p_write_word(state, 205, 16); 173 dib7000p_write_word(state, 205, 16);
171 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */ 174 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
172 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
173 } else { 175 } else {
174 dib7000p_write_word(state, 204, 1); 176 dib7000p_write_word(state, 204, 1);
175 dib7000p_write_word(state, 205, 0); 177 dib7000p_write_word(state, 205, 0);
176 dib7000p_write_word(state, 207, 0);
177 } 178 }
178 179
179 return 0; 180 return 0;
@@ -1188,7 +1189,7 @@ static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
1188 *stat |= FE_HAS_VITERBI; 1189 *stat |= FE_HAS_VITERBI;
1189 if (lock & 0x0010) 1190 if (lock & 0x0010)
1190 *stat |= FE_HAS_SYNC; 1191 *stat |= FE_HAS_SYNC;
1191 if (lock & 0x0008) 1192 if ((lock & 0x0038) == 0x38)
1192 *stat |= FE_HAS_LOCK; 1193 *stat |= FE_HAS_LOCK;
1193 1194
1194 return 0; 1195 return 0;
@@ -1302,6 +1303,24 @@ struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *demod, enum di
1302} 1303}
1303EXPORT_SYMBOL(dib7000p_get_i2c_master); 1304EXPORT_SYMBOL(dib7000p_get_i2c_master);
1304 1305
1306int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1307{
1308 struct dib7000p_state *state = fe->demodulator_priv;
1309 u16 val = dib7000p_read_word(state, 235) & 0xffef;
1310 val |= (onoff & 0x1) << 4;
1311 dprintk("PID filter enabled %d", onoff);
1312 return dib7000p_write_word(state, 235, val);
1313}
1314EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
1315
1316int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1317{
1318 struct dib7000p_state *state = fe->demodulator_priv;
1319 dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
1320 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
1321}
1322EXPORT_SYMBOL(dib7000p_pid_filter);
1323
1305int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[]) 1324int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
1306{ 1325{
1307 struct dib7000p_state st = { .i2c_adap = i2c }; 1326 struct dib7000p_state st = { .i2c_adap = i2c };
@@ -1314,8 +1333,10 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1314 /* designated i2c address */ 1333 /* designated i2c address */
1315 new_addr = (0x40 + k) << 1; 1334 new_addr = (0x40 + k) << 1;
1316 st.i2c_addr = new_addr; 1335 st.i2c_addr = new_addr;
1336 dib7000p_write_word(&st, 1287, 0x0003); /* sram lead in, rdy */
1317 if (dib7000p_identify(&st) != 0) { 1337 if (dib7000p_identify(&st) != 0) {
1318 st.i2c_addr = default_addr; 1338 st.i2c_addr = default_addr;
1339 dib7000p_write_word(&st, 1287, 0x0003); /* sram lead in, rdy */
1319 if (dib7000p_identify(&st) != 0) { 1340 if (dib7000p_identify(&st) != 0) {
1320 dprintk("DiB7000P #%d: not identified\n", k); 1341 dprintk("DiB7000P #%d: not identified\n", k);
1321 return -EIO; 1342 return -EIO;
@@ -1372,6 +1393,8 @@ struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
1372 demod->demodulator_priv = st; 1393 demod->demodulator_priv = st;
1373 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops)); 1394 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
1374 1395
1396 dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
1397
1375 if (dib7000p_identify(st) != 0) 1398 if (dib7000p_identify(st) != 0)
1376 goto error; 1399 goto error;
1377 1400
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
index 02a4c82f0c70..805dd13a97ee 100644
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ b/drivers/media/dvb/frontends/dib7000p.h
@@ -51,6 +51,8 @@ extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c,
51extern int dib7000p_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val); 51extern int dib7000p_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
52extern int dib7000p_set_wbd_ref(struct dvb_frontend *, u16 value); 52extern int dib7000p_set_wbd_ref(struct dvb_frontend *, u16 value);
53extern int dib7000pc_detection(struct i2c_adapter *i2c_adap); 53extern int dib7000pc_detection(struct i2c_adapter *i2c_adap);
54extern int dib7000p_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
55extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
54#else 56#else
55static inline 57static inline
56struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, 58struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
@@ -95,6 +97,17 @@ static inline int dib7000pc_detection(struct i2c_adapter *i2c_adap)
95 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 97 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
96 return -ENODEV; 98 return -ENODEV;
97} 99}
100static inline int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
101{
102 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
103 return -ENODEV;
104}
105
106static inline int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, uint8_t onoff)
107{
108 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
109 return -ENODEV;
110}
98#endif 111#endif
99 112
100#endif 113#endif
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
index 852c790d09d9..898400d331a3 100644
--- a/drivers/media/dvb/frontends/dib8000.c
+++ b/drivers/media/dvb/frontends/dib8000.c
@@ -954,7 +954,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
954 u8 guard, crate, constellation, timeI; 954 u8 guard, crate, constellation, timeI;
955 u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 }; 955 u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
956 u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled 956 u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled
957 const s16 *ncoeff, *ana_fe; 957 const s16 *ncoeff = NULL, *ana_fe;
958 u16 tmcc_pow = 0; 958 u16 tmcc_pow = 0;
959 u16 coff_pow = 0x2800; 959 u16 coff_pow = 0x2800;
960 u16 init_prbs = 0xfff; 960 u16 init_prbs = 0xfff;
@@ -2121,7 +2121,7 @@ static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
2121 else 2121 else
2122 result -= intlog10(2) * 10 * noise_exp - 100; 2122 result -= intlog10(2) * 10 * noise_exp - 100;
2123 2123
2124 *snr = result / (1 << 24); 2124 *snr = result / ((1 << 24) / 10);
2125 return 0; 2125 return 0;
2126} 2126}
2127 2127
@@ -2195,6 +2195,25 @@ struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000
2195 2195
2196EXPORT_SYMBOL(dib8000_get_i2c_master); 2196EXPORT_SYMBOL(dib8000_get_i2c_master);
2197 2197
2198int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
2199{
2200 struct dib8000_state *st = fe->demodulator_priv;
2201 u16 val = dib8000_read_word(st, 299) & 0xffef;
2202 val |= (onoff & 0x1) << 4;
2203
2204 dprintk("pid filter enabled %d", onoff);
2205 return dib8000_write_word(st, 299, val);
2206}
2207EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
2208
2209int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
2210{
2211 struct dib8000_state *st = fe->demodulator_priv;
2212 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
2213 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
2214}
2215EXPORT_SYMBOL(dib8000_pid_filter);
2216
2198static const struct dvb_frontend_ops dib8000_ops = { 2217static const struct dvb_frontend_ops dib8000_ops = {
2199 .info = { 2218 .info = {
2200 .name = "DiBcom 8000 ISDB-T", 2219 .name = "DiBcom 8000 ISDB-T",
diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h
index a86de340dd54..8c89482b738a 100644
--- a/drivers/media/dvb/frontends/dib8000.h
+++ b/drivers/media/dvb/frontends/dib8000.h
@@ -44,6 +44,8 @@ extern int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u
44 44
45extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val); 45extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
46extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value); 46extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value);
47extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff);
48extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
47#else 49#else
48static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg) 50static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
49{ 51{
@@ -74,6 +76,18 @@ int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
74 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 76 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
75 return -ENODEV; 77 return -ENODEV;
76} 78}
79
80int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
81{
82 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
83 return -ENODEV;
84}
85
86int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
87{
88 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
89 return -ENODEV;
90}
77#endif 91#endif
78 92
79#endif 93#endif
diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c
new file mode 100644
index 000000000000..cff3535566fe
--- /dev/null
+++ b/drivers/media/dvb/frontends/ds3000.c
@@ -0,0 +1,1367 @@
1/*
2 Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
3 Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
4
5 Copyright (C) 2009 TurboSight.com
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/slab.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/firmware.h>
28
29#include "dvb_frontend.h"
30#include "ds3000.h"
31
32static int debug;
33
34#define dprintk(args...) \
35 do { \
36 if (debug) \
37 printk(args); \
38 } while (0)
39
40/* as of March 2009 current DS3000 firmware version is 1.78 */
41/* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
42#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
43
44#define DS3000_SAMPLE_RATE 96000 /* in kHz */
45#define DS3000_XTAL_FREQ 27000 /* in kHz */
46
47/* Register values to initialise the demod in DVB-S mode */
48static u8 ds3000_dvbs_init_tab[] = {
49 0x23, 0x05,
50 0x08, 0x03,
51 0x0c, 0x00,
52 0x21, 0x54,
53 0x25, 0x82,
54 0x27, 0x31,
55 0x30, 0x08,
56 0x31, 0x40,
57 0x32, 0x32,
58 0x33, 0x35,
59 0x35, 0xff,
60 0x3a, 0x00,
61 0x37, 0x10,
62 0x38, 0x10,
63 0x39, 0x02,
64 0x42, 0x60,
65 0x4a, 0x40,
66 0x4b, 0x04,
67 0x4d, 0x91,
68 0x5d, 0xc8,
69 0x50, 0x77,
70 0x51, 0x77,
71 0x52, 0x36,
72 0x53, 0x36,
73 0x56, 0x01,
74 0x63, 0x43,
75 0x64, 0x30,
76 0x65, 0x40,
77 0x68, 0x26,
78 0x69, 0x4c,
79 0x70, 0x20,
80 0x71, 0x70,
81 0x72, 0x04,
82 0x73, 0x00,
83 0x70, 0x40,
84 0x71, 0x70,
85 0x72, 0x04,
86 0x73, 0x00,
87 0x70, 0x60,
88 0x71, 0x70,
89 0x72, 0x04,
90 0x73, 0x00,
91 0x70, 0x80,
92 0x71, 0x70,
93 0x72, 0x04,
94 0x73, 0x00,
95 0x70, 0xa0,
96 0x71, 0x70,
97 0x72, 0x04,
98 0x73, 0x00,
99 0x70, 0x1f,
100 0x76, 0x00,
101 0x77, 0xd1,
102 0x78, 0x0c,
103 0x79, 0x80,
104 0x7f, 0x04,
105 0x7c, 0x00,
106 0x80, 0x86,
107 0x81, 0xa6,
108 0x85, 0x04,
109 0xcd, 0xf4,
110 0x90, 0x33,
111 0xa0, 0x44,
112 0xc0, 0x18,
113 0xc3, 0x10,
114 0xc4, 0x08,
115 0xc5, 0x80,
116 0xc6, 0x80,
117 0xc7, 0x0a,
118 0xc8, 0x1a,
119 0xc9, 0x80,
120 0xfe, 0x92,
121 0xe0, 0xf8,
122 0xe6, 0x8b,
123 0xd0, 0x40,
124 0xf8, 0x20,
125 0xfa, 0x0f,
126 0xfd, 0x20,
127 0xad, 0x20,
128 0xae, 0x07,
129 0xb8, 0x00,
130};
131
132/* Register values to initialise the demod in DVB-S2 mode */
133static u8 ds3000_dvbs2_init_tab[] = {
134 0x23, 0x0f,
135 0x08, 0x07,
136 0x0c, 0x00,
137 0x21, 0x54,
138 0x25, 0x82,
139 0x27, 0x31,
140 0x30, 0x08,
141 0x31, 0x32,
142 0x32, 0x32,
143 0x33, 0x35,
144 0x35, 0xff,
145 0x3a, 0x00,
146 0x37, 0x10,
147 0x38, 0x10,
148 0x39, 0x02,
149 0x42, 0x60,
150 0x4a, 0x80,
151 0x4b, 0x04,
152 0x4d, 0x81,
153 0x5d, 0x88,
154 0x50, 0x36,
155 0x51, 0x36,
156 0x52, 0x36,
157 0x53, 0x36,
158 0x63, 0x60,
159 0x64, 0x10,
160 0x65, 0x10,
161 0x68, 0x04,
162 0x69, 0x29,
163 0x70, 0x20,
164 0x71, 0x70,
165 0x72, 0x04,
166 0x73, 0x00,
167 0x70, 0x40,
168 0x71, 0x70,
169 0x72, 0x04,
170 0x73, 0x00,
171 0x70, 0x60,
172 0x71, 0x70,
173 0x72, 0x04,
174 0x73, 0x00,
175 0x70, 0x80,
176 0x71, 0x70,
177 0x72, 0x04,
178 0x73, 0x00,
179 0x70, 0xa0,
180 0x71, 0x70,
181 0x72, 0x04,
182 0x73, 0x00,
183 0x70, 0x1f,
184 0xa0, 0x44,
185 0xc0, 0x08,
186 0xc1, 0x10,
187 0xc2, 0x08,
188 0xc3, 0x10,
189 0xc4, 0x08,
190 0xc5, 0xf0,
191 0xc6, 0xf0,
192 0xc7, 0x0a,
193 0xc8, 0x1a,
194 0xc9, 0x80,
195 0xca, 0x23,
196 0xcb, 0x24,
197 0xce, 0x74,
198 0x90, 0x03,
199 0x76, 0x80,
200 0x77, 0x42,
201 0x78, 0x0a,
202 0x79, 0x80,
203 0xad, 0x40,
204 0xae, 0x07,
205 0x7f, 0xd4,
206 0x7c, 0x00,
207 0x80, 0xa8,
208 0x81, 0xda,
209 0x7c, 0x01,
210 0x80, 0xda,
211 0x81, 0xec,
212 0x7c, 0x02,
213 0x80, 0xca,
214 0x81, 0xeb,
215 0x7c, 0x03,
216 0x80, 0xba,
217 0x81, 0xdb,
218 0x85, 0x08,
219 0x86, 0x00,
220 0x87, 0x02,
221 0x89, 0x80,
222 0x8b, 0x44,
223 0x8c, 0xaa,
224 0x8a, 0x10,
225 0xba, 0x00,
226 0xf5, 0x04,
227 0xfe, 0x44,
228 0xd2, 0x32,
229 0xb8, 0x00,
230};
231
232/* DS3000 doesn't need some parameters as input and auto-detects them */
233/* save input from the application of those parameters */
234struct ds3000_tuning {
235 u32 frequency;
236 u32 symbol_rate;
237 fe_spectral_inversion_t inversion;
238 enum fe_code_rate fec;
239
240 /* input values */
241 u8 inversion_val;
242 fe_modulation_t delivery;
243 u8 rolloff;
244};
245
246struct ds3000_state {
247 struct i2c_adapter *i2c;
248 const struct ds3000_config *config;
249
250 struct dvb_frontend frontend;
251
252 struct ds3000_tuning dcur;
253 struct ds3000_tuning dnxt;
254
255 u8 skip_fw_load;
256
257 /* previous uncorrected block counter for DVB-S2 */
258 u16 prevUCBS2;
259};
260
261static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
262{
263 u8 buf[] = { reg, data };
264 struct i2c_msg msg = { .addr = state->config->demod_address,
265 .flags = 0, .buf = buf, .len = 2 };
266 int err;
267
268 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
269
270 err = i2c_transfer(state->i2c, &msg, 1);
271 if (err != 1) {
272 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
273 " value == 0x%02x)\n", __func__, err, reg, data);
274 return -EREMOTEIO;
275 }
276
277 return 0;
278}
279
280static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
281{
282 u8 buf[] = { reg, data };
283 struct i2c_msg msg = { .addr = 0x60,
284 .flags = 0, .buf = buf, .len = 2 };
285 int err;
286
287 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
288
289 ds3000_writereg(state, 0x03, 0x11);
290 err = i2c_transfer(state->i2c, &msg, 1);
291 if (err != 1) {
292 printk("%s: writereg error(err == %i, reg == 0x%02x,"
293 " value == 0x%02x)\n", __func__, err, reg, data);
294 return -EREMOTEIO;
295 }
296
297 return 0;
298}
299
300/* I2C write for 8k firmware load */
301static int ds3000_writeFW(struct ds3000_state *state, int reg,
302 const u8 *data, u16 len)
303{
304 int i, ret = -EREMOTEIO;
305 struct i2c_msg msg;
306 u8 *buf;
307
308 buf = kmalloc(3, GFP_KERNEL);
309 if (buf == NULL) {
310 printk(KERN_ERR "Unable to kmalloc\n");
311 ret = -ENOMEM;
312 goto error;
313 }
314
315 *(buf) = reg;
316
317 msg.addr = state->config->demod_address;
318 msg.flags = 0;
319 msg.buf = buf;
320 msg.len = 3;
321
322 for (i = 0; i < len; i += 2) {
323 memcpy(buf + 1, data + i, 2);
324
325 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
326
327 ret = i2c_transfer(state->i2c, &msg, 1);
328 if (ret != 1) {
329 printk(KERN_ERR "%s: write error(err == %i, "
330 "reg == 0x%02x\n", __func__, ret, reg);
331 ret = -EREMOTEIO;
332 }
333 }
334
335error:
336 kfree(buf);
337
338 return ret;
339}
340
341static int ds3000_readreg(struct ds3000_state *state, u8 reg)
342{
343 int ret;
344 u8 b0[] = { reg };
345 u8 b1[] = { 0 };
346 struct i2c_msg msg[] = {
347 {
348 .addr = state->config->demod_address,
349 .flags = 0,
350 .buf = b0,
351 .len = 1
352 }, {
353 .addr = state->config->demod_address,
354 .flags = I2C_M_RD,
355 .buf = b1,
356 .len = 1
357 }
358 };
359
360 ret = i2c_transfer(state->i2c, msg, 2);
361
362 if (ret != 2) {
363 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
364 return ret;
365 }
366
367 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
368
369 return b1[0];
370}
371
372static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
373{
374 int ret;
375 u8 b0[] = { reg };
376 u8 b1[] = { 0 };
377 struct i2c_msg msg[] = {
378 {
379 .addr = 0x60,
380 .flags = 0,
381 .buf = b0,
382 .len = 1
383 }, {
384 .addr = 0x60,
385 .flags = I2C_M_RD,
386 .buf = b1,
387 .len = 1
388 }
389 };
390
391 ds3000_writereg(state, 0x03, 0x12);
392 ret = i2c_transfer(state->i2c, msg, 2);
393
394 if (ret != 2) {
395 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
396 return ret;
397 }
398
399 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
400
401 return b1[0];
402}
403
404static int ds3000_set_inversion(struct ds3000_state *state,
405 fe_spectral_inversion_t inversion)
406{
407 dprintk("%s(%d)\n", __func__, inversion);
408
409 switch (inversion) {
410 case INVERSION_OFF:
411 case INVERSION_ON:
412 case INVERSION_AUTO:
413 break;
414 default:
415 return -EINVAL;
416 }
417
418 state->dnxt.inversion = inversion;
419
420 return 0;
421}
422
423static int ds3000_set_symbolrate(struct ds3000_state *state, u32 rate)
424{
425 int ret = 0;
426
427 dprintk("%s()\n", __func__);
428
429 dprintk("%s() symbol_rate = %d\n", __func__, state->dnxt.symbol_rate);
430
431 /* check if symbol rate is within limits */
432 if ((state->dnxt.symbol_rate >
433 state->frontend.ops.info.symbol_rate_max) ||
434 (state->dnxt.symbol_rate <
435 state->frontend.ops.info.symbol_rate_min))
436 ret = -EOPNOTSUPP;
437
438 state->dnxt.symbol_rate = rate;
439
440 return ret;
441}
442
443static int ds3000_load_firmware(struct dvb_frontend *fe,
444 const struct firmware *fw);
445
446static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
447{
448 struct ds3000_state *state = fe->demodulator_priv;
449 const struct firmware *fw;
450 int ret = 0;
451
452 dprintk("%s()\n", __func__);
453
454 if (ds3000_readreg(state, 0xb2) <= 0)
455 return ret;
456
457 if (state->skip_fw_load)
458 return 0;
459 /* Load firmware */
460 /* request the firmware, this will block until someone uploads it */
461 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
462 DS3000_DEFAULT_FIRMWARE);
463 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
464 state->i2c->dev.parent);
465 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
466 if (ret) {
467 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
468 "found?)\n", __func__);
469 return ret;
470 }
471
472 /* Make sure we don't recurse back through here during loading */
473 state->skip_fw_load = 1;
474
475 ret = ds3000_load_firmware(fe, fw);
476 if (ret)
477 printk("%s: Writing firmware to device failed\n", __func__);
478
479 release_firmware(fw);
480
481 dprintk("%s: Firmware upload %s\n", __func__,
482 ret == 0 ? "complete" : "failed");
483
484 /* Ensure firmware is always loaded if required */
485 state->skip_fw_load = 0;
486
487 return ret;
488}
489
490static int ds3000_load_firmware(struct dvb_frontend *fe,
491 const struct firmware *fw)
492{
493 struct ds3000_state *state = fe->demodulator_priv;
494
495 dprintk("%s\n", __func__);
496 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
497 fw->size,
498 fw->data[0],
499 fw->data[1],
500 fw->data[fw->size - 2],
501 fw->data[fw->size - 1]);
502
503 /* Begin the firmware load process */
504 ds3000_writereg(state, 0xb2, 0x01);
505 /* write the entire firmware */
506 ds3000_writeFW(state, 0xb0, fw->data, fw->size);
507 ds3000_writereg(state, 0xb2, 0x00);
508
509 return 0;
510}
511
512static void ds3000_dump_registers(struct dvb_frontend *fe)
513{
514 struct ds3000_state *state = fe->demodulator_priv;
515 int x, y, reg = 0, val;
516
517 for (y = 0; y < 16; y++) {
518 dprintk("%s: %02x: ", __func__, y);
519 for (x = 0; x < 16; x++) {
520 reg = (y << 4) + x;
521 val = ds3000_readreg(state, reg);
522 if (x != 15)
523 dprintk("%02x ", val);
524 else
525 dprintk("%02x\n", val);
526 }
527 }
528 dprintk("%s: -- DS3000 DUMP DONE --\n", __func__);
529}
530
531static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
532{
533 struct ds3000_state *state = fe->demodulator_priv;
534 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
535 int lock;
536
537 *status = 0;
538
539 switch (c->delivery_system) {
540 case SYS_DVBS:
541 lock = ds3000_readreg(state, 0xd1);
542 if ((lock & 0x07) == 0x07)
543 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
544 FE_HAS_VITERBI | FE_HAS_SYNC |
545 FE_HAS_LOCK;
546
547 break;
548 case SYS_DVBS2:
549 lock = ds3000_readreg(state, 0x0d);
550 if ((lock & 0x8f) == 0x8f)
551 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
552 FE_HAS_VITERBI | FE_HAS_SYNC |
553 FE_HAS_LOCK;
554
555 break;
556 default:
557 return 1;
558 }
559
560 dprintk("%s: status = 0x%02x\n", __func__, lock);
561
562 return 0;
563}
564
565#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
566static int ds3000_is_tuned(struct dvb_frontend *fe)
567{
568 fe_status_t tunerstat;
569
570 ds3000_read_status(fe, &tunerstat);
571
572 return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
573}
574
575/* read DS3000 BER value */
576static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
577{
578 struct ds3000_state *state = fe->demodulator_priv;
579 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
580 u8 data;
581 u32 ber_reading, lpdc_frames;
582
583 dprintk("%s()\n", __func__);
584
585 switch (c->delivery_system) {
586 case SYS_DVBS:
587 /* set the number of bytes checked during
588 BER estimation */
589 ds3000_writereg(state, 0xf9, 0x04);
590 /* read BER estimation status */
591 data = ds3000_readreg(state, 0xf8);
592 /* check if BER estimation is ready */
593 if ((data & 0x10) == 0) {
594 /* this is the number of error bits,
595 to calculate the bit error rate
596 divide to 8388608 */
597 *ber = (ds3000_readreg(state, 0xf7) << 8) |
598 ds3000_readreg(state, 0xf6);
599 /* start counting error bits */
600 /* need to be set twice
601 otherwise it fails sometimes */
602 data |= 0x10;
603 ds3000_writereg(state, 0xf8, data);
604 ds3000_writereg(state, 0xf8, data);
605 } else
606 /* used to indicate that BER estimation
607 is not ready, i.e. BER is unknown */
608 *ber = 0xffffffff;
609 break;
610 case SYS_DVBS2:
611 /* read the number of LPDC decoded frames */
612 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
613 (ds3000_readreg(state, 0xd6) << 8) |
614 ds3000_readreg(state, 0xd5);
615 /* read the number of packets with bad CRC */
616 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
617 ds3000_readreg(state, 0xf7);
618 if (lpdc_frames > 750) {
619 /* clear LPDC frame counters */
620 ds3000_writereg(state, 0xd1, 0x01);
621 /* clear bad packets counter */
622 ds3000_writereg(state, 0xf9, 0x01);
623 /* enable bad packets counter */
624 ds3000_writereg(state, 0xf9, 0x00);
625 /* enable LPDC frame counters */
626 ds3000_writereg(state, 0xd1, 0x00);
627 *ber = ber_reading;
628 } else
629 /* used to indicate that BER estimation is not ready,
630 i.e. BER is unknown */
631 *ber = 0xffffffff;
632 break;
633 default:
634 return 1;
635 }
636
637 return 0;
638}
639
640/* read TS2020 signal strength */
641static int ds3000_read_signal_strength(struct dvb_frontend *fe,
642 u16 *signal_strength)
643{
644 struct ds3000_state *state = fe->demodulator_priv;
645 u16 sig_reading, sig_strength;
646 u8 rfgain, bbgain;
647
648 dprintk("%s()\n", __func__);
649
650 rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
651 bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
652
653 if (rfgain > 15)
654 rfgain = 15;
655 if (bbgain > 13)
656 bbgain = 13;
657
658 sig_reading = rfgain * 2 + bbgain * 3;
659
660 sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
661
662 /* cook the value to be suitable for szap-s2 human readable output */
663 *signal_strength = sig_strength * 1000;
664
665 dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
666 sig_reading, *signal_strength);
667
668 return 0;
669}
670
671/* calculate DS3000 snr value in dB */
672static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
673{
674 struct ds3000_state *state = fe->demodulator_priv;
675 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
676 u8 snr_reading, snr_value;
677 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
678 static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
679 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
680 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
681 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
682 };
683 static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
684 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
685 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
686 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
687 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
688 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
689 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
690 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
691 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
692 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
693 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
694 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
695 0x49e9, 0x4a20, 0x4a57
696 };
697
698 dprintk("%s()\n", __func__);
699
700 switch (c->delivery_system) {
701 case SYS_DVBS:
702 snr_reading = ds3000_readreg(state, 0xff);
703 snr_reading /= 8;
704 if (snr_reading == 0)
705 *snr = 0x0000;
706 else {
707 if (snr_reading > 20)
708 snr_reading = 20;
709 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
710 /* cook the value to be suitable for szap-s2
711 human readable output */
712 *snr = snr_value * 8 * 655;
713 }
714 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
715 snr_reading, *snr);
716 break;
717 case SYS_DVBS2:
718 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
719 (ds3000_readreg(state, 0x8d) << 4);
720 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
721 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
722 if (dvbs2_signal_reading == 0) {
723 *snr = 0x0000;
724 return 0;
725 }
726 if (dvbs2_noise_reading == 0) {
727 snr_value = 0x0013;
728 /* cook the value to be suitable for szap-s2
729 human readable output */
730 *snr = 0xffff;
731 return 0;
732 }
733 if (tmp > dvbs2_noise_reading) {
734 snr_reading = tmp / dvbs2_noise_reading;
735 if (snr_reading > 80)
736 snr_reading = 80;
737 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
738 /* cook the value to be suitable for szap-s2
739 human readable output */
740 *snr = snr_value * 5 * 655;
741 } else {
742 snr_reading = dvbs2_noise_reading / tmp;
743 if (snr_reading > 80)
744 snr_reading = 80;
745 *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
746 }
747 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
748 snr_reading, *snr);
749 break;
750 default:
751 return 1;
752 }
753
754 return 0;
755}
756
757/* read DS3000 uncorrected blocks */
758static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
759{
760 struct ds3000_state *state = fe->demodulator_priv;
761 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
762 u8 data;
763 u16 _ucblocks;
764
765 dprintk("%s()\n", __func__);
766
767 switch (c->delivery_system) {
768 case SYS_DVBS:
769 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
770 ds3000_readreg(state, 0xf4);
771 data = ds3000_readreg(state, 0xf8);
772 /* clear packet counters */
773 data &= ~0x20;
774 ds3000_writereg(state, 0xf8, data);
775 /* enable packet counters */
776 data |= 0x20;
777 ds3000_writereg(state, 0xf8, data);
778 break;
779 case SYS_DVBS2:
780 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
781 ds3000_readreg(state, 0xe1);
782 if (_ucblocks > state->prevUCBS2)
783 *ucblocks = _ucblocks - state->prevUCBS2;
784 else
785 *ucblocks = state->prevUCBS2 - _ucblocks;
786 state->prevUCBS2 = _ucblocks;
787 break;
788 default:
789 return 1;
790 }
791
792 return 0;
793}
794
795/* Overwrite the current tuning params, we are about to tune */
796static void ds3000_clone_params(struct dvb_frontend *fe)
797{
798 struct ds3000_state *state = fe->demodulator_priv;
799 memcpy(&state->dcur, &state->dnxt, sizeof(state->dcur));
800}
801
802static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
803{
804 struct ds3000_state *state = fe->demodulator_priv;
805 u8 data;
806
807 dprintk("%s(%d)\n", __func__, tone);
808 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
809 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
810 return -EINVAL;
811 }
812
813 data = ds3000_readreg(state, 0xa2);
814 data &= ~0xc0;
815 ds3000_writereg(state, 0xa2, data);
816
817 switch (tone) {
818 case SEC_TONE_ON:
819 dprintk("%s: setting tone on\n", __func__);
820 data = ds3000_readreg(state, 0xa1);
821 data &= ~0x43;
822 data |= 0x04;
823 ds3000_writereg(state, 0xa1, data);
824 break;
825 case SEC_TONE_OFF:
826 dprintk("%s: setting tone off\n", __func__);
827 data = ds3000_readreg(state, 0xa2);
828 data |= 0x80;
829 ds3000_writereg(state, 0xa2, data);
830 break;
831 }
832
833 return 0;
834}
835
836static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
837 struct dvb_diseqc_master_cmd *d)
838{
839 struct ds3000_state *state = fe->demodulator_priv;
840 int i;
841 u8 data;
842
843 /* Dump DiSEqC message */
844 dprintk("%s(", __func__);
845 for (i = 0 ; i < d->msg_len;) {
846 dprintk("0x%02x", d->msg[i]);
847 if (++i < d->msg_len)
848 dprintk(", ");
849 }
850
851 /* enable DiSEqC message send pin */
852 data = ds3000_readreg(state, 0xa2);
853 data &= ~0xc0;
854 ds3000_writereg(state, 0xa2, data);
855
856 /* DiSEqC message */
857 for (i = 0; i < d->msg_len; i++)
858 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
859
860 data = ds3000_readreg(state, 0xa1);
861 /* clear DiSEqC message length and status,
862 enable DiSEqC message send */
863 data &= ~0xf8;
864 /* set DiSEqC mode, modulation active during 33 pulses,
865 set DiSEqC message length */
866 data |= ((d->msg_len - 1) << 3) | 0x07;
867 ds3000_writereg(state, 0xa1, data);
868
869 /* wait up to 150ms for DiSEqC transmission to complete */
870 for (i = 0; i < 15; i++) {
871 data = ds3000_readreg(state, 0xa1);
872 if ((data & 0x40) == 0)
873 break;
874 msleep(10);
875 }
876
877 /* DiSEqC timeout after 150ms */
878 if (i == 15) {
879 data = ds3000_readreg(state, 0xa1);
880 data &= ~0x80;
881 data |= 0x40;
882 ds3000_writereg(state, 0xa1, data);
883
884 data = ds3000_readreg(state, 0xa2);
885 data &= ~0xc0;
886 data |= 0x80;
887 ds3000_writereg(state, 0xa2, data);
888
889 return 1;
890 }
891
892 data = ds3000_readreg(state, 0xa2);
893 data &= ~0xc0;
894 data |= 0x80;
895 ds3000_writereg(state, 0xa2, data);
896
897 return 0;
898}
899
900/* Send DiSEqC burst */
901static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
902 fe_sec_mini_cmd_t burst)
903{
904 struct ds3000_state *state = fe->demodulator_priv;
905 int i;
906 u8 data;
907
908 dprintk("%s()\n", __func__);
909
910 data = ds3000_readreg(state, 0xa2);
911 data &= ~0xc0;
912 ds3000_writereg(state, 0xa2, data);
913
914 /* DiSEqC burst */
915 if (burst == SEC_MINI_A)
916 /* Unmodulated tone burst */
917 ds3000_writereg(state, 0xa1, 0x02);
918 else if (burst == SEC_MINI_B)
919 /* Modulated tone burst */
920 ds3000_writereg(state, 0xa1, 0x01);
921 else
922 return -EINVAL;
923
924 msleep(13);
925 for (i = 0; i < 5; i++) {
926 data = ds3000_readreg(state, 0xa1);
927 if ((data & 0x40) == 0)
928 break;
929 msleep(1);
930 }
931
932 if (i == 5) {
933 data = ds3000_readreg(state, 0xa1);
934 data &= ~0x80;
935 data |= 0x40;
936 ds3000_writereg(state, 0xa1, data);
937
938 data = ds3000_readreg(state, 0xa2);
939 data &= ~0xc0;
940 data |= 0x80;
941 ds3000_writereg(state, 0xa2, data);
942
943 return 1;
944 }
945
946 data = ds3000_readreg(state, 0xa2);
947 data &= ~0xc0;
948 data |= 0x80;
949 ds3000_writereg(state, 0xa2, data);
950
951 return 0;
952}
953
954static void ds3000_release(struct dvb_frontend *fe)
955{
956 struct ds3000_state *state = fe->demodulator_priv;
957 dprintk("%s\n", __func__);
958 kfree(state);
959}
960
961static struct dvb_frontend_ops ds3000_ops;
962
963struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
964 struct i2c_adapter *i2c)
965{
966 struct ds3000_state *state = NULL;
967 int ret;
968
969 dprintk("%s\n", __func__);
970
971 /* allocate memory for the internal state */
972 state = kmalloc(sizeof(struct ds3000_state), GFP_KERNEL);
973 if (state == NULL) {
974 printk(KERN_ERR "Unable to kmalloc\n");
975 goto error2;
976 }
977
978 /* setup the state */
979 memset(state, 0, sizeof(struct ds3000_state));
980
981 state->config = config;
982 state->i2c = i2c;
983 state->prevUCBS2 = 0;
984
985 /* check if the demod is present */
986 ret = ds3000_readreg(state, 0x00) & 0xfe;
987 if (ret != 0xe0) {
988 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
989 goto error3;
990 }
991
992 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
993 ds3000_readreg(state, 0x02),
994 ds3000_readreg(state, 0x01));
995
996 memcpy(&state->frontend.ops, &ds3000_ops,
997 sizeof(struct dvb_frontend_ops));
998 state->frontend.demodulator_priv = state;
999 return &state->frontend;
1000
1001error3:
1002 kfree(state);
1003error2:
1004 return NULL;
1005}
1006EXPORT_SYMBOL(ds3000_attach);
1007
1008static int ds3000_set_property(struct dvb_frontend *fe,
1009 struct dtv_property *tvp)
1010{
1011 dprintk("%s(..)\n", __func__);
1012 return 0;
1013}
1014
1015static int ds3000_get_property(struct dvb_frontend *fe,
1016 struct dtv_property *tvp)
1017{
1018 dprintk("%s(..)\n", __func__);
1019 return 0;
1020}
1021
1022static int ds3000_tune(struct dvb_frontend *fe,
1023 struct dvb_frontend_parameters *p)
1024{
1025 struct ds3000_state *state = fe->demodulator_priv;
1026 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1027
1028 int ret = 0, retune, i;
1029 u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;
1030 u16 value, ndiv;
1031 u32 f3db;
1032
1033 dprintk("%s() ", __func__);
1034
1035 /* Load the firmware if required */
1036 ret = ds3000_firmware_ondemand(fe);
1037 if (ret != 0) {
1038 printk(KERN_ERR "%s: Unable initialise the firmware\n",
1039 __func__);
1040 return ret;
1041 }
1042
1043 state->dnxt.delivery = c->modulation;
1044 state->dnxt.frequency = c->frequency;
1045 state->dnxt.rolloff = 2; /* fixme */
1046 state->dnxt.fec = c->fec_inner;
1047
1048 ret = ds3000_set_inversion(state, p->inversion);
1049 if (ret != 0)
1050 return ret;
1051
1052 ret = ds3000_set_symbolrate(state, c->symbol_rate);
1053 if (ret != 0)
1054 return ret;
1055
1056 /* discard the 'current' tuning parameters and prepare to tune */
1057 ds3000_clone_params(fe);
1058
1059 retune = 1; /* try 1 times */
1060 dprintk("%s: retune = %d\n", __func__, retune);
1061 dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency);
1062 dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
1063 dprintk("%s: FEC = %d \n", __func__,
1064 state->dcur.fec);
1065 dprintk("%s: Inversion = %d\n", __func__, state->dcur.inversion);
1066
1067 do {
1068 /* Reset status register */
1069 status = 0;
1070 /* Tune */
1071 /* TS2020 init */
1072 ds3000_tuner_writereg(state, 0x42, 0x73);
1073 ds3000_tuner_writereg(state, 0x05, 0x01);
1074 ds3000_tuner_writereg(state, 0x62, 0xf5);
1075 /* unknown */
1076 ds3000_tuner_writereg(state, 0x07, 0x02);
1077 ds3000_tuner_writereg(state, 0x10, 0x00);
1078 ds3000_tuner_writereg(state, 0x60, 0x79);
1079 ds3000_tuner_writereg(state, 0x08, 0x01);
1080 ds3000_tuner_writereg(state, 0x00, 0x01);
1081 /* calculate and set freq divider */
1082 if (state->dcur.frequency < 1146000) {
1083 ds3000_tuner_writereg(state, 0x10, 0x11);
1084 ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
1085 (DS3000_XTAL_FREQ / 2)) /
1086 DS3000_XTAL_FREQ - 1024;
1087 } else {
1088 ds3000_tuner_writereg(state, 0x10, 0x01);
1089 ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
1090 (DS3000_XTAL_FREQ / 2)) /
1091 DS3000_XTAL_FREQ - 1024;
1092 }
1093
1094 ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
1095 ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
1096
1097 /* set pll */
1098 ds3000_tuner_writereg(state, 0x03, 0x06);
1099 ds3000_tuner_writereg(state, 0x51, 0x0f);
1100 ds3000_tuner_writereg(state, 0x51, 0x1f);
1101 ds3000_tuner_writereg(state, 0x50, 0x10);
1102 ds3000_tuner_writereg(state, 0x50, 0x00);
1103 msleep(5);
1104
1105 /* unknown */
1106 ds3000_tuner_writereg(state, 0x51, 0x17);
1107 ds3000_tuner_writereg(state, 0x51, 0x1f);
1108 ds3000_tuner_writereg(state, 0x50, 0x08);
1109 ds3000_tuner_writereg(state, 0x50, 0x00);
1110 msleep(5);
1111
1112 value = ds3000_tuner_readreg(state, 0x3d);
1113 value &= 0x0f;
1114 if ((value > 4) && (value < 15)) {
1115 value -= 3;
1116 if (value < 4)
1117 value = 4;
1118 value = ((value << 3) | 0x01) & 0x79;
1119 }
1120
1121 ds3000_tuner_writereg(state, 0x60, value);
1122 ds3000_tuner_writereg(state, 0x51, 0x17);
1123 ds3000_tuner_writereg(state, 0x51, 0x1f);
1124 ds3000_tuner_writereg(state, 0x50, 0x08);
1125 ds3000_tuner_writereg(state, 0x50, 0x00);
1126
1127 /* set low-pass filter period */
1128 ds3000_tuner_writereg(state, 0x04, 0x2e);
1129 ds3000_tuner_writereg(state, 0x51, 0x1b);
1130 ds3000_tuner_writereg(state, 0x51, 0x1f);
1131 ds3000_tuner_writereg(state, 0x50, 0x04);
1132 ds3000_tuner_writereg(state, 0x50, 0x00);
1133 msleep(5);
1134
1135 f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
1136 if ((state->dcur.symbol_rate / 1000) < 5000)
1137 f3db += 3000;
1138 if (f3db < 7000)
1139 f3db = 7000;
1140 if (f3db > 40000)
1141 f3db = 40000;
1142
1143 /* set low-pass filter baseband */
1144 value = ds3000_tuner_readreg(state, 0x26);
1145 mlpf = 0x2e * 207 / ((value << 1) + 151);
1146 mlpf_max = mlpf * 135 / 100;
1147 mlpf_min = mlpf * 78 / 100;
1148 if (mlpf_max > 63)
1149 mlpf_max = 63;
1150
1151 /* rounded to the closest integer */
1152 nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
1153 / (2766 * DS3000_XTAL_FREQ);
1154 if (nlpf > 23)
1155 nlpf = 23;
1156 if (nlpf < 1)
1157 nlpf = 1;
1158
1159 /* rounded to the closest integer */
1160 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1161 (1000 * f3db / 2)) / (1000 * f3db);
1162
1163 if (mlpf_new < mlpf_min) {
1164 nlpf++;
1165 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1166 (1000 * f3db / 2)) / (1000 * f3db);
1167 }
1168
1169 if (mlpf_new > mlpf_max)
1170 mlpf_new = mlpf_max;
1171
1172 ds3000_tuner_writereg(state, 0x04, mlpf_new);
1173 ds3000_tuner_writereg(state, 0x06, nlpf);
1174 ds3000_tuner_writereg(state, 0x51, 0x1b);
1175 ds3000_tuner_writereg(state, 0x51, 0x1f);
1176 ds3000_tuner_writereg(state, 0x50, 0x04);
1177 ds3000_tuner_writereg(state, 0x50, 0x00);
1178 msleep(5);
1179
1180 /* unknown */
1181 ds3000_tuner_writereg(state, 0x51, 0x1e);
1182 ds3000_tuner_writereg(state, 0x51, 0x1f);
1183 ds3000_tuner_writereg(state, 0x50, 0x01);
1184 ds3000_tuner_writereg(state, 0x50, 0x00);
1185 msleep(60);
1186
1187 /* ds3000 global reset */
1188 ds3000_writereg(state, 0x07, 0x80);
1189 ds3000_writereg(state, 0x07, 0x00);
1190 /* ds3000 build-in uC reset */
1191 ds3000_writereg(state, 0xb2, 0x01);
1192 /* ds3000 software reset */
1193 ds3000_writereg(state, 0x00, 0x01);
1194
1195 switch (c->delivery_system) {
1196 case SYS_DVBS:
1197 /* initialise the demod in DVB-S mode */
1198 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
1199 ds3000_writereg(state,
1200 ds3000_dvbs_init_tab[i],
1201 ds3000_dvbs_init_tab[i + 1]);
1202 value = ds3000_readreg(state, 0xfe);
1203 value &= 0xc0;
1204 value |= 0x1b;
1205 ds3000_writereg(state, 0xfe, value);
1206 break;
1207 case SYS_DVBS2:
1208 /* initialise the demod in DVB-S2 mode */
1209 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1210 ds3000_writereg(state,
1211 ds3000_dvbs2_init_tab[i],
1212 ds3000_dvbs2_init_tab[i + 1]);
1213 ds3000_writereg(state, 0xfe, 0x54);
1214 break;
1215 default:
1216 return 1;
1217 }
1218
1219 /* enable 27MHz clock output */
1220 ds3000_writereg(state, 0x29, 0x80);
1221 /* enable ac coupling */
1222 ds3000_writereg(state, 0x25, 0x8a);
1223
1224 /* enhance symbol rate performance */
1225 if ((state->dcur.symbol_rate / 1000) <= 5000) {
1226 value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
1227 if (value % 2 != 0)
1228 value++;
1229 ds3000_writereg(state, 0xc3, 0x0d);
1230 ds3000_writereg(state, 0xc8, value);
1231 ds3000_writereg(state, 0xc4, 0x10);
1232 ds3000_writereg(state, 0xc7, 0x0e);
1233 } else if ((state->dcur.symbol_rate / 1000) <= 10000) {
1234 value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
1235 if (value % 2 != 0)
1236 value++;
1237 ds3000_writereg(state, 0xc3, 0x07);
1238 ds3000_writereg(state, 0xc8, value);
1239 ds3000_writereg(state, 0xc4, 0x09);
1240 ds3000_writereg(state, 0xc7, 0x12);
1241 } else if ((state->dcur.symbol_rate / 1000) <= 20000) {
1242 value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
1243 ds3000_writereg(state, 0xc3, value);
1244 ds3000_writereg(state, 0xc8, 0x0e);
1245 ds3000_writereg(state, 0xc4, 0x07);
1246 ds3000_writereg(state, 0xc7, 0x18);
1247 } else {
1248 value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
1249 ds3000_writereg(state, 0xc3, value);
1250 ds3000_writereg(state, 0xc8, 0x0a);
1251 ds3000_writereg(state, 0xc4, 0x05);
1252 ds3000_writereg(state, 0xc7, 0x24);
1253 }
1254
1255 /* normalized symbol rate rounded to the closest integer */
1256 value = (((state->dcur.symbol_rate / 1000) << 16) +
1257 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
1258 ds3000_writereg(state, 0x61, value & 0x00ff);
1259 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1260
1261 /* co-channel interference cancellation disabled */
1262 ds3000_writereg(state, 0x56, 0x00);
1263
1264 /* equalizer disabled */
1265 ds3000_writereg(state, 0x76, 0x00);
1266
1267 /*ds3000_writereg(state, 0x08, 0x03);
1268 ds3000_writereg(state, 0xfd, 0x22);
1269 ds3000_writereg(state, 0x08, 0x07);
1270 ds3000_writereg(state, 0xfd, 0x42);
1271 ds3000_writereg(state, 0x08, 0x07);*/
1272
1273 /* ds3000 out of software reset */
1274 ds3000_writereg(state, 0x00, 0x00);
1275 /* start ds3000 build-in uC */
1276 ds3000_writereg(state, 0xb2, 0x00);
1277
1278 /* TODO: calculate and set carrier offset */
1279
1280 /* wait before retrying */
1281 for (i = 0; i < 30 ; i++) {
1282 if (ds3000_is_tuned(fe)) {
1283 dprintk("%s: Tuned\n", __func__);
1284 ds3000_dump_registers(fe);
1285 goto tuned;
1286 }
1287 msleep(1);
1288 }
1289
1290 dprintk("%s: Not tuned\n", __func__);
1291 ds3000_dump_registers(fe);
1292
1293 } while (--retune);
1294
1295tuned:
1296 return ret;
1297}
1298
1299static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1300{
1301 dprintk("%s()\n", __func__);
1302 return DVBFE_ALGO_SW;
1303}
1304
1305/*
1306 * Initialise or wake up device
1307 *
1308 * Power config will reset and load initial firmware if required
1309 */
1310static int ds3000_initfe(struct dvb_frontend *fe)
1311{
1312 dprintk("%s()\n", __func__);
1313 return 0;
1314}
1315
1316/* Put device to sleep */
1317static int ds3000_sleep(struct dvb_frontend *fe)
1318{
1319 dprintk("%s()\n", __func__);
1320 return 0;
1321}
1322
1323static struct dvb_frontend_ops ds3000_ops = {
1324
1325 .info = {
1326 .name = "Montage Technology DS3000/TS2020",
1327 .type = FE_QPSK,
1328 .frequency_min = 950000,
1329 .frequency_max = 2150000,
1330 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1331 .frequency_tolerance = 5000,
1332 .symbol_rate_min = 1000000,
1333 .symbol_rate_max = 45000000,
1334 .caps = FE_CAN_INVERSION_AUTO |
1335 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1336 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1337 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1338 FE_CAN_2G_MODULATION |
1339 FE_CAN_QPSK | FE_CAN_RECOVER
1340 },
1341
1342 .release = ds3000_release,
1343
1344 .init = ds3000_initfe,
1345 .sleep = ds3000_sleep,
1346 .read_status = ds3000_read_status,
1347 .read_ber = ds3000_read_ber,
1348 .read_signal_strength = ds3000_read_signal_strength,
1349 .read_snr = ds3000_read_snr,
1350 .read_ucblocks = ds3000_read_ucblocks,
1351 .set_tone = ds3000_set_tone,
1352 .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1353 .diseqc_send_burst = ds3000_diseqc_send_burst,
1354 .get_frontend_algo = ds3000_get_algo,
1355
1356 .set_property = ds3000_set_property,
1357 .get_property = ds3000_get_property,
1358 .set_frontend = ds3000_tune,
1359};
1360
1361module_param(debug, int, 0644);
1362MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1363
1364MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
1365 "DS3000/TS2020 hardware");
1366MODULE_AUTHOR("Konstantin Dimitrov");
1367MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/ds3000.h b/drivers/media/dvb/frontends/ds3000.h
new file mode 100644
index 000000000000..67f67038740a
--- /dev/null
+++ b/drivers/media/dvb/frontends/ds3000.h
@@ -0,0 +1,45 @@
1/*
2 Montage Technology DS3000/TS2020 - DVBS/S2 Satellite demod/tuner driver
3 Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
4
5 Copyright (C) 2009 TurboSight.com
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef DS3000_H
23#define DS3000_H
24
25#include <linux/dvb/frontend.h>
26
27struct ds3000_config {
28 /* the demodulator's i2c address */
29 u8 demod_address;
30};
31
32#if defined(CONFIG_DVB_DS3000) || \
33 (defined(CONFIG_DVB_DS3000_MODULE) && defined(MODULE))
34extern struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
35 struct i2c_adapter *i2c);
36#else
37static inline
38struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
39 struct i2c_adapter *i2c)
40{
41 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
42 return NULL;
43}
44#endif /* CONFIG_DVB_DS3000 */
45#endif /* DS3000_H */
diff --git a/drivers/media/dvb/frontends/ec100.c b/drivers/media/dvb/frontends/ec100.c
new file mode 100644
index 000000000000..2414dc6ee5d9
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100.c
@@ -0,0 +1,335 @@
1/*
2 * E3C EC100 demodulator driver
3 *
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22#include "dvb_frontend.h"
23#include "ec100_priv.h"
24#include "ec100.h"
25
26int ec100_debug;
27module_param_named(debug, ec100_debug, int, 0644);
28MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
29
30struct ec100_state {
31 struct i2c_adapter *i2c;
32 struct dvb_frontend frontend;
33 struct ec100_config config;
34
35 u16 ber;
36};
37
38/* write single register */
39static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val)
40{
41 u8 buf[2] = {reg, val};
42 struct i2c_msg msg = {
43 .addr = state->config.demod_address,
44 .flags = 0,
45 .len = 2,
46 .buf = buf};
47
48 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
49 warn("I2C write failed reg:%02x", reg);
50 return -EREMOTEIO;
51 }
52 return 0;
53}
54
55/* read single register */
56static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val)
57{
58 struct i2c_msg msg[2] = {
59 {
60 .addr = state->config.demod_address,
61 .flags = 0,
62 .len = 1,
63 .buf = &reg
64 }, {
65 .addr = state->config.demod_address,
66 .flags = I2C_M_RD,
67 .len = 1,
68 .buf = val
69 }
70 };
71
72 if (i2c_transfer(state->i2c, msg, 2) != 2) {
73 warn("I2C read failed reg:%02x", reg);
74 return -EREMOTEIO;
75 }
76 return 0;
77}
78
79static int ec100_set_frontend(struct dvb_frontend *fe,
80 struct dvb_frontend_parameters *params)
81{
82 struct ec100_state *state = fe->demodulator_priv;
83 int ret;
84 u8 tmp, tmp2;
85
86 deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency,
87 params->u.ofdm.bandwidth);
88
89 /* program tuner */
90 if (fe->ops.tuner_ops.set_params)
91 fe->ops.tuner_ops.set_params(fe, params);
92
93 ret = ec100_write_reg(state, 0x04, 0x06);
94 if (ret)
95 goto error;
96 ret = ec100_write_reg(state, 0x67, 0x58);
97 if (ret)
98 goto error;
99 ret = ec100_write_reg(state, 0x05, 0x18);
100 if (ret)
101 goto error;
102
103 /* reg/bw | 6 | 7 | 8
104 -------+------+------+------
105 A 0x1b | 0xa1 | 0xe7 | 0x2c
106 A 0x1c | 0x55 | 0x63 | 0x72
107 -------+------+------+------
108 B 0x1b | 0xb7 | 0x00 | 0x49
109 B 0x1c | 0x55 | 0x64 | 0x72 */
110
111 switch (params->u.ofdm.bandwidth) {
112 case BANDWIDTH_6_MHZ:
113 tmp = 0xb7;
114 tmp2 = 0x55;
115 break;
116 case BANDWIDTH_7_MHZ:
117 tmp = 0x00;
118 tmp2 = 0x64;
119 break;
120 case BANDWIDTH_8_MHZ:
121 default:
122 tmp = 0x49;
123 tmp2 = 0x72;
124 }
125
126 ret = ec100_write_reg(state, 0x1b, tmp);
127 if (ret)
128 goto error;
129 ret = ec100_write_reg(state, 0x1c, tmp2);
130 if (ret)
131 goto error;
132
133 ret = ec100_write_reg(state, 0x0c, 0xbb); /* if freq */
134 if (ret)
135 goto error;
136 ret = ec100_write_reg(state, 0x0d, 0x31); /* if freq */
137 if (ret)
138 goto error;
139
140 ret = ec100_write_reg(state, 0x08, 0x24);
141 if (ret)
142 goto error;
143
144 ret = ec100_write_reg(state, 0x00, 0x00); /* go */
145 if (ret)
146 goto error;
147 ret = ec100_write_reg(state, 0x00, 0x20); /* go */
148 if (ret)
149 goto error;
150
151 return ret;
152error:
153 deb_info("%s: failed:%d\n", __func__, ret);
154 return ret;
155}
156
157static int ec100_get_tune_settings(struct dvb_frontend *fe,
158 struct dvb_frontend_tune_settings *fesettings)
159{
160 fesettings->min_delay_ms = 300;
161 fesettings->step_size = 0;
162 fesettings->max_drift = 0;
163
164 return 0;
165}
166
167static int ec100_read_status(struct dvb_frontend *fe, fe_status_t *status)
168{
169 struct ec100_state *state = fe->demodulator_priv;
170 int ret;
171 u8 tmp;
172 *status = 0;
173
174 ret = ec100_read_reg(state, 0x42, &tmp);
175 if (ret)
176 goto error;
177
178 if (tmp & 0x80) {
179 /* bit7 set - have lock */
180 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
181 FE_HAS_SYNC | FE_HAS_LOCK;
182 } else {
183 ret = ec100_read_reg(state, 0x01, &tmp);
184 if (ret)
185 goto error;
186
187 if (tmp & 0x10) {
188 /* bit4 set - have signal */
189 *status |= FE_HAS_SIGNAL;
190 if (!(tmp & 0x01)) {
191 /* bit0 clear - have ~valid signal */
192 *status |= FE_HAS_CARRIER | FE_HAS_VITERBI;
193 }
194 }
195 }
196
197 return ret;
198error:
199 deb_info("%s: failed:%d\n", __func__, ret);
200 return ret;
201}
202
203static int ec100_read_ber(struct dvb_frontend *fe, u32 *ber)
204{
205 struct ec100_state *state = fe->demodulator_priv;
206 int ret;
207 u8 tmp, tmp2;
208 u16 ber2;
209
210 *ber = 0;
211
212 ret = ec100_read_reg(state, 0x65, &tmp);
213 if (ret)
214 goto error;
215 ret = ec100_read_reg(state, 0x66, &tmp2);
216 if (ret)
217 goto error;
218
219 ber2 = (tmp2 << 8) | tmp;
220
221 /* if counter overflow or clear */
222 if (ber2 < state->ber)
223 *ber = ber2;
224 else
225 *ber = ber2 - state->ber;
226
227 state->ber = ber2;
228
229 return ret;
230error:
231 deb_info("%s: failed:%d\n", __func__, ret);
232 return ret;
233}
234
235static int ec100_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
236{
237 struct ec100_state *state = fe->demodulator_priv;
238 int ret;
239 u8 tmp;
240
241 ret = ec100_read_reg(state, 0x24, &tmp);
242 if (ret) {
243 *strength = 0;
244 goto error;
245 }
246
247 *strength = ((tmp << 8) | tmp);
248
249 return ret;
250error:
251 deb_info("%s: failed:%d\n", __func__, ret);
252 return ret;
253}
254
255static int ec100_read_snr(struct dvb_frontend *fe, u16 *snr)
256{
257 *snr = 0;
258 return 0;
259}
260
261static int ec100_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
262{
263 *ucblocks = 0;
264 return 0;
265}
266
267static void ec100_release(struct dvb_frontend *fe)
268{
269 struct ec100_state *state = fe->demodulator_priv;
270 kfree(state);
271}
272
273static struct dvb_frontend_ops ec100_ops;
274
275struct dvb_frontend *ec100_attach(const struct ec100_config *config,
276 struct i2c_adapter *i2c)
277{
278 int ret;
279 struct ec100_state *state = NULL;
280 u8 tmp;
281
282 /* allocate memory for the internal state */
283 state = kzalloc(sizeof(struct ec100_state), GFP_KERNEL);
284 if (state == NULL)
285 goto error;
286
287 /* setup the state */
288 state->i2c = i2c;
289 memcpy(&state->config, config, sizeof(struct ec100_config));
290
291 /* check if the demod is there */
292 ret = ec100_read_reg(state, 0x33, &tmp);
293 if (ret || tmp != 0x0b)
294 goto error;
295
296 /* create dvb_frontend */
297 memcpy(&state->frontend.ops, &ec100_ops,
298 sizeof(struct dvb_frontend_ops));
299 state->frontend.demodulator_priv = state;
300
301 return &state->frontend;
302error:
303 kfree(state);
304 return NULL;
305}
306EXPORT_SYMBOL(ec100_attach);
307
308static struct dvb_frontend_ops ec100_ops = {
309 .info = {
310 .name = "E3C EC100 DVB-T",
311 .type = FE_OFDM,
312 .caps =
313 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
314 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
315 FE_CAN_QPSK | FE_CAN_QAM_16 |
316 FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
317 FE_CAN_TRANSMISSION_MODE_AUTO |
318 FE_CAN_GUARD_INTERVAL_AUTO |
319 FE_CAN_HIERARCHY_AUTO |
320 FE_CAN_MUTE_TS
321 },
322
323 .release = ec100_release,
324 .set_frontend = ec100_set_frontend,
325 .get_tune_settings = ec100_get_tune_settings,
326 .read_status = ec100_read_status,
327 .read_ber = ec100_read_ber,
328 .read_signal_strength = ec100_read_signal_strength,
329 .read_snr = ec100_read_snr,
330 .read_ucblocks = ec100_read_ucblocks,
331};
332
333MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
334MODULE_DESCRIPTION("E3C EC100 DVB-T demodulator driver");
335MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/ec100.h b/drivers/media/dvb/frontends/ec100.h
new file mode 100644
index 000000000000..ee8e52417958
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100.h
@@ -0,0 +1,46 @@
1/*
2 * E3C EC100 demodulator driver
3 *
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22#ifndef EC100_H
23#define EC100_H
24
25#include <linux/dvb/frontend.h>
26
27struct ec100_config {
28 /* demodulator's I2C address */
29 u8 demod_address;
30};
31
32
33#if defined(CONFIG_DVB_EC100) || \
34 (defined(CONFIG_DVB_EC100_MODULE) && defined(MODULE))
35extern struct dvb_frontend *ec100_attach(const struct ec100_config *config,
36 struct i2c_adapter *i2c);
37#else
38static inline struct dvb_frontend *ec100_attach(
39 const struct ec100_config *config, struct i2c_adapter *i2c)
40{
41 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
42 return NULL;
43}
44#endif
45
46#endif /* EC100_H */
diff --git a/drivers/media/dvb/frontends/ec100_priv.h b/drivers/media/dvb/frontends/ec100_priv.h
new file mode 100644
index 000000000000..5c990144bc47
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100_priv.h
@@ -0,0 +1,39 @@
1/*
2 * E3C EC100 demodulator driver
3 *
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22#ifndef EC100_PRIV
23#define EC100_PRIV
24
25#define LOG_PREFIX "ec100"
26
27#define dprintk(var, level, args...) \
28 do { if ((var & level)) printk(args); } while (0)
29
30#define deb_info(args...) dprintk(ec100_debug, 0x01, args)
31
32#undef err
33#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
34#undef info
35#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
36#undef warn
37#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
38
39#endif /* EC100_PRIV */
diff --git a/drivers/media/dvb/frontends/s5h1409.c b/drivers/media/dvb/frontends/s5h1409.c
index fb3011518427..0e2f61a8978f 100644
--- a/drivers/media/dvb/frontends/s5h1409.c
+++ b/drivers/media/dvb/frontends/s5h1409.c
@@ -44,7 +44,15 @@ struct s5h1409_state {
44 int if_freq; 44 int if_freq;
45 45
46 u32 is_qam_locked; 46 u32 is_qam_locked;
47 u32 qam_state; 47
48 /* QAM tuning state goes through the following state transitions */
49#define QAM_STATE_UNTUNED 0
50#define QAM_STATE_TUNING_STARTED 1
51#define QAM_STATE_INTERLEAVE_SET 2
52#define QAM_STATE_QAM_OPTIMIZED_L1 3
53#define QAM_STATE_QAM_OPTIMIZED_L2 4
54#define QAM_STATE_QAM_OPTIMIZED_L3 5
55 u8 qam_state;
48}; 56};
49 57
50static int debug; 58static int debug;
@@ -347,7 +355,7 @@ static int s5h1409_softreset(struct dvb_frontend *fe)
347 s5h1409_writereg(state, 0xf5, 0); 355 s5h1409_writereg(state, 0xf5, 0);
348 s5h1409_writereg(state, 0xf5, 1); 356 s5h1409_writereg(state, 0xf5, 1);
349 state->is_qam_locked = 0; 357 state->is_qam_locked = 0;
350 state->qam_state = 0; 358 state->qam_state = QAM_STATE_UNTUNED;
351 return 0; 359 return 0;
352} 360}
353 361
@@ -474,6 +482,59 @@ static void s5h1409_set_qam_amhum_mode(struct dvb_frontend *fe)
474 struct s5h1409_state *state = fe->demodulator_priv; 482 struct s5h1409_state *state = fe->demodulator_priv;
475 u16 reg; 483 u16 reg;
476 484
485 if (state->qam_state < QAM_STATE_INTERLEAVE_SET) {
486 /* We should not perform amhum optimization until
487 the interleave mode has been configured */
488 return;
489 }
490
491 if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) {
492 /* We've already reached the maximum optimization level, so
493 dont bother banging on the status registers */
494 return;
495 }
496
497 /* QAM EQ lock check */
498 reg = s5h1409_readreg(state, 0xf0);
499
500 if ((reg >> 13) & 0x1) {
501 reg &= 0xff;
502
503 s5h1409_writereg(state, 0x96, 0x000c);
504 if (reg < 0x68) {
505 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) {
506 dprintk("%s() setting QAM state to OPT_L3\n",
507 __func__);
508 s5h1409_writereg(state, 0x93, 0x3130);
509 s5h1409_writereg(state, 0x9e, 0x2836);
510 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3;
511 }
512 } else {
513 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) {
514 dprintk("%s() setting QAM state to OPT_L2\n",
515 __func__);
516 s5h1409_writereg(state, 0x93, 0x3332);
517 s5h1409_writereg(state, 0x9e, 0x2c37);
518 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2;
519 }
520 }
521
522 } else {
523 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) {
524 dprintk("%s() setting QAM state to OPT_L1\n", __func__);
525 s5h1409_writereg(state, 0x96, 0x0008);
526 s5h1409_writereg(state, 0x93, 0x3332);
527 s5h1409_writereg(state, 0x9e, 0x2c37);
528 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1;
529 }
530 }
531}
532
533static void s5h1409_set_qam_amhum_mode_legacy(struct dvb_frontend *fe)
534{
535 struct s5h1409_state *state = fe->demodulator_priv;
536 u16 reg;
537
477 if (state->is_qam_locked) 538 if (state->is_qam_locked)
478 return; 539 return;
479 540
@@ -506,6 +567,44 @@ static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
506 struct s5h1409_state *state = fe->demodulator_priv; 567 struct s5h1409_state *state = fe->demodulator_priv;
507 u16 reg, reg1, reg2; 568 u16 reg, reg1, reg2;
508 569
570 if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) {
571 /* We've done the optimization already */
572 return;
573 }
574
575 reg = s5h1409_readreg(state, 0xf1);
576
577 /* Master lock */
578 if ((reg >> 15) & 0x1) {
579 if (state->qam_state == QAM_STATE_UNTUNED ||
580 state->qam_state == QAM_STATE_TUNING_STARTED) {
581 dprintk("%s() setting QAM state to INTERLEAVE_SET\n",
582 __func__);
583 reg1 = s5h1409_readreg(state, 0xb2);
584 reg2 = s5h1409_readreg(state, 0xad);
585
586 s5h1409_writereg(state, 0x96, 0x0020);
587 s5h1409_writereg(state, 0xad,
588 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
589 state->qam_state = QAM_STATE_INTERLEAVE_SET;
590 }
591 } else {
592 if (state->qam_state == QAM_STATE_UNTUNED) {
593 dprintk("%s() setting QAM state to TUNING_STARTED\n",
594 __func__);
595 s5h1409_writereg(state, 0x96, 0x08);
596 s5h1409_writereg(state, 0xab,
597 s5h1409_readreg(state, 0xab) | 0x1001);
598 state->qam_state = QAM_STATE_TUNING_STARTED;
599 }
600 }
601}
602
603static void s5h1409_set_qam_interleave_mode_legacy(struct dvb_frontend *fe)
604{
605 struct s5h1409_state *state = fe->demodulator_priv;
606 u16 reg, reg1, reg2;
607
509 reg = s5h1409_readreg(state, 0xf1); 608 reg = s5h1409_readreg(state, 0xf1);
510 609
511 /* Master lock */ 610 /* Master lock */
@@ -553,16 +652,24 @@ static int s5h1409_set_frontend(struct dvb_frontend *fe,
553 fe->ops.i2c_gate_ctrl(fe, 0); 652 fe->ops.i2c_gate_ctrl(fe, 0);
554 } 653 }
555 654
556 /* Optimize the demod for QAM */
557 if (p->u.vsb.modulation != VSB_8) {
558 s5h1409_set_qam_amhum_mode(fe);
559 s5h1409_set_qam_interleave_mode(fe);
560 }
561
562 /* Issue a reset to the demod so it knows to resync against the 655 /* Issue a reset to the demod so it knows to resync against the
563 newly tuned frequency */ 656 newly tuned frequency */
564 s5h1409_softreset(fe); 657 s5h1409_softreset(fe);
565 658
659 /* Optimize the demod for QAM */
660 if (state->current_modulation != VSB_8) {
661 /* This almost certainly applies to all boards, but for now
662 only do it for the HVR-1600. Once the other boards are
663 tested, the "legacy" versions can just go away */
664 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
665 s5h1409_set_qam_interleave_mode(fe);
666 s5h1409_set_qam_amhum_mode(fe);
667 } else {
668 s5h1409_set_qam_amhum_mode_legacy(fe);
669 s5h1409_set_qam_interleave_mode_legacy(fe);
670 }
671 }
672
566 return 0; 673 return 0;
567} 674}
568 675
@@ -614,6 +721,21 @@ static int s5h1409_init(struct dvb_frontend *fe)
614 /* The datasheet says that after initialisation, VSB is default */ 721 /* The datasheet says that after initialisation, VSB is default */
615 state->current_modulation = VSB_8; 722 state->current_modulation = VSB_8;
616 723
724 /* Optimize for the HVR-1600 if appropriate. Note that some of these
725 may get folded into the generic case after testing with other
726 devices */
727 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
728 /* VSB AGC REF */
729 s5h1409_writereg(state, 0x09, 0x0050);
730
731 /* Unknown but Windows driver does it... */
732 s5h1409_writereg(state, 0x21, 0x0001);
733 s5h1409_writereg(state, 0x50, 0x030e);
734
735 /* QAM AGC REF */
736 s5h1409_writereg(state, 0x82, 0x0800);
737 }
738
617 if (state->config->output_mode == S5H1409_SERIAL_OUTPUT) 739 if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
618 s5h1409_writereg(state, 0xab, 740 s5h1409_writereg(state, 0xab,
619 s5h1409_readreg(state, 0xab) | 0x100); /* Serial */ 741 s5h1409_readreg(state, 0xab) | 0x100); /* Serial */
@@ -641,6 +763,17 @@ static int s5h1409_read_status(struct dvb_frontend *fe, fe_status_t *status)
641 763
642 *status = 0; 764 *status = 0;
643 765
766 /* Optimize the demod for QAM */
767 if (state->current_modulation != VSB_8) {
768 /* This almost certainly applies to all boards, but for now
769 only do it for the HVR-1600. Once the other boards are
770 tested, the "legacy" versions can just go away */
771 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
772 s5h1409_set_qam_interleave_mode(fe);
773 s5h1409_set_qam_amhum_mode(fe);
774 }
775 }
776
644 /* Get the demodulator status */ 777 /* Get the demodulator status */
645 reg = s5h1409_readreg(state, 0xf1); 778 reg = s5h1409_readreg(state, 0xf1);
646 if (reg & 0x1000) 779 if (reg & 0x1000)
diff --git a/drivers/media/dvb/frontends/s5h1409.h b/drivers/media/dvb/frontends/s5h1409.h
index 070d9743e330..91f2ebd1a534 100644
--- a/drivers/media/dvb/frontends/s5h1409.h
+++ b/drivers/media/dvb/frontends/s5h1409.h
@@ -57,6 +57,13 @@ struct s5h1409_config {
57#define S5H1409_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK 2 57#define S5H1409_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK 2
58#define S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK 3 58#define S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK 3
59 u16 mpeg_timing; 59 u16 mpeg_timing;
60
61 /* HVR-1600 optimizations (to better work with MXL5005s)
62 Note: some of these are likely to be folded into the generic driver
63 after being regression tested with other boards */
64#define S5H1409_HVR1600_NOOPTIMIZE 0
65#define S5H1409_HVR1600_OPTIMIZE 1
66 u8 hvr1600_opt;
60}; 67};
61 68
62#if defined(CONFIG_DVB_S5H1409) || (defined(CONFIG_DVB_S5H1409_MODULE) \ 69#if defined(CONFIG_DVB_S5H1409) || (defined(CONFIG_DVB_S5H1409_MODULE) \
diff --git a/drivers/media/dvb/frontends/stb6100_proc.h b/drivers/media/dvb/frontends/stb6100_proc.h
new file mode 100644
index 000000000000..112163a48622
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb6100_proc.h
@@ -0,0 +1,138 @@
1/*
2 STB6100 Silicon Tuner wrapper
3 Copyright (C)2009 Igor M. Liplianin (liplianin@me.by)
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18*/
19
20static int stb6100_get_freq(struct dvb_frontend *fe, u32 *frequency)
21{
22 struct dvb_frontend_ops *frontend_ops = NULL;
23 struct dvb_tuner_ops *tuner_ops = NULL;
24 struct tuner_state state;
25 int err = 0;
26
27 if (&fe->ops)
28 frontend_ops = &fe->ops;
29 if (&frontend_ops->tuner_ops)
30 tuner_ops = &frontend_ops->tuner_ops;
31 if (tuner_ops->get_state) {
32 if (frontend_ops->i2c_gate_ctrl)
33 frontend_ops->i2c_gate_ctrl(fe, 1);
34
35 err = tuner_ops->get_state(fe, DVBFE_TUNER_FREQUENCY, &state);
36 if (err < 0) {
37 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
38 return err;
39 }
40
41 if (frontend_ops->i2c_gate_ctrl)
42 frontend_ops->i2c_gate_ctrl(fe, 0);
43
44 *frequency = state.frequency;
45 }
46
47 return 0;
48}
49
50static int stb6100_set_freq(struct dvb_frontend *fe, u32 frequency)
51{
52 struct dvb_frontend_ops *frontend_ops = NULL;
53 struct dvb_tuner_ops *tuner_ops = NULL;
54 struct tuner_state state;
55 int err = 0;
56
57 state.frequency = frequency;
58 if (&fe->ops)
59 frontend_ops = &fe->ops;
60 if (&frontend_ops->tuner_ops)
61 tuner_ops = &frontend_ops->tuner_ops;
62 if (tuner_ops->set_state) {
63 if (frontend_ops->i2c_gate_ctrl)
64 frontend_ops->i2c_gate_ctrl(fe, 1);
65
66 err = tuner_ops->set_state(fe, DVBFE_TUNER_FREQUENCY, &state);
67 if (err < 0) {
68 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
69 return err;
70 }
71
72 if (frontend_ops->i2c_gate_ctrl)
73 frontend_ops->i2c_gate_ctrl(fe, 0);
74
75 }
76
77 return 0;
78}
79
80static int stb6100_get_bandw(struct dvb_frontend *fe, u32 *bandwidth)
81{
82 struct dvb_frontend_ops *frontend_ops = NULL;
83 struct dvb_tuner_ops *tuner_ops = NULL;
84 struct tuner_state state;
85 int err = 0;
86
87 if (&fe->ops)
88 frontend_ops = &fe->ops;
89 if (&frontend_ops->tuner_ops)
90 tuner_ops = &frontend_ops->tuner_ops;
91 if (tuner_ops->get_state) {
92 if (frontend_ops->i2c_gate_ctrl)
93 frontend_ops->i2c_gate_ctrl(fe, 1);
94
95 err = tuner_ops->get_state(fe, DVBFE_TUNER_BANDWIDTH, &state);
96 if (err < 0) {
97 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
98 return err;
99 }
100
101 if (frontend_ops->i2c_gate_ctrl)
102 frontend_ops->i2c_gate_ctrl(fe, 0);
103
104 *bandwidth = state.bandwidth;
105 }
106
107 return 0;
108}
109
110static int stb6100_set_bandw(struct dvb_frontend *fe, u32 bandwidth)
111{
112 struct dvb_frontend_ops *frontend_ops = NULL;
113 struct dvb_tuner_ops *tuner_ops = NULL;
114 struct tuner_state state;
115 int err = 0;
116
117 state.bandwidth = bandwidth;
118 if (&fe->ops)
119 frontend_ops = &fe->ops;
120 if (&frontend_ops->tuner_ops)
121 tuner_ops = &frontend_ops->tuner_ops;
122 if (tuner_ops->set_state) {
123 if (frontend_ops->i2c_gate_ctrl)
124 frontend_ops->i2c_gate_ctrl(fe, 1);
125
126 err = tuner_ops->set_state(fe, DVBFE_TUNER_BANDWIDTH, &state);
127 if (err < 0) {
128 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
129 return err;
130 }
131
132 if (frontend_ops->i2c_gate_ctrl)
133 frontend_ops->i2c_gate_ctrl(fe, 0);
134
135 }
136
137 return 0;
138}
diff --git a/drivers/media/dvb/frontends/stv0900.h b/drivers/media/dvb/frontends/stv0900.h
index bf4e9b633044..29c3fa85c227 100644
--- a/drivers/media/dvb/frontends/stv0900.h
+++ b/drivers/media/dvb/frontends/stv0900.h
@@ -36,6 +36,7 @@ struct stv0900_reg {
36 36
37struct stv0900_config { 37struct stv0900_config {
38 u8 demod_address; 38 u8 demod_address;
39 u8 demod_mode;
39 u32 xtal; 40 u32 xtal;
40 u8 clkmode;/* 0 for CLKI, 2 for XTALI */ 41 u8 clkmode;/* 0 for CLKI, 2 for XTALI */
41 42
@@ -48,6 +49,8 @@ struct stv0900_config {
48 u8 tun2_maddress; 49 u8 tun2_maddress;
49 u8 tun1_adc;/* 1 for stv6110, 2 for stb6100 */ 50 u8 tun1_adc;/* 1 for stv6110, 2 for stb6100 */
50 u8 tun2_adc; 51 u8 tun2_adc;
52 /* Set device param to start dma */
53 int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
51}; 54};
52 55
53#if defined(CONFIG_DVB_STV0900) || (defined(CONFIG_DVB_STV0900_MODULE) \ 56#if defined(CONFIG_DVB_STV0900) || (defined(CONFIG_DVB_STV0900_MODULE) \
diff --git a/drivers/media/dvb/frontends/stv0900_core.c b/drivers/media/dvb/frontends/stv0900_core.c
index 3bde3324a032..df49ea0983bc 100644
--- a/drivers/media/dvb/frontends/stv0900_core.c
+++ b/drivers/media/dvb/frontends/stv0900_core.c
@@ -34,7 +34,7 @@
34#include "stv0900_priv.h" 34#include "stv0900_priv.h"
35#include "stv0900_init.h" 35#include "stv0900_init.h"
36 36
37static int stvdebug = 1; 37int stvdebug = 1;
38module_param_named(debug, stvdebug, int, 0644); 38module_param_named(debug, stvdebug, int, 0644);
39 39
40/* internal params node */ 40/* internal params node */
@@ -105,7 +105,8 @@ static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
105 while (new_node->next_inode != NULL) 105 while (new_node->next_inode != NULL)
106 new_node = new_node->next_inode; 106 new_node = new_node->next_inode;
107 107
108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL); 108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
109 GFP_KERNEL);
109 if (new_node->next_inode != NULL) 110 if (new_node->next_inode != NULL)
110 new_node = new_node->next_inode; 111 new_node = new_node->next_inode;
111 else 112 else
@@ -128,13 +129,13 @@ s32 ge2comp(s32 a, s32 width)
128 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a; 129 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
129} 130}
130 131
131void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr, 132void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
132 u8 reg_data) 133 u8 reg_data)
133{ 134{
134 u8 data[3]; 135 u8 data[3];
135 int ret; 136 int ret;
136 struct i2c_msg i2cmsg = { 137 struct i2c_msg i2cmsg = {
137 .addr = i_params->i2c_addr, 138 .addr = intp->i2c_addr,
138 .flags = 0, 139 .flags = 0,
139 .len = 3, 140 .len = 3,
140 .buf = data, 141 .buf = data,
@@ -144,33 +145,33 @@ void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
144 data[1] = LSB(reg_addr); 145 data[1] = LSB(reg_addr);
145 data[2] = reg_data; 146 data[2] = reg_data;
146 147
147 ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1); 148 ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
148 if (ret != 1) 149 if (ret != 1)
149 dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret); 150 dprintk("%s: i2c error %d\n", __func__, ret);
150} 151}
151 152
152u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg) 153u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
153{ 154{
154 int ret; 155 int ret;
155 u8 b0[] = { MSB(reg), LSB(reg) }; 156 u8 b0[] = { MSB(reg), LSB(reg) };
156 u8 buf = 0; 157 u8 buf = 0;
157 struct i2c_msg msg[] = { 158 struct i2c_msg msg[] = {
158 { 159 {
159 .addr = i_params->i2c_addr, 160 .addr = intp->i2c_addr,
160 .flags = 0, 161 .flags = 0,
161 .buf = b0, 162 .buf = b0,
162 .len = 2, 163 .len = 2,
163 }, { 164 }, {
164 .addr = i_params->i2c_addr, 165 .addr = intp->i2c_addr,
165 .flags = I2C_M_RD, 166 .flags = I2C_M_RD,
166 .buf = &buf, 167 .buf = &buf,
167 .len = 1, 168 .len = 1,
168 }, 169 },
169 }; 170 };
170 171
171 ret = i2c_transfer(i_params->i2c_adap, msg, 2); 172 ret = i2c_transfer(intp->i2c_adap, msg, 2);
172 if (ret != 2) 173 if (ret != 2)
173 dprintk(KERN_ERR "%s: i2c error %d, reg[0x%02x]\n", 174 dprintk("%s: i2c error %d, reg[0x%02x]\n",
174 __func__, ret, reg); 175 __func__, ret, reg);
175 176
176 return buf; 177 return buf;
@@ -190,169 +191,165 @@ void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
190 (*pos) = (i - 1); 191 (*pos) = (i - 1);
191} 192}
192 193
193void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val) 194void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
194{ 195{
195 u8 reg, mask, pos; 196 u8 reg, mask, pos;
196 197
197 reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff); 198 reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
198 extract_mask_pos(label, &mask, &pos); 199 extract_mask_pos(label, &mask, &pos);
199 200
200 val = mask & (val << pos); 201 val = mask & (val << pos);
201 202
202 reg = (reg & (~mask)) | val; 203 reg = (reg & (~mask)) | val;
203 stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg); 204 stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
204 205
205} 206}
206 207
207u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label) 208u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
208{ 209{
209 u8 val = 0xff; 210 u8 val = 0xff;
210 u8 mask, pos; 211 u8 mask, pos;
211 212
212 extract_mask_pos(label, &mask, &pos); 213 extract_mask_pos(label, &mask, &pos);
213 214
214 val = stv0900_read_reg(i_params, label >> 16); 215 val = stv0900_read_reg(intp, label >> 16);
215 val = (val & mask) >> pos; 216 val = (val & mask) >> pos;
216 217
217 return val; 218 return val;
218} 219}
219 220
220enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params) 221enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
221{ 222{
222 s32 i; 223 s32 i;
223 enum fe_stv0900_error error;
224
225 if (i_params != NULL) {
226 i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
227 if (i_params->errs == STV0900_NO_ERROR) {
228 /*Startup sequence*/
229 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
230 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
231 stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
232 stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
233 stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x20);
234 stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x20);
235 stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
236 msleep(3);
237 stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
238
239 switch (i_params->clkmode) {
240 case 0:
241 case 2:
242 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
243 | i_params->clkmode);
244 break;
245 default:
246 /* preserve SELOSCI bit */
247 i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
248 stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
249 break;
250 }
251 224
252 msleep(3); 225 if (intp == NULL)
253 for (i = 0; i < 182; i++) 226 return STV0900_INVALID_HANDLE;
254 stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
255 227
256 if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) { 228 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
257 stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
258 for (i = 0; i < 32; i++)
259 stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
260 }
261 229
262 stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c); 230 if (intp->errs != STV0900_NO_ERROR)
263 stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c); 231 return intp->errs;
264 stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
265 stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
266 }
267 error = i_params->errs;
268 } else
269 error = STV0900_INVALID_HANDLE;
270 232
271 return error; 233 /*Startup sequence*/
234 stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
235 stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
236 msleep(3);
237 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
238 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
239 stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
240 stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
241 stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
242 msleep(3);
243 stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
272 244
245 switch (intp->clkmode) {
246 case 0:
247 case 2:
248 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
249 | intp->clkmode);
250 break;
251 default:
252 /* preserve SELOSCI bit */
253 i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
254 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
255 break;
256 }
257
258 msleep(3);
259 for (i = 0; i < 181; i++)
260 stv0900_write_reg(intp, STV0900_InitVal[i][0],
261 STV0900_InitVal[i][1]);
262
263 if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
264 stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
265 for (i = 0; i < 32; i++)
266 stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
267 STV0900_Cut20_AddOnVal[i][1]);
268 }
269
270 stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
271 stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
272
273 stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
274 stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
275
276 stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
277 stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
278
279 stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
280 stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
281
282 return STV0900_NO_ERROR;
273} 283}
274 284
275u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk) 285u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
276{ 286{
277 u32 mclk = 90000000, div = 0, ad_div = 0; 287 u32 mclk = 90000000, div = 0, ad_div = 0;
278 288
279 div = stv0900_get_bits(i_params, F0900_M_DIV); 289 div = stv0900_get_bits(intp, F0900_M_DIV);
280 ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6); 290 ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
281 291
282 mclk = (div + 1) * ext_clk / ad_div; 292 mclk = (div + 1) * ext_clk / ad_div;
283 293
284 dprintk(KERN_INFO "%s: Calculated Mclk = %d\n", __func__, mclk); 294 dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
285 295
286 return mclk; 296 return mclk;
287} 297}
288 298
289enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk) 299enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
290{ 300{
291 enum fe_stv0900_error error = STV0900_NO_ERROR;
292 u32 m_div, clk_sel; 301 u32 m_div, clk_sel;
293 302
294 dprintk(KERN_INFO "%s: Mclk set to %d, Quartz = %d\n", __func__, mclk, 303 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
295 i_params->quartz); 304 intp->quartz);
296 305
297 if (i_params == NULL) 306 if (intp == NULL)
298 error = STV0900_INVALID_HANDLE; 307 return STV0900_INVALID_HANDLE;
299 else {
300 if (i_params->errs)
301 error = STV0900_I2C_ERROR;
302 else {
303 clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
304 m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
305 stv0900_write_bits(i_params, F0900_M_DIV, m_div);
306 i_params->mclk = stv0900_get_mclk_freq(i_params,
307 i_params->quartz);
308
309 /*Set the DiseqC frequency to 22KHz */
310 /*
311 Formula:
312 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
313 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
314 */
315 m_div = i_params->mclk / 704000;
316 stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
317 stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
318
319 stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
320 stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
321
322 if ((i_params->errs))
323 error = STV0900_I2C_ERROR;
324 }
325 }
326 308
327 return error; 309 if (intp->errs)
310 return STV0900_I2C_ERROR;
311
312 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
313 m_div = ((clk_sel * mclk) / intp->quartz) - 1;
314 stv0900_write_bits(intp, F0900_M_DIV, m_div);
315 intp->mclk = stv0900_get_mclk_freq(intp,
316 intp->quartz);
317
318 /*Set the DiseqC frequency to 22KHz */
319 /*
320 Formula:
321 DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
322 DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
323 */
324 m_div = intp->mclk / 704000;
325 stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
326 stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
327
328 stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
329 stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
330
331 if ((intp->errs))
332 return STV0900_I2C_ERROR;
333
334 return STV0900_NO_ERROR;
328} 335}
329 336
330u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr, 337u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
331 enum fe_stv0900_demod_num demod) 338 enum fe_stv0900_demod_num demod)
332{ 339{
333 u32 lsb, msb, hsb, err_val; 340 u32 lsb, msb, hsb, err_val;
334 s32 err1field_hsb, err1field_msb, err1field_lsb;
335 s32 err2field_hsb, err2field_msb, err2field_lsb;
336
337 dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
338 dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
339 dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
340
341 dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
342 dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
343 dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
344 341
345 switch (cntr) { 342 switch (cntr) {
346 case 0: 343 case 0:
347 default: 344 default:
348 hsb = stv0900_get_bits(i_params, err1field_hsb); 345 hsb = stv0900_get_bits(intp, ERR_CNT12);
349 msb = stv0900_get_bits(i_params, err1field_msb); 346 msb = stv0900_get_bits(intp, ERR_CNT11);
350 lsb = stv0900_get_bits(i_params, err1field_lsb); 347 lsb = stv0900_get_bits(intp, ERR_CNT10);
351 break; 348 break;
352 case 1: 349 case 1:
353 hsb = stv0900_get_bits(i_params, err2field_hsb); 350 hsb = stv0900_get_bits(intp, ERR_CNT22);
354 msb = stv0900_get_bits(i_params, err2field_msb); 351 msb = stv0900_get_bits(intp, ERR_CNT21);
355 lsb = stv0900_get_bits(i_params, err2field_lsb); 352 lsb = stv0900_get_bits(intp, ERR_CNT20);
356 break; 353 break;
357 } 354 }
358 355
@@ -364,26 +361,22 @@ u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
364static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 361static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
365{ 362{
366 struct stv0900_state *state = fe->demodulator_priv; 363 struct stv0900_state *state = fe->demodulator_priv;
367 struct stv0900_internal *i_params = state->internal; 364 struct stv0900_internal *intp = state->internal;
368 enum fe_stv0900_demod_num demod = state->demod; 365 enum fe_stv0900_demod_num demod = state->demod;
369 366
370 u32 fi2c; 367 stv0900_write_bits(intp, I2CT_ON, enable);
371
372 dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
373
374 stv0900_write_bits(i_params, fi2c, enable);
375 368
376 return 0; 369 return 0;
377} 370}
378 371
379static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params, 372static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
380 enum fe_stv0900_clock_type path1_ts, 373 enum fe_stv0900_clock_type path1_ts,
381 enum fe_stv0900_clock_type path2_ts) 374 enum fe_stv0900_clock_type path2_ts)
382{ 375{
383 376
384 dprintk(KERN_INFO "%s\n", __func__); 377 dprintk("%s\n", __func__);
385 378
386 if (i_params->chip_id >= 0x20) { 379 if (intp->chip_id >= 0x20) {
387 switch (path1_ts) { 380 switch (path1_ts) {
388 case STV0900_PARALLEL_PUNCT_CLOCK: 381 case STV0900_PARALLEL_PUNCT_CLOCK:
389 case STV0900_DVBCI_CLOCK: 382 case STV0900_DVBCI_CLOCK:
@@ -391,20 +384,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
391 case STV0900_SERIAL_PUNCT_CLOCK: 384 case STV0900_SERIAL_PUNCT_CLOCK:
392 case STV0900_SERIAL_CONT_CLOCK: 385 case STV0900_SERIAL_CONT_CLOCK:
393 default: 386 default:
394 stv0900_write_reg(i_params, R0900_TSGENERAL, 387 stv0900_write_reg(intp, R0900_TSGENERAL,
395 0x00); 388 0x00);
396 break; 389 break;
397 case STV0900_PARALLEL_PUNCT_CLOCK: 390 case STV0900_PARALLEL_PUNCT_CLOCK:
398 case STV0900_DVBCI_CLOCK: 391 case STV0900_DVBCI_CLOCK:
399 stv0900_write_reg(i_params, R0900_TSGENERAL, 392 stv0900_write_reg(intp, R0900_TSGENERAL,
400 0x06); 393 0x06);
401 stv0900_write_bits(i_params, 394 stv0900_write_bits(intp,
402 F0900_P1_TSFIFO_MANSPEED, 3); 395 F0900_P1_TSFIFO_MANSPEED, 3);
403 stv0900_write_bits(i_params, 396 stv0900_write_bits(intp,
404 F0900_P2_TSFIFO_MANSPEED, 0); 397 F0900_P2_TSFIFO_MANSPEED, 0);
405 stv0900_write_reg(i_params, 398 stv0900_write_reg(intp,
406 R0900_P1_TSSPEED, 0x14); 399 R0900_P1_TSSPEED, 0x14);
407 stv0900_write_reg(i_params, 400 stv0900_write_reg(intp,
408 R0900_P2_TSSPEED, 0x28); 401 R0900_P2_TSSPEED, 0x28);
409 break; 402 break;
410 } 403 }
@@ -416,14 +409,14 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
416 case STV0900_SERIAL_PUNCT_CLOCK: 409 case STV0900_SERIAL_PUNCT_CLOCK:
417 case STV0900_SERIAL_CONT_CLOCK: 410 case STV0900_SERIAL_CONT_CLOCK:
418 default: 411 default:
419 stv0900_write_reg(i_params, 412 stv0900_write_reg(intp,
420 R0900_TSGENERAL, 0x0C); 413 R0900_TSGENERAL, 0x0C);
421 break; 414 break;
422 case STV0900_PARALLEL_PUNCT_CLOCK: 415 case STV0900_PARALLEL_PUNCT_CLOCK:
423 case STV0900_DVBCI_CLOCK: 416 case STV0900_DVBCI_CLOCK:
424 stv0900_write_reg(i_params, 417 stv0900_write_reg(intp,
425 R0900_TSGENERAL, 0x0A); 418 R0900_TSGENERAL, 0x0A);
426 dprintk(KERN_INFO "%s: 0x0a\n", __func__); 419 dprintk("%s: 0x0a\n", __func__);
427 break; 420 break;
428 } 421 }
429 break; 422 break;
@@ -436,20 +429,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
436 case STV0900_SERIAL_PUNCT_CLOCK: 429 case STV0900_SERIAL_PUNCT_CLOCK:
437 case STV0900_SERIAL_CONT_CLOCK: 430 case STV0900_SERIAL_CONT_CLOCK:
438 default: 431 default:
439 stv0900_write_reg(i_params, R0900_TSGENERAL1X, 432 stv0900_write_reg(intp, R0900_TSGENERAL1X,
440 0x10); 433 0x10);
441 break; 434 break;
442 case STV0900_PARALLEL_PUNCT_CLOCK: 435 case STV0900_PARALLEL_PUNCT_CLOCK:
443 case STV0900_DVBCI_CLOCK: 436 case STV0900_DVBCI_CLOCK:
444 stv0900_write_reg(i_params, R0900_TSGENERAL1X, 437 stv0900_write_reg(intp, R0900_TSGENERAL1X,
445 0x16); 438 0x16);
446 stv0900_write_bits(i_params, 439 stv0900_write_bits(intp,
447 F0900_P1_TSFIFO_MANSPEED, 3); 440 F0900_P1_TSFIFO_MANSPEED, 3);
448 stv0900_write_bits(i_params, 441 stv0900_write_bits(intp,
449 F0900_P2_TSFIFO_MANSPEED, 0); 442 F0900_P2_TSFIFO_MANSPEED, 0);
450 stv0900_write_reg(i_params, R0900_P1_TSSPEED, 443 stv0900_write_reg(intp, R0900_P1_TSSPEED,
451 0x14); 444 0x14);
452 stv0900_write_reg(i_params, R0900_P2_TSSPEED, 445 stv0900_write_reg(intp, R0900_P2_TSSPEED,
453 0x28); 446 0x28);
454 break; 447 break;
455 } 448 }
@@ -462,14 +455,14 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
462 case STV0900_SERIAL_PUNCT_CLOCK: 455 case STV0900_SERIAL_PUNCT_CLOCK:
463 case STV0900_SERIAL_CONT_CLOCK: 456 case STV0900_SERIAL_CONT_CLOCK:
464 default: 457 default:
465 stv0900_write_reg(i_params, R0900_TSGENERAL1X, 458 stv0900_write_reg(intp, R0900_TSGENERAL1X,
466 0x14); 459 0x14);
467 break; 460 break;
468 case STV0900_PARALLEL_PUNCT_CLOCK: 461 case STV0900_PARALLEL_PUNCT_CLOCK:
469 case STV0900_DVBCI_CLOCK: 462 case STV0900_DVBCI_CLOCK:
470 stv0900_write_reg(i_params, R0900_TSGENERAL1X, 463 stv0900_write_reg(intp, R0900_TSGENERAL1X,
471 0x12); 464 0x12);
472 dprintk(KERN_INFO "%s: 0x12\n", __func__); 465 dprintk("%s: 0x12\n", __func__);
473 break; 466 break;
474 } 467 }
475 468
@@ -479,20 +472,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
479 472
480 switch (path1_ts) { 473 switch (path1_ts) {
481 case STV0900_PARALLEL_PUNCT_CLOCK: 474 case STV0900_PARALLEL_PUNCT_CLOCK:
482 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00); 475 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
483 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00); 476 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
484 break; 477 break;
485 case STV0900_DVBCI_CLOCK: 478 case STV0900_DVBCI_CLOCK:
486 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00); 479 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
487 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01); 480 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
488 break; 481 break;
489 case STV0900_SERIAL_PUNCT_CLOCK: 482 case STV0900_SERIAL_PUNCT_CLOCK:
490 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01); 483 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
491 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00); 484 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
492 break; 485 break;
493 case STV0900_SERIAL_CONT_CLOCK: 486 case STV0900_SERIAL_CONT_CLOCK:
494 stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01); 487 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
495 stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01); 488 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
496 break; 489 break;
497 default: 490 default:
498 break; 491 break;
@@ -500,29 +493,29 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
500 493
501 switch (path2_ts) { 494 switch (path2_ts) {
502 case STV0900_PARALLEL_PUNCT_CLOCK: 495 case STV0900_PARALLEL_PUNCT_CLOCK:
503 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00); 496 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
504 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00); 497 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
505 break; 498 break;
506 case STV0900_DVBCI_CLOCK: 499 case STV0900_DVBCI_CLOCK:
507 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00); 500 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
508 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01); 501 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
509 break; 502 break;
510 case STV0900_SERIAL_PUNCT_CLOCK: 503 case STV0900_SERIAL_PUNCT_CLOCK:
511 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01); 504 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
512 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00); 505 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
513 break; 506 break;
514 case STV0900_SERIAL_CONT_CLOCK: 507 case STV0900_SERIAL_CONT_CLOCK:
515 stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01); 508 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
516 stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01); 509 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
517 break; 510 break;
518 default: 511 default:
519 break; 512 break;
520 } 513 }
521 514
522 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1); 515 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
523 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0); 516 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
524 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1); 517 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
525 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0); 518 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
526} 519}
527 520
528void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency, 521void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
@@ -574,7 +567,7 @@ void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
574 } 567 }
575} 568}
576 569
577static s32 stv0900_get_rf_level(struct stv0900_internal *i_params, 570static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
578 const struct stv0900_table *lookup, 571 const struct stv0900_table *lookup,
579 enum fe_stv0900_demod_num demod) 572 enum fe_stv0900_demod_num demod)
580{ 573{
@@ -584,45 +577,41 @@ static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
584 i, 577 i,
585 rf_lvl = 0; 578 rf_lvl = 0;
586 579
587 dprintk(KERN_INFO "%s\n", __func__); 580 dprintk("%s\n", __func__);
588 581
589 if ((lookup != NULL) && lookup->size) { 582 if ((lookup == NULL) || (lookup->size <= 0))
590 switch (demod) { 583 return 0;
591 case STV0900_DEMOD_1:
592 default:
593 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
594 stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
595 break;
596 case STV0900_DEMOD_2:
597 agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
598 stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
599 break;
600 }
601 584
602 imin = 0; 585 agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
603 imax = lookup->size - 1; 586 stv0900_get_bits(intp, AGCIQ_VALUE0));
604 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
605 while ((imax - imin) > 1) {
606 i = (imax + imin) >> 1;
607 587
608 if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval)) 588 imin = 0;
609 imax = i; 589 imax = lookup->size - 1;
610 else 590 if (INRANGE(lookup->table[imin].regval, agc_gain,
611 imin = i; 591 lookup->table[imax].regval)) {
612 } 592 while ((imax - imin) > 1) {
593 i = (imax + imin) >> 1;
613 594
614 rf_lvl = (((s32)agc_gain - lookup->table[imin].regval) 595 if (INRANGE(lookup->table[imin].regval,
615 * (lookup->table[imax].realval - lookup->table[imin].realval) 596 agc_gain,
616 / (lookup->table[imax].regval - lookup->table[imin].regval)) 597 lookup->table[i].regval))
617 + lookup->table[imin].realval; 598 imax = i;
618 } else if (agc_gain > lookup->table[0].regval) 599 else
619 rf_lvl = 5; 600 imin = i;
620 else if (agc_gain < lookup->table[lookup->size-1].regval) 601 }
621 rf_lvl = -100;
622 602
623 } 603 rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
604 rf_lvl *= (lookup->table[imax].realval -
605 lookup->table[imin].realval);
606 rf_lvl /= (lookup->table[imax].regval -
607 lookup->table[imin].regval);
608 rf_lvl += lookup->table[imin].realval;
609 } else if (agc_gain > lookup->table[0].regval)
610 rf_lvl = 5;
611 else if (agc_gain < lookup->table[lookup->size-1].regval)
612 rf_lvl = -100;
624 613
625 dprintk(KERN_INFO "%s: RFLevel = %d\n", __func__, rf_lvl); 614 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
626 615
627 return rf_lvl; 616 return rf_lvl;
628} 617}
@@ -634,50 +623,51 @@ static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
634 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf, 623 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
635 state->demod); 624 state->demod);
636 625
637 *strength = (rflevel + 100) * (16383 / 105); 626 rflevel = (rflevel + 100) * (65535 / 70);
627 if (rflevel < 0)
628 rflevel = 0;
629
630 if (rflevel > 65535)
631 rflevel = 65535;
632
633 *strength = rflevel;
638 634
639 return 0; 635 return 0;
640} 636}
641 637
642
643static s32 stv0900_carr_get_quality(struct dvb_frontend *fe, 638static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
644 const struct stv0900_table *lookup) 639 const struct stv0900_table *lookup)
645{ 640{
646 struct stv0900_state *state = fe->demodulator_priv; 641 struct stv0900_state *state = fe->demodulator_priv;
647 struct stv0900_internal *i_params = state->internal; 642 struct stv0900_internal *intp = state->internal;
648 enum fe_stv0900_demod_num demod = state->demod; 643 enum fe_stv0900_demod_num demod = state->demod;
649 644
650 s32 c_n = -100, 645 s32 c_n = -100,
651 regval, imin, imax, 646 regval,
647 imin,
648 imax,
652 i, 649 i,
653 lock_flag_field,
654 noise_field1, 650 noise_field1,
655 noise_field0; 651 noise_field0;
656 652
657 dprintk(KERN_INFO "%s\n", __func__); 653 dprintk("%s\n", __func__);
658 654
659 dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF,
660 F0900_P2_LOCK_DEFINITIF);
661 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) { 655 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
662 dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1, 656 noise_field1 = NOSPLHT_NORMED1;
663 F0900_P2_NOSPLHT_NORMED1); 657 noise_field0 = NOSPLHT_NORMED0;
664 dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0,
665 F0900_P2_NOSPLHT_NORMED0);
666 } else { 658 } else {
667 dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1, 659 noise_field1 = NOSDATAT_NORMED1;
668 F0900_P2_NOSDATAT_NORMED1); 660 noise_field0 = NOSDATAT_NORMED0;
669 dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0,
670 F0900_P2_NOSDATAT_NORMED0);
671 } 661 }
672 662
673 if (stv0900_get_bits(i_params, lock_flag_field)) { 663 if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
674 if ((lookup != NULL) && lookup->size) { 664 if ((lookup != NULL) && lookup->size) {
675 regval = 0; 665 regval = 0;
676 msleep(5); 666 msleep(5);
677 for (i = 0; i < 16; i++) { 667 for (i = 0; i < 16; i++) {
678 regval += MAKEWORD(stv0900_get_bits(i_params, 668 regval += MAKEWORD(stv0900_get_bits(intp,
679 noise_field1), 669 noise_field1),
680 stv0900_get_bits(i_params, 670 stv0900_get_bits(intp,
681 noise_field0)); 671 noise_field0));
682 msleep(1); 672 msleep(1);
683 } 673 }
@@ -715,10 +705,9 @@ static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
715static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) 705static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
716{ 706{
717 struct stv0900_state *state = fe->demodulator_priv; 707 struct stv0900_state *state = fe->demodulator_priv;
718 struct stv0900_internal *i_params = state->internal; 708 struct stv0900_internal *intp = state->internal;
719 enum fe_stv0900_demod_num demod = state->demod; 709 enum fe_stv0900_demod_num demod = state->demod;
720 u8 err_val1, err_val0; 710 u8 err_val1, err_val0;
721 s32 err_field1, err_field0;
722 u32 header_err_val = 0; 711 u32 header_err_val = 0;
723 712
724 *ucblocks = 0x0; 713 *ucblocks = 0x0;
@@ -726,24 +715,14 @@ static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
726 /* DVB-S2 delineator errors count */ 715 /* DVB-S2 delineator errors count */
727 716
728 /* retreiving number for errnous headers */ 717 /* retreiving number for errnous headers */
729 dmd_reg(err_field0, R0900_P1_BBFCRCKO0, 718 err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
730 R0900_P2_BBFCRCKO0); 719 err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
731 dmd_reg(err_field1, R0900_P1_BBFCRCKO1, 720 header_err_val = (err_val1 << 8) | err_val0;
732 R0900_P2_BBFCRCKO1);
733
734 err_val1 = stv0900_read_reg(i_params, err_field1);
735 err_val0 = stv0900_read_reg(i_params, err_field0);
736 header_err_val = (err_val1<<8) | err_val0;
737 721
738 /* retreiving number for errnous packets */ 722 /* retreiving number for errnous packets */
739 dmd_reg(err_field0, R0900_P1_UPCRCKO0, 723 err_val1 = stv0900_read_reg(intp, UPCRCKO1);
740 R0900_P2_UPCRCKO0); 724 err_val0 = stv0900_read_reg(intp, UPCRCKO0);
741 dmd_reg(err_field1, R0900_P1_UPCRCKO1, 725 *ucblocks = (err_val1 << 8) | err_val0;
742 R0900_P2_UPCRCKO1);
743
744 err_val1 = stv0900_read_reg(i_params, err_field1);
745 err_val0 = stv0900_read_reg(i_params, err_field0);
746 *ucblocks = (err_val1<<8) | err_val0;
747 *ucblocks += header_err_val; 726 *ucblocks += header_err_val;
748 } 727 }
749 728
@@ -752,33 +731,27 @@ static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
752 731
753static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr) 732static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
754{ 733{
755 *snr = stv0900_carr_get_quality(fe, 734 s32 snrlcl = stv0900_carr_get_quality(fe,
756 (const struct stv0900_table *)&stv0900_s2_cn); 735 (const struct stv0900_table *)&stv0900_s2_cn);
757 *snr += 30; 736 snrlcl = (snrlcl + 30) * 384;
758 *snr *= (16383 / 1030); 737 if (snrlcl < 0)
738 snrlcl = 0;
739
740 if (snrlcl > 65535)
741 snrlcl = 65535;
742
743 *snr = snrlcl;
759 744
760 return 0; 745 return 0;
761} 746}
762 747
763static u32 stv0900_get_ber(struct stv0900_internal *i_params, 748static u32 stv0900_get_ber(struct stv0900_internal *intp,
764 enum fe_stv0900_demod_num demod) 749 enum fe_stv0900_demod_num demod)
765{ 750{
766 u32 ber = 10000000, i; 751 u32 ber = 10000000, i;
767 s32 dmd_state_reg;
768 s32 demod_state; 752 s32 demod_state;
769 s32 vstatus_reg;
770 s32 prvit_field;
771 s32 pdel_status_reg;
772 s32 pdel_lock_field;
773
774 dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
775 dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
776 dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
777 dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
778 dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
779 F0900_P2_PKTDELIN_LOCK);
780 753
781 demod_state = stv0900_get_bits(i_params, dmd_state_reg); 754 demod_state = stv0900_get_bits(intp, HEADER_MODE);
782 755
783 switch (demod_state) { 756 switch (demod_state) {
784 case STV0900_SEARCH: 757 case STV0900_SEARCH:
@@ -790,11 +763,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
790 ber = 0; 763 ber = 0;
791 for (i = 0; i < 5; i++) { 764 for (i = 0; i < 5; i++) {
792 msleep(5); 765 msleep(5);
793 ber += stv0900_get_err_count(i_params, 0, demod); 766 ber += stv0900_get_err_count(intp, 0, demod);
794 } 767 }
795 768
796 ber /= 5; 769 ber /= 5;
797 if (stv0900_get_bits(i_params, prvit_field)) { 770 if (stv0900_get_bits(intp, PRFVIT)) {
798 ber *= 9766; 771 ber *= 9766;
799 ber = ber >> 13; 772 ber = ber >> 13;
800 } 773 }
@@ -804,11 +777,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
804 ber = 0; 777 ber = 0;
805 for (i = 0; i < 5; i++) { 778 for (i = 0; i < 5; i++) {
806 msleep(5); 779 msleep(5);
807 ber += stv0900_get_err_count(i_params, 0, demod); 780 ber += stv0900_get_err_count(intp, 0, demod);
808 } 781 }
809 782
810 ber /= 5; 783 ber /= 5;
811 if (stv0900_get_bits(i_params, pdel_lock_field)) { 784 if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
812 ber *= 9766; 785 ber *= 9766;
813 ber = ber >> 13; 786 ber = ber >> 13;
814 } 787 }
@@ -829,20 +802,16 @@ static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
829 return 0; 802 return 0;
830} 803}
831 804
832int stv0900_get_demod_lock(struct stv0900_internal *i_params, 805int stv0900_get_demod_lock(struct stv0900_internal *intp,
833 enum fe_stv0900_demod_num demod, s32 time_out) 806 enum fe_stv0900_demod_num demod, s32 time_out)
834{ 807{
835 s32 timer = 0, 808 s32 timer = 0,
836 lock = 0, 809 lock = 0;
837 header_field,
838 lock_field;
839 810
840 enum fe_stv0900_search_state dmd_state; 811 enum fe_stv0900_search_state dmd_state;
841 812
842 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
843 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
844 while ((timer < time_out) && (lock == 0)) { 813 while ((timer < time_out) && (lock == 0)) {
845 dmd_state = stv0900_get_bits(i_params, header_field); 814 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
846 dprintk("Demod State = %d\n", dmd_state); 815 dprintk("Demod State = %d\n", dmd_state);
847 switch (dmd_state) { 816 switch (dmd_state) {
848 case STV0900_SEARCH: 817 case STV0900_SEARCH:
@@ -852,7 +821,7 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
852 break; 821 break;
853 case STV0900_DVBS2_FOUND: 822 case STV0900_DVBS2_FOUND:
854 case STV0900_DVBS_FOUND: 823 case STV0900_DVBS_FOUND:
855 lock = stv0900_get_bits(i_params, lock_field); 824 lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
856 break; 825 break;
857 } 826 }
858 827
@@ -870,56 +839,40 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
870 return lock; 839 return lock;
871} 840}
872 841
873void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params, 842void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
874 enum fe_stv0900_demod_num demod) 843 enum fe_stv0900_demod_num demod)
875{ 844{
876 s32 regflist, 845 s32 regflist,
877 i; 846 i;
878 847
879 dprintk(KERN_INFO "%s\n", __func__); 848 dprintk("%s\n", __func__);
880 849
881 dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0); 850 regflist = MODCODLST0;
882 851
883 for (i = 0; i < 16; i++) 852 for (i = 0; i < 16; i++)
884 stv0900_write_reg(i_params, regflist + i, 0xff); 853 stv0900_write_reg(intp, regflist + i, 0xff);
885} 854}
886 855
887void stv0900_activate_s2_modcode(struct stv0900_internal *i_params, 856void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
888 enum fe_stv0900_demod_num demod) 857 enum fe_stv0900_demod_num demod)
889{ 858{
890 u32 matype, 859 u32 matype,
891 mod_code, 860 mod_code,
892 fmod, 861 fmod,
893 reg_index, 862 reg_index,
894 field_index; 863 field_index;
895 864
896 dprintk(KERN_INFO "%s\n", __func__); 865 dprintk("%s\n", __func__);
897 866
898 if (i_params->chip_id <= 0x11) { 867 if (intp->chip_id <= 0x11) {
899 msleep(5); 868 msleep(5);
900 869
901 switch (demod) { 870 mod_code = stv0900_read_reg(intp, PLHMODCOD);
902 case STV0900_DEMOD_1: 871 matype = mod_code & 0x3;
903 default: 872 mod_code = (mod_code & 0x7f) >> 2;
904 mod_code = stv0900_read_reg(i_params,
905 R0900_P1_PLHMODCOD);
906 matype = mod_code & 0x3;
907 mod_code = (mod_code & 0x7f) >> 2;
908
909 reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
910 field_index = mod_code % 2;
911 break;
912 case STV0900_DEMOD_2:
913 mod_code = stv0900_read_reg(i_params,
914 R0900_P2_PLHMODCOD);
915 matype = mod_code & 0x3;
916 mod_code = (mod_code & 0x7f) >> 2;
917
918 reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
919 field_index = mod_code % 2;
920 break;
921 }
922 873
874 reg_index = MODCODLSTF - mod_code / 2;
875 field_index = mod_code % 2;
923 876
924 switch (matype) { 877 switch (matype) {
925 case 0: 878 case 0:
@@ -938,70 +891,41 @@ void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
938 } 891 }
939 892
940 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910)) 893 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
941 && (matype <= 1)) { 894 && (matype <= 1)) {
942 if (field_index == 0) 895 if (field_index == 0)
943 stv0900_write_reg(i_params, reg_index, 896 stv0900_write_reg(intp, reg_index,
944 0xf0 | fmod); 897 0xf0 | fmod);
945 else 898 else
946 stv0900_write_reg(i_params, reg_index, 899 stv0900_write_reg(intp, reg_index,
947 (fmod << 4) | 0xf); 900 (fmod << 4) | 0xf);
948 } 901 }
949 } else if (i_params->chip_id >= 0x12) {
950 switch (demod) {
951 case STV0900_DEMOD_1:
952 default:
953 for (reg_index = 0; reg_index < 7; reg_index++)
954 stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
955 902
956 stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff); 903 } else if (intp->chip_id >= 0x12) {
957 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf); 904 for (reg_index = 0; reg_index < 7; reg_index++)
958 for (reg_index = 0; reg_index < 8; reg_index++) 905 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
959 stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
960 906
961 break; 907 stv0900_write_reg(intp, MODCODLSTE, 0xff);
962 case STV0900_DEMOD_2: 908 stv0900_write_reg(intp, MODCODLSTF, 0xcf);
963 for (reg_index = 0; reg_index < 7; reg_index++) 909 for (reg_index = 0; reg_index < 8; reg_index++)
964 stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff); 910 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
965 911
966 stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff);
967 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf);
968 for (reg_index = 0; reg_index < 8; reg_index++)
969 stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc);
970
971 break;
972 }
973 912
974 } 913 }
975} 914}
976 915
977void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params, 916void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
978 enum fe_stv0900_demod_num demod) 917 enum fe_stv0900_demod_num demod)
979{ 918{
980 u32 reg_index; 919 u32 reg_index;
981 920
982 dprintk(KERN_INFO "%s\n", __func__); 921 dprintk("%s\n", __func__);
983
984 switch (demod) {
985 case STV0900_DEMOD_1:
986 default:
987 stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff);
988 stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0);
989 stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
990 for (reg_index = 0; reg_index < 13; reg_index++)
991 stv0900_write_reg(i_params,
992 R0900_P1_MODCODLST2 + reg_index, 0);
993 922
994 break; 923 stv0900_write_reg(intp, MODCODLST0, 0xff);
995 case STV0900_DEMOD_2: 924 stv0900_write_reg(intp, MODCODLST1, 0xf0);
996 stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff); 925 stv0900_write_reg(intp, MODCODLSTF, 0x0f);
997 stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0); 926 for (reg_index = 0; reg_index < 13; reg_index++)
998 stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f); 927 stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
999 for (reg_index = 0; reg_index < 13; reg_index++)
1000 stv0900_write_reg(i_params,
1001 R0900_P2_MODCODLST2 + reg_index, 0);
1002 928
1003 break;
1004 }
1005} 929}
1006 930
1007static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe) 931static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
@@ -1012,7 +936,7 @@ static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
1012static int stb0900_set_property(struct dvb_frontend *fe, 936static int stb0900_set_property(struct dvb_frontend *fe,
1013 struct dtv_property *tvp) 937 struct dtv_property *tvp)
1014{ 938{
1015 dprintk(KERN_INFO "%s(..)\n", __func__); 939 dprintk("%s(..)\n", __func__);
1016 940
1017 return 0; 941 return 0;
1018} 942}
@@ -1020,166 +944,123 @@ static int stb0900_set_property(struct dvb_frontend *fe,
1020static int stb0900_get_property(struct dvb_frontend *fe, 944static int stb0900_get_property(struct dvb_frontend *fe,
1021 struct dtv_property *tvp) 945 struct dtv_property *tvp)
1022{ 946{
1023 dprintk(KERN_INFO "%s(..)\n", __func__); 947 dprintk("%s(..)\n", __func__);
1024 948
1025 return 0; 949 return 0;
1026} 950}
1027 951
1028void stv0900_start_search(struct stv0900_internal *i_params, 952void stv0900_start_search(struct stv0900_internal *intp,
1029 enum fe_stv0900_demod_num demod) 953 enum fe_stv0900_demod_num demod)
1030{ 954{
1031 955 u32 freq;
1032 switch (demod) { 956 s16 freq_s16 ;
1033 case STV0900_DEMOD_1: 957
1034 default: 958 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1035 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f); 959 if (intp->chip_id == 0x10)
1036 960 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1037 if (i_params->chip_id == 0x10) 961
1038 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa); 962 if (intp->chip_id < 0x20)
1039 963 stv0900_write_reg(intp, CARHDR, 0x55);
1040 if (i_params->chip_id < 0x20) 964
1041 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55); 965 if (intp->chip_id <= 0x20) {
1042 966 if (intp->symbol_rate[0] <= 5000000) {
1043 if (i_params->dmd1_symbol_rate <= 5000000) { 967 stv0900_write_reg(intp, CARCFG, 0x44);
1044 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44); 968 stv0900_write_reg(intp, CFRUP1, 0x0f);
1045 stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f); 969 stv0900_write_reg(intp, CFRUP0, 0xff);
1046 stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff); 970 stv0900_write_reg(intp, CFRLOW1, 0xf0);
1047 stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0); 971 stv0900_write_reg(intp, CFRLOW0, 0x00);
1048 stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00); 972 stv0900_write_reg(intp, RTCS2, 0x68);
1049 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
1050 } else { 973 } else {
1051 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4); 974 stv0900_write_reg(intp, CARCFG, 0xc4);
1052 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44); 975 stv0900_write_reg(intp, RTCS2, 0x44);
1053 }
1054
1055 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
1056 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
1057
1058 if (i_params->chip_id >= 0x20) {
1059 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
1060 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
1061
1062 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
1063 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
1064 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
1065 }
1066 } 976 }
1067 977
1068 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00); 978 } else { /*cut 3.0 above*/
1069 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0); 979 if (intp->symbol_rate[demod] <= 5000000)
1070 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0); 980 stv0900_write_reg(intp, RTCS2, 0x68);
1071 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0); 981 else
1072 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0); 982 stv0900_write_reg(intp, RTCS2, 0x44);
1073 stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
1074 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
1075 if (i_params->chip_id >= 0x20) {
1076 if (i_params->dmd1_symbol_rate < 2000000) {
1077 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
1078 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
1079 }
1080
1081 if (i_params->dmd1_symbol_rate < 10000000) {
1082 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
1083 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1084 } else {
1085 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
1086 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
1087 }
1088 983
984 stv0900_write_reg(intp, CARCFG, 0x46);
985 if (intp->srch_algo[demod] == STV0900_WARM_START) {
986 freq = 1000 << 16;
987 freq /= (intp->mclk / 1000);
988 freq_s16 = (s16)freq;
1089 } else { 989 } else {
1090 if (i_params->dmd1_symbol_rate < 10000000) 990 freq = (intp->srch_range[demod] / 2000);
1091 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef); 991 if (intp->symbol_rate[demod] <= 5000000)
992 freq += 80;
1092 else 993 else
1093 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed); 994 freq += 600;
1094 }
1095 995
1096 switch (i_params->dmd1_srch_algo) { 996 freq = freq << 16;
1097 case STV0900_WARM_START: 997 freq /= (intp->mclk / 1000);
1098 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f); 998 freq_s16 = (s16)freq;
1099 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1100 break;
1101 case STV0900_COLD_START:
1102 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
1103 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
1104 break;
1105 default:
1106 break;
1107 }
1108
1109 break;
1110 case STV0900_DEMOD_2:
1111 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f);
1112 if (i_params->chip_id == 0x10)
1113 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
1114
1115 if (i_params->chip_id < 0x20)
1116 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
1117
1118 if (i_params->dmd2_symbol_rate <= 5000000) {
1119 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
1120 stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
1121 stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
1122 stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
1123 stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
1124 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
1125 } else {
1126 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
1127 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
1128 } 999 }
1129 1000
1130 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0); 1001 stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
1131 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0); 1002 stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
1003 freq_s16 *= (-1);
1004 stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
1005 stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
1006 }
1132 1007
1133 if (i_params->chip_id >= 0x20) { 1008 stv0900_write_reg(intp, CFRINIT1, 0);
1134 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41); 1009 stv0900_write_reg(intp, CFRINIT0, 0);
1135 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
1136 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
1137 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
1138 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
1139 }
1140 }
1141 1010
1142 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00); 1011 if (intp->chip_id >= 0x20) {
1143 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0); 1012 stv0900_write_reg(intp, EQUALCFG, 0x41);
1144 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0); 1013 stv0900_write_reg(intp, FFECFG, 0x41);
1145 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
1146 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1147 stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
1148 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
1149 if (i_params->chip_id >= 0x20) {
1150 if (i_params->dmd2_symbol_rate < 2000000) {
1151 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
1152 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
1153 }
1154 1014
1155 if (i_params->dmd2_symbol_rate < 10000000) { 1015 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
1156 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c); 1016 (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
1157 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20); 1017 (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
1158 } else { 1018 stv0900_write_reg(intp, VITSCALE,
1159 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b); 1019 0x82);
1160 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20); 1020 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1161 } 1021 }
1022 }
1162 1023
1024 stv0900_write_reg(intp, SFRSTEP, 0x00);
1025 stv0900_write_reg(intp, TMGTHRISE, 0xe0);
1026 stv0900_write_reg(intp, TMGTHFALL, 0xc0);
1027 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1028 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1029 stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
1030 stv0900_write_reg(intp, RTC, 0x88);
1031 if (intp->chip_id >= 0x20) {
1032 if (intp->symbol_rate[demod] < 2000000) {
1033 if (intp->chip_id <= 0x20)
1034 stv0900_write_reg(intp, CARFREQ, 0x39);
1035 else /*cut 3.0*/
1036 stv0900_write_reg(intp, CARFREQ, 0x89);
1037
1038 stv0900_write_reg(intp, CARHDR, 0x40);
1039 } else if (intp->symbol_rate[demod] < 10000000) {
1040 stv0900_write_reg(intp, CARFREQ, 0x4c);
1041 stv0900_write_reg(intp, CARHDR, 0x20);
1163 } else { 1042 } else {
1164 if (i_params->dmd2_symbol_rate < 10000000) 1043 stv0900_write_reg(intp, CARFREQ, 0x4b);
1165 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef); 1044 stv0900_write_reg(intp, CARHDR, 0x20);
1166 else
1167 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
1168 } 1045 }
1169 1046
1170 switch (i_params->dmd2_srch_algo) { 1047 } else {
1171 case STV0900_WARM_START: 1048 if (intp->symbol_rate[demod] < 10000000)
1172 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f); 1049 stv0900_write_reg(intp, CARFREQ, 0xef);
1173 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18); 1050 else
1174 break; 1051 stv0900_write_reg(intp, CARFREQ, 0xed);
1175 case STV0900_COLD_START: 1052 }
1176 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
1177 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
1178 break;
1179 default:
1180 break;
1181 }
1182 1053
1054 switch (intp->srch_algo[demod]) {
1055 case STV0900_WARM_START:
1056 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1057 stv0900_write_reg(intp, DMDISTATE, 0x18);
1058 break;
1059 case STV0900_COLD_START:
1060 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1061 stv0900_write_reg(intp, DMDISTATE, 0x15);
1062 break;
1063 default:
1183 break; 1064 break;
1184 } 1065 }
1185} 1066}
@@ -1188,33 +1069,40 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1188 s32 pilot, u8 chip_id) 1069 s32 pilot, u8 chip_id)
1189{ 1070{
1190 u8 aclc_value = 0x29; 1071 u8 aclc_value = 0x29;
1191 s32 i; 1072 s32 i;
1192 const struct stv0900_car_loop_optim *car_loop_s2; 1073 const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
1193 1074
1194 dprintk(KERN_INFO "%s\n", __func__); 1075 dprintk("%s\n", __func__);
1195 1076
1196 if (chip_id <= 0x12) 1077 if (chip_id <= 0x12) {
1197 car_loop_s2 = FE_STV0900_S2CarLoop; 1078 cls2 = FE_STV0900_S2CarLoop;
1198 else if (chip_id == 0x20) 1079 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1199 car_loop_s2 = FE_STV0900_S2CarLoopCut20; 1080 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1200 else 1081 } else if (chip_id == 0x20) {
1201 car_loop_s2 = FE_STV0900_S2CarLoop; 1082 cls2 = FE_STV0900_S2CarLoopCut20;
1083 cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
1084 cllas2 = FE_STV0900_S2APSKCarLoopCut20;
1085 } else {
1086 cls2 = FE_STV0900_S2CarLoopCut30;
1087 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1088 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1089 }
1202 1090
1203 if (modcode < STV0900_QPSK_12) { 1091 if (modcode < STV0900_QPSK_12) {
1204 i = 0; 1092 i = 0;
1205 while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode)) 1093 while ((i < 3) && (modcode != cllqs2[i].modcode))
1206 i++; 1094 i++;
1207 1095
1208 if (i >= 3) 1096 if (i >= 3)
1209 i = 2; 1097 i = 2;
1210 } else { 1098 } else {
1211 i = 0; 1099 i = 0;
1212 while ((i < 14) && (modcode != car_loop_s2[i].modcode)) 1100 while ((i < 14) && (modcode != cls2[i].modcode))
1213 i++; 1101 i++;
1214 1102
1215 if (i >= 14) { 1103 if (i >= 14) {
1216 i = 0; 1104 i = 0;
1217 while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode)) 1105 while ((i < 11) && (modcode != cllas2[i].modcode))
1218 i++; 1106 i++;
1219 1107
1220 if (i >= 11) 1108 if (i >= 11)
@@ -1225,76 +1113,82 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1225 if (modcode <= STV0900_QPSK_25) { 1113 if (modcode <= STV0900_QPSK_25) {
1226 if (pilot) { 1114 if (pilot) {
1227 if (srate <= 3000000) 1115 if (srate <= 3000000)
1228 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2; 1116 aclc_value = cllqs2[i].car_loop_pilots_on_2;
1229 else if (srate <= 7000000) 1117 else if (srate <= 7000000)
1230 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5; 1118 aclc_value = cllqs2[i].car_loop_pilots_on_5;
1231 else if (srate <= 15000000) 1119 else if (srate <= 15000000)
1232 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10; 1120 aclc_value = cllqs2[i].car_loop_pilots_on_10;
1233 else if (srate <= 25000000) 1121 else if (srate <= 25000000)
1234 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20; 1122 aclc_value = cllqs2[i].car_loop_pilots_on_20;
1235 else 1123 else
1236 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30; 1124 aclc_value = cllqs2[i].car_loop_pilots_on_30;
1237 } else { 1125 } else {
1238 if (srate <= 3000000) 1126 if (srate <= 3000000)
1239 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2; 1127 aclc_value = cllqs2[i].car_loop_pilots_off_2;
1240 else if (srate <= 7000000) 1128 else if (srate <= 7000000)
1241 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5; 1129 aclc_value = cllqs2[i].car_loop_pilots_off_5;
1242 else if (srate <= 15000000) 1130 else if (srate <= 15000000)
1243 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10; 1131 aclc_value = cllqs2[i].car_loop_pilots_off_10;
1244 else if (srate <= 25000000) 1132 else if (srate <= 25000000)
1245 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20; 1133 aclc_value = cllqs2[i].car_loop_pilots_off_20;
1246 else 1134 else
1247 aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30; 1135 aclc_value = cllqs2[i].car_loop_pilots_off_30;
1248 } 1136 }
1249 1137
1250 } else if (modcode <= STV0900_8PSK_910) { 1138 } else if (modcode <= STV0900_8PSK_910) {
1251 if (pilot) { 1139 if (pilot) {
1252 if (srate <= 3000000) 1140 if (srate <= 3000000)
1253 aclc_value = car_loop_s2[i].car_loop_pilots_on_2; 1141 aclc_value = cls2[i].car_loop_pilots_on_2;
1254 else if (srate <= 7000000) 1142 else if (srate <= 7000000)
1255 aclc_value = car_loop_s2[i].car_loop_pilots_on_5; 1143 aclc_value = cls2[i].car_loop_pilots_on_5;
1256 else if (srate <= 15000000) 1144 else if (srate <= 15000000)
1257 aclc_value = car_loop_s2[i].car_loop_pilots_on_10; 1145 aclc_value = cls2[i].car_loop_pilots_on_10;
1258 else if (srate <= 25000000) 1146 else if (srate <= 25000000)
1259 aclc_value = car_loop_s2[i].car_loop_pilots_on_20; 1147 aclc_value = cls2[i].car_loop_pilots_on_20;
1260 else 1148 else
1261 aclc_value = car_loop_s2[i].car_loop_pilots_on_30; 1149 aclc_value = cls2[i].car_loop_pilots_on_30;
1262 } else { 1150 } else {
1263 if (srate <= 3000000) 1151 if (srate <= 3000000)
1264 aclc_value = car_loop_s2[i].car_loop_pilots_off_2; 1152 aclc_value = cls2[i].car_loop_pilots_off_2;
1265 else if (srate <= 7000000) 1153 else if (srate <= 7000000)
1266 aclc_value = car_loop_s2[i].car_loop_pilots_off_5; 1154 aclc_value = cls2[i].car_loop_pilots_off_5;
1267 else if (srate <= 15000000) 1155 else if (srate <= 15000000)
1268 aclc_value = car_loop_s2[i].car_loop_pilots_off_10; 1156 aclc_value = cls2[i].car_loop_pilots_off_10;
1269 else if (srate <= 25000000) 1157 else if (srate <= 25000000)
1270 aclc_value = car_loop_s2[i].car_loop_pilots_off_20; 1158 aclc_value = cls2[i].car_loop_pilots_off_20;
1271 else 1159 else
1272 aclc_value = car_loop_s2[i].car_loop_pilots_off_30; 1160 aclc_value = cls2[i].car_loop_pilots_off_30;
1273 } 1161 }
1274 1162
1275 } else { 1163 } else {
1276 if (srate <= 3000000) 1164 if (srate <= 3000000)
1277 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2; 1165 aclc_value = cllas2[i].car_loop_pilots_on_2;
1278 else if (srate <= 7000000) 1166 else if (srate <= 7000000)
1279 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5; 1167 aclc_value = cllas2[i].car_loop_pilots_on_5;
1280 else if (srate <= 15000000) 1168 else if (srate <= 15000000)
1281 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10; 1169 aclc_value = cllas2[i].car_loop_pilots_on_10;
1282 else if (srate <= 25000000) 1170 else if (srate <= 25000000)
1283 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20; 1171 aclc_value = cllas2[i].car_loop_pilots_on_20;
1284 else 1172 else
1285 aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30; 1173 aclc_value = cllas2[i].car_loop_pilots_on_30;
1286 } 1174 }
1287 1175
1288 return aclc_value; 1176 return aclc_value;
1289} 1177}
1290 1178
1291u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id) 1179u8 stv0900_get_optim_short_carr_loop(s32 srate,
1180 enum fe_stv0900_modulation modulation,
1181 u8 chip_id)
1292{ 1182{
1183 const struct stv0900_short_frames_car_loop_optim *s2scl;
1184 const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
1293 s32 mod_index = 0; 1185 s32 mod_index = 0;
1294
1295 u8 aclc_value = 0x0b; 1186 u8 aclc_value = 0x0b;
1296 1187
1297 dprintk(KERN_INFO "%s\n", __func__); 1188 dprintk("%s\n", __func__);
1189
1190 s2scl = FE_STV0900_S2ShortCarLoop;
1191 s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
1298 1192
1299 switch (modulation) { 1193 switch (modulation) {
1300 case STV0900_QPSK: 1194 case STV0900_QPSK:
@@ -1312,75 +1206,116 @@ u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modul
1312 break; 1206 break;
1313 } 1207 }
1314 1208
1315 switch (chip_id) { 1209 if (chip_id >= 0x30) {
1316 case 0x20:
1317 if (srate <= 3000000) 1210 if (srate <= 3000000)
1318 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2; 1211 aclc_value = s2sclc30[mod_index].car_loop_2;
1319 else if (srate <= 7000000) 1212 else if (srate <= 7000000)
1320 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5; 1213 aclc_value = s2sclc30[mod_index].car_loop_5;
1321 else if (srate <= 15000000) 1214 else if (srate <= 15000000)
1322 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10; 1215 aclc_value = s2sclc30[mod_index].car_loop_10;
1323 else if (srate <= 25000000) 1216 else if (srate <= 25000000)
1324 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20; 1217 aclc_value = s2sclc30[mod_index].car_loop_20;
1325 else 1218 else
1326 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30; 1219 aclc_value = s2sclc30[mod_index].car_loop_30;
1327 1220
1328 break; 1221 } else if (chip_id >= 0x20) {
1329 case 0x12:
1330 default:
1331 if (srate <= 3000000) 1222 if (srate <= 3000000)
1332 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2; 1223 aclc_value = s2scl[mod_index].car_loop_cut20_2;
1333 else if (srate <= 7000000) 1224 else if (srate <= 7000000)
1334 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5; 1225 aclc_value = s2scl[mod_index].car_loop_cut20_5;
1335 else if (srate <= 15000000) 1226 else if (srate <= 15000000)
1336 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10; 1227 aclc_value = s2scl[mod_index].car_loop_cut20_10;
1337 else if (srate <= 25000000) 1228 else if (srate <= 25000000)
1338 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20; 1229 aclc_value = s2scl[mod_index].car_loop_cut20_20;
1339 else 1230 else
1340 aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30; 1231 aclc_value = s2scl[mod_index].car_loop_cut20_30;
1232
1233 } else {
1234 if (srate <= 3000000)
1235 aclc_value = s2scl[mod_index].car_loop_cut12_2;
1236 else if (srate <= 7000000)
1237 aclc_value = s2scl[mod_index].car_loop_cut12_5;
1238 else if (srate <= 15000000)
1239 aclc_value = s2scl[mod_index].car_loop_cut12_10;
1240 else if (srate <= 25000000)
1241 aclc_value = s2scl[mod_index].car_loop_cut12_20;
1242 else
1243 aclc_value = s2scl[mod_index].car_loop_cut12_30;
1341 1244
1342 break;
1343 } 1245 }
1344 1246
1345 return aclc_value; 1247 return aclc_value;
1346} 1248}
1347 1249
1348static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params, 1250static
1251enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
1349 enum fe_stv0900_demod_mode LDPC_Mode, 1252 enum fe_stv0900_demod_mode LDPC_Mode,
1350 enum fe_stv0900_demod_num demod) 1253 enum fe_stv0900_demod_num demod)
1351{ 1254{
1352 enum fe_stv0900_error error = STV0900_NO_ERROR; 1255 enum fe_stv0900_error error = STV0900_NO_ERROR;
1256 s32 reg_ind;
1353 1257
1354 dprintk(KERN_INFO "%s\n", __func__); 1258 dprintk("%s\n", __func__);
1355 1259
1356 switch (LDPC_Mode) { 1260 switch (LDPC_Mode) {
1357 case STV0900_DUAL: 1261 case STV0900_DUAL:
1358 default: 1262 default:
1359 if ((i_params->demod_mode != STV0900_DUAL) 1263 if ((intp->demod_mode != STV0900_DUAL)
1360 || (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) { 1264 || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
1361 stv0900_write_reg(i_params, R0900_GENCFG, 0x1d); 1265 stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
1362 1266
1363 i_params->demod_mode = STV0900_DUAL; 1267 intp->demod_mode = STV0900_DUAL;
1364 1268
1365 stv0900_write_bits(i_params, F0900_FRESFEC, 1); 1269 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1366 stv0900_write_bits(i_params, F0900_FRESFEC, 0); 1270 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1271
1272 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1273 stv0900_write_reg(intp,
1274 R0900_P1_MODCODLST0 + reg_ind,
1275 0xff);
1276 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1277 stv0900_write_reg(intp,
1278 R0900_P1_MODCODLST7 + reg_ind,
1279 0xcc);
1280
1281 stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
1282 stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
1283
1284 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1285 stv0900_write_reg(intp,
1286 R0900_P2_MODCODLST0 + reg_ind,
1287 0xff);
1288 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1289 stv0900_write_reg(intp,
1290 R0900_P2_MODCODLST7 + reg_ind,
1291 0xcc);
1292
1293 stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
1294 stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
1367 } 1295 }
1368 1296
1369 break; 1297 break;
1370 case STV0900_SINGLE: 1298 case STV0900_SINGLE:
1371 if (demod == STV0900_DEMOD_2) 1299 if (demod == STV0900_DEMOD_2) {
1372 stv0900_write_reg(i_params, R0900_GENCFG, 0x06); 1300 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
1373 else 1301 stv0900_activate_s2_modcod_single(intp,
1374 stv0900_write_reg(i_params, R0900_GENCFG, 0x04); 1302 STV0900_DEMOD_2);
1303 stv0900_write_reg(intp, R0900_GENCFG, 0x06);
1304 } else {
1305 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
1306 stv0900_activate_s2_modcod_single(intp,
1307 STV0900_DEMOD_1);
1308 stv0900_write_reg(intp, R0900_GENCFG, 0x04);
1309 }
1375 1310
1376 i_params->demod_mode = STV0900_SINGLE; 1311 intp->demod_mode = STV0900_SINGLE;
1377 1312
1378 stv0900_write_bits(i_params, F0900_FRESFEC, 1); 1313 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1379 stv0900_write_bits(i_params, F0900_FRESFEC, 0); 1314 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1380 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1); 1315 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
1381 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0); 1316 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
1382 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1); 1317 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
1383 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0); 1318 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
1384 break; 1319 break;
1385 } 1320 }
1386 1321
@@ -1393,131 +1328,131 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1393 struct stv0900_state *state = fe->demodulator_priv; 1328 struct stv0900_state *state = fe->demodulator_priv;
1394 enum fe_stv0900_error error = STV0900_NO_ERROR; 1329 enum fe_stv0900_error error = STV0900_NO_ERROR;
1395 enum fe_stv0900_error demodError = STV0900_NO_ERROR; 1330 enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1331 struct stv0900_internal *intp = NULL;
1332
1396 int selosci, i; 1333 int selosci, i;
1397 1334
1398 struct stv0900_inode *temp_int = find_inode(state->i2c_adap, 1335 struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1399 state->config->demod_address); 1336 state->config->demod_address);
1400 1337
1401 dprintk(KERN_INFO "%s\n", __func__); 1338 dprintk("%s\n", __func__);
1402 1339
1403 if (temp_int != NULL) { 1340 if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
1404 state->internal = temp_int->internal; 1341 state->internal = temp_int->internal;
1405 (state->internal->dmds_used)++; 1342 (state->internal->dmds_used)++;
1406 dprintk(KERN_INFO "%s: Find Internal Structure!\n", __func__); 1343 dprintk("%s: Find Internal Structure!\n", __func__);
1407 return STV0900_NO_ERROR; 1344 return STV0900_NO_ERROR;
1408 } else { 1345 } else {
1409 state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL); 1346 state->internal = kmalloc(sizeof(struct stv0900_internal),
1347 GFP_KERNEL);
1410 temp_int = append_internal(state->internal); 1348 temp_int = append_internal(state->internal);
1411 state->internal->dmds_used = 1; 1349 state->internal->dmds_used = 1;
1412 state->internal->i2c_adap = state->i2c_adap; 1350 state->internal->i2c_adap = state->i2c_adap;
1413 state->internal->i2c_addr = state->config->demod_address; 1351 state->internal->i2c_addr = state->config->demod_address;
1414 state->internal->clkmode = state->config->clkmode; 1352 state->internal->clkmode = state->config->clkmode;
1415 state->internal->errs = STV0900_NO_ERROR; 1353 state->internal->errs = STV0900_NO_ERROR;
1416 dprintk(KERN_INFO "%s: Create New Internal Structure!\n", __func__); 1354 dprintk("%s: Create New Internal Structure!\n", __func__);
1417 } 1355 }
1418 1356
1419 if (state->internal != NULL) { 1357 if (state->internal == NULL) {
1420 demodError = stv0900_initialize(state->internal); 1358 error = STV0900_INVALID_HANDLE;
1421 if (demodError == STV0900_NO_ERROR) { 1359 return error;
1422 error = STV0900_NO_ERROR; 1360 }
1423 } else {
1424 if (demodError == STV0900_INVALID_HANDLE)
1425 error = STV0900_INVALID_HANDLE;
1426 else
1427 error = STV0900_I2C_ERROR;
1428 }
1429 1361
1430 if (state->internal != NULL) { 1362 demodError = stv0900_initialize(state->internal);
1431 if (error == STV0900_NO_ERROR) { 1363 if (demodError == STV0900_NO_ERROR) {
1432 state->internal->demod_mode = p_init->demod_mode; 1364 error = STV0900_NO_ERROR;
1433 1365 } else {
1434 stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1); 1366 if (demodError == STV0900_INVALID_HANDLE)
1435 1367 error = STV0900_INVALID_HANDLE;
1436 state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID); 1368 else
1437 state->internal->rolloff = p_init->rolloff; 1369 error = STV0900_I2C_ERROR;
1438 state->internal->quartz = p_init->dmd_ref_clk;
1439
1440 stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1441 stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1442
1443 state->internal->ts_config = p_init->ts_config;
1444 if (state->internal->ts_config == NULL)
1445 stv0900_set_ts_parallel_serial(state->internal,
1446 p_init->path1_ts_clock,
1447 p_init->path2_ts_clock);
1448 else {
1449 for (i = 0; state->internal->ts_config[i].addr != 0xffff; i++)
1450 stv0900_write_reg(state->internal,
1451 state->internal->ts_config[i].addr,
1452 state->internal->ts_config[i].val);
1453
1454 stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 1);
1455 stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 0);
1456 stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 1);
1457 stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 0);
1458 }
1459 1370
1460 stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress); 1371 return error;
1461 switch (p_init->tuner1_adc) { 1372 }
1462 case 1:
1463 stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
1464 break;
1465 default:
1466 break;
1467 }
1468 1373
1469 stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress); 1374 if (state->internal == NULL) {
1470 switch (p_init->tuner2_adc) { 1375 error = STV0900_INVALID_HANDLE;
1471 case 1: 1376 return error;
1472 stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26); 1377 }
1473 break;
1474 default:
1475 break;
1476 }
1477 1378
1478 stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion); 1379 intp = state->internal;
1479 stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
1480 stv0900_set_mclk(state->internal, 135000000);
1481 msleep(3);
1482
1483 switch (state->internal->clkmode) {
1484 case 0:
1485 case 2:
1486 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
1487 break;
1488 default:
1489 selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
1490 stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
1491 break;
1492 }
1493 msleep(3);
1494 1380
1495 state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz); 1381 intp->demod_mode = p_init->demod_mode;
1496 if (state->internal->errs) 1382 stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
1497 error = STV0900_I2C_ERROR; 1383 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
1498 } 1384 intp->rolloff = p_init->rolloff;
1499 } else { 1385 intp->quartz = p_init->dmd_ref_clk;
1500 error = STV0900_INVALID_HANDLE; 1386
1501 } 1387 stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1388 stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1389
1390 intp->ts_config = p_init->ts_config;
1391 if (intp->ts_config == NULL)
1392 stv0900_set_ts_parallel_serial(intp,
1393 p_init->path1_ts_clock,
1394 p_init->path2_ts_clock);
1395 else {
1396 for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
1397 stv0900_write_reg(intp,
1398 intp->ts_config[i].addr,
1399 intp->ts_config[i].val);
1400
1401 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
1402 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
1403 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
1404 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
1405 }
1406
1407 stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1408 switch (p_init->tuner1_adc) {
1409 case 1:
1410 stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
1411 break;
1412 default:
1413 break;
1414 }
1415
1416 stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1417 switch (p_init->tuner2_adc) {
1418 case 1:
1419 stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
1420 break;
1421 default:
1422 break;
1423 }
1424
1425 stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
1426 stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
1427 stv0900_set_mclk(intp, 135000000);
1428 msleep(3);
1429
1430 switch (intp->clkmode) {
1431 case 0:
1432 case 2:
1433 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
1434 break;
1435 default:
1436 selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
1437 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
1438 break;
1502 } 1439 }
1440 msleep(3);
1441
1442 intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
1443 if (intp->errs)
1444 error = STV0900_I2C_ERROR;
1503 1445
1504 return error; 1446 return error;
1505} 1447}
1506 1448
1507static int stv0900_status(struct stv0900_internal *i_params, 1449static int stv0900_status(struct stv0900_internal *intp,
1508 enum fe_stv0900_demod_num demod) 1450 enum fe_stv0900_demod_num demod)
1509{ 1451{
1510 enum fe_stv0900_search_state demod_state; 1452 enum fe_stv0900_search_state demod_state;
1511 s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
1512 int locked = FALSE; 1453 int locked = FALSE;
1513 1454
1514 dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE); 1455 demod_state = stv0900_get_bits(intp, HEADER_MODE);
1515 dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
1516 dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1517 dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1518 dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1519
1520 demod_state = stv0900_get_bits(i_params, mode_field);
1521 switch (demod_state) { 1456 switch (demod_state) {
1522 case STV0900_SEARCH: 1457 case STV0900_SEARCH:
1523 case STV0900_PLH_DETECTED: 1458 case STV0900_PLH_DETECTED:
@@ -1525,17 +1460,19 @@ static int stv0900_status(struct stv0900_internal *i_params,
1525 locked = FALSE; 1460 locked = FALSE;
1526 break; 1461 break;
1527 case STV0900_DVBS2_FOUND: 1462 case STV0900_DVBS2_FOUND:
1528 locked = stv0900_get_bits(i_params, lock_field) && 1463 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1529 stv0900_get_bits(i_params, delin_field) && 1464 stv0900_get_bits(intp, PKTDELIN_LOCK) &&
1530 stv0900_get_bits(i_params, fifo_field); 1465 stv0900_get_bits(intp, TSFIFO_LINEOK);
1531 break; 1466 break;
1532 case STV0900_DVBS_FOUND: 1467 case STV0900_DVBS_FOUND:
1533 locked = stv0900_get_bits(i_params, lock_field) && 1468 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1534 stv0900_get_bits(i_params, lockedvit_field) && 1469 stv0900_get_bits(intp, LOCKEDVIT) &&
1535 stv0900_get_bits(i_params, fifo_field); 1470 stv0900_get_bits(intp, TSFIFO_LINEOK);
1536 break; 1471 break;
1537 } 1472 }
1538 1473
1474 dprintk("%s: locked = %d\n", __func__, locked);
1475
1539 return locked; 1476 return locked;
1540} 1477}
1541 1478
@@ -1543,7 +1480,8 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1543 struct dvb_frontend_parameters *params) 1480 struct dvb_frontend_parameters *params)
1544{ 1481{
1545 struct stv0900_state *state = fe->demodulator_priv; 1482 struct stv0900_state *state = fe->demodulator_priv;
1546 struct stv0900_internal *i_params = state->internal; 1483 struct stv0900_internal *intp = state->internal;
1484 enum fe_stv0900_demod_num demod = state->demod;
1547 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 1485 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1548 1486
1549 struct stv0900_search_params p_search; 1487 struct stv0900_search_params p_search;
@@ -1551,10 +1489,16 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1551 1489
1552 enum fe_stv0900_error error = STV0900_NO_ERROR; 1490 enum fe_stv0900_error error = STV0900_NO_ERROR;
1553 1491
1554 dprintk(KERN_INFO "%s: ", __func__); 1492 dprintk("%s: ", __func__);
1493
1494 if (!(INRANGE(100000, c->symbol_rate, 70000000)))
1495 return DVBFE_ALGO_SEARCH_FAILED;
1496
1497 if (state->config->set_ts_params)
1498 state->config->set_ts_params(fe, 0);
1555 1499
1556 p_result.locked = FALSE; 1500 p_result.locked = FALSE;
1557 p_search.path = state->demod; 1501 p_search.path = demod;
1558 p_search.frequency = c->frequency; 1502 p_search.frequency = c->frequency;
1559 p_search.symbol_rate = c->symbol_rate; 1503 p_search.symbol_rate = c->symbol_rate;
1560 p_search.search_range = 10000000; 1504 p_search.search_range = 10000000;
@@ -1563,103 +1507,47 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
1563 p_search.iq_inversion = STV0900_IQ_AUTO; 1507 p_search.iq_inversion = STV0900_IQ_AUTO;
1564 p_search.search_algo = STV0900_BLIND_SEARCH; 1508 p_search.search_algo = STV0900_BLIND_SEARCH;
1565 1509
1566 if ((INRANGE(100000, p_search.symbol_rate, 70000000)) && 1510 intp->srch_standard[demod] = p_search.standard;
1567 (INRANGE(100000, p_search.search_range, 50000000))) { 1511 intp->symbol_rate[demod] = p_search.symbol_rate;
1568 switch (p_search.path) { 1512 intp->srch_range[demod] = p_search.search_range;
1569 case STV0900_DEMOD_1: 1513 intp->freq[demod] = p_search.frequency;
1570 default: 1514 intp->srch_algo[demod] = p_search.search_algo;
1571 i_params->dmd1_srch_standard = p_search.standard; 1515 intp->srch_iq_inv[demod] = p_search.iq_inversion;
1572 i_params->dmd1_symbol_rate = p_search.symbol_rate; 1516 intp->fec[demod] = p_search.fec;
1573 i_params->dmd1_srch_range = p_search.search_range; 1517 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1574 i_params->tuner1_freq = p_search.frequency; 1518 (intp->errs == STV0900_NO_ERROR)) {
1575 i_params->dmd1_srch_algo = p_search.search_algo; 1519 p_result.locked = intp->result[demod].locked;
1576 i_params->dmd1_srch_iq_inv = p_search.iq_inversion; 1520 p_result.standard = intp->result[demod].standard;
1577 i_params->dmd1_fec = p_search.fec; 1521 p_result.frequency = intp->result[demod].frequency;
1522 p_result.symbol_rate = intp->result[demod].symbol_rate;
1523 p_result.fec = intp->result[demod].fec;
1524 p_result.modcode = intp->result[demod].modcode;
1525 p_result.pilot = intp->result[demod].pilot;
1526 p_result.frame_len = intp->result[demod].frame_len;
1527 p_result.spectrum = intp->result[demod].spectrum;
1528 p_result.rolloff = intp->result[demod].rolloff;
1529 p_result.modulation = intp->result[demod].modulation;
1530 } else {
1531 p_result.locked = FALSE;
1532 switch (intp->err[demod]) {
1533 case STV0900_I2C_ERROR:
1534 error = STV0900_I2C_ERROR;
1578 break; 1535 break;
1579 1536 case STV0900_NO_ERROR:
1580 case STV0900_DEMOD_2: 1537 default:
1581 i_params->dmd2_srch_stndrd = p_search.standard; 1538 error = STV0900_SEARCH_FAILED;
1582 i_params->dmd2_symbol_rate = p_search.symbol_rate;
1583 i_params->dmd2_srch_range = p_search.search_range;
1584 i_params->tuner2_freq = p_search.frequency;
1585 i_params->dmd2_srch_algo = p_search.search_algo;
1586 i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
1587 i_params->dmd2_fec = p_search.fec;
1588 break; 1539 break;
1589 } 1540 }
1590 1541 }
1591 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1592 (i_params->errs == STV0900_NO_ERROR)) {
1593 switch (p_search.path) {
1594 case STV0900_DEMOD_1:
1595 default:
1596 p_result.locked = i_params->dmd1_rslts.locked;
1597 p_result.standard = i_params->dmd1_rslts.standard;
1598 p_result.frequency = i_params->dmd1_rslts.frequency;
1599 p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
1600 p_result.fec = i_params->dmd1_rslts.fec;
1601 p_result.modcode = i_params->dmd1_rslts.modcode;
1602 p_result.pilot = i_params->dmd1_rslts.pilot;
1603 p_result.frame_length = i_params->dmd1_rslts.frame_length;
1604 p_result.spectrum = i_params->dmd1_rslts.spectrum;
1605 p_result.rolloff = i_params->dmd1_rslts.rolloff;
1606 p_result.modulation = i_params->dmd1_rslts.modulation;
1607 break;
1608 case STV0900_DEMOD_2:
1609 p_result.locked = i_params->dmd2_rslts.locked;
1610 p_result.standard = i_params->dmd2_rslts.standard;
1611 p_result.frequency = i_params->dmd2_rslts.frequency;
1612 p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
1613 p_result.fec = i_params->dmd2_rslts.fec;
1614 p_result.modcode = i_params->dmd2_rslts.modcode;
1615 p_result.pilot = i_params->dmd2_rslts.pilot;
1616 p_result.frame_length = i_params->dmd2_rslts.frame_length;
1617 p_result.spectrum = i_params->dmd2_rslts.spectrum;
1618 p_result.rolloff = i_params->dmd2_rslts.rolloff;
1619 p_result.modulation = i_params->dmd2_rslts.modulation;
1620 break;
1621 }
1622
1623 } else {
1624 p_result.locked = FALSE;
1625 switch (p_search.path) {
1626 case STV0900_DEMOD_1:
1627 switch (i_params->dmd1_err) {
1628 case STV0900_I2C_ERROR:
1629 error = STV0900_I2C_ERROR;
1630 break;
1631 case STV0900_NO_ERROR:
1632 default:
1633 error = STV0900_SEARCH_FAILED;
1634 break;
1635 }
1636 break;
1637 case STV0900_DEMOD_2:
1638 switch (i_params->dmd2_err) {
1639 case STV0900_I2C_ERROR:
1640 error = STV0900_I2C_ERROR;
1641 break;
1642 case STV0900_NO_ERROR:
1643 default:
1644 error = STV0900_SEARCH_FAILED;
1645 break;
1646 }
1647 break;
1648 }
1649 }
1650
1651 } else
1652 error = STV0900_BAD_PARAMETER;
1653 1542
1654 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) { 1543 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1655 dprintk(KERN_INFO "Search Success\n"); 1544 dprintk("Search Success\n");
1656 return DVBFE_ALGO_SEARCH_SUCCESS; 1545 return DVBFE_ALGO_SEARCH_SUCCESS;
1657 } else { 1546 } else {
1658 dprintk(KERN_INFO "Search Fail\n"); 1547 dprintk("Search Fail\n");
1659 return DVBFE_ALGO_SEARCH_FAILED; 1548 return DVBFE_ALGO_SEARCH_FAILED;
1660 } 1549 }
1661 1550
1662 return DVBFE_ALGO_SEARCH_ERROR;
1663} 1551}
1664 1552
1665static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status) 1553static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
@@ -1690,16 +1578,13 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1690{ 1578{
1691 1579
1692 struct stv0900_state *state = fe->demodulator_priv; 1580 struct stv0900_state *state = fe->demodulator_priv;
1693 struct stv0900_internal *i_params = state->internal; 1581 struct stv0900_internal *intp = state->internal;
1694 enum fe_stv0900_demod_num demod = state->demod; 1582 enum fe_stv0900_demod_num demod = state->demod;
1695 s32 rst_field;
1696
1697 dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
1698 1583
1699 if (stop_ts == TRUE) 1584 if (stop_ts == TRUE)
1700 stv0900_write_bits(i_params, rst_field, 1); 1585 stv0900_write_bits(intp, RST_HWARE, 1);
1701 else 1586 else
1702 stv0900_write_bits(i_params, rst_field, 0); 1587 stv0900_write_bits(intp, RST_HWARE, 0);
1703 1588
1704 return 0; 1589 return 0;
1705} 1590}
@@ -1707,23 +1592,19 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1707static int stv0900_diseqc_init(struct dvb_frontend *fe) 1592static int stv0900_diseqc_init(struct dvb_frontend *fe)
1708{ 1593{
1709 struct stv0900_state *state = fe->demodulator_priv; 1594 struct stv0900_state *state = fe->demodulator_priv;
1710 struct stv0900_internal *i_params = state->internal; 1595 struct stv0900_internal *intp = state->internal;
1711 enum fe_stv0900_demod_num demod = state->demod; 1596 enum fe_stv0900_demod_num demod = state->demod;
1712 s32 mode_field, reset_field;
1713 1597
1714 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE); 1598 stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
1715 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET); 1599 stv0900_write_bits(intp, DISEQC_RESET, 1);
1716 1600 stv0900_write_bits(intp, DISEQC_RESET, 0);
1717 stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
1718 stv0900_write_bits(i_params, reset_field, 1);
1719 stv0900_write_bits(i_params, reset_field, 0);
1720 1601
1721 return 0; 1602 return 0;
1722} 1603}
1723 1604
1724static int stv0900_init(struct dvb_frontend *fe) 1605static int stv0900_init(struct dvb_frontend *fe)
1725{ 1606{
1726 dprintk(KERN_INFO "%s\n", __func__); 1607 dprintk("%s\n", __func__);
1727 1608
1728 stv0900_stop_ts(fe, 1); 1609 stv0900_stop_ts(fe, 1);
1729 stv0900_diseqc_init(fe); 1610 stv0900_diseqc_init(fe);
@@ -1731,48 +1612,24 @@ static int stv0900_init(struct dvb_frontend *fe)
1731 return 0; 1612 return 0;
1732} 1613}
1733 1614
1734static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data, 1615static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
1735 u32 NbData, enum fe_stv0900_demod_num demod) 1616 u32 NbData, enum fe_stv0900_demod_num demod)
1736{ 1617{
1737 s32 i = 0; 1618 s32 i = 0;
1738 1619
1739 switch (demod) { 1620 stv0900_write_bits(intp, DIS_PRECHARGE, 1);
1740 case STV0900_DEMOD_1: 1621 while (i < NbData) {
1741 default: 1622 while (stv0900_get_bits(intp, FIFO_FULL))
1742 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1); 1623 ;/* checkpatch complains */
1743 while (i < NbData) { 1624 stv0900_write_reg(intp, DISTXDATA, data[i]);
1744 while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL)) 1625 i++;
1745 ;/* checkpatch complains */ 1626 }
1746 stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
1747 i++;
1748 }
1749
1750 stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
1751 i = 0;
1752 while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
1753 msleep(10);
1754 i++;
1755 }
1756
1757 break;
1758 case STV0900_DEMOD_2:
1759 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
1760
1761 while (i < NbData) {
1762 while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
1763 ;/* checkpatch complains */
1764 stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
1765 i++;
1766 }
1767
1768 stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0);
1769 i = 0;
1770 while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) {
1771 msleep(10);
1772 i++;
1773 }
1774 1627
1775 break; 1628 stv0900_write_bits(intp, DIS_PRECHARGE, 0);
1629 i = 0;
1630 while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
1631 msleep(10);
1632 i++;
1776 } 1633 }
1777 1634
1778 return 0; 1635 return 0;
@@ -1792,22 +1649,21 @@ static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1792static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) 1649static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1793{ 1650{
1794 struct stv0900_state *state = fe->demodulator_priv; 1651 struct stv0900_state *state = fe->demodulator_priv;
1795 struct stv0900_internal *i_params = state->internal; 1652 struct stv0900_internal *intp = state->internal;
1796 enum fe_stv0900_demod_num demod = state->demod; 1653 enum fe_stv0900_demod_num demod = state->demod;
1797 s32 mode_field; 1654 u8 data;
1798 u32 diseqc_fifo;
1799 1655
1800 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
1801 dmd_reg(diseqc_fifo, R0900_P1_DISTXDATA, R0900_P2_DISTXDATA);
1802 1656
1803 switch (burst) { 1657 switch (burst) {
1804 case SEC_MINI_A: 1658 case SEC_MINI_A:
1805 stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */ 1659 stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
1806 stv0900_write_reg(i_params, diseqc_fifo, 0x00); 1660 data = 0x00;
1661 stv0900_diseqc_send(intp, &data, 1, state->demod);
1807 break; 1662 break;
1808 case SEC_MINI_B: 1663 case SEC_MINI_B:
1809 stv0900_write_bits(i_params, mode_field, 2);/* Modulated */ 1664 stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
1810 stv0900_write_reg(i_params, diseqc_fifo, 0xff); 1665 data = 0xff;
1666 stv0900_diseqc_send(intp, &data, 1, state->demod);
1811 break; 1667 break;
1812 } 1668 }
1813 1669
@@ -1818,68 +1674,54 @@ static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1818 struct dvb_diseqc_slave_reply *reply) 1674 struct dvb_diseqc_slave_reply *reply)
1819{ 1675{
1820 struct stv0900_state *state = fe->demodulator_priv; 1676 struct stv0900_state *state = fe->demodulator_priv;
1821 struct stv0900_internal *i_params = state->internal; 1677 struct stv0900_internal *intp = state->internal;
1678 enum fe_stv0900_demod_num demod = state->demod;
1822 s32 i = 0; 1679 s32 i = 0;
1823 1680
1824 switch (state->demod) { 1681 reply->msg_len = 0;
1825 case STV0900_DEMOD_1:
1826 default:
1827 reply->msg_len = 0;
1828
1829 while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
1830 msleep(10);
1831 i++;
1832 }
1833
1834 if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
1835 reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
1836
1837 for (i = 0; i < reply->msg_len; i++)
1838 reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA);
1839 }
1840 break;
1841 case STV0900_DEMOD_2:
1842 reply->msg_len = 0;
1843 1682
1844 while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) { 1683 while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
1845 msleep(10); 1684 msleep(10);
1846 i++; 1685 i++;
1847 } 1686 }
1848 1687
1849 if (stv0900_get_bits(i_params, F0900_P2_RX_END)) { 1688 if (stv0900_get_bits(intp, RX_END)) {
1850 reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR); 1689 reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
1851 1690
1852 for (i = 0; i < reply->msg_len; i++) 1691 for (i = 0; i < reply->msg_len; i++)
1853 reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA); 1692 reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
1854 }
1855 break;
1856 } 1693 }
1857 1694
1858 return 0; 1695 return 0;
1859} 1696}
1860 1697
1861static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 1698static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
1862{ 1699{
1863 struct stv0900_state *state = fe->demodulator_priv; 1700 struct stv0900_state *state = fe->demodulator_priv;
1864 struct stv0900_internal *i_params = state->internal; 1701 struct stv0900_internal *intp = state->internal;
1865 enum fe_stv0900_demod_num demod = state->demod; 1702 enum fe_stv0900_demod_num demod = state->demod;
1866 s32 mode_field, reset_field;
1867
1868 dprintk(KERN_INFO "%s: %s\n", __func__, ((tone == 0) ? "Off" : "On"));
1869 1703
1870 dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE); 1704 dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
1871 dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
1872 1705
1873 if (tone) { 1706 switch (toneoff) {
1874 /*Set the DiseqC mode to 22Khz continues tone*/ 1707 case SEC_TONE_ON:
1875 stv0900_write_bits(i_params, mode_field, 0); 1708 /*Set the DiseqC mode to 22Khz _continues_ tone*/
1876 stv0900_write_bits(i_params, reset_field, 1); 1709 stv0900_write_bits(intp, DISTX_MODE, 0);
1710 stv0900_write_bits(intp, DISEQC_RESET, 1);
1877 /*release DiseqC reset to enable the 22KHz tone*/ 1711 /*release DiseqC reset to enable the 22KHz tone*/
1878 stv0900_write_bits(i_params, reset_field, 0); 1712 stv0900_write_bits(intp, DISEQC_RESET, 0);
1879 } else { 1713 break;
1880 stv0900_write_bits(i_params, mode_field, 0); 1714 case SEC_TONE_OFF:
1715 /*return diseqc mode to config->diseqc_mode.
1716 Usually it's without _continues_ tone */
1717 stv0900_write_bits(intp, DISTX_MODE,
1718 state->config->diseqc_mode);
1881 /*maintain the DiseqC reset to disable the 22KHz tone*/ 1719 /*maintain the DiseqC reset to disable the 22KHz tone*/
1882 stv0900_write_bits(i_params, reset_field, 1); 1720 stv0900_write_bits(intp, DISEQC_RESET, 1);
1721 stv0900_write_bits(intp, DISEQC_RESET, 0);
1722 break;
1723 default:
1724 return -EINVAL;
1883 } 1725 }
1884 1726
1885 return 0; 1727 return 0;
@@ -1889,11 +1731,11 @@ static void stv0900_release(struct dvb_frontend *fe)
1889{ 1731{
1890 struct stv0900_state *state = fe->demodulator_priv; 1732 struct stv0900_state *state = fe->demodulator_priv;
1891 1733
1892 dprintk(KERN_INFO "%s\n", __func__); 1734 dprintk("%s\n", __func__);
1893 1735
1894 if ((--(state->internal->dmds_used)) <= 0) { 1736 if ((--(state->internal->dmds_used)) <= 0) {
1895 1737
1896 dprintk(KERN_INFO "%s: Actually removing\n", __func__); 1738 dprintk("%s: Actually removing\n", __func__);
1897 1739
1898 remove_inode(state->internal); 1740 remove_inode(state->internal);
1899 kfree(state->internal); 1741 kfree(state->internal);
@@ -1963,17 +1805,17 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1963 case 0: 1805 case 0:
1964 case 1: 1806 case 1:
1965 init_params.dmd_ref_clk = config->xtal; 1807 init_params.dmd_ref_clk = config->xtal;
1966 init_params.demod_mode = STV0900_DUAL; 1808 init_params.demod_mode = config->demod_mode;
1967 init_params.rolloff = STV0900_35; 1809 init_params.rolloff = STV0900_35;
1968 init_params.path1_ts_clock = config->path1_mode; 1810 init_params.path1_ts_clock = config->path1_mode;
1969 init_params.tun1_maddress = config->tun1_maddress; 1811 init_params.tun1_maddress = config->tun1_maddress;
1970 init_params.tun1_iq_inversion = STV0900_IQ_NORMAL; 1812 init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
1971 init_params.tuner1_adc = config->tun1_adc; 1813 init_params.tuner1_adc = config->tun1_adc;
1972 init_params.path2_ts_clock = config->path2_mode; 1814 init_params.path2_ts_clock = config->path2_mode;
1973 init_params.ts_config = config->ts_config_regs; 1815 init_params.ts_config = config->ts_config_regs;
1974 init_params.tun2_maddress = config->tun2_maddress; 1816 init_params.tun2_maddress = config->tun2_maddress;
1975 init_params.tuner2_adc = config->tun2_adc; 1817 init_params.tuner2_adc = config->tun2_adc;
1976 init_params.tun2_iq_inversion = STV0900_IQ_SWAPPED; 1818 init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
1977 1819
1978 err_stv0900 = stv0900_init_internal(&state->frontend, 1820 err_stv0900 = stv0900_init_internal(&state->frontend,
1979 &init_params); 1821 &init_params);
diff --git a/drivers/media/dvb/frontends/stv0900_init.h b/drivers/media/dvb/frontends/stv0900_init.h
index ff388b47a4e3..b684df9995d8 100644
--- a/drivers/media/dvb/frontends/stv0900_init.h
+++ b/drivers/media/dvb/frontends/stv0900_init.h
@@ -141,85 +141,228 @@ struct stv0900_short_frames_car_loop_optim {
141 141
142}; 142};
143 143
144struct stv0900_short_frames_car_loop_optim_vs_mod {
145 enum fe_stv0900_modulation modulation;
146 u8 car_loop_2; /* SR<3msps */
147 u8 car_loop_5; /* 3<SR<=7msps */
148 u8 car_loop_10; /* 7<SR<=15msps */
149 u8 car_loop_20; /* 10<SR<=25msps */
150 u8 car_loop_30; /* 10<SR<=45msps */
151};
152
144/* Cut 1.x Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */ 153/* Cut 1.x Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */
145static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = { 154static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = {
146 /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 155 /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
147 { STV0900_QPSK_12, 0x1C, 0x0D, 0x1B, 0x2C, 0x3A, 0x1C, 0x2A, 0x3B, 0x2A, 0x1B }, 156 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
148 { STV0900_QPSK_35, 0x2C, 0x0D, 0x2B, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B, 0x2A, 0x0B }, 157 { STV0900_QPSK_12, 0x1C, 0x0D, 0x1B, 0x2C, 0x3A,
149 { STV0900_QPSK_23, 0x2C, 0x0D, 0x2B, 0x2C, 0x0B, 0x0C, 0x3A, 0x1B, 0x2A, 0x3A }, 158 0x1C, 0x2A, 0x3B, 0x2A, 0x1B },
150 { STV0900_QPSK_34, 0x3C, 0x0D, 0x3B, 0x1C, 0x0B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A }, 159 { STV0900_QPSK_35, 0x2C, 0x0D, 0x2B, 0x2C, 0x3A,
151 { STV0900_QPSK_45, 0x3C, 0x0D, 0x3B, 0x1C, 0x0B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A }, 160 0x0C, 0x3A, 0x2B, 0x2A, 0x0B },
152 { STV0900_QPSK_56, 0x0D, 0x0D, 0x3B, 0x1C, 0x0B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A }, 161 { STV0900_QPSK_23, 0x2C, 0x0D, 0x2B, 0x2C, 0x0B,
153 { STV0900_QPSK_89, 0x0D, 0x0D, 0x3B, 0x1C, 0x1B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A }, 162 0x0C, 0x3A, 0x1B, 0x2A, 0x3A },
154 { STV0900_QPSK_910, 0x1D, 0x0D, 0x3B, 0x1C, 0x1B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A }, 163 { STV0900_QPSK_34, 0x3C, 0x0D, 0x3B, 0x1C, 0x0B,
155 { STV0900_8PSK_35, 0x29, 0x3B, 0x09, 0x2B, 0x38, 0x0B, 0x18, 0x1A, 0x08, 0x0A }, 164 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
156 { STV0900_8PSK_23, 0x0A, 0x3B, 0x29, 0x2B, 0x19, 0x0B, 0x38, 0x1A, 0x18, 0x0A }, 165 { STV0900_QPSK_45, 0x3C, 0x0D, 0x3B, 0x1C, 0x0B,
157 { STV0900_8PSK_34, 0x3A, 0x3B, 0x2A, 0x2B, 0x39, 0x0B, 0x19, 0x1A, 0x38, 0x0A }, 166 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
158 { STV0900_8PSK_56, 0x1B, 0x3B, 0x0B, 0x2B, 0x1A, 0x0B, 0x39, 0x1A, 0x19, 0x0A }, 167 { STV0900_QPSK_56, 0x0D, 0x0D, 0x3B, 0x1C, 0x0B,
159 { STV0900_8PSK_89, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, 0x0B, 0x39, 0x1A, 0x29, 0x39 }, 168 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
160 { STV0900_8PSK_910, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, 0x0B, 0x39, 0x1A, 0x29, 0x39 } 169 { STV0900_QPSK_89, 0x0D, 0x0D, 0x3B, 0x1C, 0x1B,
170 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
171 { STV0900_QPSK_910, 0x1D, 0x0D, 0x3B, 0x1C, 0x1B,
172 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
173 { STV0900_8PSK_35, 0x29, 0x3B, 0x09, 0x2B, 0x38,
174 0x0B, 0x18, 0x1A, 0x08, 0x0A },
175 { STV0900_8PSK_23, 0x0A, 0x3B, 0x29, 0x2B, 0x19,
176 0x0B, 0x38, 0x1A, 0x18, 0x0A },
177 { STV0900_8PSK_34, 0x3A, 0x3B, 0x2A, 0x2B, 0x39,
178 0x0B, 0x19, 0x1A, 0x38, 0x0A },
179 { STV0900_8PSK_56, 0x1B, 0x3B, 0x0B, 0x2B, 0x1A,
180 0x0B, 0x39, 0x1A, 0x19, 0x0A },
181 { STV0900_8PSK_89, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A,
182 0x0B, 0x39, 0x1A, 0x29, 0x39 },
183 { STV0900_8PSK_910, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A,
184 0x0B, 0x39, 0x1A, 0x29, 0x39 }
161}; 185};
162 186
163 187
164/* Cut 2.0 Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */ 188/* Cut 2.0 Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */
165static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = { 189static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = {
166 /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 190 /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
167 { STV0900_QPSK_12, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D, 0x1F, 0x3D, 0x3E, 0x3D, 0x1E }, 191 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
168 { STV0900_QPSK_35, 0x2F, 0x3F, 0x2E, 0x2F, 0x3D, 0x0F, 0x0E, 0x2E, 0x3D, 0x0E }, 192 { STV0900_QPSK_12, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D,
169 { STV0900_QPSK_23, 0x2F, 0x3F, 0x2E, 0x2F, 0x0E, 0x0F, 0x0E, 0x1E, 0x3D, 0x3D }, 193 0x1F, 0x3D, 0x3E, 0x3D, 0x1E },
170 { STV0900_QPSK_34, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D }, 194 { STV0900_QPSK_35, 0x2F, 0x3F, 0x2E, 0x2F, 0x3D,
171 { STV0900_QPSK_45, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D }, 195 0x0F, 0x0E, 0x2E, 0x3D, 0x0E },
172 { STV0900_QPSK_56, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D }, 196 { STV0900_QPSK_23, 0x2F, 0x3F, 0x2E, 0x2F, 0x0E,
173 { STV0900_QPSK_89, 0x3F, 0x3F, 0x3E, 0x1F, 0x1E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D }, 197 0x0F, 0x0E, 0x1E, 0x3D, 0x3D },
174 { STV0900_QPSK_910, 0x3F, 0x3F, 0x3E, 0x1F, 0x1E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D }, 198 { STV0900_QPSK_34, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E,
175 { STV0900_8PSK_35, 0x3c, 0x0c, 0x1c, 0x3b, 0x0c, 0x3b, 0x2b, 0x2b, 0x1b, 0x2b }, 199 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
176 { STV0900_8PSK_23, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x3b, 0x0c, 0x2b, 0x2b, 0x2b }, 200 { STV0900_QPSK_45, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E,
177 { STV0900_8PSK_34, 0x0e, 0x1c, 0x3d, 0x0c, 0x0d, 0x3b, 0x2c, 0x3b, 0x0c, 0x2b }, 201 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
178 { STV0900_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d }, 202 { STV0900_QPSK_56, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E,
179 { STV0900_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d }, 203 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
180 { STV0900_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d } 204 { STV0900_QPSK_89, 0x3F, 0x3F, 0x3E, 0x1F, 0x1E,
205 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
206 { STV0900_QPSK_910, 0x3F, 0x3F, 0x3E, 0x1F, 0x1E,
207 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
208 { STV0900_8PSK_35, 0x3c, 0x0c, 0x1c, 0x3b, 0x0c,
209 0x3b, 0x2b, 0x2b, 0x1b, 0x2b },
210 { STV0900_8PSK_23, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c,
211 0x3b, 0x0c, 0x2b, 0x2b, 0x2b },
212 { STV0900_8PSK_34, 0x0e, 0x1c, 0x3d, 0x0c, 0x0d,
213 0x3b, 0x2c, 0x3b, 0x0c, 0x2b },
214 { STV0900_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d,
215 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
216 { STV0900_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d,
217 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
218 { STV0900_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d,
219 0x1e, 0x1d, 0x2d, 0x0d, 0x1d },
181}; 220};
182 221
183 222
184 223
185/* Cut 2.0 Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame */ 224/* Cut 2.0 Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame */
186static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = { 225static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = {
187 /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 226 /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
188 { STV0900_16APSK_23, 0x0C, 0x0C, 0x0C, 0x0C, 0x1D, 0x0C, 0x3C, 0x0C, 0x2C, 0x0C }, 227 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
189 { STV0900_16APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x0C, 0x2D, 0x0C, 0x1D, 0x0C }, 228 { STV0900_16APSK_23, 0x0C, 0x0C, 0x0C, 0x0C, 0x1D,
190 { STV0900_16APSK_45, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x0C, 0x3D, 0x0C, 0x2D, 0x0C }, 229 0x0C, 0x3C, 0x0C, 0x2C, 0x0C },
191 { STV0900_16APSK_56, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x0C, 0x3D, 0x0C, 0x2D, 0x0C }, 230 { STV0900_16APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0E,
192 { STV0900_16APSK_89, 0x0C, 0x0C, 0x0C, 0x0C, 0x2E, 0x0C, 0x0E, 0x0C, 0x3D, 0x0C }, 231 0x0C, 0x2D, 0x0C, 0x1D, 0x0C },
193 { STV0900_16APSK_910, 0x0C, 0x0C, 0x0C, 0x0C, 0x2E, 0x0C, 0x0E, 0x0C, 0x3D, 0x0C }, 232 { STV0900_16APSK_45, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E,
194 { STV0900_32APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C }, 233 0x0C, 0x3D, 0x0C, 0x2D, 0x0C },
195 { STV0900_32APSK_45, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C }, 234 { STV0900_16APSK_56, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E,
196 { STV0900_32APSK_56, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C }, 235 0x0C, 0x3D, 0x0C, 0x2D, 0x0C },
197 { STV0900_32APSK_89, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C }, 236 { STV0900_16APSK_89, 0x0C, 0x0C, 0x0C, 0x0C, 0x2E,
198 { STV0900_32APSK_910, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C } 237 0x0C, 0x0E, 0x0C, 0x3D, 0x0C },
238 { STV0900_16APSK_910, 0x0C, 0x0C, 0x0C, 0x0C, 0x2E,
239 0x0C, 0x0E, 0x0C, 0x3D, 0x0C },
240 { STV0900_32APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
241 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
242 { STV0900_32APSK_45, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
243 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
244 { STV0900_32APSK_56, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
245 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
246 { STV0900_32APSK_89, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
247 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
248 { STV0900_32APSK_910, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
249 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
199}; 250};
200 251
201 252
202/* Cut 2.0 Tracking carrier loop carrier QPSK 1/4 to QPSK 2/5 long Frame */ 253/* Cut 2.0 Tracking carrier loop carrier QPSK 1/4 to QPSK 2/5 long Frame */
203static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut20[3] = { 254static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut20[3] = {
204 /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */ 255 /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
205 { STV0900_QPSK_14, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D, 0x2F, 0x2D, 0x1F, 0x3D, 0x3E }, 256 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
206 { STV0900_QPSK_13, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D, 0x2F, 0x3D, 0x0F, 0x3D, 0x2E }, 257 { STV0900_QPSK_14, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D,
207 { STV0900_QPSK_25, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D, 0x1F, 0x3D, 0x3E, 0x3D, 0x2E } 258 0x2F, 0x2D, 0x1F, 0x3D, 0x3E },
259 { STV0900_QPSK_13, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D,
260 0x2F, 0x3D, 0x0F, 0x3D, 0x2E },
261 { STV0900_QPSK_25, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D,
262 0x1F, 0x3D, 0x3E, 0x3D, 0x2E }
208}; 263};
209 264
210 265
211/* Cut 2.0 Tracking carrier loop carrier short Frame, cut 1.2 and 2.0 */ 266/* Cut 2.0 Tracking carrier loop carrier short Frame, cut 1.2 and 2.0 */
212static const struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4] = { 267static const
213 /*Mod 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */ 268struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4] = {
214 { STV0900_QPSK, 0x3C, 0x2F, 0x2B, 0x2E, 0x0B, 0x0E, 0x3A, 0x0E, 0x2A, 0x3D }, 269 /*Mod 2Mcut1.2 2Mcut2.0 5Mcut1.2 5Mcut2.0 10Mcut1.2
215 { STV0900_8PSK, 0x0B, 0x3E, 0x2A, 0x0E, 0x0A, 0x2D, 0x19, 0x0D, 0x09, 0x3C }, 270 10Mcut2.0 20Mcut1.2 20M_cut2.0 30Mcut1.2 30Mcut2.0*/
216 { STV0900_16APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B, 0x1E, 0x3A, 0x3D, 0x2A, 0x2D }, 271 { STV0900_QPSK, 0x3C, 0x2F, 0x2B, 0x2E, 0x0B,
217 { STV0900_32APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B, 0x1E, 0x3A, 0x3D, 0x2A, 0x2D } 272 0x0E, 0x3A, 0x0E, 0x2A, 0x3D },
273 { STV0900_8PSK, 0x0B, 0x3E, 0x2A, 0x0E, 0x0A,
274 0x2D, 0x19, 0x0D, 0x09, 0x3C },
275 { STV0900_16APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B,
276 0x1E, 0x3A, 0x3D, 0x2A, 0x2D },
277 { STV0900_32APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B,
278 0x1E, 0x3A, 0x3D, 0x2A, 0x2D }
279};
280
281static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = {
282 /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
283 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
284 { STV0900_QPSK_12, 0x3C, 0x2C, 0x0C, 0x2C, 0x1B,
285 0x2C, 0x1B, 0x1C, 0x0B, 0x3B },
286 { STV0900_QPSK_35, 0x0D, 0x0D, 0x0C, 0x0D, 0x1B,
287 0x3C, 0x1B, 0x1C, 0x0B, 0x3B },
288 { STV0900_QPSK_23, 0x1D, 0x0D, 0x0C, 0x1D, 0x2B,
289 0x3C, 0x1B, 0x1C, 0x0B, 0x3B },
290 { STV0900_QPSK_34, 0x1D, 0x1D, 0x0C, 0x1D, 0x2B,
291 0x3C, 0x1B, 0x1C, 0x0B, 0x3B },
292 { STV0900_QPSK_45, 0x2D, 0x1D, 0x1C, 0x1D, 0x2B,
293 0x3C, 0x2B, 0x0C, 0x1B, 0x3B },
294 { STV0900_QPSK_56, 0x2D, 0x1D, 0x1C, 0x1D, 0x2B,
295 0x3C, 0x2B, 0x0C, 0x1B, 0x3B },
296 { STV0900_QPSK_89, 0x3D, 0x2D, 0x1C, 0x1D, 0x3B,
297 0x3C, 0x2B, 0x0C, 0x1B, 0x3B },
298 { STV0900_QPSK_910, 0x3D, 0x2D, 0x1C, 0x1D, 0x3B,
299 0x3C, 0x2B, 0x0C, 0x1B, 0x3B },
300 { STV0900_8PSK_35, 0x39, 0x19, 0x39, 0x19, 0x19,
301 0x19, 0x19, 0x19, 0x09, 0x19 },
302 { STV0900_8PSK_23, 0x2A, 0x39, 0x1A, 0x0A, 0x39,
303 0x0A, 0x29, 0x39, 0x29, 0x0A },
304 { STV0900_8PSK_34, 0x0B, 0x3A, 0x0B, 0x0B, 0x3A,
305 0x1B, 0x1A, 0x0B, 0x1A, 0x3A },
306 { STV0900_8PSK_56, 0x0C, 0x1B, 0x3B, 0x2B, 0x1B,
307 0x3B, 0x3A, 0x3B, 0x3A, 0x1B },
308 { STV0900_8PSK_89, 0x2C, 0x2C, 0x2C, 0x1C, 0x2B,
309 0x0C, 0x0B, 0x3B, 0x0B, 0x1B },
310 { STV0900_8PSK_910, 0x2C, 0x3C, 0x2C, 0x1C, 0x3B,
311 0x1C, 0x0B, 0x3B, 0x0B, 0x1B }
312};
313
314static const
315struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = {
316 /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
317 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
318 { STV0900_16APSK_23, 0x0A, 0x0A, 0x0A, 0x0A, 0x1A,
319 0x0A, 0x3A, 0x0A, 0x2A, 0x0A },
320 { STV0900_16APSK_34, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B,
321 0x0A, 0x3B, 0x0A, 0x1B, 0x0A },
322 { STV0900_16APSK_45, 0x0A, 0x0A, 0x0A, 0x0A, 0x1B,
323 0x0A, 0x3B, 0x0A, 0x2B, 0x0A },
324 { STV0900_16APSK_56, 0x0A, 0x0A, 0x0A, 0x0A, 0x1B,
325 0x0A, 0x3B, 0x0A, 0x2B, 0x0A },
326 { STV0900_16APSK_89, 0x0A, 0x0A, 0x0A, 0x0A, 0x2B,
327 0x0A, 0x0C, 0x0A, 0x3B, 0x0A },
328 { STV0900_16APSK_910, 0x0A, 0x0A, 0x0A, 0x0A, 0x2B,
329 0x0A, 0x0C, 0x0A, 0x3B, 0x0A },
330 { STV0900_32APSK_34, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
331 0x0A, 0x0A, 0x0A, 0x0A, 0x0A },
332 { STV0900_32APSK_45, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
333 0x0A, 0x0A, 0x0A, 0x0A, 0x0A },
334 { STV0900_32APSK_56, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
335 0x0A, 0x0A, 0x0A, 0x0A, 0x0A },
336 { STV0900_32APSK_89, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
337 0x0A, 0x0A, 0x0A, 0x0A, 0x0A },
338 { STV0900_32APSK_910, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
339 0x0A, 0x0A, 0x0A, 0x0A, 0x0A }
340};
341
342static const
343struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut30[3] = {
344 /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
345 10MPoff 20MPon 20MPoff 30MPon 30MPoff*/
346 { STV0900_QPSK_14, 0x0C, 0x3C, 0x0B, 0x3C, 0x2A,
347 0x2C, 0x2A, 0x1C, 0x3A, 0x3B },
348 { STV0900_QPSK_13, 0x0C, 0x3C, 0x0B, 0x3C, 0x2A,
349 0x2C, 0x3A, 0x0C, 0x3A, 0x2B },
350 { STV0900_QPSK_25, 0x1C, 0x3C, 0x1B, 0x3C, 0x3A,
351 0x1C, 0x3A, 0x3B, 0x3A, 0x2B }
352};
353
354static const struct stv0900_short_frames_car_loop_optim_vs_mod
355FE_STV0900_S2ShortCarLoopCut30[4] = {
356 /*Mod 2Mcut3.0 5Mcut3.0 10Mcut3.0 20Mcut3.0 30Mcut3.0*/
357 { STV0900_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
358 { STV0900_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
359 { STV0900_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
360 { STV0900_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
361
218}; 362};
219 363
220static const u16 STV0900_InitVal[182][2] = { 364static const u16 STV0900_InitVal[181][2] = {
221 { R0900_OUTCFG , 0x00 }, 365 { R0900_OUTCFG , 0x00 },
222 { R0900_MODECFG , 0xff },
223 { R0900_AGCRF1CFG , 0x11 }, 366 { R0900_AGCRF1CFG , 0x11 },
224 { R0900_AGCRF2CFG , 0x13 }, 367 { R0900_AGCRF2CFG , 0x13 },
225 { R0900_TSGENERAL1X , 0x14 }, 368 { R0900_TSGENERAL1X , 0x14 },
@@ -381,7 +524,7 @@ static const u16 STV0900_InitVal[182][2] = {
381 { R0900_GAINLLR_NF15 , 0x1A }, 524 { R0900_GAINLLR_NF15 , 0x1A },
382 { R0900_GAINLLR_NF16 , 0x1F }, 525 { R0900_GAINLLR_NF16 , 0x1F },
383 { R0900_GAINLLR_NF17 , 0x21 }, 526 { R0900_GAINLLR_NF17 , 0x21 },
384 { R0900_RCCFGH , 0x20 }, 527 { R0900_RCCFG2 , 0x20 },
385 { R0900_P1_FECM , 0x01 }, /*disable DSS modes*/ 528 { R0900_P1_FECM , 0x01 }, /*disable DSS modes*/
386 { R0900_P2_FECM , 0x01 }, /*disable DSS modes*/ 529 { R0900_P2_FECM , 0x01 }, /*disable DSS modes*/
387 { R0900_P1_PRVIT , 0x2F }, /*disable puncture rate 6/7*/ 530 { R0900_P1_PRVIT , 0x2F }, /*disable puncture rate 6/7*/
diff --git a/drivers/media/dvb/frontends/stv0900_priv.h b/drivers/media/dvb/frontends/stv0900_priv.h
index 5ed7a145c7d3..d8ba8a984abe 100644
--- a/drivers/media/dvb/frontends/stv0900_priv.h
+++ b/drivers/media/dvb/frontends/stv0900_priv.h
@@ -46,22 +46,6 @@
46#define FALSE (!TRUE) 46#define FALSE (!TRUE)
47#endif 47#endif
48 48
49#define dmd_reg(a, b, c) \
50 do { \
51 a = 0; \
52 switch (demod) { \
53 case STV0900_DEMOD_1: \
54 default: \
55 a = b; \
56 break; \
57 case STV0900_DEMOD_2: \
58 a = c; \
59 break; \
60 } \
61 } while (0)
62
63static int stvdebug;
64
65#define dprintk(args...) \ 49#define dprintk(args...) \
66 do { \ 50 do { \
67 if (stvdebug) \ 51 if (stvdebug) \
@@ -70,6 +54,8 @@ static int stvdebug;
70 54
71#define STV0900_MAXLOOKUPSIZE 500 55#define STV0900_MAXLOOKUPSIZE 500
72#define STV0900_BLIND_SEARCH_AGC2_TH 700 56#define STV0900_BLIND_SEARCH_AGC2_TH 700
57#define STV0900_BLIND_SEARCH_AGC2_TH_CUT30 1400
58#define IQPOWER_THRESHOLD 30
73 59
74/* One point of the lookup table */ 60/* One point of the lookup table */
75struct stv000_lookpoint { 61struct stv000_lookpoint {
@@ -263,14 +249,14 @@ struct stv0900_init_params{
263 int tuner1_adc; 249 int tuner1_adc;
264 250
265 /* IQ from the tuner1 to the demod */ 251 /* IQ from the tuner1 to the demod */
266 enum stv0900_iq_inversion tun1_iq_inversion; 252 enum stv0900_iq_inversion tun1_iq_inv;
267 enum fe_stv0900_clock_type path2_ts_clock; 253 enum fe_stv0900_clock_type path2_ts_clock;
268 254
269 u8 tun2_maddress; 255 u8 tun2_maddress;
270 int tuner2_adc; 256 int tuner2_adc;
271 257
272 /* IQ from the tuner2 to the demod */ 258 /* IQ from the tuner2 to the demod */
273 enum stv0900_iq_inversion tun2_iq_inversion; 259 enum stv0900_iq_inversion tun2_iq_inv;
274 struct stv0900_reg *ts_config; 260 struct stv0900_reg *ts_config;
275}; 261};
276 262
@@ -300,7 +286,7 @@ struct stv0900_signal_info {
300 enum fe_stv0900_modcode modcode; 286 enum fe_stv0900_modcode modcode;
301 enum fe_stv0900_modulation modulation; 287 enum fe_stv0900_modulation modulation;
302 enum fe_stv0900_pilot pilot; 288 enum fe_stv0900_pilot pilot;
303 enum fe_stv0900_frame_length frame_length; 289 enum fe_stv0900_frame_length frame_len;
304 enum stv0900_iq_inversion spectrum; 290 enum stv0900_iq_inversion spectrum;
305 enum fe_stv0900_rolloff rolloff; 291 enum fe_stv0900_rolloff rolloff;
306 292
@@ -318,47 +304,25 @@ struct stv0900_internal{
318 /* Demodulator use for single demod or for dual demod) */ 304 /* Demodulator use for single demod or for dual demod) */
319 enum fe_stv0900_demod_mode demod_mode; 305 enum fe_stv0900_demod_mode demod_mode;
320 306
321 /*Demod 1*/ 307 /*Demods */
322 s32 tuner1_freq; 308 s32 freq[2];
323 s32 tuner1_bw; 309 s32 bw[2];
324 s32 dmd1_symbol_rate; 310 s32 symbol_rate[2];
325 s32 dmd1_srch_range; 311 s32 srch_range[2];
326 312
327 /* algorithm for search Blind, Cold or Warm*/ 313 /* algorithm for search Blind, Cold or Warm*/
328 enum fe_stv0900_search_algo dmd1_srch_algo; 314 enum fe_stv0900_search_algo srch_algo[2];
329 /* search standard: Auto, DVBS1/DSS only or DVBS2 only*/ 315 /* search standard: Auto, DVBS1/DSS only or DVBS2 only*/
330 enum fe_stv0900_search_standard dmd1_srch_standard; 316 enum fe_stv0900_search_standard srch_standard[2];
331 /* inversion search : auto, auto norma first, normal or inverted */ 317 /* inversion search : auto, auto norma first, normal or inverted */
332 enum fe_stv0900_search_iq dmd1_srch_iq_inv; 318 enum fe_stv0900_search_iq srch_iq_inv[2];
333 enum fe_stv0900_modcode dmd1_modcode; 319 enum fe_stv0900_modcode modcode[2];
334 enum fe_stv0900_modulation dmd1_modulation; 320 enum fe_stv0900_modulation modulation[2];
335 enum fe_stv0900_fec dmd1_fec; 321 enum fe_stv0900_fec fec[2];
336
337 struct stv0900_signal_info dmd1_rslts;
338 enum fe_stv0900_signal_type dmd1_state;
339 322
340 enum fe_stv0900_error dmd1_err; 323 struct stv0900_signal_info result[2];
324 enum fe_stv0900_error err[2];
341 325
342 /*Demod 2*/
343 s32 tuner2_freq;
344 s32 tuner2_bw;
345 s32 dmd2_symbol_rate;
346 s32 dmd2_srch_range;
347
348 enum fe_stv0900_search_algo dmd2_srch_algo;
349 enum fe_stv0900_search_standard dmd2_srch_stndrd;
350 /* inversion search : auto, auto normal first, normal or inverted */
351 enum fe_stv0900_search_iq dmd2_srch_iq_inv;
352 enum fe_stv0900_modcode dmd2_modcode;
353 enum fe_stv0900_modulation dmd2_modulation;
354 enum fe_stv0900_fec dmd2_fec;
355
356 /* results of the search*/
357 struct stv0900_signal_info dmd2_rslts;
358 /* current state of the search algorithm */
359 enum fe_stv0900_signal_type dmd2_state;
360
361 enum fe_stv0900_error dmd2_err;
362 326
363 struct i2c_adapter *i2c_adap; 327 struct i2c_adapter *i2c_adap;
364 u8 i2c_addr; 328 u8 i2c_addr;
@@ -379,6 +343,8 @@ struct stv0900_state {
379 int demod; 343 int demod;
380}; 344};
381 345
346extern int stvdebug;
347
382extern s32 ge2comp(s32 a, s32 width); 348extern s32 ge2comp(s32 a, s32 width);
383 349
384extern void stv0900_write_reg(struct stv0900_internal *i_params, 350extern void stv0900_write_reg(struct stv0900_internal *i_params,
@@ -418,13 +384,14 @@ extern u8 stv0900_get_optim_short_carr_loop(s32 srate,
418extern void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params, 384extern void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
419 enum fe_stv0900_demod_num demod); 385 enum fe_stv0900_demod_num demod);
420 386
421extern void stv0900_activate_s2_modcode(struct stv0900_internal *i_params, 387extern void stv0900_activate_s2_modcod(struct stv0900_internal *i_params,
422 enum fe_stv0900_demod_num demod); 388 enum fe_stv0900_demod_num demod);
423 389
424extern void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params, 390extern void stv0900_activate_s2_modcod_single(struct stv0900_internal *i_params,
425 enum fe_stv0900_demod_num demod); 391 enum fe_stv0900_demod_num demod);
426 392
427extern enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe, 393extern enum
394fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
428 enum fe_stv0900_demod_num demod); 395 enum fe_stv0900_demod_num demod);
429 396
430#endif 397#endif
diff --git a/drivers/media/dvb/frontends/stv0900_reg.h b/drivers/media/dvb/frontends/stv0900_reg.h
index 264f9cf9a17e..7b8edf192e97 100644
--- a/drivers/media/dvb/frontends/stv0900_reg.h
+++ b/drivers/media/dvb/frontends/stv0900_reg.h
@@ -14,7 +14,7 @@
14 * 14 *
15 * This program is distributed in the hope that it will be useful, 15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * 18 *
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
@@ -26,3762 +26,3950 @@
26#ifndef STV0900_REG_H 26#ifndef STV0900_REG_H
27#define STV0900_REG_H 27#define STV0900_REG_H
28 28
29extern s32 shiftx(s32 x, int demod, s32 shift);
30
31#define REGx(x) shiftx(x, demod, 0x200)
32#define FLDx(x) shiftx(x, demod, 0x2000000)
33
29/*MID*/ 34/*MID*/
30#define R0900_MID 0xf100 35#define R0900_MID 0xf100
31#define F0900_MCHIP_IDENT 0xf10000f0 36#define F0900_MCHIP_IDENT 0xf10000f0
32#define F0900_MRELEASE 0xf100000f 37#define F0900_MRELEASE 0xf100000f
33 38
34/*DACR1*/ 39/*DACR1*/
35#define R0900_DACR1 0xf113 40#define R0900_DACR1 0xf113
36#define F0900_DAC_MODE 0xf11300e0 41#define F0900_DAC_MODE 0xf11300e0
37#define F0900_DAC_VALUE1 0xf113000f 42#define F0900_DAC_VALUE1 0xf113000f
38 43
39/*DACR2*/ 44/*DACR2*/
40#define R0900_DACR2 0xf114 45#define R0900_DACR2 0xf114
41#define F0900_DAC_VALUE0 0xf11400ff 46#define F0900_DAC_VALUE0 0xf11400ff
42 47
43/*OUTCFG*/ 48/*OUTCFG*/
44#define R0900_OUTCFG 0xf11c 49#define R0900_OUTCFG 0xf11c
45#define F0900_INV_DATA6 0xf11c0080 50#define F0900_OUTSERRS1_HZ 0xf11c0040
46#define F0900_OUTSERRS1_HZ 0xf11c0040 51#define F0900_OUTSERRS2_HZ 0xf11c0020
47#define F0900_OUTSERRS2_HZ 0xf11c0020 52#define F0900_OUTSERRS3_HZ 0xf11c0010
48#define F0900_OUTSERRS3_HZ 0xf11c0010 53#define F0900_OUTPARRS3_HZ 0xf11c0008
49#define F0900_OUTPARRS3_HZ 0xf11c0008
50#define F0900_OUTHZ3_CONTROL 0xf11c0007
51
52/*MODECFG*/
53#define R0900_MODECFG 0xf11d
54#define F0900_FECSPY_SEL_2 0xf11d0020
55#define F0900_HWARE_SEL_2 0xf11d0010
56#define F0900_PKTDEL_SEL_2 0xf11d0008
57#define F0900_DISEQC_SEL_2 0xf11d0004
58#define F0900_VIT_SEL_2 0xf11d0002
59#define F0900_DEMOD_SEL_2 0xf11d0001
60 54
61/*IRQSTATUS3*/ 55/*IRQSTATUS3*/
62#define R0900_IRQSTATUS3 0xf120 56#define R0900_IRQSTATUS3 0xf120
63#define F0900_SPLL_LOCK 0xf1200020 57#define F0900_SPLL_LOCK 0xf1200020
64#define F0900_SSTREAM_LCK_3 0xf1200010 58#define F0900_SSTREAM_LCK_3 0xf1200010
65#define F0900_SSTREAM_LCK_2 0xf1200008 59#define F0900_SSTREAM_LCK_2 0xf1200008
66#define F0900_SSTREAM_LCK_1 0xf1200004 60#define F0900_SSTREAM_LCK_1 0xf1200004
67#define F0900_SDVBS1_PRF_2 0xf1200002 61#define F0900_SDVBS1_PRF_2 0xf1200002
68#define F0900_SDVBS1_PRF_1 0xf1200001 62#define F0900_SDVBS1_PRF_1 0xf1200001
69 63
70/*IRQSTATUS2*/ 64/*IRQSTATUS2*/
71#define R0900_IRQSTATUS2 0xf121 65#define R0900_IRQSTATUS2 0xf121
72#define F0900_SSPY_ENDSIM_3 0xf1210080 66#define F0900_SSPY_ENDSIM_3 0xf1210080
73#define F0900_SSPY_ENDSIM_2 0xf1210040 67#define F0900_SSPY_ENDSIM_2 0xf1210040
74#define F0900_SSPY_ENDSIM_1 0xf1210020 68#define F0900_SSPY_ENDSIM_1 0xf1210020
75#define F0900_SPKTDEL_ERROR_2 0xf1210010 69#define F0900_SPKTDEL_ERROR_2 0xf1210010
76#define F0900_SPKTDEL_LOCKB_2 0xf1210008 70#define F0900_SPKTDEL_LOCKB_2 0xf1210008
77#define F0900_SPKTDEL_LOCK_2 0xf1210004 71#define F0900_SPKTDEL_LOCK_2 0xf1210004
78#define F0900_SPKTDEL_ERROR_1 0xf1210002 72#define F0900_SPKTDEL_ERROR_1 0xf1210002
79#define F0900_SPKTDEL_LOCKB_1 0xf1210001 73#define F0900_SPKTDEL_LOCKB_1 0xf1210001
80 74
81/*IRQSTATUS1*/ 75/*IRQSTATUS1*/
82#define R0900_IRQSTATUS1 0xf122 76#define R0900_IRQSTATUS1 0xf122
83#define F0900_SPKTDEL_LOCK_1 0xf1220080 77#define F0900_SPKTDEL_LOCK_1 0xf1220080
84#define F0900_SEXTPINB2 0xf1220040 78#define F0900_SDEMOD_LOCKB_2 0xf1220004
85#define F0900_SEXTPIN2 0xf1220020 79#define F0900_SDEMOD_LOCK_2 0xf1220002
86#define F0900_SEXTPINB1 0xf1220010 80#define F0900_SDEMOD_IRQ_2 0xf1220001
87#define F0900_SEXTPIN1 0xf1220008
88#define F0900_SDEMOD_LOCKB_2 0xf1220004
89#define F0900_SDEMOD_LOCK_2 0xf1220002
90#define F0900_SDEMOD_IRQ_2 0xf1220001
91 81
92/*IRQSTATUS0*/ 82/*IRQSTATUS0*/
93#define R0900_IRQSTATUS0 0xf123 83#define R0900_IRQSTATUS0 0xf123
94#define F0900_SDEMOD_LOCKB_1 0xf1230080 84#define F0900_SDEMOD_LOCKB_1 0xf1230080
95#define F0900_SDEMOD_LOCK_1 0xf1230040 85#define F0900_SDEMOD_LOCK_1 0xf1230040
96#define F0900_SDEMOD_IRQ_1 0xf1230020 86#define F0900_SDEMOD_IRQ_1 0xf1230020
97#define F0900_SBCH_ERRFLAG 0xf1230010 87#define F0900_SBCH_ERRFLAG 0xf1230010
98#define F0900_SDISEQC2RX_IRQ 0xf1230008 88#define F0900_SDISEQC2RX_IRQ 0xf1230008
99#define F0900_SDISEQC2TX_IRQ 0xf1230004 89#define F0900_SDISEQC2TX_IRQ 0xf1230004
100#define F0900_SDISEQC1RX_IRQ 0xf1230002 90#define F0900_SDISEQC1RX_IRQ 0xf1230002
101#define F0900_SDISEQC1TX_IRQ 0xf1230001 91#define F0900_SDISEQC1TX_IRQ 0xf1230001
102 92
103/*IRQMASK3*/ 93/*IRQMASK3*/
104#define R0900_IRQMASK3 0xf124 94#define R0900_IRQMASK3 0xf124
105#define F0900_MPLL_LOCK 0xf1240020 95#define F0900_MPLL_LOCK 0xf1240020
106#define F0900_MSTREAM_LCK_3 0xf1240010 96#define F0900_MSTREAM_LCK_3 0xf1240010
107#define F0900_MSTREAM_LCK_2 0xf1240008 97#define F0900_MSTREAM_LCK_2 0xf1240008
108#define F0900_MSTREAM_LCK_1 0xf1240004 98#define F0900_MSTREAM_LCK_1 0xf1240004
109#define F0900_MDVBS1_PRF_2 0xf1240002 99#define F0900_MDVBS1_PRF_2 0xf1240002
110#define F0900_MDVBS1_PRF_1 0xf1240001 100#define F0900_MDVBS1_PRF_1 0xf1240001
111 101
112/*IRQMASK2*/ 102/*IRQMASK2*/
113#define R0900_IRQMASK2 0xf125 103#define R0900_IRQMASK2 0xf125
114#define F0900_MSPY_ENDSIM_3 0xf1250080 104#define F0900_MSPY_ENDSIM_3 0xf1250080
115#define F0900_MSPY_ENDSIM_2 0xf1250040 105#define F0900_MSPY_ENDSIM_2 0xf1250040
116#define F0900_MSPY_ENDSIM_1 0xf1250020 106#define F0900_MSPY_ENDSIM_1 0xf1250020
117#define F0900_MPKTDEL_ERROR_2 0xf1250010 107#define F0900_MPKTDEL_ERROR_2 0xf1250010
118#define F0900_MPKTDEL_LOCKB_2 0xf1250008 108#define F0900_MPKTDEL_LOCKB_2 0xf1250008
119#define F0900_MPKTDEL_LOCK_2 0xf1250004 109#define F0900_MPKTDEL_LOCK_2 0xf1250004
120#define F0900_MPKTDEL_ERROR_1 0xf1250002 110#define F0900_MPKTDEL_ERROR_1 0xf1250002
121#define F0900_MPKTDEL_LOCKB_1 0xf1250001 111#define F0900_MPKTDEL_LOCKB_1 0xf1250001
122 112
123/*IRQMASK1*/ 113/*IRQMASK1*/
124#define R0900_IRQMASK1 0xf126 114#define R0900_IRQMASK1 0xf126
125#define F0900_MPKTDEL_LOCK_1 0xf1260080 115#define F0900_MPKTDEL_LOCK_1 0xf1260080
126#define F0900_MEXTPINB2 0xf1260040 116#define F0900_MEXTPINB2 0xf1260040
127#define F0900_MEXTPIN2 0xf1260020 117#define F0900_MEXTPIN2 0xf1260020
128#define F0900_MEXTPINB1 0xf1260010 118#define F0900_MEXTPINB1 0xf1260010
129#define F0900_MEXTPIN1 0xf1260008 119#define F0900_MEXTPIN1 0xf1260008
130#define F0900_MDEMOD_LOCKB_2 0xf1260004 120#define F0900_MDEMOD_LOCKB_2 0xf1260004
131#define F0900_MDEMOD_LOCK_2 0xf1260002 121#define F0900_MDEMOD_LOCK_2 0xf1260002
132#define F0900_MDEMOD_IRQ_2 0xf1260001 122#define F0900_MDEMOD_IRQ_2 0xf1260001
133 123
134/*IRQMASK0*/ 124/*IRQMASK0*/
135#define R0900_IRQMASK0 0xf127 125#define R0900_IRQMASK0 0xf127
136#define F0900_MDEMOD_LOCKB_1 0xf1270080 126#define F0900_MDEMOD_LOCKB_1 0xf1270080
137#define F0900_MDEMOD_LOCK_1 0xf1270040 127#define F0900_MDEMOD_LOCK_1 0xf1270040
138#define F0900_MDEMOD_IRQ_1 0xf1270020 128#define F0900_MDEMOD_IRQ_1 0xf1270020
139#define F0900_MBCH_ERRFLAG 0xf1270010 129#define F0900_MBCH_ERRFLAG 0xf1270010
140#define F0900_MDISEQC2RX_IRQ 0xf1270008 130#define F0900_MDISEQC2RX_IRQ 0xf1270008
141#define F0900_MDISEQC2TX_IRQ 0xf1270004 131#define F0900_MDISEQC2TX_IRQ 0xf1270004
142#define F0900_MDISEQC1RX_IRQ 0xf1270002 132#define F0900_MDISEQC1RX_IRQ 0xf1270002
143#define F0900_MDISEQC1TX_IRQ 0xf1270001 133#define F0900_MDISEQC1TX_IRQ 0xf1270001
144 134
145/*I2CCFG*/ 135/*I2CCFG*/
146#define R0900_I2CCFG 0xf129 136#define R0900_I2CCFG 0xf129
147#define F0900_I2C2_FASTMODE 0xf1290080 137#define F0900_I2C_FASTMODE 0xf1290008
148#define F0900_STATUS_WR2 0xf1290040 138#define F0900_I2CADDR_INC 0xf1290003
149#define F0900_I2C2ADDR_INC 0xf1290030
150#define F0900_I2C_FASTMODE 0xf1290008
151#define F0900_STATUS_WR 0xf1290004
152#define F0900_I2CADDR_INC 0xf1290003
153 139
154/*P1_I2CRPT*/ 140/*P1_I2CRPT*/
155#define R0900_P1_I2CRPT 0xf12a 141#define R0900_P1_I2CRPT 0xf12a
156#define F0900_P1_I2CT_ON 0xf12a0080 142#define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1)
157#define F0900_P1_ENARPT_LEVEL 0xf12a0070 143#define F0900_P1_I2CT_ON 0xf12a0080
158#define F0900_P1_SCLT_DELAY 0xf12a0008 144#define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000)
159#define F0900_P1_STOP_ENABLE 0xf12a0004 145#define F0900_P1_ENARPT_LEVEL 0xf12a0070
160#define F0900_P1_STOP_SDAT2SDA 0xf12a0002 146#define F0900_P1_SCLT_DELAY 0xf12a0008
147#define F0900_P1_STOP_ENABLE 0xf12a0004
148#define F0900_P1_STOP_SDAT2SDA 0xf12a0002
161 149
162/*P2_I2CRPT*/ 150/*P2_I2CRPT*/
163#define R0900_P2_I2CRPT 0xf12b 151#define R0900_P2_I2CRPT 0xf12b
164#define F0900_P2_I2CT_ON 0xf12b0080 152#define F0900_P2_I2CT_ON 0xf12b0080
165#define F0900_P2_ENARPT_LEVEL 0xf12b0070 153#define F0900_P2_ENARPT_LEVEL 0xf12b0070
166#define F0900_P2_SCLT_DELAY 0xf12b0008 154#define F0900_P2_SCLT_DELAY 0xf12b0008
167#define F0900_P2_STOP_ENABLE 0xf12b0004 155#define F0900_P2_STOP_ENABLE 0xf12b0004
168#define F0900_P2_STOP_SDAT2SDA 0xf12b0002 156#define F0900_P2_STOP_SDAT2SDA 0xf12b0002
157
158/*IOPVALUE6*/
159#define R0900_IOPVALUE6 0xf138
160#define F0900_VSCL 0xf1380004
161#define F0900_VSDA 0xf1380002
162#define F0900_VDATA3_0 0xf1380001
163
164/*IOPVALUE5*/
165#define R0900_IOPVALUE5 0xf139
166#define F0900_VDATA3_1 0xf1390080
167#define F0900_VDATA3_2 0xf1390040
168#define F0900_VDATA3_3 0xf1390020
169#define F0900_VDATA3_4 0xf1390010
170#define F0900_VDATA3_5 0xf1390008
171#define F0900_VDATA3_6 0xf1390004
172#define F0900_VDATA3_7 0xf1390002
173#define F0900_VCLKOUT3 0xf1390001
174
175/*IOPVALUE4*/
176#define R0900_IOPVALUE4 0xf13a
177#define F0900_VSTROUT3 0xf13a0080
178#define F0900_VDPN3 0xf13a0040
179#define F0900_VERROR3 0xf13a0020
180#define F0900_VDATA2_7 0xf13a0010
181#define F0900_VCLKOUT2 0xf13a0008
182#define F0900_VSTROUT2 0xf13a0004
183#define F0900_VDPN2 0xf13a0002
184#define F0900_VERROR2 0xf13a0001
185
186/*IOPVALUE3*/
187#define R0900_IOPVALUE3 0xf13b
188#define F0900_VDATA1_7 0xf13b0080
189#define F0900_VCLKOUT1 0xf13b0040
190#define F0900_VSTROUT1 0xf13b0020
191#define F0900_VDPN1 0xf13b0010
192#define F0900_VERROR1 0xf13b0008
193#define F0900_VCLKOUT27 0xf13b0004
194#define F0900_VDISEQCOUT2 0xf13b0002
195#define F0900_VSCLT2 0xf13b0001
196
197/*IOPVALUE2*/
198#define R0900_IOPVALUE2 0xf13c
199#define F0900_VSDAT2 0xf13c0080
200#define F0900_VAGCRF2 0xf13c0040
201#define F0900_VDISEQCOUT1 0xf13c0020
202#define F0900_VSCLT1 0xf13c0010
203#define F0900_VSDAT1 0xf13c0008
204#define F0900_VAGCRF1 0xf13c0004
205#define F0900_VDIRCLK 0xf13c0002
206#define F0900_VSTDBY 0xf13c0001
207
208/*IOPVALUE1*/
209#define R0900_IOPVALUE1 0xf13d
210#define F0900_VCS1 0xf13d0080
211#define F0900_VCS0 0xf13d0040
212#define F0900_VGPIO13 0xf13d0020
213#define F0900_VGPIO12 0xf13d0010
214#define F0900_VGPIO11 0xf13d0008
215#define F0900_VGPIO10 0xf13d0004
216#define F0900_VGPIO9 0xf13d0002
217#define F0900_VGPIO8 0xf13d0001
218
219/*IOPVALUE0*/
220#define R0900_IOPVALUE0 0xf13e
221#define F0900_VGPIO7 0xf13e0080
222#define F0900_VGPIO6 0xf13e0040
223#define F0900_VGPIO5 0xf13e0020
224#define F0900_VGPIO4 0xf13e0010
225#define F0900_VGPIO3 0xf13e0008
226#define F0900_VGPIO2 0xf13e0004
227#define F0900_VGPIO1 0xf13e0002
228#define F0900_VCLKI2 0xf13e0001
169 229
170/*CLKI2CFG*/ 230/*CLKI2CFG*/
171#define R0900_CLKI2CFG 0xf140 231#define R0900_CLKI2CFG 0xf140
172#define F0900_CLKI2_OPD 0xf1400080 232#define F0900_CLKI2_OPD 0xf1400080
173#define F0900_CLKI2_CONFIG 0xf140007e 233#define F0900_CLKI2_CONFIG 0xf140007e
174#define F0900_CLKI2_XOR 0xf1400001 234#define F0900_CLKI2_XOR 0xf1400001
175 235
176/*GPIO1CFG*/ 236/*GPIO1CFG*/
177#define R0900_GPIO1CFG 0xf141 237#define R0900_GPIO1CFG 0xf141
178#define F0900_GPIO1_OPD 0xf1410080 238#define F0900_GPIO1_OPD 0xf1410080
179#define F0900_GPIO1_CONFIG 0xf141007e 239#define F0900_GPIO1_CONFIG 0xf141007e
180#define F0900_GPIO1_XOR 0xf1410001 240#define F0900_GPIO1_XOR 0xf1410001
181 241
182/*GPIO2CFG*/ 242/*GPIO2CFG*/
183#define R0900_GPIO2CFG 0xf142 243#define R0900_GPIO2CFG 0xf142
184#define F0900_GPIO2_OPD 0xf1420080 244#define F0900_GPIO2_OPD 0xf1420080
185#define F0900_GPIO2_CONFIG 0xf142007e 245#define F0900_GPIO2_CONFIG 0xf142007e
186#define F0900_GPIO2_XOR 0xf1420001 246#define F0900_GPIO2_XOR 0xf1420001
187 247
188/*GPIO3CFG*/ 248/*GPIO3CFG*/
189#define R0900_GPIO3CFG 0xf143 249#define R0900_GPIO3CFG 0xf143
190#define F0900_GPIO3_OPD 0xf1430080 250#define F0900_GPIO3_OPD 0xf1430080
191#define F0900_GPIO3_CONFIG 0xf143007e 251#define F0900_GPIO3_CONFIG 0xf143007e
192#define F0900_GPIO3_XOR 0xf1430001 252#define F0900_GPIO3_XOR 0xf1430001
193 253
194/*GPIO4CFG*/ 254/*GPIO4CFG*/
195#define R0900_GPIO4CFG 0xf144 255#define R0900_GPIO4CFG 0xf144
196#define F0900_GPIO4_OPD 0xf1440080 256#define F0900_GPIO4_OPD 0xf1440080
197#define F0900_GPIO4_CONFIG 0xf144007e 257#define F0900_GPIO4_CONFIG 0xf144007e
198#define F0900_GPIO4_XOR 0xf1440001 258#define F0900_GPIO4_XOR 0xf1440001
199 259
200/*GPIO5CFG*/ 260/*GPIO5CFG*/
201#define R0900_GPIO5CFG 0xf145 261#define R0900_GPIO5CFG 0xf145
202#define F0900_GPIO5_OPD 0xf1450080 262#define F0900_GPIO5_OPD 0xf1450080
203#define F0900_GPIO5_CONFIG 0xf145007e 263#define F0900_GPIO5_CONFIG 0xf145007e
204#define F0900_GPIO5_XOR 0xf1450001 264#define F0900_GPIO5_XOR 0xf1450001
205 265
206/*GPIO6CFG*/ 266/*GPIO6CFG*/
207#define R0900_GPIO6CFG 0xf146 267#define R0900_GPIO6CFG 0xf146
208#define F0900_GPIO6_OPD 0xf1460080 268#define F0900_GPIO6_OPD 0xf1460080
209#define F0900_GPIO6_CONFIG 0xf146007e 269#define F0900_GPIO6_CONFIG 0xf146007e
210#define F0900_GPIO6_XOR 0xf1460001 270#define F0900_GPIO6_XOR 0xf1460001
211 271
212/*GPIO7CFG*/ 272/*GPIO7CFG*/
213#define R0900_GPIO7CFG 0xf147 273#define R0900_GPIO7CFG 0xf147
214#define F0900_GPIO7_OPD 0xf1470080 274#define F0900_GPIO7_OPD 0xf1470080
215#define F0900_GPIO7_CONFIG 0xf147007e 275#define F0900_GPIO7_CONFIG 0xf147007e
216#define F0900_GPIO7_XOR 0xf1470001 276#define F0900_GPIO7_XOR 0xf1470001
217 277
218/*GPIO8CFG*/ 278/*GPIO8CFG*/
219#define R0900_GPIO8CFG 0xf148 279#define R0900_GPIO8CFG 0xf148
220#define F0900_GPIO8_OPD 0xf1480080 280#define F0900_GPIO8_OPD 0xf1480080
221#define F0900_GPIO8_CONFIG 0xf148007e 281#define F0900_GPIO8_CONFIG 0xf148007e
222#define F0900_GPIO8_XOR 0xf1480001 282#define F0900_GPIO8_XOR 0xf1480001
223 283
224/*GPIO9CFG*/ 284/*GPIO9CFG*/
225#define R0900_GPIO9CFG 0xf149 285#define R0900_GPIO9CFG 0xf149
226#define F0900_GPIO9_OPD 0xf1490080 286#define F0900_GPIO9_OPD 0xf1490080
227#define F0900_GPIO9_CONFIG 0xf149007e 287#define F0900_GPIO9_CONFIG 0xf149007e
228#define F0900_GPIO9_XOR 0xf1490001 288#define F0900_GPIO9_XOR 0xf1490001
229 289
230/*GPIO10CFG*/ 290/*GPIO10CFG*/
231#define R0900_GPIO10CFG 0xf14a 291#define R0900_GPIO10CFG 0xf14a
232#define F0900_GPIO10_OPD 0xf14a0080 292#define F0900_GPIO10_OPD 0xf14a0080
233#define F0900_GPIO10_CONFIG 0xf14a007e 293#define F0900_GPIO10_CONFIG 0xf14a007e
234#define F0900_GPIO10_XOR 0xf14a0001 294#define F0900_GPIO10_XOR 0xf14a0001
235 295
236/*GPIO11CFG*/ 296/*GPIO11CFG*/
237#define R0900_GPIO11CFG 0xf14b 297#define R0900_GPIO11CFG 0xf14b
238#define F0900_GPIO11_OPD 0xf14b0080 298#define F0900_GPIO11_OPD 0xf14b0080
239#define F0900_GPIO11_CONFIG 0xf14b007e 299#define F0900_GPIO11_CONFIG 0xf14b007e
240#define F0900_GPIO11_XOR 0xf14b0001 300#define F0900_GPIO11_XOR 0xf14b0001
241 301
242/*GPIO12CFG*/ 302/*GPIO12CFG*/
243#define R0900_GPIO12CFG 0xf14c 303#define R0900_GPIO12CFG 0xf14c
244#define F0900_GPIO12_OPD 0xf14c0080 304#define F0900_GPIO12_OPD 0xf14c0080
245#define F0900_GPIO12_CONFIG 0xf14c007e 305#define F0900_GPIO12_CONFIG 0xf14c007e
246#define F0900_GPIO12_XOR 0xf14c0001 306#define F0900_GPIO12_XOR 0xf14c0001
247 307
248/*GPIO13CFG*/ 308/*GPIO13CFG*/
249#define R0900_GPIO13CFG 0xf14d 309#define R0900_GPIO13CFG 0xf14d
250#define F0900_GPIO13_OPD 0xf14d0080 310#define F0900_GPIO13_OPD 0xf14d0080
251#define F0900_GPIO13_CONFIG 0xf14d007e 311#define F0900_GPIO13_CONFIG 0xf14d007e
252#define F0900_GPIO13_XOR 0xf14d0001 312#define F0900_GPIO13_XOR 0xf14d0001
253 313
254/*CS0CFG*/ 314/*CS0CFG*/
255#define R0900_CS0CFG 0xf14e 315#define R0900_CS0CFG 0xf14e
256#define F0900_CS0_OPD 0xf14e0080 316#define F0900_CS0_OPD 0xf14e0080
257#define F0900_CS0_CONFIG 0xf14e007e 317#define F0900_CS0_CONFIG 0xf14e007e
258#define F0900_CS0_XOR 0xf14e0001 318#define F0900_CS0_XOR 0xf14e0001
259 319
260/*CS1CFG*/ 320/*CS1CFG*/
261#define R0900_CS1CFG 0xf14f 321#define R0900_CS1CFG 0xf14f
262#define F0900_CS1_OPD 0xf14f0080 322#define F0900_CS1_OPD 0xf14f0080
263#define F0900_CS1_CONFIG 0xf14f007e 323#define F0900_CS1_CONFIG 0xf14f007e
264#define F0900_CS1_XOR 0xf14f0001 324#define F0900_CS1_XOR 0xf14f0001
265 325
266/*STDBYCFG*/ 326/*STDBYCFG*/
267#define R0900_STDBYCFG 0xf150 327#define R0900_STDBYCFG 0xf150
268#define F0900_STDBY_OPD 0xf1500080 328#define F0900_STDBY_OPD 0xf1500080
269#define F0900_STDBY_CONFIG 0xf150007e 329#define F0900_STDBY_CONFIG 0xf150007e
270#define F0900_STBDY_XOR 0xf1500001 330#define F0900_STBDY_XOR 0xf1500001
271 331
272/*DIRCLKCFG*/ 332/*DIRCLKCFG*/
273#define R0900_DIRCLKCFG 0xf151 333#define R0900_DIRCLKCFG 0xf151
274#define F0900_DIRCLK_OPD 0xf1510080 334#define F0900_DIRCLK_OPD 0xf1510080
275#define F0900_DIRCLK_CONFIG 0xf151007e 335#define F0900_DIRCLK_CONFIG 0xf151007e
276#define F0900_DIRCLK_XOR 0xf1510001 336#define F0900_DIRCLK_XOR 0xf1510001
277 337
278/*AGCRF1CFG*/ 338/*AGCRF1CFG*/
279#define R0900_AGCRF1CFG 0xf152 339#define R0900_AGCRF1CFG 0xf152
280#define F0900_AGCRF1_OPD 0xf1520080 340#define F0900_AGCRF1_OPD 0xf1520080
281#define F0900_AGCRF1_CONFIG 0xf152007e 341#define F0900_AGCRF1_CONFIG 0xf152007e
282#define F0900_AGCRF1_XOR 0xf1520001 342#define F0900_AGCRF1_XOR 0xf1520001
283 343
284/*SDAT1CFG*/ 344/*SDAT1CFG*/
285#define R0900_SDAT1CFG 0xf153 345#define R0900_SDAT1CFG 0xf153
286#define F0900_SDAT1_OPD 0xf1530080 346#define F0900_SDAT1_OPD 0xf1530080
287#define F0900_SDAT1_CONFIG 0xf153007e 347#define F0900_SDAT1_CONFIG 0xf153007e
288#define F0900_SDAT1_XOR 0xf1530001 348#define F0900_SDAT1_XOR 0xf1530001
289 349
290/*SCLT1CFG*/ 350/*SCLT1CFG*/
291#define R0900_SCLT1CFG 0xf154 351#define R0900_SCLT1CFG 0xf154
292#define F0900_SCLT1_OPD 0xf1540080 352#define F0900_SCLT1_OPD 0xf1540080
293#define F0900_SCLT1_CONFIG 0xf154007e 353#define F0900_SCLT1_CONFIG 0xf154007e
294#define F0900_SCLT1_XOR 0xf1540001 354#define F0900_SCLT1_XOR 0xf1540001
295 355
296/*DISEQCO1CFG*/ 356/*DISEQCO1CFG*/
297#define R0900_DISEQCO1CFG 0xf155 357#define R0900_DISEQCO1CFG 0xf155
298#define F0900_DISEQCO1_OPD 0xf1550080 358#define F0900_DISEQCO1_OPD 0xf1550080
299#define F0900_DISEQCO1_CONFIG 0xf155007e 359#define F0900_DISEQCO1_CONFIG 0xf155007e
300#define F0900_DISEQC1_XOR 0xf1550001 360#define F0900_DISEQC1_XOR 0xf1550001
301 361
302/*AGCRF2CFG*/ 362/*AGCRF2CFG*/
303#define R0900_AGCRF2CFG 0xf156 363#define R0900_AGCRF2CFG 0xf156
304#define F0900_AGCRF2_OPD 0xf1560080 364#define F0900_AGCRF2_OPD 0xf1560080
305#define F0900_AGCRF2_CONFIG 0xf156007e 365#define F0900_AGCRF2_CONFIG 0xf156007e
306#define F0900_AGCRF2_XOR 0xf1560001 366#define F0900_AGCRF2_XOR 0xf1560001
307 367
308/*SDAT2CFG*/ 368/*SDAT2CFG*/
309#define R0900_SDAT2CFG 0xf157 369#define R0900_SDAT2CFG 0xf157
310#define F0900_SDAT2_OPD 0xf1570080 370#define F0900_SDAT2_OPD 0xf1570080
311#define F0900_SDAT2_CONFIG 0xf157007e 371#define F0900_SDAT2_CONFIG 0xf157007e
312#define F0900_SDAT2_XOR 0xf1570001 372#define F0900_SDAT2_XOR 0xf1570001
313 373
314/*SCLT2CFG*/ 374/*SCLT2CFG*/
315#define R0900_SCLT2CFG 0xf158 375#define R0900_SCLT2CFG 0xf158
316#define F0900_SCLT2_OPD 0xf1580080 376#define F0900_SCLT2_OPD 0xf1580080
317#define F0900_SCLT2_CONFIG 0xf158007e 377#define F0900_SCLT2_CONFIG 0xf158007e
318#define F0900_SCLT2_XOR 0xf1580001 378#define F0900_SCLT2_XOR 0xf1580001
319 379
320/*DISEQCO2CFG*/ 380/*DISEQCO2CFG*/
321#define R0900_DISEQCO2CFG 0xf159 381#define R0900_DISEQCO2CFG 0xf159
322#define F0900_DISEQCO2_OPD 0xf1590080 382#define F0900_DISEQCO2_OPD 0xf1590080
323#define F0900_DISEQCO2_CONFIG 0xf159007e 383#define F0900_DISEQCO2_CONFIG 0xf159007e
324#define F0900_DISEQC2_XOR 0xf1590001 384#define F0900_DISEQC2_XOR 0xf1590001
325 385
326/*CLKOUT27CFG*/ 386/*CLKOUT27CFG*/
327#define R0900_CLKOUT27CFG 0xf15a 387#define R0900_CLKOUT27CFG 0xf15a
328#define F0900_CLKOUT27_OPD 0xf15a0080 388#define F0900_CLKOUT27_OPD 0xf15a0080
329#define F0900_CLKOUT27_CONFIG 0xf15a007e 389#define F0900_CLKOUT27_CONFIG 0xf15a007e
330#define F0900_CLKOUT27_XOR 0xf15a0001 390#define F0900_CLKOUT27_XOR 0xf15a0001
331 391
332/*ERROR1CFG*/ 392/*ERROR1CFG*/
333#define R0900_ERROR1CFG 0xf15b 393#define R0900_ERROR1CFG 0xf15b
334#define F0900_ERROR1_OPD 0xf15b0080 394#define F0900_ERROR1_OPD 0xf15b0080
335#define F0900_ERROR1_CONFIG 0xf15b007e 395#define F0900_ERROR1_CONFIG 0xf15b007e
336#define F0900_ERROR1_XOR 0xf15b0001 396#define F0900_ERROR1_XOR 0xf15b0001
337 397
338/*DPN1CFG*/ 398/*DPN1CFG*/
339#define R0900_DPN1CFG 0xf15c 399#define R0900_DPN1CFG 0xf15c
340#define F0900_DPN1_OPD 0xf15c0080 400#define F0900_DPN1_OPD 0xf15c0080
341#define F0900_DPN1_CONFIG 0xf15c007e 401#define F0900_DPN1_CONFIG 0xf15c007e
342#define F0900_DPN1_XOR 0xf15c0001 402#define F0900_DPN1_XOR 0xf15c0001
343 403
344/*STROUT1CFG*/ 404/*STROUT1CFG*/
345#define R0900_STROUT1CFG 0xf15d 405#define R0900_STROUT1CFG 0xf15d
346#define F0900_STROUT1_OPD 0xf15d0080 406#define F0900_STROUT1_OPD 0xf15d0080
347#define F0900_STROUT1_CONFIG 0xf15d007e 407#define F0900_STROUT1_CONFIG 0xf15d007e
348#define F0900_STROUT1_XOR 0xf15d0001 408#define F0900_STROUT1_XOR 0xf15d0001
349 409
350/*CLKOUT1CFG*/ 410/*CLKOUT1CFG*/
351#define R0900_CLKOUT1CFG 0xf15e 411#define R0900_CLKOUT1CFG 0xf15e
352#define F0900_CLKOUT1_OPD 0xf15e0080 412#define F0900_CLKOUT1_OPD 0xf15e0080
353#define F0900_CLKOUT1_CONFIG 0xf15e007e 413#define F0900_CLKOUT1_CONFIG 0xf15e007e
354#define F0900_CLKOUT1_XOR 0xf15e0001 414#define F0900_CLKOUT1_XOR 0xf15e0001
355 415
356/*DATA71CFG*/ 416/*DATA71CFG*/
357#define R0900_DATA71CFG 0xf15f 417#define R0900_DATA71CFG 0xf15f
358#define F0900_DATA71_OPD 0xf15f0080 418#define F0900_DATA71_OPD 0xf15f0080
359#define F0900_DATA71_CONFIG 0xf15f007e 419#define F0900_DATA71_CONFIG 0xf15f007e
360#define F0900_DATA71_XOR 0xf15f0001 420#define F0900_DATA71_XOR 0xf15f0001
361 421
362/*ERROR2CFG*/ 422/*ERROR2CFG*/
363#define R0900_ERROR2CFG 0xf160 423#define R0900_ERROR2CFG 0xf160
364#define F0900_ERROR2_OPD 0xf1600080 424#define F0900_ERROR2_OPD 0xf1600080
365#define F0900_ERROR2_CONFIG 0xf160007e 425#define F0900_ERROR2_CONFIG 0xf160007e
366#define F0900_ERROR2_XOR 0xf1600001 426#define F0900_ERROR2_XOR 0xf1600001
367 427
368/*DPN2CFG*/ 428/*DPN2CFG*/
369#define R0900_DPN2CFG 0xf161 429#define R0900_DPN2CFG 0xf161
370#define F0900_DPN2_OPD 0xf1610080 430#define F0900_DPN2_OPD 0xf1610080
371#define F0900_DPN2_CONFIG 0xf161007e 431#define F0900_DPN2_CONFIG 0xf161007e
372#define F0900_DPN2_XOR 0xf1610001 432#define F0900_DPN2_XOR 0xf1610001
373 433
374/*STROUT2CFG*/ 434/*STROUT2CFG*/
375#define R0900_STROUT2CFG 0xf162 435#define R0900_STROUT2CFG 0xf162
376#define F0900_STROUT2_OPD 0xf1620080 436#define F0900_STROUT2_OPD 0xf1620080
377#define F0900_STROUT2_CONFIG 0xf162007e 437#define F0900_STROUT2_CONFIG 0xf162007e
378#define F0900_STROUT2_XOR 0xf1620001 438#define F0900_STROUT2_XOR 0xf1620001
379 439
380/*CLKOUT2CFG*/ 440/*CLKOUT2CFG*/
381#define R0900_CLKOUT2CFG 0xf163 441#define R0900_CLKOUT2CFG 0xf163
382#define F0900_CLKOUT2_OPD 0xf1630080 442#define F0900_CLKOUT2_OPD 0xf1630080
383#define F0900_CLKOUT2_CONFIG 0xf163007e 443#define F0900_CLKOUT2_CONFIG 0xf163007e
384#define F0900_CLKOUT2_XOR 0xf1630001 444#define F0900_CLKOUT2_XOR 0xf1630001
385 445
386/*DATA72CFG*/ 446/*DATA72CFG*/
387#define R0900_DATA72CFG 0xf164 447#define R0900_DATA72CFG 0xf164
388#define F0900_DATA72_OPD 0xf1640080 448#define F0900_DATA72_OPD 0xf1640080
389#define F0900_DATA72_CONFIG 0xf164007e 449#define F0900_DATA72_CONFIG 0xf164007e
390#define F0900_DATA72_XOR 0xf1640001 450#define F0900_DATA72_XOR 0xf1640001
391 451
392/*ERROR3CFG*/ 452/*ERROR3CFG*/
393#define R0900_ERROR3CFG 0xf165 453#define R0900_ERROR3CFG 0xf165
394#define F0900_ERROR3_OPD 0xf1650080 454#define F0900_ERROR3_OPD 0xf1650080
395#define F0900_ERROR3_CONFIG 0xf165007e 455#define F0900_ERROR3_CONFIG 0xf165007e
396#define F0900_ERROR3_XOR 0xf1650001 456#define F0900_ERROR3_XOR 0xf1650001
397 457
398/*DPN3CFG*/ 458/*DPN3CFG*/
399#define R0900_DPN3CFG 0xf166 459#define R0900_DPN3CFG 0xf166
400#define F0900_DPN3_OPD 0xf1660080 460#define F0900_DPN3_OPD 0xf1660080
401#define F0900_DPN3_CONFIG 0xf166007e 461#define F0900_DPN3_CONFIG 0xf166007e
402#define F0900_DPN3_XOR 0xf1660001 462#define F0900_DPN3_XOR 0xf1660001
403 463
404/*STROUT3CFG*/ 464/*STROUT3CFG*/
405#define R0900_STROUT3CFG 0xf167 465#define R0900_STROUT3CFG 0xf167
406#define F0900_STROUT3_OPD 0xf1670080 466#define F0900_STROUT3_OPD 0xf1670080
407#define F0900_STROUT3_CONFIG 0xf167007e 467#define F0900_STROUT3_CONFIG 0xf167007e
408#define F0900_STROUT3_XOR 0xf1670001 468#define F0900_STROUT3_XOR 0xf1670001
409 469
410/*CLKOUT3CFG*/ 470/*CLKOUT3CFG*/
411#define R0900_CLKOUT3CFG 0xf168 471#define R0900_CLKOUT3CFG 0xf168
412#define F0900_CLKOUT3_OPD 0xf1680080 472#define F0900_CLKOUT3_OPD 0xf1680080
413#define F0900_CLKOUT3_CONFIG 0xf168007e 473#define F0900_CLKOUT3_CONFIG 0xf168007e
414#define F0900_CLKOUT3_XOR 0xf1680001 474#define F0900_CLKOUT3_XOR 0xf1680001
415 475
416/*DATA73CFG*/ 476/*DATA73CFG*/
417#define R0900_DATA73CFG 0xf169 477#define R0900_DATA73CFG 0xf169
418#define F0900_DATA73_OPD 0xf1690080 478#define F0900_DATA73_OPD 0xf1690080
419#define F0900_DATA73_CONFIG 0xf169007e 479#define F0900_DATA73_CONFIG 0xf169007e
420#define F0900_DATA73_XOR 0xf1690001 480#define F0900_DATA73_XOR 0xf1690001
481
482/*STRSTATUS1*/
483#define R0900_STRSTATUS1 0xf16a
484#define F0900_STRSTATUS_SEL2 0xf16a00f0
485#define F0900_STRSTATUS_SEL1 0xf16a000f
486
487/*STRSTATUS2*/
488#define R0900_STRSTATUS2 0xf16b
489#define F0900_STRSTATUS_SEL4 0xf16b00f0
490#define F0900_STRSTATUS_SEL3 0xf16b000f
491
492/*STRSTATUS3*/
493#define R0900_STRSTATUS3 0xf16c
494#define F0900_STRSTATUS_SEL6 0xf16c00f0
495#define F0900_STRSTATUS_SEL5 0xf16c000f
421 496
422/*FSKTFC2*/ 497/*FSKTFC2*/
423#define R0900_FSKTFC2 0xf170 498#define R0900_FSKTFC2 0xf170
424#define F0900_FSKT_KMOD 0xf17000fc 499#define F0900_FSKT_KMOD 0xf17000fc
425#define F0900_FSKT_CAR2 0xf1700003 500#define F0900_FSKT_CAR2 0xf1700003
426 501
427/*FSKTFC1*/ 502/*FSKTFC1*/
428#define R0900_FSKTFC1 0xf171 503#define R0900_FSKTFC1 0xf171
429#define F0900_FSKT_CAR1 0xf17100ff 504#define F0900_FSKT_CAR1 0xf17100ff
430 505
431/*FSKTFC0*/ 506/*FSKTFC0*/
432#define R0900_FSKTFC0 0xf172 507#define R0900_FSKTFC0 0xf172
433#define F0900_FSKT_CAR0 0xf17200ff 508#define F0900_FSKT_CAR0 0xf17200ff
434 509
435/*FSKTDELTAF1*/ 510/*FSKTDELTAF1*/
436#define R0900_FSKTDELTAF1 0xf173 511#define R0900_FSKTDELTAF1 0xf173
437#define F0900_FSKT_DELTAF1 0xf173000f 512#define F0900_FSKT_DELTAF1 0xf173000f
438 513
439/*FSKTDELTAF0*/ 514/*FSKTDELTAF0*/
440#define R0900_FSKTDELTAF0 0xf174 515#define R0900_FSKTDELTAF0 0xf174
441#define F0900_FSKT_DELTAF0 0xf17400ff 516#define F0900_FSKT_DELTAF0 0xf17400ff
442 517
443/*FSKTCTRL*/ 518/*FSKTCTRL*/
444#define R0900_FSKTCTRL 0xf175 519#define R0900_FSKTCTRL 0xf175
445#define F0900_FSKT_EN_SGN 0xf1750040 520#define F0900_FSKT_EN_SGN 0xf1750040
446#define F0900_FSKT_MOD_SGN 0xf1750020 521#define F0900_FSKT_MOD_SGN 0xf1750020
447#define F0900_FSKT_MOD_EN 0xf175001c 522#define F0900_FSKT_MOD_EN 0xf175001c
448#define F0900_FSKT_DACMODE 0xf1750003 523#define F0900_FSKT_DACMODE 0xf1750003
449 524
450/*FSKRFC2*/ 525/*FSKRFC2*/
451#define R0900_FSKRFC2 0xf176 526#define R0900_FSKRFC2 0xf176
452#define F0900_FSKR_DETSGN 0xf1760040 527#define F0900_FSKR_DETSGN 0xf1760040
453#define F0900_FSKR_OUTSGN 0xf1760020 528#define F0900_FSKR_OUTSGN 0xf1760020
454#define F0900_FSKR_KAGC 0xf176001c 529#define F0900_FSKR_KAGC 0xf176001c
455#define F0900_FSKR_CAR2 0xf1760003 530#define F0900_FSKR_CAR2 0xf1760003
456 531
457/*FSKRFC1*/ 532/*FSKRFC1*/
458#define R0900_FSKRFC1 0xf177 533#define R0900_FSKRFC1 0xf177
459#define F0900_FSKR_CAR1 0xf17700ff 534#define F0900_FSKR_CAR1 0xf17700ff
460 535
461/*FSKRFC0*/ 536/*FSKRFC0*/
462#define R0900_FSKRFC0 0xf178 537#define R0900_FSKRFC0 0xf178
463#define F0900_FSKR_CAR0 0xf17800ff 538#define F0900_FSKR_CAR0 0xf17800ff
464 539
465/*FSKRK1*/ 540/*FSKRK1*/
466#define R0900_FSKRK1 0xf179 541#define R0900_FSKRK1 0xf179
467#define F0900_FSKR_K1_EXP 0xf17900e0 542#define F0900_FSKR_K1_EXP 0xf17900e0
468#define F0900_FSKR_K1_MANT 0xf179001f 543#define F0900_FSKR_K1_MANT 0xf179001f
469 544
470/*FSKRK2*/ 545/*FSKRK2*/
471#define R0900_FSKRK2 0xf17a 546#define R0900_FSKRK2 0xf17a
472#define F0900_FSKR_K2_EXP 0xf17a00e0 547#define F0900_FSKR_K2_EXP 0xf17a00e0
473#define F0900_FSKR_K2_MANT 0xf17a001f 548#define F0900_FSKR_K2_MANT 0xf17a001f
474 549
475/*FSKRAGCR*/ 550/*FSKRAGCR*/
476#define R0900_FSKRAGCR 0xf17b 551#define R0900_FSKRAGCR 0xf17b
477#define F0900_FSKR_OUTCTL 0xf17b00c0 552#define F0900_FSKR_OUTCTL 0xf17b00c0
478#define F0900_FSKR_AGC_REF 0xf17b003f 553#define F0900_FSKR_AGC_REF 0xf17b003f
479 554
480/*FSKRAGC*/ 555/*FSKRAGC*/
481#define R0900_FSKRAGC 0xf17c 556#define R0900_FSKRAGC 0xf17c
482#define F0900_FSKR_AGC_ACCU 0xf17c00ff 557#define F0900_FSKR_AGC_ACCU 0xf17c00ff
483 558
484/*FSKRALPHA*/ 559/*FSKRALPHA*/
485#define R0900_FSKRALPHA 0xf17d 560#define R0900_FSKRALPHA 0xf17d
486#define F0900_FSKR_ALPHA_EXP 0xf17d001c 561#define F0900_FSKR_ALPHA_EXP 0xf17d001c
487#define F0900_FSKR_ALPHA_M 0xf17d0003 562#define F0900_FSKR_ALPHA_M 0xf17d0003
488 563
489/*FSKRPLTH1*/ 564/*FSKRPLTH1*/
490#define R0900_FSKRPLTH1 0xf17e 565#define R0900_FSKRPLTH1 0xf17e
491#define F0900_FSKR_BETA 0xf17e00f0 566#define F0900_FSKR_BETA 0xf17e00f0
492#define F0900_FSKR_PLL_TRESH1 0xf17e000f 567#define F0900_FSKR_PLL_TRESH1 0xf17e000f
493 568
494/*FSKRPLTH0*/ 569/*FSKRPLTH0*/
495#define R0900_FSKRPLTH0 0xf17f 570#define R0900_FSKRPLTH0 0xf17f
496#define F0900_FSKR_PLL_TRESH0 0xf17f00ff 571#define F0900_FSKR_PLL_TRESH0 0xf17f00ff
497 572
498/*FSKRDF1*/ 573/*FSKRDF1*/
499#define R0900_FSKRDF1 0xf180 574#define R0900_FSKRDF1 0xf180
500#define F0900_FSKR_OUT 0xf1800080 575#define F0900_FSKR_OUT 0xf1800080
501#define F0900_FSKR_DELTAF1 0xf180001f 576#define F0900_FSKR_DELTAF1 0xf180001f
502 577
503/*FSKRDF0*/ 578/*FSKRDF0*/
504#define R0900_FSKRDF0 0xf181 579#define R0900_FSKRDF0 0xf181
505#define F0900_FSKR_DELTAF0 0xf18100ff 580#define F0900_FSKR_DELTAF0 0xf18100ff
506 581
507/*FSKRSTEPP*/ 582/*FSKRSTEPP*/
508#define R0900_FSKRSTEPP 0xf182 583#define R0900_FSKRSTEPP 0xf182
509#define F0900_FSKR_STEP_PLUS 0xf18200ff 584#define F0900_FSKR_STEP_PLUS 0xf18200ff
510 585
511/*FSKRSTEPM*/ 586/*FSKRSTEPM*/
512#define R0900_FSKRSTEPM 0xf183 587#define R0900_FSKRSTEPM 0xf183
513#define F0900_FSKR_STEP_MINUS 0xf18300ff 588#define F0900_FSKR_STEP_MINUS 0xf18300ff
514 589
515/*FSKRDET1*/ 590/*FSKRDET1*/
516#define R0900_FSKRDET1 0xf184 591#define R0900_FSKRDET1 0xf184
517#define F0900_FSKR_DETECT 0xf1840080 592#define F0900_FSKR_DETECT 0xf1840080
518#define F0900_FSKR_CARDET_ACCU1 0xf184000f 593#define F0900_FSKR_CARDET_ACCU1 0xf184000f
519 594
520/*FSKRDET0*/ 595/*FSKRDET0*/
521#define R0900_FSKRDET0 0xf185 596#define R0900_FSKRDET0 0xf185
522#define F0900_FSKR_CARDET_ACCU0 0xf18500ff 597#define F0900_FSKR_CARDET_ACCU0 0xf18500ff
523 598
524/*FSKRDTH1*/ 599/*FSKRDTH1*/
525#define R0900_FSKRDTH1 0xf186 600#define R0900_FSKRDTH1 0xf186
526#define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0 601#define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0
527#define F0900_FSKR_CARDET_THRESH1 0xf186000f 602#define F0900_FSKR_CARDET_THRESH1 0xf186000f
528 603
529/*FSKRDTH0*/ 604/*FSKRDTH0*/
530#define R0900_FSKRDTH0 0xf187 605#define R0900_FSKRDTH0 0xf187
531#define F0900_FSKR_CARDET_THRESH0 0xf18700ff 606#define F0900_FSKR_CARDET_THRESH0 0xf18700ff
532 607
533/*FSKRLOSS*/ 608/*FSKRLOSS*/
534#define R0900_FSKRLOSS 0xf188 609#define R0900_FSKRLOSS 0xf188
535#define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff 610#define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff
536 611
537/*P2_DISTXCTL*/ 612/*P2_DISTXCTL*/
538#define R0900_P2_DISTXCTL 0xf190 613#define R0900_P2_DISTXCTL 0xf190
539#define F0900_P2_TIM_OFF 0xf1900080 614#define F0900_P2_TIM_OFF 0xf1900080
540#define F0900_P2_DISEQC_RESET 0xf1900040 615#define F0900_P2_DISEQC_RESET 0xf1900040
541#define F0900_P2_TIM_CMD 0xf1900030 616#define F0900_P2_TIM_CMD 0xf1900030
542#define F0900_P2_DIS_PRECHARGE 0xf1900008 617#define F0900_P2_DIS_PRECHARGE 0xf1900008
543#define F0900_P2_DISTX_MODE 0xf1900007 618#define F0900_P2_DISTX_MODE 0xf1900007
544 619
545/*P2_DISRXCTL*/ 620/*P2_DISRXCTL*/
546#define R0900_P2_DISRXCTL 0xf191 621#define R0900_P2_DISRXCTL 0xf191
547#define F0900_P2_RECEIVER_ON 0xf1910080 622#define F0900_P2_RECEIVER_ON 0xf1910080
548#define F0900_P2_IGNO_SHORT22K 0xf1910040 623#define F0900_P2_IGNO_SHORT22K 0xf1910040
549#define F0900_P2_ONECHIP_TRX 0xf1910020 624#define F0900_P2_ONECHIP_TRX 0xf1910020
550#define F0900_P2_EXT_ENVELOP 0xf1910010 625#define F0900_P2_EXT_ENVELOP 0xf1910010
551#define F0900_P2_PIN_SELECT 0xf191000c 626#define F0900_P2_PIN_SELECT0 0xf191000c
552#define F0900_P2_IRQ_RXEND 0xf1910002 627#define F0900_P2_IRQ_RXEND 0xf1910002
553#define F0900_P2_IRQ_4NBYTES 0xf1910001 628#define F0900_P2_IRQ_4NBYTES 0xf1910001
554 629
555/*P2_DISRX_ST0*/ 630/*P2_DISRX_ST0*/
556#define R0900_P2_DISRX_ST0 0xf194 631#define R0900_P2_DISRX_ST0 0xf194
557#define F0900_P2_RX_END 0xf1940080 632#define F0900_P2_RX_END 0xf1940080
558#define F0900_P2_RX_ACTIVE 0xf1940040 633#define F0900_P2_RX_ACTIVE 0xf1940040
559#define F0900_P2_SHORT_22KHZ 0xf1940020 634#define F0900_P2_SHORT_22KHZ 0xf1940020
560#define F0900_P2_CONT_TONE 0xf1940010 635#define F0900_P2_CONT_TONE 0xf1940010
561#define F0900_P2_FIFO_4BREADY 0xf1940008 636#define F0900_P2_FIFO_4BREADY 0xf1940008
562#define F0900_P2_FIFO_EMPTY 0xf1940004 637#define F0900_P2_FIFO_EMPTY 0xf1940004
563#define F0900_P2_ABORT_DISRX 0xf1940001 638#define F0900_P2_ABORT_DISRX 0xf1940001
564 639
565/*P2_DISRX_ST1*/ 640/*P2_DISRX_ST1*/
566#define R0900_P2_DISRX_ST1 0xf195 641#define R0900_P2_DISRX_ST1 0xf195
567#define F0900_P2_RX_FAIL 0xf1950080 642#define F0900_P2_RX_FAIL 0xf1950080
568#define F0900_P2_FIFO_PARITYFAIL 0xf1950040 643#define F0900_P2_FIFO_PARITYFAIL 0xf1950040
569#define F0900_P2_RX_NONBYTE 0xf1950020 644#define F0900_P2_RX_NONBYTE 0xf1950020
570#define F0900_P2_FIFO_OVERFLOW 0xf1950010 645#define F0900_P2_FIFO_OVERFLOW 0xf1950010
571#define F0900_P2_FIFO_BYTENBR 0xf195000f 646#define F0900_P2_FIFO_BYTENBR 0xf195000f
572 647
573/*P2_DISRXDATA*/ 648/*P2_DISRXDATA*/
574#define R0900_P2_DISRXDATA 0xf196 649#define R0900_P2_DISRXDATA 0xf196
575#define F0900_P2_DISRX_DATA 0xf19600ff 650#define F0900_P2_DISRX_DATA 0xf19600ff
576 651
577/*P2_DISTXDATA*/ 652/*P2_DISTXDATA*/
578#define R0900_P2_DISTXDATA 0xf197 653#define R0900_P2_DISTXDATA 0xf197
579#define F0900_P2_DISEQC_FIFO 0xf19700ff 654#define F0900_P2_DISEQC_FIFO 0xf19700ff
580 655
581/*P2_DISTXSTATUS*/ 656/*P2_DISTXSTATUS*/
582#define R0900_P2_DISTXSTATUS 0xf198 657#define R0900_P2_DISTXSTATUS 0xf198
583#define F0900_P2_TX_FAIL 0xf1980080 658#define F0900_P2_TX_FAIL 0xf1980080
584#define F0900_P2_FIFO_FULL 0xf1980040 659#define F0900_P2_FIFO_FULL 0xf1980040
585#define F0900_P2_TX_IDLE 0xf1980020 660#define F0900_P2_TX_IDLE 0xf1980020
586#define F0900_P2_GAP_BURST 0xf1980010 661#define F0900_P2_GAP_BURST 0xf1980010
587#define F0900_P2_TXFIFO_BYTES 0xf198000f 662#define F0900_P2_TXFIFO_BYTES 0xf198000f
588 663
589/*P2_F22TX*/ 664/*P2_F22TX*/
590#define R0900_P2_F22TX 0xf199 665#define R0900_P2_F22TX 0xf199
591#define F0900_P2_F22_REG 0xf19900ff 666#define F0900_P2_F22_REG 0xf19900ff
592 667
593/*P2_F22RX*/ 668/*P2_F22RX*/
594#define R0900_P2_F22RX 0xf19a 669#define R0900_P2_F22RX 0xf19a
595#define F0900_P2_F22RX_REG 0xf19a00ff 670#define F0900_P2_F22RX_REG 0xf19a00ff
596 671
597/*P2_ACRPRESC*/ 672/*P2_ACRPRESC*/
598#define R0900_P2_ACRPRESC 0xf19c 673#define R0900_P2_ACRPRESC 0xf19c
599#define F0900_P2_ACR_CODFRDY 0xf19c0008 674#define F0900_P2_ACR_PRESC 0xf19c0007
600#define F0900_P2_ACR_PRESC 0xf19c0007
601 675
602/*P2_ACRDIV*/ 676/*P2_ACRDIV*/
603#define R0900_P2_ACRDIV 0xf19d 677#define R0900_P2_ACRDIV 0xf19d
604#define F0900_P2_ACR_DIV 0xf19d00ff 678#define F0900_P2_ACR_DIV 0xf19d00ff
605 679
606/*P1_DISTXCTL*/ 680/*P1_DISTXCTL*/
607#define R0900_P1_DISTXCTL 0xf1a0 681#define R0900_P1_DISTXCTL 0xf1a0
608#define F0900_P1_TIM_OFF 0xf1a00080 682#define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10)
609#define F0900_P1_DISEQC_RESET 0xf1a00040 683#define F0900_P1_TIM_OFF 0xf1a00080
610#define F0900_P1_TIM_CMD 0xf1a00030 684#define F0900_P1_DISEQC_RESET 0xf1a00040
611#define F0900_P1_DIS_PRECHARGE 0xf1a00008 685#define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000)
612#define F0900_P1_DISTX_MODE 0xf1a00007 686#define F0900_P1_TIM_CMD 0xf1a00030
687#define F0900_P1_DIS_PRECHARGE 0xf1a00008
688#define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000)
689#define F0900_P1_DISTX_MODE 0xf1a00007
690#define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000)
613 691
614/*P1_DISRXCTL*/ 692/*P1_DISRXCTL*/
615#define R0900_P1_DISRXCTL 0xf1a1 693#define R0900_P1_DISRXCTL 0xf1a1
616#define F0900_P1_RECEIVER_ON 0xf1a10080 694#define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10)
617#define F0900_P1_IGNO_SHORT22K 0xf1a10040 695#define F0900_P1_RECEIVER_ON 0xf1a10080
618#define F0900_P1_ONECHIP_TRX 0xf1a10020 696#define F0900_P1_IGNO_SHORT22K 0xf1a10040
619#define F0900_P1_EXT_ENVELOP 0xf1a10010 697#define F0900_P1_ONECHIP_TRX 0xf1a10020
620#define F0900_P1_PIN_SELECT 0xf1a1000c 698#define F0900_P1_EXT_ENVELOP 0xf1a10010
621#define F0900_P1_IRQ_RXEND 0xf1a10002 699#define F0900_P1_PIN_SELECT0 0xf1a1000c
622#define F0900_P1_IRQ_4NBYTES 0xf1a10001 700#define F0900_P1_IRQ_RXEND 0xf1a10002
701#define F0900_P1_IRQ_4NBYTES 0xf1a10001
623 702
624/*P1_DISRX_ST0*/ 703/*P1_DISRX_ST0*/
625#define R0900_P1_DISRX_ST0 0xf1a4 704#define R0900_P1_DISRX_ST0 0xf1a4
626#define F0900_P1_RX_END 0xf1a40080 705#define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10)
627#define F0900_P1_RX_ACTIVE 0xf1a40040 706#define F0900_P1_RX_END 0xf1a40080
628#define F0900_P1_SHORT_22KHZ 0xf1a40020 707#define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000)
629#define F0900_P1_CONT_TONE 0xf1a40010 708#define F0900_P1_RX_ACTIVE 0xf1a40040
630#define F0900_P1_FIFO_4BREADY 0xf1a40008 709#define F0900_P1_SHORT_22KHZ 0xf1a40020
631#define F0900_P1_FIFO_EMPTY 0xf1a40004 710#define F0900_P1_CONT_TONE 0xf1a40010
632#define F0900_P1_ABORT_DISRX 0xf1a40001 711#define F0900_P1_FIFO_4BREADY 0xf1a40008
712#define F0900_P1_FIFO_EMPTY 0xf1a40004
713#define F0900_P1_ABORT_DISRX 0xf1a40001
633 714
634/*P1_DISRX_ST1*/ 715/*P1_DISRX_ST1*/
635#define R0900_P1_DISRX_ST1 0xf1a5 716#define R0900_P1_DISRX_ST1 0xf1a5
636#define F0900_P1_RX_FAIL 0xf1a50080 717#define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10)
637#define F0900_P1_FIFO_PARITYFAIL 0xf1a50040 718#define F0900_P1_RX_FAIL 0xf1a50080
638#define F0900_P1_RX_NONBYTE 0xf1a50020 719#define F0900_P1_FIFO_PARITYFAIL 0xf1a50040
639#define F0900_P1_FIFO_OVERFLOW 0xf1a50010 720#define F0900_P1_RX_NONBYTE 0xf1a50020
640#define F0900_P1_FIFO_BYTENBR 0xf1a5000f 721#define F0900_P1_FIFO_OVERFLOW 0xf1a50010
722#define F0900_P1_FIFO_BYTENBR 0xf1a5000f
723#define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000)
641 724
642/*P1_DISRXDATA*/ 725/*P1_DISRXDATA*/
643#define R0900_P1_DISRXDATA 0xf1a6 726#define R0900_P1_DISRXDATA 0xf1a6
644#define F0900_P1_DISRX_DATA 0xf1a600ff 727#define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10)
728#define F0900_P1_DISRX_DATA 0xf1a600ff
645 729
646/*P1_DISTXDATA*/ 730/*P1_DISTXDATA*/
647#define R0900_P1_DISTXDATA 0xf1a7 731#define R0900_P1_DISTXDATA 0xf1a7
648#define F0900_P1_DISEQC_FIFO 0xf1a700ff 732#define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10)
733#define F0900_P1_DISEQC_FIFO 0xf1a700ff
649 734
650/*P1_DISTXSTATUS*/ 735/*P1_DISTXSTATUS*/
651#define R0900_P1_DISTXSTATUS 0xf1a8 736#define R0900_P1_DISTXSTATUS 0xf1a8
652#define F0900_P1_TX_FAIL 0xf1a80080 737#define F0900_P1_TX_FAIL 0xf1a80080
653#define F0900_P1_FIFO_FULL 0xf1a80040 738#define F0900_P1_FIFO_FULL 0xf1a80040
654#define F0900_P1_TX_IDLE 0xf1a80020 739#define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000)
655#define F0900_P1_GAP_BURST 0xf1a80010 740#define F0900_P1_TX_IDLE 0xf1a80020
656#define F0900_P1_TXFIFO_BYTES 0xf1a8000f 741#define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000)
742#define F0900_P1_GAP_BURST 0xf1a80010
743#define F0900_P1_TXFIFO_BYTES 0xf1a8000f
657 744
658/*P1_F22TX*/ 745/*P1_F22TX*/
659#define R0900_P1_F22TX 0xf1a9 746#define R0900_P1_F22TX 0xf1a9
660#define F0900_P1_F22_REG 0xf1a900ff 747#define F22TX shiftx(R0900_P1_F22TX, demod, 0x10)
748#define F0900_P1_F22_REG 0xf1a900ff
661 749
662/*P1_F22RX*/ 750/*P1_F22RX*/
663#define R0900_P1_F22RX 0xf1aa 751#define R0900_P1_F22RX 0xf1aa
664#define F0900_P1_F22RX_REG 0xf1aa00ff 752#define F22RX shiftx(R0900_P1_F22RX, demod, 0x10)
753#define F0900_P1_F22RX_REG 0xf1aa00ff
665 754
666/*P1_ACRPRESC*/ 755/*P1_ACRPRESC*/
667#define R0900_P1_ACRPRESC 0xf1ac 756#define R0900_P1_ACRPRESC 0xf1ac
668#define F0900_P1_ACR_CODFRDY 0xf1ac0008 757#define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10)
669#define F0900_P1_ACR_PRESC 0xf1ac0007 758#define F0900_P1_ACR_PRESC 0xf1ac0007
670 759
671/*P1_ACRDIV*/ 760/*P1_ACRDIV*/
672#define R0900_P1_ACRDIV 0xf1ad 761#define R0900_P1_ACRDIV 0xf1ad
673#define F0900_P1_ACR_DIV 0xf1ad00ff 762#define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10)
763#define F0900_P1_ACR_DIV 0xf1ad00ff
674 764
675/*NCOARSE*/ 765/*NCOARSE*/
676#define R0900_NCOARSE 0xf1b3 766#define R0900_NCOARSE 0xf1b3
677#define F0900_M_DIV 0xf1b300ff 767#define F0900_M_DIV 0xf1b300ff
678 768
679/*SYNTCTRL*/ 769/*SYNTCTRL*/
680#define R0900_SYNTCTRL 0xf1b6 770#define R0900_SYNTCTRL 0xf1b6
681#define F0900_STANDBY 0xf1b60080 771#define F0900_STANDBY 0xf1b60080
682#define F0900_BYPASSPLLCORE 0xf1b60040 772#define F0900_BYPASSPLLCORE 0xf1b60040
683#define F0900_SELX1RATIO 0xf1b60020 773#define F0900_SELX1RATIO 0xf1b60020
684#define F0900_I2C_TUD 0xf1b60010 774#define F0900_STOP_PLL 0xf1b60008
685#define F0900_STOP_PLL 0xf1b60008 775#define F0900_BYPASSPLLFSK 0xf1b60004
686#define F0900_BYPASSPLLFSK 0xf1b60004 776#define F0900_SELOSCI 0xf1b60002
687#define F0900_SELOSCI 0xf1b60002 777#define F0900_BYPASSPLLADC 0xf1b60001
688#define F0900_BYPASSPLLADC 0xf1b60001
689 778
690/*FILTCTRL*/ 779/*FILTCTRL*/
691#define R0900_FILTCTRL 0xf1b7 780#define R0900_FILTCTRL 0xf1b7
692#define F0900_INV_CLK135 0xf1b70080 781#define F0900_INV_CLK135 0xf1b70080
693#define F0900_PERM_BYPDIS 0xf1b70040 782#define F0900_SEL_FSKCKDIV 0xf1b70004
694#define F0900_SEL_FSKCKDIV 0xf1b70004 783#define F0900_INV_CLKFSK 0xf1b70002
695#define F0900_INV_CLKFSK 0xf1b70002 784#define F0900_BYPASS_APPLI 0xf1b70001
696#define F0900_BYPASS_APPLI 0xf1b70001
697 785
698/*PLLSTAT*/ 786/*PLLSTAT*/
699#define R0900_PLLSTAT 0xf1b8 787#define R0900_PLLSTAT 0xf1b8
700#define F0900_ACM_SEL 0xf1b80080 788#define F0900_PLLLOCK 0xf1b80001
701#define F0900_DTV_SEL 0xf1b80040
702#define F0900_PLLLOCK 0xf1b80001
703 789
704/*STOPCLK1*/ 790/*STOPCLK1*/
705#define R0900_STOPCLK1 0xf1c2 791#define R0900_STOPCLK1 0xf1c2
706#define F0900_STOP_CLKPKDT2 0xf1c20040 792#define F0900_STOP_CLKPKDT2 0xf1c20040
707#define F0900_STOP_CLKPKDT1 0xf1c20020 793#define F0900_STOP_CLKPKDT1 0xf1c20020
708#define F0900_STOP_CLKFEC 0xf1c20010 794#define F0900_STOP_CLKFEC 0xf1c20010
709#define F0900_STOP_CLKADCI2 0xf1c20008 795#define F0900_STOP_CLKADCI2 0xf1c20008
710#define F0900_INV_CLKADCI2 0xf1c20004 796#define F0900_INV_CLKADCI2 0xf1c20004
711#define F0900_STOP_CLKADCI1 0xf1c20002 797#define F0900_STOP_CLKADCI1 0xf1c20002
712#define F0900_INV_CLKADCI1 0xf1c20001 798#define F0900_INV_CLKADCI1 0xf1c20001
713 799
714/*STOPCLK2*/ 800/*STOPCLK2*/
715#define R0900_STOPCLK2 0xf1c3 801#define R0900_STOPCLK2 0xf1c3
716#define F0900_STOP_CLKSAMP2 0xf1c30010 802#define F0900_STOP_CLKSAMP2 0xf1c30010
717#define F0900_STOP_CLKSAMP1 0xf1c30008 803#define F0900_STOP_CLKSAMP1 0xf1c30008
718#define F0900_STOP_CLKVIT2 0xf1c30004 804#define F0900_STOP_CLKVIT2 0xf1c30004
719#define F0900_STOP_CLKVIT1 0xf1c30002 805#define F0900_STOP_CLKVIT1 0xf1c30002
720#define F0900_STOP_CLKTS 0xf1c30001 806#define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2)
807#define F0900_STOP_CLKTS 0xf1c30001
721 808
722/*TSTTNR0*/ 809/*TSTTNR0*/
723#define R0900_TSTTNR0 0xf1df 810#define R0900_TSTTNR0 0xf1df
724#define F0900_SEL_FSK 0xf1df0080 811#define F0900_SEL_FSK 0xf1df0080
725#define F0900_FSK_PON 0xf1df0004 812#define F0900_FSK_PON 0xf1df0004
726#define F0900_FSK_OPENLOOP 0xf1df0002
727 813
728/*TSTTNR1*/ 814/*TSTTNR1*/
729#define R0900_TSTTNR1 0xf1e0 815#define R0900_TSTTNR1 0xf1e0
730#define F0900_BYPASS_ADC1 0xf1e00080 816#define F0900_ADC1_PON 0xf1e00002
731#define F0900_INVADC1_CKOUT 0xf1e00040 817#define F0900_ADC1_INMODE 0xf1e00001
732#define F0900_SELIQSRC1 0xf1e00030
733#define F0900_ADC1_PON 0xf1e00002
734#define F0900_ADC1_INMODE 0xf1e00001
735 818
736/*TSTTNR2*/ 819/*TSTTNR2*/
737#define R0900_TSTTNR2 0xf1e1 820#define R0900_TSTTNR2 0xf1e1
738#define F0900_DISEQC1_PON 0xf1e10020 821#define F0900_DISEQC1_PON 0xf1e10020
739#define F0900_DISEQC1_TEST 0xf1e1001f
740 822
741/*TSTTNR3*/ 823/*TSTTNR3*/
742#define R0900_TSTTNR3 0xf1e2 824#define R0900_TSTTNR3 0xf1e2
743#define F0900_BYPASS_ADC2 0xf1e20080 825#define F0900_ADC2_PON 0xf1e20002
744#define F0900_INVADC2_CKOUT 0xf1e20040 826#define F0900_ADC2_INMODE 0xf1e20001
745#define F0900_SELIQSRC2 0xf1e20030
746#define F0900_ADC2_PON 0xf1e20002
747#define F0900_ADC2_INMODE 0xf1e20001
748 827
749/*TSTTNR4*/ 828/*TSTTNR4*/
750#define R0900_TSTTNR4 0xf1e3 829#define R0900_TSTTNR4 0xf1e3
751#define F0900_DISEQC2_PON 0xf1e30020 830#define F0900_DISEQC2_PON 0xf1e30020
752#define F0900_DISEQC2_TEST 0xf1e3001f
753 831
754/*P2_IQCONST*/ 832/*P2_IQCONST*/
755#define R0900_P2_IQCONST 0xf200 833#define R0900_P2_IQCONST 0xf200
756#define F0900_P2_CONSTEL_SELECT 0xf2000060 834#define F0900_P2_CONSTEL_SELECT 0xf2000060
757#define F0900_P2_IQSYMB_SEL 0xf200001f 835#define F0900_P2_IQSYMB_SEL 0xf200001f
758 836
759/*P2_NOSCFG*/ 837/*P2_NOSCFG*/
760#define R0900_P2_NOSCFG 0xf201 838#define R0900_P2_NOSCFG 0xf201
761#define F0900_P2_DUMMYPL_NOSDATA 0xf2010020 839#define F0900_P2_DUMMYPL_NOSDATA 0xf2010020
762#define F0900_P2_NOSPLH_BETA 0xf2010018 840#define F0900_P2_NOSPLH_BETA 0xf2010018
763#define F0900_P2_NOSDATA_BETA 0xf2010007 841#define F0900_P2_NOSDATA_BETA 0xf2010007
764 842
765/*P2_ISYMB*/ 843/*P2_ISYMB*/
766#define R0900_P2_ISYMB 0xf202 844#define R0900_P2_ISYMB 0xf202
767#define F0900_P2_I_SYMBOL 0xf20201ff 845#define F0900_P2_I_SYMBOL 0xf20201ff
768 846
769/*P2_QSYMB*/ 847/*P2_QSYMB*/
770#define R0900_P2_QSYMB 0xf203 848#define R0900_P2_QSYMB 0xf203
771#define F0900_P2_Q_SYMBOL 0xf20301ff 849#define F0900_P2_Q_SYMBOL 0xf20301ff
772 850
773/*P2_AGC1CFG*/ 851/*P2_AGC1CFG*/
774#define R0900_P2_AGC1CFG 0xf204 852#define R0900_P2_AGC1CFG 0xf204
775#define F0900_P2_DC_FROZEN 0xf2040080 853#define F0900_P2_DC_FROZEN 0xf2040080
776#define F0900_P2_DC_CORRECT 0xf2040040 854#define F0900_P2_DC_CORRECT 0xf2040040
777#define F0900_P2_AMM_FROZEN 0xf2040020 855#define F0900_P2_AMM_FROZEN 0xf2040020
778#define F0900_P2_AMM_CORRECT 0xf2040010 856#define F0900_P2_AMM_CORRECT 0xf2040010
779#define F0900_P2_QUAD_FROZEN 0xf2040008 857#define F0900_P2_QUAD_FROZEN 0xf2040008
780#define F0900_P2_QUAD_CORRECT 0xf2040004 858#define F0900_P2_QUAD_CORRECT 0xf2040004
781#define F0900_P2_DCCOMP_SLOW 0xf2040002
782#define F0900_P2_IQMISM_SLOW 0xf2040001
783 859
784/*P2_AGC1CN*/ 860/*P2_AGC1CN*/
785#define R0900_P2_AGC1CN 0xf206 861#define R0900_P2_AGC1CN 0xf206
786#define F0900_P2_AGC1_LOCKED 0xf2060080 862#define F0900_P2_AGC1_LOCKED 0xf2060080
787#define F0900_P2_AGC1_OVERFLOW 0xf2060040 863#define F0900_P2_AGC1_MINPOWER 0xf2060010
788#define F0900_P2_AGC1_NOSLOWLK 0xf2060020 864#define F0900_P2_AGCOUT_FAST 0xf2060008
789#define F0900_P2_AGC1_MINPOWER 0xf2060010 865#define F0900_P2_AGCIQ_BETA 0xf2060007
790#define F0900_P2_AGCOUT_FAST 0xf2060008
791#define F0900_P2_AGCIQ_BETA 0xf2060007
792 866
793/*P2_AGC1REF*/ 867/*P2_AGC1REF*/
794#define R0900_P2_AGC1REF 0xf207 868#define R0900_P2_AGC1REF 0xf207
795#define F0900_P2_AGCIQ_REF 0xf20700ff 869#define F0900_P2_AGCIQ_REF 0xf20700ff
796 870
797/*P2_IDCCOMP*/ 871/*P2_IDCCOMP*/
798#define R0900_P2_IDCCOMP 0xf208 872#define R0900_P2_IDCCOMP 0xf208
799#define F0900_P2_IAVERAGE_ADJ 0xf20801ff 873#define F0900_P2_IAVERAGE_ADJ 0xf20801ff
800 874
801/*P2_QDCCOMP*/ 875/*P2_QDCCOMP*/
802#define R0900_P2_QDCCOMP 0xf209 876#define R0900_P2_QDCCOMP 0xf209
803#define F0900_P2_QAVERAGE_ADJ 0xf20901ff 877#define F0900_P2_QAVERAGE_ADJ 0xf20901ff
804 878
805/*P2_POWERI*/ 879/*P2_POWERI*/
806#define R0900_P2_POWERI 0xf20a 880#define R0900_P2_POWERI 0xf20a
807#define F0900_P2_POWER_I 0xf20a00ff 881#define F0900_P2_POWER_I 0xf20a00ff
808 882
809/*P2_POWERQ*/ 883/*P2_POWERQ*/
810#define R0900_P2_POWERQ 0xf20b 884#define R0900_P2_POWERQ 0xf20b
811#define F0900_P2_POWER_Q 0xf20b00ff 885#define F0900_P2_POWER_Q 0xf20b00ff
812 886
813/*P2_AGC1AMM*/ 887/*P2_AGC1AMM*/
814#define R0900_P2_AGC1AMM 0xf20c 888#define R0900_P2_AGC1AMM 0xf20c
815#define F0900_P2_AMM_VALUE 0xf20c00ff 889#define F0900_P2_AMM_VALUE 0xf20c00ff
816 890
817/*P2_AGC1QUAD*/ 891/*P2_AGC1QUAD*/
818#define R0900_P2_AGC1QUAD 0xf20d 892#define R0900_P2_AGC1QUAD 0xf20d
819#define F0900_P2_QUAD_VALUE 0xf20d01ff 893#define F0900_P2_QUAD_VALUE 0xf20d01ff
820 894
821/*P2_AGCIQIN1*/ 895/*P2_AGCIQIN1*/
822#define R0900_P2_AGCIQIN1 0xf20e 896#define R0900_P2_AGCIQIN1 0xf20e
823#define F0900_P2_AGCIQ_VALUE1 0xf20e00ff 897#define F0900_P2_AGCIQ_VALUE1 0xf20e00ff
824 898
825/*P2_AGCIQIN0*/ 899/*P2_AGCIQIN0*/
826#define R0900_P2_AGCIQIN0 0xf20f 900#define R0900_P2_AGCIQIN0 0xf20f
827#define F0900_P2_AGCIQ_VALUE0 0xf20f00ff 901#define F0900_P2_AGCIQ_VALUE0 0xf20f00ff
828 902
829/*P2_DEMOD*/ 903/*P2_DEMOD*/
830#define R0900_P2_DEMOD 0xf210 904#define R0900_P2_DEMOD 0xf210
831#define F0900_P2_DEMOD_STOP 0xf2100040 905#define F0900_P2_MANUALS2_ROLLOFF 0xf2100080
832#define F0900_P2_SPECINV_CONTROL 0xf2100030 906#define F0900_P2_SPECINV_CONTROL 0xf2100030
833#define F0900_P2_FORCE_ENASAMP 0xf2100008 907#define F0900_P2_FORCE_ENASAMP 0xf2100008
834#define F0900_P2_MANUAL_ROLLOFF 0xf2100004 908#define F0900_P2_MANUALSX_ROLLOFF 0xf2100004
835#define F0900_P2_ROLLOFF_CONTROL 0xf2100003 909#define F0900_P2_ROLLOFF_CONTROL 0xf2100003
836 910
837/*P2_DMDMODCOD*/ 911/*P2_DMDMODCOD*/
838#define R0900_P2_DMDMODCOD 0xf211 912#define R0900_P2_DMDMODCOD 0xf211
839#define F0900_P2_MANUAL_MODCOD 0xf2110080 913#define F0900_P2_MANUAL_MODCOD 0xf2110080
840#define F0900_P2_DEMOD_MODCOD 0xf211007c 914#define F0900_P2_DEMOD_MODCOD 0xf211007c
841#define F0900_P2_DEMOD_TYPE 0xf2110003 915#define F0900_P2_DEMOD_TYPE 0xf2110003
842 916
843/*P2_DSTATUS*/ 917/*P2_DSTATUS*/
844#define R0900_P2_DSTATUS 0xf212 918#define R0900_P2_DSTATUS 0xf212
845#define F0900_P2_CAR_LOCK 0xf2120080 919#define F0900_P2_CAR_LOCK 0xf2120080
846#define F0900_P2_TMGLOCK_QUALITY 0xf2120060 920#define F0900_P2_TMGLOCK_QUALITY 0xf2120060
847#define F0900_P2_SDVBS1_ENABLE 0xf2120010 921#define F0900_P2_LOCK_DEFINITIF 0xf2120008
848#define F0900_P2_LOCK_DEFINITIF 0xf2120008 922#define F0900_P2_OVADC_DETECT 0xf2120001
849#define F0900_P2_TIMING_IS_LOCKED 0xf2120004
850#define F0900_P2_COARSE_TMGLOCK 0xf2120002
851#define F0900_P2_COARSE_CARLOCK 0xf2120001
852 923
853/*P2_DSTATUS2*/ 924/*P2_DSTATUS2*/
854#define R0900_P2_DSTATUS2 0xf213 925#define R0900_P2_DSTATUS2 0xf213
855#define F0900_P2_DEMOD_DELOCK 0xf2130080 926#define F0900_P2_DEMOD_DELOCK 0xf2130080
856#define F0900_P2_DEMOD_TIMEOUT 0xf2130040 927#define F0900_P2_AGC1_NOSIGNALACK 0xf2130008
857#define F0900_P2_MODCODRQ_SYNCTAG 0xf2130020 928#define F0900_P2_AGC2_OVERFLOW 0xf2130004
858#define F0900_P2_POLYPH_SATEVENT 0xf2130010 929#define F0900_P2_CFR_OVERFLOW 0xf2130002
859#define F0900_P2_AGC1_NOSIGNALACK 0xf2130008 930#define F0900_P2_GAMMA_OVERUNDER 0xf2130001
860#define F0900_P2_AGC2_OVERFLOW 0xf2130004
861#define F0900_P2_CFR_OVERFLOW 0xf2130002
862#define F0900_P2_GAMMA_OVERUNDER 0xf2130001
863 931
864/*P2_DMDCFGMD*/ 932/*P2_DMDCFGMD*/
865#define R0900_P2_DMDCFGMD 0xf214 933#define R0900_P2_DMDCFGMD 0xf214
866#define F0900_P2_DVBS2_ENABLE 0xf2140080 934#define F0900_P2_DVBS2_ENABLE 0xf2140080
867#define F0900_P2_DVBS1_ENABLE 0xf2140040 935#define F0900_P2_DVBS1_ENABLE 0xf2140040
868#define F0900_P2_CFR_AUTOSCAN 0xf2140020 936#define F0900_P2_SCAN_ENABLE 0xf2140010
869#define F0900_P2_SCAN_ENABLE 0xf2140010 937#define F0900_P2_CFR_AUTOSCAN 0xf2140008
870#define F0900_P2_TUN_AUTOSCAN 0xf2140008 938#define F0900_P2_TUN_RNG 0xf2140003
871#define F0900_P2_NOFORCE_RELOCK 0xf2140004
872#define F0900_P2_TUN_RNG 0xf2140003
873 939
874/*P2_DMDCFG2*/ 940/*P2_DMDCFG2*/
875#define R0900_P2_DMDCFG2 0xf215 941#define R0900_P2_DMDCFG2 0xf215
876#define F0900_P2_AGC1_WAITLOCK 0xf2150080 942#define F0900_P2_S1S2_SEQUENTIAL 0xf2150040
877#define F0900_P2_S1S2_SEQUENTIAL 0xf2150040 943#define F0900_P2_INFINITE_RELOCK 0xf2150010
878#define F0900_P2_OVERFLOW_TIMEOUT 0xf2150020
879#define F0900_P2_SCANFAIL_TIMEOUT 0xf2150010
880#define F0900_P2_DMDTOUT_BACK 0xf2150008
881#define F0900_P2_CARLOCK_S1ENABLE 0xf2150004
882#define F0900_P2_COARSE_LK3MODE 0xf2150002
883#define F0900_P2_COARSE_LK2MODE 0xf2150001
884 944
885/*P2_DMDISTATE*/ 945/*P2_DMDISTATE*/
886#define R0900_P2_DMDISTATE 0xf216 946#define R0900_P2_DMDISTATE 0xf216
887#define F0900_P2_I2C_NORESETDMODE 0xf2160080 947#define F0900_P2_I2C_DEMOD_MODE 0xf216001f
888#define F0900_P2_FORCE_ETAPED 0xf2160040
889#define F0900_P2_SDMDRST_DIRCLK 0xf2160020
890#define F0900_P2_I2C_DEMOD_MODE 0xf216001f
891 948
892/*P2_DMDT0M*/ 949/*P2_DMDT0M*/
893#define R0900_P2_DMDT0M 0xf217 950#define R0900_P2_DMDT0M 0xf217
894#define F0900_P2_DMDT0_MIN 0xf21700ff 951#define F0900_P2_DMDT0_MIN 0xf21700ff
895 952
896/*P2_DMDSTATE*/ 953/*P2_DMDSTATE*/
897#define R0900_P2_DMDSTATE 0xf21b 954#define R0900_P2_DMDSTATE 0xf21b
898#define F0900_P2_DEMOD_LOCKED 0xf21b0080 955#define F0900_P2_HEADER_MODE 0xf21b0060
899#define F0900_P2_HEADER_MODE 0xf21b0060
900#define F0900_P2_DEMOD_MODE 0xf21b001f
901 956
902/*P2_DMDFLYW*/ 957/*P2_DMDFLYW*/
903#define R0900_P2_DMDFLYW 0xf21c 958#define R0900_P2_DMDFLYW 0xf21c
904#define F0900_P2_I2C_IRQVAL 0xf21c00f0 959#define F0900_P2_I2C_IRQVAL 0xf21c00f0
905#define F0900_P2_FLYWHEEL_CPT 0xf21c000f 960#define F0900_P2_FLYWHEEL_CPT 0xf21c000f
906 961
907/*P2_DSTATUS3*/ 962/*P2_DSTATUS3*/
908#define R0900_P2_DSTATUS3 0xf21d 963#define R0900_P2_DSTATUS3 0xf21d
909#define F0900_P2_CFR_ZIGZAG 0xf21d0080 964#define F0900_P2_DEMOD_CFGMODE 0xf21d0060
910#define F0900_P2_DEMOD_CFGMODE 0xf21d0060
911#define F0900_P2_GAMMA_LOWBAUDRATE 0xf21d0010
912#define F0900_P2_RELOCK_MODE 0xf21d0008
913#define F0900_P2_DEMOD_FAIL 0xf21d0004
914#define F0900_P2_ETAPE1A_DVBXMEM 0xf21d0003
915 965
916/*P2_DMDCFG3*/ 966/*P2_DMDCFG3*/
917#define R0900_P2_DMDCFG3 0xf21e 967#define R0900_P2_DMDCFG3 0xf21e
918#define F0900_P2_DVBS1_TMGWAIT 0xf21e0080 968#define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
919#define F0900_P2_NO_BWCENTERING 0xf21e0040
920#define F0900_P2_INV_SEQSRCH 0xf21e0020
921#define F0900_P2_DIS_SFRUPLOW_TRK 0xf21e0010
922#define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
923#define F0900_P2_LOCKTIME_MODE 0xf21e0007
924 969
925/*P2_DMDCFG4*/ 970/*P2_DMDCFG4*/
926#define R0900_P2_DMDCFG4 0xf21f 971#define R0900_P2_DMDCFG4 0xf21f
927#define F0900_P2_TUNER_NRELAUNCH 0xf21f0008 972#define F0900_P2_TUNER_NRELAUNCH 0xf21f0008
928#define F0900_P2_DIS_CLKENABLE 0xf21f0004
929#define F0900_P2_DIS_HDRDIVLOCK 0xf21f0002
930#define F0900_P2_NO_TNRWBINIT 0xf21f0001
931 973
932/*P2_CORRELMANT*/ 974/*P2_CORRELMANT*/
933#define R0900_P2_CORRELMANT 0xf220 975#define R0900_P2_CORRELMANT 0xf220
934#define F0900_P2_CORREL_MANT 0xf22000ff 976#define F0900_P2_CORREL_MANT 0xf22000ff
935 977
936/*P2_CORRELABS*/ 978/*P2_CORRELABS*/
937#define R0900_P2_CORRELABS 0xf221 979#define R0900_P2_CORRELABS 0xf221
938#define F0900_P2_CORREL_ABS 0xf22100ff 980#define F0900_P2_CORREL_ABS 0xf22100ff
939 981
940/*P2_CORRELEXP*/ 982/*P2_CORRELEXP*/
941#define R0900_P2_CORRELEXP 0xf222 983#define R0900_P2_CORRELEXP 0xf222
942#define F0900_P2_CORREL_ABSEXP 0xf22200f0 984#define F0900_P2_CORREL_ABSEXP 0xf22200f0
943#define F0900_P2_CORREL_EXP 0xf222000f 985#define F0900_P2_CORREL_EXP 0xf222000f
944 986
945/*P2_PLHMODCOD*/ 987/*P2_PLHMODCOD*/
946#define R0900_P2_PLHMODCOD 0xf224 988#define R0900_P2_PLHMODCOD 0xf224
947#define F0900_P2_SPECINV_DEMOD 0xf2240080 989#define F0900_P2_SPECINV_DEMOD 0xf2240080
948#define F0900_P2_PLH_MODCOD 0xf224007c 990#define F0900_P2_PLH_MODCOD 0xf224007c
949#define F0900_P2_PLH_TYPE 0xf2240003 991#define F0900_P2_PLH_TYPE 0xf2240003
950 992
951/*P2_AGCK32*/ 993/*P2_DMDREG*/
952#define R0900_P2_AGCK32 0xf22b 994#define R0900_P2_DMDREG 0xf225
953#define F0900_P2_R3ADJOFF_32APSK 0xf22b0080 995#define F0900_P2_DECIM_PLFRAMES 0xf2250001
954#define F0900_P2_R2ADJOFF_32APSK 0xf22b0040
955#define F0900_P2_R1ADJOFF_32APSK 0xf22b0020
956#define F0900_P2_RADJ_32APSK 0xf22b001f
957 996
958/*P2_AGC2O*/ 997/*P2_AGC2O*/
959#define R0900_P2_AGC2O 0xf22c 998#define R0900_P2_AGC2O 0xf22c
960#define F0900_P2_AGC2REF_ADJUSTING 0xf22c0080 999#define F0900_P2_AGC2_COEF 0xf22c0007
961#define F0900_P2_AGC2_COARSEFAST 0xf22c0040
962#define F0900_P2_AGC2_LKSQRT 0xf22c0020
963#define F0900_P2_AGC2_LKMODE 0xf22c0010
964#define F0900_P2_AGC2_LKEQUA 0xf22c0008
965#define F0900_P2_AGC2_COEF 0xf22c0007
966 1000
967/*P2_AGC2REF*/ 1001/*P2_AGC2REF*/
968#define R0900_P2_AGC2REF 0xf22d 1002#define R0900_P2_AGC2REF 0xf22d
969#define F0900_P2_AGC2_REF 0xf22d00ff 1003#define F0900_P2_AGC2_REF 0xf22d00ff
970 1004
971/*P2_AGC1ADJ*/ 1005/*P2_AGC1ADJ*/
972#define R0900_P2_AGC1ADJ 0xf22e 1006#define R0900_P2_AGC1ADJ 0xf22e
973#define F0900_P2_AGC1ADJ_MANUAL 0xf22e0080 1007#define F0900_P2_AGC1_ADJUSTED 0xf22e007f
974#define F0900_P2_AGC1_ADJUSTED 0xf22e017f
975 1008
976/*P2_AGC2I1*/ 1009/*P2_AGC2I1*/
977#define R0900_P2_AGC2I1 0xf236 1010#define R0900_P2_AGC2I1 0xf236
978#define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff 1011#define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff
979 1012
980/*P2_AGC2I0*/ 1013/*P2_AGC2I0*/
981#define R0900_P2_AGC2I0 0xf237 1014#define R0900_P2_AGC2I0 0xf237
982#define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff 1015#define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff
983 1016
984/*P2_CARCFG*/ 1017/*P2_CARCFG*/
985#define R0900_P2_CARCFG 0xf238 1018#define R0900_P2_CARCFG 0xf238
986#define F0900_P2_CFRUPLOW_AUTO 0xf2380080 1019#define F0900_P2_CFRUPLOW_AUTO 0xf2380080
987#define F0900_P2_CFRUPLOW_TEST 0xf2380040 1020#define F0900_P2_CFRUPLOW_TEST 0xf2380040
988#define F0900_P2_EN_CAR2CENTER 0xf2380020 1021#define F0900_P2_ROTAON 0xf2380004
989#define F0900_P2_CARHDR_NODIV8 0xf2380010 1022#define F0900_P2_PH_DET_ALGO 0xf2380003
990#define F0900_P2_I2C_ROTA 0xf2380008
991#define F0900_P2_ROTAON 0xf2380004
992#define F0900_P2_PH_DET_ALGO 0xf2380003
993 1023
994/*P2_ACLC*/ 1024/*P2_ACLC*/
995#define R0900_P2_ACLC 0xf239 1025#define R0900_P2_ACLC 0xf239
996#define F0900_P2_STOP_S2ALPHA 0xf23900c0 1026#define F0900_P2_CAR_ALPHA_MANT 0xf2390030
997#define F0900_P2_CAR_ALPHA_MANT 0xf2390030 1027#define F0900_P2_CAR_ALPHA_EXP 0xf239000f
998#define F0900_P2_CAR_ALPHA_EXP 0xf239000f
999 1028
1000/*P2_BCLC*/ 1029/*P2_BCLC*/
1001#define R0900_P2_BCLC 0xf23a 1030#define R0900_P2_BCLC 0xf23a
1002#define F0900_P2_STOP_S2BETA 0xf23a00c0 1031#define F0900_P2_CAR_BETA_MANT 0xf23a0030
1003#define F0900_P2_CAR_BETA_MANT 0xf23a0030 1032#define F0900_P2_CAR_BETA_EXP 0xf23a000f
1004#define F0900_P2_CAR_BETA_EXP 0xf23a000f
1005 1033
1006/*P2_CARFREQ*/ 1034/*P2_CARFREQ*/
1007#define R0900_P2_CARFREQ 0xf23d 1035#define R0900_P2_CARFREQ 0xf23d
1008#define F0900_P2_KC_COARSE_EXP 0xf23d00f0 1036#define F0900_P2_KC_COARSE_EXP 0xf23d00f0
1009#define F0900_P2_BETA_FREQ 0xf23d000f 1037#define F0900_P2_BETA_FREQ 0xf23d000f
1010 1038
1011/*P2_CARHDR*/ 1039/*P2_CARHDR*/
1012#define R0900_P2_CARHDR 0xf23e 1040#define R0900_P2_CARHDR 0xf23e
1013#define F0900_P2_K_FREQ_HDR 0xf23e00ff 1041#define F0900_P2_K_FREQ_HDR 0xf23e00ff
1014 1042
1015/*P2_LDT*/ 1043/*P2_LDT*/
1016#define R0900_P2_LDT 0xf23f 1044#define R0900_P2_LDT 0xf23f
1017#define F0900_P2_CARLOCK_THRES 0xf23f01ff 1045#define F0900_P2_CARLOCK_THRES 0xf23f01ff
1018 1046
1019/*P2_LDT2*/ 1047/*P2_LDT2*/
1020#define R0900_P2_LDT2 0xf240 1048#define R0900_P2_LDT2 0xf240
1021#define F0900_P2_CARLOCK_THRES2 0xf24001ff 1049#define F0900_P2_CARLOCK_THRES2 0xf24001ff
1022 1050
1023/*P2_CFRICFG*/ 1051/*P2_CFRICFG*/
1024#define R0900_P2_CFRICFG 0xf241 1052#define R0900_P2_CFRICFG 0xf241
1025#define F0900_P2_CFRINIT_UNVALRNG 0xf2410080 1053#define F0900_P2_NEG_CFRSTEP 0xf2410001
1026#define F0900_P2_CFRINIT_LUNVALCPT 0xf2410040
1027#define F0900_P2_CFRINIT_ABORTDBL 0xf2410020
1028#define F0900_P2_CFRINIT_ABORTPRED 0xf2410010
1029#define F0900_P2_CFRINIT_UNVALSKIP 0xf2410008
1030#define F0900_P2_CFRINIT_CSTINC 0xf2410004
1031#define F0900_P2_NEG_CFRSTEP 0xf2410001
1032 1054
1033/*P2_CFRUP1*/ 1055/*P2_CFRUP1*/
1034#define R0900_P2_CFRUP1 0xf242 1056#define R0900_P2_CFRUP1 0xf242
1035#define F0900_P2_CFR_UP1 0xf24201ff 1057#define F0900_P2_CFR_UP1 0xf24201ff
1036 1058
1037/*P2_CFRUP0*/ 1059/*P2_CFRUP0*/
1038#define R0900_P2_CFRUP0 0xf243 1060#define R0900_P2_CFRUP0 0xf243
1039#define F0900_P2_CFR_UP0 0xf24300ff 1061#define F0900_P2_CFR_UP0 0xf24300ff
1040 1062
1041/*P2_CFRLOW1*/ 1063/*P2_CFRLOW1*/
1042#define R0900_P2_CFRLOW1 0xf246 1064#define R0900_P2_CFRLOW1 0xf246
1043#define F0900_P2_CFR_LOW1 0xf24601ff 1065#define F0900_P2_CFR_LOW1 0xf24601ff
1044 1066
1045/*P2_CFRLOW0*/ 1067/*P2_CFRLOW0*/
1046#define R0900_P2_CFRLOW0 0xf247 1068#define R0900_P2_CFRLOW0 0xf247
1047#define F0900_P2_CFR_LOW0 0xf24700ff 1069#define F0900_P2_CFR_LOW0 0xf24700ff
1048 1070
1049/*P2_CFRINIT1*/ 1071/*P2_CFRINIT1*/
1050#define R0900_P2_CFRINIT1 0xf248 1072#define R0900_P2_CFRINIT1 0xf248
1051#define F0900_P2_CFR_INIT1 0xf24801ff 1073#define F0900_P2_CFR_INIT1 0xf24801ff
1052 1074
1053/*P2_CFRINIT0*/ 1075/*P2_CFRINIT0*/
1054#define R0900_P2_CFRINIT0 0xf249 1076#define R0900_P2_CFRINIT0 0xf249
1055#define F0900_P2_CFR_INIT0 0xf24900ff 1077#define F0900_P2_CFR_INIT0 0xf24900ff
1056 1078
1057/*P2_CFRINC1*/ 1079/*P2_CFRINC1*/
1058#define R0900_P2_CFRINC1 0xf24a 1080#define R0900_P2_CFRINC1 0xf24a
1059#define F0900_P2_MANUAL_CFRINC 0xf24a0080 1081#define F0900_P2_MANUAL_CFRINC 0xf24a0080
1060#define F0900_P2_CFR_INC1 0xf24a017f 1082#define F0900_P2_CFR_INC1 0xf24a003f
1061 1083
1062/*P2_CFRINC0*/ 1084/*P2_CFRINC0*/
1063#define R0900_P2_CFRINC0 0xf24b 1085#define R0900_P2_CFRINC0 0xf24b
1064#define F0900_P2_CFR_INC0 0xf24b00f0 1086#define F0900_P2_CFR_INC0 0xf24b00f8
1065 1087
1066/*P2_CFR2*/ 1088/*P2_CFR2*/
1067#define R0900_P2_CFR2 0xf24c 1089#define R0900_P2_CFR2 0xf24c
1068#define F0900_P2_CAR_FREQ2 0xf24c01ff 1090#define F0900_P2_CAR_FREQ2 0xf24c01ff
1069 1091
1070/*P2_CFR1*/ 1092/*P2_CFR1*/
1071#define R0900_P2_CFR1 0xf24d 1093#define R0900_P2_CFR1 0xf24d
1072#define F0900_P2_CAR_FREQ1 0xf24d00ff 1094#define F0900_P2_CAR_FREQ1 0xf24d00ff
1073 1095
1074/*P2_CFR0*/ 1096/*P2_CFR0*/
1075#define R0900_P2_CFR0 0xf24e 1097#define R0900_P2_CFR0 0xf24e
1076#define F0900_P2_CAR_FREQ0 0xf24e00ff 1098#define F0900_P2_CAR_FREQ0 0xf24e00ff
1077 1099
1078/*P2_LDI*/ 1100/*P2_LDI*/
1079#define R0900_P2_LDI 0xf24f 1101#define R0900_P2_LDI 0xf24f
1080#define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff 1102#define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff
1081 1103
1082/*P2_TMGCFG*/ 1104/*P2_TMGCFG*/
1083#define R0900_P2_TMGCFG 0xf250 1105#define R0900_P2_TMGCFG 0xf250
1084#define F0900_P2_TMGLOCK_BETA 0xf25000c0 1106#define F0900_P2_TMGLOCK_BETA 0xf25000c0
1085#define F0900_P2_NOTMG_GROUPDELAY 0xf2500020 1107#define F0900_P2_DO_TIMING_CORR 0xf2500010
1086#define F0900_P2_DO_TIMING_CORR 0xf2500010 1108#define F0900_P2_TMG_MINFREQ 0xf2500003
1087#define F0900_P2_MANUAL_SCAN 0xf250000c
1088#define F0900_P2_TMG_MINFREQ 0xf2500003
1089 1109
1090/*P2_RTC*/ 1110/*P2_RTC*/
1091#define R0900_P2_RTC 0xf251 1111#define R0900_P2_RTC 0xf251
1092#define F0900_P2_TMGALPHA_EXP 0xf25100f0 1112#define F0900_P2_TMGALPHA_EXP 0xf25100f0
1093#define F0900_P2_TMGBETA_EXP 0xf251000f 1113#define F0900_P2_TMGBETA_EXP 0xf251000f
1094 1114
1095/*P2_RTCS2*/ 1115/*P2_RTCS2*/
1096#define R0900_P2_RTCS2 0xf252 1116#define R0900_P2_RTCS2 0xf252
1097#define F0900_P2_TMGALPHAS2_EXP 0xf25200f0 1117#define F0900_P2_TMGALPHAS2_EXP 0xf25200f0
1098#define F0900_P2_TMGBETAS2_EXP 0xf252000f 1118#define F0900_P2_TMGBETAS2_EXP 0xf252000f
1099 1119
1100/*P2_TMGTHRISE*/ 1120/*P2_TMGTHRISE*/
1101#define R0900_P2_TMGTHRISE 0xf253 1121#define R0900_P2_TMGTHRISE 0xf253
1102#define F0900_P2_TMGLOCK_THRISE 0xf25300ff 1122#define F0900_P2_TMGLOCK_THRISE 0xf25300ff
1103 1123
1104/*P2_TMGTHFALL*/ 1124/*P2_TMGTHFALL*/
1105#define R0900_P2_TMGTHFALL 0xf254 1125#define R0900_P2_TMGTHFALL 0xf254
1106#define F0900_P2_TMGLOCK_THFALL 0xf25400ff 1126#define F0900_P2_TMGLOCK_THFALL 0xf25400ff
1107 1127
1108/*P2_SFRUPRATIO*/ 1128/*P2_SFRUPRATIO*/
1109#define R0900_P2_SFRUPRATIO 0xf255 1129#define R0900_P2_SFRUPRATIO 0xf255
1110#define F0900_P2_SFR_UPRATIO 0xf25500ff 1130#define F0900_P2_SFR_UPRATIO 0xf25500ff
1111 1131
1112/*P2_SFRLOWRATIO*/ 1132/*P2_SFRLOWRATIO*/
1113#define R0900_P2_SFRLOWRATIO 0xf256 1133#define R0900_P2_SFRLOWRATIO 0xf256
1114#define F0900_P2_SFR_LOWRATIO 0xf25600ff 1134#define F0900_P2_SFR_LOWRATIO 0xf25600ff
1115 1135
1116/*P2_KREFTMG*/ 1136/*P2_KREFTMG*/
1117#define R0900_P2_KREFTMG 0xf258 1137#define R0900_P2_KREFTMG 0xf258
1118#define F0900_P2_KREF_TMG 0xf25800ff 1138#define F0900_P2_KREF_TMG 0xf25800ff
1119 1139
1120/*P2_SFRSTEP*/ 1140/*P2_SFRSTEP*/
1121#define R0900_P2_SFRSTEP 0xf259 1141#define R0900_P2_SFRSTEP 0xf259
1122#define F0900_P2_SFR_SCANSTEP 0xf25900f0 1142#define F0900_P2_SFR_SCANSTEP 0xf25900f0
1123#define F0900_P2_SFR_CENTERSTEP 0xf259000f 1143#define F0900_P2_SFR_CENTERSTEP 0xf259000f
1124 1144
1125/*P2_TMGCFG2*/ 1145/*P2_TMGCFG2*/
1126#define R0900_P2_TMGCFG2 0xf25a 1146#define R0900_P2_TMGCFG2 0xf25a
1127#define F0900_P2_DIS_AUTOSAMP 0xf25a0008 1147#define F0900_P2_SFRRATIO_FINE 0xf25a0001
1128#define F0900_P2_SCANINIT_QUART 0xf25a0004 1148
1129#define F0900_P2_NOTMG_DVBS1DERAT 0xf25a0002 1149/*P2_KREFTMG2*/
1130#define F0900_P2_SFRRATIO_FINE 0xf25a0001 1150#define R0900_P2_KREFTMG2 0xf25b
1151#define F0900_P2_KREF_TMG2 0xf25b00ff
1131 1152
1132/*P2_SFRINIT1*/ 1153/*P2_SFRINIT1*/
1133#define R0900_P2_SFRINIT1 0xf25e 1154#define R0900_P2_SFRINIT1 0xf25e
1134#define F0900_P2_SFR_INIT1 0xf25e00ff 1155#define F0900_P2_SFR_INIT1 0xf25e007f
1135 1156
1136/*P2_SFRINIT0*/ 1157/*P2_SFRINIT0*/
1137#define R0900_P2_SFRINIT0 0xf25f 1158#define R0900_P2_SFRINIT0 0xf25f
1138#define F0900_P2_SFR_INIT0 0xf25f00ff 1159#define F0900_P2_SFR_INIT0 0xf25f00ff
1139 1160
1140/*P2_SFRUP1*/ 1161/*P2_SFRUP1*/
1141#define R0900_P2_SFRUP1 0xf260 1162#define R0900_P2_SFRUP1 0xf260
1142#define F0900_P2_AUTO_GUP 0xf2600080 1163#define F0900_P2_AUTO_GUP 0xf2600080
1143#define F0900_P2_SYMB_FREQ_UP1 0xf260007f 1164#define F0900_P2_SYMB_FREQ_UP1 0xf260007f
1144 1165
1145/*P2_SFRUP0*/ 1166/*P2_SFRUP0*/
1146#define R0900_P2_SFRUP0 0xf261 1167#define R0900_P2_SFRUP0 0xf261
1147#define F0900_P2_SYMB_FREQ_UP0 0xf26100ff 1168#define F0900_P2_SYMB_FREQ_UP0 0xf26100ff
1148 1169
1149/*P2_SFRLOW1*/ 1170/*P2_SFRLOW1*/
1150#define R0900_P2_SFRLOW1 0xf262 1171#define R0900_P2_SFRLOW1 0xf262
1151#define F0900_P2_AUTO_GLOW 0xf2620080 1172#define F0900_P2_AUTO_GLOW 0xf2620080
1152#define F0900_P2_SYMB_FREQ_LOW1 0xf262007f 1173#define F0900_P2_SYMB_FREQ_LOW1 0xf262007f
1153 1174
1154/*P2_SFRLOW0*/ 1175/*P2_SFRLOW0*/
1155#define R0900_P2_SFRLOW0 0xf263 1176#define R0900_P2_SFRLOW0 0xf263
1156#define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff 1177#define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff
1157 1178
1158/*P2_SFR3*/ 1179/*P2_SFR3*/
1159#define R0900_P2_SFR3 0xf264 1180#define R0900_P2_SFR3 0xf264
1160#define F0900_P2_SYMB_FREQ3 0xf26400ff 1181#define F0900_P2_SYMB_FREQ3 0xf26400ff
1161 1182
1162/*P2_SFR2*/ 1183/*P2_SFR2*/
1163#define R0900_P2_SFR2 0xf265 1184#define R0900_P2_SFR2 0xf265
1164#define F0900_P2_SYMB_FREQ2 0xf26500ff 1185#define F0900_P2_SYMB_FREQ2 0xf26500ff
1165 1186
1166/*P2_SFR1*/ 1187/*P2_SFR1*/
1167#define R0900_P2_SFR1 0xf266 1188#define R0900_P2_SFR1 0xf266
1168#define F0900_P2_SYMB_FREQ1 0xf26600ff 1189#define F0900_P2_SYMB_FREQ1 0xf26600ff
1169 1190
1170/*P2_SFR0*/ 1191/*P2_SFR0*/
1171#define R0900_P2_SFR0 0xf267 1192#define R0900_P2_SFR0 0xf267
1172#define F0900_P2_SYMB_FREQ0 0xf26700ff 1193#define F0900_P2_SYMB_FREQ0 0xf26700ff
1173 1194
1174/*P2_TMGREG2*/ 1195/*P2_TMGREG2*/
1175#define R0900_P2_TMGREG2 0xf268 1196#define R0900_P2_TMGREG2 0xf268
1176#define F0900_P2_TMGREG2 0xf26800ff 1197#define F0900_P2_TMGREG2 0xf26800ff
1177 1198
1178/*P2_TMGREG1*/ 1199/*P2_TMGREG1*/
1179#define R0900_P2_TMGREG1 0xf269 1200#define R0900_P2_TMGREG1 0xf269
1180#define F0900_P2_TMGREG1 0xf26900ff 1201#define F0900_P2_TMGREG1 0xf26900ff
1181 1202
1182/*P2_TMGREG0*/ 1203/*P2_TMGREG0*/
1183#define R0900_P2_TMGREG0 0xf26a 1204#define R0900_P2_TMGREG0 0xf26a
1184#define F0900_P2_TMGREG0 0xf26a00ff 1205#define F0900_P2_TMGREG0 0xf26a00ff
1185 1206
1186/*P2_TMGLOCK1*/ 1207/*P2_TMGLOCK1*/
1187#define R0900_P2_TMGLOCK1 0xf26b 1208#define R0900_P2_TMGLOCK1 0xf26b
1188#define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff 1209#define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff
1189 1210
1190/*P2_TMGLOCK0*/ 1211/*P2_TMGLOCK0*/
1191#define R0900_P2_TMGLOCK0 0xf26c 1212#define R0900_P2_TMGLOCK0 0xf26c
1192#define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff 1213#define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff
1193 1214
1194/*P2_TMGOBS*/ 1215/*P2_TMGOBS*/
1195#define R0900_P2_TMGOBS 0xf26d 1216#define R0900_P2_TMGOBS 0xf26d
1196#define F0900_P2_ROLLOFF_STATUS 0xf26d00c0 1217#define F0900_P2_ROLLOFF_STATUS 0xf26d00c0
1197#define F0900_P2_SCAN_SIGN 0xf26d0030
1198#define F0900_P2_TMG_SCANNING 0xf26d0008
1199#define F0900_P2_CHCENTERING_MODE 0xf26d0004
1200#define F0900_P2_TMG_SCANFAIL 0xf26d0002
1201 1218
1202/*P2_EQUALCFG*/ 1219/*P2_EQUALCFG*/
1203#define R0900_P2_EQUALCFG 0xf26f 1220#define R0900_P2_EQUALCFG 0xf26f
1204#define F0900_P2_NOTMG_NEGALWAIT 0xf26f0080 1221#define F0900_P2_EQUAL_ON 0xf26f0040
1205#define F0900_P2_EQUAL_ON 0xf26f0040 1222#define F0900_P2_MU_EQUALDFE 0xf26f0007
1206#define F0900_P2_SEL_EQUALCOR 0xf26f0038
1207#define F0900_P2_MU_EQUALDFE 0xf26f0007
1208 1223
1209/*P2_EQUAI1*/ 1224/*P2_EQUAI1*/
1210#define R0900_P2_EQUAI1 0xf270 1225#define R0900_P2_EQUAI1 0xf270
1211#define F0900_P2_EQUA_ACCI1 0xf27001ff 1226#define F0900_P2_EQUA_ACCI1 0xf27001ff
1212 1227
1213/*P2_EQUAQ1*/ 1228/*P2_EQUAQ1*/
1214#define R0900_P2_EQUAQ1 0xf271 1229#define R0900_P2_EQUAQ1 0xf271
1215#define F0900_P2_EQUA_ACCQ1 0xf27101ff 1230#define F0900_P2_EQUA_ACCQ1 0xf27101ff
1216 1231
1217/*P2_EQUAI2*/ 1232/*P2_EQUAI2*/
1218#define R0900_P2_EQUAI2 0xf272 1233#define R0900_P2_EQUAI2 0xf272
1219#define F0900_P2_EQUA_ACCI2 0xf27201ff 1234#define F0900_P2_EQUA_ACCI2 0xf27201ff
1220 1235
1221/*P2_EQUAQ2*/ 1236/*P2_EQUAQ2*/
1222#define R0900_P2_EQUAQ2 0xf273 1237#define R0900_P2_EQUAQ2 0xf273
1223#define F0900_P2_EQUA_ACCQ2 0xf27301ff 1238#define F0900_P2_EQUA_ACCQ2 0xf27301ff
1224 1239
1225/*P2_EQUAI3*/ 1240/*P2_EQUAI3*/
1226#define R0900_P2_EQUAI3 0xf274 1241#define R0900_P2_EQUAI3 0xf274
1227#define F0900_P2_EQUA_ACCI3 0xf27401ff 1242#define F0900_P2_EQUA_ACCI3 0xf27401ff
1228 1243
1229/*P2_EQUAQ3*/ 1244/*P2_EQUAQ3*/
1230#define R0900_P2_EQUAQ3 0xf275 1245#define R0900_P2_EQUAQ3 0xf275
1231#define F0900_P2_EQUA_ACCQ3 0xf27501ff 1246#define F0900_P2_EQUA_ACCQ3 0xf27501ff
1232 1247
1233/*P2_EQUAI4*/ 1248/*P2_EQUAI4*/
1234#define R0900_P2_EQUAI4 0xf276 1249#define R0900_P2_EQUAI4 0xf276
1235#define F0900_P2_EQUA_ACCI4 0xf27601ff 1250#define F0900_P2_EQUA_ACCI4 0xf27601ff
1236 1251
1237/*P2_EQUAQ4*/ 1252/*P2_EQUAQ4*/
1238#define R0900_P2_EQUAQ4 0xf277 1253#define R0900_P2_EQUAQ4 0xf277
1239#define F0900_P2_EQUA_ACCQ4 0xf27701ff 1254#define F0900_P2_EQUA_ACCQ4 0xf27701ff
1240 1255
1241/*P2_EQUAI5*/ 1256/*P2_EQUAI5*/
1242#define R0900_P2_EQUAI5 0xf278 1257#define R0900_P2_EQUAI5 0xf278
1243#define F0900_P2_EQUA_ACCI5 0xf27801ff 1258#define F0900_P2_EQUA_ACCI5 0xf27801ff
1244 1259
1245/*P2_EQUAQ5*/ 1260/*P2_EQUAQ5*/
1246#define R0900_P2_EQUAQ5 0xf279 1261#define R0900_P2_EQUAQ5 0xf279
1247#define F0900_P2_EQUA_ACCQ5 0xf27901ff 1262#define F0900_P2_EQUA_ACCQ5 0xf27901ff
1248 1263
1249/*P2_EQUAI6*/ 1264/*P2_EQUAI6*/
1250#define R0900_P2_EQUAI6 0xf27a 1265#define R0900_P2_EQUAI6 0xf27a
1251#define F0900_P2_EQUA_ACCI6 0xf27a01ff 1266#define F0900_P2_EQUA_ACCI6 0xf27a01ff
1252 1267
1253/*P2_EQUAQ6*/ 1268/*P2_EQUAQ6*/
1254#define R0900_P2_EQUAQ6 0xf27b 1269#define R0900_P2_EQUAQ6 0xf27b
1255#define F0900_P2_EQUA_ACCQ6 0xf27b01ff 1270#define F0900_P2_EQUA_ACCQ6 0xf27b01ff
1256 1271
1257/*P2_EQUAI7*/ 1272/*P2_EQUAI7*/
1258#define R0900_P2_EQUAI7 0xf27c 1273#define R0900_P2_EQUAI7 0xf27c
1259#define F0900_P2_EQUA_ACCI7 0xf27c01ff 1274#define F0900_P2_EQUA_ACCI7 0xf27c01ff
1260 1275
1261/*P2_EQUAQ7*/ 1276/*P2_EQUAQ7*/
1262#define R0900_P2_EQUAQ7 0xf27d 1277#define R0900_P2_EQUAQ7 0xf27d
1263#define F0900_P2_EQUA_ACCQ7 0xf27d01ff 1278#define F0900_P2_EQUA_ACCQ7 0xf27d01ff
1264 1279
1265/*P2_EQUAI8*/ 1280/*P2_EQUAI8*/
1266#define R0900_P2_EQUAI8 0xf27e 1281#define R0900_P2_EQUAI8 0xf27e
1267#define F0900_P2_EQUA_ACCI8 0xf27e01ff 1282#define F0900_P2_EQUA_ACCI8 0xf27e01ff
1268 1283
1269/*P2_EQUAQ8*/ 1284/*P2_EQUAQ8*/
1270#define R0900_P2_EQUAQ8 0xf27f 1285#define R0900_P2_EQUAQ8 0xf27f
1271#define F0900_P2_EQUA_ACCQ8 0xf27f01ff 1286#define F0900_P2_EQUA_ACCQ8 0xf27f01ff
1272 1287
1273/*P2_NNOSDATAT1*/ 1288/*P2_NNOSDATAT1*/
1274#define R0900_P2_NNOSDATAT1 0xf280 1289#define R0900_P2_NNOSDATAT1 0xf280
1275#define F0900_P2_NOSDATAT_NORMED1 0xf28000ff 1290#define F0900_P2_NOSDATAT_NORMED1 0xf28000ff
1276 1291
1277/*P2_NNOSDATAT0*/ 1292/*P2_NNOSDATAT0*/
1278#define R0900_P2_NNOSDATAT0 0xf281 1293#define R0900_P2_NNOSDATAT0 0xf281
1279#define F0900_P2_NOSDATAT_NORMED0 0xf28100ff 1294#define F0900_P2_NOSDATAT_NORMED0 0xf28100ff
1280 1295
1281/*P2_NNOSDATA1*/ 1296/*P2_NNOSDATA1*/
1282#define R0900_P2_NNOSDATA1 0xf282 1297#define R0900_P2_NNOSDATA1 0xf282
1283#define F0900_P2_NOSDATA_NORMED1 0xf28200ff 1298#define F0900_P2_NOSDATA_NORMED1 0xf28200ff
1284 1299
1285/*P2_NNOSDATA0*/ 1300/*P2_NNOSDATA0*/
1286#define R0900_P2_NNOSDATA0 0xf283 1301#define R0900_P2_NNOSDATA0 0xf283
1287#define F0900_P2_NOSDATA_NORMED0 0xf28300ff 1302#define F0900_P2_NOSDATA_NORMED0 0xf28300ff
1288 1303
1289/*P2_NNOSPLHT1*/ 1304/*P2_NNOSPLHT1*/
1290#define R0900_P2_NNOSPLHT1 0xf284 1305#define R0900_P2_NNOSPLHT1 0xf284
1291#define F0900_P2_NOSPLHT_NORMED1 0xf28400ff 1306#define F0900_P2_NOSPLHT_NORMED1 0xf28400ff
1292 1307
1293/*P2_NNOSPLHT0*/ 1308/*P2_NNOSPLHT0*/
1294#define R0900_P2_NNOSPLHT0 0xf285 1309#define R0900_P2_NNOSPLHT0 0xf285
1295#define F0900_P2_NOSPLHT_NORMED0 0xf28500ff 1310#define F0900_P2_NOSPLHT_NORMED0 0xf28500ff
1296 1311
1297/*P2_NNOSPLH1*/ 1312/*P2_NNOSPLH1*/
1298#define R0900_P2_NNOSPLH1 0xf286 1313#define R0900_P2_NNOSPLH1 0xf286
1299#define F0900_P2_NOSPLH_NORMED1 0xf28600ff 1314#define F0900_P2_NOSPLH_NORMED1 0xf28600ff
1300 1315
1301/*P2_NNOSPLH0*/ 1316/*P2_NNOSPLH0*/
1302#define R0900_P2_NNOSPLH0 0xf287 1317#define R0900_P2_NNOSPLH0 0xf287
1303#define F0900_P2_NOSPLH_NORMED0 0xf28700ff 1318#define F0900_P2_NOSPLH_NORMED0 0xf28700ff
1304 1319
1305/*P2_NOSDATAT1*/ 1320/*P2_NOSDATAT1*/
1306#define R0900_P2_NOSDATAT1 0xf288 1321#define R0900_P2_NOSDATAT1 0xf288
1307#define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff 1322#define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff
1308 1323
1309/*P2_NOSDATAT0*/ 1324/*P2_NOSDATAT0*/
1310#define R0900_P2_NOSDATAT0 0xf289 1325#define R0900_P2_NOSDATAT0 0xf289
1311#define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff 1326#define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff
1312 1327
1313/*P2_NOSDATA1*/ 1328/*P2_NOSDATA1*/
1314#define R0900_P2_NOSDATA1 0xf28a 1329#define R0900_P2_NOSDATA1 0xf28a
1315#define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff 1330#define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff
1316 1331
1317/*P2_NOSDATA0*/ 1332/*P2_NOSDATA0*/
1318#define R0900_P2_NOSDATA0 0xf28b 1333#define R0900_P2_NOSDATA0 0xf28b
1319#define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff 1334#define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff
1320 1335
1321/*P2_NOSPLHT1*/ 1336/*P2_NOSPLHT1*/
1322#define R0900_P2_NOSPLHT1 0xf28c 1337#define R0900_P2_NOSPLHT1 0xf28c
1323#define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff 1338#define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff
1324 1339
1325/*P2_NOSPLHT0*/ 1340/*P2_NOSPLHT0*/
1326#define R0900_P2_NOSPLHT0 0xf28d 1341#define R0900_P2_NOSPLHT0 0xf28d
1327#define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff 1342#define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff
1328 1343
1329/*P2_NOSPLH1*/ 1344/*P2_NOSPLH1*/
1330#define R0900_P2_NOSPLH1 0xf28e 1345#define R0900_P2_NOSPLH1 0xf28e
1331#define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff 1346#define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff
1332 1347
1333/*P2_NOSPLH0*/ 1348/*P2_NOSPLH0*/
1334#define R0900_P2_NOSPLH0 0xf28f 1349#define R0900_P2_NOSPLH0 0xf28f
1335#define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff 1350#define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff
1336 1351
1337/*P2_CAR2CFG*/ 1352/*P2_CAR2CFG*/
1338#define R0900_P2_CAR2CFG 0xf290 1353#define R0900_P2_CAR2CFG 0xf290
1339#define F0900_P2_DESCRAMB_OFF 0xf2900080 1354#define F0900_P2_CARRIER3_DISABLE 0xf2900040
1340#define F0900_P2_PN4_SELECT 0xf2900040 1355#define F0900_P2_ROTA2ON 0xf2900004
1341#define F0900_P2_CFR2_STOPDVBS1 0xf2900020 1356#define F0900_P2_PH_DET_ALGO2 0xf2900003
1342#define F0900_P2_STOP_CFR2UPDATE 0xf2900010 1357
1343#define F0900_P2_STOP_NCO2UPDATE 0xf2900008 1358/*P2_CFR2CFR1*/
1344#define F0900_P2_ROTA2ON 0xf2900004 1359#define R0900_P2_CFR2CFR1 0xf291
1345#define F0900_P2_PH_DET_ALGO2 0xf2900003 1360#define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0
1346 1361#define F0900_P2_EN_S2CAR2CENTER 0xf2910020
1347/*P2_ACLC2*/ 1362#define F0900_P2_DIS_BCHERRCFR2 0xf2910010
1348#define R0900_P2_ACLC2 0xf291 1363#define F0900_P2_CFR2TOCFR1_BETA 0xf2910007
1349#define F0900_P2_CAR2_PUNCT_ADERAT 0xf2910040
1350#define F0900_P2_CAR2_ALPHA_MANT 0xf2910030
1351#define F0900_P2_CAR2_ALPHA_EXP 0xf291000f
1352
1353/*P2_BCLC2*/
1354#define R0900_P2_BCLC2 0xf292
1355#define F0900_P2_DVBS2_NIP 0xf2920080
1356#define F0900_P2_CAR2_PUNCT_BDERAT 0xf2920040
1357#define F0900_P2_CAR2_BETA_MANT 0xf2920030
1358#define F0900_P2_CAR2_BETA_EXP 0xf292000f
1359 1364
1360/*P2_CFR22*/ 1365/*P2_CFR22*/
1361#define R0900_P2_CFR22 0xf293 1366#define R0900_P2_CFR22 0xf293
1362#define F0900_P2_CAR2_FREQ2 0xf29301ff 1367#define F0900_P2_CAR2_FREQ2 0xf29301ff
1363 1368
1364/*P2_CFR21*/ 1369/*P2_CFR21*/
1365#define R0900_P2_CFR21 0xf294 1370#define R0900_P2_CFR21 0xf294
1366#define F0900_P2_CAR2_FREQ1 0xf29400ff 1371#define F0900_P2_CAR2_FREQ1 0xf29400ff
1367 1372
1368/*P2_CFR20*/ 1373/*P2_CFR20*/
1369#define R0900_P2_CFR20 0xf295 1374#define R0900_P2_CFR20 0xf295
1370#define F0900_P2_CAR2_FREQ0 0xf29500ff 1375#define F0900_P2_CAR2_FREQ0 0xf29500ff
1371 1376
1372/*P2_ACLC2S2Q*/ 1377/*P2_ACLC2S2Q*/
1373#define R0900_P2_ACLC2S2Q 0xf297 1378#define R0900_P2_ACLC2S2Q 0xf297
1374#define F0900_P2_ENAB_SPSKSYMB 0xf2970080 1379#define F0900_P2_ENAB_SPSKSYMB 0xf2970080
1375#define F0900_P2_CAR2S2_QADERAT 0xf2970040 1380#define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030
1376#define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030 1381#define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f
1377#define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f
1378 1382
1379/*P2_ACLC2S28*/ 1383/*P2_ACLC2S28*/
1380#define R0900_P2_ACLC2S28 0xf298 1384#define R0900_P2_ACLC2S28 0xf298
1381#define F0900_P2_OLDI3Q_MODE 0xf2980080 1385#define F0900_P2_OLDI3Q_MODE 0xf2980080
1382#define F0900_P2_CAR2S2_8ADERAT 0xf2980040 1386#define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030
1383#define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030 1387#define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f
1384#define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f
1385 1388
1386/*P2_ACLC2S216A*/ 1389/*P2_ACLC2S216A*/
1387#define R0900_P2_ACLC2S216A 0xf299 1390#define R0900_P2_ACLC2S216A 0xf299
1388#define F0900_P2_CAR2S2_16ADERAT 0xf2990040 1391#define F0900_P2_DIS_C3STOPA2 0xf2990080
1389#define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030 1392#define F0900_P2_CAR2S2_16ADERAT 0xf2990040
1390#define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f 1393#define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030
1394#define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f
1391 1395
1392/*P2_ACLC2S232A*/ 1396/*P2_ACLC2S232A*/
1393#define R0900_P2_ACLC2S232A 0xf29a 1397#define R0900_P2_ACLC2S232A 0xf29a
1394#define F0900_P2_CAR2S2_32ADERAT 0xf29a0040 1398#define F0900_P2_CAR2S2_32ADERAT 0xf29a0040
1395#define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030 1399#define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030
1396#define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f 1400#define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f
1397 1401
1398/*P2_BCLC2S2Q*/ 1402/*P2_BCLC2S2Q*/
1399#define R0900_P2_BCLC2S2Q 0xf29c 1403#define R0900_P2_BCLC2S2Q 0xf29c
1400#define F0900_P2_DVBS2S2Q_NIP 0xf29c0080 1404#define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
1401#define F0900_P2_CAR2S2_QBDERAT 0xf29c0040 1405#define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f
1402#define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
1403#define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f
1404 1406
1405/*P2_BCLC2S28*/ 1407/*P2_BCLC2S28*/
1406#define R0900_P2_BCLC2S28 0xf29d 1408#define R0900_P2_BCLC2S28 0xf29d
1407#define F0900_P2_DVBS2S28_NIP 0xf29d0080 1409#define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
1408#define F0900_P2_CAR2S2_8BDERAT 0xf29d0040 1410#define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f
1409#define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
1410#define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f
1411 1411
1412/*P2_BCLC2S216A*/ 1412/*P2_BCLC2S216A*/
1413#define R0900_P2_BCLC2S216A 0xf29e 1413#define R0900_P2_BCLC2S216A 0xf29e
1414#define F0900_P2_DVBS2S216A_NIP 0xf29e0080
1415#define F0900_P2_CAR2S2_16BDERAT 0xf29e0040
1416#define F0900_P2_CAR2S2_16A_BETA_M 0xf29e0030
1417#define F0900_P2_CAR2S2_16A_BETA_E 0xf29e000f
1418 1414
1419/*P2_BCLC2S232A*/ 1415/*P2_BCLC2S232A*/
1420#define R0900_P2_BCLC2S232A 0xf29f 1416#define R0900_P2_BCLC2S232A 0xf29f
1421#define F0900_P2_DVBS2S232A_NIP 0xf29f0080
1422#define F0900_P2_CAR2S2_32BDERAT 0xf29f0040
1423#define F0900_P2_CAR2S2_32A_BETA_M 0xf29f0030
1424#define F0900_P2_CAR2S2_32A_BETA_E 0xf29f000f
1425 1417
1426/*P2_PLROOT2*/ 1418/*P2_PLROOT2*/
1427#define R0900_P2_PLROOT2 0xf2ac 1419#define R0900_P2_PLROOT2 0xf2ac
1428#define F0900_P2_SHORTFR_DISABLE 0xf2ac0080 1420#define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
1429#define F0900_P2_LONGFR_DISABLE 0xf2ac0040 1421#define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003
1430#define F0900_P2_DUMMYPL_DISABLE 0xf2ac0020
1431#define F0900_P2_SHORTFR_AVOID 0xf2ac0010
1432#define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
1433#define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003
1434 1422
1435/*P2_PLROOT1*/ 1423/*P2_PLROOT1*/
1436#define R0900_P2_PLROOT1 0xf2ad 1424#define R0900_P2_PLROOT1 0xf2ad
1437#define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff 1425#define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff
1438 1426
1439/*P2_PLROOT0*/ 1427/*P2_PLROOT0*/
1440#define R0900_P2_PLROOT0 0xf2ae 1428#define R0900_P2_PLROOT0 0xf2ae
1441#define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff 1429#define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff
1442 1430
1443/*P2_MODCODLST0*/ 1431/*P2_MODCODLST0*/
1444#define R0900_P2_MODCODLST0 0xf2b0 1432#define R0900_P2_MODCODLST0 0xf2b0
1445#define F0900_P2_EN_TOKEN31 0xf2b00080
1446#define F0900_P2_SYNCTAG_SELECT 0xf2b00040
1447#define F0900_P2_MODCODRQ_MODE 0xf2b00030
1448 1433
1449/*P2_MODCODLST1*/ 1434/*P2_MODCODLST1*/
1450#define R0900_P2_MODCODLST1 0xf2b1 1435#define R0900_P2_MODCODLST1 0xf2b1
1451#define F0900_P2_DIS_MODCOD29 0xf2b100f0 1436#define F0900_P2_DIS_MODCOD29 0xf2b100f0
1452#define F0900_P2_DIS_32PSK_9_10 0xf2b1000f 1437#define F0900_P2_DIS_32PSK_9_10 0xf2b1000f
1453 1438
1454/*P2_MODCODLST2*/ 1439/*P2_MODCODLST2*/
1455#define R0900_P2_MODCODLST2 0xf2b2 1440#define R0900_P2_MODCODLST2 0xf2b2
1456#define F0900_P2_DIS_32PSK_8_9 0xf2b200f0 1441#define F0900_P2_DIS_32PSK_8_9 0xf2b200f0
1457#define F0900_P2_DIS_32PSK_5_6 0xf2b2000f 1442#define F0900_P2_DIS_32PSK_5_6 0xf2b2000f
1458 1443
1459/*P2_MODCODLST3*/ 1444/*P2_MODCODLST3*/
1460#define R0900_P2_MODCODLST3 0xf2b3 1445#define R0900_P2_MODCODLST3 0xf2b3
1461#define F0900_P2_DIS_32PSK_4_5 0xf2b300f0 1446#define F0900_P2_DIS_32PSK_4_5 0xf2b300f0
1462#define F0900_P2_DIS_32PSK_3_4 0xf2b3000f 1447#define F0900_P2_DIS_32PSK_3_4 0xf2b3000f
1463 1448
1464/*P2_MODCODLST4*/ 1449/*P2_MODCODLST4*/
1465#define R0900_P2_MODCODLST4 0xf2b4 1450#define R0900_P2_MODCODLST4 0xf2b4
1466#define F0900_P2_DIS_16PSK_9_10 0xf2b400f0 1451#define F0900_P2_DIS_16PSK_9_10 0xf2b400f0
1467#define F0900_P2_DIS_16PSK_8_9 0xf2b4000f 1452#define F0900_P2_DIS_16PSK_8_9 0xf2b4000f
1468 1453
1469/*P2_MODCODLST5*/ 1454/*P2_MODCODLST5*/
1470#define R0900_P2_MODCODLST5 0xf2b5 1455#define R0900_P2_MODCODLST5 0xf2b5
1471#define F0900_P2_DIS_16PSK_5_6 0xf2b500f0 1456#define F0900_P2_DIS_16PSK_5_6 0xf2b500f0
1472#define F0900_P2_DIS_16PSK_4_5 0xf2b5000f 1457#define F0900_P2_DIS_16PSK_4_5 0xf2b5000f
1473 1458
1474/*P2_MODCODLST6*/ 1459/*P2_MODCODLST6*/
1475#define R0900_P2_MODCODLST6 0xf2b6 1460#define R0900_P2_MODCODLST6 0xf2b6
1476#define F0900_P2_DIS_16PSK_3_4 0xf2b600f0 1461#define F0900_P2_DIS_16PSK_3_4 0xf2b600f0
1477#define F0900_P2_DIS_16PSK_2_3 0xf2b6000f 1462#define F0900_P2_DIS_16PSK_2_3 0xf2b6000f
1478 1463
1479/*P2_MODCODLST7*/ 1464/*P2_MODCODLST7*/
1480#define R0900_P2_MODCODLST7 0xf2b7 1465#define R0900_P2_MODCODLST7 0xf2b7
1481#define F0900_P2_DIS_8P_9_10 0xf2b700f0 1466#define F0900_P2_DIS_8P_9_10 0xf2b700f0
1482#define F0900_P2_DIS_8P_8_9 0xf2b7000f 1467#define F0900_P2_DIS_8P_8_9 0xf2b7000f
1483 1468
1484/*P2_MODCODLST8*/ 1469/*P2_MODCODLST8*/
1485#define R0900_P2_MODCODLST8 0xf2b8 1470#define R0900_P2_MODCODLST8 0xf2b8
1486#define F0900_P2_DIS_8P_5_6 0xf2b800f0 1471#define F0900_P2_DIS_8P_5_6 0xf2b800f0
1487#define F0900_P2_DIS_8P_3_4 0xf2b8000f 1472#define F0900_P2_DIS_8P_3_4 0xf2b8000f
1488 1473
1489/*P2_MODCODLST9*/ 1474/*P2_MODCODLST9*/
1490#define R0900_P2_MODCODLST9 0xf2b9 1475#define R0900_P2_MODCODLST9 0xf2b9
1491#define F0900_P2_DIS_8P_2_3 0xf2b900f0 1476#define F0900_P2_DIS_8P_2_3 0xf2b900f0
1492#define F0900_P2_DIS_8P_3_5 0xf2b9000f 1477#define F0900_P2_DIS_8P_3_5 0xf2b9000f
1493 1478
1494/*P2_MODCODLSTA*/ 1479/*P2_MODCODLSTA*/
1495#define R0900_P2_MODCODLSTA 0xf2ba 1480#define R0900_P2_MODCODLSTA 0xf2ba
1496#define F0900_P2_DIS_QP_9_10 0xf2ba00f0 1481#define F0900_P2_DIS_QP_9_10 0xf2ba00f0
1497#define F0900_P2_DIS_QP_8_9 0xf2ba000f 1482#define F0900_P2_DIS_QP_8_9 0xf2ba000f
1498 1483
1499/*P2_MODCODLSTB*/ 1484/*P2_MODCODLSTB*/
1500#define R0900_P2_MODCODLSTB 0xf2bb 1485#define R0900_P2_MODCODLSTB 0xf2bb
1501#define F0900_P2_DIS_QP_5_6 0xf2bb00f0 1486#define F0900_P2_DIS_QP_5_6 0xf2bb00f0
1502#define F0900_P2_DIS_QP_4_5 0xf2bb000f 1487#define F0900_P2_DIS_QP_4_5 0xf2bb000f
1503 1488
1504/*P2_MODCODLSTC*/ 1489/*P2_MODCODLSTC*/
1505#define R0900_P2_MODCODLSTC 0xf2bc 1490#define R0900_P2_MODCODLSTC 0xf2bc
1506#define F0900_P2_DIS_QP_3_4 0xf2bc00f0 1491#define F0900_P2_DIS_QP_3_4 0xf2bc00f0
1507#define F0900_P2_DIS_QP_2_3 0xf2bc000f 1492#define F0900_P2_DIS_QP_2_3 0xf2bc000f
1508 1493
1509/*P2_MODCODLSTD*/ 1494/*P2_MODCODLSTD*/
1510#define R0900_P2_MODCODLSTD 0xf2bd 1495#define R0900_P2_MODCODLSTD 0xf2bd
1511#define F0900_P2_DIS_QP_3_5 0xf2bd00f0 1496#define F0900_P2_DIS_QP_3_5 0xf2bd00f0
1512#define F0900_P2_DIS_QP_1_2 0xf2bd000f 1497#define F0900_P2_DIS_QP_1_2 0xf2bd000f
1513 1498
1514/*P2_MODCODLSTE*/ 1499/*P2_MODCODLSTE*/
1515#define R0900_P2_MODCODLSTE 0xf2be 1500#define R0900_P2_MODCODLSTE 0xf2be
1516#define F0900_P2_DIS_QP_2_5 0xf2be00f0 1501#define F0900_P2_DIS_QP_2_5 0xf2be00f0
1517#define F0900_P2_DIS_QP_1_3 0xf2be000f 1502#define F0900_P2_DIS_QP_1_3 0xf2be000f
1518 1503
1519/*P2_MODCODLSTF*/ 1504/*P2_MODCODLSTF*/
1520#define R0900_P2_MODCODLSTF 0xf2bf 1505#define R0900_P2_MODCODLSTF 0xf2bf
1521#define F0900_P2_DIS_QP_1_4 0xf2bf00f0 1506#define F0900_P2_DIS_QP_1_4 0xf2bf00f0
1522#define F0900_P2_DDEMOD_SET 0xf2bf0002 1507
1523#define F0900_P2_DDEMOD_MASK 0xf2bf0001 1508/*P2_GAUSSR0*/
1509#define R0900_P2_GAUSSR0 0xf2c0
1510#define F0900_P2_EN_CCIMODE 0xf2c00080
1511#define F0900_P2_R0_GAUSSIEN 0xf2c0007f
1512
1513/*P2_CCIR0*/
1514#define R0900_P2_CCIR0 0xf2c1
1515#define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080
1516#define F0900_P2_R0_CCI 0xf2c1007f
1517
1518/*P2_CCIQUANT*/
1519#define R0900_P2_CCIQUANT 0xf2c2
1520#define F0900_P2_CCI_BETA 0xf2c200e0
1521#define F0900_P2_CCI_QUANT 0xf2c2001f
1522
1523/*P2_CCITHRES*/
1524#define R0900_P2_CCITHRES 0xf2c3
1525#define F0900_P2_CCI_THRESHOLD 0xf2c300ff
1526
1527/*P2_CCIACC*/
1528#define R0900_P2_CCIACC 0xf2c4
1529#define F0900_P2_CCI_VALUE 0xf2c400ff
1524 1530
1525/*P2_DMDRESCFG*/ 1531/*P2_DMDRESCFG*/
1526#define R0900_P2_DMDRESCFG 0xf2c6 1532#define R0900_P2_DMDRESCFG 0xf2c6
1527#define F0900_P2_DMDRES_RESET 0xf2c60080 1533#define F0900_P2_DMDRES_RESET 0xf2c60080
1528#define F0900_P2_DMDRES_NOISESQR 0xf2c60010 1534#define F0900_P2_DMDRES_STRALL 0xf2c60008
1529#define F0900_P2_DMDRES_STRALL 0xf2c60008 1535#define F0900_P2_DMDRES_NEWONLY 0xf2c60004
1530#define F0900_P2_DMDRES_NEWONLY 0xf2c60004 1536#define F0900_P2_DMDRES_NOSTORE 0xf2c60002
1531#define F0900_P2_DMDRES_NOSTORE 0xf2c60002
1532#define F0900_P2_DMDRES_AGC2MEM 0xf2c60001
1533 1537
1534/*P2_DMDRESADR*/ 1538/*P2_DMDRESADR*/
1535#define R0900_P2_DMDRESADR 0xf2c7 1539#define R0900_P2_DMDRESADR 0xf2c7
1536#define F0900_P2_SUSP_PREDCANAL 0xf2c70080 1540#define F0900_P2_DMDRES_VALIDCFR 0xf2c70040
1537#define F0900_P2_DMDRES_VALIDCFR 0xf2c70040 1541#define F0900_P2_DMDRES_MEMFULL 0xf2c70030
1538#define F0900_P2_DMDRES_MEMFULL 0xf2c70030 1542#define F0900_P2_DMDRES_RESNBR 0xf2c7000f
1539#define F0900_P2_DMDRES_RESNBR 0xf2c7000f
1540 1543
1541/*P2_DMDRESDATA7*/ 1544/*P2_DMDRESDATA7*/
1542#define R0900_P2_DMDRESDATA7 0xf2c8 1545#define R0900_P2_DMDRESDATA7 0xf2c8
1543#define F0900_P2_DMDRES_DATA7 0xf2c800ff 1546#define F0900_P2_DMDRES_DATA7 0xf2c800ff
1544 1547
1545/*P2_DMDRESDATA6*/ 1548/*P2_DMDRESDATA6*/
1546#define R0900_P2_DMDRESDATA6 0xf2c9 1549#define R0900_P2_DMDRESDATA6 0xf2c9
1547#define F0900_P2_DMDRES_DATA6 0xf2c900ff 1550#define F0900_P2_DMDRES_DATA6 0xf2c900ff
1548 1551
1549/*P2_DMDRESDATA5*/ 1552/*P2_DMDRESDATA5*/
1550#define R0900_P2_DMDRESDATA5 0xf2ca 1553#define R0900_P2_DMDRESDATA5 0xf2ca
1551#define F0900_P2_DMDRES_DATA5 0xf2ca00ff 1554#define F0900_P2_DMDRES_DATA5 0xf2ca00ff
1552 1555
1553/*P2_DMDRESDATA4*/ 1556/*P2_DMDRESDATA4*/
1554#define R0900_P2_DMDRESDATA4 0xf2cb 1557#define R0900_P2_DMDRESDATA4 0xf2cb
1555#define F0900_P2_DMDRES_DATA4 0xf2cb00ff 1558#define F0900_P2_DMDRES_DATA4 0xf2cb00ff
1556 1559
1557/*P2_DMDRESDATA3*/ 1560/*P2_DMDRESDATA3*/
1558#define R0900_P2_DMDRESDATA3 0xf2cc 1561#define R0900_P2_DMDRESDATA3 0xf2cc
1559#define F0900_P2_DMDRES_DATA3 0xf2cc00ff 1562#define F0900_P2_DMDRES_DATA3 0xf2cc00ff
1560 1563
1561/*P2_DMDRESDATA2*/ 1564/*P2_DMDRESDATA2*/
1562#define R0900_P2_DMDRESDATA2 0xf2cd 1565#define R0900_P2_DMDRESDATA2 0xf2cd
1563#define F0900_P2_DMDRES_DATA2 0xf2cd00ff 1566#define F0900_P2_DMDRES_DATA2 0xf2cd00ff
1564 1567
1565/*P2_DMDRESDATA1*/ 1568/*P2_DMDRESDATA1*/
1566#define R0900_P2_DMDRESDATA1 0xf2ce 1569#define R0900_P2_DMDRESDATA1 0xf2ce
1567#define F0900_P2_DMDRES_DATA1 0xf2ce00ff 1570#define F0900_P2_DMDRES_DATA1 0xf2ce00ff
1568 1571
1569/*P2_DMDRESDATA0*/ 1572/*P2_DMDRESDATA0*/
1570#define R0900_P2_DMDRESDATA0 0xf2cf 1573#define R0900_P2_DMDRESDATA0 0xf2cf
1571#define F0900_P2_DMDRES_DATA0 0xf2cf00ff 1574#define F0900_P2_DMDRES_DATA0 0xf2cf00ff
1572 1575
1573/*P2_FFEI1*/ 1576/*P2_FFEI1*/
1574#define R0900_P2_FFEI1 0xf2d0 1577#define R0900_P2_FFEI1 0xf2d0
1575#define F0900_P2_FFE_ACCI1 0xf2d001ff 1578#define F0900_P2_FFE_ACCI1 0xf2d001ff
1576 1579
1577/*P2_FFEQ1*/ 1580/*P2_FFEQ1*/
1578#define R0900_P2_FFEQ1 0xf2d1 1581#define R0900_P2_FFEQ1 0xf2d1
1579#define F0900_P2_FFE_ACCQ1 0xf2d101ff 1582#define F0900_P2_FFE_ACCQ1 0xf2d101ff
1580 1583
1581/*P2_FFEI2*/ 1584/*P2_FFEI2*/
1582#define R0900_P2_FFEI2 0xf2d2 1585#define R0900_P2_FFEI2 0xf2d2
1583#define F0900_P2_FFE_ACCI2 0xf2d201ff 1586#define F0900_P2_FFE_ACCI2 0xf2d201ff
1584 1587
1585/*P2_FFEQ2*/ 1588/*P2_FFEQ2*/
1586#define R0900_P2_FFEQ2 0xf2d3 1589#define R0900_P2_FFEQ2 0xf2d3
1587#define F0900_P2_FFE_ACCQ2 0xf2d301ff 1590#define F0900_P2_FFE_ACCQ2 0xf2d301ff
1588 1591
1589/*P2_FFEI3*/ 1592/*P2_FFEI3*/
1590#define R0900_P2_FFEI3 0xf2d4 1593#define R0900_P2_FFEI3 0xf2d4
1591#define F0900_P2_FFE_ACCI3 0xf2d401ff 1594#define F0900_P2_FFE_ACCI3 0xf2d401ff
1592 1595
1593/*P2_FFEQ3*/ 1596/*P2_FFEQ3*/
1594#define R0900_P2_FFEQ3 0xf2d5 1597#define R0900_P2_FFEQ3 0xf2d5
1595#define F0900_P2_FFE_ACCQ3 0xf2d501ff 1598#define F0900_P2_FFE_ACCQ3 0xf2d501ff
1596 1599
1597/*P2_FFEI4*/ 1600/*P2_FFEI4*/
1598#define R0900_P2_FFEI4 0xf2d6 1601#define R0900_P2_FFEI4 0xf2d6
1599#define F0900_P2_FFE_ACCI4 0xf2d601ff 1602#define F0900_P2_FFE_ACCI4 0xf2d601ff
1600 1603
1601/*P2_FFEQ4*/ 1604/*P2_FFEQ4*/
1602#define R0900_P2_FFEQ4 0xf2d7 1605#define R0900_P2_FFEQ4 0xf2d7
1603#define F0900_P2_FFE_ACCQ4 0xf2d701ff 1606#define F0900_P2_FFE_ACCQ4 0xf2d701ff
1604 1607
1605/*P2_FFECFG*/ 1608/*P2_FFECFG*/
1606#define R0900_P2_FFECFG 0xf2d8 1609#define R0900_P2_FFECFG 0xf2d8
1607#define F0900_P2_EQUALFFE_ON 0xf2d80040 1610#define F0900_P2_EQUALFFE_ON 0xf2d80040
1608#define F0900_P2_EQUAL_USEDSYMB 0xf2d80030 1611#define F0900_P2_MU_EQUALFFE 0xf2d80007
1609#define F0900_P2_MU_EQUALFFE 0xf2d80007
1610 1612
1611/*P2_TNRCFG*/ 1613/*P2_TNRCFG*/
1612#define R0900_P2_TNRCFG 0xf2e0 1614#define R0900_P2_TNRCFG 0xf2e0
1613#define F0900_P2_TUN_ACKFAIL 0xf2e00080 1615#define F0900_P2_TUN_ACKFAIL 0xf2e00080
1614#define F0900_P2_TUN_TYPE 0xf2e00070 1616#define F0900_P2_TUN_TYPE 0xf2e00070
1615#define F0900_P2_TUN_SECSTOP 0xf2e00008 1617#define F0900_P2_TUN_SECSTOP 0xf2e00008
1616#define F0900_P2_TUN_VCOSRCH 0xf2e00004 1618#define F0900_P2_TUN_VCOSRCH 0xf2e00004
1617#define F0900_P2_TUN_MADDRESS 0xf2e00003 1619#define F0900_P2_TUN_MADDRESS 0xf2e00003
1618 1620
1619/*P2_TNRCFG2*/ 1621/*P2_TNRCFG2*/
1620#define R0900_P2_TNRCFG2 0xf2e1 1622#define R0900_P2_TNRCFG2 0xf2e1
1621#define F0900_P2_TUN_IQSWAP 0xf2e10080 1623#define F0900_P2_TUN_IQSWAP 0xf2e10080
1622#define F0900_P2_STB6110_STEP2MHZ 0xf2e10040 1624#define F0900_P2_DIS_BWCALC 0xf2e10004
1623#define F0900_P2_STB6120_DBLI2C 0xf2e10020 1625#define F0900_P2_SHORT_WAITSTATES 0xf2e10002
1624#define F0900_P2_DIS_FCCK 0xf2e10010
1625#define F0900_P2_DIS_LPEN 0xf2e10008
1626#define F0900_P2_DIS_BWCALC 0xf2e10004
1627#define F0900_P2_SHORT_WAITSTATES 0xf2e10002
1628#define F0900_P2_DIS_2BWAGC1 0xf2e10001
1629 1626
1630/*P2_TNRXTAL*/ 1627/*P2_TNRXTAL*/
1631#define R0900_P2_TNRXTAL 0xf2e4 1628#define R0900_P2_TNRXTAL 0xf2e4
1632#define F0900_P2_TUN_MCLKDECIMAL 0xf2e400e0 1629#define F0900_P2_TUN_XTALFREQ 0xf2e4001f
1633#define F0900_P2_TUN_XTALFREQ 0xf2e4001f
1634 1630
1635/*P2_TNRSTEPS*/ 1631/*P2_TNRSTEPS*/
1636#define R0900_P2_TNRSTEPS 0xf2e7 1632#define R0900_P2_TNRSTEPS 0xf2e7
1637#define F0900_P2_TUNER_BW1P6 0xf2e70080 1633#define F0900_P2_TUNER_BW0P125 0xf2e70080
1638#define F0900_P2_BWINC_OFFSET 0xf2e70070 1634#define F0900_P2_BWINC_OFFSET 0xf2e70170
1639#define F0900_P2_SOFTSTEP_RNG 0xf2e70008 1635#define F0900_P2_SOFTSTEP_RNG 0xf2e70008
1640#define F0900_P2_TUN_BWOFFSET 0xf2e70107 1636#define F0900_P2_TUN_BWOFFSET 0xf2e70007
1641 1637
1642/*P2_TNRGAIN*/ 1638/*P2_TNRGAIN*/
1643#define R0900_P2_TNRGAIN 0xf2e8 1639#define R0900_P2_TNRGAIN 0xf2e8
1644#define F0900_P2_TUN_KDIVEN 0xf2e800c0 1640#define F0900_P2_TUN_KDIVEN 0xf2e800c0
1645#define F0900_P2_STB6X00_OCK 0xf2e80030 1641#define F0900_P2_STB6X00_OCK 0xf2e80030
1646#define F0900_P2_TUN_GAIN 0xf2e8000f 1642#define F0900_P2_TUN_GAIN 0xf2e8000f
1647 1643
1648/*P2_TNRRF1*/ 1644/*P2_TNRRF1*/
1649#define R0900_P2_TNRRF1 0xf2e9 1645#define R0900_P2_TNRRF1 0xf2e9
1650#define F0900_P2_TUN_RFFREQ2 0xf2e900ff 1646#define F0900_P2_TUN_RFFREQ2 0xf2e900ff
1651 1647
1652/*P2_TNRRF0*/ 1648/*P2_TNRRF0*/
1653#define R0900_P2_TNRRF0 0xf2ea 1649#define R0900_P2_TNRRF0 0xf2ea
1654#define F0900_P2_TUN_RFFREQ1 0xf2ea00ff 1650#define F0900_P2_TUN_RFFREQ1 0xf2ea00ff
1655 1651
1656/*P2_TNRBW*/ 1652/*P2_TNRBW*/
1657#define R0900_P2_TNRBW 0xf2eb 1653#define R0900_P2_TNRBW 0xf2eb
1658#define F0900_P2_TUN_RFFREQ0 0xf2eb00c0 1654#define F0900_P2_TUN_RFFREQ0 0xf2eb00c0
1659#define F0900_P2_TUN_BW 0xf2eb003f 1655#define F0900_P2_TUN_BW 0xf2eb003f
1660 1656
1661/*P2_TNRADJ*/ 1657/*P2_TNRADJ*/
1662#define R0900_P2_TNRADJ 0xf2ec 1658#define R0900_P2_TNRADJ 0xf2ec
1663#define F0900_P2_STB61X0_RCLK 0xf2ec0080 1659#define F0900_P2_STB61X0_CALTIME 0xf2ec0040
1664#define F0900_P2_STB61X0_CALTIME 0xf2ec0040
1665#define F0900_P2_STB6X00_DLB 0xf2ec0038
1666#define F0900_P2_STB6000_FCL 0xf2ec0007
1667 1660
1668/*P2_TNRCTL2*/ 1661/*P2_TNRCTL2*/
1669#define R0900_P2_TNRCTL2 0xf2ed 1662#define R0900_P2_TNRCTL2 0xf2ed
1670#define F0900_P2_STB61X0_LCP1_RCCKOFF 0xf2ed0080 1663#define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080
1671#define F0900_P2_STB61X0_LCP0 0xf2ed0040 1664#define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040
1672#define F0900_P2_STB61X0_XTOUT_RFOUTS 0xf2ed0020 1665#define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020
1673#define F0900_P2_STB61X0_XTON_MCKDV 0xf2ed0010 1666#define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010
1674#define F0900_P2_STB61X0_CALOFF_DCOFF 0xf2ed0008 1667#define F0900_P2_STB61X0_CALOFF 0xf2ed0008
1675#define F0900_P2_STB6110_LPT 0xf2ed0004 1668#define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004
1676#define F0900_P2_STB6110_RX 0xf2ed0002 1669#define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002
1677#define F0900_P2_STB6110_SYN 0xf2ed0001 1670#define F0900_P2_STB6XX0_SYN 0xf2ed0001
1678 1671
1679/*P2_TNRCFG3*/ 1672/*P2_TNRCFG3*/
1680#define R0900_P2_TNRCFG3 0xf2ee 1673#define R0900_P2_TNRCFG3 0xf2ee
1681#define F0900_P2_STB6120_DISCTRL1 0xf2ee0080 1674#define F0900_P2_TUN_PLLFREQ 0xf2ee001c
1682#define F0900_P2_STB6120_INVORDER 0xf2ee0040 1675#define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003
1683#define F0900_P2_STB6120_ENCTRL6 0xf2ee0020
1684#define F0900_P2_TUN_PLLFREQ 0xf2ee001c
1685#define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003
1686 1676
1687/*P2_TNRLAUNCH*/ 1677/*P2_TNRLAUNCH*/
1688#define R0900_P2_TNRLAUNCH 0xf2f0 1678#define R0900_P2_TNRLAUNCH 0xf2f0
1689 1679
1690/*P2_TNRLD*/ 1680/*P2_TNRLD*/
1691#define R0900_P2_TNRLD 0xf2f0 1681#define R0900_P2_TNRLD 0xf2f0
1692#define F0900_P2_TUNLD_VCOING 0xf2f00080 1682#define F0900_P2_TUNLD_VCOING 0xf2f00080
1693#define F0900_P2_TUN_REG1FAIL 0xf2f00040 1683#define F0900_P2_TUN_REG1FAIL 0xf2f00040
1694#define F0900_P2_TUN_REG2FAIL 0xf2f00020 1684#define F0900_P2_TUN_REG2FAIL 0xf2f00020
1695#define F0900_P2_TUN_REG3FAIL 0xf2f00010 1685#define F0900_P2_TUN_REG3FAIL 0xf2f00010
1696#define F0900_P2_TUN_REG4FAIL 0xf2f00008 1686#define F0900_P2_TUN_REG4FAIL 0xf2f00008
1697#define F0900_P2_TUN_REG5FAIL 0xf2f00004 1687#define F0900_P2_TUN_REG5FAIL 0xf2f00004
1698#define F0900_P2_TUN_BWING 0xf2f00002 1688#define F0900_P2_TUN_BWING 0xf2f00002
1699#define F0900_P2_TUN_LOCKED 0xf2f00001 1689#define F0900_P2_TUN_LOCKED 0xf2f00001
1700 1690
1701/*P2_TNROBSL*/ 1691/*P2_TNROBSL*/
1702#define R0900_P2_TNROBSL 0xf2f6 1692#define R0900_P2_TNROBSL 0xf2f6
1703#define F0900_P2_TUN_I2CABORTED 0xf2f60080 1693#define F0900_P2_TUN_I2CABORTED 0xf2f60080
1704#define F0900_P2_TUN_LPEN 0xf2f60040 1694#define F0900_P2_TUN_LPEN 0xf2f60040
1705#define F0900_P2_TUN_FCCK 0xf2f60020 1695#define F0900_P2_TUN_FCCK 0xf2f60020
1706#define F0900_P2_TUN_I2CLOCKED 0xf2f60010 1696#define F0900_P2_TUN_I2CLOCKED 0xf2f60010
1707#define F0900_P2_TUN_PROGDONE 0xf2f6000c 1697#define F0900_P2_TUN_PROGDONE 0xf2f6000c
1708#define F0900_P2_TUN_RFRESTE1 0xf2f60003 1698#define F0900_P2_TUN_RFRESTE1 0xf2f60003
1709 1699
1710/*P2_TNRRESTE*/ 1700/*P2_TNRRESTE*/
1711#define R0900_P2_TNRRESTE 0xf2f7 1701#define R0900_P2_TNRRESTE 0xf2f7
1712#define F0900_P2_TUN_RFRESTE0 0xf2f700ff 1702#define F0900_P2_TUN_RFRESTE0 0xf2f700ff
1713 1703
1714/*P2_SMAPCOEF7*/ 1704/*P2_SMAPCOEF7*/
1715#define R0900_P2_SMAPCOEF7 0xf300 1705#define R0900_P2_SMAPCOEF7 0xf300
1716#define F0900_P2_DIS_QSCALE 0xf3000080 1706#define F0900_P2_DIS_QSCALE 0xf3000080
1717#define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f 1707#define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f
1718 1708
1719/*P2_SMAPCOEF6*/ 1709/*P2_SMAPCOEF6*/
1720#define R0900_P2_SMAPCOEF6 0xf301 1710#define R0900_P2_SMAPCOEF6 0xf301
1721#define F0900_P2_DIS_NEWSCALE 0xf3010008 1711#define F0900_P2_ADJ_8PSKLLR1 0xf3010004
1722#define F0900_P2_ADJ_8PSKLLR1 0xf3010004 1712#define F0900_P2_OLD_8PSKLLR1 0xf3010002
1723#define F0900_P2_OLD_8PSKLLR1 0xf3010002 1713#define F0900_P2_DIS_AB8PSK 0xf3010001
1724#define F0900_P2_DIS_AB8PSK 0xf3010001
1725 1714
1726/*P2_SMAPCOEF5*/ 1715/*P2_SMAPCOEF5*/
1727#define R0900_P2_SMAPCOEF5 0xf302 1716#define R0900_P2_SMAPCOEF5 0xf302
1728#define F0900_P2_DIS_8SCALE 0xf3020080 1717#define F0900_P2_DIS_8SCALE 0xf3020080
1729#define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f 1718#define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f
1719
1720/*P2_NCO2MAX1*/
1721#define R0900_P2_NCO2MAX1 0xf314
1722#define F0900_P2_TETA2_MAXVABS1 0xf31400ff
1723
1724/*P2_NCO2MAX0*/
1725#define R0900_P2_NCO2MAX0 0xf315
1726#define F0900_P2_TETA2_MAXVABS0 0xf31500ff
1727
1728/*P2_NCO2FR1*/
1729#define R0900_P2_NCO2FR1 0xf316
1730#define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff
1731
1732/*P2_NCO2FR0*/
1733#define R0900_P2_NCO2FR0 0xf317
1734#define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff
1735
1736/*P2_CFR2AVRGE1*/
1737#define R0900_P2_CFR2AVRGE1 0xf318
1738#define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff
1739
1740/*P2_CFR2AVRGE0*/
1741#define R0900_P2_CFR2AVRGE0 0xf319
1742#define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff
1730 1743
1731/*P2_DMDPLHSTAT*/ 1744/*P2_DMDPLHSTAT*/
1732#define R0900_P2_DMDPLHSTAT 0xf320 1745#define R0900_P2_DMDPLHSTAT 0xf320
1733#define F0900_P2_PLH_STATISTIC 0xf32000ff 1746#define F0900_P2_PLH_STATISTIC 0xf32000ff
1734 1747
1735/*P2_LOCKTIME3*/ 1748/*P2_LOCKTIME3*/
1736#define R0900_P2_LOCKTIME3 0xf322 1749#define R0900_P2_LOCKTIME3 0xf322
1737#define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff 1750#define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff
1738 1751
1739/*P2_LOCKTIME2*/ 1752/*P2_LOCKTIME2*/
1740#define R0900_P2_LOCKTIME2 0xf323 1753#define R0900_P2_LOCKTIME2 0xf323
1741#define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff 1754#define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff
1742 1755
1743/*P2_LOCKTIME1*/ 1756/*P2_LOCKTIME1*/
1744#define R0900_P2_LOCKTIME1 0xf324 1757#define R0900_P2_LOCKTIME1 0xf324
1745#define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff 1758#define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff
1746 1759
1747/*P2_LOCKTIME0*/ 1760/*P2_LOCKTIME0*/
1748#define R0900_P2_LOCKTIME0 0xf325 1761#define R0900_P2_LOCKTIME0 0xf325
1749#define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff 1762#define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff
1750 1763
1751/*P2_VITSCALE*/ 1764/*P2_VITSCALE*/
1752#define R0900_P2_VITSCALE 0xf332 1765#define R0900_P2_VITSCALE 0xf332
1753#define F0900_P2_NVTH_NOSRANGE 0xf3320080 1766#define F0900_P2_NVTH_NOSRANGE 0xf3320080
1754#define F0900_P2_VERROR_MAXMODE 0xf3320040 1767#define F0900_P2_VERROR_MAXMODE 0xf3320040
1755#define F0900_P2_KDIV_MODE 0xf3320030 1768#define F0900_P2_NSLOWSN_LOCKED 0xf3320008
1756#define F0900_P2_NSLOWSN_LOCKED 0xf3320008 1769#define F0900_P2_DIS_RSFLOCK 0xf3320002
1757#define F0900_P2_DELOCK_PRFLOSS 0xf3320004
1758#define F0900_P2_DIS_RSFLOCK 0xf3320002
1759 1770
1760/*P2_FECM*/ 1771/*P2_FECM*/
1761#define R0900_P2_FECM 0xf333 1772#define R0900_P2_FECM 0xf333
1762#define F0900_P2_DSS_DVB 0xf3330080 1773#define F0900_P2_DSS_DVB 0xf3330080
1763#define F0900_P2_DEMOD_BYPASS 0xf3330040 1774#define F0900_P2_DSS_SRCH 0xf3330010
1764#define F0900_P2_CMP_SLOWMODE 0xf3330020 1775#define F0900_P2_SYNCVIT 0xf3330002
1765#define F0900_P2_DSS_SRCH 0xf3330010 1776#define F0900_P2_IQINV 0xf3330001
1766#define F0900_P2_DIFF_MODEVIT 0xf3330004
1767#define F0900_P2_SYNCVIT 0xf3330002
1768#define F0900_P2_IQINV 0xf3330001
1769 1777
1770/*P2_VTH12*/ 1778/*P2_VTH12*/
1771#define R0900_P2_VTH12 0xf334 1779#define R0900_P2_VTH12 0xf334
1772#define F0900_P2_VTH12 0xf33400ff 1780#define F0900_P2_VTH12 0xf33400ff
1773 1781
1774/*P2_VTH23*/ 1782/*P2_VTH23*/
1775#define R0900_P2_VTH23 0xf335 1783#define R0900_P2_VTH23 0xf335
1776#define F0900_P2_VTH23 0xf33500ff 1784#define F0900_P2_VTH23 0xf33500ff
1777 1785
1778/*P2_VTH34*/ 1786/*P2_VTH34*/
1779#define R0900_P2_VTH34 0xf336 1787#define R0900_P2_VTH34 0xf336
1780#define F0900_P2_VTH34 0xf33600ff 1788#define F0900_P2_VTH34 0xf33600ff
1781 1789
1782/*P2_VTH56*/ 1790/*P2_VTH56*/
1783#define R0900_P2_VTH56 0xf337 1791#define R0900_P2_VTH56 0xf337
1784#define F0900_P2_VTH56 0xf33700ff 1792#define F0900_P2_VTH56 0xf33700ff
1785 1793
1786/*P2_VTH67*/ 1794/*P2_VTH67*/
1787#define R0900_P2_VTH67 0xf338 1795#define R0900_P2_VTH67 0xf338
1788#define F0900_P2_VTH67 0xf33800ff 1796#define F0900_P2_VTH67 0xf33800ff
1789 1797
1790/*P2_VTH78*/ 1798/*P2_VTH78*/
1791#define R0900_P2_VTH78 0xf339 1799#define R0900_P2_VTH78 0xf339
1792#define F0900_P2_VTH78 0xf33900ff 1800#define F0900_P2_VTH78 0xf33900ff
1793 1801
1794/*P2_VITCURPUN*/ 1802/*P2_VITCURPUN*/
1795#define R0900_P2_VITCURPUN 0xf33a 1803#define R0900_P2_VITCURPUN 0xf33a
1796#define F0900_P2_VIT_MAPPING 0xf33a00e0 1804#define F0900_P2_VIT_CURPUN 0xf33a001f
1797#define F0900_P2_VIT_CURPUN 0xf33a001f
1798 1805
1799/*P2_VERROR*/ 1806/*P2_VERROR*/
1800#define R0900_P2_VERROR 0xf33b 1807#define R0900_P2_VERROR 0xf33b
1801#define F0900_P2_REGERR_VIT 0xf33b00ff 1808#define F0900_P2_REGERR_VIT 0xf33b00ff
1802 1809
1803/*P2_PRVIT*/ 1810/*P2_PRVIT*/
1804#define R0900_P2_PRVIT 0xf33c 1811#define R0900_P2_PRVIT 0xf33c
1805#define F0900_P2_DIS_VTHLOCK 0xf33c0040 1812#define F0900_P2_DIS_VTHLOCK 0xf33c0040
1806#define F0900_P2_E7_8VIT 0xf33c0020 1813#define F0900_P2_E7_8VIT 0xf33c0020
1807#define F0900_P2_E6_7VIT 0xf33c0010 1814#define F0900_P2_E6_7VIT 0xf33c0010
1808#define F0900_P2_E5_6VIT 0xf33c0008 1815#define F0900_P2_E5_6VIT 0xf33c0008
1809#define F0900_P2_E3_4VIT 0xf33c0004 1816#define F0900_P2_E3_4VIT 0xf33c0004
1810#define F0900_P2_E2_3VIT 0xf33c0002 1817#define F0900_P2_E2_3VIT 0xf33c0002
1811#define F0900_P2_E1_2VIT 0xf33c0001 1818#define F0900_P2_E1_2VIT 0xf33c0001
1812 1819
1813/*P2_VAVSRVIT*/ 1820/*P2_VAVSRVIT*/
1814#define R0900_P2_VAVSRVIT 0xf33d 1821#define R0900_P2_VAVSRVIT 0xf33d
1815#define F0900_P2_AMVIT 0xf33d0080 1822#define F0900_P2_AMVIT 0xf33d0080
1816#define F0900_P2_FROZENVIT 0xf33d0040 1823#define F0900_P2_FROZENVIT 0xf33d0040
1817#define F0900_P2_SNVIT 0xf33d0030 1824#define F0900_P2_SNVIT 0xf33d0030
1818#define F0900_P2_TOVVIT 0xf33d000c 1825#define F0900_P2_TOVVIT 0xf33d000c
1819#define F0900_P2_HYPVIT 0xf33d0003 1826#define F0900_P2_HYPVIT 0xf33d0003
1820 1827
1821/*P2_VSTATUSVIT*/ 1828/*P2_VSTATUSVIT*/
1822#define R0900_P2_VSTATUSVIT 0xf33e 1829#define R0900_P2_VSTATUSVIT 0xf33e
1823#define F0900_P2_VITERBI_ON 0xf33e0080 1830#define F0900_P2_PRFVIT 0xf33e0010
1824#define F0900_P2_END_LOOPVIT 0xf33e0040 1831#define F0900_P2_LOCKEDVIT 0xf33e0008
1825#define F0900_P2_VITERBI_DEPRF 0xf33e0020
1826#define F0900_P2_PRFVIT 0xf33e0010
1827#define F0900_P2_LOCKEDVIT 0xf33e0008
1828#define F0900_P2_VITERBI_DELOCK 0xf33e0004
1829#define F0900_P2_VIT_DEMODSEL 0xf33e0002
1830#define F0900_P2_VITERBI_COMPOUT 0xf33e0001
1831 1832
1832/*P2_VTHINUSE*/ 1833/*P2_VTHINUSE*/
1833#define R0900_P2_VTHINUSE 0xf33f 1834#define R0900_P2_VTHINUSE 0xf33f
1834#define F0900_P2_VIT_INUSE 0xf33f00ff 1835#define F0900_P2_VIT_INUSE 0xf33f00ff
1835 1836
1836/*P2_KDIV12*/ 1837/*P2_KDIV12*/
1837#define R0900_P2_KDIV12 0xf340 1838#define R0900_P2_KDIV12 0xf340
1838#define F0900_P2_KDIV12_MANUAL 0xf3400080 1839#define F0900_P2_K_DIVIDER_12 0xf340007f
1839#define F0900_P2_K_DIVIDER_12 0xf340007f
1840 1840
1841/*P2_KDIV23*/ 1841/*P2_KDIV23*/
1842#define R0900_P2_KDIV23 0xf341 1842#define R0900_P2_KDIV23 0xf341
1843#define F0900_P2_KDIV23_MANUAL 0xf3410080 1843#define F0900_P2_K_DIVIDER_23 0xf341007f
1844#define F0900_P2_K_DIVIDER_23 0xf341007f
1845 1844
1846/*P2_KDIV34*/ 1845/*P2_KDIV34*/
1847#define R0900_P2_KDIV34 0xf342 1846#define R0900_P2_KDIV34 0xf342
1848#define F0900_P2_KDIV34_MANUAL 0xf3420080 1847#define F0900_P2_K_DIVIDER_34 0xf342007f
1849#define F0900_P2_K_DIVIDER_34 0xf342007f
1850 1848
1851/*P2_KDIV56*/ 1849/*P2_KDIV56*/
1852#define R0900_P2_KDIV56 0xf343 1850#define R0900_P2_KDIV56 0xf343
1853#define F0900_P2_KDIV56_MANUAL 0xf3430080 1851#define F0900_P2_K_DIVIDER_56 0xf343007f
1854#define F0900_P2_K_DIVIDER_56 0xf343007f
1855 1852
1856/*P2_KDIV67*/ 1853/*P2_KDIV67*/
1857#define R0900_P2_KDIV67 0xf344 1854#define R0900_P2_KDIV67 0xf344
1858#define F0900_P2_KDIV67_MANUAL 0xf3440080 1855#define F0900_P2_K_DIVIDER_67 0xf344007f
1859#define F0900_P2_K_DIVIDER_67 0xf344007f
1860 1856
1861/*P2_KDIV78*/ 1857/*P2_KDIV78*/
1862#define R0900_P2_KDIV78 0xf345 1858#define R0900_P2_KDIV78 0xf345
1863#define F0900_P2_KDIV78_MANUAL 0xf3450080 1859#define F0900_P2_K_DIVIDER_78 0xf345007f
1864#define F0900_P2_K_DIVIDER_78 0xf345007f
1865 1860
1866/*P2_PDELCTRL1*/ 1861/*P2_PDELCTRL1*/
1867#define R0900_P2_PDELCTRL1 0xf350 1862#define R0900_P2_PDELCTRL1 0xf350
1868#define F0900_P2_INV_MISMASK 0xf3500080 1863#define F0900_P2_INV_MISMASK 0xf3500080
1869#define F0900_P2_FORCE_ACCEPTED 0xf3500040 1864#define F0900_P2_FILTER_EN 0xf3500020
1870#define F0900_P2_FILTER_EN 0xf3500020 1865#define F0900_P2_EN_MIS00 0xf3500002
1871#define F0900_P2_FORCE_PKTDELINUSE 0xf3500010 1866#define F0900_P2_ALGOSWRST 0xf3500001
1872#define F0900_P2_HYSTEN 0xf3500008
1873#define F0900_P2_HYSTSWRST 0xf3500004
1874#define F0900_P2_EN_MIS00 0xf3500002
1875#define F0900_P2_ALGOSWRST 0xf3500001
1876 1867
1877/*P2_PDELCTRL2*/ 1868/*P2_PDELCTRL2*/
1878#define R0900_P2_PDELCTRL2 0xf351 1869#define R0900_P2_PDELCTRL2 0xf351
1879#define F0900_P2_FORCE_CONTINUOUS 0xf3510080 1870#define F0900_P2_RESET_UPKO_COUNT 0xf3510040
1880#define F0900_P2_RESET_UPKO_COUNT 0xf3510040 1871#define F0900_P2_FRAME_MODE 0xf3510002
1881#define F0900_P2_USER_PKTDELIN_NB 0xf3510020 1872#define F0900_P2_NOBCHERRFLG_USE 0xf3510001
1882#define F0900_P2_FORCE_LOCKED 0xf3510010
1883#define F0900_P2_DATA_UNBBSCRAM 0xf3510008
1884#define F0900_P2_FORCE_LONGPKT 0xf3510004
1885#define F0900_P2_FRAME_MODE 0xf3510002
1886 1873
1887/*P2_HYSTTHRESH*/ 1874/*P2_HYSTTHRESH*/
1888#define R0900_P2_HYSTTHRESH 0xf354 1875#define R0900_P2_HYSTTHRESH 0xf354
1889#define F0900_P2_UNLCK_THRESH 0xf35400f0 1876#define F0900_P2_UNLCK_THRESH 0xf35400f0
1890#define F0900_P2_DELIN_LCK_THRESH 0xf354000f 1877#define F0900_P2_DELIN_LCK_THRESH 0xf354000f
1891 1878
1892/*P2_ISIENTRY*/ 1879/*P2_ISIENTRY*/
1893#define R0900_P2_ISIENTRY 0xf35e 1880#define R0900_P2_ISIENTRY 0xf35e
1894#define F0900_P2_ISI_ENTRY 0xf35e00ff 1881#define F0900_P2_ISI_ENTRY 0xf35e00ff
1895 1882
1896/*P2_ISIBITENA*/ 1883/*P2_ISIBITENA*/
1897#define R0900_P2_ISIBITENA 0xf35f 1884#define R0900_P2_ISIBITENA 0xf35f
1898#define F0900_P2_ISI_BIT_EN 0xf35f00ff 1885#define F0900_P2_ISI_BIT_EN 0xf35f00ff
1899 1886
1900/*P2_MATSTR1*/ 1887/*P2_MATSTR1*/
1901#define R0900_P2_MATSTR1 0xf360 1888#define R0900_P2_MATSTR1 0xf360
1902#define F0900_P2_MATYPE_CURRENT1 0xf36000ff 1889#define F0900_P2_MATYPE_CURRENT1 0xf36000ff
1903 1890
1904/*P2_MATSTR0*/ 1891/*P2_MATSTR0*/
1905#define R0900_P2_MATSTR0 0xf361 1892#define R0900_P2_MATSTR0 0xf361
1906#define F0900_P2_MATYPE_CURRENT0 0xf36100ff 1893#define F0900_P2_MATYPE_CURRENT0 0xf36100ff
1907 1894
1908/*P2_UPLSTR1*/ 1895/*P2_UPLSTR1*/
1909#define R0900_P2_UPLSTR1 0xf362 1896#define R0900_P2_UPLSTR1 0xf362
1910#define F0900_P2_UPL_CURRENT1 0xf36200ff 1897#define F0900_P2_UPL_CURRENT1 0xf36200ff
1911 1898
1912/*P2_UPLSTR0*/ 1899/*P2_UPLSTR0*/
1913#define R0900_P2_UPLSTR0 0xf363 1900#define R0900_P2_UPLSTR0 0xf363
1914#define F0900_P2_UPL_CURRENT0 0xf36300ff 1901#define F0900_P2_UPL_CURRENT0 0xf36300ff
1915 1902
1916/*P2_DFLSTR1*/ 1903/*P2_DFLSTR1*/
1917#define R0900_P2_DFLSTR1 0xf364 1904#define R0900_P2_DFLSTR1 0xf364
1918#define F0900_P2_DFL_CURRENT1 0xf36400ff 1905#define F0900_P2_DFL_CURRENT1 0xf36400ff
1919 1906
1920/*P2_DFLSTR0*/ 1907/*P2_DFLSTR0*/
1921#define R0900_P2_DFLSTR0 0xf365 1908#define R0900_P2_DFLSTR0 0xf365
1922#define F0900_P2_DFL_CURRENT0 0xf36500ff 1909#define F0900_P2_DFL_CURRENT0 0xf36500ff
1923 1910
1924/*P2_SYNCSTR*/ 1911/*P2_SYNCSTR*/
1925#define R0900_P2_SYNCSTR 0xf366 1912#define R0900_P2_SYNCSTR 0xf366
1926#define F0900_P2_SYNC_CURRENT 0xf36600ff 1913#define F0900_P2_SYNC_CURRENT 0xf36600ff
1927 1914
1928/*P2_SYNCDSTR1*/ 1915/*P2_SYNCDSTR1*/
1929#define R0900_P2_SYNCDSTR1 0xf367 1916#define R0900_P2_SYNCDSTR1 0xf367
1930#define F0900_P2_SYNCD_CURRENT1 0xf36700ff 1917#define F0900_P2_SYNCD_CURRENT1 0xf36700ff
1931 1918
1932/*P2_SYNCDSTR0*/ 1919/*P2_SYNCDSTR0*/
1933#define R0900_P2_SYNCDSTR0 0xf368 1920#define R0900_P2_SYNCDSTR0 0xf368
1934#define F0900_P2_SYNCD_CURRENT0 0xf36800ff 1921#define F0900_P2_SYNCD_CURRENT0 0xf36800ff
1935 1922
1936/*P2_PDELSTATUS1*/ 1923/*P2_PDELSTATUS1*/
1937#define R0900_P2_PDELSTATUS1 0xf369 1924#define R0900_P2_PDELSTATUS1 0xf369
1938#define F0900_P2_PKTDELIN_DELOCK 0xf3690080 1925#define F0900_P2_PKTDELIN_DELOCK 0xf3690080
1939#define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040 1926#define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040
1940#define F0900_P2_CONTINUOUS_STREAM 0xf3690020 1927#define F0900_P2_CONTINUOUS_STREAM 0xf3690020
1941#define F0900_P2_UNACCEPTED_STREAM 0xf3690010 1928#define F0900_P2_UNACCEPTED_STREAM 0xf3690010
1942#define F0900_P2_BCH_ERROR_FLAG 0xf3690008 1929#define F0900_P2_BCH_ERROR_FLAG 0xf3690008
1943#define F0900_P2_BBHCRCKO 0xf3690004 1930#define F0900_P2_PKTDELIN_LOCK 0xf3690002
1944#define F0900_P2_PKTDELIN_LOCK 0xf3690002 1931#define F0900_P2_FIRST_LOCK 0xf3690001
1945#define F0900_P2_FIRST_LOCK 0xf3690001
1946 1932
1947/*P2_PDELSTATUS2*/ 1933/*P2_PDELSTATUS2*/
1948#define R0900_P2_PDELSTATUS2 0xf36a 1934#define R0900_P2_PDELSTATUS2 0xf36a
1949#define F0900_P2_PKTDEL_DEMODSEL 0xf36a0080 1935#define F0900_P2_FRAME_MODCOD 0xf36a007c
1950#define F0900_P2_FRAME_MODCOD 0xf36a007c 1936#define F0900_P2_FRAME_TYPE 0xf36a0003
1951#define F0900_P2_FRAME_TYPE 0xf36a0003
1952 1937
1953/*P2_BBFCRCKO1*/ 1938/*P2_BBFCRCKO1*/
1954#define R0900_P2_BBFCRCKO1 0xf36b 1939#define R0900_P2_BBFCRCKO1 0xf36b
1955#define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff 1940#define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff
1956 1941
1957/*P2_BBFCRCKO0*/ 1942/*P2_BBFCRCKO0*/
1958#define R0900_P2_BBFCRCKO0 0xf36c 1943#define R0900_P2_BBFCRCKO0 0xf36c
1959#define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff 1944#define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff
1960 1945
1961/*P2_UPCRCKO1*/ 1946/*P2_UPCRCKO1*/
1962#define R0900_P2_UPCRCKO1 0xf36d 1947#define R0900_P2_UPCRCKO1 0xf36d
1963#define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff 1948#define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff
1964 1949
1965/*P2_UPCRCKO0*/ 1950/*P2_UPCRCKO0*/
1966#define R0900_P2_UPCRCKO0 0xf36e 1951#define R0900_P2_UPCRCKO0 0xf36e
1967#define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff 1952#define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff
1953
1954/*P2_PDELCTRL3*/
1955#define R0900_P2_PDELCTRL3 0xf36f
1956#define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080
1957#define F0900_P2_NOFIFO_BCHERR 0xf36f0020
1968 1958
1969/*P2_TSSTATEM*/ 1959/*P2_TSSTATEM*/
1970#define R0900_P2_TSSTATEM 0xf370 1960#define R0900_P2_TSSTATEM 0xf370
1971#define F0900_P2_TSDIL_ON 0xf3700080 1961#define F0900_P2_TSDIL_ON 0xf3700080
1972#define F0900_P2_TSSKIPRS_ON 0xf3700040 1962#define F0900_P2_TSRS_ON 0xf3700020
1973#define F0900_P2_TSRS_ON 0xf3700020 1963#define F0900_P2_TSDESCRAMB_ON 0xf3700010
1974#define F0900_P2_TSDESCRAMB_ON 0xf3700010 1964#define F0900_P2_TSFRAME_MODE 0xf3700008
1975#define F0900_P2_TSFRAME_MODE 0xf3700008 1965#define F0900_P2_TS_DISABLE 0xf3700004
1976#define F0900_P2_TS_DISABLE 0xf3700004 1966#define F0900_P2_TSOUT_NOSYNC 0xf3700001
1977#define F0900_P2_TSACM_MODE 0xf3700002
1978#define F0900_P2_TSOUT_NOSYNC 0xf3700001
1979 1967
1980/*P2_TSCFGH*/ 1968/*P2_TSCFGH*/
1981#define R0900_P2_TSCFGH 0xf372 1969#define R0900_P2_TSCFGH 0xf372
1982#define F0900_P2_TSFIFO_DVBCI 0xf3720080 1970#define F0900_P2_TSFIFO_DVBCI 0xf3720080
1983#define F0900_P2_TSFIFO_SERIAL 0xf3720040 1971#define F0900_P2_TSFIFO_SERIAL 0xf3720040
1984#define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020 1972#define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020
1985#define F0900_P2_TSFIFO_DUTY50 0xf3720010 1973#define F0900_P2_TSFIFO_DUTY50 0xf3720010
1986#define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008 1974#define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008
1987#define F0900_P2_TSFIFO_ERRMODE 0xf3720006 1975#define F0900_P2_TSFIFO_ERRMODE 0xf3720006
1988#define F0900_P2_RST_HWARE 0xf3720001 1976#define F0900_P2_RST_HWARE 0xf3720001
1989 1977
1990/*P2_TSCFGM*/ 1978/*P2_TSCFGM*/
1991#define R0900_P2_TSCFGM 0xf373 1979#define R0900_P2_TSCFGM 0xf373
1992#define F0900_P2_TSFIFO_MANSPEED 0xf37300c0 1980#define F0900_P2_TSFIFO_MANSPEED 0xf37300c0
1993#define F0900_P2_TSFIFO_PERMDATA 0xf3730020 1981#define F0900_P2_TSFIFO_PERMDATA 0xf3730020
1994#define F0900_P2_TSFIFO_NONEWSGNL 0xf3730010 1982#define F0900_P2_TSFIFO_DPUNACT 0xf3730002
1995#define F0900_P2_TSFIFO_BITSPEED 0xf3730008 1983#define F0900_P2_TSFIFO_INVDATA 0xf3730001
1996#define F0900_P2_NPD_SPECDVBS2 0xf3730004
1997#define F0900_P2_TSFIFO_STOPCKDIS 0xf3730002
1998#define F0900_P2_TSFIFO_INVDATA 0xf3730001
1999 1984
2000/*P2_TSCFGL*/ 1985/*P2_TSCFGL*/
2001#define R0900_P2_TSCFGL 0xf374 1986#define R0900_P2_TSCFGL 0xf374
2002#define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 1987#define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0
2003#define F0900_P2_BCHERROR_MODE 0xf3740030 1988#define F0900_P2_BCHERROR_MODE 0xf3740030
2004#define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008 1989#define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008
2005#define F0900_P2_TSFIFO_EMBINDVB 0xf3740004 1990#define F0900_P2_TSFIFO_EMBINDVB 0xf3740004
2006#define F0900_P2_TSFIFO_DPUNACT 0xf3740002 1991#define F0900_P2_TSFIFO_BITSPEED 0xf3740003
2007#define F0900_P2_TSFIFO_NPDOFF 0xf3740001
2008 1992
2009/*P2_TSINSDELH*/ 1993/*P2_TSINSDELH*/
2010#define R0900_P2_TSINSDELH 0xf376 1994#define R0900_P2_TSINSDELH 0xf376
2011#define F0900_P2_TSDEL_SYNCBYTE 0xf3760080 1995#define F0900_P2_TSDEL_SYNCBYTE 0xf3760080
2012#define F0900_P2_TSDEL_XXHEADER 0xf3760040 1996#define F0900_P2_TSDEL_XXHEADER 0xf3760040
2013#define F0900_P2_TSDEL_BBHEADER 0xf3760020 1997#define F0900_P2_TSDEL_BBHEADER 0xf3760020
2014#define F0900_P2_TSDEL_DATAFIELD 0xf3760010 1998#define F0900_P2_TSDEL_DATAFIELD 0xf3760010
2015#define F0900_P2_TSINSDEL_ISCR 0xf3760008 1999#define F0900_P2_TSINSDEL_ISCR 0xf3760008
2016#define F0900_P2_TSINSDEL_NPD 0xf3760004 2000#define F0900_P2_TSINSDEL_NPD 0xf3760004
2017#define F0900_P2_TSINSDEL_RSPARITY 0xf3760002 2001#define F0900_P2_TSINSDEL_RSPARITY 0xf3760002
2018#define F0900_P2_TSINSDEL_CRC8 0xf3760001 2002#define F0900_P2_TSINSDEL_CRC8 0xf3760001
2003
2004/*P2_TSDIVN*/
2005#define R0900_P2_TSDIVN 0xf379
2006#define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0
2007
2008/*P2_TSCFG4*/
2009#define R0900_P2_TSCFG4 0xf37a
2010#define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0
2019 2011
2020/*P2_TSSPEED*/ 2012/*P2_TSSPEED*/
2021#define R0900_P2_TSSPEED 0xf380 2013#define R0900_P2_TSSPEED 0xf380
2022#define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff 2014#define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff
2023 2015
2024/*P2_TSSTATUS*/ 2016/*P2_TSSTATUS*/
2025#define R0900_P2_TSSTATUS 0xf381 2017#define R0900_P2_TSSTATUS 0xf381
2026#define F0900_P2_TSFIFO_LINEOK 0xf3810080 2018#define F0900_P2_TSFIFO_LINEOK 0xf3810080
2027#define F0900_P2_TSFIFO_ERROR 0xf3810040 2019#define F0900_P2_TSFIFO_ERROR 0xf3810040
2028#define F0900_P2_TSFIFO_DATA7 0xf3810020 2020#define F0900_P2_DIL_READY 0xf3810001
2029#define F0900_P2_TSFIFO_NOSYNC 0xf3810010
2030#define F0900_P2_ISCR_INITIALIZED 0xf3810008
2031#define F0900_P2_ISCR_UPDATED 0xf3810004
2032#define F0900_P2_SOFFIFO_UNREGUL 0xf3810002
2033#define F0900_P2_DIL_READY 0xf3810001
2034 2021
2035/*P2_TSSTATUS2*/ 2022/*P2_TSSTATUS2*/
2036#define R0900_P2_TSSTATUS2 0xf382 2023#define R0900_P2_TSSTATUS2 0xf382
2037#define F0900_P2_TSFIFO_DEMODSEL 0xf3820080 2024#define F0900_P2_TSFIFO_DEMODSEL 0xf3820080
2038#define F0900_P2_TSFIFOSPEED_STORE 0xf3820040 2025#define F0900_P2_TSFIFOSPEED_STORE 0xf3820040
2039#define F0900_P2_DILXX_RESET 0xf3820020 2026#define F0900_P2_DILXX_RESET 0xf3820020
2040#define F0900_P2_TSSERIAL_IMPOS 0xf3820010 2027#define F0900_P2_TSSERIAL_IMPOS 0xf3820010
2041#define F0900_P2_TSFIFO_LINENOK 0xf3820008 2028#define F0900_P2_SCRAMBDETECT 0xf3820002
2042#define F0900_P2_BITSPEED_EVENT 0xf3820004
2043#define F0900_P2_SCRAMBDETECT 0xf3820002
2044#define F0900_P2_ULDTV67_FALSELOCK 0xf3820001
2045 2029
2046/*P2_TSBITRATE1*/ 2030/*P2_TSBITRATE1*/
2047#define R0900_P2_TSBITRATE1 0xf383 2031#define R0900_P2_TSBITRATE1 0xf383
2048#define F0900_P2_TSFIFO_BITRATE1 0xf38300ff 2032#define F0900_P2_TSFIFO_BITRATE1 0xf38300ff
2049 2033
2050/*P2_TSBITRATE0*/ 2034/*P2_TSBITRATE0*/
2051#define R0900_P2_TSBITRATE0 0xf384 2035#define R0900_P2_TSBITRATE0 0xf384
2052#define F0900_P2_TSFIFO_BITRATE0 0xf38400ff 2036#define F0900_P2_TSFIFO_BITRATE0 0xf38400ff
2053 2037
2054/*P2_ERRCTRL1*/ 2038/*P2_ERRCTRL1*/
2055#define R0900_P2_ERRCTRL1 0xf398 2039#define R0900_P2_ERRCTRL1 0xf398
2056#define F0900_P2_ERR_SOURCE1 0xf39800f0 2040#define F0900_P2_ERR_SOURCE1 0xf39800f0
2057#define F0900_P2_NUM_EVENT1 0xf3980007 2041#define F0900_P2_NUM_EVENT1 0xf3980007
2058 2042
2059/*P2_ERRCNT12*/ 2043/*P2_ERRCNT12*/
2060#define R0900_P2_ERRCNT12 0xf399 2044#define R0900_P2_ERRCNT12 0xf399
2061#define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080 2045#define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080
2062#define F0900_P2_ERR_CNT12 0xf399007f 2046#define F0900_P2_ERR_CNT12 0xf399007f
2063 2047
2064/*P2_ERRCNT11*/ 2048/*P2_ERRCNT11*/
2065#define R0900_P2_ERRCNT11 0xf39a 2049#define R0900_P2_ERRCNT11 0xf39a
2066#define F0900_P2_ERR_CNT11 0xf39a00ff 2050#define F0900_P2_ERR_CNT11 0xf39a00ff
2067 2051
2068/*P2_ERRCNT10*/ 2052/*P2_ERRCNT10*/
2069#define R0900_P2_ERRCNT10 0xf39b 2053#define R0900_P2_ERRCNT10 0xf39b
2070#define F0900_P2_ERR_CNT10 0xf39b00ff 2054#define F0900_P2_ERR_CNT10 0xf39b00ff
2071 2055
2072/*P2_ERRCTRL2*/ 2056/*P2_ERRCTRL2*/
2073#define R0900_P2_ERRCTRL2 0xf39c 2057#define R0900_P2_ERRCTRL2 0xf39c
2074#define F0900_P2_ERR_SOURCE2 0xf39c00f0 2058#define F0900_P2_ERR_SOURCE2 0xf39c00f0
2075#define F0900_P2_NUM_EVENT2 0xf39c0007 2059#define F0900_P2_NUM_EVENT2 0xf39c0007
2076 2060
2077/*P2_ERRCNT22*/ 2061/*P2_ERRCNT22*/
2078#define R0900_P2_ERRCNT22 0xf39d 2062#define R0900_P2_ERRCNT22 0xf39d
2079#define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080 2063#define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080
2080#define F0900_P2_ERR_CNT22 0xf39d007f 2064#define F0900_P2_ERR_CNT22 0xf39d007f
2081 2065
2082/*P2_ERRCNT21*/ 2066/*P2_ERRCNT21*/
2083#define R0900_P2_ERRCNT21 0xf39e 2067#define R0900_P2_ERRCNT21 0xf39e
2084#define F0900_P2_ERR_CNT21 0xf39e00ff 2068#define F0900_P2_ERR_CNT21 0xf39e00ff
2085 2069
2086/*P2_ERRCNT20*/ 2070/*P2_ERRCNT20*/
2087#define R0900_P2_ERRCNT20 0xf39f 2071#define R0900_P2_ERRCNT20 0xf39f
2088#define F0900_P2_ERR_CNT20 0xf39f00ff 2072#define F0900_P2_ERR_CNT20 0xf39f00ff
2089 2073
2090/*P2_FECSPY*/ 2074/*P2_FECSPY*/
2091#define R0900_P2_FECSPY 0xf3a0 2075#define R0900_P2_FECSPY 0xf3a0
2092#define F0900_P2_SPY_ENABLE 0xf3a00080 2076#define F0900_P2_SPY_ENABLE 0xf3a00080
2093#define F0900_P2_NO_SYNCBYTE 0xf3a00040 2077#define F0900_P2_NO_SYNCBYTE 0xf3a00040
2094#define F0900_P2_SERIAL_MODE 0xf3a00020 2078#define F0900_P2_SERIAL_MODE 0xf3a00020
2095#define F0900_P2_UNUSUAL_PACKET 0xf3a00010 2079#define F0900_P2_UNUSUAL_PACKET 0xf3a00010
2096#define F0900_P2_BER_PACKMODE 0xf3a00008 2080#define F0900_P2_BERMETER_DATAMODE 0xf3a00008
2097#define F0900_P2_BERMETER_LMODE 0xf3a00002 2081#define F0900_P2_BERMETER_LMODE 0xf3a00002
2098#define F0900_P2_BERMETER_RESET 0xf3a00001 2082#define F0900_P2_BERMETER_RESET 0xf3a00001
2099 2083
2100/*P2_FSPYCFG*/ 2084/*P2_FSPYCFG*/
2101#define R0900_P2_FSPYCFG 0xf3a1 2085#define R0900_P2_FSPYCFG 0xf3a1
2102#define F0900_P2_FECSPY_INPUT 0xf3a100c0 2086#define F0900_P2_FECSPY_INPUT 0xf3a100c0
2103#define F0900_P2_RST_ON_ERROR 0xf3a10020 2087#define F0900_P2_RST_ON_ERROR 0xf3a10020
2104#define F0900_P2_ONE_SHOT 0xf3a10010 2088#define F0900_P2_ONE_SHOT 0xf3a10010
2105#define F0900_P2_I2C_MODE 0xf3a1000c 2089#define F0900_P2_I2C_MODE 0xf3a1000c
2106#define F0900_P2_SPY_HYSTERESIS 0xf3a10003 2090#define F0900_P2_SPY_HYSTERESIS 0xf3a10003
2107 2091
2108/*P2_FSPYDATA*/ 2092/*P2_FSPYDATA*/
2109#define R0900_P2_FSPYDATA 0xf3a2 2093#define R0900_P2_FSPYDATA 0xf3a2
2110#define F0900_P2_SPY_STUFFING 0xf3a20080 2094#define F0900_P2_SPY_STUFFING 0xf3a20080
2111#define F0900_P2_NOERROR_PKTJITTER 0xf3a20040 2095#define F0900_P2_SPY_CNULLPKT 0xf3a20020
2112#define F0900_P2_SPY_CNULLPKT 0xf3a20020 2096#define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f
2113#define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f
2114 2097
2115/*P2_FSPYOUT*/ 2098/*P2_FSPYOUT*/
2116#define R0900_P2_FSPYOUT 0xf3a3 2099#define R0900_P2_FSPYOUT 0xf3a3
2117#define F0900_P2_FSPY_DIRECT 0xf3a30080 2100#define F0900_P2_FSPY_DIRECT 0xf3a30080
2118#define F0900_P2_SPY_OUTDATA_BUS 0xf3a30038 2101#define F0900_P2_STUFF_MODE 0xf3a30007
2119#define F0900_P2_STUFF_MODE 0xf3a30007
2120 2102
2121/*P2_FSTATUS*/ 2103/*P2_FSTATUS*/
2122#define R0900_P2_FSTATUS 0xf3a4 2104#define R0900_P2_FSTATUS 0xf3a4
2123#define F0900_P2_SPY_ENDSIM 0xf3a40080 2105#define F0900_P2_SPY_ENDSIM 0xf3a40080
2124#define F0900_P2_VALID_SIM 0xf3a40040 2106#define F0900_P2_VALID_SIM 0xf3a40040
2125#define F0900_P2_FOUND_SIGNAL 0xf3a40020 2107#define F0900_P2_FOUND_SIGNAL 0xf3a40020
2126#define F0900_P2_DSS_SYNCBYTE 0xf3a40010 2108#define F0900_P2_DSS_SYNCBYTE 0xf3a40010
2127#define F0900_P2_RESULT_STATE 0xf3a4000f 2109#define F0900_P2_RESULT_STATE 0xf3a4000f
2128 2110
2129/*P2_FBERCPT4*/ 2111/*P2_FBERCPT4*/
2130#define R0900_P2_FBERCPT4 0xf3a8 2112#define R0900_P2_FBERCPT4 0xf3a8
2131#define F0900_P2_FBERMETER_CPT4 0xf3a800ff 2113#define F0900_P2_FBERMETER_CPT4 0xf3a800ff
2132 2114
2133/*P2_FBERCPT3*/ 2115/*P2_FBERCPT3*/
2134#define R0900_P2_FBERCPT3 0xf3a9 2116#define R0900_P2_FBERCPT3 0xf3a9
2135#define F0900_P2_FBERMETER_CPT3 0xf3a900ff 2117#define F0900_P2_FBERMETER_CPT3 0xf3a900ff
2136 2118
2137/*P2_FBERCPT2*/ 2119/*P2_FBERCPT2*/
2138#define R0900_P2_FBERCPT2 0xf3aa 2120#define R0900_P2_FBERCPT2 0xf3aa
2139#define F0900_P2_FBERMETER_CPT2 0xf3aa00ff 2121#define F0900_P2_FBERMETER_CPT2 0xf3aa00ff
2140 2122
2141/*P2_FBERCPT1*/ 2123/*P2_FBERCPT1*/
2142#define R0900_P2_FBERCPT1 0xf3ab 2124#define R0900_P2_FBERCPT1 0xf3ab
2143#define F0900_P2_FBERMETER_CPT1 0xf3ab00ff 2125#define F0900_P2_FBERMETER_CPT1 0xf3ab00ff
2144 2126
2145/*P2_FBERCPT0*/ 2127/*P2_FBERCPT0*/
2146#define R0900_P2_FBERCPT0 0xf3ac 2128#define R0900_P2_FBERCPT0 0xf3ac
2147#define F0900_P2_FBERMETER_CPT0 0xf3ac00ff 2129#define F0900_P2_FBERMETER_CPT0 0xf3ac00ff
2148 2130
2149/*P2_FBERERR2*/ 2131/*P2_FBERERR2*/
2150#define R0900_P2_FBERERR2 0xf3ad 2132#define R0900_P2_FBERERR2 0xf3ad
2151#define F0900_P2_FBERMETER_ERR2 0xf3ad00ff 2133#define F0900_P2_FBERMETER_ERR2 0xf3ad00ff
2152 2134
2153/*P2_FBERERR1*/ 2135/*P2_FBERERR1*/
2154#define R0900_P2_FBERERR1 0xf3ae 2136#define R0900_P2_FBERERR1 0xf3ae
2155#define F0900_P2_FBERMETER_ERR1 0xf3ae00ff 2137#define F0900_P2_FBERMETER_ERR1 0xf3ae00ff
2156 2138
2157/*P2_FBERERR0*/ 2139/*P2_FBERERR0*/
2158#define R0900_P2_FBERERR0 0xf3af 2140#define R0900_P2_FBERERR0 0xf3af
2159#define F0900_P2_FBERMETER_ERR0 0xf3af00ff 2141#define F0900_P2_FBERMETER_ERR0 0xf3af00ff
2160 2142
2161/*P2_FSPYBER*/ 2143/*P2_FSPYBER*/
2162#define R0900_P2_FSPYBER 0xf3b2 2144#define R0900_P2_FSPYBER 0xf3b2
2163#define F0900_P2_FSPYOBS_XORREAD 0xf3b20040 2145#define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010
2164#define F0900_P2_FSPYBER_OBSMODE 0xf3b20020 2146#define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
2165#define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010 2147#define F0900_P2_FSPYBER_CTIME 0xf3b20007
2166#define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
2167#define F0900_P2_FSPYBER_CTIME 0xf3b20007
2168 2148
2169/*P1_IQCONST*/ 2149/*P1_IQCONST*/
2170#define R0900_P1_IQCONST 0xf400 2150#define R0900_P1_IQCONST 0xf400
2171#define F0900_P1_CONSTEL_SELECT 0xf4000060 2151#define IQCONST REGx(R0900_P1_IQCONST)
2172#define F0900_P1_IQSYMB_SEL 0xf400001f 2152#define F0900_P1_CONSTEL_SELECT 0xf4000060
2153#define F0900_P1_IQSYMB_SEL 0xf400001f
2173 2154
2174/*P1_NOSCFG*/ 2155/*P1_NOSCFG*/
2175#define R0900_P1_NOSCFG 0xf401 2156#define R0900_P1_NOSCFG 0xf401
2176#define F0900_P1_DUMMYPL_NOSDATA 0xf4010020 2157#define NOSCFG REGx(R0900_P1_NOSCFG)
2177#define F0900_P1_NOSPLH_BETA 0xf4010018 2158#define F0900_P1_DUMMYPL_NOSDATA 0xf4010020
2178#define F0900_P1_NOSDATA_BETA 0xf4010007 2159#define F0900_P1_NOSPLH_BETA 0xf4010018
2160#define F0900_P1_NOSDATA_BETA 0xf4010007
2179 2161
2180/*P1_ISYMB*/ 2162/*P1_ISYMB*/
2181#define R0900_P1_ISYMB 0xf402 2163#define R0900_P1_ISYMB 0xf402
2182#define F0900_P1_I_SYMBOL 0xf40201ff 2164#define ISYMB REGx(R0900_P1_ISYMB)
2165#define F0900_P1_I_SYMBOL 0xf40201ff
2183 2166
2184/*P1_QSYMB*/ 2167/*P1_QSYMB*/
2185#define R0900_P1_QSYMB 0xf403 2168#define R0900_P1_QSYMB 0xf403
2186#define F0900_P1_Q_SYMBOL 0xf40301ff 2169#define QSYMB REGx(R0900_P1_QSYMB)
2170#define F0900_P1_Q_SYMBOL 0xf40301ff
2187 2171
2188/*P1_AGC1CFG*/ 2172/*P1_AGC1CFG*/
2189#define R0900_P1_AGC1CFG 0xf404 2173#define R0900_P1_AGC1CFG 0xf404
2190#define F0900_P1_DC_FROZEN 0xf4040080 2174#define AGC1CFG REGx(R0900_P1_AGC1CFG)
2191#define F0900_P1_DC_CORRECT 0xf4040040 2175#define F0900_P1_DC_FROZEN 0xf4040080
2192#define F0900_P1_AMM_FROZEN 0xf4040020 2176#define F0900_P1_DC_CORRECT 0xf4040040
2193#define F0900_P1_AMM_CORRECT 0xf4040010 2177#define F0900_P1_AMM_FROZEN 0xf4040020
2194#define F0900_P1_QUAD_FROZEN 0xf4040008 2178#define F0900_P1_AMM_CORRECT 0xf4040010
2195#define F0900_P1_QUAD_CORRECT 0xf4040004 2179#define F0900_P1_QUAD_FROZEN 0xf4040008
2196#define F0900_P1_DCCOMP_SLOW 0xf4040002 2180#define F0900_P1_QUAD_CORRECT 0xf4040004
2197#define F0900_P1_IQMISM_SLOW 0xf4040001
2198 2181
2199/*P1_AGC1CN*/ 2182/*P1_AGC1CN*/
2200#define R0900_P1_AGC1CN 0xf406 2183#define R0900_P1_AGC1CN 0xf406
2201#define F0900_P1_AGC1_LOCKED 0xf4060080 2184#define AGC1CN REGx(R0900_P1_AGC1CN)
2202#define F0900_P1_AGC1_OVERFLOW 0xf4060040 2185#define F0900_P1_AGC1_LOCKED 0xf4060080
2203#define F0900_P1_AGC1_NOSLOWLK 0xf4060020 2186#define F0900_P1_AGC1_MINPOWER 0xf4060010
2204#define F0900_P1_AGC1_MINPOWER 0xf4060010 2187#define F0900_P1_AGCOUT_FAST 0xf4060008
2205#define F0900_P1_AGCOUT_FAST 0xf4060008 2188#define F0900_P1_AGCIQ_BETA 0xf4060007
2206#define F0900_P1_AGCIQ_BETA 0xf4060007
2207 2189
2208/*P1_AGC1REF*/ 2190/*P1_AGC1REF*/
2209#define R0900_P1_AGC1REF 0xf407 2191#define R0900_P1_AGC1REF 0xf407
2210#define F0900_P1_AGCIQ_REF 0xf40700ff 2192#define AGC1REF REGx(R0900_P1_AGC1REF)
2193#define F0900_P1_AGCIQ_REF 0xf40700ff
2211 2194
2212/*P1_IDCCOMP*/ 2195/*P1_IDCCOMP*/
2213#define R0900_P1_IDCCOMP 0xf408 2196#define R0900_P1_IDCCOMP 0xf408
2214#define F0900_P1_IAVERAGE_ADJ 0xf40801ff 2197#define IDCCOMP REGx(R0900_P1_IDCCOMP)
2198#define F0900_P1_IAVERAGE_ADJ 0xf40801ff
2215 2199
2216/*P1_QDCCOMP*/ 2200/*P1_QDCCOMP*/
2217#define R0900_P1_QDCCOMP 0xf409 2201#define R0900_P1_QDCCOMP 0xf409
2218#define F0900_P1_QAVERAGE_ADJ 0xf40901ff 2202#define QDCCOMP REGx(R0900_P1_QDCCOMP)
2203#define F0900_P1_QAVERAGE_ADJ 0xf40901ff
2219 2204
2220/*P1_POWERI*/ 2205/*P1_POWERI*/
2221#define R0900_P1_POWERI 0xf40a 2206#define R0900_P1_POWERI 0xf40a
2222#define F0900_P1_POWER_I 0xf40a00ff 2207#define POWERI REGx(R0900_P1_POWERI)
2208#define F0900_P1_POWER_I 0xf40a00ff
2209#define POWER_I FLDx(F0900_P1_POWER_I)
2223 2210
2224/*P1_POWERQ*/ 2211/*P1_POWERQ*/
2225#define R0900_P1_POWERQ 0xf40b 2212#define R0900_P1_POWERQ 0xf40b
2226#define F0900_P1_POWER_Q 0xf40b00ff 2213#define POWERQ REGx(R0900_P1_POWERQ)
2214#define F0900_P1_POWER_Q 0xf40b00ff
2215#define POWER_Q FLDx(F0900_P1_POWER_Q)
2227 2216
2228/*P1_AGC1AMM*/ 2217/*P1_AGC1AMM*/
2229#define R0900_P1_AGC1AMM 0xf40c 2218#define R0900_P1_AGC1AMM 0xf40c
2230#define F0900_P1_AMM_VALUE 0xf40c00ff 2219#define AGC1AMM REGx(R0900_P1_AGC1AMM)
2220#define F0900_P1_AMM_VALUE 0xf40c00ff
2231 2221
2232/*P1_AGC1QUAD*/ 2222/*P1_AGC1QUAD*/
2233#define R0900_P1_AGC1QUAD 0xf40d 2223#define R0900_P1_AGC1QUAD 0xf40d
2234#define F0900_P1_QUAD_VALUE 0xf40d01ff 2224#define AGC1QUAD REGx(R0900_P1_AGC1QUAD)
2225#define F0900_P1_QUAD_VALUE 0xf40d01ff
2235 2226
2236/*P1_AGCIQIN1*/ 2227/*P1_AGCIQIN1*/
2237#define R0900_P1_AGCIQIN1 0xf40e 2228#define R0900_P1_AGCIQIN1 0xf40e
2238#define F0900_P1_AGCIQ_VALUE1 0xf40e00ff 2229#define AGCIQIN1 REGx(R0900_P1_AGCIQIN1)
2230#define F0900_P1_AGCIQ_VALUE1 0xf40e00ff
2231#define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1)
2239 2232
2240/*P1_AGCIQIN0*/ 2233/*P1_AGCIQIN0*/
2241#define R0900_P1_AGCIQIN0 0xf40f 2234#define R0900_P1_AGCIQIN0 0xf40f
2242#define F0900_P1_AGCIQ_VALUE0 0xf40f00ff 2235#define AGCIQIN0 REGx(R0900_P1_AGCIQIN0)
2236#define F0900_P1_AGCIQ_VALUE0 0xf40f00ff
2237#define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0)
2243 2238
2244/*P1_DEMOD*/ 2239/*P1_DEMOD*/
2245#define R0900_P1_DEMOD 0xf410 2240#define R0900_P1_DEMOD 0xf410
2246#define F0900_P1_DEMOD_STOP 0xf4100040 2241#define DEMOD REGx(R0900_P1_DEMOD)
2247#define F0900_P1_SPECINV_CONTROL 0xf4100030 2242#define F0900_P1_MANUALS2_ROLLOFF 0xf4100080
2248#define F0900_P1_FORCE_ENASAMP 0xf4100008 2243#define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF)
2249#define F0900_P1_MANUAL_ROLLOFF 0xf4100004 2244
2250#define F0900_P1_ROLLOFF_CONTROL 0xf4100003 2245#define F0900_P1_SPECINV_CONTROL 0xf4100030
2246#define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL)
2247#define F0900_P1_FORCE_ENASAMP 0xf4100008
2248#define F0900_P1_MANUALSX_ROLLOFF 0xf4100004
2249#define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF)
2250#define F0900_P1_ROLLOFF_CONTROL 0xf4100003
2251#define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL)
2251 2252
2252/*P1_DMDMODCOD*/ 2253/*P1_DMDMODCOD*/
2253#define R0900_P1_DMDMODCOD 0xf411 2254#define R0900_P1_DMDMODCOD 0xf411
2254#define F0900_P1_MANUAL_MODCOD 0xf4110080 2255#define DMDMODCOD REGx(R0900_P1_DMDMODCOD)
2255#define F0900_P1_DEMOD_MODCOD 0xf411007c 2256#define F0900_P1_MANUAL_MODCOD 0xf4110080
2256#define F0900_P1_DEMOD_TYPE 0xf4110003 2257#define F0900_P1_DEMOD_MODCOD 0xf411007c
2258#define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD)
2259#define F0900_P1_DEMOD_TYPE 0xf4110003
2260#define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE)
2257 2261
2258/*P1_DSTATUS*/ 2262/*P1_DSTATUS*/
2259#define R0900_P1_DSTATUS 0xf412 2263#define R0900_P1_DSTATUS 0xf412
2260#define F0900_P1_CAR_LOCK 0xf4120080 2264#define DSTATUS REGx(R0900_P1_DSTATUS)
2261#define F0900_P1_TMGLOCK_QUALITY 0xf4120060 2265#define F0900_P1_CAR_LOCK 0xf4120080
2262#define F0900_P1_SDVBS1_ENABLE 0xf4120010 2266#define F0900_P1_TMGLOCK_QUALITY 0xf4120060
2263#define F0900_P1_LOCK_DEFINITIF 0xf4120008 2267#define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY)
2264#define F0900_P1_TIMING_IS_LOCKED 0xf4120004 2268#define F0900_P1_LOCK_DEFINITIF 0xf4120008
2265#define F0900_P1_COARSE_TMGLOCK 0xf4120002 2269#define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF)
2266#define F0900_P1_COARSE_CARLOCK 0xf4120001 2270#define F0900_P1_OVADC_DETECT 0xf4120001
2267 2271
2268/*P1_DSTATUS2*/ 2272/*P1_DSTATUS2*/
2269#define R0900_P1_DSTATUS2 0xf413 2273#define R0900_P1_DSTATUS2 0xf413
2270#define F0900_P1_DEMOD_DELOCK 0xf4130080 2274#define DSTATUS2 REGx(R0900_P1_DSTATUS2)
2271#define F0900_P1_DEMOD_TIMEOUT 0xf4130040 2275#define F0900_P1_DEMOD_DELOCK 0xf4130080
2272#define F0900_P1_MODCODRQ_SYNCTAG 0xf4130020 2276#define F0900_P1_AGC1_NOSIGNALACK 0xf4130008
2273#define F0900_P1_POLYPH_SATEVENT 0xf4130010 2277#define F0900_P1_AGC2_OVERFLOW 0xf4130004
2274#define F0900_P1_AGC1_NOSIGNALACK 0xf4130008 2278#define F0900_P1_CFR_OVERFLOW 0xf4130002
2275#define F0900_P1_AGC2_OVERFLOW 0xf4130004 2279#define F0900_P1_GAMMA_OVERUNDER 0xf4130001
2276#define F0900_P1_CFR_OVERFLOW 0xf4130002
2277#define F0900_P1_GAMMA_OVERUNDER 0xf4130001
2278 2280
2279/*P1_DMDCFGMD*/ 2281/*P1_DMDCFGMD*/
2280#define R0900_P1_DMDCFGMD 0xf414 2282#define R0900_P1_DMDCFGMD 0xf414
2281#define F0900_P1_DVBS2_ENABLE 0xf4140080 2283#define DMDCFGMD REGx(R0900_P1_DMDCFGMD)
2282#define F0900_P1_DVBS1_ENABLE 0xf4140040 2284#define F0900_P1_DVBS2_ENABLE 0xf4140080
2283#define F0900_P1_CFR_AUTOSCAN 0xf4140020 2285#define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE)
2284#define F0900_P1_SCAN_ENABLE 0xf4140010 2286#define F0900_P1_DVBS1_ENABLE 0xf4140040
2285#define F0900_P1_TUN_AUTOSCAN 0xf4140008 2287#define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE)
2286#define F0900_P1_NOFORCE_RELOCK 0xf4140004 2288#define F0900_P1_SCAN_ENABLE 0xf4140010
2287#define F0900_P1_TUN_RNG 0xf4140003 2289#define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE)
2290#define F0900_P1_CFR_AUTOSCAN 0xf4140008
2291#define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN)
2292#define F0900_P1_TUN_RNG 0xf4140003
2288 2293
2289/*P1_DMDCFG2*/ 2294/*P1_DMDCFG2*/
2290#define R0900_P1_DMDCFG2 0xf415 2295#define R0900_P1_DMDCFG2 0xf415
2291#define F0900_P1_AGC1_WAITLOCK 0xf4150080 2296#define DMDCFG2 REGx(R0900_P1_DMDCFG2)
2292#define F0900_P1_S1S2_SEQUENTIAL 0xf4150040 2297#define F0900_P1_S1S2_SEQUENTIAL 0xf4150040
2293#define F0900_P1_OVERFLOW_TIMEOUT 0xf4150020 2298#define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL)
2294#define F0900_P1_SCANFAIL_TIMEOUT 0xf4150010 2299#define F0900_P1_INFINITE_RELOCK 0xf4150010
2295#define F0900_P1_DMDTOUT_BACK 0xf4150008
2296#define F0900_P1_CARLOCK_S1ENABLE 0xf4150004
2297#define F0900_P1_COARSE_LK3MODE 0xf4150002
2298#define F0900_P1_COARSE_LK2MODE 0xf4150001
2299 2300
2300/*P1_DMDISTATE*/ 2301/*P1_DMDISTATE*/
2301#define R0900_P1_DMDISTATE 0xf416 2302#define R0900_P1_DMDISTATE 0xf416
2302#define F0900_P1_I2C_NORESETDMODE 0xf4160080 2303#define DMDISTATE REGx(R0900_P1_DMDISTATE)
2303#define F0900_P1_FORCE_ETAPED 0xf4160040 2304#define F0900_P1_I2C_DEMOD_MODE 0xf416001f
2304#define F0900_P1_SDMDRST_DIRCLK 0xf4160020 2305#define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE)
2305#define F0900_P1_I2C_DEMOD_MODE 0xf416001f
2306 2306
2307/*P1_DMDT0M*/ 2307/*P1_DMDT0M*/
2308#define R0900_P1_DMDT0M 0xf417 2308#define R0900_P1_DMDT0M 0xf417
2309#define F0900_P1_DMDT0_MIN 0xf41700ff 2309#define DMDT0M REGx(R0900_P1_DMDT0M)
2310#define F0900_P1_DMDT0_MIN 0xf41700ff
2310 2311
2311/*P1_DMDSTATE*/ 2312/*P1_DMDSTATE*/
2312#define R0900_P1_DMDSTATE 0xf41b 2313#define R0900_P1_DMDSTATE 0xf41b
2313#define F0900_P1_DEMOD_LOCKED 0xf41b0080 2314#define DMDSTATE REGx(R0900_P1_DMDSTATE)
2314#define F0900_P1_HEADER_MODE 0xf41b0060 2315#define F0900_P1_HEADER_MODE 0xf41b0060
2315#define F0900_P1_DEMOD_MODE 0xf41b001f 2316#define HEADER_MODE FLDx(F0900_P1_HEADER_MODE)
2316 2317
2317/*P1_DMDFLYW*/ 2318/*P1_DMDFLYW*/
2318#define R0900_P1_DMDFLYW 0xf41c 2319#define R0900_P1_DMDFLYW 0xf41c
2319#define F0900_P1_I2C_IRQVAL 0xf41c00f0 2320#define DMDFLYW REGx(R0900_P1_DMDFLYW)
2320#define F0900_P1_FLYWHEEL_CPT 0xf41c000f 2321#define F0900_P1_I2C_IRQVAL 0xf41c00f0
2322#define F0900_P1_FLYWHEEL_CPT 0xf41c000f
2323#define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT)
2321 2324
2322/*P1_DSTATUS3*/ 2325/*P1_DSTATUS3*/
2323#define R0900_P1_DSTATUS3 0xf41d 2326#define R0900_P1_DSTATUS3 0xf41d
2324#define F0900_P1_CFR_ZIGZAG 0xf41d0080 2327#define DSTATUS3 REGx(R0900_P1_DSTATUS3)
2325#define F0900_P1_DEMOD_CFGMODE 0xf41d0060 2328#define F0900_P1_DEMOD_CFGMODE 0xf41d0060
2326#define F0900_P1_GAMMA_LOWBAUDRATE 0xf41d0010
2327#define F0900_P1_RELOCK_MODE 0xf41d0008
2328#define F0900_P1_DEMOD_FAIL 0xf41d0004
2329#define F0900_P1_ETAPE1A_DVBXMEM 0xf41d0003
2330 2329
2331/*P1_DMDCFG3*/ 2330/*P1_DMDCFG3*/
2332#define R0900_P1_DMDCFG3 0xf41e 2331#define R0900_P1_DMDCFG3 0xf41e
2333#define F0900_P1_DVBS1_TMGWAIT 0xf41e0080 2332#define DMDCFG3 REGx(R0900_P1_DMDCFG3)
2334#define F0900_P1_NO_BWCENTERING 0xf41e0040 2333#define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
2335#define F0900_P1_INV_SEQSRCH 0xf41e0020
2336#define F0900_P1_DIS_SFRUPLOW_TRK 0xf41e0010
2337#define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
2338#define F0900_P1_LOCKTIME_MODE 0xf41e0007
2339 2334
2340/*P1_DMDCFG4*/ 2335/*P1_DMDCFG4*/
2341#define R0900_P1_DMDCFG4 0xf41f 2336#define R0900_P1_DMDCFG4 0xf41f
2342#define F0900_P1_TUNER_NRELAUNCH 0xf41f0008 2337#define DMDCFG4 REGx(R0900_P1_DMDCFG4)
2343#define F0900_P1_DIS_CLKENABLE 0xf41f0004 2338#define F0900_P1_TUNER_NRELAUNCH 0xf41f0008
2344#define F0900_P1_DIS_HDRDIVLOCK 0xf41f0002
2345#define F0900_P1_NO_TNRWBINIT 0xf41f0001
2346 2339
2347/*P1_CORRELMANT*/ 2340/*P1_CORRELMANT*/
2348#define R0900_P1_CORRELMANT 0xf420 2341#define R0900_P1_CORRELMANT 0xf420
2349#define F0900_P1_CORREL_MANT 0xf42000ff 2342#define CORRELMANT REGx(R0900_P1_CORRELMANT)
2343#define F0900_P1_CORREL_MANT 0xf42000ff
2350 2344
2351/*P1_CORRELABS*/ 2345/*P1_CORRELABS*/
2352#define R0900_P1_CORRELABS 0xf421 2346#define R0900_P1_CORRELABS 0xf421
2353#define F0900_P1_CORREL_ABS 0xf42100ff 2347#define CORRELABS REGx(R0900_P1_CORRELABS)
2348#define F0900_P1_CORREL_ABS 0xf42100ff
2354 2349
2355/*P1_CORRELEXP*/ 2350/*P1_CORRELEXP*/
2356#define R0900_P1_CORRELEXP 0xf422 2351#define R0900_P1_CORRELEXP 0xf422
2357#define F0900_P1_CORREL_ABSEXP 0xf42200f0 2352#define CORRELEXP REGx(R0900_P1_CORRELEXP)
2358#define F0900_P1_CORREL_EXP 0xf422000f 2353#define F0900_P1_CORREL_ABSEXP 0xf42200f0
2354#define F0900_P1_CORREL_EXP 0xf422000f
2359 2355
2360/*P1_PLHMODCOD*/ 2356/*P1_PLHMODCOD*/
2361#define R0900_P1_PLHMODCOD 0xf424 2357#define R0900_P1_PLHMODCOD 0xf424
2362#define F0900_P1_SPECINV_DEMOD 0xf4240080 2358#define PLHMODCOD REGx(R0900_P1_PLHMODCOD)
2363#define F0900_P1_PLH_MODCOD 0xf424007c 2359#define F0900_P1_SPECINV_DEMOD 0xf4240080
2364#define F0900_P1_PLH_TYPE 0xf4240003 2360#define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD)
2365 2361#define F0900_P1_PLH_MODCOD 0xf424007c
2366/*P1_AGCK32*/ 2362#define F0900_P1_PLH_TYPE 0xf4240003
2367#define R0900_P1_AGCK32 0xf42b 2363
2368#define F0900_P1_R3ADJOFF_32APSK 0xf42b0080 2364/*P1_DMDREG*/
2369#define F0900_P1_R2ADJOFF_32APSK 0xf42b0040 2365#define R0900_P1_DMDREG 0xf425
2370#define F0900_P1_R1ADJOFF_32APSK 0xf42b0020 2366#define DMDREG REGx(R0900_P1_DMDREG)
2371#define F0900_P1_RADJ_32APSK 0xf42b001f 2367#define F0900_P1_DECIM_PLFRAMES 0xf4250001
2372 2368
2373/*P1_AGC2O*/ 2369/*P1_AGC2O*/
2374#define R0900_P1_AGC2O 0xf42c 2370#define R0900_P1_AGC2O 0xf42c
2375#define F0900_P1_AGC2REF_ADJUSTING 0xf42c0080 2371#define AGC2O REGx(R0900_P1_AGC2O)
2376#define F0900_P1_AGC2_COARSEFAST 0xf42c0040 2372#define F0900_P1_AGC2_COEF 0xf42c0007
2377#define F0900_P1_AGC2_LKSQRT 0xf42c0020
2378#define F0900_P1_AGC2_LKMODE 0xf42c0010
2379#define F0900_P1_AGC2_LKEQUA 0xf42c0008
2380#define F0900_P1_AGC2_COEF 0xf42c0007
2381 2373
2382/*P1_AGC2REF*/ 2374/*P1_AGC2REF*/
2383#define R0900_P1_AGC2REF 0xf42d 2375#define R0900_P1_AGC2REF 0xf42d
2384#define F0900_P1_AGC2_REF 0xf42d00ff 2376#define AGC2REF REGx(R0900_P1_AGC2REF)
2377#define F0900_P1_AGC2_REF 0xf42d00ff
2385 2378
2386/*P1_AGC1ADJ*/ 2379/*P1_AGC1ADJ*/
2387#define R0900_P1_AGC1ADJ 0xf42e 2380#define R0900_P1_AGC1ADJ 0xf42e
2388#define F0900_P1_AGC1ADJ_MANUAL 0xf42e0080 2381#define AGC1ADJ REGx(R0900_P1_AGC1ADJ)
2389#define F0900_P1_AGC1_ADJUSTED 0xf42e017f 2382#define F0900_P1_AGC1_ADJUSTED 0xf42e007f
2390 2383
2391/*P1_AGC2I1*/ 2384/*P1_AGC2I1*/
2392#define R0900_P1_AGC2I1 0xf436 2385#define R0900_P1_AGC2I1 0xf436
2393#define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff 2386#define AGC2I1 REGx(R0900_P1_AGC2I1)
2387#define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff
2394 2388
2395/*P1_AGC2I0*/ 2389/*P1_AGC2I0*/
2396#define R0900_P1_AGC2I0 0xf437 2390#define R0900_P1_AGC2I0 0xf437
2397#define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff 2391#define AGC2I0 REGx(R0900_P1_AGC2I0)
2392#define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff
2398 2393
2399/*P1_CARCFG*/ 2394/*P1_CARCFG*/
2400#define R0900_P1_CARCFG 0xf438 2395#define R0900_P1_CARCFG 0xf438
2401#define F0900_P1_CFRUPLOW_AUTO 0xf4380080 2396#define CARCFG REGx(R0900_P1_CARCFG)
2402#define F0900_P1_CFRUPLOW_TEST 0xf4380040 2397#define F0900_P1_CFRUPLOW_AUTO 0xf4380080
2403#define F0900_P1_EN_CAR2CENTER 0xf4380020 2398#define F0900_P1_CFRUPLOW_TEST 0xf4380040
2404#define F0900_P1_CARHDR_NODIV8 0xf4380010 2399#define F0900_P1_ROTAON 0xf4380004
2405#define F0900_P1_I2C_ROTA 0xf4380008 2400#define F0900_P1_PH_DET_ALGO 0xf4380003
2406#define F0900_P1_ROTAON 0xf4380004
2407#define F0900_P1_PH_DET_ALGO 0xf4380003
2408 2401
2409/*P1_ACLC*/ 2402/*P1_ACLC*/
2410#define R0900_P1_ACLC 0xf439 2403#define R0900_P1_ACLC 0xf439
2411#define F0900_P1_STOP_S2ALPHA 0xf43900c0 2404#define ACLC REGx(R0900_P1_ACLC)
2412#define F0900_P1_CAR_ALPHA_MANT 0xf4390030 2405#define F0900_P1_CAR_ALPHA_MANT 0xf4390030
2413#define F0900_P1_CAR_ALPHA_EXP 0xf439000f 2406#define F0900_P1_CAR_ALPHA_EXP 0xf439000f
2414 2407
2415/*P1_BCLC*/ 2408/*P1_BCLC*/
2416#define R0900_P1_BCLC 0xf43a 2409#define R0900_P1_BCLC 0xf43a
2417#define F0900_P1_STOP_S2BETA 0xf43a00c0 2410#define BCLC REGx(R0900_P1_BCLC)
2418#define F0900_P1_CAR_BETA_MANT 0xf43a0030 2411#define F0900_P1_CAR_BETA_MANT 0xf43a0030
2419#define F0900_P1_CAR_BETA_EXP 0xf43a000f 2412#define F0900_P1_CAR_BETA_EXP 0xf43a000f
2420 2413
2421/*P1_CARFREQ*/ 2414/*P1_CARFREQ*/
2422#define R0900_P1_CARFREQ 0xf43d 2415#define R0900_P1_CARFREQ 0xf43d
2423#define F0900_P1_KC_COARSE_EXP 0xf43d00f0 2416#define CARFREQ REGx(R0900_P1_CARFREQ)
2424#define F0900_P1_BETA_FREQ 0xf43d000f 2417#define F0900_P1_KC_COARSE_EXP 0xf43d00f0
2418#define F0900_P1_BETA_FREQ 0xf43d000f
2425 2419
2426/*P1_CARHDR*/ 2420/*P1_CARHDR*/
2427#define R0900_P1_CARHDR 0xf43e 2421#define R0900_P1_CARHDR 0xf43e
2428#define F0900_P1_K_FREQ_HDR 0xf43e00ff 2422#define CARHDR REGx(R0900_P1_CARHDR)
2423#define F0900_P1_K_FREQ_HDR 0xf43e00ff
2429 2424
2430/*P1_LDT*/ 2425/*P1_LDT*/
2431#define R0900_P1_LDT 0xf43f 2426#define R0900_P1_LDT 0xf43f
2432#define F0900_P1_CARLOCK_THRES 0xf43f01ff 2427#define LDT REGx(R0900_P1_LDT)
2428#define F0900_P1_CARLOCK_THRES 0xf43f01ff
2433 2429
2434/*P1_LDT2*/ 2430/*P1_LDT2*/
2435#define R0900_P1_LDT2 0xf440 2431#define R0900_P1_LDT2 0xf440
2436#define F0900_P1_CARLOCK_THRES2 0xf44001ff 2432#define LDT2 REGx(R0900_P1_LDT2)
2433#define F0900_P1_CARLOCK_THRES2 0xf44001ff
2437 2434
2438/*P1_CFRICFG*/ 2435/*P1_CFRICFG*/
2439#define R0900_P1_CFRICFG 0xf441 2436#define R0900_P1_CFRICFG 0xf441
2440#define F0900_P1_CFRINIT_UNVALRNG 0xf4410080 2437#define CFRICFG REGx(R0900_P1_CFRICFG)
2441#define F0900_P1_CFRINIT_LUNVALCPT 0xf4410040 2438#define F0900_P1_NEG_CFRSTEP 0xf4410001
2442#define F0900_P1_CFRINIT_ABORTDBL 0xf4410020
2443#define F0900_P1_CFRINIT_ABORTPRED 0xf4410010
2444#define F0900_P1_CFRINIT_UNVALSKIP 0xf4410008
2445#define F0900_P1_CFRINIT_CSTINC 0xf4410004
2446#define F0900_P1_NEG_CFRSTEP 0xf4410001
2447 2439
2448/*P1_CFRUP1*/ 2440/*P1_CFRUP1*/
2449#define R0900_P1_CFRUP1 0xf442 2441#define R0900_P1_CFRUP1 0xf442
2450#define F0900_P1_CFR_UP1 0xf44201ff 2442#define CFRUP1 REGx(R0900_P1_CFRUP1)
2443#define F0900_P1_CFR_UP1 0xf44201ff
2444#define CFR_UP1 FLDx(F0900_P1_CFR_UP1)
2451 2445
2452/*P1_CFRUP0*/ 2446/*P1_CFRUP0*/
2453#define R0900_P1_CFRUP0 0xf443 2447#define R0900_P1_CFRUP0 0xf443
2454#define F0900_P1_CFR_UP0 0xf44300ff 2448#define CFRUP0 REGx(R0900_P1_CFRUP0)
2449#define F0900_P1_CFR_UP0 0xf44300ff
2450#define CFR_UP0 FLDx(F0900_P1_CFR_UP0)
2455 2451
2456/*P1_CFRLOW1*/ 2452/*P1_CFRLOW1*/
2457#define R0900_P1_CFRLOW1 0xf446 2453#define R0900_P1_CFRLOW1 0xf446
2458#define F0900_P1_CFR_LOW1 0xf44601ff 2454#define CFRLOW1 REGx(R0900_P1_CFRLOW1)
2455#define F0900_P1_CFR_LOW1 0xf44601ff
2456#define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1)
2459 2457
2460/*P1_CFRLOW0*/ 2458/*P1_CFRLOW0*/
2461#define R0900_P1_CFRLOW0 0xf447 2459#define R0900_P1_CFRLOW0 0xf447
2462#define F0900_P1_CFR_LOW0 0xf44700ff 2460#define CFRLOW0 REGx(R0900_P1_CFRLOW0)
2461#define F0900_P1_CFR_LOW0 0xf44700ff
2462#define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0)
2463 2463
2464/*P1_CFRINIT1*/ 2464/*P1_CFRINIT1*/
2465#define R0900_P1_CFRINIT1 0xf448 2465#define R0900_P1_CFRINIT1 0xf448
2466#define F0900_P1_CFR_INIT1 0xf44801ff 2466#define CFRINIT1 REGx(R0900_P1_CFRINIT1)
2467#define F0900_P1_CFR_INIT1 0xf44801ff
2468#define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1)
2467 2469
2468/*P1_CFRINIT0*/ 2470/*P1_CFRINIT0*/
2469#define R0900_P1_CFRINIT0 0xf449 2471#define R0900_P1_CFRINIT0 0xf449
2470#define F0900_P1_CFR_INIT0 0xf44900ff 2472#define CFRINIT0 REGx(R0900_P1_CFRINIT0)
2473#define F0900_P1_CFR_INIT0 0xf44900ff
2474#define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0)
2471 2475
2472/*P1_CFRINC1*/ 2476/*P1_CFRINC1*/
2473#define R0900_P1_CFRINC1 0xf44a 2477#define R0900_P1_CFRINC1 0xf44a
2474#define F0900_P1_MANUAL_CFRINC 0xf44a0080 2478#define CFRINC1 REGx(R0900_P1_CFRINC1)
2475#define F0900_P1_CFR_INC1 0xf44a017f 2479#define F0900_P1_MANUAL_CFRINC 0xf44a0080
2480#define F0900_P1_CFR_INC1 0xf44a003f
2476 2481
2477/*P1_CFRINC0*/ 2482/*P1_CFRINC0*/
2478#define R0900_P1_CFRINC0 0xf44b 2483#define R0900_P1_CFRINC0 0xf44b
2479#define F0900_P1_CFR_INC0 0xf44b00f0 2484#define CFRINC0 REGx(R0900_P1_CFRINC0)
2485#define F0900_P1_CFR_INC0 0xf44b00f8
2480 2486
2481/*P1_CFR2*/ 2487/*P1_CFR2*/
2482#define R0900_P1_CFR2 0xf44c 2488#define R0900_P1_CFR2 0xf44c
2483#define F0900_P1_CAR_FREQ2 0xf44c01ff 2489#define CFR2 REGx(R0900_P1_CFR2)
2490#define F0900_P1_CAR_FREQ2 0xf44c01ff
2491#define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2)
2484 2492
2485/*P1_CFR1*/ 2493/*P1_CFR1*/
2486#define R0900_P1_CFR1 0xf44d 2494#define R0900_P1_CFR1 0xf44d
2487#define F0900_P1_CAR_FREQ1 0xf44d00ff 2495#define CFR1 REGx(R0900_P1_CFR1)
2496#define F0900_P1_CAR_FREQ1 0xf44d00ff
2497#define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1)
2488 2498
2489/*P1_CFR0*/ 2499/*P1_CFR0*/
2490#define R0900_P1_CFR0 0xf44e 2500#define R0900_P1_CFR0 0xf44e
2491#define F0900_P1_CAR_FREQ0 0xf44e00ff 2501#define CFR0 REGx(R0900_P1_CFR0)
2502#define F0900_P1_CAR_FREQ0 0xf44e00ff
2503#define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0)
2492 2504
2493/*P1_LDI*/ 2505/*P1_LDI*/
2494#define R0900_P1_LDI 0xf44f 2506#define R0900_P1_LDI 0xf44f
2495#define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff 2507#define LDI REGx(R0900_P1_LDI)
2508#define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff
2496 2509
2497/*P1_TMGCFG*/ 2510/*P1_TMGCFG*/
2498#define R0900_P1_TMGCFG 0xf450 2511#define R0900_P1_TMGCFG 0xf450
2499#define F0900_P1_TMGLOCK_BETA 0xf45000c0 2512#define TMGCFG REGx(R0900_P1_TMGCFG)
2500#define F0900_P1_NOTMG_GROUPDELAY 0xf4500020 2513#define F0900_P1_TMGLOCK_BETA 0xf45000c0
2501#define F0900_P1_DO_TIMING_CORR 0xf4500010 2514#define F0900_P1_DO_TIMING_CORR 0xf4500010
2502#define F0900_P1_MANUAL_SCAN 0xf450000c 2515#define F0900_P1_TMG_MINFREQ 0xf4500003
2503#define F0900_P1_TMG_MINFREQ 0xf4500003
2504 2516
2505/*P1_RTC*/ 2517/*P1_RTC*/
2506#define R0900_P1_RTC 0xf451 2518#define R0900_P1_RTC 0xf451
2507#define F0900_P1_TMGALPHA_EXP 0xf45100f0 2519#define RTC REGx(R0900_P1_RTC)
2508#define F0900_P1_TMGBETA_EXP 0xf451000f 2520#define F0900_P1_TMGALPHA_EXP 0xf45100f0
2521#define F0900_P1_TMGBETA_EXP 0xf451000f
2509 2522
2510/*P1_RTCS2*/ 2523/*P1_RTCS2*/
2511#define R0900_P1_RTCS2 0xf452 2524#define R0900_P1_RTCS2 0xf452
2512#define F0900_P1_TMGALPHAS2_EXP 0xf45200f0 2525#define RTCS2 REGx(R0900_P1_RTCS2)
2513#define F0900_P1_TMGBETAS2_EXP 0xf452000f 2526#define F0900_P1_TMGALPHAS2_EXP 0xf45200f0
2527#define F0900_P1_TMGBETAS2_EXP 0xf452000f
2514 2528
2515/*P1_TMGTHRISE*/ 2529/*P1_TMGTHRISE*/
2516#define R0900_P1_TMGTHRISE 0xf453 2530#define R0900_P1_TMGTHRISE 0xf453
2517#define F0900_P1_TMGLOCK_THRISE 0xf45300ff 2531#define TMGTHRISE REGx(R0900_P1_TMGTHRISE)
2532#define F0900_P1_TMGLOCK_THRISE 0xf45300ff
2518 2533
2519/*P1_TMGTHFALL*/ 2534/*P1_TMGTHFALL*/
2520#define R0900_P1_TMGTHFALL 0xf454 2535#define R0900_P1_TMGTHFALL 0xf454
2521#define F0900_P1_TMGLOCK_THFALL 0xf45400ff 2536#define TMGTHFALL REGx(R0900_P1_TMGTHFALL)
2537#define F0900_P1_TMGLOCK_THFALL 0xf45400ff
2522 2538
2523/*P1_SFRUPRATIO*/ 2539/*P1_SFRUPRATIO*/
2524#define R0900_P1_SFRUPRATIO 0xf455 2540#define R0900_P1_SFRUPRATIO 0xf455
2525#define F0900_P1_SFR_UPRATIO 0xf45500ff 2541#define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO)
2542#define F0900_P1_SFR_UPRATIO 0xf45500ff
2526 2543
2527/*P1_SFRLOWRATIO*/ 2544/*P1_SFRLOWRATIO*/
2528#define R0900_P1_SFRLOWRATIO 0xf456 2545#define R0900_P1_SFRLOWRATIO 0xf456
2529#define F0900_P1_SFR_LOWRATIO 0xf45600ff 2546#define F0900_P1_SFR_LOWRATIO 0xf45600ff
2530 2547
2531/*P1_KREFTMG*/ 2548/*P1_KREFTMG*/
2532#define R0900_P1_KREFTMG 0xf458 2549#define R0900_P1_KREFTMG 0xf458
2533#define F0900_P1_KREF_TMG 0xf45800ff 2550#define KREFTMG REGx(R0900_P1_KREFTMG)
2551#define F0900_P1_KREF_TMG 0xf45800ff
2534 2552
2535/*P1_SFRSTEP*/ 2553/*P1_SFRSTEP*/
2536#define R0900_P1_SFRSTEP 0xf459 2554#define R0900_P1_SFRSTEP 0xf459
2537#define F0900_P1_SFR_SCANSTEP 0xf45900f0 2555#define SFRSTEP REGx(R0900_P1_SFRSTEP)
2538#define F0900_P1_SFR_CENTERSTEP 0xf459000f 2556#define F0900_P1_SFR_SCANSTEP 0xf45900f0
2557#define F0900_P1_SFR_CENTERSTEP 0xf459000f
2539 2558
2540/*P1_TMGCFG2*/ 2559/*P1_TMGCFG2*/
2541#define R0900_P1_TMGCFG2 0xf45a 2560#define R0900_P1_TMGCFG2 0xf45a
2542#define F0900_P1_DIS_AUTOSAMP 0xf45a0008 2561#define TMGCFG2 REGx(R0900_P1_TMGCFG2)
2543#define F0900_P1_SCANINIT_QUART 0xf45a0004 2562#define F0900_P1_SFRRATIO_FINE 0xf45a0001
2544#define F0900_P1_NOTMG_DVBS1DERAT 0xf45a0002 2563
2545#define F0900_P1_SFRRATIO_FINE 0xf45a0001 2564/*P1_KREFTMG2*/
2565#define R0900_P1_KREFTMG2 0xf45b
2566#define KREFTMG2 REGx(R0900_P1_KREFTMG2)
2567#define F0900_P1_KREF_TMG2 0xf45b00ff
2546 2568
2547/*P1_SFRINIT1*/ 2569/*P1_SFRINIT1*/
2548#define R0900_P1_SFRINIT1 0xf45e 2570#define R0900_P1_SFRINIT1 0xf45e
2549#define F0900_P1_SFR_INIT1 0xf45e00ff 2571#define SFRINIT1 REGx(R0900_P1_SFRINIT1)
2572#define F0900_P1_SFR_INIT1 0xf45e007f
2550 2573
2551/*P1_SFRINIT0*/ 2574/*P1_SFRINIT0*/
2552#define R0900_P1_SFRINIT0 0xf45f 2575#define R0900_P1_SFRINIT0 0xf45f
2553#define F0900_P1_SFR_INIT0 0xf45f00ff 2576#define SFRINIT0 REGx(R0900_P1_SFRINIT0)
2577#define F0900_P1_SFR_INIT0 0xf45f00ff
2554 2578
2555/*P1_SFRUP1*/ 2579/*P1_SFRUP1*/
2556#define R0900_P1_SFRUP1 0xf460 2580#define R0900_P1_SFRUP1 0xf460
2557#define F0900_P1_AUTO_GUP 0xf4600080 2581#define SFRUP1 REGx(R0900_P1_SFRUP1)
2558#define F0900_P1_SYMB_FREQ_UP1 0xf460007f 2582#define F0900_P1_AUTO_GUP 0xf4600080
2583#define AUTO_GUP FLDx(F0900_P1_AUTO_GUP)
2584#define F0900_P1_SYMB_FREQ_UP1 0xf460007f
2559 2585
2560/*P1_SFRUP0*/ 2586/*P1_SFRUP0*/
2561#define R0900_P1_SFRUP0 0xf461 2587#define R0900_P1_SFRUP0 0xf461
2562#define F0900_P1_SYMB_FREQ_UP0 0xf46100ff 2588#define SFRUP0 REGx(R0900_P1_SFRUP0)
2589#define F0900_P1_SYMB_FREQ_UP0 0xf46100ff
2563 2590
2564/*P1_SFRLOW1*/ 2591/*P1_SFRLOW1*/
2565#define R0900_P1_SFRLOW1 0xf462 2592#define R0900_P1_SFRLOW1 0xf462
2566#define F0900_P1_AUTO_GLOW 0xf4620080 2593#define SFRLOW1 REGx(R0900_P1_SFRLOW1)
2567#define F0900_P1_SYMB_FREQ_LOW1 0xf462007f 2594#define F0900_P1_AUTO_GLOW 0xf4620080
2595#define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW)
2596#define F0900_P1_SYMB_FREQ_LOW1 0xf462007f
2568 2597
2569/*P1_SFRLOW0*/ 2598/*P1_SFRLOW0*/
2570#define R0900_P1_SFRLOW0 0xf463 2599#define R0900_P1_SFRLOW0 0xf463
2571#define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff 2600#define SFRLOW0 REGx(R0900_P1_SFRLOW0)
2601#define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff
2572 2602
2573/*P1_SFR3*/ 2603/*P1_SFR3*/
2574#define R0900_P1_SFR3 0xf464 2604#define R0900_P1_SFR3 0xf464
2575#define F0900_P1_SYMB_FREQ3 0xf46400ff 2605#define SFR3 REGx(R0900_P1_SFR3)
2606#define F0900_P1_SYMB_FREQ3 0xf46400ff
2607#define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3)
2576 2608
2577/*P1_SFR2*/ 2609/*P1_SFR2*/
2578#define R0900_P1_SFR2 0xf465 2610#define R0900_P1_SFR2 0xf465
2579#define F0900_P1_SYMB_FREQ2 0xf46500ff 2611#define SFR2 REGx(R0900_P1_SFR2)
2612#define F0900_P1_SYMB_FREQ2 0xf46500ff
2613#define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2)
2580 2614
2581/*P1_SFR1*/ 2615/*P1_SFR1*/
2582#define R0900_P1_SFR1 0xf466 2616#define R0900_P1_SFR1 0xf466
2583#define F0900_P1_SYMB_FREQ1 0xf46600ff 2617#define SFR1 REGx(R0900_P1_SFR1)
2618#define F0900_P1_SYMB_FREQ1 0xf46600ff
2619#define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1)
2584 2620
2585/*P1_SFR0*/ 2621/*P1_SFR0*/
2586#define R0900_P1_SFR0 0xf467 2622#define R0900_P1_SFR0 0xf467
2587#define F0900_P1_SYMB_FREQ0 0xf46700ff 2623#define SFR0 REGx(R0900_P1_SFR0)
2624#define F0900_P1_SYMB_FREQ0 0xf46700ff
2625#define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0)
2588 2626
2589/*P1_TMGREG2*/ 2627/*P1_TMGREG2*/
2590#define R0900_P1_TMGREG2 0xf468 2628#define R0900_P1_TMGREG2 0xf468
2591#define F0900_P1_TMGREG2 0xf46800ff 2629#define TMGREG2 REGx(R0900_P1_TMGREG2)
2630#define F0900_P1_TMGREG2 0xf46800ff
2592 2631
2593/*P1_TMGREG1*/ 2632/*P1_TMGREG1*/
2594#define R0900_P1_TMGREG1 0xf469 2633#define R0900_P1_TMGREG1 0xf469
2595#define F0900_P1_TMGREG1 0xf46900ff 2634#define TMGREG1 REGx(R0900_P1_TMGREG1)
2635#define F0900_P1_TMGREG1 0xf46900ff
2596 2636
2597/*P1_TMGREG0*/ 2637/*P1_TMGREG0*/
2598#define R0900_P1_TMGREG0 0xf46a 2638#define R0900_P1_TMGREG0 0xf46a
2599#define F0900_P1_TMGREG0 0xf46a00ff 2639#define TMGREG0 REGx(R0900_P1_TMGREG0)
2640#define F0900_P1_TMGREG0 0xf46a00ff
2600 2641
2601/*P1_TMGLOCK1*/ 2642/*P1_TMGLOCK1*/
2602#define R0900_P1_TMGLOCK1 0xf46b 2643#define R0900_P1_TMGLOCK1 0xf46b
2603#define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff 2644#define TMGLOCK1 REGx(R0900_P1_TMGLOCK1)
2645#define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff
2604 2646
2605/*P1_TMGLOCK0*/ 2647/*P1_TMGLOCK0*/
2606#define R0900_P1_TMGLOCK0 0xf46c 2648#define R0900_P1_TMGLOCK0 0xf46c
2607#define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff 2649#define TMGLOCK0 REGx(R0900_P1_TMGLOCK0)
2650#define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff
2608 2651
2609/*P1_TMGOBS*/ 2652/*P1_TMGOBS*/
2610#define R0900_P1_TMGOBS 0xf46d 2653#define R0900_P1_TMGOBS 0xf46d
2611#define F0900_P1_ROLLOFF_STATUS 0xf46d00c0 2654#define TMGOBS REGx(R0900_P1_TMGOBS)
2612#define F0900_P1_SCAN_SIGN 0xf46d0030 2655#define F0900_P1_ROLLOFF_STATUS 0xf46d00c0
2613#define F0900_P1_TMG_SCANNING 0xf46d0008 2656#define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS)
2614#define F0900_P1_CHCENTERING_MODE 0xf46d0004
2615#define F0900_P1_TMG_SCANFAIL 0xf46d0002
2616 2657
2617/*P1_EQUALCFG*/ 2658/*P1_EQUALCFG*/
2618#define R0900_P1_EQUALCFG 0xf46f 2659#define R0900_P1_EQUALCFG 0xf46f
2619#define F0900_P1_NOTMG_NEGALWAIT 0xf46f0080 2660#define EQUALCFG REGx(R0900_P1_EQUALCFG)
2620#define F0900_P1_EQUAL_ON 0xf46f0040 2661#define F0900_P1_EQUAL_ON 0xf46f0040
2621#define F0900_P1_SEL_EQUALCOR 0xf46f0038 2662#define F0900_P1_MU_EQUALDFE 0xf46f0007
2622#define F0900_P1_MU_EQUALDFE 0xf46f0007
2623 2663
2624/*P1_EQUAI1*/ 2664/*P1_EQUAI1*/
2625#define R0900_P1_EQUAI1 0xf470 2665#define R0900_P1_EQUAI1 0xf470
2626#define F0900_P1_EQUA_ACCI1 0xf47001ff 2666#define EQUAI1 REGx(R0900_P1_EQUAI1)
2667#define F0900_P1_EQUA_ACCI1 0xf47001ff
2627 2668
2628/*P1_EQUAQ1*/ 2669/*P1_EQUAQ1*/
2629#define R0900_P1_EQUAQ1 0xf471 2670#define R0900_P1_EQUAQ1 0xf471
2630#define F0900_P1_EQUA_ACCQ1 0xf47101ff 2671#define EQUAQ1 REGx(R0900_P1_EQUAQ1)
2672#define F0900_P1_EQUA_ACCQ1 0xf47101ff
2631 2673
2632/*P1_EQUAI2*/ 2674/*P1_EQUAI2*/
2633#define R0900_P1_EQUAI2 0xf472 2675#define R0900_P1_EQUAI2 0xf472
2634#define F0900_P1_EQUA_ACCI2 0xf47201ff 2676#define EQUAI2 REGx(R0900_P1_EQUAI2)
2677#define F0900_P1_EQUA_ACCI2 0xf47201ff
2635 2678
2636/*P1_EQUAQ2*/ 2679/*P1_EQUAQ2*/
2637#define R0900_P1_EQUAQ2 0xf473 2680#define R0900_P1_EQUAQ2 0xf473
2638#define F0900_P1_EQUA_ACCQ2 0xf47301ff 2681#define EQUAQ2 REGx(R0900_P1_EQUAQ2)
2682#define F0900_P1_EQUA_ACCQ2 0xf47301ff
2639 2683
2640/*P1_EQUAI3*/ 2684/*P1_EQUAI3*/
2641#define R0900_P1_EQUAI3 0xf474 2685#define R0900_P1_EQUAI3 0xf474
2642#define F0900_P1_EQUA_ACCI3 0xf47401ff 2686#define EQUAI3 REGx(R0900_P1_EQUAI3)
2687#define F0900_P1_EQUA_ACCI3 0xf47401ff
2643 2688
2644/*P1_EQUAQ3*/ 2689/*P1_EQUAQ3*/
2645#define R0900_P1_EQUAQ3 0xf475 2690#define R0900_P1_EQUAQ3 0xf475
2646#define F0900_P1_EQUA_ACCQ3 0xf47501ff 2691#define EQUAQ3 REGx(R0900_P1_EQUAQ3)
2692#define F0900_P1_EQUA_ACCQ3 0xf47501ff
2647 2693
2648/*P1_EQUAI4*/ 2694/*P1_EQUAI4*/
2649#define R0900_P1_EQUAI4 0xf476 2695#define R0900_P1_EQUAI4 0xf476
2650#define F0900_P1_EQUA_ACCI4 0xf47601ff 2696#define EQUAI4 REGx(R0900_P1_EQUAI4)
2697#define F0900_P1_EQUA_ACCI4 0xf47601ff
2651 2698
2652/*P1_EQUAQ4*/ 2699/*P1_EQUAQ4*/
2653#define R0900_P1_EQUAQ4 0xf477 2700#define R0900_P1_EQUAQ4 0xf477
2654#define F0900_P1_EQUA_ACCQ4 0xf47701ff 2701#define EQUAQ4 REGx(R0900_P1_EQUAQ4)
2702#define F0900_P1_EQUA_ACCQ4 0xf47701ff
2655 2703
2656/*P1_EQUAI5*/ 2704/*P1_EQUAI5*/
2657#define R0900_P1_EQUAI5 0xf478 2705#define R0900_P1_EQUAI5 0xf478
2658#define F0900_P1_EQUA_ACCI5 0xf47801ff 2706#define EQUAI5 REGx(R0900_P1_EQUAI5)
2707#define F0900_P1_EQUA_ACCI5 0xf47801ff
2659 2708
2660/*P1_EQUAQ5*/ 2709/*P1_EQUAQ5*/
2661#define R0900_P1_EQUAQ5 0xf479 2710#define R0900_P1_EQUAQ5 0xf479
2662#define F0900_P1_EQUA_ACCQ5 0xf47901ff 2711#define EQUAQ5 REGx(R0900_P1_EQUAQ5)
2712#define F0900_P1_EQUA_ACCQ5 0xf47901ff
2663 2713
2664/*P1_EQUAI6*/ 2714/*P1_EQUAI6*/
2665#define R0900_P1_EQUAI6 0xf47a 2715#define R0900_P1_EQUAI6 0xf47a
2666#define F0900_P1_EQUA_ACCI6 0xf47a01ff 2716#define EQUAI6 REGx(R0900_P1_EQUAI6)
2717#define F0900_P1_EQUA_ACCI6 0xf47a01ff
2667 2718
2668/*P1_EQUAQ6*/ 2719/*P1_EQUAQ6*/
2669#define R0900_P1_EQUAQ6 0xf47b 2720#define R0900_P1_EQUAQ6 0xf47b
2670#define F0900_P1_EQUA_ACCQ6 0xf47b01ff 2721#define EQUAQ6 REGx(R0900_P1_EQUAQ6)
2722#define F0900_P1_EQUA_ACCQ6 0xf47b01ff
2671 2723
2672/*P1_EQUAI7*/ 2724/*P1_EQUAI7*/
2673#define R0900_P1_EQUAI7 0xf47c 2725#define R0900_P1_EQUAI7 0xf47c
2674#define F0900_P1_EQUA_ACCI7 0xf47c01ff 2726#define EQUAI7 REGx(R0900_P1_EQUAI7)
2727#define F0900_P1_EQUA_ACCI7 0xf47c01ff
2675 2728
2676/*P1_EQUAQ7*/ 2729/*P1_EQUAQ7*/
2677#define R0900_P1_EQUAQ7 0xf47d 2730#define R0900_P1_EQUAQ7 0xf47d
2678#define F0900_P1_EQUA_ACCQ7 0xf47d01ff 2731#define EQUAQ7 REGx(R0900_P1_EQUAQ7)
2732#define F0900_P1_EQUA_ACCQ7 0xf47d01ff
2679 2733
2680/*P1_EQUAI8*/ 2734/*P1_EQUAI8*/
2681#define R0900_P1_EQUAI8 0xf47e 2735#define R0900_P1_EQUAI8 0xf47e
2682#define F0900_P1_EQUA_ACCI8 0xf47e01ff 2736#define EQUAI8 REGx(R0900_P1_EQUAI8)
2737#define F0900_P1_EQUA_ACCI8 0xf47e01ff
2683 2738
2684/*P1_EQUAQ8*/ 2739/*P1_EQUAQ8*/
2685#define R0900_P1_EQUAQ8 0xf47f 2740#define R0900_P1_EQUAQ8 0xf47f
2686#define F0900_P1_EQUA_ACCQ8 0xf47f01ff 2741#define EQUAQ8 REGx(R0900_P1_EQUAQ8)
2742#define F0900_P1_EQUA_ACCQ8 0xf47f01ff
2687 2743
2688/*P1_NNOSDATAT1*/ 2744/*P1_NNOSDATAT1*/
2689#define R0900_P1_NNOSDATAT1 0xf480 2745#define R0900_P1_NNOSDATAT1 0xf480
2690#define F0900_P1_NOSDATAT_NORMED1 0xf48000ff 2746#define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1)
2747#define F0900_P1_NOSDATAT_NORMED1 0xf48000ff
2748#define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1)
2691 2749
2692/*P1_NNOSDATAT0*/ 2750/*P1_NNOSDATAT0*/
2693#define R0900_P1_NNOSDATAT0 0xf481 2751#define R0900_P1_NNOSDATAT0 0xf481
2694#define F0900_P1_NOSDATAT_NORMED0 0xf48100ff 2752#define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0)
2753#define F0900_P1_NOSDATAT_NORMED0 0xf48100ff
2754#define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0)
2695 2755
2696/*P1_NNOSDATA1*/ 2756/*P1_NNOSDATA1*/
2697#define R0900_P1_NNOSDATA1 0xf482 2757#define R0900_P1_NNOSDATA1 0xf482
2698#define F0900_P1_NOSDATA_NORMED1 0xf48200ff 2758#define NNOSDATA1 REGx(R0900_P1_NNOSDATA1)
2759#define F0900_P1_NOSDATA_NORMED1 0xf48200ff
2699 2760
2700/*P1_NNOSDATA0*/ 2761/*P1_NNOSDATA0*/
2701#define R0900_P1_NNOSDATA0 0xf483 2762#define R0900_P1_NNOSDATA0 0xf483
2702#define F0900_P1_NOSDATA_NORMED0 0xf48300ff 2763#define NNOSDATA0 REGx(R0900_P1_NNOSDATA0)
2764#define F0900_P1_NOSDATA_NORMED0 0xf48300ff
2703 2765
2704/*P1_NNOSPLHT1*/ 2766/*P1_NNOSPLHT1*/
2705#define R0900_P1_NNOSPLHT1 0xf484 2767#define R0900_P1_NNOSPLHT1 0xf484
2706#define F0900_P1_NOSPLHT_NORMED1 0xf48400ff 2768#define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1)
2769#define F0900_P1_NOSPLHT_NORMED1 0xf48400ff
2770#define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1)
2707 2771
2708/*P1_NNOSPLHT0*/ 2772/*P1_NNOSPLHT0*/
2709#define R0900_P1_NNOSPLHT0 0xf485 2773#define R0900_P1_NNOSPLHT0 0xf485
2710#define F0900_P1_NOSPLHT_NORMED0 0xf48500ff 2774#define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0)
2775#define F0900_P1_NOSPLHT_NORMED0 0xf48500ff
2776#define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0)
2711 2777
2712/*P1_NNOSPLH1*/ 2778/*P1_NNOSPLH1*/
2713#define R0900_P1_NNOSPLH1 0xf486 2779#define R0900_P1_NNOSPLH1 0xf486
2714#define F0900_P1_NOSPLH_NORMED1 0xf48600ff 2780#define NNOSPLH1 REGx(R0900_P1_NNOSPLH1)
2781#define F0900_P1_NOSPLH_NORMED1 0xf48600ff
2715 2782
2716/*P1_NNOSPLH0*/ 2783/*P1_NNOSPLH0*/
2717#define R0900_P1_NNOSPLH0 0xf487 2784#define R0900_P1_NNOSPLH0 0xf487
2718#define F0900_P1_NOSPLH_NORMED0 0xf48700ff 2785#define NNOSPLH0 REGx(R0900_P1_NNOSPLH0)
2786#define F0900_P1_NOSPLH_NORMED0 0xf48700ff
2719 2787
2720/*P1_NOSDATAT1*/ 2788/*P1_NOSDATAT1*/
2721#define R0900_P1_NOSDATAT1 0xf488 2789#define R0900_P1_NOSDATAT1 0xf488
2722#define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff 2790#define NOSDATAT1 REGx(R0900_P1_NOSDATAT1)
2791#define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff
2723 2792
2724/*P1_NOSDATAT0*/ 2793/*P1_NOSDATAT0*/
2725#define R0900_P1_NOSDATAT0 0xf489 2794#define R0900_P1_NOSDATAT0 0xf489
2726#define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff 2795#define NOSDATAT0 REGx(R0900_P1_NOSDATAT0)
2796#define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff
2727 2797
2728/*P1_NOSDATA1*/ 2798/*P1_NOSDATA1*/
2729#define R0900_P1_NOSDATA1 0xf48a 2799#define R0900_P1_NOSDATA1 0xf48a
2730#define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff 2800#define NOSDATA1 REGx(R0900_P1_NOSDATA1)
2801#define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff
2731 2802
2732/*P1_NOSDATA0*/ 2803/*P1_NOSDATA0*/
2733#define R0900_P1_NOSDATA0 0xf48b 2804#define R0900_P1_NOSDATA0 0xf48b
2734#define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff 2805#define NOSDATA0 REGx(R0900_P1_NOSDATA0)
2806#define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff
2735 2807
2736/*P1_NOSPLHT1*/ 2808/*P1_NOSPLHT1*/
2737#define R0900_P1_NOSPLHT1 0xf48c 2809#define R0900_P1_NOSPLHT1 0xf48c
2738#define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff 2810#define NOSPLHT1 REGx(R0900_P1_NOSPLHT1)
2811#define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff
2739 2812
2740/*P1_NOSPLHT0*/ 2813/*P1_NOSPLHT0*/
2741#define R0900_P1_NOSPLHT0 0xf48d 2814#define R0900_P1_NOSPLHT0 0xf48d
2742#define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff 2815#define NOSPLHT0 REGx(R0900_P1_NOSPLHT0)
2816#define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff
2743 2817
2744/*P1_NOSPLH1*/ 2818/*P1_NOSPLH1*/
2745#define R0900_P1_NOSPLH1 0xf48e 2819#define R0900_P1_NOSPLH1 0xf48e
2746#define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff 2820#define NOSPLH1 REGx(R0900_P1_NOSPLH1)
2821#define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff
2747 2822
2748/*P1_NOSPLH0*/ 2823/*P1_NOSPLH0*/
2749#define R0900_P1_NOSPLH0 0xf48f 2824#define R0900_P1_NOSPLH0 0xf48f
2750#define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff 2825#define NOSPLH0 REGx(R0900_P1_NOSPLH0)
2826#define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff
2751 2827
2752/*P1_CAR2CFG*/ 2828/*P1_CAR2CFG*/
2753#define R0900_P1_CAR2CFG 0xf490 2829#define R0900_P1_CAR2CFG 0xf490
2754#define F0900_P1_DESCRAMB_OFF 0xf4900080 2830#define CAR2CFG REGx(R0900_P1_CAR2CFG)
2755#define F0900_P1_PN4_SELECT 0xf4900040 2831#define F0900_P1_CARRIER3_DISABLE 0xf4900040
2756#define F0900_P1_CFR2_STOPDVBS1 0xf4900020 2832#define F0900_P1_ROTA2ON 0xf4900004
2757#define F0900_P1_STOP_CFR2UPDATE 0xf4900010 2833#define F0900_P1_PH_DET_ALGO2 0xf4900003
2758#define F0900_P1_STOP_NCO2UPDATE 0xf4900008 2834
2759#define F0900_P1_ROTA2ON 0xf4900004 2835/*P1_CFR2CFR1*/
2760#define F0900_P1_PH_DET_ALGO2 0xf4900003 2836#define R0900_P1_CFR2CFR1 0xf491
2761 2837#define CFR2CFR1 REGx(R0900_P1_CFR2CFR1)
2762/*P1_ACLC2*/ 2838#define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0
2763#define R0900_P1_ACLC2 0xf491 2839#define F0900_P1_EN_S2CAR2CENTER 0xf4910020
2764#define F0900_P1_CAR2_PUNCT_ADERAT 0xf4910040 2840#define F0900_P1_DIS_BCHERRCFR2 0xf4910010
2765#define F0900_P1_CAR2_ALPHA_MANT 0xf4910030 2841#define F0900_P1_CFR2TOCFR1_BETA 0xf4910007
2766#define F0900_P1_CAR2_ALPHA_EXP 0xf491000f
2767
2768/*P1_BCLC2*/
2769#define R0900_P1_BCLC2 0xf492
2770#define F0900_P1_DVBS2_NIP 0xf4920080
2771#define F0900_P1_CAR2_PUNCT_BDERAT 0xf4920040
2772#define F0900_P1_CAR2_BETA_MANT 0xf4920030
2773#define F0900_P1_CAR2_BETA_EXP 0xf492000f
2774 2842
2775/*P1_CFR22*/ 2843/*P1_CFR22*/
2776#define R0900_P1_CFR22 0xf493 2844#define R0900_P1_CFR22 0xf493
2777#define F0900_P1_CAR2_FREQ2 0xf49301ff 2845#define CFR22 REGx(R0900_P1_CFR22)
2846#define F0900_P1_CAR2_FREQ2 0xf49301ff
2778 2847
2779/*P1_CFR21*/ 2848/*P1_CFR21*/
2780#define R0900_P1_CFR21 0xf494 2849#define R0900_P1_CFR21 0xf494
2781#define F0900_P1_CAR2_FREQ1 0xf49400ff 2850#define CFR21 REGx(R0900_P1_CFR21)
2851#define F0900_P1_CAR2_FREQ1 0xf49400ff
2782 2852
2783/*P1_CFR20*/ 2853/*P1_CFR20*/
2784#define R0900_P1_CFR20 0xf495 2854#define R0900_P1_CFR20 0xf495
2785#define F0900_P1_CAR2_FREQ0 0xf49500ff 2855#define CFR20 REGx(R0900_P1_CFR20)
2856#define F0900_P1_CAR2_FREQ0 0xf49500ff
2786 2857
2787/*P1_ACLC2S2Q*/ 2858/*P1_ACLC2S2Q*/
2788#define R0900_P1_ACLC2S2Q 0xf497 2859#define R0900_P1_ACLC2S2Q 0xf497
2789#define F0900_P1_ENAB_SPSKSYMB 0xf4970080 2860#define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q)
2790#define F0900_P1_CAR2S2_QADERAT 0xf4970040 2861#define F0900_P1_ENAB_SPSKSYMB 0xf4970080
2791#define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030 2862#define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030
2792#define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f 2863#define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f
2793 2864
2794/*P1_ACLC2S28*/ 2865/*P1_ACLC2S28*/
2795#define R0900_P1_ACLC2S28 0xf498 2866#define R0900_P1_ACLC2S28 0xf498
2796#define F0900_P1_OLDI3Q_MODE 0xf4980080 2867#define ACLC2S28 REGx(R0900_P1_ACLC2S28)
2797#define F0900_P1_CAR2S2_8ADERAT 0xf4980040 2868#define F0900_P1_OLDI3Q_MODE 0xf4980080
2798#define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030 2869#define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030
2799#define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f 2870#define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f
2800 2871
2801/*P1_ACLC2S216A*/ 2872/*P1_ACLC2S216A*/
2802#define R0900_P1_ACLC2S216A 0xf499 2873#define R0900_P1_ACLC2S216A 0xf499
2803#define F0900_P1_CAR2S2_16ADERAT 0xf4990040 2874#define ACLC2S216A REGx(R0900_P1_ACLC2S216A)
2804#define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030 2875#define F0900_P1_DIS_C3STOPA2 0xf4990080
2805#define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f 2876#define F0900_P1_CAR2S2_16ADERAT 0xf4990040
2877#define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030
2878#define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f
2806 2879
2807/*P1_ACLC2S232A*/ 2880/*P1_ACLC2S232A*/
2808#define R0900_P1_ACLC2S232A 0xf49a 2881#define R0900_P1_ACLC2S232A 0xf49a
2809#define F0900_P1_CAR2S2_32ADERAT 0xf49a0040 2882#define ACLC2S232A REGx(R0900_P1_ACLC2S232A)
2810#define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030 2883#define F0900_P1_CAR2S2_32ADERAT 0xf49a0040
2811#define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f 2884#define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030
2885#define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f
2812 2886
2813/*P1_BCLC2S2Q*/ 2887/*P1_BCLC2S2Q*/
2814#define R0900_P1_BCLC2S2Q 0xf49c 2888#define R0900_P1_BCLC2S2Q 0xf49c
2815#define F0900_P1_DVBS2S2Q_NIP 0xf49c0080 2889#define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q)
2816#define F0900_P1_CAR2S2_QBDERAT 0xf49c0040 2890#define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030
2817#define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030 2891#define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f
2818#define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f
2819 2892
2820/*P1_BCLC2S28*/ 2893/*P1_BCLC2S28*/
2821#define R0900_P1_BCLC2S28 0xf49d 2894#define R0900_P1_BCLC2S28 0xf49d
2822#define F0900_P1_DVBS2S28_NIP 0xf49d0080 2895#define BCLC2S28 REGx(R0900_P1_BCLC2S28)
2823#define F0900_P1_CAR2S2_8BDERAT 0xf49d0040 2896#define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030
2824#define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030 2897#define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f
2825#define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f
2826 2898
2827/*P1_BCLC2S216A*/ 2899/*P1_BCLC2S216A*/
2828#define R0900_P1_BCLC2S216A 0xf49e 2900#define R0900_P1_BCLC2S216A 0xf49e
2829#define F0900_P1_DVBS2S216A_NIP 0xf49e0080 2901#define BCLC2S216A REGx(R0900_P1_BCLC2S216A)
2830#define F0900_P1_CAR2S2_16BDERAT 0xf49e0040
2831#define F0900_P1_CAR2S2_16A_BETA_M 0xf49e0030
2832#define F0900_P1_CAR2S2_16A_BETA_E 0xf49e000f
2833 2902
2834/*P1_BCLC2S232A*/ 2903/*P1_BCLC2S232A*/
2835#define R0900_P1_BCLC2S232A 0xf49f 2904#define R0900_P1_BCLC2S232A 0xf49f
2836#define F0900_P1_DVBS2S232A_NIP 0xf49f0080 2905#define BCLC2S232A REGx(R0900_P1_BCLC2S232A)
2837#define F0900_P1_CAR2S2_32BDERAT 0xf49f0040
2838#define F0900_P1_CAR2S2_32A_BETA_M 0xf49f0030
2839#define F0900_P1_CAR2S2_32A_BETA_E 0xf49f000f
2840 2906
2841/*P1_PLROOT2*/ 2907/*P1_PLROOT2*/
2842#define R0900_P1_PLROOT2 0xf4ac 2908#define R0900_P1_PLROOT2 0xf4ac
2843#define F0900_P1_SHORTFR_DISABLE 0xf4ac0080 2909#define PLROOT2 REGx(R0900_P1_PLROOT2)
2844#define F0900_P1_LONGFR_DISABLE 0xf4ac0040 2910#define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
2845#define F0900_P1_DUMMYPL_DISABLE 0xf4ac0020 2911#define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003
2846#define F0900_P1_SHORTFR_AVOID 0xf4ac0010
2847#define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
2848#define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003
2849 2912
2850/*P1_PLROOT1*/ 2913/*P1_PLROOT1*/
2851#define R0900_P1_PLROOT1 0xf4ad 2914#define R0900_P1_PLROOT1 0xf4ad
2852#define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff 2915#define PLROOT1 REGx(R0900_P1_PLROOT1)
2916#define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff
2853 2917
2854/*P1_PLROOT0*/ 2918/*P1_PLROOT0*/
2855#define R0900_P1_PLROOT0 0xf4ae 2919#define R0900_P1_PLROOT0 0xf4ae
2856#define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff 2920#define PLROOT0 REGx(R0900_P1_PLROOT0)
2921#define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff
2857 2922
2858/*P1_MODCODLST0*/ 2923/*P1_MODCODLST0*/
2859#define R0900_P1_MODCODLST0 0xf4b0 2924#define R0900_P1_MODCODLST0 0xf4b0
2860#define F0900_P1_EN_TOKEN31 0xf4b00080 2925#define MODCODLST0 REGx(R0900_P1_MODCODLST0)
2861#define F0900_P1_SYNCTAG_SELECT 0xf4b00040
2862#define F0900_P1_MODCODRQ_MODE 0xf4b00030
2863 2926
2864/*P1_MODCODLST1*/ 2927/*P1_MODCODLST1*/
2865#define R0900_P1_MODCODLST1 0xf4b1 2928#define R0900_P1_MODCODLST1 0xf4b1
2866#define F0900_P1_DIS_MODCOD29 0xf4b100f0 2929#define MODCODLST1 REGx(R0900_P1_MODCODLST1)
2867#define F0900_P1_DIS_32PSK_9_10 0xf4b1000f 2930#define F0900_P1_DIS_MODCOD29 0xf4b100f0
2931#define F0900_P1_DIS_32PSK_9_10 0xf4b1000f
2868 2932
2869/*P1_MODCODLST2*/ 2933/*P1_MODCODLST2*/
2870#define R0900_P1_MODCODLST2 0xf4b2 2934#define R0900_P1_MODCODLST2 0xf4b2
2871#define F0900_P1_DIS_32PSK_8_9 0xf4b200f0 2935#define MODCODLST2 REGx(R0900_P1_MODCODLST2)
2872#define F0900_P1_DIS_32PSK_5_6 0xf4b2000f 2936#define F0900_P1_DIS_32PSK_8_9 0xf4b200f0
2937#define F0900_P1_DIS_32PSK_5_6 0xf4b2000f
2873 2938
2874/*P1_MODCODLST3*/ 2939/*P1_MODCODLST3*/
2875#define R0900_P1_MODCODLST3 0xf4b3 2940#define R0900_P1_MODCODLST3 0xf4b3
2876#define F0900_P1_DIS_32PSK_4_5 0xf4b300f0 2941#define MODCODLST3 REGx(R0900_P1_MODCODLST3)
2877#define F0900_P1_DIS_32PSK_3_4 0xf4b3000f 2942#define F0900_P1_DIS_32PSK_4_5 0xf4b300f0
2943#define F0900_P1_DIS_32PSK_3_4 0xf4b3000f
2878 2944
2879/*P1_MODCODLST4*/ 2945/*P1_MODCODLST4*/
2880#define R0900_P1_MODCODLST4 0xf4b4 2946#define R0900_P1_MODCODLST4 0xf4b4
2881#define F0900_P1_DIS_16PSK_9_10 0xf4b400f0 2947#define MODCODLST4 REGx(R0900_P1_MODCODLST4)
2882#define F0900_P1_DIS_16PSK_8_9 0xf4b4000f 2948#define F0900_P1_DIS_16PSK_9_10 0xf4b400f0
2949#define F0900_P1_DIS_16PSK_8_9 0xf4b4000f
2883 2950
2884/*P1_MODCODLST5*/ 2951/*P1_MODCODLST5*/
2885#define R0900_P1_MODCODLST5 0xf4b5 2952#define R0900_P1_MODCODLST5 0xf4b5
2886#define F0900_P1_DIS_16PSK_5_6 0xf4b500f0 2953#define MODCODLST5 REGx(R0900_P1_MODCODLST5)
2887#define F0900_P1_DIS_16PSK_4_5 0xf4b5000f 2954#define F0900_P1_DIS_16PSK_5_6 0xf4b500f0
2955#define F0900_P1_DIS_16PSK_4_5 0xf4b5000f
2888 2956
2889/*P1_MODCODLST6*/ 2957/*P1_MODCODLST6*/
2890#define R0900_P1_MODCODLST6 0xf4b6 2958#define R0900_P1_MODCODLST6 0xf4b6
2891#define F0900_P1_DIS_16PSK_3_4 0xf4b600f0 2959#define MODCODLST6 REGx(R0900_P1_MODCODLST6)
2892#define F0900_P1_DIS_16PSK_2_3 0xf4b6000f 2960#define F0900_P1_DIS_16PSK_3_4 0xf4b600f0
2961#define F0900_P1_DIS_16PSK_2_3 0xf4b6000f
2893 2962
2894/*P1_MODCODLST7*/ 2963/*P1_MODCODLST7*/
2895#define R0900_P1_MODCODLST7 0xf4b7 2964#define R0900_P1_MODCODLST7 0xf4b7
2896#define F0900_P1_DIS_8P_9_10 0xf4b700f0 2965#define MODCODLST7 REGx(R0900_P1_MODCODLST7)
2897#define F0900_P1_DIS_8P_8_9 0xf4b7000f 2966#define F0900_P1_DIS_8P_9_10 0xf4b700f0
2967#define F0900_P1_DIS_8P_8_9 0xf4b7000f
2898 2968
2899/*P1_MODCODLST8*/ 2969/*P1_MODCODLST8*/
2900#define R0900_P1_MODCODLST8 0xf4b8 2970#define R0900_P1_MODCODLST8 0xf4b8
2901#define F0900_P1_DIS_8P_5_6 0xf4b800f0 2971#define MODCODLST8 REGx(R0900_P1_MODCODLST8)
2902#define F0900_P1_DIS_8P_3_4 0xf4b8000f 2972#define F0900_P1_DIS_8P_5_6 0xf4b800f0
2973#define F0900_P1_DIS_8P_3_4 0xf4b8000f
2903 2974
2904/*P1_MODCODLST9*/ 2975/*P1_MODCODLST9*/
2905#define R0900_P1_MODCODLST9 0xf4b9 2976#define R0900_P1_MODCODLST9 0xf4b9
2906#define F0900_P1_DIS_8P_2_3 0xf4b900f0 2977#define MODCODLST9 REGx(R0900_P1_MODCODLST9)
2907#define F0900_P1_DIS_8P_3_5 0xf4b9000f 2978#define F0900_P1_DIS_8P_2_3 0xf4b900f0
2979#define F0900_P1_DIS_8P_3_5 0xf4b9000f
2908 2980
2909/*P1_MODCODLSTA*/ 2981/*P1_MODCODLSTA*/
2910#define R0900_P1_MODCODLSTA 0xf4ba 2982#define R0900_P1_MODCODLSTA 0xf4ba
2911#define F0900_P1_DIS_QP_9_10 0xf4ba00f0 2983#define MODCODLSTA REGx(R0900_P1_MODCODLSTA)
2912#define F0900_P1_DIS_QP_8_9 0xf4ba000f 2984#define F0900_P1_DIS_QP_9_10 0xf4ba00f0
2985#define F0900_P1_DIS_QP_8_9 0xf4ba000f
2913 2986
2914/*P1_MODCODLSTB*/ 2987/*P1_MODCODLSTB*/
2915#define R0900_P1_MODCODLSTB 0xf4bb 2988#define R0900_P1_MODCODLSTB 0xf4bb
2916#define F0900_P1_DIS_QP_5_6 0xf4bb00f0 2989#define MODCODLSTB REGx(R0900_P1_MODCODLSTB)
2917#define F0900_P1_DIS_QP_4_5 0xf4bb000f 2990#define F0900_P1_DIS_QP_5_6 0xf4bb00f0
2991#define F0900_P1_DIS_QP_4_5 0xf4bb000f
2918 2992
2919/*P1_MODCODLSTC*/ 2993/*P1_MODCODLSTC*/
2920#define R0900_P1_MODCODLSTC 0xf4bc 2994#define R0900_P1_MODCODLSTC 0xf4bc
2921#define F0900_P1_DIS_QP_3_4 0xf4bc00f0 2995#define MODCODLSTC REGx(R0900_P1_MODCODLSTC)
2922#define F0900_P1_DIS_QP_2_3 0xf4bc000f 2996#define F0900_P1_DIS_QP_3_4 0xf4bc00f0
2997#define F0900_P1_DIS_QP_2_3 0xf4bc000f
2923 2998
2924/*P1_MODCODLSTD*/ 2999/*P1_MODCODLSTD*/
2925#define R0900_P1_MODCODLSTD 0xf4bd 3000#define R0900_P1_MODCODLSTD 0xf4bd
2926#define F0900_P1_DIS_QP_3_5 0xf4bd00f0 3001#define MODCODLSTD REGx(R0900_P1_MODCODLSTD)
2927#define F0900_P1_DIS_QP_1_2 0xf4bd000f 3002#define F0900_P1_DIS_QP_3_5 0xf4bd00f0
3003#define F0900_P1_DIS_QP_1_2 0xf4bd000f
2928 3004
2929/*P1_MODCODLSTE*/ 3005/*P1_MODCODLSTE*/
2930#define R0900_P1_MODCODLSTE 0xf4be 3006#define R0900_P1_MODCODLSTE 0xf4be
2931#define F0900_P1_DIS_QP_2_5 0xf4be00f0 3007#define MODCODLSTE REGx(R0900_P1_MODCODLSTE)
2932#define F0900_P1_DIS_QP_1_3 0xf4be000f 3008#define F0900_P1_DIS_QP_2_5 0xf4be00f0
3009#define F0900_P1_DIS_QP_1_3 0xf4be000f
2933 3010
2934/*P1_MODCODLSTF*/ 3011/*P1_MODCODLSTF*/
2935#define R0900_P1_MODCODLSTF 0xf4bf 3012#define R0900_P1_MODCODLSTF 0xf4bf
2936#define F0900_P1_DIS_QP_1_4 0xf4bf00f0 3013#define MODCODLSTF REGx(R0900_P1_MODCODLSTF)
2937#define F0900_P1_DDEMOD_SET 0xf4bf0002 3014#define F0900_P1_DIS_QP_1_4 0xf4bf00f0
2938#define F0900_P1_DDEMOD_MASK 0xf4bf0001 3015
3016/*P1_GAUSSR0*/
3017#define R0900_P1_GAUSSR0 0xf4c0
3018#define GAUSSR0 REGx(R0900_P1_GAUSSR0)
3019#define F0900_P1_EN_CCIMODE 0xf4c00080
3020#define F0900_P1_R0_GAUSSIEN 0xf4c0007f
3021
3022/*P1_CCIR0*/
3023#define R0900_P1_CCIR0 0xf4c1
3024#define CCIR0 REGx(R0900_P1_CCIR0)
3025#define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080
3026#define F0900_P1_R0_CCI 0xf4c1007f
3027
3028/*P1_CCIQUANT*/
3029#define R0900_P1_CCIQUANT 0xf4c2
3030#define CCIQUANT REGx(R0900_P1_CCIQUANT)
3031#define F0900_P1_CCI_BETA 0xf4c200e0
3032#define F0900_P1_CCI_QUANT 0xf4c2001f
3033
3034/*P1_CCITHRES*/
3035#define R0900_P1_CCITHRES 0xf4c3
3036#define CCITHRES REGx(R0900_P1_CCITHRES)
3037#define F0900_P1_CCI_THRESHOLD 0xf4c300ff
3038
3039/*P1_CCIACC*/
3040#define R0900_P1_CCIACC 0xf4c4
3041#define CCIACC REGx(R0900_P1_CCIACC)
3042#define F0900_P1_CCI_VALUE 0xf4c400ff
2939 3043
2940/*P1_DMDRESCFG*/ 3044/*P1_DMDRESCFG*/
2941#define R0900_P1_DMDRESCFG 0xf4c6 3045#define R0900_P1_DMDRESCFG 0xf4c6
2942#define F0900_P1_DMDRES_RESET 0xf4c60080 3046#define DMDRESCFG REGx(R0900_P1_DMDRESCFG)
2943#define F0900_P1_DMDRES_NOISESQR 0xf4c60010 3047#define F0900_P1_DMDRES_RESET 0xf4c60080
2944#define F0900_P1_DMDRES_STRALL 0xf4c60008 3048#define F0900_P1_DMDRES_STRALL 0xf4c60008
2945#define F0900_P1_DMDRES_NEWONLY 0xf4c60004 3049#define F0900_P1_DMDRES_NEWONLY 0xf4c60004
2946#define F0900_P1_DMDRES_NOSTORE 0xf4c60002 3050#define F0900_P1_DMDRES_NOSTORE 0xf4c60002
2947#define F0900_P1_DMDRES_AGC2MEM 0xf4c60001
2948 3051
2949/*P1_DMDRESADR*/ 3052/*P1_DMDRESADR*/
2950#define R0900_P1_DMDRESADR 0xf4c7 3053#define R0900_P1_DMDRESADR 0xf4c7
2951#define F0900_P1_SUSP_PREDCANAL 0xf4c70080 3054#define DMDRESADR REGx(R0900_P1_DMDRESADR)
2952#define F0900_P1_DMDRES_VALIDCFR 0xf4c70040 3055#define F0900_P1_DMDRES_VALIDCFR 0xf4c70040
2953#define F0900_P1_DMDRES_MEMFULL 0xf4c70030 3056#define F0900_P1_DMDRES_MEMFULL 0xf4c70030
2954#define F0900_P1_DMDRES_RESNBR 0xf4c7000f 3057#define F0900_P1_DMDRES_RESNBR 0xf4c7000f
2955 3058
2956/*P1_DMDRESDATA7*/ 3059/*P1_DMDRESDATA7*/
2957#define R0900_P1_DMDRESDATA7 0xf4c8 3060#define R0900_P1_DMDRESDATA7 0xf4c8
2958#define F0900_P1_DMDRES_DATA7 0xf4c800ff 3061#define F0900_P1_DMDRES_DATA7 0xf4c800ff
2959 3062
2960/*P1_DMDRESDATA6*/ 3063/*P1_DMDRESDATA6*/
2961#define R0900_P1_DMDRESDATA6 0xf4c9 3064#define R0900_P1_DMDRESDATA6 0xf4c9
2962#define F0900_P1_DMDRES_DATA6 0xf4c900ff 3065#define F0900_P1_DMDRES_DATA6 0xf4c900ff
2963 3066
2964/*P1_DMDRESDATA5*/ 3067/*P1_DMDRESDATA5*/
2965#define R0900_P1_DMDRESDATA5 0xf4ca 3068#define R0900_P1_DMDRESDATA5 0xf4ca
2966#define F0900_P1_DMDRES_DATA5 0xf4ca00ff 3069#define F0900_P1_DMDRES_DATA5 0xf4ca00ff
2967 3070
2968/*P1_DMDRESDATA4*/ 3071/*P1_DMDRESDATA4*/
2969#define R0900_P1_DMDRESDATA4 0xf4cb 3072#define R0900_P1_DMDRESDATA4 0xf4cb
2970#define F0900_P1_DMDRES_DATA4 0xf4cb00ff 3073#define F0900_P1_DMDRES_DATA4 0xf4cb00ff
2971 3074
2972/*P1_DMDRESDATA3*/ 3075/*P1_DMDRESDATA3*/
2973#define R0900_P1_DMDRESDATA3 0xf4cc 3076#define R0900_P1_DMDRESDATA3 0xf4cc
2974#define F0900_P1_DMDRES_DATA3 0xf4cc00ff 3077#define F0900_P1_DMDRES_DATA3 0xf4cc00ff
2975 3078
2976/*P1_DMDRESDATA2*/ 3079/*P1_DMDRESDATA2*/
2977#define R0900_P1_DMDRESDATA2 0xf4cd 3080#define R0900_P1_DMDRESDATA2 0xf4cd
2978#define F0900_P1_DMDRES_DATA2 0xf4cd00ff 3081#define F0900_P1_DMDRES_DATA2 0xf4cd00ff
2979 3082
2980/*P1_DMDRESDATA1*/ 3083/*P1_DMDRESDATA1*/
2981#define R0900_P1_DMDRESDATA1 0xf4ce 3084#define R0900_P1_DMDRESDATA1 0xf4ce
2982#define F0900_P1_DMDRES_DATA1 0xf4ce00ff 3085#define F0900_P1_DMDRES_DATA1 0xf4ce00ff
2983 3086
2984/*P1_DMDRESDATA0*/ 3087/*P1_DMDRESDATA0*/
2985#define R0900_P1_DMDRESDATA0 0xf4cf 3088#define R0900_P1_DMDRESDATA0 0xf4cf
2986#define F0900_P1_DMDRES_DATA0 0xf4cf00ff 3089#define F0900_P1_DMDRES_DATA0 0xf4cf00ff
2987 3090
2988/*P1_FFEI1*/ 3091/*P1_FFEI1*/
2989#define R0900_P1_FFEI1 0xf4d0 3092#define R0900_P1_FFEI1 0xf4d0
2990#define F0900_P1_FFE_ACCI1 0xf4d001ff 3093#define FFEI1 REGx(R0900_P1_FFEI1)
3094#define F0900_P1_FFE_ACCI1 0xf4d001ff
2991 3095
2992/*P1_FFEQ1*/ 3096/*P1_FFEQ1*/
2993#define R0900_P1_FFEQ1 0xf4d1 3097#define R0900_P1_FFEQ1 0xf4d1
2994#define F0900_P1_FFE_ACCQ1 0xf4d101ff 3098#define FFEQ1 REGx(R0900_P1_FFEQ1)
3099#define F0900_P1_FFE_ACCQ1 0xf4d101ff
2995 3100
2996/*P1_FFEI2*/ 3101/*P1_FFEI2*/
2997#define R0900_P1_FFEI2 0xf4d2 3102#define R0900_P1_FFEI2 0xf4d2
2998#define F0900_P1_FFE_ACCI2 0xf4d201ff 3103#define FFEI2 REGx(R0900_P1_FFEI2)
3104#define F0900_P1_FFE_ACCI2 0xf4d201ff
2999 3105
3000/*P1_FFEQ2*/ 3106/*P1_FFEQ2*/
3001#define R0900_P1_FFEQ2 0xf4d3 3107#define R0900_P1_FFEQ2 0xf4d3
3002#define F0900_P1_FFE_ACCQ2 0xf4d301ff 3108#define FFEQ2 REGx(R0900_P1_FFEQ2)
3109#define F0900_P1_FFE_ACCQ2 0xf4d301ff
3003 3110
3004/*P1_FFEI3*/ 3111/*P1_FFEI3*/
3005#define R0900_P1_FFEI3 0xf4d4 3112#define R0900_P1_FFEI3 0xf4d4
3006#define F0900_P1_FFE_ACCI3 0xf4d401ff 3113#define FFEI3 REGx(R0900_P1_FFEI3)
3114#define F0900_P1_FFE_ACCI3 0xf4d401ff
3007 3115
3008/*P1_FFEQ3*/ 3116/*P1_FFEQ3*/
3009#define R0900_P1_FFEQ3 0xf4d5 3117#define R0900_P1_FFEQ3 0xf4d5
3010#define F0900_P1_FFE_ACCQ3 0xf4d501ff 3118#define FFEQ3 REGx(R0900_P1_FFEQ3)
3119#define F0900_P1_FFE_ACCQ3 0xf4d501ff
3011 3120
3012/*P1_FFEI4*/ 3121/*P1_FFEI4*/
3013#define R0900_P1_FFEI4 0xf4d6 3122#define R0900_P1_FFEI4 0xf4d6
3014#define F0900_P1_FFE_ACCI4 0xf4d601ff 3123#define FFEI4 REGx(R0900_P1_FFEI4)
3124#define F0900_P1_FFE_ACCI4 0xf4d601ff
3015 3125
3016/*P1_FFEQ4*/ 3126/*P1_FFEQ4*/
3017#define R0900_P1_FFEQ4 0xf4d7 3127#define R0900_P1_FFEQ4 0xf4d7
3018#define F0900_P1_FFE_ACCQ4 0xf4d701ff 3128#define FFEQ4 REGx(R0900_P1_FFEQ4)
3129#define F0900_P1_FFE_ACCQ4 0xf4d701ff
3019 3130
3020/*P1_FFECFG*/ 3131/*P1_FFECFG*/
3021#define R0900_P1_FFECFG 0xf4d8 3132#define R0900_P1_FFECFG 0xf4d8
3022#define F0900_P1_EQUALFFE_ON 0xf4d80040 3133#define FFECFG REGx(R0900_P1_FFECFG)
3023#define F0900_P1_EQUAL_USEDSYMB 0xf4d80030 3134#define F0900_P1_EQUALFFE_ON 0xf4d80040
3024#define F0900_P1_MU_EQUALFFE 0xf4d80007 3135#define F0900_P1_MU_EQUALFFE 0xf4d80007
3025 3136
3026/*P1_TNRCFG*/ 3137/*P1_TNRCFG*/
3027#define R0900_P1_TNRCFG 0xf4e0 3138#define R0900_P1_TNRCFG 0xf4e0
3028#define F0900_P1_TUN_ACKFAIL 0xf4e00080 3139#define TNRCFG REGx(R0900_P1_TNRCFG)
3029#define F0900_P1_TUN_TYPE 0xf4e00070 3140#define F0900_P1_TUN_ACKFAIL 0xf4e00080
3030#define F0900_P1_TUN_SECSTOP 0xf4e00008 3141#define F0900_P1_TUN_TYPE 0xf4e00070
3031#define F0900_P1_TUN_VCOSRCH 0xf4e00004 3142#define F0900_P1_TUN_SECSTOP 0xf4e00008
3032#define F0900_P1_TUN_MADDRESS 0xf4e00003 3143#define F0900_P1_TUN_VCOSRCH 0xf4e00004
3144#define F0900_P1_TUN_MADDRESS 0xf4e00003
3033 3145
3034/*P1_TNRCFG2*/ 3146/*P1_TNRCFG2*/
3035#define R0900_P1_TNRCFG2 0xf4e1 3147#define R0900_P1_TNRCFG2 0xf4e1
3036#define F0900_P1_TUN_IQSWAP 0xf4e10080 3148#define TNRCFG2 REGx(R0900_P1_TNRCFG2)
3037#define F0900_P1_STB6110_STEP2MHZ 0xf4e10040 3149#define F0900_P1_TUN_IQSWAP 0xf4e10080
3038#define F0900_P1_STB6120_DBLI2C 0xf4e10020 3150#define F0900_P1_DIS_BWCALC 0xf4e10004
3039#define F0900_P1_DIS_FCCK 0xf4e10010 3151#define F0900_P1_SHORT_WAITSTATES 0xf4e10002
3040#define F0900_P1_DIS_LPEN 0xf4e10008
3041#define F0900_P1_DIS_BWCALC 0xf4e10004
3042#define F0900_P1_SHORT_WAITSTATES 0xf4e10002
3043#define F0900_P1_DIS_2BWAGC1 0xf4e10001
3044 3152
3045/*P1_TNRXTAL*/ 3153/*P1_TNRXTAL*/
3046#define R0900_P1_TNRXTAL 0xf4e4 3154#define R0900_P1_TNRXTAL 0xf4e4
3047#define F0900_P1_TUN_MCLKDECIMAL 0xf4e400e0 3155#define TNRXTAL REGx(R0900_P1_TNRXTAL)
3048#define F0900_P1_TUN_XTALFREQ 0xf4e4001f 3156#define F0900_P1_TUN_XTALFREQ 0xf4e4001f
3049 3157
3050/*P1_TNRSTEPS*/ 3158/*P1_TNRSTEPS*/
3051#define R0900_P1_TNRSTEPS 0xf4e7 3159#define R0900_P1_TNRSTEPS 0xf4e7
3052#define F0900_P1_TUNER_BW1P6 0xf4e70080 3160#define TNRSTEPS REGx(R0900_P1_TNRSTEPS)
3053#define F0900_P1_BWINC_OFFSET 0xf4e70070 3161#define F0900_P1_TUNER_BW0P125 0xf4e70080
3054#define F0900_P1_SOFTSTEP_RNG 0xf4e70008 3162#define F0900_P1_BWINC_OFFSET 0xf4e70170
3055#define F0900_P1_TUN_BWOFFSET 0xf4e70107 3163#define F0900_P1_SOFTSTEP_RNG 0xf4e70008
3164#define F0900_P1_TUN_BWOFFSET 0xf4e70007
3056 3165
3057/*P1_TNRGAIN*/ 3166/*P1_TNRGAIN*/
3058#define R0900_P1_TNRGAIN 0xf4e8 3167#define R0900_P1_TNRGAIN 0xf4e8
3059#define F0900_P1_TUN_KDIVEN 0xf4e800c0 3168#define TNRGAIN REGx(R0900_P1_TNRGAIN)
3060#define F0900_P1_STB6X00_OCK 0xf4e80030 3169#define F0900_P1_TUN_KDIVEN 0xf4e800c0
3061#define F0900_P1_TUN_GAIN 0xf4e8000f 3170#define F0900_P1_STB6X00_OCK 0xf4e80030
3171#define F0900_P1_TUN_GAIN 0xf4e8000f
3062 3172
3063/*P1_TNRRF1*/ 3173/*P1_TNRRF1*/
3064#define R0900_P1_TNRRF1 0xf4e9 3174#define R0900_P1_TNRRF1 0xf4e9
3065#define F0900_P1_TUN_RFFREQ2 0xf4e900ff 3175#define TNRRF1 REGx(R0900_P1_TNRRF1)
3176#define F0900_P1_TUN_RFFREQ2 0xf4e900ff
3066 3177
3067/*P1_TNRRF0*/ 3178/*P1_TNRRF0*/
3068#define R0900_P1_TNRRF0 0xf4ea 3179#define R0900_P1_TNRRF0 0xf4ea
3069#define F0900_P1_TUN_RFFREQ1 0xf4ea00ff 3180#define TNRRF0 REGx(R0900_P1_TNRRF0)
3181#define F0900_P1_TUN_RFFREQ1 0xf4ea00ff
3070 3182
3071/*P1_TNRBW*/ 3183/*P1_TNRBW*/
3072#define R0900_P1_TNRBW 0xf4eb 3184#define R0900_P1_TNRBW 0xf4eb
3073#define F0900_P1_TUN_RFFREQ0 0xf4eb00c0 3185#define TNRBW REGx(R0900_P1_TNRBW)
3074#define F0900_P1_TUN_BW 0xf4eb003f 3186#define F0900_P1_TUN_RFFREQ0 0xf4eb00c0
3187#define F0900_P1_TUN_BW 0xf4eb003f
3075 3188
3076/*P1_TNRADJ*/ 3189/*P1_TNRADJ*/
3077#define R0900_P1_TNRADJ 0xf4ec 3190#define R0900_P1_TNRADJ 0xf4ec
3078#define F0900_P1_STB61X0_RCLK 0xf4ec0080 3191#define TNRADJ REGx(R0900_P1_TNRADJ)
3079#define F0900_P1_STB61X0_CALTIME 0xf4ec0040 3192#define F0900_P1_STB61X0_CALTIME 0xf4ec0040
3080#define F0900_P1_STB6X00_DLB 0xf4ec0038
3081#define F0900_P1_STB6000_FCL 0xf4ec0007
3082 3193
3083/*P1_TNRCTL2*/ 3194/*P1_TNRCTL2*/
3084#define R0900_P1_TNRCTL2 0xf4ed 3195#define R0900_P1_TNRCTL2 0xf4ed
3085#define F0900_P1_STB61X0_LCP1_RCCKOFF 0xf4ed0080 3196#define TNRCTL2 REGx(R0900_P1_TNRCTL2)
3086#define F0900_P1_STB61X0_LCP0 0xf4ed0040 3197#define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080
3087#define F0900_P1_STB61X0_XTOUT_RFOUTS 0xf4ed0020 3198#define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040
3088#define F0900_P1_STB61X0_XTON_MCKDV 0xf4ed0010 3199#define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020
3089#define F0900_P1_STB61X0_CALOFF_DCOFF 0xf4ed0008 3200#define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010
3090#define F0900_P1_STB6110_LPT 0xf4ed0004 3201#define F0900_P1_STB61X0_CALOFF 0xf4ed0008
3091#define F0900_P1_STB6110_RX 0xf4ed0002 3202#define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004
3092#define F0900_P1_STB6110_SYN 0xf4ed0001 3203#define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002
3204#define F0900_P1_STB6XX0_SYN 0xf4ed0001
3093 3205
3094/*P1_TNRCFG3*/ 3206/*P1_TNRCFG3*/
3095#define R0900_P1_TNRCFG3 0xf4ee 3207#define R0900_P1_TNRCFG3 0xf4ee
3096#define F0900_P1_STB6120_DISCTRL1 0xf4ee0080 3208#define TNRCFG3 REGx(R0900_P1_TNRCFG3)
3097#define F0900_P1_STB6120_INVORDER 0xf4ee0040 3209#define F0900_P1_TUN_PLLFREQ 0xf4ee001c
3098#define F0900_P1_STB6120_ENCTRL6 0xf4ee0020 3210#define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003
3099#define F0900_P1_TUN_PLLFREQ 0xf4ee001c
3100#define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003
3101 3211
3102/*P1_TNRLAUNCH*/ 3212/*P1_TNRLAUNCH*/
3103#define R0900_P1_TNRLAUNCH 0xf4f0 3213#define R0900_P1_TNRLAUNCH 0xf4f0
3214#define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH)
3104 3215
3105/*P1_TNRLD*/ 3216/*P1_TNRLD*/
3106#define R0900_P1_TNRLD 0xf4f0 3217#define R0900_P1_TNRLD 0xf4f0
3107#define F0900_P1_TUNLD_VCOING 0xf4f00080 3218#define TNRLD REGx(R0900_P1_TNRLD)
3108#define F0900_P1_TUN_REG1FAIL 0xf4f00040 3219#define F0900_P1_TUNLD_VCOING 0xf4f00080
3109#define F0900_P1_TUN_REG2FAIL 0xf4f00020 3220#define F0900_P1_TUN_REG1FAIL 0xf4f00040
3110#define F0900_P1_TUN_REG3FAIL 0xf4f00010 3221#define F0900_P1_TUN_REG2FAIL 0xf4f00020
3111#define F0900_P1_TUN_REG4FAIL 0xf4f00008 3222#define F0900_P1_TUN_REG3FAIL 0xf4f00010
3112#define F0900_P1_TUN_REG5FAIL 0xf4f00004 3223#define F0900_P1_TUN_REG4FAIL 0xf4f00008
3113#define F0900_P1_TUN_BWING 0xf4f00002 3224#define F0900_P1_TUN_REG5FAIL 0xf4f00004
3114#define F0900_P1_TUN_LOCKED 0xf4f00001 3225#define F0900_P1_TUN_BWING 0xf4f00002
3226#define F0900_P1_TUN_LOCKED 0xf4f00001
3115 3227
3116/*P1_TNROBSL*/ 3228/*P1_TNROBSL*/
3117#define R0900_P1_TNROBSL 0xf4f6 3229#define R0900_P1_TNROBSL 0xf4f6
3118#define F0900_P1_TUN_I2CABORTED 0xf4f60080 3230#define TNROBSL REGx(R0900_P1_TNROBSL)
3119#define F0900_P1_TUN_LPEN 0xf4f60040 3231#define F0900_P1_TUN_I2CABORTED 0xf4f60080
3120#define F0900_P1_TUN_FCCK 0xf4f60020 3232#define F0900_P1_TUN_LPEN 0xf4f60040
3121#define F0900_P1_TUN_I2CLOCKED 0xf4f60010 3233#define F0900_P1_TUN_FCCK 0xf4f60020
3122#define F0900_P1_TUN_PROGDONE 0xf4f6000c 3234#define F0900_P1_TUN_I2CLOCKED 0xf4f60010
3123#define F0900_P1_TUN_RFRESTE1 0xf4f60003 3235#define F0900_P1_TUN_PROGDONE 0xf4f6000c
3236#define F0900_P1_TUN_RFRESTE1 0xf4f60003
3124 3237
3125/*P1_TNRRESTE*/ 3238/*P1_TNRRESTE*/
3126#define R0900_P1_TNRRESTE 0xf4f7 3239#define R0900_P1_TNRRESTE 0xf4f7
3127#define F0900_P1_TUN_RFRESTE0 0xf4f700ff 3240#define TNRRESTE REGx(R0900_P1_TNRRESTE)
3241#define F0900_P1_TUN_RFRESTE0 0xf4f700ff
3128 3242
3129/*P1_SMAPCOEF7*/ 3243/*P1_SMAPCOEF7*/
3130#define R0900_P1_SMAPCOEF7 0xf500 3244#define R0900_P1_SMAPCOEF7 0xf500
3131#define F0900_P1_DIS_QSCALE 0xf5000080 3245#define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7)
3132#define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f 3246#define F0900_P1_DIS_QSCALE 0xf5000080
3247#define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f
3133 3248
3134/*P1_SMAPCOEF6*/ 3249/*P1_SMAPCOEF6*/
3135#define R0900_P1_SMAPCOEF6 0xf501 3250#define R0900_P1_SMAPCOEF6 0xf501
3136#define F0900_P1_DIS_NEWSCALE 0xf5010008 3251#define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6)
3137#define F0900_P1_ADJ_8PSKLLR1 0xf5010004 3252#define F0900_P1_ADJ_8PSKLLR1 0xf5010004
3138#define F0900_P1_OLD_8PSKLLR1 0xf5010002 3253#define F0900_P1_OLD_8PSKLLR1 0xf5010002
3139#define F0900_P1_DIS_AB8PSK 0xf5010001 3254#define F0900_P1_DIS_AB8PSK 0xf5010001
3140 3255
3141/*P1_SMAPCOEF5*/ 3256/*P1_SMAPCOEF5*/
3142#define R0900_P1_SMAPCOEF5 0xf502 3257#define R0900_P1_SMAPCOEF5 0xf502
3143#define F0900_P1_DIS_8SCALE 0xf5020080 3258#define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5)
3144#define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f 3259#define F0900_P1_DIS_8SCALE 0xf5020080
3260#define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f
3261
3262/*P1_NCO2MAX1*/
3263#define R0900_P1_NCO2MAX1 0xf514
3264#define NCO2MAX1 REGx(R0900_P1_NCO2MAX1)
3265#define F0900_P1_TETA2_MAXVABS1 0xf51400ff
3266
3267/*P1_NCO2MAX0*/
3268#define R0900_P1_NCO2MAX0 0xf515
3269#define NCO2MAX0 REGx(R0900_P1_NCO2MAX0)
3270#define F0900_P1_TETA2_MAXVABS0 0xf51500ff
3271
3272/*P1_NCO2FR1*/
3273#define R0900_P1_NCO2FR1 0xf516
3274#define NCO2FR1 REGx(R0900_P1_NCO2FR1)
3275#define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff
3276
3277/*P1_NCO2FR0*/
3278#define R0900_P1_NCO2FR0 0xf517
3279#define NCO2FR0 REGx(R0900_P1_NCO2FR0)
3280#define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff
3281
3282/*P1_CFR2AVRGE1*/
3283#define R0900_P1_CFR2AVRGE1 0xf518
3284#define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1)
3285#define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff
3286
3287/*P1_CFR2AVRGE0*/
3288#define R0900_P1_CFR2AVRGE0 0xf519
3289#define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0)
3290#define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff
3145 3291
3146/*P1_DMDPLHSTAT*/ 3292/*P1_DMDPLHSTAT*/
3147#define R0900_P1_DMDPLHSTAT 0xf520 3293#define R0900_P1_DMDPLHSTAT 0xf520
3148#define F0900_P1_PLH_STATISTIC 0xf52000ff 3294#define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT)
3295#define F0900_P1_PLH_STATISTIC 0xf52000ff
3149 3296
3150/*P1_LOCKTIME3*/ 3297/*P1_LOCKTIME3*/
3151#define R0900_P1_LOCKTIME3 0xf522 3298#define R0900_P1_LOCKTIME3 0xf522
3152#define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff 3299#define LOCKTIME3 REGx(R0900_P1_LOCKTIME3)
3300#define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff
3153 3301
3154/*P1_LOCKTIME2*/ 3302/*P1_LOCKTIME2*/
3155#define R0900_P1_LOCKTIME2 0xf523 3303#define R0900_P1_LOCKTIME2 0xf523
3156#define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff 3304#define LOCKTIME2 REGx(R0900_P1_LOCKTIME2)
3305#define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff
3157 3306
3158/*P1_LOCKTIME1*/ 3307/*P1_LOCKTIME1*/
3159#define R0900_P1_LOCKTIME1 0xf524 3308#define R0900_P1_LOCKTIME1 0xf524
3160#define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff 3309#define LOCKTIME1 REGx(R0900_P1_LOCKTIME1)
3310#define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff
3161 3311
3162/*P1_LOCKTIME0*/ 3312/*P1_LOCKTIME0*/
3163#define R0900_P1_LOCKTIME0 0xf525 3313#define R0900_P1_LOCKTIME0 0xf525
3164#define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff 3314#define LOCKTIME0 REGx(R0900_P1_LOCKTIME0)
3315#define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff
3165 3316
3166/*P1_VITSCALE*/ 3317/*P1_VITSCALE*/
3167#define R0900_P1_VITSCALE 0xf532 3318#define R0900_P1_VITSCALE 0xf532
3168#define F0900_P1_NVTH_NOSRANGE 0xf5320080 3319#define VITSCALE REGx(R0900_P1_VITSCALE)
3169#define F0900_P1_VERROR_MAXMODE 0xf5320040 3320#define F0900_P1_NVTH_NOSRANGE 0xf5320080
3170#define F0900_P1_KDIV_MODE 0xf5320030 3321#define F0900_P1_VERROR_MAXMODE 0xf5320040
3171#define F0900_P1_NSLOWSN_LOCKED 0xf5320008 3322#define F0900_P1_NSLOWSN_LOCKED 0xf5320008
3172#define F0900_P1_DELOCK_PRFLOSS 0xf5320004 3323#define F0900_P1_DIS_RSFLOCK 0xf5320002
3173#define F0900_P1_DIS_RSFLOCK 0xf5320002
3174 3324
3175/*P1_FECM*/ 3325/*P1_FECM*/
3176#define R0900_P1_FECM 0xf533 3326#define R0900_P1_FECM 0xf533
3177#define F0900_P1_DSS_DVB 0xf5330080 3327#define FECM REGx(R0900_P1_FECM)
3178#define F0900_P1_DEMOD_BYPASS 0xf5330040 3328#define F0900_P1_DSS_DVB 0xf5330080
3179#define F0900_P1_CMP_SLOWMODE 0xf5330020 3329#define DSS_DVB FLDx(F0900_P1_DSS_DVB)
3180#define F0900_P1_DSS_SRCH 0xf5330010 3330#define F0900_P1_DSS_SRCH 0xf5330010
3181#define F0900_P1_DIFF_MODEVIT 0xf5330004 3331#define F0900_P1_SYNCVIT 0xf5330002
3182#define F0900_P1_SYNCVIT 0xf5330002 3332#define F0900_P1_IQINV 0xf5330001
3183#define F0900_P1_IQINV 0xf5330001 3333#define IQINV FLDx(F0900_P1_IQINV)
3184 3334
3185/*P1_VTH12*/ 3335/*P1_VTH12*/
3186#define R0900_P1_VTH12 0xf534 3336#define R0900_P1_VTH12 0xf534
3187#define F0900_P1_VTH12 0xf53400ff 3337#define VTH12 REGx(R0900_P1_VTH12)
3338#define F0900_P1_VTH12 0xf53400ff
3188 3339
3189/*P1_VTH23*/ 3340/*P1_VTH23*/
3190#define R0900_P1_VTH23 0xf535 3341#define R0900_P1_VTH23 0xf535
3191#define F0900_P1_VTH23 0xf53500ff 3342#define VTH23 REGx(R0900_P1_VTH23)
3343#define F0900_P1_VTH23 0xf53500ff
3192 3344
3193/*P1_VTH34*/ 3345/*P1_VTH34*/
3194#define R0900_P1_VTH34 0xf536 3346#define R0900_P1_VTH34 0xf536
3195#define F0900_P1_VTH34 0xf53600ff 3347#define VTH34 REGx(R0900_P1_VTH34)
3348#define F0900_P1_VTH34 0xf53600ff
3196 3349
3197/*P1_VTH56*/ 3350/*P1_VTH56*/
3198#define R0900_P1_VTH56 0xf537 3351#define R0900_P1_VTH56 0xf537
3199#define F0900_P1_VTH56 0xf53700ff 3352#define VTH56 REGx(R0900_P1_VTH56)
3353#define F0900_P1_VTH56 0xf53700ff
3200 3354
3201/*P1_VTH67*/ 3355/*P1_VTH67*/
3202#define R0900_P1_VTH67 0xf538 3356#define R0900_P1_VTH67 0xf538
3203#define F0900_P1_VTH67 0xf53800ff 3357#define VTH67 REGx(R0900_P1_VTH67)
3358#define F0900_P1_VTH67 0xf53800ff
3204 3359
3205/*P1_VTH78*/ 3360/*P1_VTH78*/
3206#define R0900_P1_VTH78 0xf539 3361#define R0900_P1_VTH78 0xf539
3207#define F0900_P1_VTH78 0xf53900ff 3362#define VTH78 REGx(R0900_P1_VTH78)
3363#define F0900_P1_VTH78 0xf53900ff
3208 3364
3209/*P1_VITCURPUN*/ 3365/*P1_VITCURPUN*/
3210#define R0900_P1_VITCURPUN 0xf53a 3366#define R0900_P1_VITCURPUN 0xf53a
3211#define F0900_P1_VIT_MAPPING 0xf53a00e0 3367#define VITCURPUN REGx(R0900_P1_VITCURPUN)
3212#define F0900_P1_VIT_CURPUN 0xf53a001f 3368#define F0900_P1_VIT_CURPUN 0xf53a001f
3369#define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN)
3213 3370
3214/*P1_VERROR*/ 3371/*P1_VERROR*/
3215#define R0900_P1_VERROR 0xf53b 3372#define R0900_P1_VERROR 0xf53b
3216#define F0900_P1_REGERR_VIT 0xf53b00ff 3373#define VERROR REGx(R0900_P1_VERROR)
3374#define F0900_P1_REGERR_VIT 0xf53b00ff
3217 3375
3218/*P1_PRVIT*/ 3376/*P1_PRVIT*/
3219#define R0900_P1_PRVIT 0xf53c 3377#define R0900_P1_PRVIT 0xf53c
3220#define F0900_P1_DIS_VTHLOCK 0xf53c0040 3378#define PRVIT REGx(R0900_P1_PRVIT)
3221#define F0900_P1_E7_8VIT 0xf53c0020 3379#define F0900_P1_DIS_VTHLOCK 0xf53c0040
3222#define F0900_P1_E6_7VIT 0xf53c0010 3380#define F0900_P1_E7_8VIT 0xf53c0020
3223#define F0900_P1_E5_6VIT 0xf53c0008 3381#define F0900_P1_E6_7VIT 0xf53c0010
3224#define F0900_P1_E3_4VIT 0xf53c0004 3382#define F0900_P1_E5_6VIT 0xf53c0008
3225#define F0900_P1_E2_3VIT 0xf53c0002 3383#define F0900_P1_E3_4VIT 0xf53c0004
3226#define F0900_P1_E1_2VIT 0xf53c0001 3384#define F0900_P1_E2_3VIT 0xf53c0002
3385#define F0900_P1_E1_2VIT 0xf53c0001
3227 3386
3228/*P1_VAVSRVIT*/ 3387/*P1_VAVSRVIT*/
3229#define R0900_P1_VAVSRVIT 0xf53d 3388#define R0900_P1_VAVSRVIT 0xf53d
3230#define F0900_P1_AMVIT 0xf53d0080 3389#define VAVSRVIT REGx(R0900_P1_VAVSRVIT)
3231#define F0900_P1_FROZENVIT 0xf53d0040 3390#define F0900_P1_AMVIT 0xf53d0080
3232#define F0900_P1_SNVIT 0xf53d0030 3391#define F0900_P1_FROZENVIT 0xf53d0040
3233#define F0900_P1_TOVVIT 0xf53d000c 3392#define F0900_P1_SNVIT 0xf53d0030
3234#define F0900_P1_HYPVIT 0xf53d0003 3393#define F0900_P1_TOVVIT 0xf53d000c
3394#define F0900_P1_HYPVIT 0xf53d0003
3235 3395
3236/*P1_VSTATUSVIT*/ 3396/*P1_VSTATUSVIT*/
3237#define R0900_P1_VSTATUSVIT 0xf53e 3397#define R0900_P1_VSTATUSVIT 0xf53e
3238#define F0900_P1_VITERBI_ON 0xf53e0080 3398#define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT)
3239#define F0900_P1_END_LOOPVIT 0xf53e0040 3399#define F0900_P1_PRFVIT 0xf53e0010
3240#define F0900_P1_VITERBI_DEPRF 0xf53e0020 3400#define PRFVIT FLDx(F0900_P1_PRFVIT)
3241#define F0900_P1_PRFVIT 0xf53e0010 3401#define F0900_P1_LOCKEDVIT 0xf53e0008
3242#define F0900_P1_LOCKEDVIT 0xf53e0008 3402#define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT)
3243#define F0900_P1_VITERBI_DELOCK 0xf53e0004
3244#define F0900_P1_VIT_DEMODSEL 0xf53e0002
3245#define F0900_P1_VITERBI_COMPOUT 0xf53e0001
3246 3403
3247/*P1_VTHINUSE*/ 3404/*P1_VTHINUSE*/
3248#define R0900_P1_VTHINUSE 0xf53f 3405#define R0900_P1_VTHINUSE 0xf53f
3249#define F0900_P1_VIT_INUSE 0xf53f00ff 3406#define VTHINUSE REGx(R0900_P1_VTHINUSE)
3407#define F0900_P1_VIT_INUSE 0xf53f00ff
3250 3408
3251/*P1_KDIV12*/ 3409/*P1_KDIV12*/
3252#define R0900_P1_KDIV12 0xf540 3410#define R0900_P1_KDIV12 0xf540
3253#define F0900_P1_KDIV12_MANUAL 0xf5400080 3411#define KDIV12 REGx(R0900_P1_KDIV12)
3254#define F0900_P1_K_DIVIDER_12 0xf540007f 3412#define F0900_P1_K_DIVIDER_12 0xf540007f
3255 3413
3256/*P1_KDIV23*/ 3414/*P1_KDIV23*/
3257#define R0900_P1_KDIV23 0xf541 3415#define R0900_P1_KDIV23 0xf541
3258#define F0900_P1_KDIV23_MANUAL 0xf5410080 3416#define KDIV23 REGx(R0900_P1_KDIV23)
3259#define F0900_P1_K_DIVIDER_23 0xf541007f 3417#define F0900_P1_K_DIVIDER_23 0xf541007f
3260 3418
3261/*P1_KDIV34*/ 3419/*P1_KDIV34*/
3262#define R0900_P1_KDIV34 0xf542 3420#define R0900_P1_KDIV34 0xf542
3263#define F0900_P1_KDIV34_MANUAL 0xf5420080 3421#define KDIV34 REGx(R0900_P1_KDIV34)
3264#define F0900_P1_K_DIVIDER_34 0xf542007f 3422#define F0900_P1_K_DIVIDER_34 0xf542007f
3265 3423
3266/*P1_KDIV56*/ 3424/*P1_KDIV56*/
3267#define R0900_P1_KDIV56 0xf543 3425#define R0900_P1_KDIV56 0xf543
3268#define F0900_P1_KDIV56_MANUAL 0xf5430080 3426#define KDIV56 REGx(R0900_P1_KDIV56)
3269#define F0900_P1_K_DIVIDER_56 0xf543007f 3427#define F0900_P1_K_DIVIDER_56 0xf543007f
3270 3428
3271/*P1_KDIV67*/ 3429/*P1_KDIV67*/
3272#define R0900_P1_KDIV67 0xf544 3430#define R0900_P1_KDIV67 0xf544
3273#define F0900_P1_KDIV67_MANUAL 0xf5440080 3431#define KDIV67 REGx(R0900_P1_KDIV67)
3274#define F0900_P1_K_DIVIDER_67 0xf544007f 3432#define F0900_P1_K_DIVIDER_67 0xf544007f
3275 3433
3276/*P1_KDIV78*/ 3434/*P1_KDIV78*/
3277#define R0900_P1_KDIV78 0xf545 3435#define R0900_P1_KDIV78 0xf545
3278#define F0900_P1_KDIV78_MANUAL 0xf5450080 3436#define KDIV78 REGx(R0900_P1_KDIV78)
3279#define F0900_P1_K_DIVIDER_78 0xf545007f 3437#define F0900_P1_K_DIVIDER_78 0xf545007f
3280 3438
3281/*P1_PDELCTRL1*/ 3439/*P1_PDELCTRL1*/
3282#define R0900_P1_PDELCTRL1 0xf550 3440#define R0900_P1_PDELCTRL1 0xf550
3283#define F0900_P1_INV_MISMASK 0xf5500080 3441#define PDELCTRL1 REGx(R0900_P1_PDELCTRL1)
3284#define F0900_P1_FORCE_ACCEPTED 0xf5500040 3442#define F0900_P1_INV_MISMASK 0xf5500080
3285#define F0900_P1_FILTER_EN 0xf5500020 3443#define F0900_P1_FILTER_EN 0xf5500020
3286#define F0900_P1_FORCE_PKTDELINUSE 0xf5500010 3444#define F0900_P1_EN_MIS00 0xf5500002
3287#define F0900_P1_HYSTEN 0xf5500008 3445#define F0900_P1_ALGOSWRST 0xf5500001
3288#define F0900_P1_HYSTSWRST 0xf5500004 3446#define ALGOSWRST FLDx(F0900_P1_ALGOSWRST)
3289#define F0900_P1_EN_MIS00 0xf5500002
3290#define F0900_P1_ALGOSWRST 0xf5500001
3291 3447
3292/*P1_PDELCTRL2*/ 3448/*P1_PDELCTRL2*/
3293#define R0900_P1_PDELCTRL2 0xf551 3449#define R0900_P1_PDELCTRL2 0xf551
3294#define F0900_P1_FORCE_CONTINUOUS 0xf5510080 3450#define PDELCTRL2 REGx(R0900_P1_PDELCTRL2)
3295#define F0900_P1_RESET_UPKO_COUNT 0xf5510040 3451#define F0900_P1_RESET_UPKO_COUNT 0xf5510040
3296#define F0900_P1_USER_PKTDELIN_NB 0xf5510020 3452#define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT)
3297#define F0900_P1_FORCE_LOCKED 0xf5510010 3453#define F0900_P1_FRAME_MODE 0xf5510002
3298#define F0900_P1_DATA_UNBBSCRAM 0xf5510008 3454#define F0900_P1_NOBCHERRFLG_USE 0xf5510001
3299#define F0900_P1_FORCE_LONGPKT 0xf5510004
3300#define F0900_P1_FRAME_MODE 0xf5510002
3301 3455
3302/*P1_HYSTTHRESH*/ 3456/*P1_HYSTTHRESH*/
3303#define R0900_P1_HYSTTHRESH 0xf554 3457#define R0900_P1_HYSTTHRESH 0xf554
3304#define F0900_P1_UNLCK_THRESH 0xf55400f0 3458#define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH)
3305#define F0900_P1_DELIN_LCK_THRESH 0xf554000f 3459#define F0900_P1_UNLCK_THRESH 0xf55400f0
3460#define F0900_P1_DELIN_LCK_THRESH 0xf554000f
3306 3461
3307/*P1_ISIENTRY*/ 3462/*P1_ISIENTRY*/
3308#define R0900_P1_ISIENTRY 0xf55e 3463#define R0900_P1_ISIENTRY 0xf55e
3309#define F0900_P1_ISI_ENTRY 0xf55e00ff 3464#define ISIENTRY REGx(R0900_P1_ISIENTRY)
3465#define F0900_P1_ISI_ENTRY 0xf55e00ff
3310 3466
3311/*P1_ISIBITENA*/ 3467/*P1_ISIBITENA*/
3312#define R0900_P1_ISIBITENA 0xf55f 3468#define R0900_P1_ISIBITENA 0xf55f
3313#define F0900_P1_ISI_BIT_EN 0xf55f00ff 3469#define ISIBITENA REGx(R0900_P1_ISIBITENA)
3470#define F0900_P1_ISI_BIT_EN 0xf55f00ff
3314 3471
3315/*P1_MATSTR1*/ 3472/*P1_MATSTR1*/
3316#define R0900_P1_MATSTR1 0xf560 3473#define R0900_P1_MATSTR1 0xf560
3317#define F0900_P1_MATYPE_CURRENT1 0xf56000ff 3474#define MATSTR1 REGx(R0900_P1_MATSTR1)
3475#define F0900_P1_MATYPE_CURRENT1 0xf56000ff
3318 3476
3319/*P1_MATSTR0*/ 3477/*P1_MATSTR0*/
3320#define R0900_P1_MATSTR0 0xf561 3478#define R0900_P1_MATSTR0 0xf561
3321#define F0900_P1_MATYPE_CURRENT0 0xf56100ff 3479#define MATSTR0 REGx(R0900_P1_MATSTR0)
3480#define F0900_P1_MATYPE_CURRENT0 0xf56100ff
3322 3481
3323/*P1_UPLSTR1*/ 3482/*P1_UPLSTR1*/
3324#define R0900_P1_UPLSTR1 0xf562 3483#define R0900_P1_UPLSTR1 0xf562
3325#define F0900_P1_UPL_CURRENT1 0xf56200ff 3484#define UPLSTR1 REGx(R0900_P1_UPLSTR1)
3485#define F0900_P1_UPL_CURRENT1 0xf56200ff
3326 3486
3327/*P1_UPLSTR0*/ 3487/*P1_UPLSTR0*/
3328#define R0900_P1_UPLSTR0 0xf563 3488#define R0900_P1_UPLSTR0 0xf563
3329#define F0900_P1_UPL_CURRENT0 0xf56300ff 3489#define UPLSTR0 REGx(R0900_P1_UPLSTR0)
3490#define F0900_P1_UPL_CURRENT0 0xf56300ff
3330 3491
3331/*P1_DFLSTR1*/ 3492/*P1_DFLSTR1*/
3332#define R0900_P1_DFLSTR1 0xf564 3493#define R0900_P1_DFLSTR1 0xf564
3333#define F0900_P1_DFL_CURRENT1 0xf56400ff 3494#define DFLSTR1 REGx(R0900_P1_DFLSTR1)
3495#define F0900_P1_DFL_CURRENT1 0xf56400ff
3334 3496
3335/*P1_DFLSTR0*/ 3497/*P1_DFLSTR0*/
3336#define R0900_P1_DFLSTR0 0xf565 3498#define R0900_P1_DFLSTR0 0xf565
3337#define F0900_P1_DFL_CURRENT0 0xf56500ff 3499#define DFLSTR0 REGx(R0900_P1_DFLSTR0)
3500#define F0900_P1_DFL_CURRENT0 0xf56500ff
3338 3501
3339/*P1_SYNCSTR*/ 3502/*P1_SYNCSTR*/
3340#define R0900_P1_SYNCSTR 0xf566 3503#define R0900_P1_SYNCSTR 0xf566
3341#define F0900_P1_SYNC_CURRENT 0xf56600ff 3504#define SYNCSTR REGx(R0900_P1_SYNCSTR)
3505#define F0900_P1_SYNC_CURRENT 0xf56600ff
3342 3506
3343/*P1_SYNCDSTR1*/ 3507/*P1_SYNCDSTR1*/
3344#define R0900_P1_SYNCDSTR1 0xf567 3508#define R0900_P1_SYNCDSTR1 0xf567
3345#define F0900_P1_SYNCD_CURRENT1 0xf56700ff 3509#define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1)
3510#define F0900_P1_SYNCD_CURRENT1 0xf56700ff
3346 3511
3347/*P1_SYNCDSTR0*/ 3512/*P1_SYNCDSTR0*/
3348#define R0900_P1_SYNCDSTR0 0xf568 3513#define R0900_P1_SYNCDSTR0 0xf568
3349#define F0900_P1_SYNCD_CURRENT0 0xf56800ff 3514#define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0)
3515#define F0900_P1_SYNCD_CURRENT0 0xf56800ff
3350 3516
3351/*P1_PDELSTATUS1*/ 3517/*P1_PDELSTATUS1*/
3352#define R0900_P1_PDELSTATUS1 0xf569 3518#define R0900_P1_PDELSTATUS1 0xf569
3353#define F0900_P1_PKTDELIN_DELOCK 0xf5690080 3519#define F0900_P1_PKTDELIN_DELOCK 0xf5690080
3354#define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040 3520#define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040
3355#define F0900_P1_CONTINUOUS_STREAM 0xf5690020 3521#define F0900_P1_CONTINUOUS_STREAM 0xf5690020
3356#define F0900_P1_UNACCEPTED_STREAM 0xf5690010 3522#define F0900_P1_UNACCEPTED_STREAM 0xf5690010
3357#define F0900_P1_BCH_ERROR_FLAG 0xf5690008 3523#define F0900_P1_BCH_ERROR_FLAG 0xf5690008
3358#define F0900_P1_BBHCRCKO 0xf5690004 3524#define F0900_P1_PKTDELIN_LOCK 0xf5690002
3359#define F0900_P1_PKTDELIN_LOCK 0xf5690002 3525#define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK)
3360#define F0900_P1_FIRST_LOCK 0xf5690001 3526#define F0900_P1_FIRST_LOCK 0xf5690001
3361 3527
3362/*P1_PDELSTATUS2*/ 3528/*P1_PDELSTATUS2*/
3363#define R0900_P1_PDELSTATUS2 0xf56a 3529#define R0900_P1_PDELSTATUS2 0xf56a
3364#define F0900_P1_PKTDEL_DEMODSEL 0xf56a0080 3530#define F0900_P1_FRAME_MODCOD 0xf56a007c
3365#define F0900_P1_FRAME_MODCOD 0xf56a007c 3531#define F0900_P1_FRAME_TYPE 0xf56a0003
3366#define F0900_P1_FRAME_TYPE 0xf56a0003
3367 3532
3368/*P1_BBFCRCKO1*/ 3533/*P1_BBFCRCKO1*/
3369#define R0900_P1_BBFCRCKO1 0xf56b 3534#define R0900_P1_BBFCRCKO1 0xf56b
3370#define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff 3535#define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1)
3536#define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff
3371 3537
3372/*P1_BBFCRCKO0*/ 3538/*P1_BBFCRCKO0*/
3373#define R0900_P1_BBFCRCKO0 0xf56c 3539#define R0900_P1_BBFCRCKO0 0xf56c
3374#define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff 3540#define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0)
3541#define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff
3375 3542
3376/*P1_UPCRCKO1*/ 3543/*P1_UPCRCKO1*/
3377#define R0900_P1_UPCRCKO1 0xf56d 3544#define R0900_P1_UPCRCKO1 0xf56d
3378#define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff 3545#define UPCRCKO1 REGx(R0900_P1_UPCRCKO1)
3546#define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff
3379 3547
3380/*P1_UPCRCKO0*/ 3548/*P1_UPCRCKO0*/
3381#define R0900_P1_UPCRCKO0 0xf56e 3549#define R0900_P1_UPCRCKO0 0xf56e
3382#define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff 3550#define UPCRCKO0 REGx(R0900_P1_UPCRCKO0)
3551#define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff
3552
3553/*P1_PDELCTRL3*/
3554#define R0900_P1_PDELCTRL3 0xf56f
3555#define PDELCTRL3 REGx(R0900_P1_PDELCTRL3)
3556#define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080
3557#define F0900_P1_NOFIFO_BCHERR 0xf56f0020
3383 3558
3384/*P1_TSSTATEM*/ 3559/*P1_TSSTATEM*/
3385#define R0900_P1_TSSTATEM 0xf570 3560#define R0900_P1_TSSTATEM 0xf570
3386#define F0900_P1_TSDIL_ON 0xf5700080 3561#define TSSTATEM REGx(R0900_P1_TSSTATEM)
3387#define F0900_P1_TSSKIPRS_ON 0xf5700040 3562#define F0900_P1_TSDIL_ON 0xf5700080
3388#define F0900_P1_TSRS_ON 0xf5700020 3563#define F0900_P1_TSRS_ON 0xf5700020
3389#define F0900_P1_TSDESCRAMB_ON 0xf5700010 3564#define F0900_P1_TSDESCRAMB_ON 0xf5700010
3390#define F0900_P1_TSFRAME_MODE 0xf5700008 3565#define F0900_P1_TSFRAME_MODE 0xf5700008
3391#define F0900_P1_TS_DISABLE 0xf5700004 3566#define F0900_P1_TS_DISABLE 0xf5700004
3392#define F0900_P1_TSACM_MODE 0xf5700002 3567#define F0900_P1_TSOUT_NOSYNC 0xf5700001
3393#define F0900_P1_TSOUT_NOSYNC 0xf5700001
3394 3568
3395/*P1_TSCFGH*/ 3569/*P1_TSCFGH*/
3396#define R0900_P1_TSCFGH 0xf572 3570#define R0900_P1_TSCFGH 0xf572
3397#define F0900_P1_TSFIFO_DVBCI 0xf5720080 3571#define TSCFGH REGx(R0900_P1_TSCFGH)
3398#define F0900_P1_TSFIFO_SERIAL 0xf5720040 3572#define F0900_P1_TSFIFO_DVBCI 0xf5720080
3399#define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020 3573#define F0900_P1_TSFIFO_SERIAL 0xf5720040
3400#define F0900_P1_TSFIFO_DUTY50 0xf5720010 3574#define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020
3401#define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008 3575#define F0900_P1_TSFIFO_DUTY50 0xf5720010
3402#define F0900_P1_TSFIFO_ERRMODE 0xf5720006 3576#define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008
3403#define F0900_P1_RST_HWARE 0xf5720001 3577#define F0900_P1_TSFIFO_ERRMODE 0xf5720006
3578#define F0900_P1_RST_HWARE 0xf5720001
3579#define RST_HWARE FLDx(F0900_P1_RST_HWARE)
3404 3580
3405/*P1_TSCFGM*/ 3581/*P1_TSCFGM*/
3406#define R0900_P1_TSCFGM 0xf573 3582#define R0900_P1_TSCFGM 0xf573
3407#define F0900_P1_TSFIFO_MANSPEED 0xf57300c0 3583#define TSCFGM REGx(R0900_P1_TSCFGM)
3408#define F0900_P1_TSFIFO_PERMDATA 0xf5730020 3584#define F0900_P1_TSFIFO_MANSPEED 0xf57300c0
3409#define F0900_P1_TSFIFO_NONEWSGNL 0xf5730010 3585#define F0900_P1_TSFIFO_PERMDATA 0xf5730020
3410#define F0900_P1_TSFIFO_BITSPEED 0xf5730008 3586#define F0900_P1_TSFIFO_DPUNACT 0xf5730002
3411#define F0900_P1_NPD_SPECDVBS2 0xf5730004 3587#define F0900_P1_TSFIFO_INVDATA 0xf5730001
3412#define F0900_P1_TSFIFO_STOPCKDIS 0xf5730002
3413#define F0900_P1_TSFIFO_INVDATA 0xf5730001
3414 3588
3415/*P1_TSCFGL*/ 3589/*P1_TSCFGL*/
3416#define R0900_P1_TSCFGL 0xf574 3590#define R0900_P1_TSCFGL 0xf574
3417#define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 3591#define TSCFGL REGx(R0900_P1_TSCFGL)
3418#define F0900_P1_BCHERROR_MODE 0xf5740030 3592#define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0
3419#define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008 3593#define F0900_P1_BCHERROR_MODE 0xf5740030
3420#define F0900_P1_TSFIFO_EMBINDVB 0xf5740004 3594#define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008
3421#define F0900_P1_TSFIFO_DPUNACT 0xf5740002 3595#define F0900_P1_TSFIFO_EMBINDVB 0xf5740004
3422#define F0900_P1_TSFIFO_NPDOFF 0xf5740001 3596#define F0900_P1_TSFIFO_BITSPEED 0xf5740003
3423 3597
3424/*P1_TSINSDELH*/ 3598/*P1_TSINSDELH*/
3425#define R0900_P1_TSINSDELH 0xf576 3599#define R0900_P1_TSINSDELH 0xf576
3426#define F0900_P1_TSDEL_SYNCBYTE 0xf5760080 3600#define TSINSDELH REGx(R0900_P1_TSINSDELH)
3427#define F0900_P1_TSDEL_XXHEADER 0xf5760040 3601#define F0900_P1_TSDEL_SYNCBYTE 0xf5760080
3428#define F0900_P1_TSDEL_BBHEADER 0xf5760020 3602#define F0900_P1_TSDEL_XXHEADER 0xf5760040
3429#define F0900_P1_TSDEL_DATAFIELD 0xf5760010 3603#define F0900_P1_TSDEL_BBHEADER 0xf5760020
3430#define F0900_P1_TSINSDEL_ISCR 0xf5760008 3604#define F0900_P1_TSDEL_DATAFIELD 0xf5760010
3431#define F0900_P1_TSINSDEL_NPD 0xf5760004 3605#define F0900_P1_TSINSDEL_ISCR 0xf5760008
3432#define F0900_P1_TSINSDEL_RSPARITY 0xf5760002 3606#define F0900_P1_TSINSDEL_NPD 0xf5760004
3433#define F0900_P1_TSINSDEL_CRC8 0xf5760001 3607#define F0900_P1_TSINSDEL_RSPARITY 0xf5760002
3608#define F0900_P1_TSINSDEL_CRC8 0xf5760001
3609
3610/*P1_TSDIVN*/
3611#define R0900_P1_TSDIVN 0xf579
3612#define TSDIVN REGx(R0900_P1_TSDIVN)
3613#define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0
3614
3615/*P1_TSCFG4*/
3616#define R0900_P1_TSCFG4 0xf57a
3617#define TSCFG4 REGx(R0900_P1_TSCFG4)
3618#define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0
3434 3619
3435/*P1_TSSPEED*/ 3620/*P1_TSSPEED*/
3436#define R0900_P1_TSSPEED 0xf580 3621#define R0900_P1_TSSPEED 0xf580
3437#define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff 3622#define TSSPEED REGx(R0900_P1_TSSPEED)
3623#define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff
3438 3624
3439/*P1_TSSTATUS*/ 3625/*P1_TSSTATUS*/
3440#define R0900_P1_TSSTATUS 0xf581 3626#define R0900_P1_TSSTATUS 0xf581
3441#define F0900_P1_TSFIFO_LINEOK 0xf5810080 3627#define TSSTATUS REGx(R0900_P1_TSSTATUS)
3442#define F0900_P1_TSFIFO_ERROR 0xf5810040 3628#define F0900_P1_TSFIFO_LINEOK 0xf5810080
3443#define F0900_P1_TSFIFO_DATA7 0xf5810020 3629#define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK)
3444#define F0900_P1_TSFIFO_NOSYNC 0xf5810010 3630#define F0900_P1_TSFIFO_ERROR 0xf5810040
3445#define F0900_P1_ISCR_INITIALIZED 0xf5810008 3631#define F0900_P1_DIL_READY 0xf5810001
3446#define F0900_P1_ISCR_UPDATED 0xf5810004
3447#define F0900_P1_SOFFIFO_UNREGUL 0xf5810002
3448#define F0900_P1_DIL_READY 0xf5810001
3449 3632
3450/*P1_TSSTATUS2*/ 3633/*P1_TSSTATUS2*/
3451#define R0900_P1_TSSTATUS2 0xf582 3634#define R0900_P1_TSSTATUS2 0xf582
3452#define F0900_P1_TSFIFO_DEMODSEL 0xf5820080 3635#define TSSTATUS2 REGx(R0900_P1_TSSTATUS2)
3453#define F0900_P1_TSFIFOSPEED_STORE 0xf5820040 3636#define F0900_P1_TSFIFO_DEMODSEL 0xf5820080
3454#define F0900_P1_DILXX_RESET 0xf5820020 3637#define F0900_P1_TSFIFOSPEED_STORE 0xf5820040
3455#define F0900_P1_TSSERIAL_IMPOS 0xf5820010 3638#define F0900_P1_DILXX_RESET 0xf5820020
3456#define F0900_P1_TSFIFO_LINENOK 0xf5820008 3639#define F0900_P1_TSSERIAL_IMPOS 0xf5820010
3457#define F0900_P1_BITSPEED_EVENT 0xf5820004 3640#define F0900_P1_SCRAMBDETECT 0xf5820002
3458#define F0900_P1_SCRAMBDETECT 0xf5820002
3459#define F0900_P1_ULDTV67_FALSELOCK 0xf5820001
3460 3641
3461/*P1_TSBITRATE1*/ 3642/*P1_TSBITRATE1*/
3462#define R0900_P1_TSBITRATE1 0xf583 3643#define R0900_P1_TSBITRATE1 0xf583
3463#define F0900_P1_TSFIFO_BITRATE1 0xf58300ff 3644#define TSBITRATE1 REGx(R0900_P1_TSBITRATE1)
3645#define F0900_P1_TSFIFO_BITRATE1 0xf58300ff
3464 3646
3465/*P1_TSBITRATE0*/ 3647/*P1_TSBITRATE0*/
3466#define R0900_P1_TSBITRATE0 0xf584 3648#define R0900_P1_TSBITRATE0 0xf584
3467#define F0900_P1_TSFIFO_BITRATE0 0xf58400ff 3649#define TSBITRATE0 REGx(R0900_P1_TSBITRATE0)
3650#define F0900_P1_TSFIFO_BITRATE0 0xf58400ff
3468 3651
3469/*P1_ERRCTRL1*/ 3652/*P1_ERRCTRL1*/
3470#define R0900_P1_ERRCTRL1 0xf598 3653#define R0900_P1_ERRCTRL1 0xf598
3471#define F0900_P1_ERR_SOURCE1 0xf59800f0 3654#define ERRCTRL1 REGx(R0900_P1_ERRCTRL1)
3472#define F0900_P1_NUM_EVENT1 0xf5980007 3655#define F0900_P1_ERR_SOURCE1 0xf59800f0
3656#define F0900_P1_NUM_EVENT1 0xf5980007
3473 3657
3474/*P1_ERRCNT12*/ 3658/*P1_ERRCNT12*/
3475#define R0900_P1_ERRCNT12 0xf599 3659#define R0900_P1_ERRCNT12 0xf599
3476#define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080 3660#define ERRCNT12 REGx(R0900_P1_ERRCNT12)
3477#define F0900_P1_ERR_CNT12 0xf599007f 3661#define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080
3662#define F0900_P1_ERR_CNT12 0xf599007f
3663#define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12)
3478 3664
3479/*P1_ERRCNT11*/ 3665/*P1_ERRCNT11*/
3480#define R0900_P1_ERRCNT11 0xf59a 3666#define R0900_P1_ERRCNT11 0xf59a
3481#define F0900_P1_ERR_CNT11 0xf59a00ff 3667#define ERRCNT11 REGx(R0900_P1_ERRCNT11)
3668#define F0900_P1_ERR_CNT11 0xf59a00ff
3669#define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11)
3482 3670
3483/*P1_ERRCNT10*/ 3671/*P1_ERRCNT10*/
3484#define R0900_P1_ERRCNT10 0xf59b 3672#define R0900_P1_ERRCNT10 0xf59b
3485#define F0900_P1_ERR_CNT10 0xf59b00ff 3673#define ERRCNT10 REGx(R0900_P1_ERRCNT10)
3674#define F0900_P1_ERR_CNT10 0xf59b00ff
3675#define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10)
3486 3676
3487/*P1_ERRCTRL2*/ 3677/*P1_ERRCTRL2*/
3488#define R0900_P1_ERRCTRL2 0xf59c 3678#define R0900_P1_ERRCTRL2 0xf59c
3489#define F0900_P1_ERR_SOURCE2 0xf59c00f0 3679#define ERRCTRL2 REGx(R0900_P1_ERRCTRL2)
3490#define F0900_P1_NUM_EVENT2 0xf59c0007 3680#define F0900_P1_ERR_SOURCE2 0xf59c00f0
3681#define F0900_P1_NUM_EVENT2 0xf59c0007
3491 3682
3492/*P1_ERRCNT22*/ 3683/*P1_ERRCNT22*/
3493#define R0900_P1_ERRCNT22 0xf59d 3684#define R0900_P1_ERRCNT22 0xf59d
3494#define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080 3685#define ERRCNT22 REGx(R0900_P1_ERRCNT22)
3495#define F0900_P1_ERR_CNT22 0xf59d007f 3686#define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080
3687#define F0900_P1_ERR_CNT22 0xf59d007f
3688#define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22)
3496 3689
3497/*P1_ERRCNT21*/ 3690/*P1_ERRCNT21*/
3498#define R0900_P1_ERRCNT21 0xf59e 3691#define R0900_P1_ERRCNT21 0xf59e
3499#define F0900_P1_ERR_CNT21 0xf59e00ff 3692#define ERRCNT21 REGx(R0900_P1_ERRCNT21)
3693#define F0900_P1_ERR_CNT21 0xf59e00ff
3694#define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21)
3500 3695
3501/*P1_ERRCNT20*/ 3696/*P1_ERRCNT20*/
3502#define R0900_P1_ERRCNT20 0xf59f 3697#define R0900_P1_ERRCNT20 0xf59f
3503#define F0900_P1_ERR_CNT20 0xf59f00ff 3698#define ERRCNT20 REGx(R0900_P1_ERRCNT20)
3699#define F0900_P1_ERR_CNT20 0xf59f00ff
3700#define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20)
3504 3701
3505/*P1_FECSPY*/ 3702/*P1_FECSPY*/
3506#define R0900_P1_FECSPY 0xf5a0 3703#define R0900_P1_FECSPY 0xf5a0
3507#define F0900_P1_SPY_ENABLE 0xf5a00080 3704#define FECSPY REGx(R0900_P1_FECSPY)
3508#define F0900_P1_NO_SYNCBYTE 0xf5a00040 3705#define F0900_P1_SPY_ENABLE 0xf5a00080
3509#define F0900_P1_SERIAL_MODE 0xf5a00020 3706#define F0900_P1_NO_SYNCBYTE 0xf5a00040
3510#define F0900_P1_UNUSUAL_PACKET 0xf5a00010 3707#define F0900_P1_SERIAL_MODE 0xf5a00020
3511#define F0900_P1_BER_PACKMODE 0xf5a00008 3708#define F0900_P1_UNUSUAL_PACKET 0xf5a00010
3512#define F0900_P1_BERMETER_LMODE 0xf5a00002 3709#define F0900_P1_BERMETER_DATAMODE 0xf5a00008
3513#define F0900_P1_BERMETER_RESET 0xf5a00001 3710#define F0900_P1_BERMETER_LMODE 0xf5a00002
3711#define F0900_P1_BERMETER_RESET 0xf5a00001
3514 3712
3515/*P1_FSPYCFG*/ 3713/*P1_FSPYCFG*/
3516#define R0900_P1_FSPYCFG 0xf5a1 3714#define R0900_P1_FSPYCFG 0xf5a1
3517#define F0900_P1_FECSPY_INPUT 0xf5a100c0 3715#define FSPYCFG REGx(R0900_P1_FSPYCFG)
3518#define F0900_P1_RST_ON_ERROR 0xf5a10020 3716#define F0900_P1_FECSPY_INPUT 0xf5a100c0
3519#define F0900_P1_ONE_SHOT 0xf5a10010 3717#define F0900_P1_RST_ON_ERROR 0xf5a10020
3520#define F0900_P1_I2C_MODE 0xf5a1000c 3718#define F0900_P1_ONE_SHOT 0xf5a10010
3521#define F0900_P1_SPY_HYSTERESIS 0xf5a10003 3719#define F0900_P1_I2C_MODE 0xf5a1000c
3720#define F0900_P1_SPY_HYSTERESIS 0xf5a10003
3522 3721
3523/*P1_FSPYDATA*/ 3722/*P1_FSPYDATA*/
3524#define R0900_P1_FSPYDATA 0xf5a2 3723#define R0900_P1_FSPYDATA 0xf5a2
3525#define F0900_P1_SPY_STUFFING 0xf5a20080 3724#define FSPYDATA REGx(R0900_P1_FSPYDATA)
3526#define F0900_P1_NOERROR_PKTJITTER 0xf5a20040 3725#define F0900_P1_SPY_STUFFING 0xf5a20080
3527#define F0900_P1_SPY_CNULLPKT 0xf5a20020 3726#define F0900_P1_SPY_CNULLPKT 0xf5a20020
3528#define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f 3727#define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f
3529 3728
3530/*P1_FSPYOUT*/ 3729/*P1_FSPYOUT*/
3531#define R0900_P1_FSPYOUT 0xf5a3 3730#define R0900_P1_FSPYOUT 0xf5a3
3532#define F0900_P1_FSPY_DIRECT 0xf5a30080 3731#define FSPYOUT REGx(R0900_P1_FSPYOUT)
3533#define F0900_P1_SPY_OUTDATA_BUS 0xf5a30038 3732#define F0900_P1_FSPY_DIRECT 0xf5a30080
3534#define F0900_P1_STUFF_MODE 0xf5a30007 3733#define F0900_P1_STUFF_MODE 0xf5a30007
3535 3734
3536/*P1_FSTATUS*/ 3735/*P1_FSTATUS*/
3537#define R0900_P1_FSTATUS 0xf5a4 3736#define R0900_P1_FSTATUS 0xf5a4
3538#define F0900_P1_SPY_ENDSIM 0xf5a40080 3737#define FSTATUS REGx(R0900_P1_FSTATUS)
3539#define F0900_P1_VALID_SIM 0xf5a40040 3738#define F0900_P1_SPY_ENDSIM 0xf5a40080
3540#define F0900_P1_FOUND_SIGNAL 0xf5a40020 3739#define F0900_P1_VALID_SIM 0xf5a40040
3541#define F0900_P1_DSS_SYNCBYTE 0xf5a40010 3740#define F0900_P1_FOUND_SIGNAL 0xf5a40020
3542#define F0900_P1_RESULT_STATE 0xf5a4000f 3741#define F0900_P1_DSS_SYNCBYTE 0xf5a40010
3742#define F0900_P1_RESULT_STATE 0xf5a4000f
3543 3743
3544/*P1_FBERCPT4*/ 3744/*P1_FBERCPT4*/
3545#define R0900_P1_FBERCPT4 0xf5a8 3745#define R0900_P1_FBERCPT4 0xf5a8
3546#define F0900_P1_FBERMETER_CPT4 0xf5a800ff 3746#define FBERCPT4 REGx(R0900_P1_FBERCPT4)
3747#define F0900_P1_FBERMETER_CPT4 0xf5a800ff
3547 3748
3548/*P1_FBERCPT3*/ 3749/*P1_FBERCPT3*/
3549#define R0900_P1_FBERCPT3 0xf5a9 3750#define R0900_P1_FBERCPT3 0xf5a9
3550#define F0900_P1_FBERMETER_CPT3 0xf5a900ff 3751#define FBERCPT3 REGx(R0900_P1_FBERCPT3)
3752#define F0900_P1_FBERMETER_CPT3 0xf5a900ff
3551 3753
3552/*P1_FBERCPT2*/ 3754/*P1_FBERCPT2*/
3553#define R0900_P1_FBERCPT2 0xf5aa 3755#define R0900_P1_FBERCPT2 0xf5aa
3554#define F0900_P1_FBERMETER_CPT2 0xf5aa00ff 3756#define FBERCPT2 REGx(R0900_P1_FBERCPT2)
3757#define F0900_P1_FBERMETER_CPT2 0xf5aa00ff
3555 3758
3556/*P1_FBERCPT1*/ 3759/*P1_FBERCPT1*/
3557#define R0900_P1_FBERCPT1 0xf5ab 3760#define R0900_P1_FBERCPT1 0xf5ab
3558#define F0900_P1_FBERMETER_CPT1 0xf5ab00ff 3761#define FBERCPT1 REGx(R0900_P1_FBERCPT1)
3762#define F0900_P1_FBERMETER_CPT1 0xf5ab00ff
3559 3763
3560/*P1_FBERCPT0*/ 3764/*P1_FBERCPT0*/
3561#define R0900_P1_FBERCPT0 0xf5ac 3765#define R0900_P1_FBERCPT0 0xf5ac
3562#define F0900_P1_FBERMETER_CPT0 0xf5ac00ff 3766#define FBERCPT0 REGx(R0900_P1_FBERCPT0)
3767#define F0900_P1_FBERMETER_CPT0 0xf5ac00ff
3563 3768
3564/*P1_FBERERR2*/ 3769/*P1_FBERERR2*/
3565#define R0900_P1_FBERERR2 0xf5ad 3770#define R0900_P1_FBERERR2 0xf5ad
3566#define F0900_P1_FBERMETER_ERR2 0xf5ad00ff 3771#define FBERERR2 REGx(R0900_P1_FBERERR2)
3772#define F0900_P1_FBERMETER_ERR2 0xf5ad00ff
3567 3773
3568/*P1_FBERERR1*/ 3774/*P1_FBERERR1*/
3569#define R0900_P1_FBERERR1 0xf5ae 3775#define R0900_P1_FBERERR1 0xf5ae
3570#define F0900_P1_FBERMETER_ERR1 0xf5ae00ff 3776#define FBERERR1 REGx(R0900_P1_FBERERR1)
3777#define F0900_P1_FBERMETER_ERR1 0xf5ae00ff
3571 3778
3572/*P1_FBERERR0*/ 3779/*P1_FBERERR0*/
3573#define R0900_P1_FBERERR0 0xf5af 3780#define R0900_P1_FBERERR0 0xf5af
3574#define F0900_P1_FBERMETER_ERR0 0xf5af00ff 3781#define FBERERR0 REGx(R0900_P1_FBERERR0)
3782#define F0900_P1_FBERMETER_ERR0 0xf5af00ff
3575 3783
3576/*P1_FSPYBER*/ 3784/*P1_FSPYBER*/
3577#define R0900_P1_FSPYBER 0xf5b2 3785#define R0900_P1_FSPYBER 0xf5b2
3578#define F0900_P1_FSPYOBS_XORREAD 0xf5b20040 3786#define FSPYBER REGx(R0900_P1_FSPYBER)
3579#define F0900_P1_FSPYBER_OBSMODE 0xf5b20020 3787#define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010
3580#define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010 3788#define F0900_P1_FSPYBER_UNSYNC 0xf5b20008
3581#define F0900_P1_FSPYBER_UNSYNC 0xf5b20008 3789#define F0900_P1_FSPYBER_CTIME 0xf5b20007
3582#define F0900_P1_FSPYBER_CTIME 0xf5b20007 3790
3583 3791/*RCCFG2*/
3584/*RCCFGH*/ 3792#define R0900_RCCFG2 0xf600
3585#define R0900_RCCFGH 0xf600
3586#define F0900_TSRCFIFO_DVBCI 0xf6000080
3587#define F0900_TSRCFIFO_SERIAL 0xf6000040
3588#define F0900_TSRCFIFO_DISABLE 0xf6000020
3589#define F0900_TSFIFO_2TORC 0xf6000010
3590#define F0900_TSRCFIFO_HSGNLOUT 0xf6000008
3591#define F0900_TSRCFIFO_ERRMODE 0xf6000006
3592 3793
3593/*TSGENERAL*/ 3794/*TSGENERAL*/
3594#define R0900_TSGENERAL 0xf630 3795#define R0900_TSGENERAL 0xf630
3595#define F0900_TSFIFO_BCLK1ALL 0xf6300020 3796#define F0900_TSFIFO_DISTS2PAR 0xf6300040
3596#define F0900_MUXSTREAM_OUTMODE 0xf6300008 3797#define F0900_MUXSTREAM_OUTMODE 0xf6300008
3597#define F0900_TSFIFO_PERMPARAL 0xf6300006 3798#define F0900_TSFIFO_PERMPARAL 0xf6300006
3598#define F0900_RST_REEDSOLO 0xf6300001
3599 3799
3600/*TSGENERAL1X*/ 3800/*TSGENERAL1X*/
3601#define R0900_TSGENERAL1X 0xf670 3801#define R0900_TSGENERAL1X 0xf670
3602#define F0900_TSFIFO1X_BCLK1ALL 0xf6700020
3603#define F0900_MUXSTREAM1X_OUTMODE 0xf6700008
3604#define F0900_TSFIFO1X_PERMPARAL 0xf6700006
3605#define F0900_RST1X_REEDSOLO 0xf6700001
3606 3802
3607/*NBITER_NF4*/ 3803/*NBITER_NF4*/
3608#define R0900_NBITER_NF4 0xfa03 3804#define R0900_NBITER_NF4 0xfa03
3609#define F0900_NBITER_NF_QP_1_2 0xfa0300ff 3805#define F0900_NBITER_NF_QP_1_2 0xfa0300ff
3610 3806
3611/*NBITER_NF5*/ 3807/*NBITER_NF5*/
3612#define R0900_NBITER_NF5 0xfa04 3808#define R0900_NBITER_NF5 0xfa04
3613#define F0900_NBITER_NF_QP_3_5 0xfa0400ff 3809#define F0900_NBITER_NF_QP_3_5 0xfa0400ff
3614 3810
3615/*NBITER_NF6*/ 3811/*NBITER_NF6*/
3616#define R0900_NBITER_NF6 0xfa05 3812#define R0900_NBITER_NF6 0xfa05
3617#define F0900_NBITER_NF_QP_2_3 0xfa0500ff 3813#define F0900_NBITER_NF_QP_2_3 0xfa0500ff
3618 3814
3619/*NBITER_NF7*/ 3815/*NBITER_NF7*/
3620#define R0900_NBITER_NF7 0xfa06 3816#define R0900_NBITER_NF7 0xfa06
3621#define F0900_NBITER_NF_QP_3_4 0xfa0600ff 3817#define F0900_NBITER_NF_QP_3_4 0xfa0600ff
3622 3818
3623/*NBITER_NF8*/ 3819/*NBITER_NF8*/
3624#define R0900_NBITER_NF8 0xfa07 3820#define R0900_NBITER_NF8 0xfa07
3625#define F0900_NBITER_NF_QP_4_5 0xfa0700ff 3821#define F0900_NBITER_NF_QP_4_5 0xfa0700ff
3626 3822
3627/*NBITER_NF9*/ 3823/*NBITER_NF9*/
3628#define R0900_NBITER_NF9 0xfa08 3824#define R0900_NBITER_NF9 0xfa08
3629#define F0900_NBITER_NF_QP_5_6 0xfa0800ff 3825#define F0900_NBITER_NF_QP_5_6 0xfa0800ff
3630 3826
3631/*NBITER_NF10*/ 3827/*NBITER_NF10*/
3632#define R0900_NBITER_NF10 0xfa09 3828#define R0900_NBITER_NF10 0xfa09
3633#define F0900_NBITER_NF_QP_8_9 0xfa0900ff 3829#define F0900_NBITER_NF_QP_8_9 0xfa0900ff
3634 3830
3635/*NBITER_NF11*/ 3831/*NBITER_NF11*/
3636#define R0900_NBITER_NF11 0xfa0a 3832#define R0900_NBITER_NF11 0xfa0a
3637#define F0900_NBITER_NF_QP_9_10 0xfa0a00ff 3833#define F0900_NBITER_NF_QP_9_10 0xfa0a00ff
3638 3834
3639/*NBITER_NF12*/ 3835/*NBITER_NF12*/
3640#define R0900_NBITER_NF12 0xfa0b 3836#define R0900_NBITER_NF12 0xfa0b
3641#define F0900_NBITER_NF_8P_3_5 0xfa0b00ff 3837#define F0900_NBITER_NF_8P_3_5 0xfa0b00ff
3642 3838
3643/*NBITER_NF13*/ 3839/*NBITER_NF13*/
3644#define R0900_NBITER_NF13 0xfa0c 3840#define R0900_NBITER_NF13 0xfa0c
3645#define F0900_NBITER_NF_8P_2_3 0xfa0c00ff 3841#define F0900_NBITER_NF_8P_2_3 0xfa0c00ff
3646 3842
3647/*NBITER_NF14*/ 3843/*NBITER_NF14*/
3648#define R0900_NBITER_NF14 0xfa0d 3844#define R0900_NBITER_NF14 0xfa0d
3649#define F0900_NBITER_NF_8P_3_4 0xfa0d00ff 3845#define F0900_NBITER_NF_8P_3_4 0xfa0d00ff
3650 3846
3651/*NBITER_NF15*/ 3847/*NBITER_NF15*/
3652#define R0900_NBITER_NF15 0xfa0e 3848#define R0900_NBITER_NF15 0xfa0e
3653#define F0900_NBITER_NF_8P_5_6 0xfa0e00ff 3849#define F0900_NBITER_NF_8P_5_6 0xfa0e00ff
3654 3850
3655/*NBITER_NF16*/ 3851/*NBITER_NF16*/
3656#define R0900_NBITER_NF16 0xfa0f 3852#define R0900_NBITER_NF16 0xfa0f
3657#define F0900_NBITER_NF_8P_8_9 0xfa0f00ff 3853#define F0900_NBITER_NF_8P_8_9 0xfa0f00ff
3658 3854
3659/*NBITER_NF17*/ 3855/*NBITER_NF17*/
3660#define R0900_NBITER_NF17 0xfa10 3856#define R0900_NBITER_NF17 0xfa10
3661#define F0900_NBITER_NF_8P_9_10 0xfa1000ff 3857#define F0900_NBITER_NF_8P_9_10 0xfa1000ff
3662 3858
3663/*NBITERNOERR*/ 3859/*NBITERNOERR*/
3664#define R0900_NBITERNOERR 0xfa3f 3860#define R0900_NBITERNOERR 0xfa3f
3665#define F0900_NBITER_STOP_CRIT 0xfa3f000f 3861#define F0900_NBITER_STOP_CRIT 0xfa3f000f
3666 3862
3667/*GAINLLR_NF4*/ 3863/*GAINLLR_NF4*/
3668#define R0900_GAINLLR_NF4 0xfa43 3864#define R0900_GAINLLR_NF4 0xfa43
3669#define F0900_GAINLLR_NF_QP_1_2 0xfa43007f 3865#define F0900_GAINLLR_NF_QP_1_2 0xfa43007f
3670 3866
3671/*GAINLLR_NF5*/ 3867/*GAINLLR_NF5*/
3672#define R0900_GAINLLR_NF5 0xfa44 3868#define R0900_GAINLLR_NF5 0xfa44
3673#define F0900_GAINLLR_NF_QP_3_5 0xfa44007f 3869#define F0900_GAINLLR_NF_QP_3_5 0xfa44007f
3674 3870
3675/*GAINLLR_NF6*/ 3871/*GAINLLR_NF6*/
3676#define R0900_GAINLLR_NF6 0xfa45 3872#define R0900_GAINLLR_NF6 0xfa45
3677#define F0900_GAINLLR_NF_QP_2_3 0xfa45007f 3873#define F0900_GAINLLR_NF_QP_2_3 0xfa45007f
3678 3874
3679/*GAINLLR_NF7*/ 3875/*GAINLLR_NF7*/
3680#define R0900_GAINLLR_NF7 0xfa46 3876#define R0900_GAINLLR_NF7 0xfa46
3681#define F0900_GAINLLR_NF_QP_3_4 0xfa46007f 3877#define F0900_GAINLLR_NF_QP_3_4 0xfa46007f
3682 3878
3683/*GAINLLR_NF8*/ 3879/*GAINLLR_NF8*/
3684#define R0900_GAINLLR_NF8 0xfa47 3880#define R0900_GAINLLR_NF8 0xfa47
3685#define F0900_GAINLLR_NF_QP_4_5 0xfa47007f 3881#define F0900_GAINLLR_NF_QP_4_5 0xfa47007f
3686 3882
3687/*GAINLLR_NF9*/ 3883/*GAINLLR_NF9*/
3688#define R0900_GAINLLR_NF9 0xfa48 3884#define R0900_GAINLLR_NF9 0xfa48
3689#define F0900_GAINLLR_NF_QP_5_6 0xfa48007f 3885#define F0900_GAINLLR_NF_QP_5_6 0xfa48007f
3690 3886
3691/*GAINLLR_NF10*/ 3887/*GAINLLR_NF10*/
3692#define R0900_GAINLLR_NF10 0xfa49 3888#define R0900_GAINLLR_NF10 0xfa49
3693#define F0900_GAINLLR_NF_QP_8_9 0xfa49007f 3889#define F0900_GAINLLR_NF_QP_8_9 0xfa49007f
3694 3890
3695/*GAINLLR_NF11*/ 3891/*GAINLLR_NF11*/
3696#define R0900_GAINLLR_NF11 0xfa4a 3892#define R0900_GAINLLR_NF11 0xfa4a
3697#define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f 3893#define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f
3698 3894
3699/*GAINLLR_NF12*/ 3895/*GAINLLR_NF12*/
3700#define R0900_GAINLLR_NF12 0xfa4b 3896#define R0900_GAINLLR_NF12 0xfa4b
3701#define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f 3897#define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f
3702 3898
3703/*GAINLLR_NF13*/ 3899/*GAINLLR_NF13*/
3704#define R0900_GAINLLR_NF13 0xfa4c 3900#define R0900_GAINLLR_NF13 0xfa4c
3705#define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f 3901#define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f
3706 3902
3707/*GAINLLR_NF14*/ 3903/*GAINLLR_NF14*/
3708#define R0900_GAINLLR_NF14 0xfa4d 3904#define R0900_GAINLLR_NF14 0xfa4d
3709#define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f 3905#define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f
3710 3906
3711/*GAINLLR_NF15*/ 3907/*GAINLLR_NF15*/
3712#define R0900_GAINLLR_NF15 0xfa4e 3908#define R0900_GAINLLR_NF15 0xfa4e
3713#define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f 3909#define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f
3714 3910
3715/*GAINLLR_NF16*/ 3911/*GAINLLR_NF16*/
3716#define R0900_GAINLLR_NF16 0xfa4f 3912#define R0900_GAINLLR_NF16 0xfa4f
3717#define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f 3913#define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f
3718 3914
3719/*GAINLLR_NF17*/ 3915/*GAINLLR_NF17*/
3720#define R0900_GAINLLR_NF17 0xfa50 3916#define R0900_GAINLLR_NF17 0xfa50
3721#define F0900_GAINLLR_NF_8P_9_10 0xfa50007f 3917#define F0900_GAINLLR_NF_8P_9_10 0xfa50007f
3722 3918
3723/*CFGEXT*/ 3919/*CFGEXT*/
3724#define R0900_CFGEXT 0xfa80 3920#define R0900_CFGEXT 0xfa80
3725#define F0900_STAGMODE 0xfa800080 3921#define F0900_STAGMODE 0xfa800080
3726#define F0900_BYPBCH 0xfa800040 3922#define F0900_BYPBCH 0xfa800040
3727#define F0900_BYPLDPC 0xfa800020 3923#define F0900_BYPLDPC 0xfa800020
3728#define F0900_LDPCMODE 0xfa800010 3924#define F0900_LDPCMODE 0xfa800010
3729#define F0900_INVLLRSIGN 0xfa800008 3925#define F0900_INVLLRSIGN 0xfa800008
3730#define F0900_SHORTMULT 0xfa800004 3926#define F0900_SHORTMULT 0xfa800004
3731#define F0900_EXTERNTX 0xfa800001 3927#define F0900_EXTERNTX 0xfa800001
3732 3928
3733/*GENCFG*/ 3929/*GENCFG*/
3734#define R0900_GENCFG 0xfa86 3930#define R0900_GENCFG 0xfa86
3735#define F0900_BROADCAST 0xfa860010 3931#define F0900_BROADCAST 0xfa860010
3736#define F0900_NOSHFRD2 0xfa860008 3932#define F0900_PRIORITY 0xfa860002
3737#define F0900_BCHERRFLAG 0xfa860004 3933#define F0900_DDEMOD 0xfa860001
3738#define F0900_PRIORITY 0xfa860002
3739#define F0900_DDEMOD 0xfa860001
3740 3934
3741/*LDPCERR1*/ 3935/*LDPCERR1*/
3742#define R0900_LDPCERR1 0xfa96 3936#define R0900_LDPCERR1 0xfa96
3743#define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff 3937#define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff
3744 3938
3745/*LDPCERR0*/ 3939/*LDPCERR0*/
3746#define R0900_LDPCERR0 0xfa97 3940#define R0900_LDPCERR0 0xfa97
3747#define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff 3941#define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff
3748 3942
3749/*BCHERR*/ 3943/*BCHERR*/
3750#define R0900_BCHERR 0xfa98 3944#define R0900_BCHERR 0xfa98
3751#define F0900_ERRORFLAG 0xfa980010 3945#define F0900_ERRORFLAG 0xfa980010
3752#define F0900_BCH_ERRORS_COUNTER 0xfa98000f 3946#define F0900_BCH_ERRORS_COUNTER 0xfa98000f
3753 3947
3754/*TSTRES0*/ 3948/*TSTRES0*/
3755#define R0900_TSTRES0 0xff11 3949#define R0900_TSTRES0 0xff11
3756#define F0900_FRESFEC 0xff110080 3950#define F0900_FRESFEC 0xff110080
3757#define F0900_FRESTS 0xff110040 3951
3758#define F0900_FRESVIT1 0xff110020 3952/*P2_TCTL4*/
3759#define F0900_FRESVIT2 0xff110010 3953#define R0900_P2_TCTL4 0xff28
3760#define F0900_FRESSYM1 0xff110008 3954#define F0900_P2_PN4_SELECT 0xff280020
3761#define F0900_FRESSYM2 0xff110004 3955
3762#define F0900_FRESMAS 0xff110002 3956/*P1_TCTL4*/
3763#define F0900_FRESINT 0xff110001 3957#define R0900_P1_TCTL4 0xff48
3958#define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20)
3959#define F0900_P1_PN4_SELECT 0xff480020
3764 3960
3765/*P2_TSTDISRX*/ 3961/*P2_TSTDISRX*/
3766#define R0900_P2_TSTDISRX 0xff65 3962#define R0900_P2_TSTDISRX 0xff65
3767#define F0900_P2_EN_DISRX 0xff650080 3963#define F0900_P2_PIN_SELECT1 0xff650008
3768#define F0900_P2_TST_CURRSRC 0xff650040
3769#define F0900_P2_IN_DIGSIGNAL 0xff650020
3770#define F0900_P2_HIZ_CURRENTSRC 0xff650010
3771#define F0900_TST_P2_PIN_SELECT 0xff650008
3772#define F0900_P2_TST_DISRX 0xff650007
3773 3964
3774/*P1_TSTDISRX*/ 3965/*P1_TSTDISRX*/
3775#define R0900_P1_TSTDISRX 0xff67 3966#define R0900_P1_TSTDISRX 0xff67
3776#define F0900_P1_EN_DISRX 0xff670080 3967#define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2)
3777#define F0900_P1_TST_CURRSRC 0xff670040 3968#define F0900_P1_PIN_SELECT1 0xff670008
3778#define F0900_P1_IN_DIGSIGNAL 0xff670020 3969#define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000)
3779#define F0900_P1_HIZ_CURRENTSRC 0xff670010 3970
3780#define F0900_TST_P1_PIN_SELECT 0xff670008 3971#define STV0900_NBREGS 723
3781#define F0900_P1_TST_DISRX 0xff670007 3972#define STV0900_NBFIELDS 1420
3782
3783#define STV0900_NBREGS 684
3784#define STV0900_NBFIELDS 1702
3785 3973
3786#endif 3974#endif
3787 3975
diff --git a/drivers/media/dvb/frontends/stv0900_sw.c b/drivers/media/dvb/frontends/stv0900_sw.c
index 962fde1437ce..b8da87fa637f 100644
--- a/drivers/media/dvb/frontends/stv0900_sw.c
+++ b/drivers/media/dvb/frontends/stv0900_sw.c
@@ -27,56 +27,45 @@
27#include "stv0900_reg.h" 27#include "stv0900_reg.h"
28#include "stv0900_priv.h" 28#include "stv0900_priv.h"
29 29
30int stv0900_check_signal_presence(struct stv0900_internal *i_params, 30s32 shiftx(s32 x, int demod, s32 shift)
31{
32 if (demod == 1)
33 return x - shift;
34
35 return x;
36}
37
38int stv0900_check_signal_presence(struct stv0900_internal *intp,
31 enum fe_stv0900_demod_num demod) 39 enum fe_stv0900_demod_num demod)
32{ 40{
33 s32 carr_offset, 41 s32 carr_offset,
34 agc2_integr, 42 agc2_integr,
35 max_carrier; 43 max_carrier;
36 44
37 int no_signal; 45 int no_signal = FALSE;
38 46
39 switch (demod) { 47 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
40 case STV0900_DEMOD_1: 48 | stv0900_read_reg(intp, CFR1);
41 default: 49 carr_offset = ge2comp(carr_offset, 16);
42 carr_offset = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8) 50 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
43 | stv0900_read_reg(i_params, 51 | stv0900_read_reg(intp, AGC2I0);
44 R0900_P1_CFR1); 52 max_carrier = intp->srch_range[demod] / 1000;
45 carr_offset = ge2comp(carr_offset, 16);
46 agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
47 | stv0900_read_reg(i_params,
48 R0900_P1_AGC2I0);
49 max_carrier = i_params->dmd1_srch_range / 1000;
50 break;
51 case STV0900_DEMOD_2:
52 carr_offset = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
53 | stv0900_read_reg(i_params,
54 R0900_P2_CFR1);
55 carr_offset = ge2comp(carr_offset, 16);
56 agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
57 | stv0900_read_reg(i_params,
58 R0900_P2_AGC2I0);
59 max_carrier = i_params->dmd2_srch_range / 1000;
60 break;
61 }
62 53
63 max_carrier += (max_carrier / 10); 54 max_carrier += (max_carrier / 10);
64 max_carrier = 65536 * (max_carrier / 2); 55 max_carrier = 65536 * (max_carrier / 2);
65 max_carrier /= i_params->mclk / 1000; 56 max_carrier /= intp->mclk / 1000;
66 if (max_carrier > 0x4000) 57 if (max_carrier > 0x4000)
67 max_carrier = 0x4000; 58 max_carrier = 0x4000;
68 59
69 if ((agc2_integr > 0x2000) 60 if ((agc2_integr > 0x2000)
70 || (carr_offset > + 2*max_carrier) 61 || (carr_offset > (2 * max_carrier))
71 || (carr_offset < -2*max_carrier)) 62 || (carr_offset < (-2 * max_carrier)))
72 no_signal = TRUE; 63 no_signal = TRUE;
73 else
74 no_signal = FALSE;
75 64
76 return no_signal; 65 return no_signal;
77} 66}
78 67
79static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params, 68static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
80 s32 *frequency_inc, s32 *sw_timeout, 69 s32 *frequency_inc, s32 *sw_timeout,
81 s32 *steps, 70 s32 *steps,
82 enum fe_stv0900_demod_num demod) 71 enum fe_stv0900_demod_num demod)
@@ -85,30 +74,19 @@ static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
85 74
86 enum fe_stv0900_search_standard standard; 75 enum fe_stv0900_search_standard standard;
87 76
88 switch (demod) { 77 srate = intp->symbol_rate[demod];
89 case STV0900_DEMOD_1: 78 max_carrier = intp->srch_range[demod] / 1000;
90 default: 79 max_carrier += max_carrier / 10;
91 srate = i_params->dmd1_symbol_rate; 80 standard = intp->srch_standard[demod];
92 max_carrier = i_params->dmd1_srch_range / 1000;
93 max_carrier += max_carrier / 10;
94 standard = i_params->dmd1_srch_standard;
95 break;
96 case STV0900_DEMOD_2:
97 srate = i_params->dmd2_symbol_rate;
98 max_carrier = i_params->dmd2_srch_range / 1000;
99 max_carrier += max_carrier / 10;
100 standard = i_params->dmd2_srch_stndrd;
101 break;
102 }
103 81
104 max_carrier = 65536 * (max_carrier / 2); 82 max_carrier = 65536 * (max_carrier / 2);
105 max_carrier /= i_params->mclk / 1000; 83 max_carrier /= intp->mclk / 1000;
106 84
107 if (max_carrier > 0x4000) 85 if (max_carrier > 0x4000)
108 max_carrier = 0x4000; 86 max_carrier = 0x4000;
109 87
110 freq_inc = srate; 88 freq_inc = srate;
111 freq_inc /= i_params->mclk >> 10; 89 freq_inc /= intp->mclk >> 10;
112 freq_inc = freq_inc << 6; 90 freq_inc = freq_inc << 6;
113 91
114 switch (standard) { 92 switch (standard) {
@@ -154,7 +132,7 @@ static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
154 132
155} 133}
156 134
157static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params, 135static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
158 s32 FreqIncr, s32 Timeout, int zigzag, 136 s32 FreqIncr, s32 Timeout, int zigzag,
159 s32 MaxStep, enum fe_stv0900_demod_num demod) 137 s32 MaxStep, enum fe_stv0900_demod_num demod)
160{ 138{
@@ -164,20 +142,11 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
164 freqOffset, 142 freqOffset,
165 max_carrier; 143 max_carrier;
166 144
167 switch (demod) { 145 max_carrier = intp->srch_range[demod] / 1000;
168 case STV0900_DEMOD_1: 146 max_carrier += (max_carrier / 10);
169 default:
170 max_carrier = i_params->dmd1_srch_range / 1000;
171 max_carrier += (max_carrier / 10);
172 break;
173 case STV0900_DEMOD_2:
174 max_carrier = i_params->dmd2_srch_range / 1000;
175 max_carrier += (max_carrier / 10);
176 break;
177 }
178 147
179 max_carrier = 65536 * (max_carrier / 2); 148 max_carrier = 65536 * (max_carrier / 2);
180 max_carrier /= i_params->mclk / 1000; 149 max_carrier /= intp->mclk / 1000;
181 150
182 if (max_carrier > 0x4000) 151 if (max_carrier > 0x4000)
183 max_carrier = 0x4000; 152 max_carrier = 0x4000;
@@ -190,40 +159,15 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
190 stepCpt = 0; 159 stepCpt = 0;
191 160
192 do { 161 do {
193 switch (demod) { 162 stv0900_write_reg(intp, DMDISTATE, 0x1c);
194 case STV0900_DEMOD_1: 163 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
195 default: 164 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
196 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C); 165 stv0900_write_reg(intp, DMDISTATE, 0x18);
197 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 166 stv0900_write_bits(intp, ALGOSWRST, 1);
198 (freqOffset / 256) & 0xFF); 167
199 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 168 if (intp->chip_id == 0x12) {
200 freqOffset & 0xFF); 169 stv0900_write_bits(intp, RST_HWARE, 1);
201 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 170 stv0900_write_bits(intp, RST_HWARE, 0);
202 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
203
204 if (i_params->chip_id == 0x12) {
205 stv0900_write_bits(i_params,
206 F0900_P1_RST_HWARE, 1);
207 stv0900_write_bits(i_params,
208 F0900_P1_RST_HWARE, 0);
209 }
210 break;
211 case STV0900_DEMOD_2:
212 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
213 stv0900_write_reg(i_params, R0900_P2_CFRINIT1,
214 (freqOffset / 256) & 0xFF);
215 stv0900_write_reg(i_params, R0900_P2_CFRINIT0,
216 freqOffset & 0xFF);
217 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
218 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
219
220 if (i_params->chip_id == 0x12) {
221 stv0900_write_bits(i_params,
222 F0900_P2_RST_HWARE, 1);
223 stv0900_write_bits(i_params,
224 F0900_P2_RST_HWARE, 0);
225 }
226 break;
227 } 171 }
228 172
229 if (zigzag == TRUE) { 173 if (zigzag == TRUE) {
@@ -235,8 +179,8 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
235 freqOffset += + 2 * FreqIncr; 179 freqOffset += + 2 * FreqIncr;
236 180
237 stepCpt++; 181 stepCpt++;
238 lock = stv0900_get_demod_lock(i_params, demod, Timeout); 182 lock = stv0900_get_demod_lock(intp, demod, Timeout);
239 no_signal = stv0900_check_signal_presence(i_params, demod); 183 no_signal = stv0900_check_signal_presence(intp, demod);
240 184
241 } while ((lock == FALSE) 185 } while ((lock == FALSE)
242 && (no_signal == FALSE) 186 && (no_signal == FALSE)
@@ -244,269 +188,138 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
244 && ((freqOffset + FreqIncr) > -max_carrier) 188 && ((freqOffset + FreqIncr) > -max_carrier)
245 && (stepCpt < MaxStep)); 189 && (stepCpt < MaxStep));
246 190
247 switch (demod) { 191 stv0900_write_bits(intp, ALGOSWRST, 0);
248 case STV0900_DEMOD_1:
249 default:
250 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
251 break;
252 case STV0900_DEMOD_2:
253 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
254 break;
255 }
256 192
257 return lock; 193 return lock;
258} 194}
259 195
260int stv0900_sw_algo(struct stv0900_internal *i_params, 196int stv0900_sw_algo(struct stv0900_internal *intp,
261 enum fe_stv0900_demod_num demod) 197 enum fe_stv0900_demod_num demod)
262{ 198{
263 int lock = FALSE; 199 int lock = FALSE,
264 200 no_signal,
265 int no_signal, 201 zigzag;
266 zigzag; 202 s32 s2fw,
267 s32 dvbs2_fly_wheel; 203 fqc_inc,
268 204 sft_stp_tout,
269 s32 freqIncrement, softStepTimeout, trialCounter, max_steps; 205 trial_cntr,
270 206 max_steps;
271 stv0900_get_sw_loop_params(i_params, &freqIncrement, &softStepTimeout, 207
208 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
272 &max_steps, demod); 209 &max_steps, demod);
273 switch (demod) { 210 switch (intp->srch_standard[demod]) {
274 case STV0900_DEMOD_1: 211 case STV0900_SEARCH_DVBS1:
275 default: 212 case STV0900_SEARCH_DSS:
276 switch (i_params->dmd1_srch_standard) { 213 if (intp->chip_id >= 0x20)
277 case STV0900_SEARCH_DVBS1: 214 stv0900_write_reg(intp, CARFREQ, 0x3b);
278 case STV0900_SEARCH_DSS: 215 else
279 if (i_params->chip_id >= 0x20) 216 stv0900_write_reg(intp, CARFREQ, 0xef);
280 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
281 0x3B);
282 else
283 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
284 0xef);
285
286 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x49);
287 zigzag = FALSE;
288 break;
289 case STV0900_SEARCH_DVBS2:
290 if (i_params->chip_id >= 0x20)
291 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
292 0x79);
293 else
294 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
295 0x68);
296 217
297 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 218 stv0900_write_reg(intp, DMDCFGMD, 0x49);
298 0x89); 219 zigzag = FALSE;
220 break;
221 case STV0900_SEARCH_DVBS2:
222 if (intp->chip_id >= 0x20)
223 stv0900_write_reg(intp, CORRELABS, 0x79);
224 else
225 stv0900_write_reg(intp, CORRELABS, 0x68);
299 226
300 zigzag = TRUE; 227 stv0900_write_reg(intp, DMDCFGMD, 0x89);
301 break;
302 case STV0900_AUTO_SEARCH:
303 default:
304 if (i_params->chip_id >= 0x20) {
305 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
306 0x3B);
307 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
308 0x79);
309 } else {
310 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
311 0xef);
312 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
313 0x68);
314 }
315 228
316 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 229 zigzag = TRUE;
317 0xc9); 230 break;
318 zigzag = FALSE; 231 case STV0900_AUTO_SEARCH:
319 break; 232 default:
233 if (intp->chip_id >= 0x20) {
234 stv0900_write_reg(intp, CARFREQ, 0x3b);
235 stv0900_write_reg(intp, CORRELABS, 0x79);
236 } else {
237 stv0900_write_reg(intp, CARFREQ, 0xef);
238 stv0900_write_reg(intp, CORRELABS, 0x68);
320 } 239 }
321 240
322 trialCounter = 0; 241 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
323 do { 242 zigzag = FALSE;
324 lock = stv0900_search_carr_sw_loop(i_params,
325 freqIncrement,
326 softStepTimeout,
327 zigzag,
328 max_steps,
329 demod);
330 no_signal = stv0900_check_signal_presence(i_params,
331 demod);
332 trialCounter++;
333 if ((lock == TRUE)
334 || (no_signal == TRUE)
335 || (trialCounter == 2)) {
336
337 if (i_params->chip_id >= 0x20) {
338 stv0900_write_reg(i_params,
339 R0900_P1_CARFREQ,
340 0x49);
341 stv0900_write_reg(i_params,
342 R0900_P1_CORRELABS,
343 0x9e);
344 } else {
345 stv0900_write_reg(i_params,
346 R0900_P1_CARFREQ,
347 0xed);
348 stv0900_write_reg(i_params,
349 R0900_P1_CORRELABS,
350 0x88);
351 }
352
353 if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
354 msleep(softStepTimeout);
355 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
356
357 if (dvbs2_fly_wheel < 0xd) {
358 msleep(softStepTimeout);
359 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
360 }
361
362 if (dvbs2_fly_wheel < 0xd) {
363 lock = FALSE;
364
365 if (trialCounter < 2) {
366 if (i_params->chip_id >= 0x20)
367 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x79);
368 else
369 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x68);
370
371 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x89);
372 }
373 }
374 }
375 }
376
377 } while ((lock == FALSE)
378 && (trialCounter < 2)
379 && (no_signal == FALSE));
380
381 break; 243 break;
382 case STV0900_DEMOD_2: 244 }
383 switch (i_params->dmd2_srch_stndrd) {
384 case STV0900_SEARCH_DVBS1:
385 case STV0900_SEARCH_DSS:
386 if (i_params->chip_id >= 0x20)
387 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
388 0x3b);
389 else
390 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
391 0xef);
392
393 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD,
394 0x49);
395 zigzag = FALSE;
396 break;
397 case STV0900_SEARCH_DVBS2:
398 if (i_params->chip_id >= 0x20)
399 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
400 0x79);
401 else
402 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
403 0x68);
404 245
405 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89); 246 trial_cntr = 0;
406 zigzag = TRUE; 247 do {
407 break; 248 lock = stv0900_search_carr_sw_loop(intp,
408 case STV0900_AUTO_SEARCH: 249 fqc_inc,
409 default: 250 sft_stp_tout,
410 if (i_params->chip_id >= 0x20) { 251 zigzag,
411 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 252 max_steps,
412 0x3b); 253 demod);
413 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 254 no_signal = stv0900_check_signal_presence(intp, demod);
414 0x79); 255 trial_cntr++;
256 if ((lock == TRUE)
257 || (no_signal == TRUE)
258 || (trial_cntr == 2)) {
259
260 if (intp->chip_id >= 0x20) {
261 stv0900_write_reg(intp, CARFREQ, 0x49);
262 stv0900_write_reg(intp, CORRELABS, 0x9e);
415 } else { 263 } else {
416 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 264 stv0900_write_reg(intp, CARFREQ, 0xed);
417 0xef); 265 stv0900_write_reg(intp, CORRELABS, 0x88);
418 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
419 0x68);
420 } 266 }
421 267
422 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0xc9); 268 if ((stv0900_get_bits(intp, HEADER_MODE) ==
423 269 STV0900_DVBS2_FOUND) &&
424 zigzag = FALSE; 270 (lock == TRUE)) {
425 break; 271 msleep(sft_stp_tout);
426 } 272 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
427 273
428 trialCounter = 0; 274 if (s2fw < 0xd) {
429 275 msleep(sft_stp_tout);
430 do { 276 s2fw = stv0900_get_bits(intp,
431 lock = stv0900_search_carr_sw_loop(i_params, 277 FLYWHEEL_CPT);
432 freqIncrement,
433 softStepTimeout,
434 zigzag,
435 max_steps,
436 demod);
437 no_signal = stv0900_check_signal_presence(i_params,
438 demod);
439 trialCounter++;
440 if ((lock == TRUE)
441 || (no_signal == TRUE)
442 || (trialCounter == 2)) {
443 if (i_params->chip_id >= 0x20) {
444 stv0900_write_reg(i_params,
445 R0900_P2_CARFREQ,
446 0x49);
447 stv0900_write_reg(i_params,
448 R0900_P2_CORRELABS,
449 0x9e);
450 } else {
451 stv0900_write_reg(i_params,
452 R0900_P2_CARFREQ,
453 0xed);
454 stv0900_write_reg(i_params,
455 R0900_P2_CORRELABS,
456 0x88);
457 } 278 }
458 279
459 if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS2_FOUND)) { 280 if (s2fw < 0xd) {
460 msleep(softStepTimeout); 281 lock = FALSE;
461 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
462 if (dvbs2_fly_wheel < 0xd) {
463 msleep(softStepTimeout);
464 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
465 }
466 282
467 if (dvbs2_fly_wheel < 0xd) { 283 if (trial_cntr < 2) {
468 lock = FALSE; 284 if (intp->chip_id >= 0x20)
469 if (trialCounter < 2) { 285 stv0900_write_reg(intp,
470 if (i_params->chip_id >= 0x20) 286 CORRELABS,
471 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x79); 287 0x79);
472 else 288 else
473 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x68); 289 stv0900_write_reg(intp,
290 CORRELABS,
291 0x68);
474 292
475 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89); 293 stv0900_write_reg(intp,
476 } 294 DMDCFGMD,
295 0x89);
477 } 296 }
478 } 297 }
479 } 298 }
299 }
480 300
481 } while ((lock == FALSE) && (trialCounter < 2) && (no_signal == FALSE)); 301 } while ((lock == FALSE)
482 302 && (trial_cntr < 2)
483 break; 303 && (no_signal == FALSE));
484 }
485 304
486 return lock; 305 return lock;
487} 306}
488 307
489static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params, 308static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
490 u32 mclk, 309 u32 mclk,
491 enum fe_stv0900_demod_num demod) 310 enum fe_stv0900_demod_num demod)
492{ 311{
493 s32 sfr_field3, sfr_field2, sfr_field1, sfr_field0, 312 s32 rem1, rem2, intval1, intval2, srate;
494 rem1, rem2, intval1, intval2, srate; 313
495 314 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
496 dmd_reg(sfr_field3, F0900_P1_SYMB_FREQ3, F0900_P2_SYMB_FREQ3); 315 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
497 dmd_reg(sfr_field2, F0900_P1_SYMB_FREQ2, F0900_P2_SYMB_FREQ2); 316 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
498 dmd_reg(sfr_field1, F0900_P1_SYMB_FREQ1, F0900_P2_SYMB_FREQ1); 317 (stv0900_get_bits(intp, SYMB_FREQ0));
499 dmd_reg(sfr_field0, F0900_P1_SYMB_FREQ0, F0900_P2_SYMB_FREQ0);
500
501 srate = (stv0900_get_bits(i_params, sfr_field3) << 24) +
502 (stv0900_get_bits(i_params, sfr_field2) << 16) +
503 (stv0900_get_bits(i_params, sfr_field1) << 8) +
504 (stv0900_get_bits(i_params, sfr_field0));
505 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n", 318 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
506 srate, stv0900_get_bits(i_params, sfr_field0), 319 srate, stv0900_get_bits(intp, SYMB_FREQ0),
507 stv0900_get_bits(i_params, sfr_field1), 320 stv0900_get_bits(intp, SYMB_FREQ1),
508 stv0900_get_bits(i_params, sfr_field2), 321 stv0900_get_bits(intp, SYMB_FREQ2),
509 stv0900_get_bits(i_params, sfr_field3)); 322 stv0900_get_bits(intp, SYMB_FREQ3));
510 323
511 intval1 = (mclk) >> 16; 324 intval1 = (mclk) >> 16;
512 intval2 = (srate) >> 16; 325 intval2 = (srate) >> 16;
@@ -520,18 +333,15 @@ static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params,
520 return srate; 333 return srate;
521} 334}
522 335
523static void stv0900_set_symbol_rate(struct stv0900_internal *i_params, 336static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
524 u32 mclk, u32 srate, 337 u32 mclk, u32 srate,
525 enum fe_stv0900_demod_num demod) 338 enum fe_stv0900_demod_num demod)
526{ 339{
527 s32 sfr_init_reg;
528 u32 symb; 340 u32 symb;
529 341
530 dprintk(KERN_INFO "%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk, 342 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
531 srate, demod); 343 srate, demod);
532 344
533 dmd_reg(sfr_init_reg, R0900_P1_SFRINIT1, R0900_P2_SFRINIT1);
534
535 if (srate > 60000000) { 345 if (srate > 60000000) {
536 symb = srate << 4; 346 symb = srate << 4;
537 symb /= (mclk >> 12); 347 symb /= (mclk >> 12);
@@ -543,19 +353,16 @@ static void stv0900_set_symbol_rate(struct stv0900_internal *i_params,
543 symb /= (mclk >> 7); 353 symb /= (mclk >> 7);
544 } 354 }
545 355
546 stv0900_write_reg(i_params, sfr_init_reg, (symb >> 8) & 0x7F); 356 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
547 stv0900_write_reg(i_params, sfr_init_reg + 1, (symb & 0xFF)); 357 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
548} 358}
549 359
550static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params, 360static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
551 u32 mclk, u32 srate, 361 u32 mclk, u32 srate,
552 enum fe_stv0900_demod_num demod) 362 enum fe_stv0900_demod_num demod)
553{ 363{
554 s32 sfr_max_reg;
555 u32 symb; 364 u32 symb;
556 365
557 dmd_reg(sfr_max_reg, R0900_P1_SFRUP1, R0900_P2_SFRUP1);
558
559 srate = 105 * (srate / 100); 366 srate = 105 * (srate / 100);
560 367
561 if (srate > 60000000) { 368 if (srate > 60000000) {
@@ -570,23 +377,20 @@ static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params,
570 } 377 }
571 378
572 if (symb < 0x7fff) { 379 if (symb < 0x7fff) {
573 stv0900_write_reg(i_params, sfr_max_reg, (symb >> 8) & 0x7F); 380 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
574 stv0900_write_reg(i_params, sfr_max_reg + 1, (symb & 0xFF)); 381 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
575 } else { 382 } else {
576 stv0900_write_reg(i_params, sfr_max_reg, 0x7F); 383 stv0900_write_reg(intp, SFRUP1, 0x7f);
577 stv0900_write_reg(i_params, sfr_max_reg + 1, 0xFF); 384 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
578 } 385 }
579} 386}
580 387
581static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params, 388static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
582 u32 mclk, u32 srate, 389 u32 mclk, u32 srate,
583 enum fe_stv0900_demod_num demod) 390 enum fe_stv0900_demod_num demod)
584{ 391{
585 s32 sfr_min_reg;
586 u32 symb; 392 u32 symb;
587 393
588 dmd_reg(sfr_min_reg, R0900_P1_SFRLOW1, R0900_P2_SFRLOW1);
589
590 srate = 95 * (srate / 100); 394 srate = 95 * (srate / 100);
591 if (srate > 60000000) { 395 if (srate > 60000000) {
592 symb = srate << 4; 396 symb = srate << 4;
@@ -601,22 +405,20 @@ static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params,
601 symb /= (mclk >> 7); 405 symb /= (mclk >> 7);
602 } 406 }
603 407
604 stv0900_write_reg(i_params, sfr_min_reg, (symb >> 8) & 0xFF); 408 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
605 stv0900_write_reg(i_params, sfr_min_reg + 1, (symb & 0xFF)); 409 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
606} 410}
607 411
608static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params, 412static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
609 u32 srate, 413 u32 srate,
610 enum fe_stv0900_demod_num demod) 414 enum fe_stv0900_demod_num demod)
611{ 415{
612 s32 tmgreg, 416 s32 timingoffset;
613 timingoffset;
614 417
615 dmd_reg(tmgreg, R0900_P1_TMGREG2, R0900_P2_TMGREG2);
616 418
617 timingoffset = (stv0900_read_reg(i_params, tmgreg) << 16) + 419 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
618 (stv0900_read_reg(i_params, tmgreg + 1) << 8) + 420 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
619 (stv0900_read_reg(i_params, tmgreg + 2)); 421 (stv0900_read_reg(intp, TMGREG2 + 2));
620 422
621 timingoffset = ge2comp(timingoffset, 24); 423 timingoffset = ge2comp(timingoffset, 24);
622 424
@@ -630,22 +432,19 @@ static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params,
630 return timingoffset; 432 return timingoffset;
631} 433}
632 434
633static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *i_params, 435static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
634 enum fe_stv0900_demod_num demod) 436 enum fe_stv0900_demod_num demod)
635{ 437{
636 s32 rolloff, man_fld, matstr_reg, rolloff_ctl_fld; 438 s32 rolloff;
637 439
638 dmd_reg(man_fld, F0900_P1_MANUAL_ROLLOFF, F0900_P2_MANUAL_ROLLOFF); 440 if (intp->chip_id == 0x10) {
639 dmd_reg(matstr_reg, R0900_P1_MATSTR1, R0900_P2_MATSTR1); 441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
640 dmd_reg(rolloff_ctl_fld, F0900_P1_ROLLOFF_CONTROL, 442 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
641 F0900_P2_ROLLOFF_CONTROL); 443 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
642 444 } else if (intp->chip_id <= 0x20)
643 if (i_params->chip_id == 0x10) { 445 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
644 stv0900_write_bits(i_params, man_fld, 1); 446 else /* cut 3.0 */
645 rolloff = stv0900_read_reg(i_params, matstr_reg) & 0x03; 447 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
646 stv0900_write_bits(i_params, rolloff_ctl_fld, rolloff);
647 } else
648 stv0900_write_bits(i_params, man_fld, 0);
649} 448}
650 449
651static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro) 450static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
@@ -668,84 +467,47 @@ static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
668 return srate + (srate * rolloff) / 100; 467 return srate + (srate * rolloff) / 100;
669} 468}
670 469
671static int stv0900_check_timing_lock(struct stv0900_internal *i_params, 470static int stv0900_check_timing_lock(struct stv0900_internal *intp,
672 enum fe_stv0900_demod_num demod) 471 enum fe_stv0900_demod_num demod)
673{ 472{
674 int timingLock = FALSE; 473 int timingLock = FALSE;
675 s32 i, 474 s32 i,
676 timingcpt = 0; 475 timingcpt = 0;
677 u8 carFreq, 476 u8 car_freq,
678 tmgTHhigh, 477 tmg_th_high,
679 tmgTHLow; 478 tmg_th_low;
680 479
681 switch (demod) { 480 car_freq = stv0900_read_reg(intp, CARFREQ);
682 case STV0900_DEMOD_1: 481 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
683 default: 482 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
684 carFreq = stv0900_read_reg(i_params, R0900_P1_CARFREQ); 483 stv0900_write_reg(intp, TMGTHRISE, 0x20);
685 tmgTHhigh = stv0900_read_reg(i_params, R0900_P1_TMGTHRISE); 484 stv0900_write_reg(intp, TMGTHFALL, 0x0);
686 tmgTHLow = stv0900_read_reg(i_params, R0900_P1_TMGTHFALL); 485 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
687 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20); 486 stv0900_write_reg(intp, RTC, 0x80);
688 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x0); 487 stv0900_write_reg(intp, RTCS2, 0x40);
689 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0); 488 stv0900_write_reg(intp, CARFREQ, 0x0);
690 stv0900_write_reg(i_params, R0900_P1_RTC, 0x80); 489 stv0900_write_reg(intp, CFRINIT1, 0x0);
691 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x40); 490 stv0900_write_reg(intp, CFRINIT0, 0x0);
692 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x0); 491 stv0900_write_reg(intp, AGC2REF, 0x65);
693 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0x0); 492 stv0900_write_reg(intp, DMDISTATE, 0x18);
694 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0x0); 493 msleep(7);
695 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x65); 494
696 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 495 for (i = 0; i < 10; i++) {
697 msleep(7); 496 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
698 497 timingcpt++;
699 for (i = 0; i < 10; i++) { 498
700 if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2) 499 msleep(1);
701 timingcpt++; 500 }
702
703 msleep(1);
704 }
705
706 if (timingcpt >= 3)
707 timingLock = TRUE;
708
709 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
710 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
711 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
712 stv0900_write_reg(i_params, R0900_P1_CARFREQ, carFreq);
713 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, tmgTHhigh);
714 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, tmgTHLow);
715 break;
716 case STV0900_DEMOD_2:
717 carFreq = stv0900_read_reg(i_params, R0900_P2_CARFREQ);
718 tmgTHhigh = stv0900_read_reg(i_params, R0900_P2_TMGTHRISE);
719 tmgTHLow = stv0900_read_reg(i_params, R0900_P2_TMGTHFALL);
720 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
721 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0);
722 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
723 stv0900_write_reg(i_params, R0900_P2_RTC, 0x80);
724 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x40);
725 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x0);
726 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0x0);
727 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0x0);
728 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x65);
729 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
730 msleep(5);
731 for (i = 0; i < 10; i++) {
732 if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
733 timingcpt++;
734 501
735 msleep(1); 502 if (timingcpt >= 3)
736 } 503 timingLock = TRUE;
737 504
738 if (timingcpt >= 3) 505 stv0900_write_reg(intp, AGC2REF, 0x38);
739 timingLock = TRUE; 506 stv0900_write_reg(intp, RTC, 0x88);
740 507 stv0900_write_reg(intp, RTCS2, 0x68);
741 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38); 508 stv0900_write_reg(intp, CARFREQ, car_freq);
742 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88); 509 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
743 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68); 510 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
744 stv0900_write_reg(i_params, R0900_P2_CARFREQ, carFreq);
745 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, tmgTHhigh);
746 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, tmgTHLow);
747 break;
748 }
749 511
750 return timingLock; 512 return timingLock;
751} 513}
@@ -754,142 +516,114 @@ static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
754 s32 demod_timeout) 516 s32 demod_timeout)
755{ 517{
756 struct stv0900_state *state = fe->demodulator_priv; 518 struct stv0900_state *state = fe->demodulator_priv;
757 struct stv0900_internal *i_params = state->internal; 519 struct stv0900_internal *intp = state->internal;
758 enum fe_stv0900_demod_num demod = state->demod; 520 enum fe_stv0900_demod_num demod = state->demod;
521 int lock = FALSE,
522 d = demod;
523 s32 srate,
524 search_range,
525 locktimeout,
526 currier_step,
527 nb_steps,
528 current_step,
529 direction,
530 tuner_freq,
531 timeout,
532 freq;
759 533
760 int lock = FALSE; 534 srate = intp->symbol_rate[d];
761 s32 srate, search_range, locktimeout, 535 search_range = intp->srch_range[d];
762 currier_step, nb_steps, current_step,
763 direction, tuner_freq, timeout;
764
765 switch (demod) {
766 case STV0900_DEMOD_1:
767 default:
768 srate = i_params->dmd1_symbol_rate;
769 search_range = i_params->dmd1_srch_range;
770 break;
771
772 case STV0900_DEMOD_2:
773 srate = i_params->dmd2_symbol_rate;
774 search_range = i_params->dmd2_srch_range;
775 break;
776 }
777 536
778 if (srate >= 10000000) 537 if (srate >= 10000000)
779 locktimeout = demod_timeout / 3; 538 locktimeout = demod_timeout / 3;
780 else 539 else
781 locktimeout = demod_timeout / 2; 540 locktimeout = demod_timeout / 2;
782 541
783 lock = stv0900_get_demod_lock(i_params, demod, locktimeout); 542 lock = stv0900_get_demod_lock(intp, d, locktimeout);
784
785 if (lock == FALSE) {
786 if (srate >= 10000000) {
787 if (stv0900_check_timing_lock(i_params, demod) == TRUE) {
788 switch (demod) {
789 case STV0900_DEMOD_1:
790 default:
791 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
792 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
793 break;
794 case STV0900_DEMOD_2:
795 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
796 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
797 break;
798 }
799 543
800 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout); 544 if (lock != FALSE)
801 } else 545 return lock;
802 lock = FALSE; 546
803 } else { 547 if (srate >= 10000000) {
804 if (srate <= 4000000) 548 if (stv0900_check_timing_lock(intp, d) == TRUE) {
805 currier_step = 1000; 549 stv0900_write_reg(intp, DMDISTATE, 0x1f);
806 else if (srate <= 7000000) 550 stv0900_write_reg(intp, DMDISTATE, 0x15);
807 currier_step = 2000; 551 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
808 else if (srate <= 10000000) 552 } else
809 currier_step = 3000; 553 lock = FALSE;
810 else 554
811 currier_step = 5000; 555 return lock;
812 556 }
813 nb_steps = ((search_range / 1000) / currier_step); 557
814 nb_steps /= 2; 558 if (intp->chip_id <= 0x20) {
815 nb_steps = (2 * (nb_steps + 1)); 559 if (srate <= 1000000)
816 if (nb_steps < 0) 560 currier_step = 500;
817 nb_steps = 2; 561 else if (srate <= 4000000)
818 else if (nb_steps > 12) 562 currier_step = 1000;
819 nb_steps = 12; 563 else if (srate <= 7000000)
820 564 currier_step = 2000;
821 current_step = 1; 565 else if (srate <= 10000000)
822 direction = 1; 566 currier_step = 3000;
567 else
568 currier_step = 5000;
569
570 if (srate >= 2000000) {
823 timeout = (demod_timeout / 3); 571 timeout = (demod_timeout / 3);
824 if (timeout > 1000) 572 if (timeout > 1000)
825 timeout = 1000; 573 timeout = 1000;
574 } else
575 timeout = (demod_timeout / 2);
576 } else {
577 /*cut 3.0 */
578 currier_step = srate / 4000;
579 timeout = (demod_timeout * 3) / 4;
580 }
826 581
827 switch (demod) { 582 nb_steps = ((search_range / 1000) / currier_step);
828 case STV0900_DEMOD_1:
829 default:
830 if (lock == FALSE) {
831 tuner_freq = i_params->tuner1_freq;
832 i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + i_params->dmd1_symbol_rate;
833 583
834 while ((current_step <= nb_steps) && (lock == FALSE)) { 584 if ((nb_steps % 2) != 0)
585 nb_steps += 1;
835 586
836 if (direction > 0) 587 if (nb_steps <= 0)
837 tuner_freq += (current_step * currier_step); 588 nb_steps = 2;
838 else 589 else if (nb_steps > 12)
839 tuner_freq -= (current_step * currier_step); 590 nb_steps = 12;
840
841 stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
842 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
843 if (i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS2) {
844 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
845 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
846 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
847 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
848 }
849
850 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
851 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
852 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
853 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
854 lock = stv0900_get_demod_lock(i_params, demod, timeout);
855 direction *= -1;
856 current_step++;
857 }
858 }
859 break;
860 case STV0900_DEMOD_2:
861 if (lock == FALSE) {
862 tuner_freq = i_params->tuner2_freq;
863 i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + srate;
864 591
865 while ((current_step <= nb_steps) && (lock == FALSE)) { 592 current_step = 1;
593 direction = 1;
866 594
867 if (direction > 0) 595 if (intp->chip_id <= 0x20) {
868 tuner_freq += (current_step * currier_step); 596 tuner_freq = intp->freq[d];
869 else 597 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
870 tuner_freq -= (current_step * currier_step); 598 intp->rolloff) + intp->symbol_rate[d];
871 599 } else
872 stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw); 600 tuner_freq = 0;
873 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C); 601
874 if (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS2) { 602 while ((current_step <= nb_steps) && (lock == FALSE)) {
875 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0); 603 if (direction > 0)
876 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0); 604 tuner_freq += (current_step * currier_step);
877 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1); 605 else
878 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1); 606 tuner_freq -= (current_step * currier_step);
879 } 607
880 608 if (intp->chip_id <= 0x20) {
881 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0); 609 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
882 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0); 610 stv0900_write_reg(intp, DMDISTATE, 0x1c);
883 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F); 611 stv0900_write_reg(intp, CFRINIT1, 0);
884 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15); 612 stv0900_write_reg(intp, CFRINIT0, 0);
885 lock = stv0900_get_demod_lock(i_params, demod, timeout); 613 stv0900_write_reg(intp, DMDISTATE, 0x1f);
886 direction *= -1; 614 stv0900_write_reg(intp, DMDISTATE, 0x15);
887 current_step++; 615 } else {
888 } 616 stv0900_write_reg(intp, DMDISTATE, 0x1c);
889 } 617 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
890 break; 618 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
891 } 619 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
620 stv0900_write_reg(intp, DMDISTATE, 0x1f);
621 stv0900_write_reg(intp, DMDISTATE, 0x05);
892 } 622 }
623
624 lock = stv0900_get_demod_lock(intp, d, timeout);
625 direction *= -1;
626 current_step++;
893 } 627 }
894 628
895 return lock; 629 return lock;
@@ -931,9 +665,7 @@ static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
931 } else if (srate <= 20000000) { 665 } else if (srate <= 20000000) {
932 (*demod_timeout) = 400; 666 (*demod_timeout) = 400;
933 (*fec_timeout) = 130; 667 (*fec_timeout) = 130;
934 } 668 } else {
935
936 else {
937 (*demod_timeout) = 300; 669 (*demod_timeout) = 300;
938 (*fec_timeout) = 100; 670 (*fec_timeout) = 100;
939 } 671 }
@@ -946,95 +678,77 @@ static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
946 (*demod_timeout) /= 2; 678 (*demod_timeout) /= 2;
947} 679}
948 680
949static void stv0900_set_viterbi_tracq(struct stv0900_internal *i_params, 681static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
950 enum fe_stv0900_demod_num demod) 682 enum fe_stv0900_demod_num demod)
951{ 683{
952 684
953 s32 vth_reg; 685 s32 vth_reg = VTH12;
954 686
955 dprintk(KERN_INFO "%s\n", __func__); 687 dprintk("%s\n", __func__);
956 688
957 dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12); 689 stv0900_write_reg(intp, vth_reg++, 0xd0);
958 690 stv0900_write_reg(intp, vth_reg++, 0x7d);
959 stv0900_write_reg(i_params, vth_reg++, 0xd0); 691 stv0900_write_reg(intp, vth_reg++, 0x53);
960 stv0900_write_reg(i_params, vth_reg++, 0x7d); 692 stv0900_write_reg(intp, vth_reg++, 0x2f);
961 stv0900_write_reg(i_params, vth_reg++, 0x53); 693 stv0900_write_reg(intp, vth_reg++, 0x24);
962 stv0900_write_reg(i_params, vth_reg++, 0x2F); 694 stv0900_write_reg(intp, vth_reg++, 0x1f);
963 stv0900_write_reg(i_params, vth_reg++, 0x24);
964 stv0900_write_reg(i_params, vth_reg++, 0x1F);
965} 695}
966 696
967static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params, 697static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
968 enum fe_stv0900_search_standard Standard, 698 enum fe_stv0900_search_standard standard,
969 enum fe_stv0900_fec PunctureRate, 699 enum fe_stv0900_fec fec,
970 enum fe_stv0900_demod_num demod) 700 enum fe_stv0900_demod_num demod)
971{ 701{
702 dprintk("%s: ViterbiStandard = ", __func__);
972 703
973 s32 fecmReg, 704 switch (standard) {
974 prvitReg;
975
976 dprintk(KERN_INFO "%s: ViterbiStandard = ", __func__);
977
978 switch (demod) {
979 case STV0900_DEMOD_1:
980 default:
981 fecmReg = R0900_P1_FECM;
982 prvitReg = R0900_P1_PRVIT;
983 break;
984 case STV0900_DEMOD_2:
985 fecmReg = R0900_P2_FECM;
986 prvitReg = R0900_P2_PRVIT;
987 break;
988 }
989
990 switch (Standard) {
991 case STV0900_AUTO_SEARCH: 705 case STV0900_AUTO_SEARCH:
992 dprintk("Auto\n"); 706 dprintk("Auto\n");
993 stv0900_write_reg(i_params, fecmReg, 0x10); 707 stv0900_write_reg(intp, FECM, 0x10);
994 stv0900_write_reg(i_params, prvitReg, 0x3F); 708 stv0900_write_reg(intp, PRVIT, 0x3f);
995 break; 709 break;
996 case STV0900_SEARCH_DVBS1: 710 case STV0900_SEARCH_DVBS1:
997 dprintk("DVBS1\n"); 711 dprintk("DVBS1\n");
998 stv0900_write_reg(i_params, fecmReg, 0x00); 712 stv0900_write_reg(intp, FECM, 0x00);
999 switch (PunctureRate) { 713 switch (fec) {
1000 case STV0900_FEC_UNKNOWN: 714 case STV0900_FEC_UNKNOWN:
1001 default: 715 default:
1002 stv0900_write_reg(i_params, prvitReg, 0x2F); 716 stv0900_write_reg(intp, PRVIT, 0x2f);
1003 break; 717 break;
1004 case STV0900_FEC_1_2: 718 case STV0900_FEC_1_2:
1005 stv0900_write_reg(i_params, prvitReg, 0x01); 719 stv0900_write_reg(intp, PRVIT, 0x01);
1006 break; 720 break;
1007 case STV0900_FEC_2_3: 721 case STV0900_FEC_2_3:
1008 stv0900_write_reg(i_params, prvitReg, 0x02); 722 stv0900_write_reg(intp, PRVIT, 0x02);
1009 break; 723 break;
1010 case STV0900_FEC_3_4: 724 case STV0900_FEC_3_4:
1011 stv0900_write_reg(i_params, prvitReg, 0x04); 725 stv0900_write_reg(intp, PRVIT, 0x04);
1012 break; 726 break;
1013 case STV0900_FEC_5_6: 727 case STV0900_FEC_5_6:
1014 stv0900_write_reg(i_params, prvitReg, 0x08); 728 stv0900_write_reg(intp, PRVIT, 0x08);
1015 break; 729 break;
1016 case STV0900_FEC_7_8: 730 case STV0900_FEC_7_8:
1017 stv0900_write_reg(i_params, prvitReg, 0x20); 731 stv0900_write_reg(intp, PRVIT, 0x20);
1018 break; 732 break;
1019 } 733 }
1020 734
1021 break; 735 break;
1022 case STV0900_SEARCH_DSS: 736 case STV0900_SEARCH_DSS:
1023 dprintk("DSS\n"); 737 dprintk("DSS\n");
1024 stv0900_write_reg(i_params, fecmReg, 0x80); 738 stv0900_write_reg(intp, FECM, 0x80);
1025 switch (PunctureRate) { 739 switch (fec) {
1026 case STV0900_FEC_UNKNOWN: 740 case STV0900_FEC_UNKNOWN:
1027 default: 741 default:
1028 stv0900_write_reg(i_params, prvitReg, 0x13); 742 stv0900_write_reg(intp, PRVIT, 0x13);
1029 break; 743 break;
1030 case STV0900_FEC_1_2: 744 case STV0900_FEC_1_2:
1031 stv0900_write_reg(i_params, prvitReg, 0x01); 745 stv0900_write_reg(intp, PRVIT, 0x01);
1032 break; 746 break;
1033 case STV0900_FEC_2_3: 747 case STV0900_FEC_2_3:
1034 stv0900_write_reg(i_params, prvitReg, 0x02); 748 stv0900_write_reg(intp, PRVIT, 0x02);
1035 break; 749 break;
1036 case STV0900_FEC_6_7: 750 case STV0900_FEC_6_7:
1037 stv0900_write_reg(i_params, prvitReg, 0x10); 751 stv0900_write_reg(intp, PRVIT, 0x10);
1038 break; 752 break;
1039 } 753 }
1040 break; 754 break;
@@ -1043,340 +757,277 @@ static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params,
1043 } 757 }
1044} 758}
1045 759
1046static void stv0900_track_optimization(struct dvb_frontend *fe) 760static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
761 enum fe_stv0900_demod_num demod)
1047{ 762{
1048 struct stv0900_state *state = fe->demodulator_priv; 763 enum fe_stv0900_fec prate;
1049 struct stv0900_internal *i_params = state->internal; 764 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
1050 enum fe_stv0900_demod_num demod = state->demod;
1051 765
1052 s32 srate, pilots, aclc, freq1, freq0, 766 switch (rate_fld) {
1053 i = 0, timed, timef, blindTunSw = 0; 767 case 13:
768 prate = STV0900_FEC_1_2;
769 break;
770 case 18:
771 prate = STV0900_FEC_2_3;
772 break;
773 case 21:
774 prate = STV0900_FEC_3_4;
775 break;
776 case 24:
777 prate = STV0900_FEC_5_6;
778 break;
779 case 25:
780 prate = STV0900_FEC_6_7;
781 break;
782 case 26:
783 prate = STV0900_FEC_7_8;
784 break;
785 default:
786 prate = STV0900_FEC_UNKNOWN;
787 break;
788 }
1054 789
1055 enum fe_stv0900_rolloff rolloff; 790 return prate;
1056 enum fe_stv0900_modcode foundModcod; 791}
1057 792
1058 dprintk(KERN_INFO "%s\n", __func__); 793void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
794 enum fe_stv0900_demod_num demod,
795 u32 srate)
796{
797 if (intp->chip_id >= 0x30) {
798 if (srate >= 15000000) {
799 stv0900_write_reg(intp, ACLC, 0x2b);
800 stv0900_write_reg(intp, BCLC, 0x1a);
801 } else if ((srate >= 7000000) && (15000000 > srate)) {
802 stv0900_write_reg(intp, ACLC, 0x0c);
803 stv0900_write_reg(intp, BCLC, 0x1b);
804 } else if (srate < 7000000) {
805 stv0900_write_reg(intp, ACLC, 0x2c);
806 stv0900_write_reg(intp, BCLC, 0x1c);
807 }
1059 808
1060 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod); 809 } else { /*cut 2.0 and 1.x*/
1061 srate += stv0900_get_timing_offst(i_params, srate, demod); 810 stv0900_write_reg(intp, ACLC, 0x1a);
811 stv0900_write_reg(intp, BCLC, 0x09);
812 }
1062 813
1063 switch (demod) { 814}
1064 case STV0900_DEMOD_1:
1065 default:
1066 switch (i_params->dmd1_rslts.standard) {
1067 case STV0900_DVBS1_STANDARD:
1068 if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
1069 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1070 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
1071 }
1072 815
1073 stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff); 816static void stv0900_track_optimization(struct dvb_frontend *fe)
1074 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1); 817{
1075 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75); 818 struct stv0900_state *state = fe->demodulator_priv;
1076 break; 819 struct stv0900_internal *intp = state->internal;
1077 case STV0900_DSS_STANDARD: 820 enum fe_stv0900_demod_num demod = state->demod;
1078 if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
1079 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1080 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
1081 }
1082 821
1083 stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff); 822 s32 srate,
1084 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1); 823 pilots,
1085 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75); 824 aclc,
1086 break; 825 freq1,
1087 case STV0900_DVBS2_STANDARD: 826 freq0,
1088 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0); 827 i = 0,
1089 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1); 828 timed,
1090 stv0900_write_reg(i_params, R0900_P1_ACLC, 0); 829 timef,
1091 stv0900_write_reg(i_params, R0900_P1_BCLC, 0); 830 blind_tun_sw = 0,
1092 if (i_params->dmd1_rslts.frame_length == STV0900_LONG_FRAME) { 831 modulation;
1093 foundModcod = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
1094 pilots = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
1095 aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
1096 if (foundModcod <= STV0900_QPSK_910)
1097 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
1098 else if (foundModcod <= STV0900_8PSK_910) {
1099 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1100 stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
1101 }
1102 832
1103 if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) { 833 enum fe_stv0900_rolloff rolloff;
1104 if (foundModcod <= STV0900_16APSK_910) { 834 enum fe_stv0900_modcode foundModcod;
1105 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1106 stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
1107 } else if (foundModcod <= STV0900_32APSK_910) {
1108 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1109 stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
1110 }
1111 }
1112 835
1113 } else { 836 dprintk("%s\n", __func__);
1114 aclc = stv0900_get_optim_short_carr_loop(srate, i_params->dmd1_rslts.modulation, i_params->chip_id);
1115 if (i_params->dmd1_rslts.modulation == STV0900_QPSK)
1116 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
1117
1118 else if (i_params->dmd1_rslts.modulation == STV0900_8PSK) {
1119 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1120 stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
1121 } else if (i_params->dmd1_rslts.modulation == STV0900_16APSK) {
1122 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1123 stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
1124 } else if (i_params->dmd1_rslts.modulation == STV0900_32APSK) {
1125 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1126 stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
1127 }
1128 837
1129 } 838 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
839 srate += stv0900_get_timing_offst(intp, srate, demod);
1130 840
1131 if (i_params->chip_id <= 0x11) { 841 switch (intp->result[demod].standard) {
1132 if (i_params->demod_mode != STV0900_SINGLE) 842 case STV0900_DVBS1_STANDARD:
1133 stv0900_activate_s2_modcode(i_params, demod); 843 case STV0900_DSS_STANDARD:
844 dprintk("%s: found DVB-S or DSS\n", __func__);
845 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
846 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
847 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
848 }
1134 849
1135 } 850 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
851 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1136 852
1137 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67); 853 if (intp->chip_id < 0x30) {
1138 break; 854 stv0900_write_reg(intp, ERRCTRL1, 0x75);
1139 case STV0900_UNKNOWN_STANDARD:
1140 default:
1141 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1142 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
1143 break; 855 break;
1144 } 856 }
1145 857
1146 freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2); 858 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
1147 freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1); 859 stv0900_write_reg(intp, GAUSSR0, 0x98);
1148 rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS); 860 stv0900_write_reg(intp, CCIR0, 0x18);
1149 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) { 861 } else {
1150 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00); 862 stv0900_write_reg(intp, GAUSSR0, 0x18);
1151 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0); 863 stv0900_write_reg(intp, CCIR0, 0x18);
1152 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1153 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
1154 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1155 stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
1156 stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
1157 blindTunSw = 1;
1158 } 864 }
1159 865
1160 if (i_params->chip_id >= 0x20) { 866 stv0900_write_reg(intp, ERRCTRL1, 0x75);
1161 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) { 867 break;
1162 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0a); 868 case STV0900_DVBS2_STANDARD:
1163 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x0); 869 dprintk("%s: found DVB-S2\n", __func__);
870 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
871 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
872 stv0900_write_reg(intp, ACLC, 0);
873 stv0900_write_reg(intp, BCLC, 0);
874 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
875 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
876 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
877 aclc = stv0900_get_optim_carr_loop(srate,
878 foundModcod,
879 pilots,
880 intp->chip_id);
881 if (foundModcod <= STV0900_QPSK_910)
882 stv0900_write_reg(intp, ACLC2S2Q, aclc);
883 else if (foundModcod <= STV0900_8PSK_910) {
884 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
885 stv0900_write_reg(intp, ACLC2S28, aclc);
1164 } 886 }
1165 }
1166
1167 if (i_params->chip_id < 0x20)
1168 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x08);
1169
1170 if (i_params->chip_id == 0x10)
1171 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0x0A);
1172 887
1173 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38); 888 if ((intp->demod_mode == STV0900_SINGLE) &&
1174 889 (foundModcod > STV0900_8PSK_910)) {
1175 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd1_symbol_rate < 10000000)) { 890 if (foundModcod <= STV0900_16APSK_910) {
1176 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1); 891 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1177 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0); 892 stv0900_write_reg(intp, ACLC2S216A,
1178 i_params->tuner1_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000; 893 aclc);
1179 894 } else if (foundModcod <= STV0900_32APSK_910) {
1180 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) { 895 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1181 if (i_params->dmd1_srch_algo != STV0900_WARM_START) 896 stv0900_write_reg(intp, ACLC2S232A,
1182 stv0900_set_bandwidth(fe, i_params->tuner1_bw); 897 aclc);
898 }
1183 } 899 }
1184 900
1185 if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000)) 901 } else {
1186 msleep(50); 902 modulation = intp->result[demod].modulation;
1187 else 903 aclc = stv0900_get_optim_short_carr_loop(srate,
1188 msleep(5); 904 modulation, intp->chip_id);
1189 905 if (modulation == STV0900_QPSK)
1190 stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START); 906 stv0900_write_reg(intp, ACLC2S2Q, aclc);
1191 907 else if (modulation == STV0900_8PSK) {
1192 if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) { 908 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1193 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F); 909 stv0900_write_reg(intp, ACLC2S28, aclc);
1194 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1); 910 } else if (modulation == STV0900_16APSK) {
1195 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0); 911 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1196 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 912 stv0900_write_reg(intp, ACLC2S216A, aclc);
1197 i = 0; 913 } else if (modulation == STV0900_32APSK) {
1198 while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) { 914 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1199 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F); 915 stv0900_write_reg(intp, ACLC2S232A, aclc);
1200 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1201 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1202 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1203 i++;
1204 }
1205 } 916 }
1206 917
1207 } 918 }
1208 919
1209 if (i_params->chip_id >= 0x20) 920 if (intp->chip_id <= 0x11) {
1210 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49); 921 if (intp->demod_mode != STV0900_SINGLE)
922 stv0900_activate_s2_modcod(intp, demod);
1211 923
1212 if ((i_params->dmd1_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd1_rslts.standard == STV0900_DSS_STANDARD)) 924 }
1213 stv0900_set_viterbi_tracq(i_params, demod);
1214 925
926 stv0900_write_reg(intp, ERRCTRL1, 0x67);
1215 break; 927 break;
928 case STV0900_UNKNOWN_STANDARD:
929 default:
930 dprintk("%s: found unknown standard\n", __func__);
931 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
932 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
933 break;
934 }
1216 935
1217 case STV0900_DEMOD_2: 936 freq1 = stv0900_read_reg(intp, CFR2);
1218 switch (i_params->dmd2_rslts.standard) { 937 freq0 = stv0900_read_reg(intp, CFR1);
1219 case STV0900_DVBS1_STANDARD: 938 rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1220 939 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1221 if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) { 940 stv0900_write_reg(intp, SFRSTEP, 0x00);
1222 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1); 941 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1223 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0); 942 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1224 } 943 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1225 944 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1226 stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff); 945 blind_tun_sw = 1;
1227 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1); 946 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
1228 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75); 947 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
1229 break;
1230 case STV0900_DSS_STANDARD:
1231 if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
1232 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1233 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
1234 }
1235
1236 stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
1237 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
1238 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
1239 break;
1240 case STV0900_DVBS2_STANDARD:
1241 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
1242 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
1243 stv0900_write_reg(i_params, R0900_P2_ACLC, 0);
1244 stv0900_write_reg(i_params, R0900_P2_BCLC, 0);
1245 if (i_params->dmd2_rslts.frame_length == STV0900_LONG_FRAME) {
1246 foundModcod = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
1247 pilots = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
1248 aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
1249 if (foundModcod <= STV0900_QPSK_910)
1250 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
1251 else if (foundModcod <= STV0900_8PSK_910) {
1252 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1253 stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
1254 }
1255 948
1256 if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) { 949 }
1257 if (foundModcod <= STV0900_16APSK_910) {
1258 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1259 stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
1260 } else if (foundModcod <= STV0900_32APSK_910) {
1261 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1262 stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
1263 }
1264 950
1265 } 951 if (intp->chip_id >= 0x20) {
952 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
953 (intp->srch_standard[demod] ==
954 STV0900_SEARCH_DSS) ||
955 (intp->srch_standard[demod] ==
956 STV0900_AUTO_SEARCH)) {
957 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
958 stv0900_write_reg(intp, VITSCALE, 0x0);
959 }
960 }
1266 961
1267 } else { 962 if (intp->chip_id < 0x20)
1268 aclc = stv0900_get_optim_short_carr_loop(srate, 963 stv0900_write_reg(intp, CARHDR, 0x08);
1269 i_params->dmd2_rslts.modulation,
1270 i_params->chip_id);
1271
1272 if (i_params->dmd2_rslts.modulation == STV0900_QPSK)
1273 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
1274
1275 else if (i_params->dmd2_rslts.modulation == STV0900_8PSK) {
1276 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1277 stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
1278 } else if (i_params->dmd2_rslts.modulation == STV0900_16APSK) {
1279 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1280 stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
1281 } else if (i_params->dmd2_rslts.modulation == STV0900_32APSK) {
1282 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1283 stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
1284 }
1285 }
1286 964
1287 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67); 965 if (intp->chip_id == 0x10)
966 stv0900_write_reg(intp, CORRELEXP, 0x0a);
1288 967
1289 break; 968 stv0900_write_reg(intp, AGC2REF, 0x38);
1290 case STV0900_UNKNOWN_STANDARD:
1291 default:
1292 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1293 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
1294 break;
1295 }
1296 969
1297 freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2); 970 if ((intp->chip_id >= 0x20) ||
1298 freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1); 971 (blind_tun_sw == 1) ||
1299 rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS); 972 (intp->symbol_rate[demod] < 10000000)) {
1300 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) { 973 stv0900_write_reg(intp, CFRINIT1, freq1);
1301 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00); 974 stv0900_write_reg(intp, CFRINIT0, freq0);
1302 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0); 975 intp->bw[demod] = stv0900_carrier_width(srate,
1303 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0); 976 intp->rolloff) + 10000000;
1304 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
1305 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1306 stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
1307 stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
1308 blindTunSw = 1;
1309 }
1310 977
1311 if (i_params->chip_id >= 0x20) { 978 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
1312 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) { 979 if (intp->srch_algo[demod] != STV0900_WARM_START)
1313 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0a); 980 stv0900_set_bandwidth(fe, intp->bw[demod]);
1314 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x0);
1315 }
1316 } 981 }
1317 982
1318 if (i_params->chip_id < 0x20) 983 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
1319 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x08); 984 (intp->symbol_rate[demod] < 10000000))
1320 985 msleep(50);
1321 if (i_params->chip_id == 0x10) 986 else
1322 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0x0a); 987 msleep(5);
1323
1324 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
1325 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd2_symbol_rate < 10000000)) {
1326 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1327 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1328 i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
1329 988
1330 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) { 989 stv0900_get_lock_timeout(&timed, &timef, srate,
1331 if (i_params->dmd2_srch_algo != STV0900_WARM_START) 990 STV0900_WARM_START);
1332 stv0900_set_bandwidth(fe, i_params->tuner2_bw);
1333 }
1334 991
1335 if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000)) 992 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
1336 msleep(50); 993 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1337 else 994 stv0900_write_reg(intp, CFRINIT1, freq1);
1338 msleep(5); 995 stv0900_write_reg(intp, CFRINIT0, freq0);
1339 996 stv0900_write_reg(intp, DMDISTATE, 0x18);
1340 stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START); 997 i = 0;
1341 if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) { 998 while ((stv0900_get_demod_lock(intp,
1342 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F); 999 demod,
1343 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1); 1000 timed / 2) == FALSE) &&
1344 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0); 1001 (i <= 2)) {
1345 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18); 1002 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1346 i = 0; 1003 stv0900_write_reg(intp, CFRINIT1, freq1);
1347 while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) { 1004 stv0900_write_reg(intp, CFRINIT0, freq0);
1348 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F); 1005 stv0900_write_reg(intp, DMDISTATE, 0x18);
1349 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1); 1006 i++;
1350 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1351 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1352 i++;
1353 }
1354 } 1007 }
1355 } 1008 }
1356 1009
1357 if (i_params->chip_id >= 0x20) 1010 }
1358 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
1359 1011
1360 if ((i_params->dmd2_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd2_rslts.standard == STV0900_DSS_STANDARD)) 1012 if (intp->chip_id >= 0x20)
1361 stv0900_set_viterbi_tracq(i_params, demod); 1013 stv0900_write_reg(intp, CARFREQ, 0x49);
1014
1015 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1016 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1017 stv0900_set_viterbi_tracq(intp, demod);
1362 1018
1363 break;
1364 }
1365} 1019}
1366 1020
1367static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv0900_demod_num demod, s32 time_out) 1021static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1022 enum fe_stv0900_demod_num demod, s32 time_out)
1368{ 1023{
1369 s32 timer = 0, lock = 0, header_field, pktdelin_field, lock_vit_field; 1024 s32 timer = 0, lock = 0;
1370 1025
1371 enum fe_stv0900_search_state dmd_state; 1026 enum fe_stv0900_search_state dmd_state;
1372 1027
1373 dprintk(KERN_INFO "%s\n", __func__); 1028 dprintk("%s\n", __func__);
1374 1029
1375 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE); 1030 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1376 dmd_reg(pktdelin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1377 dmd_reg(lock_vit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1378
1379 dmd_state = stv0900_get_bits(i_params, header_field);
1380 1031
1381 while ((timer < time_out) && (lock == 0)) { 1032 while ((timer < time_out) && (lock == 0)) {
1382 switch (dmd_state) { 1033 switch (dmd_state) {
@@ -1386,10 +1037,10 @@ static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv09
1386 lock = 0; 1037 lock = 0;
1387 break; 1038 break;
1388 case STV0900_DVBS2_FOUND: 1039 case STV0900_DVBS2_FOUND:
1389 lock = stv0900_get_bits(i_params, pktdelin_field); 1040 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1390 break; 1041 break;
1391 case STV0900_DVBS_FOUND: 1042 case STV0900_DVBS_FOUND:
1392 lock = stv0900_get_bits(i_params, lock_vit_field); 1043 lock = stv0900_get_bits(intp, LOCKEDVIT);
1393 break; 1044 break;
1394 } 1045 }
1395 1046
@@ -1400,46 +1051,44 @@ static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv09
1400 } 1051 }
1401 1052
1402 if (lock) 1053 if (lock)
1403 dprintk("DEMOD FEC LOCK OK\n"); 1054 dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1404 else 1055 else
1405 dprintk("DEMOD FEC LOCK FAIL\n"); 1056 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1406 1057
1407 return lock; 1058 return lock;
1408} 1059}
1409 1060
1410static int stv0900_wait_for_lock(struct stv0900_internal *i_params, 1061static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1411 enum fe_stv0900_demod_num demod, 1062 enum fe_stv0900_demod_num demod,
1412 s32 dmd_timeout, s32 fec_timeout) 1063 s32 dmd_timeout, s32 fec_timeout)
1413{ 1064{
1414 1065
1415 s32 timer = 0, lock = 0, str_merg_rst_fld, str_merg_lock_fld; 1066 s32 timer = 0, lock = 0;
1416
1417 dprintk(KERN_INFO "%s\n", __func__);
1418 1067
1419 dmd_reg(str_merg_rst_fld, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE); 1068 dprintk("%s\n", __func__);
1420 dmd_reg(str_merg_lock_fld, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1421 1069
1422 lock = stv0900_get_demod_lock(i_params, demod, dmd_timeout); 1070 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1423 1071
1424 if (lock) 1072 if (lock)
1425 lock = lock && stv0900_get_fec_lock(i_params, demod, fec_timeout); 1073 lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
1426 1074
1427 if (lock) { 1075 if (lock) {
1428 lock = 0; 1076 lock = 0;
1429 1077
1430 dprintk(KERN_INFO "%s: Timer = %d, time_out = %d\n", __func__, timer, fec_timeout); 1078 dprintk("%s: Timer = %d, time_out = %d\n",
1079 __func__, timer, fec_timeout);
1431 1080
1432 while ((timer < fec_timeout) && (lock == 0)) { 1081 while ((timer < fec_timeout) && (lock == 0)) {
1433 lock = stv0900_get_bits(i_params, str_merg_lock_fld); 1082 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1434 msleep(1); 1083 msleep(1);
1435 timer++; 1084 timer++;
1436 } 1085 }
1437 } 1086 }
1438 1087
1439 if (lock) 1088 if (lock)
1440 dprintk(KERN_INFO "%s: DEMOD LOCK OK\n", __func__); 1089 dprintk("%s: DEMOD LOCK OK\n", __func__);
1441 else 1090 else
1442 dprintk(KERN_INFO "%s: DEMOD LOCK FAIL\n", __func__); 1091 dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1443 1092
1444 if (lock) 1093 if (lock)
1445 return TRUE; 1094 return TRUE;
@@ -1451,43 +1100,43 @@ enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1451 enum fe_stv0900_demod_num demod) 1100 enum fe_stv0900_demod_num demod)
1452{ 1101{
1453 struct stv0900_state *state = fe->demodulator_priv; 1102 struct stv0900_state *state = fe->demodulator_priv;
1454 struct stv0900_internal *i_params = state->internal; 1103 struct stv0900_internal *intp = state->internal;
1455 enum fe_stv0900_tracking_standard fnd_standard; 1104 enum fe_stv0900_tracking_standard fnd_standard;
1456 s32 state_field,
1457 dss_dvb_field;
1458 1105
1459 dprintk(KERN_INFO "%s\n", __func__); 1106 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1460 1107
1461 dmd_reg(state_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE); 1108 switch (hdr_mode) {
1462 dmd_reg(dss_dvb_field, F0900_P1_DSS_DVB, F0900_P2_DSS_DVB); 1109 case 2:
1463
1464 if (stv0900_get_bits(i_params, state_field) == 2)
1465 fnd_standard = STV0900_DVBS2_STANDARD; 1110 fnd_standard = STV0900_DVBS2_STANDARD;
1466 1111 break;
1467 else if (stv0900_get_bits(i_params, state_field) == 3) { 1112 case 3:
1468 if (stv0900_get_bits(i_params, dss_dvb_field) == 1) 1113 if (stv0900_get_bits(intp, DSS_DVB) == 1)
1469 fnd_standard = STV0900_DSS_STANDARD; 1114 fnd_standard = STV0900_DSS_STANDARD;
1470 else 1115 else
1471 fnd_standard = STV0900_DVBS1_STANDARD; 1116 fnd_standard = STV0900_DVBS1_STANDARD;
1472 } else 1117
1118 break;
1119 default:
1473 fnd_standard = STV0900_UNKNOWN_STANDARD; 1120 fnd_standard = STV0900_UNKNOWN_STANDARD;
1121 }
1122
1123 dprintk("%s: standard %d\n", __func__, fnd_standard);
1474 1124
1475 return fnd_standard; 1125 return fnd_standard;
1476} 1126}
1477 1127
1478static s32 stv0900_get_carr_freq(struct stv0900_internal *i_params, u32 mclk, 1128static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1479 enum fe_stv0900_demod_num demod) 1129 enum fe_stv0900_demod_num demod)
1480{ 1130{
1481 s32 cfr_field2, cfr_field1, cfr_field0, 1131 s32 derot,
1482 derot, rem1, rem2, intval1, intval2; 1132 rem1,
1133 rem2,
1134 intval1,
1135 intval2;
1483 1136
1484 dmd_reg(cfr_field2, F0900_P1_CAR_FREQ2, F0900_P2_CAR_FREQ2); 1137 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1485 dmd_reg(cfr_field1, F0900_P1_CAR_FREQ1, F0900_P2_CAR_FREQ1); 1138 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1486 dmd_reg(cfr_field0, F0900_P1_CAR_FREQ0, F0900_P2_CAR_FREQ0); 1139 (stv0900_get_bits(intp, CAR_FREQ0));
1487
1488 derot = (stv0900_get_bits(i_params, cfr_field2) << 16) +
1489 (stv0900_get_bits(i_params, cfr_field1) << 8) +
1490 (stv0900_get_bits(i_params, cfr_field0));
1491 1140
1492 derot = ge2comp(derot, 24); 1141 derot = ge2comp(derot, 24);
1493 intval1 = mclk >> 12; 1142 intval1 = mclk >> 12;
@@ -1505,7 +1154,7 @@ static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1505{ 1154{
1506 struct dvb_frontend_ops *frontend_ops = NULL; 1155 struct dvb_frontend_ops *frontend_ops = NULL;
1507 struct dvb_tuner_ops *tuner_ops = NULL; 1156 struct dvb_tuner_ops *tuner_ops = NULL;
1508 u32 frequency = 0; 1157 u32 freq = 0;
1509 1158
1510 if (&fe->ops) 1159 if (&fe->ops)
1511 frontend_ops = &fe->ops; 1160 frontend_ops = &fe->ops;
@@ -1514,304 +1163,159 @@ static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1514 tuner_ops = &frontend_ops->tuner_ops; 1163 tuner_ops = &frontend_ops->tuner_ops;
1515 1164
1516 if (tuner_ops->get_frequency) { 1165 if (tuner_ops->get_frequency) {
1517 if ((tuner_ops->get_frequency(fe, &frequency)) < 0) 1166 if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1518 dprintk("%s: Invalid parameter\n", __func__); 1167 dprintk("%s: Invalid parameter\n", __func__);
1519 else 1168 else
1520 dprintk("%s: Frequency=%d\n", __func__, frequency); 1169 dprintk("%s: Frequency=%d\n", __func__, freq);
1521
1522 }
1523
1524 return frequency;
1525}
1526
1527static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *i_params,
1528 enum fe_stv0900_demod_num demod)
1529{
1530 s32 rate_fld, vit_curpun_fld;
1531 enum fe_stv0900_fec prate;
1532 1170
1533 dmd_reg(vit_curpun_fld, F0900_P1_VIT_CURPUN, F0900_P2_VIT_CURPUN);
1534 rate_fld = stv0900_get_bits(i_params, vit_curpun_fld);
1535
1536 switch (rate_fld) {
1537 case 13:
1538 prate = STV0900_FEC_1_2;
1539 break;
1540 case 18:
1541 prate = STV0900_FEC_2_3;
1542 break;
1543 case 21:
1544 prate = STV0900_FEC_3_4;
1545 break;
1546 case 24:
1547 prate = STV0900_FEC_5_6;
1548 break;
1549 case 25:
1550 prate = STV0900_FEC_6_7;
1551 break;
1552 case 26:
1553 prate = STV0900_FEC_7_8;
1554 break;
1555 default:
1556 prate = STV0900_FEC_UNKNOWN;
1557 break;
1558 } 1171 }
1559 1172
1560 return prate; 1173 return freq;
1561} 1174}
1562 1175
1563static enum fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe) 1176static enum
1177fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1564{ 1178{
1565 struct stv0900_state *state = fe->demodulator_priv; 1179 struct stv0900_state *state = fe->demodulator_priv;
1566 struct stv0900_internal *i_params = state->internal; 1180 struct stv0900_internal *intp = state->internal;
1567 enum fe_stv0900_demod_num demod = state->demod; 1181 enum fe_stv0900_demod_num demod = state->demod;
1568 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE; 1182 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1569 s32 offsetFreq, 1183 struct stv0900_signal_info *result = &intp->result[demod];
1570 srate_offset, 1184 s32 offsetFreq,
1571 i = 0; 1185 srate_offset;
1186 int i = 0,
1187 d = demod;
1572 1188
1573 u8 timing; 1189 u8 timing;
1574 1190
1575 msleep(5); 1191 msleep(5);
1576 switch (demod) { 1192 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1577 case STV0900_DEMOD_1: 1193 timing = stv0900_read_reg(intp, TMGREG2);
1578 default: 1194 i = 0;
1579 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) { 1195 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1580 timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2); 1196
1581 i = 0; 1197 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1582 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x5c); 1198 timing = stv0900_read_reg(intp, TMGREG2);
1583 1199 msleep(5);
1584 while ((i <= 50) && (timing != 0) && (timing != 0xFF)) { 1200 i += 5;
1585 timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
1586 msleep(5);
1587 i += 5;
1588 }
1589 } 1201 }
1202 }
1590 1203
1591 i_params->dmd1_rslts.standard = stv0900_get_standard(fe, demod); 1204 result->standard = stv0900_get_standard(fe, d);
1592 i_params->dmd1_rslts.frequency = stv0900_get_tuner_freq(fe); 1205 result->frequency = stv0900_get_tuner_freq(fe);
1593 offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000; 1206 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1594 i_params->dmd1_rslts.frequency += offsetFreq; 1207 result->frequency += offsetFreq;
1595 i_params->dmd1_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod); 1208 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1596 srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd1_rslts.symbol_rate, demod); 1209 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1597 i_params->dmd1_rslts.symbol_rate += srate_offset; 1210 result->symbol_rate += srate_offset;
1598 i_params->dmd1_rslts.fec = stv0900_get_vit_fec(i_params, demod); 1211 result->fec = stv0900_get_vit_fec(intp, d);
1599 i_params->dmd1_rslts.modcode = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD); 1212 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1600 i_params->dmd1_rslts.pilot = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01; 1213 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1601 i_params->dmd1_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE)) >> 1; 1214 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1602 i_params->dmd1_rslts.rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS); 1215 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1603 switch (i_params->dmd1_rslts.standard) { 1216 switch (result->standard) {
1604 case STV0900_DVBS2_STANDARD: 1217 case STV0900_DVBS2_STANDARD:
1605 i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_SPECINV_DEMOD); 1218 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1606 if (i_params->dmd1_rslts.modcode <= STV0900_QPSK_910) 1219 if (result->modcode <= STV0900_QPSK_910)
1607 i_params->dmd1_rslts.modulation = STV0900_QPSK; 1220 result->modulation = STV0900_QPSK;
1608 else if (i_params->dmd1_rslts.modcode <= STV0900_8PSK_910) 1221 else if (result->modcode <= STV0900_8PSK_910)
1609 i_params->dmd1_rslts.modulation = STV0900_8PSK; 1222 result->modulation = STV0900_8PSK;
1610 else if (i_params->dmd1_rslts.modcode <= STV0900_16APSK_910) 1223 else if (result->modcode <= STV0900_16APSK_910)
1611 i_params->dmd1_rslts.modulation = STV0900_16APSK; 1224 result->modulation = STV0900_16APSK;
1612 else if (i_params->dmd1_rslts.modcode <= STV0900_32APSK_910) 1225 else if (result->modcode <= STV0900_32APSK_910)
1613 i_params->dmd1_rslts.modulation = STV0900_32APSK; 1226 result->modulation = STV0900_32APSK;
1614 else 1227 else
1615 i_params->dmd1_rslts.modulation = STV0900_UNKNOWN; 1228 result->modulation = STV0900_UNKNOWN;
1616 break;
1617 case STV0900_DVBS1_STANDARD:
1618 case STV0900_DSS_STANDARD:
1619 i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_IQINV);
1620 i_params->dmd1_rslts.modulation = STV0900_QPSK;
1621 break;
1622 default:
1623 break;
1624 }
1625
1626 if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000)) {
1627 offsetFreq = i_params->dmd1_rslts.frequency - i_params->tuner1_freq;
1628 i_params->tuner1_freq = stv0900_get_tuner_freq(fe);
1629 if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
1630 range = STV0900_RANGEOK;
1631 else
1632 if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd1_rslts.symbol_rate, i_params->dmd1_rslts.rolloff) / 2000))
1633 range = STV0900_RANGEOK;
1634 else
1635 range = STV0900_OUTOFRANGE;
1636
1637 } else {
1638 if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
1639 range = STV0900_RANGEOK;
1640 else
1641 range = STV0900_OUTOFRANGE;
1642 }
1643 break; 1229 break;
1644 case STV0900_DEMOD_2: 1230 case STV0900_DVBS1_STANDARD:
1645 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) { 1231 case STV0900_DSS_STANDARD:
1646 timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2); 1232 result->spectrum = stv0900_get_bits(intp, IQINV);
1647 i = 0; 1233 result->modulation = STV0900_QPSK;
1648 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x5c); 1234 break;
1649 1235 default:
1650 while ((i <= 50) && (timing != 0) && (timing != 0xff)) { 1236 break;
1651 timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2); 1237 }
1652 msleep(5);
1653 i += 5;
1654 }
1655 }
1656
1657 i_params->dmd2_rslts.standard = stv0900_get_standard(fe, demod);
1658 i_params->dmd2_rslts.frequency = stv0900_get_tuner_freq(fe);
1659 offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
1660 i_params->dmd2_rslts.frequency += offsetFreq;
1661 i_params->dmd2_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1662 srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd2_rslts.symbol_rate, demod);
1663 i_params->dmd2_rslts.symbol_rate += srate_offset;
1664 i_params->dmd2_rslts.fec = stv0900_get_vit_fec(i_params, demod);
1665 i_params->dmd2_rslts.modcode = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
1666 i_params->dmd2_rslts.pilot = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
1667 i_params->dmd2_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE)) >> 1;
1668 i_params->dmd2_rslts.rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
1669 switch (i_params->dmd2_rslts.standard) {
1670 case STV0900_DVBS2_STANDARD:
1671 i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_SPECINV_DEMOD);
1672 if (i_params->dmd2_rslts.modcode <= STV0900_QPSK_910)
1673 i_params->dmd2_rslts.modulation = STV0900_QPSK;
1674 else if (i_params->dmd2_rslts.modcode <= STV0900_8PSK_910)
1675 i_params->dmd2_rslts.modulation = STV0900_8PSK;
1676 else if (i_params->dmd2_rslts.modcode <= STV0900_16APSK_910)
1677 i_params->dmd2_rslts.modulation = STV0900_16APSK;
1678 else if (i_params->dmd2_rslts.modcode <= STV0900_32APSK_910)
1679 i_params->dmd2_rslts.modulation = STV0900_32APSK;
1680 else
1681 i_params->dmd2_rslts.modulation = STV0900_UNKNOWN;
1682 break;
1683 case STV0900_DVBS1_STANDARD:
1684 case STV0900_DSS_STANDARD:
1685 i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_IQINV);
1686 i_params->dmd2_rslts.modulation = STV0900_QPSK;
1687 break;
1688 default:
1689 break;
1690 }
1691 1238
1692 if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000)) { 1239 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1693 offsetFreq = i_params->dmd2_rslts.frequency - i_params->tuner2_freq; 1240 (intp->symbol_rate[d] < 10000000)) {
1694 i_params->tuner2_freq = stv0900_get_tuner_freq(fe); 1241 offsetFreq = result->frequency - intp->freq[d];
1242 intp->freq[d] = stv0900_get_tuner_freq(fe);
1243 if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1244 range = STV0900_RANGEOK;
1245 else if (ABS(offsetFreq) <=
1246 (stv0900_carrier_width(result->symbol_rate,
1247 result->rolloff) / 2000))
1248 range = STV0900_RANGEOK;
1695 1249
1696 if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500)) 1250 } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1697 range = STV0900_RANGEOK; 1251 range = STV0900_RANGEOK;
1698 else
1699 if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd2_rslts.symbol_rate, i_params->dmd2_rslts.rolloff) / 2000))
1700 range = STV0900_RANGEOK;
1701 else
1702 range = STV0900_OUTOFRANGE;
1703 } else {
1704 if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
1705 range = STV0900_RANGEOK;
1706 else
1707 range = STV0900_OUTOFRANGE;
1708 }
1709 1252
1710 break; 1253 dprintk("%s: range %d\n", __func__, range);
1711 }
1712 1254
1713 return range; 1255 return range;
1714} 1256}
1715 1257
1716static enum fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe) 1258static enum
1259fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1717{ 1260{
1718 struct stv0900_state *state = fe->demodulator_priv; 1261 struct stv0900_state *state = fe->demodulator_priv;
1719 struct stv0900_internal *i_params = state->internal; 1262 struct stv0900_internal *intp = state->internal;
1720 enum fe_stv0900_demod_num demod = state->demod; 1263 enum fe_stv0900_demod_num demod = state->demod;
1721
1722 s32 srate, demod_timeout,
1723 fec_timeout, freq1, freq0;
1724 enum fe_stv0900_signal_type signal_type = STV0900_NODATA; 1264 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1725 1265
1726 switch (demod) { 1266 s32 srate,
1727 case STV0900_DEMOD_1: 1267 demod_timeout,
1728 default: 1268 fec_timeout,
1729 i_params->dmd1_rslts.locked = FALSE; 1269 freq1,
1730 if (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) { 1270 freq0;
1731 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod); 1271
1732 srate += stv0900_get_timing_offst(i_params, srate, demod); 1272 intp->result[demod].locked = FALSE;
1733 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) 1273
1734 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod); 1274 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1735 1275 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1736 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START); 1276 srate += stv0900_get_timing_offst(intp, srate, demod);
1737 freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2); 1277 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1738 freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1); 1278 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1739 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0); 1279
1740 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED); 1280 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1741 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C); 1281 srate, STV0900_WARM_START);
1742 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1); 1282 freq1 = stv0900_read_reg(intp, CFR2);
1743 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0); 1283 freq0 = stv0900_read_reg(intp, CFR1);
1744 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 1284 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1745 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) { 1285 stv0900_write_bits(intp, SPECINV_CONTROL,
1746 i_params->dmd1_rslts.locked = TRUE; 1286 STV0900_IQ_FORCE_SWAPPED);
1747 signal_type = stv0900_get_signal_params(fe); 1287 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1748 stv0900_track_optimization(fe); 1288 stv0900_write_reg(intp, CFRINIT1, freq1);
1749 } else { 1289 stv0900_write_reg(intp, CFRINIT0, freq0);
1750 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL); 1290 stv0900_write_reg(intp, DMDISTATE, 0x18);
1751 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1c); 1291 if (stv0900_wait_for_lock(intp, demod,
1752 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1); 1292 demod_timeout, fec_timeout) == TRUE) {
1753 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0); 1293 intp->result[demod].locked = TRUE;
1754 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 1294 signal_type = stv0900_get_signal_params(fe);
1755 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) { 1295 stv0900_track_optimization(fe);
1756 i_params->dmd1_rslts.locked = TRUE; 1296 } else {
1757 signal_type = stv0900_get_signal_params(fe); 1297 stv0900_write_bits(intp, SPECINV_CONTROL,
1758 stv0900_track_optimization(fe); 1298 STV0900_IQ_FORCE_NORMAL);
1759 } 1299 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1760 1300 stv0900_write_reg(intp, CFRINIT1, freq1);
1761 } 1301 stv0900_write_reg(intp, CFRINIT0, freq0);
1762 1302 stv0900_write_reg(intp, DMDISTATE, 0x18);
1763 } else 1303 if (stv0900_wait_for_lock(intp, demod,
1764 i_params->dmd1_rslts.locked = FALSE; 1304 demod_timeout, fec_timeout) == TRUE) {
1765 1305 intp->result[demod].locked = TRUE;
1766 break;
1767 case STV0900_DEMOD_2:
1768 i_params->dmd2_rslts.locked = FALSE;
1769 if (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) {
1770 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1771 srate += stv0900_get_timing_offst(i_params, srate, demod);
1772
1773 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH)
1774 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1775
1776 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
1777 freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
1778 freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
1779 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1780 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
1781 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
1782 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1783 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1784 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1785
1786 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1787 i_params->dmd2_rslts.locked = TRUE;
1788 signal_type = stv0900_get_signal_params(fe); 1306 signal_type = stv0900_get_signal_params(fe);
1789 stv0900_track_optimization(fe); 1307 stv0900_track_optimization(fe);
1790 } else {
1791 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
1792 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1c);
1793 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1794 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1795 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1796
1797 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1798 i_params->dmd2_rslts.locked = TRUE;
1799 signal_type = stv0900_get_signal_params(fe);
1800 stv0900_track_optimization(fe);
1801 }
1802
1803 } 1308 }
1804 1309
1805 } else 1310 }
1806 i_params->dmd1_rslts.locked = FALSE;
1807 1311
1808 break; 1312 } else
1809 } 1313 intp->result[demod].locked = FALSE;
1810 1314
1811 return signal_type; 1315 return signal_type;
1812} 1316}
1813 1317
1814static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params, 1318static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1815 enum fe_stv0900_demod_num demod) 1319 enum fe_stv0900_demod_num demod)
1816{ 1320{
1817 u32 minagc2level = 0xffff, 1321 u32 minagc2level = 0xffff,
@@ -1820,105 +1324,54 @@ static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
1820 1324
1821 s32 i, j, nb_steps, direction; 1325 s32 i, j, nb_steps, direction;
1822 1326
1823 dprintk(KERN_INFO "%s\n", __func__); 1327 dprintk("%s\n", __func__);
1824
1825 switch (demod) {
1826 case STV0900_DEMOD_1:
1827 default:
1828 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
1829 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
1830 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
1831
1832 stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
1833 stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
1834
1835 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
1836 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
1837 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
1838 1328
1839 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod); 1329 stv0900_write_reg(intp, AGC2REF, 0x38);
1840 nb_steps = -1 + (i_params->dmd1_srch_range / 1000000); 1330 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1841 nb_steps /= 2; 1331 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1842 nb_steps = (2 * nb_steps) + 1;
1843 1332
1844 if (nb_steps < 0) 1333 stv0900_write_bits(intp, AUTO_GUP, 1);
1845 nb_steps = 1; 1334 stv0900_write_bits(intp, AUTO_GLOW, 1);
1846 1335
1847 direction = 1; 1336 stv0900_write_reg(intp, DMDT0M, 0x0);
1848 1337
1849 freq_step = (1000000 << 8) / (i_params->mclk >> 8); 1338 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1339 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1340 nb_steps /= 2;
1341 nb_steps = (2 * nb_steps) + 1;
1850 1342
1851 init_freq = 0; 1343 if (nb_steps < 0)
1344 nb_steps = 1;
1852 1345
1853 for (i = 0; i < nb_steps; i++) { 1346 direction = 1;
1854 if (direction > 0)
1855 init_freq = init_freq + (freq_step * i);
1856 else
1857 init_freq = init_freq - (freq_step * i);
1858 1347
1859 direction *= -1; 1348 freq_step = (1000000 << 8) / (intp->mclk >> 8);
1860 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
1861 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (init_freq >> 8) & 0xff);
1862 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, init_freq & 0xff);
1863 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x58);
1864 msleep(10);
1865 agc2level = 0;
1866 1349
1867 for (j = 0; j < 10; j++) 1350 init_freq = 0;
1868 agc2level += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
1869 | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
1870 1351
1871 agc2level /= 10; 1352 for (i = 0; i < nb_steps; i++) {
1872 1353 if (direction > 0)
1873 if (agc2level < minagc2level) 1354 init_freq = init_freq + (freq_step * i);
1874 minagc2level = agc2level; 1355 else
1875 } 1356 init_freq = init_freq - (freq_step * i);
1876 break;
1877 case STV0900_DEMOD_2:
1878 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
1879 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
1880 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
1881 stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
1882 stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
1883 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
1884 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
1885 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
1886 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
1887 nb_steps = -1 + (i_params->dmd2_srch_range / 1000000);
1888 nb_steps /= 2;
1889 nb_steps = (2 * nb_steps) + 1;
1890
1891 if (nb_steps < 0)
1892 nb_steps = 1;
1893
1894 direction = 1;
1895 freq_step = (1000000 << 8) / (i_params->mclk >> 8);
1896 init_freq = 0;
1897 for (i = 0; i < nb_steps; i++) {
1898 if (direction > 0)
1899 init_freq = init_freq + (freq_step * i);
1900 else
1901 init_freq = init_freq - (freq_step * i);
1902 1357
1903 direction *= -1; 1358 direction *= -1;
1359 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1360 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1361 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1362 stv0900_write_reg(intp, DMDISTATE, 0x58);
1363 msleep(10);
1364 agc2level = 0;
1904 1365
1905 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C); 1366 for (j = 0; j < 10; j++)
1906 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (init_freq >> 8) & 0xff); 1367 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1907 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, init_freq & 0xff); 1368 | stv0900_read_reg(intp, AGC2I0);
1908 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x58);
1909 1369
1910 msleep(10); 1370 agc2level /= 10;
1911 agc2level = 0;
1912 for (j = 0; j < 10; j++)
1913 agc2level += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
1914 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
1915 1371
1916 agc2level /= 10; 1372 if (agc2level < minagc2level)
1373 minagc2level = agc2level;
1917 1374
1918 if (agc2level < minagc2level)
1919 minagc2level = agc2level;
1920 }
1921 break;
1922 } 1375 }
1923 1376
1924 return (u16)minagc2level; 1377 return (u16)minagc2level;
@@ -1927,336 +1380,192 @@ static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
1927static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe) 1380static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1928{ 1381{
1929 struct stv0900_state *state = fe->demodulator_priv; 1382 struct stv0900_state *state = fe->demodulator_priv;
1930 struct stv0900_internal *i_params = state->internal; 1383 struct stv0900_internal *intp = state->internal;
1931 enum fe_stv0900_demod_num demod = state->demod; 1384 enum fe_stv0900_demod_num demod = state->demod;
1932 int timingLock = FALSE; 1385 int timing_lck = FALSE;
1933 s32 i, timingcpt = 0, 1386 s32 i, timingcpt = 0,
1934 direction = 1, 1387 direction = 1,
1935 nb_steps, 1388 nb_steps,
1936 current_step = 0, 1389 current_step = 0,
1937 tuner_freq; 1390 tuner_freq;
1391 u32 agc2_th,
1392 coarse_srate = 0,
1393 agc2_integr = 0,
1394 currier_step = 1200;
1938 1395
1939 u32 coarse_srate = 0, agc2_integr = 0, currier_step = 1200; 1396 if (intp->chip_id >= 0x30)
1940 1397 agc2_th = 0x2e00;
1941 switch (demod) { 1398 else
1942 case STV0900_DEMOD_1: 1399 agc2_th = 0x1f00;
1943 default: 1400
1944 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1F); 1401 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1945 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0x12); 1402 stv0900_write_reg(intp, TMGCFG, 0x12);
1946 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xf0); 1403 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1947 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xe0); 1404 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1948 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1); 1405 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1949 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1); 1406 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1950 stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83); 1407 stv0900_write_reg(intp, SFRUP1, 0x83);
1951 stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0); 1408 stv0900_write_reg(intp, SFRUP0, 0xc0);
1952 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82); 1409 stv0900_write_reg(intp, SFRLOW1, 0x82);
1953 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0); 1410 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1954 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0); 1411 stv0900_write_reg(intp, DMDT0M, 0x0);
1955 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x50); 1412 stv0900_write_reg(intp, AGC2REF, 0x50);
1956 1413
1957 if (i_params->chip_id >= 0x20) { 1414 if (intp->chip_id >= 0x30) {
1958 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x6a); 1415 stv0900_write_reg(intp, CARFREQ, 0x99);
1959 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x95); 1416 stv0900_write_reg(intp, SFRSTEP, 0x98);
1960 } else { 1417 } else if (intp->chip_id >= 0x20) {
1961 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed); 1418 stv0900_write_reg(intp, CARFREQ, 0x6a);
1962 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x73); 1419 stv0900_write_reg(intp, SFRSTEP, 0x95);
1963 } 1420 } else {
1421 stv0900_write_reg(intp, CARFREQ, 0xed);
1422 stv0900_write_reg(intp, SFRSTEP, 0x73);
1423 }
1964 1424
1965 if (i_params->dmd1_symbol_rate <= 2000000) 1425 if (intp->symbol_rate[demod] <= 2000000)
1966 currier_step = 1000; 1426 currier_step = 1000;
1967 else if (i_params->dmd1_symbol_rate <= 5000000) 1427 else if (intp->symbol_rate[demod] <= 5000000)
1968 currier_step = 2000; 1428 currier_step = 2000;
1969 else if (i_params->dmd1_symbol_rate <= 12000000) 1429 else if (intp->symbol_rate[demod] <= 12000000)
1970 currier_step = 3000; 1430 currier_step = 3000;
1971 else 1431 else
1972 currier_step = 5000; 1432 currier_step = 5000;
1973 1433
1974 nb_steps = -1 + ((i_params->dmd1_srch_range / 1000) / currier_step); 1434 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1975 nb_steps /= 2; 1435 nb_steps /= 2;
1976 nb_steps = (2 * nb_steps) + 1; 1436 nb_steps = (2 * nb_steps) + 1;
1977
1978 if (nb_steps < 0)
1979 nb_steps = 1;
1980
1981 else if (nb_steps > 10) {
1982 nb_steps = 11;
1983 currier_step = (i_params->dmd1_srch_range / 1000) / 10;
1984 }
1985
1986 current_step = 0;
1987
1988 direction = 1;
1989 tuner_freq = i_params->tuner1_freq;
1990
1991 while ((timingLock == FALSE) && (current_step < nb_steps)) {
1992 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5F);
1993 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x0);
1994
1995 msleep(50);
1996
1997 for (i = 0; i < 10; i++) {
1998 if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
1999 timingcpt++;
2000
2001 agc2_integr += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8) | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
2002
2003 }
2004 1437
2005 agc2_integr /= 10; 1438 if (nb_steps < 0)
2006 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod); 1439 nb_steps = 1;
2007 current_step++; 1440 else if (nb_steps > 10) {
2008 direction *= -1; 1441 nb_steps = 11;
1442 currier_step = (intp->srch_range[demod] / 1000) / 10;
1443 }
2009 1444
2010 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n", tuner_freq, agc2_integr, coarse_srate, timingcpt); 1445 current_step = 0;
1446 direction = 1;
2011 1447
2012 if ((timingcpt >= 5) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000)) { 1448 tuner_freq = intp->freq[demod];
2013 timingLock = TRUE;
2014 }
2015 1449
2016 else if (current_step < nb_steps) { 1450 while ((timing_lck == FALSE) && (current_step < nb_steps)) {
2017 if (direction > 0) 1451 stv0900_write_reg(intp, DMDISTATE, 0x5f);
2018 tuner_freq += (current_step * currier_step); 1452 stv0900_write_bits(intp, DEMOD_MODE, 0);
2019 else
2020 tuner_freq -= (current_step * currier_step);
2021 1453
2022 stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw); 1454 msleep(50);
2023 }
2024 }
2025 1455
2026 if (timingLock == FALSE) 1456 for (i = 0; i < 10; i++) {
2027 coarse_srate = 0; 1457 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
2028 else 1458 timingcpt++;
2029 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2030 break;
2031 case STV0900_DEMOD_2:
2032 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1F);
2033 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0x12);
2034 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xf0);
2035 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xe0);
2036 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
2037 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
2038 stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
2039 stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
2040 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
2041 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
2042 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
2043 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x50);
2044
2045 if (i_params->chip_id >= 0x20) {
2046 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x6a);
2047 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x95);
2048 } else {
2049 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
2050 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x73);
2051 }
2052
2053 if (i_params->dmd2_symbol_rate <= 2000000)
2054 currier_step = 1000;
2055 else if (i_params->dmd2_symbol_rate <= 5000000)
2056 currier_step = 2000;
2057 else if (i_params->dmd2_symbol_rate <= 12000000)
2058 currier_step = 3000;
2059 else
2060 currier_step = 5000;
2061
2062
2063 nb_steps = -1 + ((i_params->dmd2_srch_range / 1000) / currier_step);
2064 nb_steps /= 2;
2065 nb_steps = (2 * nb_steps) + 1;
2066 1459
2067 if (nb_steps < 0) 1460 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
2068 nb_steps = 1; 1461 stv0900_read_reg(intp, AGC2I0);
2069 else if (nb_steps > 10) {
2070 nb_steps = 11;
2071 currier_step = (i_params->dmd2_srch_range / 1000) / 10;
2072 } 1462 }
2073 1463
2074 current_step = 0; 1464 agc2_integr /= 10;
2075 direction = 1; 1465 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
2076 tuner_freq = i_params->tuner2_freq; 1466 current_step++;
2077 1467 direction *= -1;
2078 while ((timingLock == FALSE) && (current_step < nb_steps)) { 1468
2079 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5F); 1469 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
2080 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x0); 1470 " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
2081 1471 tuner_freq, agc2_integr, coarse_srate, timingcpt);
2082 msleep(50); 1472
2083 timingcpt = 0; 1473 if ((timingcpt >= 5) &&
2084 1474 (agc2_integr < agc2_th) &&
2085 for (i = 0; i < 20; i++) { 1475 (coarse_srate < 55000000) &&
2086 if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2) 1476 (coarse_srate > 850000))
2087 timingcpt++; 1477 timing_lck = TRUE;
2088 agc2_integr += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8) 1478 else if (current_step < nb_steps) {
2089 | stv0900_read_reg(i_params, R0900_P2_AGC2I0); 1479 if (direction > 0)
2090 } 1480 tuner_freq += (current_step * currier_step);
2091 1481 else
2092 agc2_integr /= 20; 1482 tuner_freq -= (current_step * currier_step);
2093 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2094 if ((timingcpt >= 10) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000))
2095 timingLock = TRUE;
2096 else {
2097 current_step++;
2098 direction *= -1;
2099
2100 if (direction > 0)
2101 tuner_freq += (current_step * currier_step);
2102 else
2103 tuner_freq -= (current_step * currier_step);
2104 1483
2105 stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw); 1484 stv0900_set_tuner(fe, tuner_freq, intp->bw[demod]);
2106 }
2107 } 1485 }
2108
2109 if (timingLock == FALSE)
2110 coarse_srate = 0;
2111 else
2112 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2113 break;
2114 } 1486 }
2115 1487
1488 if (timing_lck == FALSE)
1489 coarse_srate = 0;
1490 else
1491 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1492
2116 return coarse_srate; 1493 return coarse_srate;
2117} 1494}
2118 1495
2119static u32 stv0900_search_srate_fine(struct dvb_frontend *fe) 1496static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
2120{ 1497{
2121 struct stv0900_state *state = fe->demodulator_priv; 1498 struct stv0900_state *state = fe->demodulator_priv;
2122 struct stv0900_internal *i_params = state->internal; 1499 struct stv0900_internal *intp = state->internal;
2123 enum fe_stv0900_demod_num demod = state->demod; 1500 enum fe_stv0900_demod_num demod = state->demod;
2124 u32 coarse_srate, 1501 u32 coarse_srate,
2125 coarse_freq, 1502 coarse_freq,
2126 symb; 1503 symb,
1504 symbmax,
1505 symbmin,
1506 symbcomp;
1507
1508 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1509
1510 if (coarse_srate > 3000000) {
1511 symbmax = 13 * (coarse_srate / 10);
1512 symbmax = (symbmax / 1000) * 65536;
1513 symbmax /= (intp->mclk / 1000);
1514
1515 symbmin = 10 * (coarse_srate / 13);
1516 symbmin = (symbmin / 1000)*65536;
1517 symbmin /= (intp->mclk / 1000);
1518
1519 symb = (coarse_srate / 1000) * 65536;
1520 symb /= (intp->mclk / 1000);
1521 } else {
1522 symbmax = 13 * (coarse_srate / 10);
1523 symbmax = (symbmax / 100) * 65536;
1524 symbmax /= (intp->mclk / 100);
2127 1525
2128 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod); 1526 symbmin = 10 * (coarse_srate / 14);
1527 symbmin = (symbmin / 100) * 65536;
1528 symbmin /= (intp->mclk / 100);
2129 1529
2130 switch (demod) { 1530 symb = (coarse_srate / 100) * 65536;
2131 case STV0900_DEMOD_1: 1531 symb /= (intp->mclk / 100);
2132 default: 1532 }
2133 coarse_freq = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
2134 | stv0900_read_reg(i_params, R0900_P1_CFR1);
2135 symb = 13 * (coarse_srate / 10);
2136
2137 if (symb < i_params->dmd1_symbol_rate)
2138 coarse_srate = 0;
2139 else {
2140 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
2141 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
2142 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
2143 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x00);
2144 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
2145 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
2146
2147 if (i_params->chip_id >= 0x20)
2148 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
2149 else
2150 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
2151
2152 if (coarse_srate > 3000000) {
2153 symb = 13 * (coarse_srate / 10);
2154 symb = (symb / 1000) * 65536;
2155 symb /= (i_params->mclk / 1000);
2156 stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
2157 stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
2158
2159 symb = 10 * (coarse_srate / 13);
2160 symb = (symb / 1000) * 65536;
2161 symb /= (i_params->mclk / 1000);
2162
2163 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
2164 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
2165
2166 symb = (coarse_srate / 1000) * 65536;
2167 symb /= (i_params->mclk / 1000);
2168 stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
2169 stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
2170 } else {
2171 symb = 13 * (coarse_srate / 10);
2172 symb = (symb / 100) * 65536;
2173 symb /= (i_params->mclk / 100);
2174 stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
2175 stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
2176
2177 symb = 10 * (coarse_srate / 14);
2178 symb = (symb / 100) * 65536;
2179 symb /= (i_params->mclk / 100);
2180 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
2181 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
2182
2183 symb = (coarse_srate / 100) * 65536;
2184 symb /= (i_params->mclk / 100);
2185 stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
2186 stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
2187 }
2188 1533
2189 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20); 1534 symbcomp = 13 * (coarse_srate / 10);
2190 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (coarse_freq >> 8) & 0xff); 1535 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
2191 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, coarse_freq & 0xff); 1536 | stv0900_read_reg(intp, CFR1);
2192 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15); 1537
2193 } 1538 if (symbcomp < intp->symbol_rate[demod])
2194 break; 1539 coarse_srate = 0;
2195 case STV0900_DEMOD_2: 1540 else {
2196 coarse_freq = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8) 1541 stv0900_write_reg(intp, DMDISTATE, 0x1f);
2197 | stv0900_read_reg(i_params, R0900_P2_CFR1); 1542 stv0900_write_reg(intp, TMGCFG2, 0xc1);
2198 1543 stv0900_write_reg(intp, TMGTHRISE, 0x20);
2199 symb = 13 * (coarse_srate / 10); 1544 stv0900_write_reg(intp, TMGTHFALL, 0x00);
2200 1545 stv0900_write_reg(intp, TMGCFG, 0xd2);
2201 if (symb < i_params->dmd2_symbol_rate) 1546 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
2202 coarse_srate = 0; 1547 stv0900_write_reg(intp, AGC2REF, 0x38);
2203 else { 1548
2204 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F); 1549 if (intp->chip_id >= 0x30)
2205 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01); 1550 stv0900_write_reg(intp, CARFREQ, 0x79);
2206 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20); 1551 else if (intp->chip_id >= 0x20)
2207 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0x00); 1552 stv0900_write_reg(intp, CARFREQ, 0x49);
2208 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2); 1553 else
2209 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0); 1554 stv0900_write_reg(intp, CARFREQ, 0xed);
2210
2211 if (i_params->chip_id >= 0x20)
2212 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
2213 else
2214 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
2215
2216 if (coarse_srate > 3000000) {
2217 symb = 13 * (coarse_srate / 10);
2218 symb = (symb / 1000) * 65536;
2219 symb /= (i_params->mclk / 1000);
2220 stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
2221 stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
2222
2223 symb = 10 * (coarse_srate / 13);
2224 symb = (symb / 1000) * 65536;
2225 symb /= (i_params->mclk / 1000);
2226
2227 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
2228 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
2229
2230 symb = (coarse_srate / 1000) * 65536;
2231 symb /= (i_params->mclk / 1000);
2232 stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
2233 stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
2234 } else {
2235 symb = 13 * (coarse_srate / 10);
2236 symb = (symb / 100) * 65536;
2237 symb /= (i_params->mclk / 100);
2238 stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
2239 stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
2240
2241 symb = 10 * (coarse_srate / 14);
2242 symb = (symb / 100) * 65536;
2243 symb /= (i_params->mclk / 100);
2244 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
2245 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
2246
2247 symb = (coarse_srate / 100) * 65536;
2248 symb /= (i_params->mclk / 100);
2249 stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
2250 stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
2251 }
2252 1555
2253 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20); 1556 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
2254 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (coarse_freq >> 8) & 0xff); 1557 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
2255 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, coarse_freq & 0xff);
2256 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
2257 }
2258 1558
2259 break; 1559 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1560 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1561
1562 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1563 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1564
1565 stv0900_write_reg(intp, DMDT0M, 0x20);
1566 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1567 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1568 stv0900_write_reg(intp, DMDISTATE, 0x15);
2260 } 1569 }
2261 1570
2262 return coarse_srate; 1571 return coarse_srate;
@@ -2265,163 +1574,135 @@ static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
2265static int stv0900_blind_search_algo(struct dvb_frontend *fe) 1574static int stv0900_blind_search_algo(struct dvb_frontend *fe)
2266{ 1575{
2267 struct stv0900_state *state = fe->demodulator_priv; 1576 struct stv0900_state *state = fe->demodulator_priv;
2268 struct stv0900_internal *i_params = state->internal; 1577 struct stv0900_internal *intp = state->internal;
2269 enum fe_stv0900_demod_num demod = state->demod; 1578 enum fe_stv0900_demod_num demod = state->demod;
2270 u8 k_ref_tmg, k_ref_tmg_max, k_ref_tmg_min; 1579 u8 k_ref_tmg,
2271 u32 coarse_srate; 1580 k_ref_tmg_max,
2272 int lock = FALSE, coarse_fail = FALSE; 1581 k_ref_tmg_min;
2273 s32 demod_timeout = 500, fec_timeout = 50, kref_tmg_reg, fail_cpt, i, agc2_overflow; 1582 u32 coarse_srate,
2274 u16 agc2_integr; 1583 agc2_th;
2275 u8 dstatus2; 1584 int lock = FALSE,
2276 1585 coarse_fail = FALSE;
2277 dprintk(KERN_INFO "%s\n", __func__); 1586 s32 demod_timeout = 500,
2278 1587 fec_timeout = 50,
2279 if (i_params->chip_id < 0x20) { 1588 fail_cpt,
1589 i,
1590 agc2_overflow;
1591 u16 agc2_int;
1592 u8 dstatus2;
1593
1594 dprintk("%s\n", __func__);
1595
1596 if (intp->chip_id < 0x20) {
2280 k_ref_tmg_max = 233; 1597 k_ref_tmg_max = 233;
2281 k_ref_tmg_min = 143; 1598 k_ref_tmg_min = 143;
2282 } else { 1599 } else {
2283 k_ref_tmg_max = 120; 1600 k_ref_tmg_max = 110;
2284 k_ref_tmg_min = 30; 1601 k_ref_tmg_min = 10;
2285 } 1602 }
2286 1603
2287 agc2_integr = stv0900_blind_check_agc2_min_level(i_params, demod); 1604 if (intp->chip_id <= 0x20)
2288 1605 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
2289 if (agc2_integr > STV0900_BLIND_SEARCH_AGC2_TH) { 1606 else
2290 lock = FALSE; 1607 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
2291
2292 } else {
2293 switch (demod) {
2294 case STV0900_DEMOD_1:
2295 default:
2296 if (i_params->chip_id == 0x10)
2297 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xAA);
2298
2299 if (i_params->chip_id < 0x20)
2300 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
2301
2302 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xC4);
2303 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
2304
2305 if (i_params->chip_id >= 0x20) {
2306 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
2307 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
2308 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
2309 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
2310 }
2311
2312 kref_tmg_reg = R0900_P1_KREFTMG;
2313 break;
2314 case STV0900_DEMOD_2:
2315 if (i_params->chip_id == 0x10)
2316 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xAA);
2317
2318 if (i_params->chip_id < 0x20)
2319 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
2320 1608
2321 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xC4); 1609 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
2322 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
2323 1610
2324 if (i_params->chip_id >= 0x20) { 1611 if (agc2_int > STV0900_BLIND_SEARCH_AGC2_TH)
2325 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41); 1612 return FALSE;
2326 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
2327 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
2328 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
2329 }
2330 1613
2331 kref_tmg_reg = R0900_P2_KREFTMG; 1614 if (intp->chip_id == 0x10)
2332 break; 1615 stv0900_write_reg(intp, CORRELEXP, 0xaa);
2333 }
2334 1616
2335 k_ref_tmg = k_ref_tmg_max; 1617 if (intp->chip_id < 0x20)
1618 stv0900_write_reg(intp, CARHDR, 0x55);
1619 else
1620 stv0900_write_reg(intp, CARHDR, 0x20);
2336 1621
2337 do { 1622 if (intp->chip_id <= 0x20)
2338 stv0900_write_reg(i_params, kref_tmg_reg, k_ref_tmg); 1623 stv0900_write_reg(intp, CARCFG, 0xc4);
2339 if (stv0900_search_srate_coarse(fe) != 0) { 1624 else
2340 coarse_srate = stv0900_search_srate_fine(fe); 1625 stv0900_write_reg(intp, CARCFG, 0x6);
2341 1626
2342 if (coarse_srate != 0) { 1627 stv0900_write_reg(intp, RTCS2, 0x44);
2343 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, coarse_srate, STV0900_BLIND_SEARCH);
2344 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
2345 } else
2346 lock = FALSE;
2347 } else {
2348 fail_cpt = 0;
2349 agc2_overflow = 0;
2350 1628
2351 switch (demod) { 1629 if (intp->chip_id >= 0x20) {
2352 case STV0900_DEMOD_1: 1630 stv0900_write_reg(intp, EQUALCFG, 0x41);
2353 default: 1631 stv0900_write_reg(intp, FFECFG, 0x41);
2354 for (i = 0; i < 10; i++) { 1632 stv0900_write_reg(intp, VITSCALE, 0x82);
2355 agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8) 1633 stv0900_write_reg(intp, VAVSRVIT, 0x0);
2356 | stv0900_read_reg(i_params, R0900_P1_AGC2I0); 1634 }
2357 1635
2358 if (agc2_integr >= 0xff00) 1636 k_ref_tmg = k_ref_tmg_max;
2359 agc2_overflow++;
2360 1637
2361 dstatus2 = stv0900_read_reg(i_params, R0900_P1_DSTATUS2); 1638 do {
1639 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1640 if (stv0900_search_srate_coarse(fe) != 0) {
1641 coarse_srate = stv0900_search_srate_fine(fe);
1642
1643 if (coarse_srate != 0) {
1644 stv0900_get_lock_timeout(&demod_timeout,
1645 &fec_timeout,
1646 coarse_srate,
1647 STV0900_BLIND_SEARCH);
1648 lock = stv0900_get_demod_lock(intp,
1649 demod,
1650 demod_timeout);
1651 } else
1652 lock = FALSE;
1653 } else {
1654 fail_cpt = 0;
1655 agc2_overflow = 0;
2362 1656
2363 if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1)) 1657 for (i = 0; i < 10; i++) {
2364 fail_cpt++; 1658 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
2365 } 1659 | stv0900_read_reg(intp, AGC2I0);
2366 break;
2367 case STV0900_DEMOD_2:
2368 for (i = 0; i < 10; i++) {
2369 agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
2370 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
2371 1660
2372 if (agc2_integr >= 0xff00) 1661 if (agc2_int >= 0xff00)
2373 agc2_overflow++; 1662 agc2_overflow++;
2374 1663
2375 dstatus2 = stv0900_read_reg(i_params, R0900_P2_DSTATUS2); 1664 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
2376 1665
2377 if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1)) 1666 if (((dstatus2 & 0x1) == 0x1) &&
2378 fail_cpt++; 1667 ((dstatus2 >> 7) == 1))
2379 } 1668 fail_cpt++;
2380 break; 1669 }
2381 }
2382 1670
2383 if ((fail_cpt > 7) || (agc2_overflow > 7)) 1671 if ((fail_cpt > 7) || (agc2_overflow > 7))
2384 coarse_fail = TRUE; 1672 coarse_fail = TRUE;
2385 1673
2386 lock = FALSE; 1674 lock = FALSE;
2387 } 1675 }
2388 k_ref_tmg -= 30; 1676 k_ref_tmg -= 30;
2389 } while ((k_ref_tmg >= k_ref_tmg_min) && (lock == FALSE) && (coarse_fail == FALSE)); 1677 } while ((k_ref_tmg >= k_ref_tmg_min) &&
2390 } 1678 (lock == FALSE) &&
1679 (coarse_fail == FALSE));
2391 1680
2392 return lock; 1681 return lock;
2393} 1682}
2394 1683
2395static void stv0900_set_viterbi_acq(struct stv0900_internal *i_params, 1684static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
2396 enum fe_stv0900_demod_num demod) 1685 enum fe_stv0900_demod_num demod)
2397{ 1686{
2398 s32 vth_reg; 1687 s32 vth_reg = VTH12;
2399 1688
2400 dprintk(KERN_INFO "%s\n", __func__); 1689 dprintk("%s\n", __func__);
2401 1690
2402 dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12); 1691 stv0900_write_reg(intp, vth_reg++, 0x96);
2403 1692 stv0900_write_reg(intp, vth_reg++, 0x64);
2404 stv0900_write_reg(i_params, vth_reg++, 0x96); 1693 stv0900_write_reg(intp, vth_reg++, 0x36);
2405 stv0900_write_reg(i_params, vth_reg++, 0x64); 1694 stv0900_write_reg(intp, vth_reg++, 0x23);
2406 stv0900_write_reg(i_params, vth_reg++, 0x36); 1695 stv0900_write_reg(intp, vth_reg++, 0x1e);
2407 stv0900_write_reg(i_params, vth_reg++, 0x23); 1696 stv0900_write_reg(intp, vth_reg++, 0x19);
2408 stv0900_write_reg(i_params, vth_reg++, 0x1E);
2409 stv0900_write_reg(i_params, vth_reg++, 0x19);
2410} 1697}
2411 1698
2412static void stv0900_set_search_standard(struct stv0900_internal *i_params, 1699static void stv0900_set_search_standard(struct stv0900_internal *intp,
2413 enum fe_stv0900_demod_num demod) 1700 enum fe_stv0900_demod_num demod)
2414{ 1701{
2415 1702
2416 int sstndrd; 1703 dprintk("%s\n", __func__);
2417
2418 dprintk(KERN_INFO "%s\n", __func__);
2419 1704
2420 sstndrd = i_params->dmd1_srch_standard; 1705 switch (intp->srch_standard[demod]) {
2421 if (demod == 1)
2422 sstndrd = i_params->dmd2_srch_stndrd;
2423
2424 switch (sstndrd) {
2425 case STV0900_SEARCH_DVBS1: 1706 case STV0900_SEARCH_DVBS1:
2426 dprintk("Search Standard = DVBS1\n"); 1707 dprintk("Search Standard = DVBS1\n");
2427 break; 1708 break;
@@ -2436,129 +1717,74 @@ static void stv0900_set_search_standard(struct stv0900_internal *i_params,
2436 break; 1717 break;
2437 } 1718 }
2438 1719
2439 switch (demod) { 1720 switch (intp->srch_standard[demod]) {
2440 case STV0900_DEMOD_1: 1721 case STV0900_SEARCH_DVBS1:
2441 default: 1722 case STV0900_SEARCH_DSS:
2442 switch (i_params->dmd1_srch_standard) { 1723 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
2443 case STV0900_SEARCH_DVBS1: 1724 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
2444 case STV0900_SEARCH_DSS: 1725 stv0900_write_bits(intp, STOP_CLKVIT, 0);
2445 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1); 1726 stv0900_set_dvbs1_track_car_loop(intp,
2446 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0); 1727 demod,
2447 1728 intp->symbol_rate[demod]);
2448 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0); 1729 stv0900_write_reg(intp, CAR2CFG, 0x22);
2449 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a); 1730
2450 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09); 1731 stv0900_set_viterbi_acq(intp, demod);
2451 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x22); 1732 stv0900_set_viterbi_standard(intp,
2452 1733 intp->srch_standard[demod],
2453 stv0900_set_viterbi_acq(i_params, demod); 1734 intp->fec[demod], demod);
2454 stv0900_set_viterbi_standard(i_params,
2455 i_params->dmd1_srch_standard,
2456 i_params->dmd1_fec, demod);
2457
2458 break;
2459 case STV0900_SEARCH_DVBS2:
2460 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
2461 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2462 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2463 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
2464 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 1);
2465 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2466 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2467 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
2468 if (i_params->demod_mode != STV0900_SINGLE) {
2469 if (i_params->chip_id <= 0x11)
2470 stv0900_stop_all_s2_modcod(i_params, demod);
2471 else
2472 stv0900_activate_s2_modcode(i_params, demod);
2473
2474 } else
2475 stv0900_activate_s2_modcode_single(i_params, demod);
2476
2477 stv0900_set_viterbi_tracq(i_params, demod);
2478
2479 break;
2480 case STV0900_AUTO_SEARCH:
2481 default:
2482 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
2483 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2484 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2485 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
2486 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
2487 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2488 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2489 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
2490 if (i_params->demod_mode != STV0900_SINGLE) {
2491 if (i_params->chip_id <= 0x11)
2492 stv0900_stop_all_s2_modcod(i_params, demod);
2493 else
2494 stv0900_activate_s2_modcode(i_params, demod);
2495 1735
2496 } else 1736 break;
2497 stv0900_activate_s2_modcode_single(i_params, demod); 1737 case STV0900_SEARCH_DVBS2:
1738 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1739 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1740 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1741 stv0900_write_reg(intp, ACLC, 0x1a);
1742 stv0900_write_reg(intp, BCLC, 0x09);
1743 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1744 stv0900_write_reg(intp, CAR2CFG, 0x26);
1745 else
1746 stv0900_write_reg(intp, CAR2CFG, 0x66);
2498 1747
2499 if (i_params->dmd1_symbol_rate >= 2000000) 1748 if (intp->demod_mode != STV0900_SINGLE) {
2500 stv0900_set_viterbi_acq(i_params, demod); 1749 if (intp->chip_id <= 0x11)
1750 stv0900_stop_all_s2_modcod(intp, demod);
2501 else 1751 else
2502 stv0900_set_viterbi_tracq(i_params, demod); 1752 stv0900_activate_s2_modcod(intp, demod);
2503 1753
2504 stv0900_set_viterbi_standard(i_params, i_params->dmd1_srch_standard, i_params->dmd1_fec, demod); 1754 } else
1755 stv0900_activate_s2_modcod_single(intp, demod);
2505 1756
2506 break; 1757 stv0900_set_viterbi_tracq(intp, demod);
2507 }
2508 break;
2509 case STV0900_DEMOD_2:
2510 switch (i_params->dmd2_srch_stndrd) {
2511 case STV0900_SEARCH_DVBS1:
2512 case STV0900_SEARCH_DSS:
2513 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2514 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2515 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
2516 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2517 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2518 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x22);
2519 stv0900_set_viterbi_acq(i_params, demod);
2520 stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
2521 break;
2522 case STV0900_SEARCH_DVBS2:
2523 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
2524 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2525 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2526 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
2527 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 1);
2528 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2529 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2530 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
2531 if (i_params->demod_mode != STV0900_SINGLE)
2532 stv0900_activate_s2_modcode(i_params, demod);
2533 else
2534 stv0900_activate_s2_modcode_single(i_params, demod);
2535 1758
2536 stv0900_set_viterbi_tracq(i_params, demod); 1759 break;
2537 break; 1760 case STV0900_AUTO_SEARCH:
2538 case STV0900_AUTO_SEARCH: 1761 default:
2539 default: 1762 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
2540 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0); 1763 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
2541 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0); 1764 stv0900_write_bits(intp, STOP_CLKVIT, 0);
2542 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1); 1765 stv0900_write_reg(intp, ACLC, 0x1a);
2543 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1); 1766 stv0900_write_reg(intp, BCLC, 0x09);
2544 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0); 1767 stv0900_set_dvbs1_track_car_loop(intp,
2545 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a); 1768 demod,
2546 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09); 1769 intp->symbol_rate[demod]);
2547 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26); 1770 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
2548 if (i_params->demod_mode != STV0900_SINGLE) 1771 stv0900_write_reg(intp, CAR2CFG, 0x26);
2549 stv0900_activate_s2_modcode(i_params, demod); 1772 else
2550 else 1773 stv0900_write_reg(intp, CAR2CFG, 0x66);
2551 stv0900_activate_s2_modcode_single(i_params, demod);
2552 1774
2553 if (i_params->dmd2_symbol_rate >= 2000000) 1775 if (intp->demod_mode != STV0900_SINGLE) {
2554 stv0900_set_viterbi_acq(i_params, demod); 1776 if (intp->chip_id <= 0x11)
1777 stv0900_stop_all_s2_modcod(intp, demod);
2555 else 1778 else
2556 stv0900_set_viterbi_tracq(i_params, demod); 1779 stv0900_activate_s2_modcod(intp, demod);
2557 1780
2558 stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod); 1781 } else
1782 stv0900_activate_s2_modcod_single(intp, demod);
2559 1783
2560 break; 1784 stv0900_set_viterbi_tracq(intp, demod);
2561 } 1785 stv0900_set_viterbi_standard(intp,
1786 intp->srch_standard[demod],
1787 intp->fec[demod], demod);
2562 1788
2563 break; 1789 break;
2564 } 1790 }
@@ -2567,10 +1793,11 @@ static void stv0900_set_search_standard(struct stv0900_internal *i_params,
2567enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe) 1793enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2568{ 1794{
2569 struct stv0900_state *state = fe->demodulator_priv; 1795 struct stv0900_state *state = fe->demodulator_priv;
2570 struct stv0900_internal *i_params = state->internal; 1796 struct stv0900_internal *intp = state->internal;
2571 enum fe_stv0900_demod_num demod = state->demod; 1797 enum fe_stv0900_demod_num demod = state->demod;
2572 1798
2573 s32 demod_timeout = 500, fec_timeout = 50, stream_merger_field; 1799 s32 demod_timeout = 500, fec_timeout = 50;
1800 s32 aq_power, agc1_power, i;
2574 1801
2575 int lock = FALSE, low_sr = FALSE; 1802 int lock = FALSE, low_sr = FALSE;
2576 1803
@@ -2578,157 +1805,117 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2578 enum fe_stv0900_search_algo algo; 1805 enum fe_stv0900_search_algo algo;
2579 int no_signal = FALSE; 1806 int no_signal = FALSE;
2580 1807
2581 dprintk(KERN_INFO "%s\n", __func__); 1808 dprintk("%s\n", __func__);
2582
2583 switch (demod) {
2584 case STV0900_DEMOD_1:
2585 default:
2586 algo = i_params->dmd1_srch_algo;
2587 1809
2588 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1); 1810 algo = intp->srch_algo[demod];
2589 stream_merger_field = F0900_P1_RST_HWARE; 1811 stv0900_write_bits(intp, RST_HWARE, 1);
2590 1812 stv0900_write_reg(intp, DMDISTATE, 0x5c);
2591 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C); 1813 if (intp->chip_id >= 0x20) {
2592 1814 if (intp->symbol_rate[demod] > 5000000)
2593 if (i_params->chip_id >= 0x20) 1815 stv0900_write_reg(intp, CORRELABS, 0x9e);
2594 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x9e);
2595 else 1816 else
2596 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x88); 1817 stv0900_write_reg(intp, CORRELABS, 0x82);
2597 1818 } else
2598 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd1_symbol_rate, i_params->dmd1_srch_algo); 1819 stv0900_write_reg(intp, CORRELABS, 0x88);
2599
2600 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
2601 i_params->tuner1_bw = 2 * 36000000;
2602
2603 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x00);
2604 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
2605
2606 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
2607 } else {
2608 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
2609 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
2610
2611 if (i_params->dmd1_symbol_rate < 2000000)
2612 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x63);
2613 else
2614 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
2615
2616 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
2617 if (i_params->chip_id >= 0x20) {
2618 stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0x5a);
2619
2620 if (i_params->dmd1_srch_algo == STV0900_COLD_START)
2621 i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
2622 else if (i_params->dmd1_srch_algo == STV0900_WARM_START)
2623 i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000;
2624 } else {
2625 stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0xc1);
2626 i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
2627 }
2628
2629 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
2630
2631 stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2632 stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2633 stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2634 if (i_params->dmd1_symbol_rate >= 10000000)
2635 low_sr = FALSE;
2636 else
2637 low_sr = TRUE;
2638
2639 }
2640
2641 stv0900_set_tuner(fe, i_params->tuner1_freq, i_params->tuner1_bw);
2642
2643 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, i_params->dmd1_srch_iq_inv);
2644 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
2645
2646 stv0900_set_search_standard(i_params, demod);
2647 1820
2648 if (i_params->dmd1_srch_algo != STV0900_BLIND_SEARCH) 1821 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
2649 stv0900_start_search(i_params, demod); 1822 intp->symbol_rate[demod],
2650 break; 1823 intp->srch_algo[demod]);
2651 case STV0900_DEMOD_2:
2652 algo = i_params->dmd2_srch_algo;
2653 1824
2654 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1); 1825 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1826 intp->bw[demod] = 2 * 36000000;
2655 1827
2656 stream_merger_field = F0900_P2_RST_HWARE; 1828 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1829 stv0900_write_reg(intp, CORRELMANT, 0x70);
2657 1830
2658 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C); 1831 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1832 } else {
1833 stv0900_write_reg(intp, DMDT0M, 0x20);
1834 stv0900_write_reg(intp, TMGCFG, 0xd2);
2659 1835
2660 if (i_params->chip_id >= 0x20) 1836 if (intp->symbol_rate[demod] < 2000000)
2661 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x9e); 1837 stv0900_write_reg(intp, CORRELMANT, 0x63);
2662 else 1838 else
2663 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x88); 1839 stv0900_write_reg(intp, CORRELMANT, 0x70);
2664 1840
2665 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd2_symbol_rate, i_params->dmd2_srch_algo); 1841 stv0900_write_reg(intp, AGC2REF, 0x38);
2666 1842
2667 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) { 1843 intp->bw[demod] =
2668 i_params->tuner2_bw = 2 * 36000000; 1844 stv0900_carrier_width(intp->symbol_rate[demod],
1845 intp->rolloff);
1846 if (intp->chip_id >= 0x20) {
1847 stv0900_write_reg(intp, KREFTMG, 0x5a);
2669 1848
2670 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x00); 1849 if (intp->srch_algo[demod] == STV0900_COLD_START) {
2671 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70); 1850 intp->bw[demod] += 10000000;
1851 intp->bw[demod] *= 15;
1852 intp->bw[demod] /= 10;
1853 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1854 intp->bw[demod] += 10000000;
2672 1855
2673 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
2674 } else { 1856 } else {
2675 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20); 1857 stv0900_write_reg(intp, KREFTMG, 0xc1);
2676 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2); 1858 intp->bw[demod] += 10000000;
1859 intp->bw[demod] *= 15;
1860 intp->bw[demod] /= 10;
1861 }
2677 1862
2678 if (i_params->dmd2_symbol_rate < 2000000) 1863 stv0900_write_reg(intp, TMGCFG2, 0xc1);
2679 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x63);
2680 else
2681 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
2682 1864
2683 if (i_params->dmd2_symbol_rate >= 10000000) 1865 stv0900_set_symbol_rate(intp, intp->mclk,
2684 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38); 1866 intp->symbol_rate[demod], demod);
2685 else 1867 stv0900_set_max_symbol_rate(intp, intp->mclk,
2686 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x60); 1868 intp->symbol_rate[demod], demod);
1869 stv0900_set_min_symbol_rate(intp, intp->mclk,
1870 intp->symbol_rate[demod], demod);
1871 if (intp->symbol_rate[demod] >= 10000000)
1872 low_sr = FALSE;
1873 else
1874 low_sr = TRUE;
2687 1875
2688 if (i_params->chip_id >= 0x20) { 1876 }
2689 stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0x5a);
2690 1877
2691 if (i_params->dmd2_srch_algo == STV0900_COLD_START) 1878 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
2692 i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
2693 i_params->rolloff) + 10000000)) / 10;
2694 else if (i_params->dmd2_srch_algo == STV0900_WARM_START)
2695 i_params->tuner2_bw = stv0900_carrier_width(i_params->dmd2_symbol_rate,
2696 i_params->rolloff) + 10000000;
2697 } else {
2698 stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0xc1);
2699 i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
2700 i_params->rolloff) + 10000000)) / 10;
2701 }
2702 1879
2703 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01); 1880 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1881 stv0900_get_bits(intp, AGCIQ_VALUE0));
2704 1882
2705 stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod); 1883 aq_power = 0;
2706 stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2707 stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2708 if (i_params->dmd2_symbol_rate >= 10000000)
2709 low_sr = FALSE;
2710 else
2711 low_sr = TRUE;
2712 1884
2713 } 1885 if (agc1_power == 0) {
1886 for (i = 0; i < 5; i++)
1887 aq_power += (stv0900_get_bits(intp, POWER_I) +
1888 stv0900_get_bits(intp, POWER_Q)) / 2;
2714 1889
2715 stv0900_set_tuner(fe, i_params->tuner2_freq, i_params->tuner2_bw); 1890 aq_power /= 5;
1891 }
2716 1892
2717 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, i_params->dmd2_srch_iq_inv); 1893 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
2718 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1); 1894 intp->result[demod].locked = FALSE;
1895 signal_type = STV0900_NOAGC1;
1896 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1897 } else {
1898 stv0900_write_bits(intp, SPECINV_CONTROL,
1899 intp->srch_iq_inv[demod]);
1900 if (intp->chip_id <= 0x20) /*cut 2.0*/
1901 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1902 else /*cut 3.0*/
1903 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
2719 1904
2720 stv0900_set_search_standard(i_params, demod); 1905 stv0900_set_search_standard(intp, demod);
2721 1906
2722 if (i_params->dmd2_srch_algo != STV0900_BLIND_SEARCH) 1907 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
2723 stv0900_start_search(i_params, demod); 1908 stv0900_start_search(intp, demod);
2724 break;
2725 } 1909 }
2726 1910
2727 if (i_params->chip_id == 0x12) { 1911 if (signal_type == STV0900_NOAGC1)
2728 stv0900_write_bits(i_params, stream_merger_field, 0); 1912 return signal_type;
1913
1914 if (intp->chip_id == 0x12) {
1915 stv0900_write_bits(intp, RST_HWARE, 0);
2729 msleep(3); 1916 msleep(3);
2730 stv0900_write_bits(i_params, stream_merger_field, 1); 1917 stv0900_write_bits(intp, RST_HWARE, 1);
2731 stv0900_write_bits(i_params, stream_merger_field, 0); 1918 stv0900_write_bits(intp, RST_HWARE, 0);
2732 } 1919 }
2733 1920
2734 if (algo == STV0900_BLIND_SEARCH) 1921 if (algo == STV0900_BLIND_SEARCH)
@@ -2736,12 +1923,12 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2736 else if (algo == STV0900_COLD_START) 1923 else if (algo == STV0900_COLD_START)
2737 lock = stv0900_get_demod_cold_lock(fe, demod_timeout); 1924 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
2738 else if (algo == STV0900_WARM_START) 1925 else if (algo == STV0900_WARM_START)
2739 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout); 1926 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
2740 1927
2741 if ((lock == FALSE) && (algo == STV0900_COLD_START)) { 1928 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
2742 if (low_sr == FALSE) { 1929 if (low_sr == FALSE) {
2743 if (stv0900_check_timing_lock(i_params, demod) == TRUE) 1930 if (stv0900_check_timing_lock(intp, demod) == TRUE)
2744 lock = stv0900_sw_algo(i_params, demod); 1931 lock = stv0900_sw_algo(intp, demod);
2745 } 1932 }
2746 } 1933 }
2747 1934
@@ -2750,98 +1937,64 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2750 1937
2751 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) { 1938 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
2752 stv0900_track_optimization(fe); 1939 stv0900_track_optimization(fe);
2753 if (i_params->chip_id <= 0x11) { 1940 if (intp->chip_id <= 0x11) {
2754 if ((stv0900_get_standard(fe, STV0900_DEMOD_1) == STV0900_DVBS1_STANDARD) && (stv0900_get_standard(fe, STV0900_DEMOD_2) == STV0900_DVBS1_STANDARD)) { 1941 if ((stv0900_get_standard(fe, 0) ==
1942 STV0900_DVBS1_STANDARD) &&
1943 (stv0900_get_standard(fe, 1) ==
1944 STV0900_DVBS1_STANDARD)) {
2755 msleep(20); 1945 msleep(20);
2756 stv0900_write_bits(i_params, stream_merger_field, 0); 1946 stv0900_write_bits(intp, RST_HWARE, 0);
2757 } else { 1947 } else {
2758 stv0900_write_bits(i_params, stream_merger_field, 0); 1948 stv0900_write_bits(intp, RST_HWARE, 0);
2759 msleep(3); 1949 msleep(3);
2760 stv0900_write_bits(i_params, stream_merger_field, 1); 1950 stv0900_write_bits(intp, RST_HWARE, 1);
2761 stv0900_write_bits(i_params, stream_merger_field, 0); 1951 stv0900_write_bits(intp, RST_HWARE, 0);
2762 } 1952 }
2763 } else if (i_params->chip_id == 0x20) { 1953
2764 stv0900_write_bits(i_params, stream_merger_field, 0); 1954 } else if (intp->chip_id >= 0x20) {
1955 stv0900_write_bits(intp, RST_HWARE, 0);
2765 msleep(3); 1956 msleep(3);
2766 stv0900_write_bits(i_params, stream_merger_field, 1); 1957 stv0900_write_bits(intp, RST_HWARE, 1);
2767 stv0900_write_bits(i_params, stream_merger_field, 0); 1958 stv0900_write_bits(intp, RST_HWARE, 0);
2768 } 1959 }
2769 1960
2770 if (stv0900_wait_for_lock(i_params, demod, fec_timeout, fec_timeout) == TRUE) { 1961 if (stv0900_wait_for_lock(intp, demod,
1962 fec_timeout, fec_timeout) == TRUE) {
2771 lock = TRUE; 1963 lock = TRUE;
2772 switch (demod) { 1964 intp->result[demod].locked = TRUE;
2773 case STV0900_DEMOD_1: 1965 if (intp->result[demod].standard ==
2774 default: 1966 STV0900_DVBS2_STANDARD) {
2775 i_params->dmd1_rslts.locked = TRUE; 1967 stv0900_set_dvbs2_rolloff(intp, demod);
2776 if (i_params->dmd1_rslts.standard == STV0900_DVBS2_STANDARD) { 1968 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
2777 stv0900_set_dvbs2_rolloff(i_params, demod); 1969 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
2778 stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0x40); 1970 stv0900_write_reg(intp, ERRCTRL1, 0x67);
2779 stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0); 1971 } else {
2780 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67); 1972 stv0900_write_reg(intp, ERRCTRL1, 0x75);
2781 } else {
2782 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
2783 }
2784
2785 stv0900_write_reg(i_params, R0900_P1_FBERCPT4, 0);
2786 stv0900_write_reg(i_params, R0900_P1_ERRCTRL2, 0xc1);
2787 break;
2788 case STV0900_DEMOD_2:
2789 i_params->dmd2_rslts.locked = TRUE;
2790
2791 if (i_params->dmd2_rslts.standard == STV0900_DVBS2_STANDARD) {
2792 stv0900_set_dvbs2_rolloff(i_params, demod);
2793 stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x60);
2794 stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x20);
2795 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
2796 } else {
2797 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
2798 }
2799
2800 stv0900_write_reg(i_params, R0900_P2_FBERCPT4, 0);
2801
2802 stv0900_write_reg(i_params, R0900_P2_ERRCTRL2, 0xc1);
2803 break;
2804 } 1973 }
1974
1975 stv0900_write_reg(intp, FBERCPT4, 0);
1976 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
2805 } else { 1977 } else {
2806 lock = FALSE; 1978 lock = FALSE;
2807 signal_type = STV0900_NODATA; 1979 signal_type = STV0900_NODATA;
2808 no_signal = stv0900_check_signal_presence(i_params, demod); 1980 no_signal = stv0900_check_signal_presence(intp, demod);
2809 1981
2810 switch (demod) { 1982 intp->result[demod].locked = FALSE;
2811 case STV0900_DEMOD_1:
2812 default:
2813 i_params->dmd1_rslts.locked = FALSE;
2814 break;
2815 case STV0900_DEMOD_2:
2816 i_params->dmd2_rslts.locked = FALSE;
2817 break;
2818 }
2819 } 1983 }
2820 } 1984 }
2821 1985
2822 if ((signal_type == STV0900_NODATA) && (no_signal == FALSE)) { 1986 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2823 switch (demod) { 1987 return signal_type;
2824 case STV0900_DEMOD_1:
2825 default:
2826 if (i_params->chip_id <= 0x11) {
2827 if ((stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) &&
2828 (i_params->dmd1_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
2829 signal_type = stv0900_dvbs1_acq_workaround(fe);
2830 } else
2831 i_params->dmd1_rslts.locked = FALSE;
2832 1988
2833 break; 1989 if (intp->chip_id > 0x11) {
2834 case STV0900_DEMOD_2: 1990 intp->result[demod].locked = FALSE;
2835 if (i_params->chip_id <= 0x11) { 1991 return signal_type;
2836 if ((stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) &&
2837 (i_params->dmd2_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
2838 signal_type = stv0900_dvbs1_acq_workaround(fe);
2839 } else
2840 i_params->dmd2_rslts.locked = FALSE;
2841 break;
2842 }
2843 } 1992 }
2844 1993
1994 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
1995 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
1996 signal_type = stv0900_dvbs1_acq_workaround(fe);
1997
2845 return signal_type; 1998 return signal_type;
2846} 1999}
2847 2000
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c
index 488bdfb34fb3..48edd542242e 100644
--- a/drivers/media/dvb/frontends/stv090x.c
+++ b/drivers/media/dvb/frontends/stv090x.c
@@ -825,7 +825,7 @@ static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate
825 sym /= (state->mclk >> 7); 825 sym /= (state->mclk >> 7);
826 } 826 }
827 827
828 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */ 828 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
829 goto err; 829 goto err;
830 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */ 830 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
831 goto err; 831 goto err;
@@ -1238,6 +1238,8 @@ static int stv090x_delivery_search(struct stv090x_state *state)
1238 goto err; 1238 goto err;
1239 } 1239 }
1240 1240
1241 if (stv090x_set_vit_thtracq(state) < 0)
1242 goto err;
1241 break; 1243 break;
1242 1244
1243 case STV090x_SEARCH_AUTO: 1245 case STV090x_SEARCH_AUTO:
@@ -1278,17 +1280,8 @@ static int stv090x_delivery_search(struct stv090x_state *state)
1278 goto err; 1280 goto err;
1279 } 1281 }
1280 1282
1281 if (state->srate >= 2000000) { 1283 if (stv090x_set_vit_thacq(state) < 0)
1282 /* Srate >= 2MSPS, Viterbi threshold to acquire */ 1284 goto err;
1283 if (stv090x_set_vit_thacq(state) < 0)
1284 goto err;
1285 } else {
1286 /* Srate < 2MSPS, Reset Viterbi thresholdto track
1287 * and then re-acquire
1288 */
1289 if (stv090x_set_vit_thtracq(state) < 0)
1290 goto err;
1291 }
1292 1285
1293 if (stv090x_set_viterbi(state) < 0) 1286 if (stv090x_set_viterbi(state) < 0)
1294 goto err; 1287 goto err;
@@ -1317,7 +1310,7 @@ static int stv090x_start_search(struct stv090x_state *state)
1317 goto err; 1310 goto err;
1318 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0) 1311 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1319 goto err; 1312 goto err;
1320 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0) 1313 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1321 goto err; 1314 goto err;
1322 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0) 1315 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1323 goto err; 1316 goto err;
@@ -1371,7 +1364,7 @@ static int stv090x_start_search(struct stv090x_state *state)
1371 1364
1372 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0) 1365 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1373 goto err; 1366 goto err;
1374 if (STV090x_WRITE_DEMOD(state, CFRUP1, LSB(freq)) < 0) 1367 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1375 goto err; 1368 goto err;
1376 1369
1377 freq *= -1; 1370 freq *= -1;
@@ -1422,6 +1415,9 @@ static int stv090x_start_search(struct stv090x_state *state)
1422 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) 1415 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1423 goto err; 1416 goto err;
1424 1417
1418 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1419 goto err;
1420
1425 if (state->dev_ver >= 0x20) { 1421 if (state->dev_ver >= 0x20) {
1426 /*Frequency offset detector setting*/ 1422 /*Frequency offset detector setting*/
1427 if (state->srate < 2000000) { 1423 if (state->srate < 2000000) {
@@ -1430,20 +1426,22 @@ static int stv090x_start_search(struct stv090x_state *state)
1430 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0) 1426 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1431 goto err; 1427 goto err;
1432 } else { 1428 } else {
1433 /* Cut 2 */ 1429 /* Cut 3 */
1434 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0) 1430 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1435 goto err; 1431 goto err;
1436 } 1432 }
1437 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0) 1433 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1438 goto err; 1434 goto err;
1439 } 1435 } else if (state->srate < 10000000) {
1440
1441 if (state->srate < 10000000) {
1442 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0) 1436 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1443 goto err; 1437 goto err;
1438 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1439 goto err;
1444 } else { 1440 } else {
1445 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0) 1441 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1446 goto err; 1442 goto err;
1443 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1444 goto err;
1447 } 1445 }
1448 } else { 1446 } else {
1449 if (state->srate < 10000000) { 1447 if (state->srate < 10000000) {
@@ -1485,14 +1483,14 @@ err:
1485 1483
1486static int stv090x_get_agc2_min_level(struct stv090x_state *state) 1484static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1487{ 1485{
1488 u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg; 1486 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1489 s32 i, j, steps, dir; 1487 s32 i, j, steps, dir;
1490 1488
1491 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) 1489 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1492 goto err; 1490 goto err;
1493 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1491 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1494 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); 1492 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1495 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1); 1493 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1496 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1494 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1497 goto err; 1495 goto err;
1498 1496
@@ -1509,10 +1507,8 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1509 if (stv090x_set_srate(state, 1000000) < 0) 1507 if (stv090x_set_srate(state, 1000000) < 0)
1510 goto err; 1508 goto err;
1511 1509
1512 steps = -1 + state->search_range / 1000000; 1510 steps = state->search_range / 1000000;
1513 steps /= 2; 1511 if (steps <= 0)
1514 steps = (2 * steps) + 1;
1515 if (steps < 0)
1516 steps = 1; 1512 steps = 1;
1517 1513
1518 dir = 1; 1514 dir = 1;
@@ -1525,7 +1521,7 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1525 else 1521 else
1526 freq_init = freq_init - (freq_step * i); 1522 freq_init = freq_init - (freq_step * i);
1527 1523
1528 dir = -1; 1524 dir *= -1;
1529 1525
1530 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */ 1526 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1531 goto err; 1527 goto err;
@@ -1536,13 +1532,14 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1536 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */ 1532 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1537 goto err; 1533 goto err;
1538 msleep(10); 1534 msleep(10);
1535
1536 agc2 = 0;
1539 for (j = 0; j < 10; j++) { 1537 for (j = 0; j < 10; j++) {
1540 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8; 1538 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1541 agc2 |= STV090x_READ_DEMOD(state, AGC2I0); 1539 STV090x_READ_DEMOD(state, AGC2I0);
1542 } 1540 }
1543 agc2 /= 10; 1541 agc2 /= 10;
1544 agc2_min = 0xffff; 1542 if (agc2 < agc2_min)
1545 if (agc2 < 0xffff)
1546 agc2_min = agc2; 1543 agc2_min = agc2;
1547 } 1544 }
1548 1545
@@ -1584,6 +1581,12 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1584 int tmg_lock = 0, i; 1581 int tmg_lock = 0, i;
1585 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq; 1582 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1586 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; 1583 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1584 u32 agc2th;
1585
1586 if (state->dev_ver >= 0x30)
1587 agc2th = 0x2e00;
1588 else
1589 agc2th = 0x1f00;
1587 1590
1588 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1591 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1589 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ 1592 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
@@ -1591,13 +1594,15 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1591 goto err; 1594 goto err;
1592 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0) 1595 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1593 goto err; 1596 goto err;
1597 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1598 goto err;
1594 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0) 1599 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1595 goto err; 1600 goto err;
1596 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0) 1601 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1597 goto err; 1602 goto err;
1598 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 1603 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1599 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); 1604 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1600 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1); 1605 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1601 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1606 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1602 goto err; 1607 goto err;
1603 1608
@@ -1611,13 +1616,13 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1611 goto err; 1616 goto err;
1612 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) 1617 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1613 goto err; 1618 goto err;
1614 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) 1619 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1615 goto err; 1620 goto err;
1616 1621
1617 if (state->dev_ver >= 0x30) { 1622 if (state->dev_ver >= 0x30) {
1618 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0) 1623 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1619 goto err; 1624 goto err;
1620 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0) 1625 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1621 goto err; 1626 goto err;
1622 1627
1623 } else if (state->dev_ver >= 0x20) { 1628 } else if (state->dev_ver >= 0x20) {
@@ -1652,23 +1657,31 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1652 while ((!tmg_lock) && (cur_step < steps)) { 1657 while ((!tmg_lock) && (cur_step < steps)) {
1653 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */ 1658 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1654 goto err; 1659 goto err;
1655 reg = STV090x_READ_DEMOD(state, DMDISTATE); 1660 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1656 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */ 1661 goto err;
1657 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) 1662 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1663 goto err;
1664 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1665 goto err;
1666 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1667 goto err;
1668 /* trigger acquisition */
1669 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1658 goto err; 1670 goto err;
1659 msleep(50); 1671 msleep(50);
1660 for (i = 0; i < 10; i++) { 1672 for (i = 0; i < 10; i++) {
1661 reg = STV090x_READ_DEMOD(state, DSTATUS); 1673 reg = STV090x_READ_DEMOD(state, DSTATUS);
1662 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) 1674 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1663 tmg_cpt++; 1675 tmg_cpt++;
1664 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8; 1676 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1665 agc2 |= STV090x_READ_DEMOD(state, AGC2I0); 1677 STV090x_READ_DEMOD(state, AGC2I0);
1666 } 1678 }
1667 agc2 /= 10; 1679 agc2 /= 10;
1668 srate_coarse = stv090x_get_srate(state, state->mclk); 1680 srate_coarse = stv090x_get_srate(state, state->mclk);
1669 cur_step++; 1681 cur_step++;
1670 dir *= -1; 1682 dir *= -1;
1671 if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000)) 1683 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1684 (srate_coarse < 50000000) && (srate_coarse > 850000))
1672 tmg_lock = 1; 1685 tmg_lock = 1;
1673 else if (cur_step < steps) { 1686 else if (cur_step < steps) {
1674 if (dir > 0) 1687 if (dir > 0)
@@ -1681,7 +1694,7 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1681 goto err; 1694 goto err;
1682 1695
1683 if (state->config->tuner_set_frequency) { 1696 if (state->config->tuner_set_frequency) {
1684 if (state->config->tuner_set_frequency(fe, state->frequency) < 0) 1697 if (state->config->tuner_set_frequency(fe, freq) < 0)
1685 goto err; 1698 goto err;
1686 } 1699 }
1687 1700
@@ -1738,7 +1751,7 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1738 else { 1751 else {
1739 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */ 1752 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1740 goto err; 1753 goto err;
1741 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) 1754 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1742 goto err; 1755 goto err;
1743 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0) 1756 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1744 goto err; 1757 goto err;
@@ -1751,6 +1764,9 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1751 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) 1764 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1752 goto err; 1765 goto err;
1753 1766
1767 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1768 goto err;
1769
1754 if (state->dev_ver >= 0x30) { 1770 if (state->dev_ver >= 0x30) {
1755 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0) 1771 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1756 goto err; 1772 goto err;
@@ -1856,12 +1872,12 @@ static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1856static int stv090x_blind_search(struct stv090x_state *state) 1872static int stv090x_blind_search(struct stv090x_state *state)
1857{ 1873{
1858 u32 agc2, reg, srate_coarse; 1874 u32 agc2, reg, srate_coarse;
1859 s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i; 1875 s32 cpt_fail, agc2_ovflw, i;
1860 u8 k_ref, k_max, k_min; 1876 u8 k_ref, k_max, k_min;
1861 int coarse_fail, lock; 1877 int coarse_fail, lock;
1862 1878
1863 k_max = 120; 1879 k_max = 110;
1864 k_min = 30; 1880 k_min = 10;
1865 1881
1866 agc2 = stv090x_get_agc2_min_level(state); 1882 agc2 = stv090x_get_agc2_min_level(state);
1867 1883
@@ -1900,7 +1916,8 @@ static int stv090x_blind_search(struct stv090x_state *state)
1900 srate_coarse = stv090x_srate_srch_fine(state); 1916 srate_coarse = stv090x_srate_srch_fine(state);
1901 if (srate_coarse != 0) { 1917 if (srate_coarse != 0) {
1902 stv090x_get_lock_tmg(state); 1918 stv090x_get_lock_tmg(state);
1903 lock = stv090x_get_dmdlock(state, timeout_dmd); 1919 lock = stv090x_get_dmdlock(state,
1920 state->DemodTimeout);
1904 } else { 1921 } else {
1905 lock = 0; 1922 lock = 0;
1906 } 1923 }
@@ -1908,8 +1925,8 @@ static int stv090x_blind_search(struct stv090x_state *state)
1908 cpt_fail = 0; 1925 cpt_fail = 0;
1909 agc2_ovflw = 0; 1926 agc2_ovflw = 0;
1910 for (i = 0; i < 10; i++) { 1927 for (i = 0; i < 10; i++) {
1911 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8; 1928 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1912 agc2 |= STV090x_READ_DEMOD(state, AGC2I0); 1929 STV090x_READ_DEMOD(state, AGC2I0);
1913 if (agc2 >= 0xff00) 1930 if (agc2 >= 0xff00)
1914 agc2_ovflw++; 1931 agc2_ovflw++;
1915 reg = STV090x_READ_DEMOD(state, DSTATUS2); 1932 reg = STV090x_READ_DEMOD(state, DSTATUS2);
@@ -1923,7 +1940,7 @@ static int stv090x_blind_search(struct stv090x_state *state)
1923 1940
1924 lock = 0; 1941 lock = 0;
1925 } 1942 }
1926 k_ref -= 30; 1943 k_ref -= 20;
1927 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail)); 1944 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1928 } 1945 }
1929 1946
@@ -2062,7 +2079,7 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2062 goto err; 2079 goto err;
2063 2080
2064 if (state->config->tuner_set_frequency) { 2081 if (state->config->tuner_set_frequency) {
2065 if (state->config->tuner_set_frequency(fe, state->frequency) < 0) 2082 if (state->config->tuner_set_frequency(fe, freq) < 0)
2066 goto err; 2083 goto err;
2067 } 2084 }
2068 2085
@@ -2093,17 +2110,6 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2093 goto err; 2110 goto err;
2094 2111
2095 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c); 2112 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2096 if (state->delsys == STV090x_DVBS2) {
2097 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2098 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2099 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2100 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2101 goto err;
2102 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2103 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2104 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2105 goto err;
2106 }
2107 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) 2113 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2108 goto err; 2114 goto err;
2109 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0) 2115 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
@@ -2425,7 +2431,7 @@ static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2425 2431
2426 derot = (int_1 * int_2) + 2432 derot = (int_1 * int_2) +
2427 ((int_1 * tmp_2) >> 12) + 2433 ((int_1 * tmp_2) >> 12) +
2428 ((int_1 * tmp_1) >> 12); 2434 ((int_2 * tmp_1) >> 12);
2429 2435
2430 return derot; 2436 return derot;
2431} 2437}
@@ -2732,7 +2738,7 @@ static int stv090x_optimize_track(struct stv090x_state *state)
2732 switch (state->delsys) { 2738 switch (state->delsys) {
2733 case STV090x_DVBS1: 2739 case STV090x_DVBS1:
2734 case STV090x_DSS: 2740 case STV090x_DSS:
2735 if (state->algo == STV090x_SEARCH_AUTO) { 2741 if (state->search_mode == STV090x_SEARCH_AUTO) {
2736 reg = STV090x_READ_DEMOD(state, DMDCFGMD); 2742 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2737 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); 2743 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2738 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); 2744 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
@@ -2857,6 +2863,9 @@ static int stv090x_optimize_track(struct stv090x_state *state)
2857 if (stv090x_set_srate(state, srate) < 0) 2863 if (stv090x_set_srate(state, srate) < 0)
2858 goto err; 2864 goto err;
2859 blind_tune = 1; 2865 blind_tune = 1;
2866
2867 if (stv090x_dvbs_track_crl(state) < 0)
2868 goto err;
2860 } 2869 }
2861 2870
2862 if (state->dev_ver >= 0x20) { 2871 if (state->dev_ver >= 0x20) {
@@ -3042,7 +3051,7 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3042 struct dvb_frontend *fe = &state->frontend; 3051 struct dvb_frontend *fe = &state->frontend;
3043 enum stv090x_signal_state signal_state = STV090x_NOCARRIER; 3052 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3044 u32 reg; 3053 u32 reg;
3045 s32 timeout_dmd = 500, timeout_fec = 50, agc1_power, power_iq = 0, i; 3054 s32 agc1_power, power_iq = 0, i;
3046 int lock = 0, low_sr = 0, no_signal = 0; 3055 int lock = 0, low_sr = 0, no_signal = 0;
3047 3056
3048 reg = STV090x_READ_DEMOD(state, TSCFGH); 3057 reg = STV090x_READ_DEMOD(state, TSCFGH);
@@ -3054,8 +3063,13 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3054 goto err; 3063 goto err;
3055 3064
3056 if (state->dev_ver >= 0x20) { 3065 if (state->dev_ver >= 0x20) {
3057 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */ 3066 if (state->srate > 5000000) {
3058 goto err; 3067 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3068 goto err;
3069 } else {
3070 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3071 goto err;
3072 }
3059 } 3073 }
3060 3074
3061 stv090x_get_lock_tmg(state); 3075 stv090x_get_lock_tmg(state);
@@ -3175,7 +3189,7 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3175 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) { 3189 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3176 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq); 3190 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3177 lock = 0; 3191 lock = 0;
3178 3192 signal_state = STV090x_NOAGC1;
3179 } else { 3193 } else {
3180 reg = STV090x_READ_DEMOD(state, DEMOD); 3194 reg = STV090x_READ_DEMOD(state, DEMOD);
3181 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); 3195 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
@@ -3199,18 +3213,17 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3199 } 3213 }
3200 } 3214 }
3201 3215
3202 /* need to check for AGC1 state */ 3216 if (signal_state == STV090x_NOAGC1)
3203 3217 return signal_state;
3204
3205 3218
3206 if (state->algo == STV090x_BLIND_SEARCH) 3219 if (state->algo == STV090x_BLIND_SEARCH)
3207 lock = stv090x_blind_search(state); 3220 lock = stv090x_blind_search(state);
3208 3221
3209 else if (state->algo == STV090x_COLD_SEARCH) 3222 else if (state->algo == STV090x_COLD_SEARCH)
3210 lock = stv090x_get_coldlock(state, timeout_dmd); 3223 lock = stv090x_get_coldlock(state, state->DemodTimeout);
3211 3224
3212 else if (state->algo == STV090x_WARM_SEARCH) 3225 else if (state->algo == STV090x_WARM_SEARCH)
3213 lock = stv090x_get_dmdlock(state, timeout_dmd); 3226 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3214 3227
3215 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) { 3228 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3216 if (!low_sr) { 3229 if (!low_sr) {
@@ -3245,8 +3258,9 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3245 goto err; 3258 goto err;
3246 } 3259 }
3247 3260
3248 if (stv090x_get_lock(state, timeout_fec, timeout_fec)) { 3261 lock = stv090x_get_lock(state, state->FecTimeout,
3249 lock = 1; 3262 state->FecTimeout);
3263 if (lock) {
3250 if (state->delsys == STV090x_DVBS2) { 3264 if (state->delsys == STV090x_DVBS2) {
3251 stv090x_set_s2rolloff(state); 3265 stv090x_set_s2rolloff(state);
3252 3266
@@ -3273,7 +3287,6 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3273 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0) 3287 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3274 goto err; 3288 goto err;
3275 } else { 3289 } else {
3276 lock = 0;
3277 signal_state = STV090x_NODATA; 3290 signal_state = STV090x_NODATA;
3278 no_signal = stv090x_chk_signal(state); 3291 no_signal = stv090x_chk_signal(state);
3279 } 3292 }
@@ -3296,7 +3309,13 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_fron
3296 state->search_mode = STV090x_SEARCH_AUTO; 3309 state->search_mode = STV090x_SEARCH_AUTO;
3297 state->algo = STV090x_COLD_SEARCH; 3310 state->algo = STV090x_COLD_SEARCH;
3298 state->fec = STV090x_PRERR; 3311 state->fec = STV090x_PRERR;
3299 state->search_range = 2000000; 3312 if (state->srate > 10000000) {
3313 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3314 state->search_range = 10000000;
3315 } else {
3316 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3317 state->search_range = 5000000;
3318 }
3300 3319
3301 if (stv090x_algo(state) == STV090x_RANGEOK) { 3320 if (stv090x_algo(state) == STV090x_RANGEOK) {
3302 dprintk(FE_DEBUG, 1, "Search success!"); 3321 dprintk(FE_DEBUG, 1, "Search success!");
@@ -3309,7 +3328,6 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_fron
3309 return DVBFE_ALGO_SEARCH_ERROR; 3328 return DVBFE_ALGO_SEARCH_ERROR;
3310} 3329}
3311 3330
3312/* FIXME! */
3313static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) 3331static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3314{ 3332{
3315 struct stv090x_state *state = fe->demodulator_priv; 3333 struct stv090x_state *state = fe->demodulator_priv;
@@ -3331,9 +3349,15 @@ static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3331 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2"); 3349 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3332 reg = STV090x_READ_DEMOD(state, DSTATUS); 3350 reg = STV090x_READ_DEMOD(state, DSTATUS);
3333 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) { 3351 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3334 reg = STV090x_READ_DEMOD(state, TSSTATUS); 3352 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3335 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) { 3353 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3336 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; 3354 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3355 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3356 *status = FE_HAS_CARRIER |
3357 FE_HAS_VITERBI |
3358 FE_HAS_SYNC |
3359 FE_HAS_LOCK;
3360 }
3337 } 3361 }
3338 } 3362 }
3339 break; 3363 break;
@@ -3412,14 +3436,12 @@ static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3412 int res = 0; 3436 int res = 0;
3413 int min = 0, med; 3437 int min = 0, med;
3414 3438
3415 if (val < tab[min].read) 3439 if ((val >= tab[min].read && val < tab[max].read) ||
3416 res = tab[min].real; 3440 (val >= tab[max].read && val < tab[min].read)) {
3417 else if (val >= tab[max].read)
3418 res = tab[max].real;
3419 else {
3420 while ((max - min) > 1) { 3441 while ((max - min) > 1) {
3421 med = (max + min) / 2; 3442 med = (max + min) / 2;
3422 if (val >= tab[min].read && val < tab[med].read) 3443 if ((val >= tab[min].read && val < tab[med].read) ||
3444 (val >= tab[med].read && val < tab[min].read))
3423 max = med; 3445 max = med;
3424 else 3446 else
3425 min = med; 3447 min = med;
@@ -3428,6 +3450,18 @@ static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3428 (tab[max].real - tab[min].real) / 3450 (tab[max].real - tab[min].real) /
3429 (tab[max].read - tab[min].read)) + 3451 (tab[max].read - tab[min].read)) +
3430 tab[min].real; 3452 tab[min].real;
3453 } else {
3454 if (tab[min].read < tab[max].read) {
3455 if (val < tab[min].read)
3456 res = tab[min].real;
3457 else if (val >= tab[max].read)
3458 res = tab[max].real;
3459 } else {
3460 if (val >= tab[min].read)
3461 res = tab[min].real;
3462 else if (val < tab[max].read)
3463 res = tab[max].real;
3464 }
3431 } 3465 }
3432 3466
3433 return res; 3467 return res;
@@ -3437,16 +3471,22 @@ static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3437{ 3471{
3438 struct stv090x_state *state = fe->demodulator_priv; 3472 struct stv090x_state *state = fe->demodulator_priv;
3439 u32 reg; 3473 u32 reg;
3440 s32 agc; 3474 s32 agc_0, agc_1, agc;
3475 s32 str;
3441 3476
3442 reg = STV090x_READ_DEMOD(state, AGCIQIN1); 3477 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3443 agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); 3478 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3479 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3480 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3481 agc = MAKEWORD16(agc_1, agc_0);
3444 3482
3445 *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc); 3483 str = stv090x_table_lookup(stv090x_rf_tab,
3484 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3446 if (agc > stv090x_rf_tab[0].read) 3485 if (agc > stv090x_rf_tab[0].read)
3447 *strength = 5; 3486 str = 0;
3448 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read) 3487 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3449 *strength = -100; 3488 str = -100;
3489 *strength = (str + 100) * 0xFFFF / 100;
3450 3490
3451 return 0; 3491 return 0;
3452} 3492}
@@ -3457,6 +3497,8 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3457 u32 reg_0, reg_1, reg, i; 3497 u32 reg_0, reg_1, reg, i;
3458 s32 val_0, val_1, val = 0; 3498 s32 val_0, val_1, val = 0;
3459 u8 lock_f; 3499 u8 lock_f;
3500 s32 div;
3501 u32 last;
3460 3502
3461 switch (state->delsys) { 3503 switch (state->delsys) {
3462 case STV090x_DVBS2: 3504 case STV090x_DVBS2:
@@ -3468,14 +3510,15 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3468 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1); 3510 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3469 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); 3511 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3470 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0); 3512 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3471 val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD); 3513 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3472 val += MAKEWORD16(val_1, val_0); 3514 val += MAKEWORD16(val_1, val_0);
3473 msleep(1); 3515 msleep(1);
3474 } 3516 }
3475 val /= 16; 3517 val /= 16;
3476 *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val); 3518 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3477 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read) 3519 div = stv090x_s2cn_tab[0].read -
3478 *cnr = 1000; 3520 stv090x_s2cn_tab[last].read;
3521 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3479 } 3522 }
3480 break; 3523 break;
3481 3524
@@ -3489,14 +3532,15 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3489 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1); 3532 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3490 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); 3533 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3491 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0); 3534 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3492 val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD); 3535 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3493 val += MAKEWORD16(val_1, val_0); 3536 val += MAKEWORD16(val_1, val_0);
3494 msleep(1); 3537 msleep(1);
3495 } 3538 }
3496 val /= 16; 3539 val /= 16;
3497 *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val); 3540 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3498 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read) 3541 div = stv090x_s1cn_tab[0].read -
3499 *cnr = 1000; 3542 stv090x_s1cn_tab[last].read;
3543 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3500 } 3544 }
3501 break; 3545 break;
3502 default: 3546 default:
@@ -3732,6 +3776,8 @@ static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc
3732{ 3776{
3733 u32 reg = 0; 3777 u32 reg = 0;
3734 3778
3779 reg = stv090x_read_reg(state, STV090x_GENCFG);
3780
3735 switch (ldpc_mode) { 3781 switch (ldpc_mode) {
3736 case STV090x_DUAL: 3782 case STV090x_DUAL:
3737 default: 3783 default:
diff --git a/drivers/media/dvb/frontends/stv090x_priv.h b/drivers/media/dvb/frontends/stv090x_priv.h
index 5a4a01740d88..5921a8d6c89f 100644
--- a/drivers/media/dvb/frontends/stv090x_priv.h
+++ b/drivers/media/dvb/frontends/stv090x_priv.h
@@ -83,7 +83,7 @@
83 83
84#define STV090x_IQPOWER_THRESHOLD 30 84#define STV090x_IQPOWER_THRESHOLD 30
85#define STV090x_SEARCH_AGC2_TH_CUT20 700 85#define STV090x_SEARCH_AGC2_TH_CUT20 700
86#define STV090x_SEARCH_AGC2_TH_CUT30 1200 86#define STV090x_SEARCH_AGC2_TH_CUT30 1400
87 87
88#define STV090x_SEARCH_AGC2_TH(__ver) \ 88#define STV090x_SEARCH_AGC2_TH(__ver) \
89 ((__ver <= 0x20) ? \ 89 ((__ver <= 0x20) ? \
@@ -91,6 +91,7 @@
91 STV090x_SEARCH_AGC2_TH_CUT30) 91 STV090x_SEARCH_AGC2_TH_CUT30)
92 92
93enum stv090x_signal_state { 93enum stv090x_signal_state {
94 STV090x_NOAGC1,
94 STV090x_NOCARRIER, 95 STV090x_NOCARRIER,
95 STV090x_NODATA, 96 STV090x_NODATA,
96 STV090x_DATAOK, 97 STV090x_DATAOK,
diff --git a/drivers/media/dvb/frontends/stv090x_reg.h b/drivers/media/dvb/frontends/stv090x_reg.h
index 57b6abbbd32d..2502855dd784 100644
--- a/drivers/media/dvb/frontends/stv090x_reg.h
+++ b/drivers/media/dvb/frontends/stv090x_reg.h
@@ -44,7 +44,7 @@
44#define STV090x_OFFST_OUTSERRS2_HZ_FIELD 5 44#define STV090x_OFFST_OUTSERRS2_HZ_FIELD 5
45#define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1 45#define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1
46#define STV090x_OFFST_OUTSERRS3_HZ_FIELD 4 46#define STV090x_OFFST_OUTSERRS3_HZ_FIELD 4
47#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1 47#define STV090x_WIDTH_OUTSERRS3_HZ_FIELD 1
48#define STV090x_OFFST_OUTPARRS3_HZ_FIELD 3 48#define STV090x_OFFST_OUTPARRS3_HZ_FIELD 3
49#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1 49#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1
50 50
@@ -113,24 +113,24 @@
113#define STV090x_IRQMASK3 0xf124 113#define STV090x_IRQMASK3 0xf124
114#define STV090x_OFFST_MPLL_LOCK_FIELD 5 114#define STV090x_OFFST_MPLL_LOCK_FIELD 5
115#define STV090x_WIDTH_MPLL_LOCK_FIELD 1 115#define STV090x_WIDTH_MPLL_LOCK_FIELD 1
116#define STV090x_OFFST_MSTREAM_LCK_3_FIELD 2 116#define STV090x_OFFST_MSTREAM_LCK_3_FIELD 4
117#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD 3 117#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD 1
118#define STV090x_OFFST_MSTREAM_LCK_2_FIELD 2 118#define STV090x_OFFST_MSTREAM_LCK_2_FIELD 3
119#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD 3 119#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD 1
120#define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2 120#define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2
121#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD 3 121#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD 1
122#define STV090x_OFFST_MDVBS1_PRF_2_FIELD 1 122#define STV090x_OFFST_MDVBS1_PRF_2_FIELD 1
123#define STV090x_WIDTH_MDVBS1_PRF_2_FIELD 1 123#define STV090x_WIDTH_MDVBS1_PRF_2_FIELD 1
124#define STV090x_OFFST_MDVBS1_PRF_1_FIELD 0 124#define STV090x_OFFST_MDVBS1_PRF_1_FIELD 0
125#define STV090x_WIDTH_MDVBS1_PRF_1_FIELD 1 125#define STV090x_WIDTH_MDVBS1_PRF_1_FIELD 1
126 126
127#define STV090x_IRQMASK2 0xf125 127#define STV090x_IRQMASK2 0xf125
128#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD 5 128#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD 7
129#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD 3 129#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD 1
130#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD 5 130#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD 6
131#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD 3 131#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD 1
132#define STV090x_OFFST_MSPY_ENDSIM_1_FIELD 5 132#define STV090x_OFFST_MSPY_ENDSIM_1_FIELD 5
133#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD 3 133#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD 1
134#define STV090x_OFFST_MPKTDEL_ERROR_2_FIELD 4 134#define STV090x_OFFST_MPKTDEL_ERROR_2_FIELD 4
135#define STV090x_WIDTH_MPKTDEL_ERROR_2_FIELD 1 135#define STV090x_WIDTH_MPKTDEL_ERROR_2_FIELD 1
136#define STV090x_OFFST_MPKTDEL_LOCKB_2_FIELD 3 136#define STV090x_OFFST_MPKTDEL_LOCKB_2_FIELD 3
@@ -370,7 +370,7 @@
370#define STV090x_OFFST_SELX1RATIO_FIELD 5 370#define STV090x_OFFST_SELX1RATIO_FIELD 5
371#define STV090x_WIDTH_SELX1RATIO_FIELD 1 371#define STV090x_WIDTH_SELX1RATIO_FIELD 1
372#define STV090x_OFFST_STOP_PLL_FIELD 3 372#define STV090x_OFFST_STOP_PLL_FIELD 3
373#define STV090x_WIDTH_SELX1RATIO_FIELD 1 373#define STV090x_WIDTH_STOP_PLL_FIELD 1
374#define STV090x_OFFST_BYPASSPLLFSK_FIELD 2 374#define STV090x_OFFST_BYPASSPLLFSK_FIELD 2
375#define STV090x_WIDTH_BYPASSPLLFSK_FIELD 1 375#define STV090x_WIDTH_BYPASSPLLFSK_FIELD 1
376#define STV090x_OFFST_SELOSCI_FIELD 1 376#define STV090x_OFFST_SELOSCI_FIELD 1
@@ -616,7 +616,7 @@
616#define STV090x_OFFST_Px_CONT_TONE_FIELD 4 616#define STV090x_OFFST_Px_CONT_TONE_FIELD 4
617#define STV090x_WIDTH_Px_CONT_TONE_FIELD 1 617#define STV090x_WIDTH_Px_CONT_TONE_FIELD 1
618#define STV090x_OFFST_Px_FIFO_4BREADY_FIELD 3 618#define STV090x_OFFST_Px_FIFO_4BREADY_FIELD 3
619#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD 2 619#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD 1
620#define STV090x_OFFST_Px_FIFO_EMPTY_FIELD 2 620#define STV090x_OFFST_Px_FIFO_EMPTY_FIELD 2
621#define STV090x_WIDTH_Px_FIFO_EMPTY_FIELD 1 621#define STV090x_WIDTH_Px_FIFO_EMPTY_FIELD 1
622#define STV090x_OFFST_Px_ABORT_DISRX_FIELD 0 622#define STV090x_OFFST_Px_ABORT_DISRX_FIELD 0
@@ -847,12 +847,10 @@
847#define STV090x_WIDTH_Px_DVBS2_ENABLE_FIELD 1 847#define STV090x_WIDTH_Px_DVBS2_ENABLE_FIELD 1
848#define STV090x_OFFST_Px_DVBS1_ENABLE_FIELD 6 848#define STV090x_OFFST_Px_DVBS1_ENABLE_FIELD 6
849#define STV090x_WIDTH_Px_DVBS1_ENABLE_FIELD 1 849#define STV090x_WIDTH_Px_DVBS1_ENABLE_FIELD 1
850#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD 5 /* check */ 850#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD 4
851#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD 1
852#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD 4 /* check */
853#define STV090x_WIDTH_Px_SCAN_ENABLE_FIELD 1 851#define STV090x_WIDTH_Px_SCAN_ENABLE_FIELD 1
854#define STV090x_OFFST_Px_TUN_AUTOSCAN_FIELD 3 852#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD 3
855#define STV090x_WIDTH_Px_TUN_AUTOSCAN_FIELD 1 853#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD 1
856#define STV090x_OFFST_Px_NOFORCE_RELOCK_FIELD 2 854#define STV090x_OFFST_Px_NOFORCE_RELOCK_FIELD 2
857#define STV090x_WIDTH_Px_NOFORCE_RELOCK_FIELD 1 855#define STV090x_WIDTH_Px_NOFORCE_RELOCK_FIELD 1
858#define STV090x_OFFST_Px_TUN_RNG_FIELD 0 856#define STV090x_OFFST_Px_TUN_RNG_FIELD 0
@@ -885,7 +883,7 @@
885#define STV090x_P2_DMDFLYW STV090x_Px_DMDFLYW(2) 883#define STV090x_P2_DMDFLYW STV090x_Px_DMDFLYW(2)
886#define STV090x_OFFST_Px_I2C_IRQVAL_FIELD 4 884#define STV090x_OFFST_Px_I2C_IRQVAL_FIELD 4
887#define STV090x_WIDTH_Px_I2C_IRQVAL_FIELD 4 885#define STV090x_WIDTH_Px_I2C_IRQVAL_FIELD 4
888#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD 0 /* check */ 886#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD 0
889#define STV090x_WIDTH_Px_FLYWHEEL_CPT_FIELD 4 887#define STV090x_WIDTH_Px_FLYWHEEL_CPT_FIELD 4
890 888
891#define STV090x_Px_DSTATUS3(__x) (0xF41D - (__x - 1) * 0x200) 889#define STV090x_Px_DSTATUS3(__x) (0xF41D - (__x - 1) * 0x200)
@@ -1048,12 +1046,12 @@
1048#define STV090x_P1_CFRINC1 STV090x_Px_CFRINC1(1) 1046#define STV090x_P1_CFRINC1 STV090x_Px_CFRINC1(1)
1049#define STV090x_P2_CFRINC1 STV090x_Px_CFRINC1(2) 1047#define STV090x_P2_CFRINC1 STV090x_Px_CFRINC1(2)
1050#define STV090x_OFFST_Px_CFR_INC1_FIELD 0 1048#define STV090x_OFFST_Px_CFR_INC1_FIELD 0
1051#define STV090x_WIDTH_Px_CFR_INC1_FIELD 7 1049#define STV090x_WIDTH_Px_CFR_INC1_FIELD 7 /* check */
1052 1050
1053#define STV090x_Px_CFRINC0(__x) (0xF44B - (__x - 1) * 0x200) 1051#define STV090x_Px_CFRINC0(__x) (0xF44B - (__x - 1) * 0x200)
1054#define STV090x_P1_CFRINC0 STV090x_Px_CFRINC0(1) 1052#define STV090x_P1_CFRINC0 STV090x_Px_CFRINC0(1)
1055#define STV090x_P2_CFRINC0 STV090x_Px_CFRINC0(2) 1053#define STV090x_P2_CFRINC0 STV090x_Px_CFRINC0(2)
1056#define STV090x_OFFST_Px_CFR_INC0_FIELD 4 1054#define STV090x_OFFST_Px_CFR_INC0_FIELD 4 /* check */
1057#define STV090x_WIDTH_Px_CFR_INC0_FIELD 4 1055#define STV090x_WIDTH_Px_CFR_INC0_FIELD 4
1058 1056
1059#define STV090x_Pn_CFRy(__x, __y) (0xF44E - (__x - 1) * 0x200 - __y * 0x1) 1057#define STV090x_Pn_CFRy(__x, __y) (0xF44E - (__x - 1) * 0x200 - __y * 0x1)
@@ -1145,14 +1143,14 @@
1145#define STV090x_Px_SFRINIT1(__x) (0xF45E - (__x - 1) * 0x200) 1143#define STV090x_Px_SFRINIT1(__x) (0xF45E - (__x - 1) * 0x200)
1146#define STV090x_P1_SFRINIT1 STV090x_Px_SFRINIT1(1) 1144#define STV090x_P1_SFRINIT1 STV090x_Px_SFRINIT1(1)
1147#define STV090x_P2_SFRINIT1 STV090x_Px_SFRINIT1(2) 1145#define STV090x_P2_SFRINIT1 STV090x_Px_SFRINIT1(2)
1148#define STV090x_OFFST_Px_SFR_INIT_FIELD 0 1146#define STV090x_OFFST_Px_SFR_INIT1_FIELD 0
1149#define STV090x_WIDTH_Px_SFR_INIT_FIELD 8 1147#define STV090x_WIDTH_Px_SFR_INIT1_FIELD 7
1150 1148
1151#define STV090x_Px_SFRINIT0(__x) (0xF45F - (__x - 1) * 0x200) 1149#define STV090x_Px_SFRINIT0(__x) (0xF45F - (__x - 1) * 0x200)
1152#define STV090x_P1_SFRINIT0 STV090x_Px_SFRINIT0(1) 1150#define STV090x_P1_SFRINIT0 STV090x_Px_SFRINIT0(1)
1153#define STV090x_P2_SFRINIT0 STV090x_Px_SFRINIT0(2) 1151#define STV090x_P2_SFRINIT0 STV090x_Px_SFRINIT0(2)
1154#define STV090x_OFFST_Px_SFR_INIT_FIELD 0 1152#define STV090x_OFFST_Px_SFR_INIT0_FIELD 0
1155#define STV090x_WIDTH_Px_SFR_INIT_FIELD 8 1153#define STV090x_WIDTH_Px_SFR_INIT0_FIELD 8
1156 1154
1157#define STV090x_Px_SFRUP1(__x) (0xF460 - (__x - 1) * 0x200) 1155#define STV090x_Px_SFRUP1(__x) (0xF460 - (__x - 1) * 0x200)
1158#define STV090x_P1_SFRUP1 STV090x_Px_SFRUP1(1) 1156#define STV090x_P1_SFRUP1 STV090x_Px_SFRUP1(1)
@@ -1178,7 +1176,7 @@
1178#define STV090x_OFFST_Px_SYMB_FREQ_LOW0_FIELD 0 1176#define STV090x_OFFST_Px_SYMB_FREQ_LOW0_FIELD 0
1179#define STV090x_WIDTH_Px_SYMB_FREQ_LOW0_FIELD 8 1177#define STV090x_WIDTH_Px_SYMB_FREQ_LOW0_FIELD 8
1180 1178
1181#define STV090x_Px_SFRy(__x, __y) (0xF464 - (__x-1) * 0x200 + (3 - __y)) 1179#define STV090x_Px_SFRy(__x, __y) (0xF467 - (__x-1) * 0x200 - __y)
1182#define STV090x_P1_SFR0 STV090x_Px_SFRy(1, 0) 1180#define STV090x_P1_SFR0 STV090x_Px_SFRy(1, 0)
1183#define STV090x_P1_SFR1 STV090x_Px_SFRy(1, 1) 1181#define STV090x_P1_SFR1 STV090x_Px_SFRy(1, 1)
1184#define STV090x_P1_SFR2 STV090x_Px_SFRy(1, 2) 1182#define STV090x_P1_SFR2 STV090x_Px_SFRy(1, 2)
@@ -1188,7 +1186,7 @@
1188#define STV090x_P2_SFR2 STV090x_Px_SFRy(2, 2) 1186#define STV090x_P2_SFR2 STV090x_Px_SFRy(2, 2)
1189#define STV090x_P2_SFR3 STV090x_Px_SFRy(2, 3) 1187#define STV090x_P2_SFR3 STV090x_Px_SFRy(2, 3)
1190#define STV090x_OFFST_Px_SYMB_FREQ_FIELD 0 1188#define STV090x_OFFST_Px_SYMB_FREQ_FIELD 0
1191#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD 32 1189#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD 8
1192 1190
1193#define STV090x_Px_TMGREG2(__x) (0xF468 - (__x - 1) * 0x200) 1191#define STV090x_Px_TMGREG2(__x) (0xF468 - (__x - 1) * 0x200)
1194#define STV090x_P1_TMGREG2 STV090x_Px_TMGREG2(1) 1192#define STV090x_P1_TMGREG2 STV090x_Px_TMGREG2(1)
@@ -1198,7 +1196,7 @@
1198 1196
1199#define STV090x_Px_TMGREG1(__x) (0xF469 - (__x - 1) * 0x200) 1197#define STV090x_Px_TMGREG1(__x) (0xF469 - (__x - 1) * 0x200)
1200#define STV090x_P1_TMGREG1 STV090x_Px_TMGREG1(1) 1198#define STV090x_P1_TMGREG1 STV090x_Px_TMGREG1(1)
1201#define STV090x_P2_TMGREG1 STV090x_Px_TMGREG1(2) 1199#define STV090x_P2_TMGREG1 STV090x_Px_TMGREG1(2)
1202#define STV090x_OFFST_Px_TMGREG_FIELD 0 1200#define STV090x_OFFST_Px_TMGREG_FIELD 0
1203#define STV090x_WIDTH_Px_TMGREG_FIELD 8 1201#define STV090x_WIDTH_Px_TMGREG_FIELD 8
1204 1202
@@ -1230,7 +1228,7 @@
1230#define STV090x_OFFST_Px_MU_EQUALDFE_FIELD 0 1228#define STV090x_OFFST_Px_MU_EQUALDFE_FIELD 0
1231#define STV090x_WIDTH_Px_MU_EQUALDFE_FIELD 3 1229#define STV090x_WIDTH_Px_MU_EQUALDFE_FIELD 3
1232 1230
1233#define STV090x_Px_EQUAIy(__x, __y) (0xf470 - (__x - 1) * 0x200 + (__y - 1)) 1231#define STV090x_Px_EQUAIy(__x, __y) (0xf470 - (__x-1) * 0x200 + 2 * (__y-1))
1234#define STV090x_P1_EQUAI1 STV090x_Px_EQUAIy(1, 1) 1232#define STV090x_P1_EQUAI1 STV090x_Px_EQUAIy(1, 1)
1235#define STV090x_P1_EQUAI2 STV090x_Px_EQUAIy(1, 2) 1233#define STV090x_P1_EQUAI2 STV090x_Px_EQUAIy(1, 2)
1236#define STV090x_P1_EQUAI3 STV090x_Px_EQUAIy(1, 3) 1234#define STV090x_P1_EQUAI3 STV090x_Px_EQUAIy(1, 3)
@@ -1251,7 +1249,7 @@
1251#define STV090x_OFFST_Px_EQUA_ACCIy_FIELD 0 1249#define STV090x_OFFST_Px_EQUA_ACCIy_FIELD 0
1252#define STV090x_WIDTH_Px_EQUA_ACCIy_FIELD 8 1250#define STV090x_WIDTH_Px_EQUA_ACCIy_FIELD 8
1253 1251
1254#define STV090x_Px_EQUAQy(__x, __y) (0xf471 - (__x - 1) * 0x200 + (__y - 1)) 1252#define STV090x_Px_EQUAQy(__x, __y) (0xf471 - (__x-1) * 0x200 + 2 * (__y-1))
1255#define STV090x_P1_EQUAQ1 STV090x_Px_EQUAQy(1, 1) 1253#define STV090x_P1_EQUAQ1 STV090x_Px_EQUAQy(1, 1)
1256#define STV090x_P1_EQUAQ2 STV090x_Px_EQUAQy(1, 2) 1254#define STV090x_P1_EQUAQ2 STV090x_Px_EQUAQy(1, 2)
1257#define STV090x_P1_EQUAQ3 STV090x_Px_EQUAQy(1, 3) 1255#define STV090x_P1_EQUAQ3 STV090x_Px_EQUAQy(1, 3)
@@ -1390,7 +1388,7 @@
1390#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_E_FIELD 0 1388#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_E_FIELD 0
1391#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_E_FIELD 4 1389#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_E_FIELD 4
1392 1390
1393#define STV090x_Px_ACLC2S232A(__x) (0xf499 - (__x - 1) * 0x200) 1391#define STV090x_Px_ACLC2S232A(__x) (0xf49A - (__x - 1) * 0x200)
1394#define STV090x_P1_ACLC2S232A STV090x_Px_ACLC2S232A(1) 1392#define STV090x_P1_ACLC2S232A STV090x_Px_ACLC2S232A(1)
1395#define STV090x_P2_ACLC2S232A STV090x_Px_ACLC2S232A(2) 1393#define STV090x_P2_ACLC2S232A STV090x_Px_ACLC2S232A(2)
1396#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_M_FIELD 4 1394#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_M_FIELD 4
@@ -1414,7 +1412,7 @@
1414#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0 1412#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0
1415#define STV090x_WIDTH_Px_CAR2S2_8_BETA_E_FIELD 4 1413#define STV090x_WIDTH_Px_CAR2S2_8_BETA_E_FIELD 4
1416 1414
1417#define STV090x_Px_BCLC2S216A(__x) (0xf49d - (__x - 1) * 0x200) 1415#define STV090x_Px_BCLC2S216A(__x) (0xf49e - (__x - 1) * 0x200)
1418#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1) 1416#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1)
1419#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(1) 1417#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(1)
1420#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4 1418#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4
@@ -1422,7 +1420,7 @@
1422#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0 1420#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0
1423#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_E_FIELD 4 1421#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_E_FIELD 4
1424 1422
1425#define STV090x_Px_BCLC2S232A(__x) (0xf49d - (__x - 1) * 0x200) 1423#define STV090x_Px_BCLC2S232A(__x) (0xf49f - (__x - 1) * 0x200)
1426#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1) 1424#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1)
1427#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(1) 1425#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(1)
1428#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4 1426#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4
@@ -1458,7 +1456,7 @@
1458#define STV090x_P1_MODCODLST1 STV090x_Px_MODCODLST1(1) 1456#define STV090x_P1_MODCODLST1 STV090x_Px_MODCODLST1(1)
1459#define STV090x_P2_MODCODLST1 STV090x_Px_MODCODLST1(2) 1457#define STV090x_P2_MODCODLST1 STV090x_Px_MODCODLST1(2)
1460#define STV090x_OFFST_Px_DIS_MODCOD29_FIELD 4 1458#define STV090x_OFFST_Px_DIS_MODCOD29_FIELD 4
1461#define STV090x_WIDTH_Px_DIS_MODCOD29T_FIELD 4 1459#define STV090x_WIDTH_Px_DIS_MODCOD29_FIELD 4
1462#define STV090x_OFFST_Px_DIS_32PSK_9_10_FIELD 0 1460#define STV090x_OFFST_Px_DIS_32PSK_9_10_FIELD 0
1463#define STV090x_WIDTH_Px_DIS_32PSK_9_10_FIELD 4 1461#define STV090x_WIDTH_Px_DIS_32PSK_9_10_FIELD 4
1464 1462
@@ -2180,7 +2178,7 @@
2180#define STV090x_WIDTH_Px_TSFIFOSPEED_STORE_FIELD 1 2178#define STV090x_WIDTH_Px_TSFIFOSPEED_STORE_FIELD 1
2181#define STV090x_OFFST_Px_DILXX_RESET_FIELD 5 2179#define STV090x_OFFST_Px_DILXX_RESET_FIELD 5
2182#define STV090x_WIDTH_Px_DILXX_RESET_FIELD 1 2180#define STV090x_WIDTH_Px_DILXX_RESET_FIELD 1
2183#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD 5 2181#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD 4
2184#define STV090x_WIDTH_Px_TSSERIAL_IMPOS_FIELD 1 2182#define STV090x_WIDTH_Px_TSSERIAL_IMPOS_FIELD 1
2185#define STV090x_OFFST_Px_SCRAMBDETECT_FIELD 1 2183#define STV090x_OFFST_Px_SCRAMBDETECT_FIELD 1
2186#define STV090x_WIDTH_Px_SCRAMBDETECT_FIELD 1 2184#define STV090x_WIDTH_Px_SCRAMBDETECT_FIELD 1
@@ -2190,7 +2188,7 @@
2190#define STV090x_P1_TSBITRATE1 STV090x_Px_TSBITRATEy(1, 1) 2188#define STV090x_P1_TSBITRATE1 STV090x_Px_TSBITRATEy(1, 1)
2191#define STV090x_P2_TSBITRATE0 STV090x_Px_TSBITRATEy(2, 0) 2189#define STV090x_P2_TSBITRATE0 STV090x_Px_TSBITRATEy(2, 0)
2192#define STV090x_P2_TSBITRATE1 STV090x_Px_TSBITRATEy(2, 1) 2190#define STV090x_P2_TSBITRATE1 STV090x_Px_TSBITRATEy(2, 1)
2193#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD 7 2191#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD 0
2194#define STV090x_WIDTH_Px_TSFIFO_BITRATE_FIELD 8 2192#define STV090x_WIDTH_Px_TSFIFO_BITRATE_FIELD 8
2195 2193
2196#define STV090x_Px_ERRCTRL1(__x) (0xF598 - (__x - 1) * 0x200) 2194#define STV090x_Px_ERRCTRL1(__x) (0xF598 - (__x - 1) * 0x200)
diff --git a/drivers/media/dvb/frontends/stv6110.c b/drivers/media/dvb/frontends/stv6110.c
index dcf1b21ea974..bef0cc838471 100644
--- a/drivers/media/dvb/frontends/stv6110.c
+++ b/drivers/media/dvb/frontends/stv6110.c
@@ -37,6 +37,7 @@ struct stv6110_priv {
37 37
38 u32 mclk; 38 u32 mclk;
39 u8 clk_div; 39 u8 clk_div;
40 u8 gain;
40 u8 regs[8]; 41 u8 regs[8];
41}; 42};
42 43
@@ -255,7 +256,7 @@ static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
255 u8 ret = 0x04; 256 u8 ret = 0x04;
256 u32 divider, ref, p, presc, i, result_freq, vco_freq; 257 u32 divider, ref, p, presc, i, result_freq, vco_freq;
257 s32 p_calc, p_calc_opt = 1000, r_div, r_div_opt = 0, p_val; 258 s32 p_calc, p_calc_opt = 1000, r_div, r_div_opt = 0, p_val;
258 s32 srate; u8 gain; 259 s32 srate;
259 260
260 dprintk("%s, freq=%d kHz, mclk=%d Hz\n", __func__, 261 dprintk("%s, freq=%d kHz, mclk=%d Hz\n", __func__,
261 frequency, priv->mclk); 262 frequency, priv->mclk);
@@ -273,15 +274,8 @@ static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
273 } else 274 } else
274 srate = 15000000; 275 srate = 15000000;
275 276
276 if (srate >= 15000000)
277 gain = 3; /* +6 dB */
278 else if (srate >= 5000000)
279 gain = 3; /* +6 dB */
280 else
281 gain = 3; /* +6 dB */
282
283 priv->regs[RSTV6110_CTRL2] &= ~0x0f; 277 priv->regs[RSTV6110_CTRL2] &= ~0x0f;
284 priv->regs[RSTV6110_CTRL2] |= (gain & 0x0f); 278 priv->regs[RSTV6110_CTRL2] |= (priv->gain & 0x0f);
285 279
286 if (frequency <= 1023000) { 280 if (frequency <= 1023000) {
287 p = 1; 281 p = 1;
@@ -436,6 +430,7 @@ struct dvb_frontend *stv6110_attach(struct dvb_frontend *fe,
436 priv->i2c = i2c; 430 priv->i2c = i2c;
437 priv->mclk = config->mclk; 431 priv->mclk = config->mclk;
438 priv->clk_div = config->clk_div; 432 priv->clk_div = config->clk_div;
433 priv->gain = config->gain;
439 434
440 memcpy(&priv->regs, &reg0[1], 8); 435 memcpy(&priv->regs, &reg0[1], 8);
441 436
diff --git a/drivers/media/dvb/frontends/stv6110.h b/drivers/media/dvb/frontends/stv6110.h
index 9db2402410f6..fe71bba6a26e 100644
--- a/drivers/media/dvb/frontends/stv6110.h
+++ b/drivers/media/dvb/frontends/stv6110.h
@@ -41,6 +41,7 @@
41struct stv6110_config { 41struct stv6110_config {
42 u8 i2c_address; 42 u8 i2c_address;
43 u32 mclk; 43 u32 mclk;
44 u8 gain;
44 u8 clk_div; /* divisor value for the output clock */ 45 u8 clk_div; /* divisor value for the output clock */
45}; 46};
46 47
diff --git a/drivers/media/dvb/frontends/stv6110x.c b/drivers/media/dvb/frontends/stv6110x.c
index 3d8a2e01c9c4..bcfcb652464c 100644
--- a/drivers/media/dvb/frontends/stv6110x.c
+++ b/drivers/media/dvb/frontends/stv6110x.c
@@ -95,7 +95,7 @@ static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
95{ 95{
96 struct stv6110x_state *stv6110x = fe->tuner_priv; 96 struct stv6110x_state *stv6110x = fe->tuner_priv;
97 u32 rDiv, divider; 97 u32 rDiv, divider;
98 s32 pVal, pCalc, rDivOpt = 0; 98 s32 pVal, pCalc, rDivOpt = 0, pCalcOpt = 1000;
99 u8 i; 99 u8 i;
100 100
101 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16)); 101 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16));
@@ -121,8 +121,10 @@ static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
121 for (rDiv = 0; rDiv <= 3; rDiv++) { 121 for (rDiv = 0; rDiv <= 3; rDiv++) {
122 pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv); 122 pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv);
123 123
124 if ((abs((s32)(pCalc - pVal))) < (abs((s32)(1000 - pVal)))) 124 if ((abs((s32)(pCalc - pVal))) < (abs((s32)(pCalcOpt - pVal))))
125 rDivOpt = rDiv; 125 rDivOpt = rDiv;
126
127 pCalcOpt = (REFCLOCK_kHz / 100) / R_DIV(rDivOpt);
126 } 128 }
127 129
128 divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz; 130 divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 15:56:43 -0500