aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/media/dvb/frontends/dib7000p.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/media/dvb/frontends/dib7000p.c')
-rw-r--r--drivers/media/dvb/frontends/dib7000p.c1945
1 files changed, 1421 insertions, 524 deletions
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index 6aa02cb80733..900af60b9d36 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -26,24 +26,29 @@ MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (defau
26 26
27#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0) 27#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0)
28 28
29struct i2c_device {
30 struct i2c_adapter *i2c_adap;
31 u8 i2c_addr;
32};
33
29struct dib7000p_state { 34struct dib7000p_state {
30 struct dvb_frontend demod; 35 struct dvb_frontend demod;
31 struct dib7000p_config cfg; 36 struct dib7000p_config cfg;
32 37
33 u8 i2c_addr; 38 u8 i2c_addr;
34 struct i2c_adapter *i2c_adap; 39 struct i2c_adapter *i2c_adap;
35 40
36 struct dibx000_i2c_master i2c_master; 41 struct dibx000_i2c_master i2c_master;
37 42
38 u16 wbd_ref; 43 u16 wbd_ref;
39 44
40 u8 current_band; 45 u8 current_band;
41 u32 current_bandwidth; 46 u32 current_bandwidth;
42 struct dibx000_agc_config *current_agc; 47 struct dibx000_agc_config *current_agc;
43 u32 timf; 48 u32 timf;
44 49
45 u8 div_force_off : 1; 50 u8 div_force_off:1;
46 u8 div_state : 1; 51 u8 div_state:1;
47 u16 div_sync_wait; 52 u16 div_sync_wait;
48 53
49 u8 agc_state; 54 u8 agc_state;
@@ -51,7 +56,13 @@ struct dib7000p_state {
51 u16 gpio_dir; 56 u16 gpio_dir;
52 u16 gpio_val; 57 u16 gpio_val;
53 58
54 u8 sfn_workaround_active :1; 59 u8 sfn_workaround_active:1;
60
61#define SOC7090 0x7090
62 u16 version;
63
64 u16 tuner_enable;
65 struct i2c_adapter dib7090_tuner_adap;
55}; 66};
56 67
57enum dib7000p_power_mode { 68enum dib7000p_power_mode {
@@ -60,17 +71,20 @@ enum dib7000p_power_mode {
60 DIB7000P_POWER_INTERFACE_ONLY, 71 DIB7000P_POWER_INTERFACE_ONLY,
61}; 72};
62 73
74static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
75static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
76
63static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg) 77static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
64{ 78{
65 u8 wb[2] = { reg >> 8, reg & 0xff }; 79 u8 wb[2] = { reg >> 8, reg & 0xff };
66 u8 rb[2]; 80 u8 rb[2];
67 struct i2c_msg msg[2] = { 81 struct i2c_msg msg[2] = {
68 { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 }, 82 {.addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
69 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 }, 83 {.addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
70 }; 84 };
71 85
72 if (i2c_transfer(state->i2c_adap, msg, 2) != 2) 86 if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
73 dprintk("i2c read error on %d",reg); 87 dprintk("i2c read error on %d", reg);
74 88
75 return (rb[0] << 8) | rb[1]; 89 return (rb[0] << 8) | rb[1];
76} 90}
@@ -86,7 +100,8 @@ static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
86 }; 100 };
87 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; 101 return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
88} 102}
89static void dib7000p_write_tab(struct dib7000p_state *state, u16 *buf) 103
104static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
90{ 105{
91 u16 l = 0, r, *n; 106 u16 l = 0, r, *n;
92 n = buf; 107 n = buf;
@@ -104,54 +119,54 @@ static void dib7000p_write_tab(struct dib7000p_state *state, u16 *buf)
104 119
105static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode) 120static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
106{ 121{
107 int ret = 0; 122 int ret = 0;
108 u16 outreg, fifo_threshold, smo_mode; 123 u16 outreg, fifo_threshold, smo_mode;
109 124
110 outreg = 0; 125 outreg = 0;
111 fifo_threshold = 1792; 126 fifo_threshold = 1792;
112 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1); 127 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
113 128
114 dprintk( "setting output mode for demod %p to %d", 129 dprintk("setting output mode for demod %p to %d", &state->demod, mode);
115 &state->demod, mode);
116 130
117 switch (mode) { 131 switch (mode) {
118 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock 132 case OUTMODE_MPEG2_PAR_GATED_CLK:
119 outreg = (1 << 10); /* 0x0400 */ 133 outreg = (1 << 10); /* 0x0400 */
120 break; 134 break;
121 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock 135 case OUTMODE_MPEG2_PAR_CONT_CLK:
122 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ 136 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
123 break; 137 break;
124 case OUTMODE_MPEG2_SERIAL: // STBs with serial input 138 case OUTMODE_MPEG2_SERIAL:
125 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */ 139 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
126 break; 140 break;
127 case OUTMODE_DIVERSITY: 141 case OUTMODE_DIVERSITY:
128 if (state->cfg.hostbus_diversity) 142 if (state->cfg.hostbus_diversity)
129 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ 143 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
130 else 144 else
131 outreg = (1 << 11); 145 outreg = (1 << 11);
132 break; 146 break;
133 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding 147 case OUTMODE_MPEG2_FIFO:
134 smo_mode |= (3 << 1); 148 smo_mode |= (3 << 1);
135 fifo_threshold = 512; 149 fifo_threshold = 512;
136 outreg = (1 << 10) | (5 << 6); 150 outreg = (1 << 10) | (5 << 6);
137 break; 151 break;
138 case OUTMODE_ANALOG_ADC: 152 case OUTMODE_ANALOG_ADC:
139 outreg = (1 << 10) | (3 << 6); 153 outreg = (1 << 10) | (3 << 6);
140 break; 154 break;
141 case OUTMODE_HIGH_Z: // disable 155 case OUTMODE_HIGH_Z:
142 outreg = 0; 156 outreg = 0;
143 break; 157 break;
144 default: 158 default:
145 dprintk( "Unhandled output_mode passed to be set for demod %p",&state->demod); 159 dprintk("Unhandled output_mode passed to be set for demod %p", &state->demod);
146 break; 160 break;
147 } 161 }
148 162
149 if (state->cfg.output_mpeg2_in_188_bytes) 163 if (state->cfg.output_mpeg2_in_188_bytes)
150 smo_mode |= (1 << 5) ; 164 smo_mode |= (1 << 5);
151 165
152 ret |= dib7000p_write_word(state, 235, smo_mode); 166 ret |= dib7000p_write_word(state, 235, smo_mode);
153 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */ 167 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
154 ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */ 168 if (state->version != SOC7090)
169 ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
155 170
156 return ret; 171 return ret;
157} 172}
@@ -161,13 +176,13 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
161 struct dib7000p_state *state = demod->demodulator_priv; 176 struct dib7000p_state *state = demod->demodulator_priv;
162 177
163 if (state->div_force_off) { 178 if (state->div_force_off) {
164 dprintk( "diversity combination deactivated - forced by COFDM parameters"); 179 dprintk("diversity combination deactivated - forced by COFDM parameters");
165 onoff = 0; 180 onoff = 0;
166 dib7000p_write_word(state, 207, 0); 181 dib7000p_write_word(state, 207, 0);
167 } else 182 } else
168 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0)); 183 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
169 184
170 state->div_state = (u8)onoff; 185 state->div_state = (u8) onoff;
171 186
172 if (onoff) { 187 if (onoff) {
173 dib7000p_write_word(state, 204, 6); 188 dib7000p_write_word(state, 204, 6);
@@ -184,37 +199,48 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
184static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode) 199static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
185{ 200{
186 /* by default everything is powered off */ 201 /* by default everything is powered off */
187 u16 reg_774 = 0xffff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, 202 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
188 reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
189 203
190 /* now, depending on the requested mode, we power on */ 204 /* now, depending on the requested mode, we power on */
191 switch (mode) { 205 switch (mode) {
192 /* power up everything in the demod */ 206 /* power up everything in the demod */
193 case DIB7000P_POWER_ALL: 207 case DIB7000P_POWER_ALL:
194 reg_774 = 0x0000; reg_775 = 0x0000; reg_776 = 0x0; reg_899 = 0x0; reg_1280 &= 0x01ff; 208 reg_774 = 0x0000;
195 break; 209 reg_775 = 0x0000;
196 210 reg_776 = 0x0;
197 case DIB7000P_POWER_ANALOG_ADC: 211 reg_899 = 0x0;
198 /* dem, cfg, iqc, sad, agc */ 212 if (state->version == SOC7090)
199 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9)); 213 reg_1280 &= 0x001f;
200 /* nud */ 214 else
201 reg_776 &= ~((1 << 0)); 215 reg_1280 &= 0x01ff;
202 /* Dout */ 216 break;
217
218 case DIB7000P_POWER_ANALOG_ADC:
219 /* dem, cfg, iqc, sad, agc */
220 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
221 /* nud */
222 reg_776 &= ~((1 << 0));
223 /* Dout */
224 if (state->version != SOC7090)
203 reg_1280 &= ~((1 << 11)); 225 reg_1280 &= ~((1 << 11));
204 /* fall through wanted to enable the interfaces */ 226 reg_1280 &= ~(1 << 6);
227 /* fall through wanted to enable the interfaces */
205 228
206 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */ 229 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
207 case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */ 230 case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */
231 if (state->version == SOC7090)
232 reg_1280 &= ~((1 << 7) | (1 << 5));
233 else
208 reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10)); 234 reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
209 break; 235 break;
210 236
211/* TODO following stuff is just converted from the dib7000-driver - check when is used what */ 237/* TODO following stuff is just converted from the dib7000-driver - check when is used what */
212 } 238 }
213 239
214 dib7000p_write_word(state, 774, reg_774); 240 dib7000p_write_word(state, 774, reg_774);
215 dib7000p_write_word(state, 775, reg_775); 241 dib7000p_write_word(state, 775, reg_775);
216 dib7000p_write_word(state, 776, reg_776); 242 dib7000p_write_word(state, 776, reg_776);
217 dib7000p_write_word(state, 899, reg_899); 243 dib7000p_write_word(state, 899, reg_899);
218 dib7000p_write_word(state, 1280, reg_1280); 244 dib7000p_write_word(state, 1280, reg_1280);
219 245
220 return 0; 246 return 0;
@@ -222,40 +248,57 @@ static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_p
222 248
223static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no) 249static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
224{ 250{
225 u16 reg_908 = dib7000p_read_word(state, 908), 251 u16 reg_908 = dib7000p_read_word(state, 908), reg_909 = dib7000p_read_word(state, 909);
226 reg_909 = dib7000p_read_word(state, 909); 252 u16 reg;
227 253
228 switch (no) { 254 switch (no) {
229 case DIBX000_SLOW_ADC_ON: 255 case DIBX000_SLOW_ADC_ON:
256 if (state->version == SOC7090) {
257 reg = dib7000p_read_word(state, 1925);
258
259 dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */
260
261 reg = dib7000p_read_word(state, 1925); /* read acces to make it works... strange ... */
262 msleep(200);
263 dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */
264
265 reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
266 dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
267 } else {
230 reg_909 |= (1 << 1) | (1 << 0); 268 reg_909 |= (1 << 1) | (1 << 0);
231 dib7000p_write_word(state, 909, reg_909); 269 dib7000p_write_word(state, 909, reg_909);
232 reg_909 &= ~(1 << 1); 270 reg_909 &= ~(1 << 1);
233 break; 271 }
272 break;
234 273
235 case DIBX000_SLOW_ADC_OFF: 274 case DIBX000_SLOW_ADC_OFF:
236 reg_909 |= (1 << 1) | (1 << 0); 275 if (state->version == SOC7090) {
237 break; 276 reg = dib7000p_read_word(state, 1925);
277 dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
278 } else
279 reg_909 |= (1 << 1) | (1 << 0);
280 break;
238 281
239 case DIBX000_ADC_ON: 282 case DIBX000_ADC_ON:
240 reg_908 &= 0x0fff; 283 reg_908 &= 0x0fff;
241 reg_909 &= 0x0003; 284 reg_909 &= 0x0003;
242 break; 285 break;
243 286
244 case DIBX000_ADC_OFF: // leave the VBG voltage on 287 case DIBX000_ADC_OFF:
245 reg_908 |= (1 << 14) | (1 << 13) | (1 << 12); 288 reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
246 reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2); 289 reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
247 break; 290 break;
248 291
249 case DIBX000_VBG_ENABLE: 292 case DIBX000_VBG_ENABLE:
250 reg_908 &= ~(1 << 15); 293 reg_908 &= ~(1 << 15);
251 break; 294 break;
252 295
253 case DIBX000_VBG_DISABLE: 296 case DIBX000_VBG_DISABLE:
254 reg_908 |= (1 << 15); 297 reg_908 |= (1 << 15);
255 break; 298 break;
256 299
257 default: 300 default:
258 break; 301 break;
259 } 302 }
260 303
261// dprintk( "908: %x, 909: %x\n", reg_908, reg_909); 304// dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
@@ -275,17 +318,17 @@ static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
275 state->current_bandwidth = bw; 318 state->current_bandwidth = bw;
276 319
277 if (state->timf == 0) { 320 if (state->timf == 0) {
278 dprintk( "using default timf"); 321 dprintk("using default timf");
279 timf = state->cfg.bw->timf; 322 timf = state->cfg.bw->timf;
280 } else { 323 } else {
281 dprintk( "using updated timf"); 324 dprintk("using updated timf");
282 timf = state->timf; 325 timf = state->timf;
283 } 326 }
284 327
285 timf = timf * (bw / 50) / 160; 328 timf = timf * (bw / 50) / 160;
286 329
287 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); 330 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
288 dib7000p_write_word(state, 24, (u16) ((timf ) & 0xffff)); 331 dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
289 332
290 return 0; 333 return 0;
291} 334}
@@ -293,9 +336,12 @@ static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
293static int dib7000p_sad_calib(struct dib7000p_state *state) 336static int dib7000p_sad_calib(struct dib7000p_state *state)
294{ 337{
295/* internal */ 338/* internal */
296// dib7000p_write_word(state, 72, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth
297 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0)); 339 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
298 dib7000p_write_word(state, 74, 776); // 0.625*3.3 / 4096 340
341 if (state->version == SOC7090)
342 dib7000p_write_word(state, 74, 2048);
343 else
344 dib7000p_write_word(state, 74, 776);
299 345
300 /* do the calibration */ 346 /* do the calibration */
301 dib7000p_write_word(state, 73, (1 << 0)); 347 dib7000p_write_word(state, 73, (1 << 0));
@@ -314,37 +360,91 @@ int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
314 state->wbd_ref = value; 360 state->wbd_ref = value;
315 return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value); 361 return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
316} 362}
317
318EXPORT_SYMBOL(dib7000p_set_wbd_ref); 363EXPORT_SYMBOL(dib7000p_set_wbd_ref);
364
319static void dib7000p_reset_pll(struct dib7000p_state *state) 365static void dib7000p_reset_pll(struct dib7000p_state *state)
320{ 366{
321 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; 367 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
322 u16 clk_cfg0; 368 u16 clk_cfg0;
323 369
324 /* force PLL bypass */ 370 if (state->version == SOC7090) {
325 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) | 371 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
326 (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | 372
327 (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0); 373 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
374 ;
328 375
329 dib7000p_write_word(state, 900, clk_cfg0); 376 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
377 } else {
378 /* force PLL bypass */
379 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
380 (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
381
382 dib7000p_write_word(state, 900, clk_cfg0);
330 383
331 /* P_pll_cfg */ 384 /* P_pll_cfg */
332 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset); 385 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
333 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff); 386 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
334 dib7000p_write_word(state, 900, clk_cfg0); 387 dib7000p_write_word(state, 900, clk_cfg0);
388 }
335 389
336 dib7000p_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); 390 dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
337 dib7000p_write_word(state, 19, (u16) ( (bw->internal*1000 ) & 0xffff)); 391 dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
338 dib7000p_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); 392 dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
339 dib7000p_write_word(state, 22, (u16) ( (bw->ifreq ) & 0xffff)); 393 dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
340 394
341 dib7000p_write_word(state, 72, bw->sad_cfg); 395 dib7000p_write_word(state, 72, bw->sad_cfg);
342} 396}
343 397
398static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
399{
400 u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
401 internal |= (u32) dib7000p_read_word(state, 19);
402 internal /= 1000;
403
404 return internal;
405}
406
407int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
408{
409 struct dib7000p_state *state = fe->demodulator_priv;
410 u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
411 u8 loopdiv, prediv;
412 u32 internal, xtal;
413
414 /* get back old values */
415 prediv = reg_1856 & 0x3f;
416 loopdiv = (reg_1856 >> 6) & 0x3f;
417
418 if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
419 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
420 reg_1856 &= 0xf000;
421 reg_1857 = dib7000p_read_word(state, 1857);
422 dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
423
424 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
425
426 /* write new system clk into P_sec_len */
427 internal = dib7000p_get_internal_freq(state);
428 xtal = (internal / loopdiv) * prediv;
429 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
430 dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
431 dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
432
433 dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
434
435 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
436 dprintk("Waiting for PLL to lock");
437
438 return 0;
439 }
440 return -EIO;
441}
442EXPORT_SYMBOL(dib7000p_update_pll);
443
344static int dib7000p_reset_gpio(struct dib7000p_state *st) 444static int dib7000p_reset_gpio(struct dib7000p_state *st)
345{ 445{
346 /* reset the GPIOs */ 446 /* reset the GPIOs */
347 dprintk( "gpio dir: %x: val: %x, pwm_pos: %x",st->gpio_dir, st->gpio_val,st->cfg.gpio_pwm_pos); 447 dprintk("gpio dir: %x: val: %x, pwm_pos: %x", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
348 448
349 dib7000p_write_word(st, 1029, st->gpio_dir); 449 dib7000p_write_word(st, 1029, st->gpio_dir);
350 dib7000p_write_word(st, 1030, st->gpio_val); 450 dib7000p_write_word(st, 1030, st->gpio_val);
@@ -360,13 +460,13 @@ static int dib7000p_reset_gpio(struct dib7000p_state *st)
360static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val) 460static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
361{ 461{
362 st->gpio_dir = dib7000p_read_word(st, 1029); 462 st->gpio_dir = dib7000p_read_word(st, 1029);
363 st->gpio_dir &= ~(1 << num); /* reset the direction bit */ 463 st->gpio_dir &= ~(1 << num); /* reset the direction bit */
364 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */ 464 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
365 dib7000p_write_word(st, 1029, st->gpio_dir); 465 dib7000p_write_word(st, 1029, st->gpio_dir);
366 466
367 st->gpio_val = dib7000p_read_word(st, 1030); 467 st->gpio_val = dib7000p_read_word(st, 1030);
368 st->gpio_val &= ~(1 << num); /* reset the direction bit */ 468 st->gpio_val &= ~(1 << num); /* reset the direction bit */
369 st->gpio_val |= (val & 0x01) << num; /* set the new value */ 469 st->gpio_val |= (val & 0x01) << num; /* set the new value */
370 dib7000p_write_word(st, 1030, st->gpio_val); 470 dib7000p_write_word(st, 1030, st->gpio_val);
371 471
372 return 0; 472 return 0;
@@ -377,96 +477,94 @@ int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
377 struct dib7000p_state *state = demod->demodulator_priv; 477 struct dib7000p_state *state = demod->demodulator_priv;
378 return dib7000p_cfg_gpio(state, num, dir, val); 478 return dib7000p_cfg_gpio(state, num, dir, val);
379} 479}
380
381EXPORT_SYMBOL(dib7000p_set_gpio); 480EXPORT_SYMBOL(dib7000p_set_gpio);
382static u16 dib7000p_defaults[] =
383 481
384{ 482static u16 dib7000p_defaults[] = {
385 // auto search configuration 483 // auto search configuration
386 3, 2, 484 3, 2,
387 0x0004, 485 0x0004,
388 0x1000, 486 0x1000,
389 0x0814, /* Equal Lock */ 487 0x0814, /* Equal Lock */
390 488
391 12, 6, 489 12, 6,
392 0x001b, 490 0x001b,
393 0x7740, 491 0x7740,
394 0x005b, 492 0x005b,
395 0x8d80, 493 0x8d80,
396 0x01c9, 494 0x01c9,
397 0xc380, 495 0xc380,
398 0x0000, 496 0x0000,
399 0x0080, 497 0x0080,
400 0x0000, 498 0x0000,
401 0x0090, 499 0x0090,
402 0x0001, 500 0x0001,
403 0xd4c0, 501 0xd4c0,
404 502
405 1, 26, 503 1, 26,
406 0x6680, // P_timf_alpha=6, P_corm_alpha=6, P_corm_thres=128 default: 6,4,26 504 0x6680,
407 505
408 /* set ADC level to -16 */ 506 /* set ADC level to -16 */
409 11, 79, 507 11, 79,
410 (1 << 13) - 825 - 117, 508 (1 << 13) - 825 - 117,
411 (1 << 13) - 837 - 117, 509 (1 << 13) - 837 - 117,
412 (1 << 13) - 811 - 117, 510 (1 << 13) - 811 - 117,
413 (1 << 13) - 766 - 117, 511 (1 << 13) - 766 - 117,
414 (1 << 13) - 737 - 117, 512 (1 << 13) - 737 - 117,
415 (1 << 13) - 693 - 117, 513 (1 << 13) - 693 - 117,
416 (1 << 13) - 648 - 117, 514 (1 << 13) - 648 - 117,
417 (1 << 13) - 619 - 117, 515 (1 << 13) - 619 - 117,
418 (1 << 13) - 575 - 117, 516 (1 << 13) - 575 - 117,
419 (1 << 13) - 531 - 117, 517 (1 << 13) - 531 - 117,
420 (1 << 13) - 501 - 117, 518 (1 << 13) - 501 - 117,
421 519
422 1, 142, 520 1, 142,
423 0x0410, // P_palf_filter_on=1, P_palf_filter_freeze=0, P_palf_alpha_regul=16 521 0x0410,
424 522
425 /* disable power smoothing */ 523 /* disable power smoothing */
426 8, 145, 524 8, 145,
427 0, 525 0,
428 0, 526 0,
429 0, 527 0,
430 0, 528 0,
431 0, 529 0,
432 0, 530 0,
433 0, 531 0,
434 0, 532 0,
435 533
436 1, 154, 534 1, 154,
437 1 << 13, // P_fft_freq_dir=1, P_fft_nb_to_cut=0 535 1 << 13,
438 536
439 1, 168, 537 1, 168,
440 0x0ccd, // P_pha3_thres, default 0x3000 538 0x0ccd,
441
442// 1, 169,
443// 0x0010, // P_cti_use_cpe=0, P_cti_use_prog=0, P_cti_win_len=16, default: 0x0010
444 539
445 1, 183, 540 1, 183,
446 0x200f, // P_cspu_regul=512, P_cspu_win_cut=15, default: 0x2005 541 0x200f,
542
543 1, 212,
544 0x169,
447 545
448 5, 187, 546 5, 187,
449 0x023d, // P_adp_regul_cnt=573, default: 410 547 0x023d,
450 0x00a4, // P_adp_noise_cnt= 548 0x00a4,
451 0x00a4, // P_adp_regul_ext 549 0x00a4,
452 0x7ff0, // P_adp_noise_ext 550 0x7ff0,
453 0x3ccc, // P_adp_fil 551 0x3ccc,
454 552
455 1, 198, 553 1, 198,
456 0x800, // P_equal_thres_wgn 554 0x800,
457 555
458 1, 222, 556 1, 222,
459 0x0010, // P_fec_ber_rs_len=2 557 0x0010,
460 558
461 1, 235, 559 1, 235,
462 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard 560 0x0062,
463 561
464 2, 901, 562 2, 901,
465 0x0006, // P_clk_cfg1 563 0x0006,
466 (3 << 10) | (1 << 6), // P_divclksel=3 P_divbitsel=1 564 (3 << 10) | (1 << 6),
467 565
468 1, 905, 566 1, 905,
469 0x2c8e, // Tuner IO bank: max drive (14mA) + divout pads max drive 567 0x2c8e,
470 568
471 0, 569 0,
472}; 570};
@@ -475,51 +573,64 @@ static int dib7000p_demod_reset(struct dib7000p_state *state)
475{ 573{
476 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 574 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
477 575
576 if (state->version == SOC7090)
577 dibx000_reset_i2c_master(&state->i2c_master);
578
478 dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE); 579 dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
479 580
480 /* restart all parts */ 581 /* restart all parts */
481 dib7000p_write_word(state, 770, 0xffff); 582 dib7000p_write_word(state, 770, 0xffff);
482 dib7000p_write_word(state, 771, 0xffff); 583 dib7000p_write_word(state, 771, 0xffff);
483 dib7000p_write_word(state, 772, 0x001f); 584 dib7000p_write_word(state, 772, 0x001f);
484 dib7000p_write_word(state, 898, 0x0003); 585 dib7000p_write_word(state, 898, 0x0003);
485 /* except i2c, sdio, gpio - control interfaces */ 586 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
486 dib7000p_write_word(state, 1280, 0x01fc - ((1 << 7) | (1 << 6) | (1 << 5)) ); 587
487 588 dib7000p_write_word(state, 770, 0);
488 dib7000p_write_word(state, 770, 0); 589 dib7000p_write_word(state, 771, 0);
489 dib7000p_write_word(state, 771, 0); 590 dib7000p_write_word(state, 772, 0);
490 dib7000p_write_word(state, 772, 0); 591 dib7000p_write_word(state, 898, 0);
491 dib7000p_write_word(state, 898, 0);
492 dib7000p_write_word(state, 1280, 0); 592 dib7000p_write_word(state, 1280, 0);
493 593
494 /* default */ 594 /* default */
495 dib7000p_reset_pll(state); 595 dib7000p_reset_pll(state);
496 596
497 if (dib7000p_reset_gpio(state) != 0) 597 if (dib7000p_reset_gpio(state) != 0)
498 dprintk( "GPIO reset was not successful."); 598 dprintk("GPIO reset was not successful.");
499
500 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
501 dprintk( "OUTPUT_MODE could not be reset.");
502 599
503 /* unforce divstr regardless whether i2c enumeration was done or not */ 600 if (state->version == SOC7090) {
504 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1) ); 601 dib7000p_write_word(state, 899, 0);
505 602
506 dib7000p_set_bandwidth(state, 8000); 603 /* impulse noise */
604 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
605 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
606 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
607 dib7000p_write_word(state, 273, (1<<6) | 30);
608 }
609 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
610 dprintk("OUTPUT_MODE could not be reset.");
507 611
508 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); 612 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
509 dib7000p_sad_calib(state); 613 dib7000p_sad_calib(state);
510 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF); 614 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
511 615
512 // P_iqc_alpha_pha, P_iqc_alpha_amp_dcc_alpha, ... 616 /* unforce divstr regardless whether i2c enumeration was done or not */
513 if(state->cfg.tuner_is_baseband) 617 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
514 dib7000p_write_word(state, 36,0x0755); 618
515 else 619 dib7000p_set_bandwidth(state, 8000);
516 dib7000p_write_word(state, 36,0x1f55); 620
621 if (state->version == SOC7090) {
622 dib7000p_write_word(state, 36, 0x5755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
623 } else {
624 if (state->cfg.tuner_is_baseband)
625 dib7000p_write_word(state, 36, 0x0755);
626 else
627 dib7000p_write_word(state, 36, 0x1f55);
628 }
517 629
518 dib7000p_write_tab(state, dib7000p_defaults); 630 dib7000p_write_tab(state, dib7000p_defaults);
519 631
520 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 632 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
521 633
522
523 return 0; 634 return 0;
524} 635}
525 636
@@ -527,9 +638,9 @@ static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
527{ 638{
528 u16 tmp = 0; 639 u16 tmp = 0;
529 tmp = dib7000p_read_word(state, 903); 640 tmp = dib7000p_read_word(state, 903);
530 dib7000p_write_word(state, 903, (tmp | 0x1)); //pwr-up pll 641 dib7000p_write_word(state, 903, (tmp | 0x1));
531 tmp = dib7000p_read_word(state, 900); 642 tmp = dib7000p_read_word(state, 900);
532 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6)); //use High freq clock 643 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
533} 644}
534 645
535static void dib7000p_restart_agc(struct dib7000p_state *state) 646static void dib7000p_restart_agc(struct dib7000p_state *state)
@@ -543,11 +654,9 @@ static int dib7000p_update_lna(struct dib7000p_state *state)
543{ 654{
544 u16 dyn_gain; 655 u16 dyn_gain;
545 656
546 // when there is no LNA to program return immediatly
547 if (state->cfg.update_lna) { 657 if (state->cfg.update_lna) {
548 // read dyn_gain here (because it is demod-dependent and not fe)
549 dyn_gain = dib7000p_read_word(state, 394); 658 dyn_gain = dib7000p_read_word(state, 394);
550 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed 659 if (state->cfg.update_lna(&state->demod, dyn_gain)) {
551 dib7000p_restart_agc(state); 660 dib7000p_restart_agc(state);
552 return 1; 661 return 1;
553 } 662 }
@@ -571,24 +680,24 @@ static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
571 } 680 }
572 681
573 if (agc == NULL) { 682 if (agc == NULL) {
574 dprintk( "no valid AGC configuration found for band 0x%02x",band); 683 dprintk("no valid AGC configuration found for band 0x%02x", band);
575 return -EINVAL; 684 return -EINVAL;
576 } 685 }
577 686
578 state->current_agc = agc; 687 state->current_agc = agc;
579 688
580 /* AGC */ 689 /* AGC */
581 dib7000p_write_word(state, 75 , agc->setup ); 690 dib7000p_write_word(state, 75, agc->setup);
582 dib7000p_write_word(state, 76 , agc->inv_gain ); 691 dib7000p_write_word(state, 76, agc->inv_gain);
583 dib7000p_write_word(state, 77 , agc->time_stabiliz ); 692 dib7000p_write_word(state, 77, agc->time_stabiliz);
584 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock); 693 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
585 694
586 // Demod AGC loop configuration 695 // Demod AGC loop configuration
587 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp); 696 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
588 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp); 697 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
589 698
590 /* AGC continued */ 699 /* AGC continued */
591 dprintk( "WBD: ref: %d, sel: %d, active: %d, alpha: %d", 700 dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
592 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel); 701 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
593 702
594 if (state->wbd_ref != 0) 703 if (state->wbd_ref != 0)
@@ -598,101 +707,135 @@ static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
598 707
599 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); 708 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
600 709
601 dib7000p_write_word(state, 107, agc->agc1_max); 710 dib7000p_write_word(state, 107, agc->agc1_max);
602 dib7000p_write_word(state, 108, agc->agc1_min); 711 dib7000p_write_word(state, 108, agc->agc1_min);
603 dib7000p_write_word(state, 109, agc->agc2_max); 712 dib7000p_write_word(state, 109, agc->agc2_max);
604 dib7000p_write_word(state, 110, agc->agc2_min); 713 dib7000p_write_word(state, 110, agc->agc2_min);
605 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2); 714 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
606 dib7000p_write_word(state, 112, agc->agc1_pt3); 715 dib7000p_write_word(state, 112, agc->agc1_pt3);
607 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); 716 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
608 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); 717 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
609 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); 718 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
610 return 0; 719 return 0;
611} 720}
612 721
722static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
723{
724 u32 internal = dib7000p_get_internal_freq(state);
725 s32 unit_khz_dds_val = 67108864 / (internal); /* 2**26 / Fsampling is the unit 1KHz offset */
726 u32 abs_offset_khz = ABS(offset_khz);
727 u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
728 u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
729
730 dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d", offset_khz, internal, invert);
731
732 if (offset_khz < 0)
733 unit_khz_dds_val *= -1;
734
735 /* IF tuner */
736 if (invert)
737 dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
738 else
739 dds += (abs_offset_khz * unit_khz_dds_val);
740
741 if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
742 dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
743 dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
744 }
745}
746
613static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 747static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
614{ 748{
615 struct dib7000p_state *state = demod->demodulator_priv; 749 struct dib7000p_state *state = demod->demodulator_priv;
616 int ret = -1; 750 int ret = -1;
617 u8 *agc_state = &state->agc_state; 751 u8 *agc_state = &state->agc_state;
618 u8 agc_split; 752 u8 agc_split;
753 u16 reg;
754 u32 upd_demod_gain_period = 0x1000;
619 755
620 switch (state->agc_state) { 756 switch (state->agc_state) {
621 case 0: 757 case 0:
622 // set power-up level: interf+analog+AGC 758 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
623 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 759 if (state->version == SOC7090) {
760 reg = dib7000p_read_word(state, 0x79b) & 0xff00;
761 dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */
762 dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
763
764 /* enable adc i & q */
765 reg = dib7000p_read_word(state, 0x780);
766 dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
767 } else {
624 dib7000p_set_adc_state(state, DIBX000_ADC_ON); 768 dib7000p_set_adc_state(state, DIBX000_ADC_ON);
625 dib7000p_pll_clk_cfg(state); 769 dib7000p_pll_clk_cfg(state);
770 }
626 771
627 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0) 772 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
628 return -1; 773 return -1;
629
630 ret = 7;
631 (*agc_state)++;
632 break;
633 774
634 case 1: 775 dib7000p_set_dds(state, 0);
635 // AGC initialization 776 ret = 7;
636 if (state->cfg.agc_control) 777 (*agc_state)++;
637 state->cfg.agc_control(&state->demod, 1); 778 break;
638
639 dib7000p_write_word(state, 78, 32768);
640 if (!state->current_agc->perform_agc_softsplit) {
641 /* we are using the wbd - so slow AGC startup */
642 /* force 0 split on WBD and restart AGC */
643 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
644 (*agc_state)++;
645 ret = 5;
646 } else {
647 /* default AGC startup */
648 (*agc_state) = 4;
649 /* wait AGC rough lock time */
650 ret = 7;
651 }
652 779
653 dib7000p_restart_agc(state); 780 case 1:
654 break; 781 if (state->cfg.agc_control)
782 state->cfg.agc_control(&state->demod, 1);
655 783
656 case 2: /* fast split search path after 5sec */ 784 dib7000p_write_word(state, 78, 32768);
657 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */ 785 if (!state->current_agc->perform_agc_softsplit) {
658 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */ 786 /* we are using the wbd - so slow AGC startup */
787 /* force 0 split on WBD and restart AGC */
788 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
659 (*agc_state)++; 789 (*agc_state)++;
660 ret = 14; 790 ret = 5;
661 break; 791 } else {
792 /* default AGC startup */
793 (*agc_state) = 4;
794 /* wait AGC rough lock time */
795 ret = 7;
796 }
662 797
663 case 3: /* split search ended */ 798 dib7000p_restart_agc(state);
664 agc_split = (u8)dib7000p_read_word(state, 396); /* store the split value for the next time */ 799 break;
665 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
666 800
667 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */ 801 case 2: /* fast split search path after 5sec */
668 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */ 802 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
803 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
804 (*agc_state)++;
805 ret = 14;
806 break;
669 807
670 dib7000p_restart_agc(state); 808 case 3: /* split search ended */
809 agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */
810 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
671 811
672 dprintk( "SPLIT %p: %hd", demod, agc_split); 812 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
813 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
673 814
674 (*agc_state)++; 815 dib7000p_restart_agc(state);
675 ret = 5;
676 break;
677 816
678 case 4: /* LNA startup */ 817 dprintk("SPLIT %p: %hd", demod, agc_split);
679 // wait AGC accurate lock time
680 ret = 7;
681 818
682 if (dib7000p_update_lna(state)) 819 (*agc_state)++;
683 // wait only AGC rough lock time 820 ret = 5;
684 ret = 5; 821 break;
685 else // nothing was done, go to the next state
686 (*agc_state)++;
687 break;
688 822
689 case 5: 823 case 4: /* LNA startup */
690 if (state->cfg.agc_control) 824 ret = 7;
691 state->cfg.agc_control(&state->demod, 0); 825
826 if (dib7000p_update_lna(state))
827 ret = 5;
828 else
692 (*agc_state)++; 829 (*agc_state)++;
693 break; 830 break;
694 default: 831
695 break; 832 case 5:
833 if (state->cfg.agc_control)
834 state->cfg.agc_control(&state->demod, 0);
835 (*agc_state)++;
836 break;
837 default:
838 break;
696 } 839 }
697 return ret; 840 return ret;
698} 841}
@@ -703,45 +846,89 @@ static void dib7000p_update_timf(struct dib7000p_state *state)
703 state->timf = timf * 160 / (state->current_bandwidth / 50); 846 state->timf = timf * 160 / (state->current_bandwidth / 50);
704 dib7000p_write_word(state, 23, (u16) (timf >> 16)); 847 dib7000p_write_word(state, 23, (u16) (timf >> 16));
705 dib7000p_write_word(state, 24, (u16) (timf & 0xffff)); 848 dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
706 dprintk( "updated timf_frequency: %d (default: %d)",state->timf, state->cfg.bw->timf); 849 dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf);
850
851}
707 852
853u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
854{
855 struct dib7000p_state *state = fe->demodulator_priv;
856 switch (op) {
857 case DEMOD_TIMF_SET:
858 state->timf = timf;
859 break;
860 case DEMOD_TIMF_UPDATE:
861 dib7000p_update_timf(state);
862 break;
863 case DEMOD_TIMF_GET:
864 break;
865 }
866 dib7000p_set_bandwidth(state, state->current_bandwidth);
867 return state->timf;
708} 868}
869EXPORT_SYMBOL(dib7000p_ctrl_timf);
709 870
710static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq) 871static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq)
711{ 872{
712 u16 value, est[4]; 873 u16 value, est[4];
713 874
714 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 875 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
715 876
716 /* nfft, guard, qam, alpha */ 877 /* nfft, guard, qam, alpha */
717 value = 0; 878 value = 0;
718 switch (ch->u.ofdm.transmission_mode) { 879 switch (ch->u.ofdm.transmission_mode) {
719 case TRANSMISSION_MODE_2K: value |= (0 << 7); break; 880 case TRANSMISSION_MODE_2K:
720 case TRANSMISSION_MODE_4K: value |= (2 << 7); break; 881 value |= (0 << 7);
721 default: 882 break;
722 case TRANSMISSION_MODE_8K: value |= (1 << 7); break; 883 case TRANSMISSION_MODE_4K:
884 value |= (2 << 7);
885 break;
886 default:
887 case TRANSMISSION_MODE_8K:
888 value |= (1 << 7);
889 break;
723 } 890 }
724 switch (ch->u.ofdm.guard_interval) { 891 switch (ch->u.ofdm.guard_interval) {
725 case GUARD_INTERVAL_1_32: value |= (0 << 5); break; 892 case GUARD_INTERVAL_1_32:
726 case GUARD_INTERVAL_1_16: value |= (1 << 5); break; 893 value |= (0 << 5);
727 case GUARD_INTERVAL_1_4: value |= (3 << 5); break; 894 break;
728 default: 895 case GUARD_INTERVAL_1_16:
729 case GUARD_INTERVAL_1_8: value |= (2 << 5); break; 896 value |= (1 << 5);
897 break;
898 case GUARD_INTERVAL_1_4:
899 value |= (3 << 5);
900 break;
901 default:
902 case GUARD_INTERVAL_1_8:
903 value |= (2 << 5);
904 break;
730 } 905 }
731 switch (ch->u.ofdm.constellation) { 906 switch (ch->u.ofdm.constellation) {
732 case QPSK: value |= (0 << 3); break; 907 case QPSK:
733 case QAM_16: value |= (1 << 3); break; 908 value |= (0 << 3);
734 default: 909 break;
735 case QAM_64: value |= (2 << 3); break; 910 case QAM_16:
911 value |= (1 << 3);
912 break;
913 default:
914 case QAM_64:
915 value |= (2 << 3);
916 break;
736 } 917 }
737 switch (HIERARCHY_1) { 918 switch (HIERARCHY_1) {
738 case HIERARCHY_2: value |= 2; break; 919 case HIERARCHY_2:
739 case HIERARCHY_4: value |= 4; break; 920 value |= 2;
740 default: 921 break;
741 case HIERARCHY_1: value |= 1; break; 922 case HIERARCHY_4:
923 value |= 4;
924 break;
925 default:
926 case HIERARCHY_1:
927 value |= 1;
928 break;
742 } 929 }
743 dib7000p_write_word(state, 0, value); 930 dib7000p_write_word(state, 0, value);
744 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */ 931 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
745 932
746 /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */ 933 /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
747 value = 0; 934 value = 0;
@@ -752,39 +939,63 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
752 if (1 == 1) 939 if (1 == 1)
753 value |= 1; 940 value |= 1;
754 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) { 941 switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
755 case FEC_2_3: value |= (2 << 1); break; 942 case FEC_2_3:
756 case FEC_3_4: value |= (3 << 1); break; 943 value |= (2 << 1);
757 case FEC_5_6: value |= (5 << 1); break; 944 break;
758 case FEC_7_8: value |= (7 << 1); break; 945 case FEC_3_4:
759 default: 946 value |= (3 << 1);
760 case FEC_1_2: value |= (1 << 1); break; 947 break;
948 case FEC_5_6:
949 value |= (5 << 1);
950 break;
951 case FEC_7_8:
952 value |= (7 << 1);
953 break;
954 default:
955 case FEC_1_2:
956 value |= (1 << 1);
957 break;
761 } 958 }
762 dib7000p_write_word(state, 208, value); 959 dib7000p_write_word(state, 208, value);
763 960
764 /* offset loop parameters */ 961 /* offset loop parameters */
765 dib7000p_write_word(state, 26, 0x6680); // timf(6xxx) 962 dib7000p_write_word(state, 26, 0x6680);
766 dib7000p_write_word(state, 32, 0x0003); // pha_off_max(xxx3) 963 dib7000p_write_word(state, 32, 0x0003);
767 dib7000p_write_word(state, 29, 0x1273); // isi 964 dib7000p_write_word(state, 29, 0x1273);
768 dib7000p_write_word(state, 33, 0x0005); // sfreq(xxx5) 965 dib7000p_write_word(state, 33, 0x0005);
769 966
770 /* P_dvsy_sync_wait */ 967 /* P_dvsy_sync_wait */
771 switch (ch->u.ofdm.transmission_mode) { 968 switch (ch->u.ofdm.transmission_mode) {
772 case TRANSMISSION_MODE_8K: value = 256; break; 969 case TRANSMISSION_MODE_8K:
773 case TRANSMISSION_MODE_4K: value = 128; break; 970 value = 256;
774 case TRANSMISSION_MODE_2K: 971 break;
775 default: value = 64; break; 972 case TRANSMISSION_MODE_4K:
973 value = 128;
974 break;
975 case TRANSMISSION_MODE_2K:
976 default:
977 value = 64;
978 break;
776 } 979 }
777 switch (ch->u.ofdm.guard_interval) { 980 switch (ch->u.ofdm.guard_interval) {
778 case GUARD_INTERVAL_1_16: value *= 2; break; 981 case GUARD_INTERVAL_1_16:
779 case GUARD_INTERVAL_1_8: value *= 4; break; 982 value *= 2;
780 case GUARD_INTERVAL_1_4: value *= 8; break; 983 break;
781 default: 984 case GUARD_INTERVAL_1_8:
782 case GUARD_INTERVAL_1_32: value *= 1; break; 985 value *= 4;
986 break;
987 case GUARD_INTERVAL_1_4:
988 value *= 8;
989 break;
990 default:
991 case GUARD_INTERVAL_1_32:
992 value *= 1;
993 break;
783 } 994 }
784 if (state->cfg.diversity_delay == 0) 995 if (state->cfg.diversity_delay == 0)
785 state->div_sync_wait = (value * 3) / 2 + 48; // add 50% SFN margin + compensate for one DVSY-fifo 996 state->div_sync_wait = (value * 3) / 2 + 48;
786 else 997 else
787 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay; // add 50% SFN margin + compensate for one DVSY-fifo 998 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
788 999
789 /* deactive the possibility of diversity reception if extended interleaver */ 1000 /* deactive the possibility of diversity reception if extended interleaver */
790 state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K; 1001 state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K;
@@ -792,24 +1003,24 @@ static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_fronte
792 1003
793 /* channel estimation fine configuration */ 1004 /* channel estimation fine configuration */
794 switch (ch->u.ofdm.constellation) { 1005 switch (ch->u.ofdm.constellation) {
795 case QAM_64: 1006 case QAM_64:
796 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ 1007 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
797 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ 1008 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
798 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 1009 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
799 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ 1010 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
800 break; 1011 break;
801 case QAM_16: 1012 case QAM_16:
802 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */ 1013 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
803 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ 1014 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
804 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ 1015 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
805 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */ 1016 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
806 break; 1017 break;
807 default: 1018 default:
808 est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */ 1019 est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
809 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */ 1020 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
810 est[2] = 0x0333; /* P_adp_regul_ext 0.1 */ 1021 est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
811 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */ 1022 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
812 break; 1023 break;
813 } 1024 }
814 for (value = 0; value < 4; value++) 1025 for (value = 0; value < 4; value++)
815 dib7000p_write_word(state, 187 + value, est[value]); 1026 dib7000p_write_word(state, 187 + value, est[value]);
@@ -820,14 +1031,15 @@ static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_fron
820 struct dib7000p_state *state = demod->demodulator_priv; 1031 struct dib7000p_state *state = demod->demodulator_priv;
821 struct dvb_frontend_parameters schan; 1032 struct dvb_frontend_parameters schan;
822 u32 value, factor; 1033 u32 value, factor;
1034 u32 internal = dib7000p_get_internal_freq(state);
823 1035
824 schan = *ch; 1036 schan = *ch;
825 schan.u.ofdm.constellation = QAM_64; 1037 schan.u.ofdm.constellation = QAM_64;
826 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32; 1038 schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
827 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; 1039 schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
828 schan.u.ofdm.code_rate_HP = FEC_2_3; 1040 schan.u.ofdm.code_rate_HP = FEC_2_3;
829 schan.u.ofdm.code_rate_LP = FEC_3_4; 1041 schan.u.ofdm.code_rate_LP = FEC_3_4;
830 schan.u.ofdm.hierarchy_information = 0; 1042 schan.u.ofdm.hierarchy_information = 0;
831 1043
832 dib7000p_set_channel(state, &schan, 7); 1044 dib7000p_set_channel(state, &schan, 7);
833 1045
@@ -837,16 +1049,15 @@ static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_fron
837 else 1049 else
838 factor = 6; 1050 factor = 6;
839 1051
840 // always use the setting for 8MHz here lock_time for 7,6 MHz are longer 1052 value = 30 * internal * factor;
841 value = 30 * state->cfg.bw->internal * factor; 1053 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
842 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time 1054 dib7000p_write_word(state, 7, (u16) (value & 0xffff));
843 dib7000p_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time 1055 value = 100 * internal * factor;
844 value = 100 * state->cfg.bw->internal * factor; 1056 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
845 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time 1057 dib7000p_write_word(state, 9, (u16) (value & 0xffff));
846 dib7000p_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time 1058 value = 500 * internal * factor;
847 value = 500 * state->cfg.bw->internal * factor; 1059 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
848 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time 1060 dib7000p_write_word(state, 11, (u16) (value & 0xffff));
849 dib7000p_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
850 1061
851 value = dib7000p_read_word(state, 0); 1062 value = dib7000p_read_word(state, 0);
852 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value)); 1063 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
@@ -861,101 +1072,101 @@ static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
861 struct dib7000p_state *state = demod->demodulator_priv; 1072 struct dib7000p_state *state = demod->demodulator_priv;
862 u16 irq_pending = dib7000p_read_word(state, 1284); 1073 u16 irq_pending = dib7000p_read_word(state, 1284);
863 1074
864 if (irq_pending & 0x1) // failed 1075 if (irq_pending & 0x1)
865 return 1; 1076 return 1;
866 1077
867 if (irq_pending & 0x2) // succeeded 1078 if (irq_pending & 0x2)
868 return 2; 1079 return 2;
869 1080
870 return 0; // still pending 1081 return 0;
871} 1082}
872 1083
873static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw) 1084static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
874{ 1085{
875 static s16 notch[]={16143, 14402, 12238, 9713, 6902, 3888, 759, -2392}; 1086 static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
876 static u8 sine [] ={0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22, 1087 static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
877 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51, 1088 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
878 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80, 1089 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
879 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105, 1090 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
880 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126, 1091 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
881 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146, 1092 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
882 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165, 1093 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
883 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182, 1094 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
884 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 1095 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
885 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212, 1096 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
886 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224, 1097 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
887 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235, 1098 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
888 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243, 1099 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
889 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249, 1100 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
890 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254, 1101 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
891 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1102 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
892 255, 255, 255, 255, 255, 255}; 1103 255, 255, 255, 255, 255, 255
1104 };
893 1105
894 u32 xtal = state->cfg.bw->xtal_hz / 1000; 1106 u32 xtal = state->cfg.bw->xtal_hz / 1000;
895 int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz; 1107 int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
896 int k; 1108 int k;
897 int coef_re[8],coef_im[8]; 1109 int coef_re[8], coef_im[8];
898 int bw_khz = bw; 1110 int bw_khz = bw;
899 u32 pha; 1111 u32 pha;
900 1112
901 dprintk( "relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal); 1113 dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
902
903 1114
904 if (f_rel < -bw_khz/2 || f_rel > bw_khz/2) 1115 if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
905 return; 1116 return;
906 1117
907 bw_khz /= 100; 1118 bw_khz /= 100;
908 1119
909 dib7000p_write_word(state, 142 ,0x0610); 1120 dib7000p_write_word(state, 142, 0x0610);
910 1121
911 for (k = 0; k < 8; k++) { 1122 for (k = 0; k < 8; k++) {
912 pha = ((f_rel * (k+1) * 112 * 80/bw_khz) /1000) & 0x3ff; 1123 pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
913 1124
914 if (pha==0) { 1125 if (pha == 0) {
915 coef_re[k] = 256; 1126 coef_re[k] = 256;
916 coef_im[k] = 0; 1127 coef_im[k] = 0;
917 } else if(pha < 256) { 1128 } else if (pha < 256) {
918 coef_re[k] = sine[256-(pha&0xff)]; 1129 coef_re[k] = sine[256 - (pha & 0xff)];
919 coef_im[k] = sine[pha&0xff]; 1130 coef_im[k] = sine[pha & 0xff];
920 } else if (pha == 256) { 1131 } else if (pha == 256) {
921 coef_re[k] = 0; 1132 coef_re[k] = 0;
922 coef_im[k] = 256; 1133 coef_im[k] = 256;
923 } else if (pha < 512) { 1134 } else if (pha < 512) {
924 coef_re[k] = -sine[pha&0xff]; 1135 coef_re[k] = -sine[pha & 0xff];
925 coef_im[k] = sine[256 - (pha&0xff)]; 1136 coef_im[k] = sine[256 - (pha & 0xff)];
926 } else if (pha == 512) { 1137 } else if (pha == 512) {
927 coef_re[k] = -256; 1138 coef_re[k] = -256;
928 coef_im[k] = 0; 1139 coef_im[k] = 0;
929 } else if (pha < 768) { 1140 } else if (pha < 768) {
930 coef_re[k] = -sine[256-(pha&0xff)]; 1141 coef_re[k] = -sine[256 - (pha & 0xff)];
931 coef_im[k] = -sine[pha&0xff]; 1142 coef_im[k] = -sine[pha & 0xff];
932 } else if (pha == 768) { 1143 } else if (pha == 768) {
933 coef_re[k] = 0; 1144 coef_re[k] = 0;
934 coef_im[k] = -256; 1145 coef_im[k] = -256;
935 } else { 1146 } else {
936 coef_re[k] = sine[pha&0xff]; 1147 coef_re[k] = sine[pha & 0xff];
937 coef_im[k] = -sine[256 - (pha&0xff)]; 1148 coef_im[k] = -sine[256 - (pha & 0xff)];
938 } 1149 }
939 1150
940 coef_re[k] *= notch[k]; 1151 coef_re[k] *= notch[k];
941 coef_re[k] += (1<<14); 1152 coef_re[k] += (1 << 14);
942 if (coef_re[k] >= (1<<24)) 1153 if (coef_re[k] >= (1 << 24))
943 coef_re[k] = (1<<24) - 1; 1154 coef_re[k] = (1 << 24) - 1;
944 coef_re[k] /= (1<<15); 1155 coef_re[k] /= (1 << 15);
945 1156
946 coef_im[k] *= notch[k]; 1157 coef_im[k] *= notch[k];
947 coef_im[k] += (1<<14); 1158 coef_im[k] += (1 << 14);
948 if (coef_im[k] >= (1<<24)) 1159 if (coef_im[k] >= (1 << 24))
949 coef_im[k] = (1<<24)-1; 1160 coef_im[k] = (1 << 24) - 1;
950 coef_im[k] /= (1<<15); 1161 coef_im[k] /= (1 << 15);
951 1162
952 dprintk( "PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]); 1163 dprintk("PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
953 1164
954 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); 1165 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
955 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff); 1166 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
956 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); 1167 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
957 } 1168 }
958 dib7000p_write_word(state,143 ,0); 1169 dib7000p_write_word(state, 143, 0);
959} 1170}
960 1171
961static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch) 1172static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
@@ -976,11 +1187,11 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
976 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */ 1187 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
977 tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3); 1188 tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
978 if (state->sfn_workaround_active) { 1189 if (state->sfn_workaround_active) {
979 dprintk( "SFN workaround is active"); 1190 dprintk("SFN workaround is active");
980 tmp |= (1 << 9); 1191 tmp |= (1 << 9);
981 dib7000p_write_word(state, 166, 0x4000); // P_pha3_force_pha_shift 1192 dib7000p_write_word(state, 166, 0x4000);
982 } else { 1193 } else {
983 dib7000p_write_word(state, 166, 0x0000); // P_pha3_force_pha_shift 1194 dib7000p_write_word(state, 166, 0x0000);
984 } 1195 }
985 dib7000p_write_word(state, 29, tmp); 1196 dib7000p_write_word(state, 29, tmp);
986 1197
@@ -993,51 +1204,72 @@ static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_paramet
993 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ 1204 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
994 tmp = (6 << 8) | 0x80; 1205 tmp = (6 << 8) | 0x80;
995 switch (ch->u.ofdm.transmission_mode) { 1206 switch (ch->u.ofdm.transmission_mode) {
996 case TRANSMISSION_MODE_2K: tmp |= (7 << 12); break; 1207 case TRANSMISSION_MODE_2K:
997 case TRANSMISSION_MODE_4K: tmp |= (8 << 12); break; 1208 tmp |= (2 << 12);
998 default: 1209 break;
999 case TRANSMISSION_MODE_8K: tmp |= (9 << 12); break; 1210 case TRANSMISSION_MODE_4K:
1211 tmp |= (3 << 12);
1212 break;
1213 default:
1214 case TRANSMISSION_MODE_8K:
1215 tmp |= (4 << 12);
1216 break;
1000 } 1217 }
1001 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */ 1218 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
1002 1219
1003 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ 1220 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
1004 tmp = (0 << 4); 1221 tmp = (0 << 4);
1005 switch (ch->u.ofdm.transmission_mode) { 1222 switch (ch->u.ofdm.transmission_mode) {
1006 case TRANSMISSION_MODE_2K: tmp |= 0x6; break; 1223 case TRANSMISSION_MODE_2K:
1007 case TRANSMISSION_MODE_4K: tmp |= 0x7; break; 1224 tmp |= 0x6;
1008 default: 1225 break;
1009 case TRANSMISSION_MODE_8K: tmp |= 0x8; break; 1226 case TRANSMISSION_MODE_4K:
1227 tmp |= 0x7;
1228 break;
1229 default:
1230 case TRANSMISSION_MODE_8K:
1231 tmp |= 0x8;
1232 break;
1010 } 1233 }
1011 dib7000p_write_word(state, 32, tmp); 1234 dib7000p_write_word(state, 32, tmp);
1012 1235
1013 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ 1236 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
1014 tmp = (0 << 4); 1237 tmp = (0 << 4);
1015 switch (ch->u.ofdm.transmission_mode) { 1238 switch (ch->u.ofdm.transmission_mode) {
1016 case TRANSMISSION_MODE_2K: tmp |= 0x6; break; 1239 case TRANSMISSION_MODE_2K:
1017 case TRANSMISSION_MODE_4K: tmp |= 0x7; break; 1240 tmp |= 0x6;
1018 default: 1241 break;
1019 case TRANSMISSION_MODE_8K: tmp |= 0x8; break; 1242 case TRANSMISSION_MODE_4K:
1243 tmp |= 0x7;
1244 break;
1245 default:
1246 case TRANSMISSION_MODE_8K:
1247 tmp |= 0x8;
1248 break;
1020 } 1249 }
1021 dib7000p_write_word(state, 33, tmp); 1250 dib7000p_write_word(state, 33, tmp);
1022 1251
1023 tmp = dib7000p_read_word(state,509); 1252 tmp = dib7000p_read_word(state, 509);
1024 if (!((tmp >> 6) & 0x1)) { 1253 if (!((tmp >> 6) & 0x1)) {
1025 /* restart the fec */ 1254 /* restart the fec */
1026 tmp = dib7000p_read_word(state,771); 1255 tmp = dib7000p_read_word(state, 771);
1027 dib7000p_write_word(state, 771, tmp | (1 << 1)); 1256 dib7000p_write_word(state, 771, tmp | (1 << 1));
1028 dib7000p_write_word(state, 771, tmp); 1257 dib7000p_write_word(state, 771, tmp);
1029 msleep(10); 1258 msleep(40);
1030 tmp = dib7000p_read_word(state,509); 1259 tmp = dib7000p_read_word(state, 509);
1031 } 1260 }
1032
1033 // we achieved a lock - it's time to update the osc freq 1261 // we achieved a lock - it's time to update the osc freq
1034 if ((tmp >> 6) & 0x1) 1262 if ((tmp >> 6) & 0x1) {
1035 dib7000p_update_timf(state); 1263 dib7000p_update_timf(state);
1264 /* P_timf_alpha += 2 */
1265 tmp = dib7000p_read_word(state, 26);
1266 dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
1267 }
1036 1268
1037 if (state->cfg.spur_protect) 1269 if (state->cfg.spur_protect)
1038 dib7000p_spur_protect(state, ch->frequency/1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1270 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
1039 1271
1040 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)); 1272 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
1041 return 0; 1273 return 0;
1042} 1274}
1043 1275
@@ -1046,63 +1278,82 @@ static int dib7000p_wakeup(struct dvb_frontend *demod)
1046 struct dib7000p_state *state = demod->demodulator_priv; 1278 struct dib7000p_state *state = demod->demodulator_priv;
1047 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL); 1279 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
1048 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON); 1280 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1281 if (state->version == SOC7090)
1282 dib7000p_sad_calib(state);
1049 return 0; 1283 return 0;
1050} 1284}
1051 1285
1052static int dib7000p_sleep(struct dvb_frontend *demod) 1286static int dib7000p_sleep(struct dvb_frontend *demod)
1053{ 1287{
1054 struct dib7000p_state *state = demod->demodulator_priv; 1288 struct dib7000p_state *state = demod->demodulator_priv;
1289 if (state->version == SOC7090)
1290 return dib7090_set_output_mode(demod, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1055 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY); 1291 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1056} 1292}
1057 1293
1058static int dib7000p_identify(struct dib7000p_state *st) 1294static int dib7000p_identify(struct dib7000p_state *st)
1059{ 1295{
1060 u16 value; 1296 u16 value;
1061 dprintk( "checking demod on I2C address: %d (%x)", 1297 dprintk("checking demod on I2C address: %d (%x)", st->i2c_addr, st->i2c_addr);
1062 st->i2c_addr, st->i2c_addr);
1063 1298
1064 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) { 1299 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
1065 dprintk( "wrong Vendor ID (read=0x%x)",value); 1300 dprintk("wrong Vendor ID (read=0x%x)", value);
1066 return -EREMOTEIO; 1301 return -EREMOTEIO;
1067 } 1302 }
1068 1303
1069 if ((value = dib7000p_read_word(st, 769)) != 0x4000) { 1304 if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
1070 dprintk( "wrong Device ID (%x)",value); 1305 dprintk("wrong Device ID (%x)", value);
1071 return -EREMOTEIO; 1306 return -EREMOTEIO;
1072 } 1307 }
1073 1308
1074 return 0; 1309 return 0;
1075} 1310}
1076 1311
1077 1312static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1078static int dib7000p_get_frontend(struct dvb_frontend* fe,
1079 struct dvb_frontend_parameters *fep)
1080{ 1313{
1081 struct dib7000p_state *state = fe->demodulator_priv; 1314 struct dib7000p_state *state = fe->demodulator_priv;
1082 u16 tps = dib7000p_read_word(state,463); 1315 u16 tps = dib7000p_read_word(state, 463);
1083 1316
1084 fep->inversion = INVERSION_AUTO; 1317 fep->inversion = INVERSION_AUTO;
1085 1318
1086 fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth); 1319 fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth);
1087 1320
1088 switch ((tps >> 8) & 0x3) { 1321 switch ((tps >> 8) & 0x3) {
1089 case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break; 1322 case 0:
1090 case 1: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K; break; 1323 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1091 /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */ 1324 break;
1325 case 1:
1326 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1327 break;
1328 /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */
1092 } 1329 }
1093 1330
1094 switch (tps & 0x3) { 1331 switch (tps & 0x3) {
1095 case 0: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32; break; 1332 case 0:
1096 case 1: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16; break; 1333 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1097 case 2: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8; break; 1334 break;
1098 case 3: fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4; break; 1335 case 1:
1336 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1337 break;
1338 case 2:
1339 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1340 break;
1341 case 3:
1342 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1343 break;
1099 } 1344 }
1100 1345
1101 switch ((tps >> 14) & 0x3) { 1346 switch ((tps >> 14) & 0x3) {
1102 case 0: fep->u.ofdm.constellation = QPSK; break; 1347 case 0:
1103 case 1: fep->u.ofdm.constellation = QAM_16; break; 1348 fep->u.ofdm.constellation = QPSK;
1104 case 2: 1349 break;
1105 default: fep->u.ofdm.constellation = QAM_64; break; 1350 case 1:
1351 fep->u.ofdm.constellation = QAM_16;
1352 break;
1353 case 2:
1354 default:
1355 fep->u.ofdm.constellation = QAM_64;
1356 break;
1106 } 1357 }
1107 1358
1108 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */ 1359 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
@@ -1110,22 +1361,42 @@ static int dib7000p_get_frontend(struct dvb_frontend* fe,
1110 1361
1111 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE; 1362 fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1112 switch ((tps >> 5) & 0x7) { 1363 switch ((tps >> 5) & 0x7) {
1113 case 1: fep->u.ofdm.code_rate_HP = FEC_1_2; break; 1364 case 1:
1114 case 2: fep->u.ofdm.code_rate_HP = FEC_2_3; break; 1365 fep->u.ofdm.code_rate_HP = FEC_1_2;
1115 case 3: fep->u.ofdm.code_rate_HP = FEC_3_4; break; 1366 break;
1116 case 5: fep->u.ofdm.code_rate_HP = FEC_5_6; break; 1367 case 2:
1117 case 7: 1368 fep->u.ofdm.code_rate_HP = FEC_2_3;
1118 default: fep->u.ofdm.code_rate_HP = FEC_7_8; break; 1369 break;
1370 case 3:
1371 fep->u.ofdm.code_rate_HP = FEC_3_4;
1372 break;
1373 case 5:
1374 fep->u.ofdm.code_rate_HP = FEC_5_6;
1375 break;
1376 case 7:
1377 default:
1378 fep->u.ofdm.code_rate_HP = FEC_7_8;
1379 break;
1119 1380
1120 } 1381 }
1121 1382
1122 switch ((tps >> 2) & 0x7) { 1383 switch ((tps >> 2) & 0x7) {
1123 case 1: fep->u.ofdm.code_rate_LP = FEC_1_2; break; 1384 case 1:
1124 case 2: fep->u.ofdm.code_rate_LP = FEC_2_3; break; 1385 fep->u.ofdm.code_rate_LP = FEC_1_2;
1125 case 3: fep->u.ofdm.code_rate_LP = FEC_3_4; break; 1386 break;
1126 case 5: fep->u.ofdm.code_rate_LP = FEC_5_6; break; 1387 case 2:
1127 case 7: 1388 fep->u.ofdm.code_rate_LP = FEC_2_3;
1128 default: fep->u.ofdm.code_rate_LP = FEC_7_8; break; 1389 break;
1390 case 3:
1391 fep->u.ofdm.code_rate_LP = FEC_3_4;
1392 break;
1393 case 5:
1394 fep->u.ofdm.code_rate_LP = FEC_5_6;
1395 break;
1396 case 7:
1397 default:
1398 fep->u.ofdm.code_rate_LP = FEC_7_8;
1399 break;
1129 } 1400 }
1130 1401
1131 /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */ 1402 /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */
@@ -1133,15 +1404,18 @@ static int dib7000p_get_frontend(struct dvb_frontend* fe,
1133 return 0; 1404 return 0;
1134} 1405}
1135 1406
1136static int dib7000p_set_frontend(struct dvb_frontend* fe, 1407static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1137 struct dvb_frontend_parameters *fep)
1138{ 1408{
1139 struct dib7000p_state *state = fe->demodulator_priv; 1409 struct dib7000p_state *state = fe->demodulator_priv;
1140 int time, ret; 1410 int time, ret;
1141 1411
1142 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z); 1412 if (state->version == SOC7090) {
1413 dib7090_set_diversity_in(fe, 0);
1414 dib7090_set_output_mode(fe, OUTMODE_HIGH_Z);
1415 } else
1416 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
1143 1417
1144 /* maybe the parameter has been changed */ 1418 /* maybe the parameter has been changed */
1145 state->sfn_workaround_active = buggy_sfn_workaround; 1419 state->sfn_workaround_active = buggy_sfn_workaround;
1146 1420
1147 if (fe->ops.tuner_ops.set_params) 1421 if (fe->ops.tuner_ops.set_params)
@@ -1156,9 +1430,7 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
1156 } while (time != -1); 1430 } while (time != -1);
1157 1431
1158 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO || 1432 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
1159 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || 1433 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1160 fep->u.ofdm.constellation == QAM_AUTO ||
1161 fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1162 int i = 800, found; 1434 int i = 800, found;
1163 1435
1164 dib7000p_autosearch_start(fe, fep); 1436 dib7000p_autosearch_start(fe, fep);
@@ -1167,9 +1439,9 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
1167 found = dib7000p_autosearch_is_irq(fe); 1439 found = dib7000p_autosearch_is_irq(fe);
1168 } while (found == 0 && i--); 1440 } while (found == 0 && i--);
1169 1441
1170 dprintk("autosearch returns: %d",found); 1442 dprintk("autosearch returns: %d", found);
1171 if (found == 0 || found == 1) 1443 if (found == 0 || found == 1)
1172 return 0; // no channel found 1444 return 0;
1173 1445
1174 dib7000p_get_frontend(fe, fep); 1446 dib7000p_get_frontend(fe, fep);
1175 } 1447 }
@@ -1177,11 +1449,15 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
1177 ret = dib7000p_tune(fe, fep); 1449 ret = dib7000p_tune(fe, fep);
1178 1450
1179 /* make this a config parameter */ 1451 /* make this a config parameter */
1180 dib7000p_set_output_mode(state, state->cfg.output_mode); 1452 if (state->version == SOC7090)
1181 return ret; 1453 dib7090_set_output_mode(fe, state->cfg.output_mode);
1454 else
1455 dib7000p_set_output_mode(state, state->cfg.output_mode);
1456
1457 return ret;
1182} 1458}
1183 1459
1184static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat) 1460static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t * stat)
1185{ 1461{
1186 struct dib7000p_state *state = fe->demodulator_priv; 1462 struct dib7000p_state *state = fe->demodulator_priv;
1187 u16 lock = dib7000p_read_word(state, 509); 1463 u16 lock = dib7000p_read_word(state, 509);
@@ -1196,27 +1472,27 @@ static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
1196 *stat |= FE_HAS_VITERBI; 1472 *stat |= FE_HAS_VITERBI;
1197 if (lock & 0x0010) 1473 if (lock & 0x0010)
1198 *stat |= FE_HAS_SYNC; 1474 *stat |= FE_HAS_SYNC;
1199 if ((lock & 0x0038) == 0x38) 1475 if ((lock & 0x0038) == 0x38)
1200 *stat |= FE_HAS_LOCK; 1476 *stat |= FE_HAS_LOCK;
1201 1477
1202 return 0; 1478 return 0;
1203} 1479}
1204 1480
1205static int dib7000p_read_ber(struct dvb_frontend *fe, u32 *ber) 1481static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
1206{ 1482{
1207 struct dib7000p_state *state = fe->demodulator_priv; 1483 struct dib7000p_state *state = fe->demodulator_priv;
1208 *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501); 1484 *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
1209 return 0; 1485 return 0;
1210} 1486}
1211 1487
1212static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 *unc) 1488static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
1213{ 1489{
1214 struct dib7000p_state *state = fe->demodulator_priv; 1490 struct dib7000p_state *state = fe->demodulator_priv;
1215 *unc = dib7000p_read_word(state, 506); 1491 *unc = dib7000p_read_word(state, 506);
1216 return 0; 1492 return 0;
1217} 1493}
1218 1494
1219static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 *strength) 1495static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
1220{ 1496{
1221 struct dib7000p_state *state = fe->demodulator_priv; 1497 struct dib7000p_state *state = fe->demodulator_priv;
1222 u16 val = dib7000p_read_word(state, 394); 1498 u16 val = dib7000p_read_word(state, 394);
@@ -1224,7 +1500,7 @@ static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
1224 return 0; 1500 return 0;
1225} 1501}
1226 1502
1227static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr) 1503static int dib7000p_read_snr(struct dvb_frontend *fe, u16 * snr)
1228{ 1504{
1229 struct dib7000p_state *state = fe->demodulator_priv; 1505 struct dib7000p_state *state = fe->demodulator_priv;
1230 u16 val; 1506 u16 val;
@@ -1240,19 +1516,17 @@ static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr)
1240 noise_exp -= 0x40; 1516 noise_exp -= 0x40;
1241 1517
1242 signal_mant = (val >> 6) & 0xFF; 1518 signal_mant = (val >> 6) & 0xFF;
1243 signal_exp = (val & 0x3F); 1519 signal_exp = (val & 0x3F);
1244 if ((signal_exp & 0x20) != 0) 1520 if ((signal_exp & 0x20) != 0)
1245 signal_exp -= 0x40; 1521 signal_exp -= 0x40;
1246 1522
1247 if (signal_mant != 0) 1523 if (signal_mant != 0)
1248 result = intlog10(2) * 10 * signal_exp + 10 * 1524 result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
1249 intlog10(signal_mant);
1250 else 1525 else
1251 result = intlog10(2) * 10 * signal_exp - 100; 1526 result = intlog10(2) * 10 * signal_exp - 100;
1252 1527
1253 if (noise_mant != 0) 1528 if (noise_mant != 0)
1254 result -= intlog10(2) * 10 * noise_exp + 10 * 1529 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
1255 intlog10(noise_mant);
1256 else 1530 else
1257 result -= intlog10(2) * 10 * noise_exp - 100; 1531 result -= intlog10(2) * 10 * noise_exp - 100;
1258 1532
@@ -1260,7 +1534,7 @@ static int dib7000p_read_snr(struct dvb_frontend* fe, u16 *snr)
1260 return 0; 1534 return 0;
1261} 1535}
1262 1536
1263static int dib7000p_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune) 1537static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1264{ 1538{
1265 tune->min_delay_ms = 1000; 1539 tune->min_delay_ms = 1000;
1266 return 0; 1540 return 0;
@@ -1270,6 +1544,7 @@ static void dib7000p_release(struct dvb_frontend *demod)
1270{ 1544{
1271 struct dib7000p_state *st = demod->demodulator_priv; 1545 struct dib7000p_state *st = demod->demodulator_priv;
1272 dibx000_exit_i2c_master(&st->i2c_master); 1546 dibx000_exit_i2c_master(&st->i2c_master);
1547 i2c_del_adapter(&st->dib7090_tuner_adap);
1273 kfree(st); 1548 kfree(st);
1274} 1549}
1275 1550
@@ -1277,8 +1552,8 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap)
1277{ 1552{
1278 u8 tx[2], rx[2]; 1553 u8 tx[2], rx[2];
1279 struct i2c_msg msg[2] = { 1554 struct i2c_msg msg[2] = {
1280 { .addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2 }, 1555 {.addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2},
1281 { .addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2 }, 1556 {.addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2},
1282 }; 1557 };
1283 1558
1284 tx[0] = 0x03; 1559 tx[0] = 0x03;
@@ -1303,7 +1578,7 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap)
1303} 1578}
1304EXPORT_SYMBOL(dib7000pc_detection); 1579EXPORT_SYMBOL(dib7000pc_detection);
1305 1580
1306struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating) 1581struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
1307{ 1582{
1308 struct dib7000p_state *st = demod->demodulator_priv; 1583 struct dib7000p_state *st = demod->demodulator_priv;
1309 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating); 1584 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
@@ -1312,19 +1587,19 @@ EXPORT_SYMBOL(dib7000p_get_i2c_master);
1312 1587
1313int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff) 1588int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1314{ 1589{
1315 struct dib7000p_state *state = fe->demodulator_priv; 1590 struct dib7000p_state *state = fe->demodulator_priv;
1316 u16 val = dib7000p_read_word(state, 235) & 0xffef; 1591 u16 val = dib7000p_read_word(state, 235) & 0xffef;
1317 val |= (onoff & 0x1) << 4; 1592 val |= (onoff & 0x1) << 4;
1318 dprintk("PID filter enabled %d", onoff); 1593 dprintk("PID filter enabled %d", onoff);
1319 return dib7000p_write_word(state, 235, val); 1594 return dib7000p_write_word(state, 235, val);
1320} 1595}
1321EXPORT_SYMBOL(dib7000p_pid_filter_ctrl); 1596EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
1322 1597
1323int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff) 1598int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1324{ 1599{
1325 struct dib7000p_state *state = fe->demodulator_priv; 1600 struct dib7000p_state *state = fe->demodulator_priv;
1326 dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff); 1601 dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
1327 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0); 1602 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
1328} 1603}
1329EXPORT_SYMBOL(dib7000p_pid_filter); 1604EXPORT_SYMBOL(dib7000p_pid_filter);
1330 1605
@@ -1340,16 +1615,19 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1340 1615
1341 dpst->i2c_adap = i2c; 1616 dpst->i2c_adap = i2c;
1342 1617
1343 for (k = no_of_demods-1; k >= 0; k--) { 1618 for (k = no_of_demods - 1; k >= 0; k--) {
1344 dpst->cfg = cfg[k]; 1619 dpst->cfg = cfg[k];
1345 1620
1346 /* designated i2c address */ 1621 /* designated i2c address */
1347 new_addr = (0x40 + k) << 1; 1622 if (cfg[k].default_i2c_addr != 0)
1623 new_addr = cfg[k].default_i2c_addr + (k << 1);
1624 else
1625 new_addr = (0x40 + k) << 1;
1348 dpst->i2c_addr = new_addr; 1626 dpst->i2c_addr = new_addr;
1349 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */ 1627 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
1350 if (dib7000p_identify(dpst) != 0) { 1628 if (dib7000p_identify(dpst) != 0) {
1351 dpst->i2c_addr = default_addr; 1629 dpst->i2c_addr = default_addr;
1352 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */ 1630 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
1353 if (dib7000p_identify(dpst) != 0) { 1631 if (dib7000p_identify(dpst) != 0) {
1354 dprintk("DiB7000P #%d: not identified\n", k); 1632 dprintk("DiB7000P #%d: not identified\n", k);
1355 kfree(dpst); 1633 kfree(dpst);
@@ -1368,7 +1646,10 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1368 1646
1369 for (k = 0; k < no_of_demods; k++) { 1647 for (k = 0; k < no_of_demods; k++) {
1370 dpst->cfg = cfg[k]; 1648 dpst->cfg = cfg[k];
1371 dpst->i2c_addr = (0x40 + k) << 1; 1649 if (cfg[k].default_i2c_addr != 0)
1650 dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
1651 else
1652 dpst->i2c_addr = (0x40 + k) << 1;
1372 1653
1373 // unforce divstr 1654 // unforce divstr
1374 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2); 1655 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
@@ -1382,8 +1663,613 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
1382} 1663}
1383EXPORT_SYMBOL(dib7000p_i2c_enumeration); 1664EXPORT_SYMBOL(dib7000p_i2c_enumeration);
1384 1665
1666static const s32 lut_1000ln_mant[] = {
1667 6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
1668};
1669
1670static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
1671{
1672 struct dib7000p_state *state = fe->demodulator_priv;
1673 u32 tmp_val = 0, exp = 0, mant = 0;
1674 s32 pow_i;
1675 u16 buf[2];
1676 u8 ix = 0;
1677
1678 buf[0] = dib7000p_read_word(state, 0x184);
1679 buf[1] = dib7000p_read_word(state, 0x185);
1680 pow_i = (buf[0] << 16) | buf[1];
1681 dprintk("raw pow_i = %d", pow_i);
1682
1683 tmp_val = pow_i;
1684 while (tmp_val >>= 1)
1685 exp++;
1686
1687 mant = (pow_i * 1000 / (1 << exp));
1688 dprintk(" mant = %d exp = %d", mant / 1000, exp);
1689
1690 ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
1691 dprintk(" ix = %d", ix);
1692
1693 pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
1694 pow_i = (pow_i << 8) / 1000;
1695 dprintk(" pow_i = %d", pow_i);
1696
1697 return pow_i;
1698}
1699
1700static int map_addr_to_serpar_number(struct i2c_msg *msg)
1701{
1702 if ((msg->buf[0] <= 15))
1703 msg->buf[0] -= 1;
1704 else if (msg->buf[0] == 17)
1705 msg->buf[0] = 15;
1706 else if (msg->buf[0] == 16)
1707 msg->buf[0] = 17;
1708 else if (msg->buf[0] == 19)
1709 msg->buf[0] = 16;
1710 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1711 msg->buf[0] -= 3;
1712 else if (msg->buf[0] == 28)
1713 msg->buf[0] = 23;
1714 else
1715 return -EINVAL;
1716 return 0;
1717}
1718
1719static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1720{
1721 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1722 u8 n_overflow = 1;
1723 u16 i = 1000;
1724 u16 serpar_num = msg[0].buf[0];
1725
1726 while (n_overflow == 1 && i) {
1727 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
1728 i--;
1729 if (i == 0)
1730 dprintk("Tuner ITF: write busy (overflow)");
1731 }
1732 dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1733 dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1734
1735 return num;
1736}
1737
1738static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1739{
1740 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1741 u8 n_overflow = 1, n_empty = 1;
1742 u16 i = 1000;
1743 u16 serpar_num = msg[0].buf[0];
1744 u16 read_word;
1745
1746 while (n_overflow == 1 && i) {
1747 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
1748 i--;
1749 if (i == 0)
1750 dprintk("TunerITF: read busy (overflow)");
1751 }
1752 dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
1753
1754 i = 1000;
1755 while (n_empty == 1 && i) {
1756 n_empty = dib7000p_read_word(state, 1984) & 0x1;
1757 i--;
1758 if (i == 0)
1759 dprintk("TunerITF: read busy (empty)");
1760 }
1761 read_word = dib7000p_read_word(state, 1987);
1762 msg[1].buf[0] = (read_word >> 8) & 0xff;
1763 msg[1].buf[1] = (read_word) & 0xff;
1764
1765 return num;
1766}
1767
1768static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1769{
1770 if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
1771 if (num == 1) { /* write */
1772 return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
1773 } else { /* read */
1774 return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
1775 }
1776 }
1777 return num;
1778}
1779
1780int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num, u16 apb_address)
1781{
1782 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1783 u16 word;
1784
1785 if (num == 1) { /* write */
1786 dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1787 } else {
1788 word = dib7000p_read_word(state, apb_address);
1789 msg[1].buf[0] = (word >> 8) & 0xff;
1790 msg[1].buf[1] = (word) & 0xff;
1791 }
1792
1793 return num;
1794}
1795
1796static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1797{
1798 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1799
1800 u16 apb_address = 0, word;
1801 int i = 0;
1802 switch (msg[0].buf[0]) {
1803 case 0x12:
1804 apb_address = 1920;
1805 break;
1806 case 0x14:
1807 apb_address = 1921;
1808 break;
1809 case 0x24:
1810 apb_address = 1922;
1811 break;
1812 case 0x1a:
1813 apb_address = 1923;
1814 break;
1815 case 0x22:
1816 apb_address = 1924;
1817 break;
1818 case 0x33:
1819 apb_address = 1926;
1820 break;
1821 case 0x34:
1822 apb_address = 1927;
1823 break;
1824 case 0x35:
1825 apb_address = 1928;
1826 break;
1827 case 0x36:
1828 apb_address = 1929;
1829 break;
1830 case 0x37:
1831 apb_address = 1930;
1832 break;
1833 case 0x38:
1834 apb_address = 1931;
1835 break;
1836 case 0x39:
1837 apb_address = 1932;
1838 break;
1839 case 0x2a:
1840 apb_address = 1935;
1841 break;
1842 case 0x2b:
1843 apb_address = 1936;
1844 break;
1845 case 0x2c:
1846 apb_address = 1937;
1847 break;
1848 case 0x2d:
1849 apb_address = 1938;
1850 break;
1851 case 0x2e:
1852 apb_address = 1939;
1853 break;
1854 case 0x2f:
1855 apb_address = 1940;
1856 break;
1857 case 0x30:
1858 apb_address = 1941;
1859 break;
1860 case 0x31:
1861 apb_address = 1942;
1862 break;
1863 case 0x32:
1864 apb_address = 1943;
1865 break;
1866 case 0x3e:
1867 apb_address = 1944;
1868 break;
1869 case 0x3f:
1870 apb_address = 1945;
1871 break;
1872 case 0x40:
1873 apb_address = 1948;
1874 break;
1875 case 0x25:
1876 apb_address = 914;
1877 break;
1878 case 0x26:
1879 apb_address = 915;
1880 break;
1881 case 0x27:
1882 apb_address = 916;
1883 break;
1884 case 0x28:
1885 apb_address = 917;
1886 break;
1887 case 0x1d:
1888 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
1889 word = dib7000p_read_word(state, 384 + i);
1890 msg[1].buf[0] = (word >> 8) & 0xff;
1891 msg[1].buf[1] = (word) & 0xff;
1892 return num;
1893 case 0x1f:
1894 if (num == 1) { /* write */
1895 word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
1896 word &= 0x3;
1897 word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
1898 dib7000p_write_word(state, 72, word); /* Set the proper input */
1899 return num;
1900 }
1901 }
1902
1903 if (apb_address != 0) /* R/W acces via APB */
1904 return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
1905 else /* R/W access via SERPAR */
1906 return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
1907
1908 return 0;
1909}
1910
1911static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
1912{
1913 return I2C_FUNC_I2C;
1914}
1915
1916static struct i2c_algorithm dib7090_tuner_xfer_algo = {
1917 .master_xfer = dib7090_tuner_xfer,
1918 .functionality = dib7000p_i2c_func,
1919};
1920
1921struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
1922{
1923 struct dib7000p_state *st = fe->demodulator_priv;
1924 return &st->dib7090_tuner_adap;
1925}
1926EXPORT_SYMBOL(dib7090_get_i2c_tuner);
1927
1928static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
1929{
1930 u16 reg;
1931
1932 /* drive host bus 2, 3, 4 */
1933 reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1934 reg |= (drive << 12) | (drive << 6) | drive;
1935 dib7000p_write_word(state, 1798, reg);
1936
1937 /* drive host bus 5,6 */
1938 reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1939 reg |= (drive << 8) | (drive << 2);
1940 dib7000p_write_word(state, 1799, reg);
1941
1942 /* drive host bus 7, 8, 9 */
1943 reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1944 reg |= (drive << 12) | (drive << 6) | drive;
1945 dib7000p_write_word(state, 1800, reg);
1946
1947 /* drive host bus 10, 11 */
1948 reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1949 reg |= (drive << 8) | (drive << 2);
1950 dib7000p_write_word(state, 1801, reg);
1951
1952 /* drive host bus 12, 13, 14 */
1953 reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1954 reg |= (drive << 12) | (drive << 6) | drive;
1955 dib7000p_write_word(state, 1802, reg);
1956
1957 return 0;
1958}
1959
1960static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
1961{
1962 u32 quantif = 3;
1963 u32 nom = (insertExtSynchro * P_Kin + syncSize);
1964 u32 denom = P_Kout;
1965 u32 syncFreq = ((nom << quantif) / denom);
1966
1967 if ((syncFreq & ((1 << quantif) - 1)) != 0)
1968 syncFreq = (syncFreq >> quantif) + 1;
1969 else
1970 syncFreq = (syncFreq >> quantif);
1971
1972 if (syncFreq != 0)
1973 syncFreq = syncFreq - 1;
1974
1975 return syncFreq;
1976}
1977
1978static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
1979{
1980 u8 index_buf;
1981 u16 rx_copy_buf[22];
1982
1983 dprintk("Configure DibStream Tx");
1984 for (index_buf = 0; index_buf < 22; index_buf++)
1985 rx_copy_buf[index_buf] = dib7000p_read_word(state, 1536+index_buf);
1986
1987 dib7000p_write_word(state, 1615, 1);
1988 dib7000p_write_word(state, 1603, P_Kin);
1989 dib7000p_write_word(state, 1605, P_Kout);
1990 dib7000p_write_word(state, 1606, insertExtSynchro);
1991 dib7000p_write_word(state, 1608, synchroMode);
1992 dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1993 dib7000p_write_word(state, 1610, syncWord & 0xffff);
1994 dib7000p_write_word(state, 1612, syncSize);
1995 dib7000p_write_word(state, 1615, 0);
1996
1997 for (index_buf = 0; index_buf < 22; index_buf++)
1998 dib7000p_write_word(state, 1536+index_buf, rx_copy_buf[index_buf]);
1999
2000 return 0;
2001}
2002
2003static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
2004 u32 dataOutRate)
2005{
2006 u32 syncFreq;
2007
2008 dprintk("Configure DibStream Rx");
2009 if ((P_Kin != 0) && (P_Kout != 0)) {
2010 syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
2011 dib7000p_write_word(state, 1542, syncFreq);
2012 }
2013 dib7000p_write_word(state, 1554, 1);
2014 dib7000p_write_word(state, 1536, P_Kin);
2015 dib7000p_write_word(state, 1537, P_Kout);
2016 dib7000p_write_word(state, 1539, synchroMode);
2017 dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
2018 dib7000p_write_word(state, 1541, syncWord & 0xffff);
2019 dib7000p_write_word(state, 1543, syncSize);
2020 dib7000p_write_word(state, 1544, dataOutRate);
2021 dib7000p_write_word(state, 1554, 0);
2022
2023 return 0;
2024}
2025
2026static int dib7090_enDivOnHostBus(struct dib7000p_state *state)
2027{
2028 u16 reg;
2029
2030 dprintk("Enable Diversity on host bus");
2031 reg = (1 << 8) | (1 << 5);
2032 dib7000p_write_word(state, 1288, reg);
2033
2034 return dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2035}
2036
2037static int dib7090_enAdcOnHostBus(struct dib7000p_state *state)
2038{
2039 u16 reg;
2040
2041 dprintk("Enable ADC on host bus");
2042 reg = (1 << 7) | (1 << 5);
2043 dib7000p_write_word(state, 1288, reg);
2044
2045 return dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2046}
2047
2048static int dib7090_enMpegOnHostBus(struct dib7000p_state *state)
2049{
2050 u16 reg;
2051
2052 dprintk("Enable Mpeg on host bus");
2053 reg = (1 << 9) | (1 << 5);
2054 dib7000p_write_word(state, 1288, reg);
2055
2056 return dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
2057}
2058
2059static int dib7090_enMpegInput(struct dib7000p_state *state)
2060{
2061 dprintk("Enable Mpeg input");
2062 return dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
2063}
2064
2065static int dib7090_enMpegMux(struct dib7000p_state *state, u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
2066{
2067 u16 reg = (1 << 7) | ((pulseWidth & 0x1f) << 2) | ((enSerialMode & 0x1) << 1) | (enSerialClkDiv2 & 0x1);
2068
2069 dprintk("Enable Mpeg mux");
2070 dib7000p_write_word(state, 1287, reg);
2071
2072 reg &= ~(1 << 7);
2073 dib7000p_write_word(state, 1287, reg);
2074
2075 reg = (1 << 4);
2076 dib7000p_write_word(state, 1288, reg);
2077
2078 return 0;
2079}
2080
2081static int dib7090_disableMpegMux(struct dib7000p_state *state)
2082{
2083 u16 reg;
2084
2085 dprintk("Disable Mpeg mux");
2086 dib7000p_write_word(state, 1288, 0);
2087
2088 reg = dib7000p_read_word(state, 1287);
2089 reg &= ~(1 << 7);
2090 dib7000p_write_word(state, 1287, reg);
2091
2092 return 0;
2093}
2094
2095static int dib7090_set_input_mode(struct dvb_frontend *fe, int mode)
2096{
2097 struct dib7000p_state *state = fe->demodulator_priv;
2098
2099 switch (mode) {
2100 case INPUT_MODE_DIVERSITY:
2101 dprintk("Enable diversity INPUT");
2102 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
2103 break;
2104 case INPUT_MODE_MPEG:
2105 dprintk("Enable Mpeg INPUT");
2106 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
2107 break;
2108 case INPUT_MODE_OFF:
2109 default:
2110 dprintk("Disable INPUT");
2111 dib7090_cfg_DibRx(state, 0, 0, 0, 0, 0, 0, 0);
2112 break;
2113 }
2114 return 0;
2115}
2116
2117static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
2118{
2119 switch (onoff) {
2120 case 0: /* only use the internal way - not the diversity input */
2121 dib7090_set_input_mode(fe, INPUT_MODE_MPEG);
2122 break;
2123 case 1: /* both ways */
2124 case 2: /* only the diversity input */
2125 dib7090_set_input_mode(fe, INPUT_MODE_DIVERSITY);
2126 break;
2127 }
2128
2129 return 0;
2130}
2131
2132static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
2133{
2134 struct dib7000p_state *state = fe->demodulator_priv;
2135
2136 u16 outreg, smo_mode, fifo_threshold;
2137 u8 prefer_mpeg_mux_use = 1;
2138 int ret = 0;
2139
2140 dib7090_host_bus_drive(state, 1);
2141
2142 fifo_threshold = 1792;
2143 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
2144 outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
2145
2146 switch (mode) {
2147 case OUTMODE_HIGH_Z:
2148 outreg = 0;
2149 break;
2150
2151 case OUTMODE_MPEG2_SERIAL:
2152 if (prefer_mpeg_mux_use) {
2153 dprintk("Sip 7090P setting output mode TS_SERIAL using Mpeg Mux");
2154 dib7090_enMpegOnHostBus(state);
2155 dib7090_enMpegInput(state);
2156 if (state->cfg.enMpegOutput == 1)
2157 dib7090_enMpegMux(state, 3, 1, 1);
2158
2159 } else { /* Use Smooth block */
2160 dprintk("Sip 7090P setting output mode TS_SERIAL using Smooth bloc");
2161 dib7090_disableMpegMux(state);
2162 dib7000p_write_word(state, 1288, (1 << 6));
2163 outreg |= (2 << 6) | (0 << 1);
2164 }
2165 break;
2166
2167 case OUTMODE_MPEG2_PAR_GATED_CLK:
2168 if (prefer_mpeg_mux_use) {
2169 dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
2170 dib7090_enMpegOnHostBus(state);
2171 dib7090_enMpegInput(state);
2172 if (state->cfg.enMpegOutput == 1)
2173 dib7090_enMpegMux(state, 2, 0, 0);
2174 } else { /* Use Smooth block */
2175 dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Smooth block");
2176 dib7090_disableMpegMux(state);
2177 dib7000p_write_word(state, 1288, (1 << 6));
2178 outreg |= (0 << 6);
2179 }
2180 break;
2181
2182 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
2183 dprintk("Sip 7090P setting output mode TS_PARALLEL_CONT using Smooth block");
2184 dib7090_disableMpegMux(state);
2185 dib7000p_write_word(state, 1288, (1 << 6));
2186 outreg |= (1 << 6);
2187 break;
2188
2189 case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
2190 dprintk("Sip 7090P setting output mode TS_FIFO using Smooth block");
2191 dib7090_disableMpegMux(state);
2192 dib7000p_write_word(state, 1288, (1 << 6));
2193 outreg |= (5 << 6);
2194 smo_mode |= (3 << 1);
2195 fifo_threshold = 512;
2196 break;
2197
2198 case OUTMODE_DIVERSITY:
2199 dprintk("Sip 7090P setting output mode MODE_DIVERSITY");
2200 dib7090_disableMpegMux(state);
2201 dib7090_enDivOnHostBus(state);
2202 break;
2203
2204 case OUTMODE_ANALOG_ADC:
2205 dprintk("Sip 7090P setting output mode MODE_ANALOG_ADC");
2206 dib7090_enAdcOnHostBus(state);
2207 break;
2208 }
2209
2210 if (state->cfg.output_mpeg2_in_188_bytes)
2211 smo_mode |= (1 << 5);
2212
2213 ret |= dib7000p_write_word(state, 235, smo_mode);
2214 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
2215 ret |= dib7000p_write_word(state, 1286, outreg | (1 << 10)); /* allways set Dout active = 1 !!! */
2216
2217 return ret;
2218}
2219
2220int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
2221{
2222 struct dib7000p_state *state = fe->demodulator_priv;
2223 u16 en_cur_state;
2224
2225 dprintk("sleep dib7090: %d", onoff);
2226
2227 en_cur_state = dib7000p_read_word(state, 1922);
2228
2229 if (en_cur_state > 0xff)
2230 state->tuner_enable = en_cur_state;
2231
2232 if (onoff)
2233 en_cur_state &= 0x00ff;
2234 else {
2235 if (state->tuner_enable != 0)
2236 en_cur_state = state->tuner_enable;
2237 }
2238
2239 dib7000p_write_word(state, 1922, en_cur_state);
2240
2241 return 0;
2242}
2243EXPORT_SYMBOL(dib7090_tuner_sleep);
2244
2245int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
2246{
2247 dprintk("AGC restart callback: %d", restart);
2248 return 0;
2249}
2250EXPORT_SYMBOL(dib7090_agc_restart);
2251
2252int dib7090_get_adc_power(struct dvb_frontend *fe)
2253{
2254 return dib7000p_get_adc_power(fe);
2255}
2256EXPORT_SYMBOL(dib7090_get_adc_power);
2257
2258int dib7090_slave_reset(struct dvb_frontend *fe)
2259{
2260 struct dib7000p_state *state = fe->demodulator_priv;
2261 u16 reg;
2262
2263 reg = dib7000p_read_word(state, 1794);
2264 dib7000p_write_word(state, 1794, reg | (4 << 12));
2265
2266 dib7000p_write_word(state, 1032, 0xffff);
2267 return 0;
2268}
2269EXPORT_SYMBOL(dib7090_slave_reset);
2270
1385static struct dvb_frontend_ops dib7000p_ops; 2271static struct dvb_frontend_ops dib7000p_ops;
1386struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg) 2272struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
1387{ 2273{
1388 struct dvb_frontend *demod; 2274 struct dvb_frontend *demod;
1389 struct dib7000p_state *st; 2275 struct dib7000p_state *st;
@@ -1400,28 +2286,41 @@ struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
1400 /* Ensure the output mode remains at the previous default if it's 2286 /* Ensure the output mode remains at the previous default if it's
1401 * not specifically set by the caller. 2287 * not specifically set by the caller.
1402 */ 2288 */
1403 if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && 2289 if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
1404 (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
1405 st->cfg.output_mode = OUTMODE_MPEG2_FIFO; 2290 st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
1406 2291
1407 demod = &st->demod; 2292 demod = &st->demod;
1408 demod->demodulator_priv = st; 2293 demod->demodulator_priv = st;
1409 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops)); 2294 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
1410 2295
1411 dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */ 2296 dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
1412 2297
1413 if (dib7000p_identify(st) != 0) 2298 if (dib7000p_identify(st) != 0)
1414 goto error; 2299 goto error;
1415 2300
2301 st->version = dib7000p_read_word(st, 897);
2302
1416 /* FIXME: make sure the dev.parent field is initialized, or else 2303 /* FIXME: make sure the dev.parent field is initialized, or else
1417 request_firmware() will hit an OOPS (this should be moved somewhere 2304 request_firmware() will hit an OOPS (this should be moved somewhere
1418 more common) */ 2305 more common) */
1419 st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
1420 2306
1421 dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr); 2307 dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
1422 2308
2309 /* init 7090 tuner adapter */
2310 strncpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface", sizeof(st->dib7090_tuner_adap.name));
2311 st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
2312 st->dib7090_tuner_adap.algo_data = NULL;
2313 st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
2314 i2c_set_adapdata(&st->dib7090_tuner_adap, st);
2315 i2c_add_adapter(&st->dib7090_tuner_adap);
2316
1423 dib7000p_demod_reset(st); 2317 dib7000p_demod_reset(st);
1424 2318
2319 if (st->version == SOC7090) {
2320 dib7090_set_output_mode(demod, st->cfg.output_mode);
2321 dib7090_set_diversity_in(demod, 0);
2322 }
2323
1425 return demod; 2324 return demod;
1426 2325
1427error: 2326error:
@@ -1432,37 +2331,35 @@ EXPORT_SYMBOL(dib7000p_attach);
1432 2331
1433static struct dvb_frontend_ops dib7000p_ops = { 2332static struct dvb_frontend_ops dib7000p_ops = {
1434 .info = { 2333 .info = {
1435 .name = "DiBcom 7000PC", 2334 .name = "DiBcom 7000PC",
1436 .type = FE_OFDM, 2335 .type = FE_OFDM,
1437 .frequency_min = 44250000, 2336 .frequency_min = 44250000,
1438 .frequency_max = 867250000, 2337 .frequency_max = 867250000,
1439 .frequency_stepsize = 62500, 2338 .frequency_stepsize = 62500,
1440 .caps = FE_CAN_INVERSION_AUTO | 2339 .caps = FE_CAN_INVERSION_AUTO |
1441 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 2340 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1442 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 2341 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1443 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 2342 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1444 FE_CAN_TRANSMISSION_MODE_AUTO | 2343 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
1445 FE_CAN_GUARD_INTERVAL_AUTO | 2344 },
1446 FE_CAN_RECOVER | 2345
1447 FE_CAN_HIERARCHY_AUTO, 2346 .release = dib7000p_release,
1448 }, 2347
1449 2348 .init = dib7000p_wakeup,
1450 .release = dib7000p_release, 2349 .sleep = dib7000p_sleep,
1451 2350
1452 .init = dib7000p_wakeup, 2351 .set_frontend = dib7000p_set_frontend,
1453 .sleep = dib7000p_sleep, 2352 .get_tune_settings = dib7000p_fe_get_tune_settings,
1454 2353 .get_frontend = dib7000p_get_frontend,
1455 .set_frontend = dib7000p_set_frontend, 2354
1456 .get_tune_settings = dib7000p_fe_get_tune_settings, 2355 .read_status = dib7000p_read_status,
1457 .get_frontend = dib7000p_get_frontend, 2356 .read_ber = dib7000p_read_ber,
1458
1459 .read_status = dib7000p_read_status,
1460 .read_ber = dib7000p_read_ber,
1461 .read_signal_strength = dib7000p_read_signal_strength, 2357 .read_signal_strength = dib7000p_read_signal_strength,
1462 .read_snr = dib7000p_read_snr, 2358 .read_snr = dib7000p_read_snr,
1463 .read_ucblocks = dib7000p_read_unc_blocks, 2359 .read_ucblocks = dib7000p_read_unc_blocks,
1464}; 2360};
1465 2361
2362MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
1466MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); 2363MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
1467MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator"); 2364MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
1468MODULE_LICENSE("GPL"); 2365MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 13:10:11 -0500