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path: root/drivers/media/dvb/frontends/dib3000mb.c
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Diffstat (limited to 'drivers/media/dvb/frontends/dib3000mb.c')
-rw-r--r--drivers/media/dvb/frontends/dib3000mb.c784
1 files changed, 784 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/dib3000mb.c b/drivers/media/dvb/frontends/dib3000mb.c
new file mode 100644
index 000000000000..a853d12a26f1
--- /dev/null
+++ b/drivers/media/dvb/frontends/dib3000mb.c
@@ -0,0 +1,784 @@
1/*
2 * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
3 * DiBcom (http://www.dibcom.fr/)
4 *
5 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
6 *
7 * based on GPL code from DibCom, which has
8 *
9 * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation, version 2.
14 *
15 * Acknowledgements
16 *
17 * Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18 * sources, on which this driver (and the dvb-dibusb) are based.
19 *
20 * see Documentation/dvb/README.dibusb for more information
21 *
22 */
23
24#include <linux/config.h>
25#include <linux/kernel.h>
26#include <linux/version.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/delay.h>
31
32#include "dib3000-common.h"
33#include "dib3000mb_priv.h"
34#include "dib3000.h"
35
36/* Version information */
37#define DRIVER_VERSION "0.1"
38#define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
39#define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
40
41#ifdef CONFIG_DVB_DIBCOM_DEBUG
42static int debug;
43module_param(debug, int, 0644);
44MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
45#endif
46#define deb_info(args...) dprintk(0x01,args)
47#define deb_xfer(args...) dprintk(0x02,args)
48#define deb_setf(args...) dprintk(0x04,args)
49#define deb_getf(args...) dprintk(0x08,args)
50
51static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr);
52
53static int dib3000mb_get_frontend(struct dvb_frontend* fe,
54 struct dvb_frontend_parameters *fep);
55
56static int dib3000mb_set_frontend(struct dvb_frontend* fe,
57 struct dvb_frontend_parameters *fep, int tuner)
58{
59 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
60 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
61 fe_code_rate_t fe_cr = FEC_NONE;
62 int search_state, seq;
63
64 if (tuner) {
65 dib3000mb_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));
66 state->config.pll_set(fe, fep, NULL);
67 dib3000mb_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));
68
69 deb_setf("bandwidth: ");
70 switch (ofdm->bandwidth) {
71 case BANDWIDTH_8_MHZ:
72 deb_setf("8 MHz\n");
73 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
74 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
75 break;
76 case BANDWIDTH_7_MHZ:
77 deb_setf("7 MHz\n");
78 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
79 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
80 break;
81 case BANDWIDTH_6_MHZ:
82 deb_setf("6 MHz\n");
83 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
84 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
85 break;
86 case BANDWIDTH_AUTO:
87 return -EOPNOTSUPP;
88 default:
89 err("unkown bandwidth value.");
90 return -EINVAL;
91 }
92 }
93 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
94
95 deb_setf("transmission mode: ");
96 switch (ofdm->transmission_mode) {
97 case TRANSMISSION_MODE_2K:
98 deb_setf("2k\n");
99 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
100 break;
101 case TRANSMISSION_MODE_8K:
102 deb_setf("8k\n");
103 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
104 break;
105 case TRANSMISSION_MODE_AUTO:
106 deb_setf("auto\n");
107 break;
108 default:
109 return -EINVAL;
110 }
111
112 deb_setf("guard: ");
113 switch (ofdm->guard_interval) {
114 case GUARD_INTERVAL_1_32:
115 deb_setf("1_32\n");
116 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
117 break;
118 case GUARD_INTERVAL_1_16:
119 deb_setf("1_16\n");
120 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
121 break;
122 case GUARD_INTERVAL_1_8:
123 deb_setf("1_8\n");
124 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
125 break;
126 case GUARD_INTERVAL_1_4:
127 deb_setf("1_4\n");
128 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
129 break;
130 case GUARD_INTERVAL_AUTO:
131 deb_setf("auto\n");
132 break;
133 default:
134 return -EINVAL;
135 }
136
137 deb_setf("inversion: ");
138 switch (fep->inversion) {
139 case INVERSION_OFF:
140 deb_setf("off\n");
141 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
142 break;
143 case INVERSION_AUTO:
144 deb_setf("auto ");
145 break;
146 case INVERSION_ON:
147 deb_setf("on\n");
148 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
149 break;
150 default:
151 return -EINVAL;
152 }
153
154 deb_setf("constellation: ");
155 switch (ofdm->constellation) {
156 case QPSK:
157 deb_setf("qpsk\n");
158 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
159 break;
160 case QAM_16:
161 deb_setf("qam16\n");
162 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
163 break;
164 case QAM_64:
165 deb_setf("qam64\n");
166 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
167 break;
168 case QAM_AUTO:
169 break;
170 default:
171 return -EINVAL;
172 }
173 deb_setf("hierachy: ");
174 switch (ofdm->hierarchy_information) {
175 case HIERARCHY_NONE:
176 deb_setf("none ");
177 /* fall through */
178 case HIERARCHY_1:
179 deb_setf("alpha=1\n");
180 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
181 break;
182 case HIERARCHY_2:
183 deb_setf("alpha=2\n");
184 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
185 break;
186 case HIERARCHY_4:
187 deb_setf("alpha=4\n");
188 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
189 break;
190 case HIERARCHY_AUTO:
191 deb_setf("alpha=auto\n");
192 break;
193 default:
194 return -EINVAL;
195 }
196
197 deb_setf("hierarchy: ");
198 if (ofdm->hierarchy_information == HIERARCHY_NONE) {
199 deb_setf("none\n");
200 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
201 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
202 fe_cr = ofdm->code_rate_HP;
203 } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
204 deb_setf("on\n");
205 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
206 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
207 fe_cr = ofdm->code_rate_LP;
208 }
209 deb_setf("fec: ");
210 switch (fe_cr) {
211 case FEC_1_2:
212 deb_setf("1_2\n");
213 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
214 break;
215 case FEC_2_3:
216 deb_setf("2_3\n");
217 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
218 break;
219 case FEC_3_4:
220 deb_setf("3_4\n");
221 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
222 break;
223 case FEC_5_6:
224 deb_setf("5_6\n");
225 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
226 break;
227 case FEC_7_8:
228 deb_setf("7_8\n");
229 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
230 break;
231 case FEC_NONE:
232 deb_setf("none ");
233 break;
234 case FEC_AUTO:
235 deb_setf("auto\n");
236 break;
237 default:
238 return -EINVAL;
239 }
240
241 seq = dib3000_seq
242 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
243 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
244 [fep->inversion == INVERSION_AUTO];
245
246 deb_setf("seq? %d\n", seq);
247
248 wr(DIB3000MB_REG_SEQ, seq);
249
250 wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
251
252 if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
253 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
254 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
255 } else {
256 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
257 }
258
259 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
260 } else {
261 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
262 }
263
264 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
265 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
266 wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
267
268 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
269
270 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
271
272 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
273 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
274
275 /* wait for AGC lock */
276 msleep(70);
277
278 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
279
280 /* something has to be auto searched */
281 if (ofdm->constellation == QAM_AUTO ||
282 ofdm->hierarchy_information == HIERARCHY_AUTO ||
283 fe_cr == FEC_AUTO ||
284 fep->inversion == INVERSION_AUTO) {
285 int as_count=0;
286
287 deb_setf("autosearch enabled.\n");
288
289 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
290
291 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
292 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
293
294 while ((search_state =
295 dib3000_search_status(
296 rd(DIB3000MB_REG_AS_IRQ_PENDING),
297 rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
298 msleep(1);
299
300 deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
301
302 if (search_state == 1) {
303 struct dvb_frontend_parameters feps;
304 if (dib3000mb_get_frontend(fe, &feps) == 0) {
305 deb_setf("reading tuning data from frontend succeeded.\n");
306 return dib3000mb_set_frontend(fe, &feps, 0);
307 }
308 }
309
310 } else {
311 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
312 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
313 }
314
315 return 0;
316}
317
318static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
319{
320 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
321
322 deb_info("dib3000mb is getting up.\n");
323 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
324
325 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
326
327 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
328 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
329
330 wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
331
332 wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
333
334 wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
335 wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
336
337 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
338
339 wr_foreach(dib3000mb_reg_impulse_noise,
340 dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
341
342 wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
343
344 wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
345
346 wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
347
348 wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
349
350 wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
351
352 wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
353 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
354 wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
355 wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
356
357 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
358
359 wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
360 wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
361 wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
362 wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
363 wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
364 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
365 wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
366 wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
367 wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
368 wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
369 wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
370 wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
371 wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
372 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
373 wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
374
375 wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
376
377 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
378 wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
379 wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
380
381 wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
382
383 wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
384 wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
385 wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
386 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
387 wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
388 wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
389
390 wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
391
392 if (state->config.pll_init) {
393 dib3000mb_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));
394 state->config.pll_init(fe,NULL);
395 dib3000mb_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));
396 }
397
398 return 0;
399}
400
401static int dib3000mb_get_frontend(struct dvb_frontend* fe,
402 struct dvb_frontend_parameters *fep)
403{
404 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
405 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
406 fe_code_rate_t *cr;
407 u16 tps_val;
408 int inv_test1,inv_test2;
409 u32 dds_val, threshold = 0x800000;
410
411 if (!rd(DIB3000MB_REG_TPS_LOCK))
412 return 0;
413
414 dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
415 deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
416 if (dds_val < threshold)
417 inv_test1 = 0;
418 else if (dds_val == threshold)
419 inv_test1 = 1;
420 else
421 inv_test1 = 2;
422
423 dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
424 deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
425 if (dds_val < threshold)
426 inv_test2 = 0;
427 else if (dds_val == threshold)
428 inv_test2 = 1;
429 else
430 inv_test2 = 2;
431
432 fep->inversion =
433 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
434 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
435 INVERSION_ON : INVERSION_OFF;
436
437 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
438
439 switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
440 case DIB3000_CONSTELLATION_QPSK:
441 deb_getf("QPSK ");
442 ofdm->constellation = QPSK;
443 break;
444 case DIB3000_CONSTELLATION_16QAM:
445 deb_getf("QAM16 ");
446 ofdm->constellation = QAM_16;
447 break;
448 case DIB3000_CONSTELLATION_64QAM:
449 deb_getf("QAM64 ");
450 ofdm->constellation = QAM_64;
451 break;
452 default:
453 err("Unexpected constellation returned by TPS (%d)", tps_val);
454 break;
455 }
456 deb_getf("TPS: %d\n", tps_val);
457
458 if (rd(DIB3000MB_REG_TPS_HRCH)) {
459 deb_getf("HRCH ON\n");
460 cr = &ofdm->code_rate_LP;
461 ofdm->code_rate_HP = FEC_NONE;
462 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
463 case DIB3000_ALPHA_0:
464 deb_getf("HIERARCHY_NONE ");
465 ofdm->hierarchy_information = HIERARCHY_NONE;
466 break;
467 case DIB3000_ALPHA_1:
468 deb_getf("HIERARCHY_1 ");
469 ofdm->hierarchy_information = HIERARCHY_1;
470 break;
471 case DIB3000_ALPHA_2:
472 deb_getf("HIERARCHY_2 ");
473 ofdm->hierarchy_information = HIERARCHY_2;
474 break;
475 case DIB3000_ALPHA_4:
476 deb_getf("HIERARCHY_4 ");
477 ofdm->hierarchy_information = HIERARCHY_4;
478 break;
479 default:
480 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
481 break;
482 }
483 deb_getf("TPS: %d\n", tps_val);
484
485 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
486 } else {
487 deb_getf("HRCH OFF\n");
488 cr = &ofdm->code_rate_HP;
489 ofdm->code_rate_LP = FEC_NONE;
490 ofdm->hierarchy_information = HIERARCHY_NONE;
491
492 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
493 }
494
495 switch (tps_val) {
496 case DIB3000_FEC_1_2:
497 deb_getf("FEC_1_2 ");
498 *cr = FEC_1_2;
499 break;
500 case DIB3000_FEC_2_3:
501 deb_getf("FEC_2_3 ");
502 *cr = FEC_2_3;
503 break;
504 case DIB3000_FEC_3_4:
505 deb_getf("FEC_3_4 ");
506 *cr = FEC_3_4;
507 break;
508 case DIB3000_FEC_5_6:
509 deb_getf("FEC_5_6 ");
510 *cr = FEC_4_5;
511 break;
512 case DIB3000_FEC_7_8:
513 deb_getf("FEC_7_8 ");
514 *cr = FEC_7_8;
515 break;
516 default:
517 err("Unexpected FEC returned by TPS (%d)", tps_val);
518 break;
519 }
520 deb_getf("TPS: %d\n",tps_val);
521
522 switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
523 case DIB3000_GUARD_TIME_1_32:
524 deb_getf("GUARD_INTERVAL_1_32 ");
525 ofdm->guard_interval = GUARD_INTERVAL_1_32;
526 break;
527 case DIB3000_GUARD_TIME_1_16:
528 deb_getf("GUARD_INTERVAL_1_16 ");
529 ofdm->guard_interval = GUARD_INTERVAL_1_16;
530 break;
531 case DIB3000_GUARD_TIME_1_8:
532 deb_getf("GUARD_INTERVAL_1_8 ");
533 ofdm->guard_interval = GUARD_INTERVAL_1_8;
534 break;
535 case DIB3000_GUARD_TIME_1_4:
536 deb_getf("GUARD_INTERVAL_1_4 ");
537 ofdm->guard_interval = GUARD_INTERVAL_1_4;
538 break;
539 default:
540 err("Unexpected Guard Time returned by TPS (%d)", tps_val);
541 break;
542 }
543 deb_getf("TPS: %d\n", tps_val);
544
545 switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
546 case DIB3000_TRANSMISSION_MODE_2K:
547 deb_getf("TRANSMISSION_MODE_2K ");
548 ofdm->transmission_mode = TRANSMISSION_MODE_2K;
549 break;
550 case DIB3000_TRANSMISSION_MODE_8K:
551 deb_getf("TRANSMISSION_MODE_8K ");
552 ofdm->transmission_mode = TRANSMISSION_MODE_8K;
553 break;
554 default:
555 err("unexpected transmission mode return by TPS (%d)", tps_val);
556 break;
557 }
558 deb_getf("TPS: %d\n", tps_val);
559
560 return 0;
561}
562
563static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
564{
565 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
566
567 *stat = 0;
568
569 if (rd(DIB3000MB_REG_AGC_LOCK))
570 *stat |= FE_HAS_SIGNAL;
571 if (rd(DIB3000MB_REG_CARRIER_LOCK))
572 *stat |= FE_HAS_CARRIER;
573 if (rd(DIB3000MB_REG_VIT_LCK))
574 *stat |= FE_HAS_VITERBI;
575 if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
576 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
577
578 deb_getf("actual status is %2x\n",*stat);
579
580 deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
581 rd(DIB3000MB_REG_TPS_LOCK),
582 rd(DIB3000MB_REG_TPS_QAM),
583 rd(DIB3000MB_REG_TPS_HRCH),
584 rd(DIB3000MB_REG_TPS_VIT_ALPHA),
585 rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
586 rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
587 rd(DIB3000MB_REG_TPS_GUARD_TIME),
588 rd(DIB3000MB_REG_TPS_FFT),
589 rd(DIB3000MB_REG_TPS_CELL_ID));
590
591 //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
592 return 0;
593}
594
595static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
596{
597 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
598
599 *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
600 return 0;
601}
602
603/* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
604static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
605{
606 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
607
608 *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
609 return 0;
610}
611
612static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
613{
614 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
615 short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
616 int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
617 rd(DIB3000MB_REG_NOISE_POWER_LSB);
618 *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
619 return 0;
620}
621
622static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
623{
624 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
625
626 *unc = rd(DIB3000MB_REG_UNC);
627 return 0;
628}
629
630static int dib3000mb_sleep(struct dvb_frontend* fe)
631{
632 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
633 deb_info("dib3000mb is going to bed.\n");
634 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
635 return 0;
636}
637
638static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
639{
640 tune->min_delay_ms = 800;
641 tune->step_size = 166667;
642 tune->max_drift = 166667 * 2;
643
644 return 0;
645}
646
647static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
648{
649 return dib3000mb_fe_init(fe, 0);
650}
651
652static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
653{
654 return dib3000mb_set_frontend(fe, fep, 1);
655}
656
657static void dib3000mb_release(struct dvb_frontend* fe)
658{
659 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
660 kfree(state);
661}
662
663/* pid filter and transfer stuff */
664static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
665{
666 struct dib3000_state *state = fe->demodulator_priv;
667 pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
668 wr(index+DIB3000MB_REG_FIRST_PID,pid);
669 return 0;
670}
671
672static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
673{
674 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
675
676 deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
677 if (onoff) {
678 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
679 } else {
680 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
681 }
682 return 0;
683}
684
685static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
686{
687 struct dib3000_state *state = fe->demodulator_priv;
688 deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
689 wr(DIB3000MB_REG_PID_PARSE,onoff);
690 return 0;
691}
692
693static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
694{
695 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
696 if (onoff) {
697 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
698 } else {
699 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
700 }
701 return 0;
702}
703
704static struct dvb_frontend_ops dib3000mb_ops;
705
706struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
707 struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
708{
709 struct dib3000_state* state = NULL;
710
711 /* allocate memory for the internal state */
712 state = (struct dib3000_state*) kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
713 if (state == NULL)
714 goto error;
715 memset(state,0,sizeof(struct dib3000_state));
716
717 /* setup the state */
718 state->i2c = i2c;
719 memcpy(&state->config,config,sizeof(struct dib3000_config));
720 memcpy(&state->ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
721
722 /* check for the correct demod */
723 if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
724 goto error;
725
726 if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
727 goto error;
728
729 /* create dvb_frontend */
730 state->frontend.ops = &state->ops;
731 state->frontend.demodulator_priv = state;
732
733 /* set the xfer operations */
734 xfer_ops->pid_parse = dib3000mb_pid_parse;
735 xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
736 xfer_ops->pid_ctrl = dib3000mb_pid_control;
737 xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
738
739 return &state->frontend;
740
741error:
742 kfree(state);
743 return NULL;
744}
745
746static struct dvb_frontend_ops dib3000mb_ops = {
747
748 .info = {
749 .name = "DiBcom 3000M-B DVB-T",
750 .type = FE_OFDM,
751 .frequency_min = 44250000,
752 .frequency_max = 867250000,
753 .frequency_stepsize = 62500,
754 .caps = FE_CAN_INVERSION_AUTO |
755 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
756 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
757 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
758 FE_CAN_TRANSMISSION_MODE_AUTO |
759 FE_CAN_GUARD_INTERVAL_AUTO |
760 FE_CAN_RECOVER |
761 FE_CAN_HIERARCHY_AUTO,
762 },
763
764 .release = dib3000mb_release,
765
766 .init = dib3000mb_fe_init_nonmobile,
767 .sleep = dib3000mb_sleep,
768
769 .set_frontend = dib3000mb_set_frontend_and_tuner,
770 .get_frontend = dib3000mb_get_frontend,
771 .get_tune_settings = dib3000mb_fe_get_tune_settings,
772
773 .read_status = dib3000mb_read_status,
774 .read_ber = dib3000mb_read_ber,
775 .read_signal_strength = dib3000mb_read_signal_strength,
776 .read_snr = dib3000mb_read_snr,
777 .read_ucblocks = dib3000mb_read_unc_blocks,
778};
779
780MODULE_AUTHOR(DRIVER_AUTHOR);
781MODULE_DESCRIPTION(DRIVER_DESC);
782MODULE_LICENSE("GPL");
783
784EXPORT_SYMBOL(dib3000mb_attach);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 23:33:37 -0500