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path: root/drivers/media/dvb/frontends/dib0090.c
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Diffstat (limited to 'drivers/media/dvb/frontends/dib0090.c')
-rw-r--r--drivers/media/dvb/frontends/dib0090.c1583
1 files changed, 1258 insertions, 325 deletions
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
index 65240b7801e8..52ff1a252a90 100644
--- a/drivers/media/dvb/frontends/dib0090.c
+++ b/drivers/media/dvb/frontends/dib0090.c
@@ -45,6 +45,7 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
45 } \ 45 } \
46} while (0) 46} while (0)
47 47
48#define CONFIG_SYS_DVBT
48#define CONFIG_SYS_ISDBT 49#define CONFIG_SYS_ISDBT
49#define CONFIG_BAND_CBAND 50#define CONFIG_BAND_CBAND
50#define CONFIG_BAND_VHF 51#define CONFIG_BAND_VHF
@@ -76,6 +77,34 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
76#define EN_SBD 0x44E9 77#define EN_SBD 0x44E9
77#define EN_CAB 0x88E9 78#define EN_CAB 0x88E9
78 79
80/* Calibration defines */
81#define DC_CAL 0x1
82#define WBD_CAL 0x2
83#define TEMP_CAL 0x4
84#define CAPTRIM_CAL 0x8
85
86#define KROSUS_PLL_LOCKED 0x800
87#define KROSUS 0x2
88
89/* Use those defines to identify SOC version */
90#define SOC 0x02
91#define SOC_7090_P1G_11R1 0x82
92#define SOC_7090_P1G_21R1 0x8a
93#define SOC_8090_P1G_11R1 0x86
94#define SOC_8090_P1G_21R1 0x8e
95
96/* else use thos ones to check */
97#define P1A_B 0x0
98#define P1C 0x1
99#define P1D_E_F 0x3
100#define P1G 0x7
101#define P1G_21R2 0xf
102
103#define MP001 0x1 /* Single 9090/8096 */
104#define MP005 0x4 /* Single Sband */
105#define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
106#define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
107
79#define pgm_read_word(w) (*w) 108#define pgm_read_word(w) (*w)
80 109
81struct dc_calibration; 110struct dc_calibration;
@@ -84,7 +113,7 @@ struct dib0090_tuning {
84 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */ 113 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
85 u8 switch_trim; 114 u8 switch_trim;
86 u8 lna_tune; 115 u8 lna_tune;
87 u8 lna_bias; 116 u16 lna_bias;
88 u16 v2i; 117 u16 v2i;
89 u16 mix; 118 u16 mix;
90 u16 load; 119 u16 load;
@@ -99,13 +128,19 @@ struct dib0090_pll {
99 u8 topresc; 128 u8 topresc;
100}; 129};
101 130
131struct dib0090_identity {
132 u8 version;
133 u8 product;
134 u8 p1g;
135 u8 in_soc;
136};
137
102struct dib0090_state { 138struct dib0090_state {
103 struct i2c_adapter *i2c; 139 struct i2c_adapter *i2c;
104 struct dvb_frontend *fe; 140 struct dvb_frontend *fe;
105 const struct dib0090_config *config; 141 const struct dib0090_config *config;
106 142
107 u8 current_band; 143 u8 current_band;
108 u16 revision;
109 enum frontend_tune_state tune_state; 144 enum frontend_tune_state tune_state;
110 u32 current_rf; 145 u32 current_rf;
111 146
@@ -143,7 +178,26 @@ struct dib0090_state {
143 u8 tuner_is_tuned; 178 u8 tuner_is_tuned;
144 u8 agc_freeze; 179 u8 agc_freeze;
145 180
146 u8 reset; 181 struct dib0090_identity identity;
182
183 u32 rf_request;
184 u8 current_standard;
185
186 u8 calibrate;
187 u32 rest;
188 u16 bias;
189 s16 temperature;
190
191 u8 wbd_calibration_gain;
192 const struct dib0090_wbd_slope *current_wbd_table;
193 u16 wbdmux;
194};
195
196struct dib0090_fw_state {
197 struct i2c_adapter *i2c;
198 struct dvb_frontend *fe;
199 struct dib0090_identity identity;
200 const struct dib0090_config *config;
147}; 201};
148 202
149static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) 203static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
@@ -171,6 +225,28 @@ static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
171 return 0; 225 return 0;
172} 226}
173 227
228static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
229{
230 u8 b[2];
231 struct i2c_msg msg = {.addr = reg, .flags = I2C_M_RD, .buf = b, .len = 2 };
232 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
233 printk(KERN_WARNING "DiB0090 I2C read failed\n");
234 return 0;
235 }
236 return (b[0] << 8) | b[1];
237}
238
239static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
240{
241 u8 b[2] = { val >> 8, val & 0xff };
242 struct i2c_msg msg = {.addr = reg, .flags = 0, .buf = b, .len = 2 };
243 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
244 printk(KERN_WARNING "DiB0090 I2C write failed\n");
245 return -EREMOTEIO;
246 }
247 return 0;
248}
249
174#define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0) 250#define HARD_RESET(state) do { if (cfg->reset) { if (cfg->sleep) cfg->sleep(fe, 0); msleep(10); cfg->reset(fe, 1); msleep(10); cfg->reset(fe, 0); msleep(10); } } while (0)
175#define ADC_TARGET -220 251#define ADC_TARGET -220
176#define GAIN_ALPHA 5 252#define GAIN_ALPHA 5
@@ -183,89 +259,327 @@ static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b,
183 } while (--c); 259 } while (--c);
184} 260}
185 261
186static u16 dib0090_identify(struct dvb_frontend *fe) 262static int dib0090_identify(struct dvb_frontend *fe)
187{ 263{
188 struct dib0090_state *state = fe->tuner_priv; 264 struct dib0090_state *state = fe->tuner_priv;
189 u16 v; 265 u16 v;
266 struct dib0090_identity *identity = &state->identity;
190 267
191 v = dib0090_read_reg(state, 0x1a); 268 v = dib0090_read_reg(state, 0x1a);
192 269
193#ifdef FIRMWARE_FIREFLY 270 identity->p1g = 0;
194 /* pll is not locked locked */ 271 identity->in_soc = 0;
195 if (!(v & 0x800)) 272
196 dprintk("FE%d : Identification : pll is not yet locked", fe->id); 273 dprintk("Tuner identification (Version = 0x%04x)", v);
197#endif
198 274
199 /* without PLL lock info */ 275 /* without PLL lock info */
200 v &= 0x3ff; 276 v &= ~KROSUS_PLL_LOCKED;
201 dprintk("P/V: %04x:", v);
202 277
203 if ((v >> 8) & 0xf) 278 identity->version = v & 0xff;
204 dprintk("FE%d : Product ID = 0x%x : KROSUS", fe->id, (v >> 8) & 0xf); 279 identity->product = (v >> 8) & 0xf;
205 else 280
206 return 0xff; 281 if (identity->product != KROSUS)
207 282 goto identification_error;
208 v &= 0xff; 283
209 if (((v >> 5) & 0x7) == 0x1) 284 if ((identity->version & 0x3) == SOC) {
210 dprintk("FE%d : MP001 : 9090/8096", fe->id); 285 identity->in_soc = 1;
211 else if (((v >> 5) & 0x7) == 0x4) 286 switch (identity->version) {
212 dprintk("FE%d : MP005 : Single Sband", fe->id); 287 case SOC_8090_P1G_11R1:
213 else if (((v >> 5) & 0x7) == 0x6) 288 dprintk("SOC 8090 P1-G11R1 Has been detected");
214 dprintk("FE%d : MP008 : diversity VHF-UHF-LBAND", fe->id); 289 identity->p1g = 1;
215 else if (((v >> 5) & 0x7) == 0x7) 290 break;
216 dprintk("FE%d : MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND", fe->id); 291 case SOC_8090_P1G_21R1:
217 else 292 dprintk("SOC 8090 P1-G21R1 Has been detected");
218 return 0xff; 293 identity->p1g = 1;
219 294 break;
220 /* revision only */ 295 case SOC_7090_P1G_11R1:
221 if ((v & 0x1f) == 0x3) 296 dprintk("SOC 7090 P1-G11R1 Has been detected");
222 dprintk("FE%d : P1-D/E/F detected", fe->id); 297 identity->p1g = 1;
223 else if ((v & 0x1f) == 0x1) 298 break;
224 dprintk("FE%d : P1C detected", fe->id); 299 case SOC_7090_P1G_21R1:
225 else if ((v & 0x1f) == 0x0) { 300 dprintk("SOC 7090 P1-G21R1 Has been detected");
226#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT 301 identity->p1g = 1;
227 dprintk("FE%d : P1-A/B detected: using previous driver - support will be removed soon", fe->id); 302 break;
228 dib0090_p1b_register(fe); 303 default:
229#else 304 goto identification_error;
230 dprintk("FE%d : P1-A/B detected: driver is deactivated - not available", fe->id); 305 }
231 return 0xff; 306 } else {
232#endif 307 switch ((identity->version >> 5) & 0x7) {
308 case MP001:
309 dprintk("MP001 : 9090/8096");
310 break;
311 case MP005:
312 dprintk("MP005 : Single Sband");
313 break;
314 case MP008:
315 dprintk("MP008 : diversity VHF-UHF-LBAND");
316 break;
317 case MP009:
318 dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
319 break;
320 default:
321 goto identification_error;
322 }
323
324 switch (identity->version & 0x1f) {
325 case P1G_21R2:
326 dprintk("P1G_21R2 detected");
327 identity->p1g = 1;
328 break;
329 case P1G:
330 dprintk("P1G detected");
331 identity->p1g = 1;
332 break;
333 case P1D_E_F:
334 dprintk("P1D/E/F detected");
335 break;
336 case P1C:
337 dprintk("P1C detected");
338 break;
339 case P1A_B:
340 dprintk("P1-A/B detected: driver is deactivated - not available");
341 goto identification_error;
342 break;
343 default:
344 goto identification_error;
345 }
233 } 346 }
234 347
235 return v; 348 return 0;
349
350identification_error:
351 return -EIO;
352}
353
354static int dib0090_fw_identify(struct dvb_frontend *fe)
355{
356 struct dib0090_fw_state *state = fe->tuner_priv;
357 struct dib0090_identity *identity = &state->identity;
358
359 u16 v = dib0090_fw_read_reg(state, 0x1a);
360 identity->p1g = 0;
361 identity->in_soc = 0;
362
363 dprintk("FE: Tuner identification (Version = 0x%04x)", v);
364
365 /* without PLL lock info */
366 v &= ~KROSUS_PLL_LOCKED;
367
368 identity->version = v & 0xff;
369 identity->product = (v >> 8) & 0xf;
370
371 if (identity->product != KROSUS)
372 goto identification_error;
373
374 if ((identity->version & 0x3) == SOC) {
375 identity->in_soc = 1;
376 switch (identity->version) {
377 case SOC_8090_P1G_11R1:
378 dprintk("SOC 8090 P1-G11R1 Has been detected");
379 identity->p1g = 1;
380 break;
381 case SOC_8090_P1G_21R1:
382 dprintk("SOC 8090 P1-G21R1 Has been detected");
383 identity->p1g = 1;
384 break;
385 case SOC_7090_P1G_11R1:
386 dprintk("SOC 7090 P1-G11R1 Has been detected");
387 identity->p1g = 1;
388 break;
389 case SOC_7090_P1G_21R1:
390 dprintk("SOC 7090 P1-G21R1 Has been detected");
391 identity->p1g = 1;
392 break;
393 default:
394 goto identification_error;
395 }
396 } else {
397 switch ((identity->version >> 5) & 0x7) {
398 case MP001:
399 dprintk("MP001 : 9090/8096");
400 break;
401 case MP005:
402 dprintk("MP005 : Single Sband");
403 break;
404 case MP008:
405 dprintk("MP008 : diversity VHF-UHF-LBAND");
406 break;
407 case MP009:
408 dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
409 break;
410 default:
411 goto identification_error;
412 }
413
414 switch (identity->version & 0x1f) {
415 case P1G_21R2:
416 dprintk("P1G_21R2 detected");
417 identity->p1g = 1;
418 break;
419 case P1G:
420 dprintk("P1G detected");
421 identity->p1g = 1;
422 break;
423 case P1D_E_F:
424 dprintk("P1D/E/F detected");
425 break;
426 case P1C:
427 dprintk("P1C detected");
428 break;
429 case P1A_B:
430 dprintk("P1-A/B detected: driver is deactivated - not available");
431 goto identification_error;
432 break;
433 default:
434 goto identification_error;
435 }
436 }
437
438 return 0;
439
440identification_error:
441 return -EIO;;
236} 442}
237 443
238static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg) 444static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
239{ 445{
240 struct dib0090_state *state = fe->tuner_priv; 446 struct dib0090_state *state = fe->tuner_priv;
447 u16 PllCfg, i, v;
241 448
242 HARD_RESET(state); 449 HARD_RESET(state);
243 450
244 dib0090_write_reg(state, 0x24, EN_PLL); 451 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
245 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */ 452 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
246 453
247 /* adcClkOutRatio=8->7, release reset */ 454 if (!cfg->in_soc) {
248 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0); 455 /* adcClkOutRatio=8->7, release reset */
456 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
457 if (cfg->clkoutdrive != 0)
458 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
459 | (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
460 else
461 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
462 | (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
463 }
464
465 /* Read Pll current config * */
466 PllCfg = dib0090_read_reg(state, 0x21);
467
468 /** Reconfigure PLL if current setting is different from default setting **/
469 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
470 && !cfg->io.pll_bypass) {
471
472 /* Set Bypass mode */
473 PllCfg |= (1 << 15);
474 dib0090_write_reg(state, 0x21, PllCfg);
475
476 /* Set Reset Pll */
477 PllCfg &= ~(1 << 13);
478 dib0090_write_reg(state, 0x21, PllCfg);
479
480 /*** Set new Pll configuration in bypass and reset state ***/
481 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
482 dib0090_write_reg(state, 0x21, PllCfg);
483
484 /* Remove Reset Pll */
485 PllCfg |= (1 << 13);
486 dib0090_write_reg(state, 0x21, PllCfg);
487
488 /*** Wait for PLL lock ***/
489 i = 100;
490 do {
491 v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
492 if (v)
493 break;
494 } while (--i);
495
496 if (i == 0) {
497 dprintk("Pll: Unable to lock Pll");
498 return;
499 }
500
501 /* Finally Remove Bypass mode */
502 PllCfg &= ~(1 << 15);
503 dib0090_write_reg(state, 0x21, PllCfg);
504 }
505
506 if (cfg->io.pll_bypass) {
507 PllCfg |= (cfg->io.pll_bypass << 15);
508 dib0090_write_reg(state, 0x21, PllCfg);
509 }
510}
511
512static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
513{
514 struct dib0090_fw_state *state = fe->tuner_priv;
515 u16 PllCfg;
516 u16 v;
517 int i;
518
519 dprintk("fw reset digital");
520 HARD_RESET(state);
521
522 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
523 dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
524
525 dib0090_fw_write_reg(state, 0x20,
526 ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) | cfg->ls_cfg_pad_drv);
527
528 v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
249 if (cfg->clkoutdrive != 0) 529 if (cfg->clkoutdrive != 0)
250 dib0090_write_reg(state, 0x23, 530 v |= cfg->clkoutdrive << 5;
251 (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (cfg->clkoutdrive << 5) | (cfg->
252 clkouttobamse
253 << 4) | (0
254 <<
255 2)
256 | (0));
257 else 531 else
258 dib0090_write_reg(state, 0x23, 532 v |= 7 << 5;
259 (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (7 << 5) | (cfg-> 533
260 clkouttobamse << 4) | (0 534 v |= 2 << 10;
261 << 535 dib0090_fw_write_reg(state, 0x23, v);
262 2) 536
263 | (0)); 537 /* Read Pll current config * */
538 PllCfg = dib0090_fw_read_reg(state, 0x21);
539
540 /** Reconfigure PLL if current setting is different from default setting **/
541 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
264 542
265 /* enable pll, de-activate reset, ratio: 2/1 = 60MHz */ 543 /* Set Bypass mode */
266 dib0090_write_reg(state, 0x21, 544 PllCfg |= (1 << 15);
267 (cfg->io.pll_bypass << 15) | (1 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)); 545 dib0090_fw_write_reg(state, 0x21, PllCfg);
268 546
547 /* Set Reset Pll */
548 PllCfg &= ~(1 << 13);
549 dib0090_fw_write_reg(state, 0x21, PllCfg);
550
551 /*** Set new Pll configuration in bypass and reset state ***/
552 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
553 dib0090_fw_write_reg(state, 0x21, PllCfg);
554
555 /* Remove Reset Pll */
556 PllCfg |= (1 << 13);
557 dib0090_fw_write_reg(state, 0x21, PllCfg);
558
559 /*** Wait for PLL lock ***/
560 i = 100;
561 do {
562 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
563 if (v)
564 break;
565 } while (--i);
566
567 if (i == 0) {
568 dprintk("Pll: Unable to lock Pll");
569 return -EIO;
570 }
571
572 /* Finally Remove Bypass mode */
573 PllCfg &= ~(1 << 15);
574 dib0090_fw_write_reg(state, 0x21, PllCfg);
575 }
576
577 if (cfg->io.pll_bypass) {
578 PllCfg |= (cfg->io.pll_bypass << 15);
579 dib0090_fw_write_reg(state, 0x21, PllCfg);
580 }
581
582 return dib0090_fw_identify(fe);
269} 583}
270 584
271static int dib0090_wakeup(struct dvb_frontend *fe) 585static int dib0090_wakeup(struct dvb_frontend *fe)
@@ -273,6 +587,9 @@ static int dib0090_wakeup(struct dvb_frontend *fe)
273 struct dib0090_state *state = fe->tuner_priv; 587 struct dib0090_state *state = fe->tuner_priv;
274 if (state->config->sleep) 588 if (state->config->sleep)
275 state->config->sleep(fe, 0); 589 state->config->sleep(fe, 0);
590
591 /* enable dataTX in case we have been restarted in the wrong moment */
592 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
276 return 0; 593 return 0;
277} 594}
278 595
@@ -292,8 +609,75 @@ void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
292 else 609 else
293 dib0090_write_reg(state, 0x04, 1); 610 dib0090_write_reg(state, 0x04, 1);
294} 611}
612
295EXPORT_SYMBOL(dib0090_dcc_freq); 613EXPORT_SYMBOL(dib0090_dcc_freq);
296 614
615static const u16 bb_ramp_pwm_normal_socs[] = {
616 550, /* max BB gain in 10th of dB */
617 (1 << 9) | 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
618 440,
619 (4 << 9) | 0, /* BB_RAMP3 = 26dB */
620 (0 << 9) | 208, /* BB_RAMP4 */
621 (4 << 9) | 208, /* BB_RAMP5 = 29dB */
622 (0 << 9) | 440, /* BB_RAMP6 */
623};
624
625static const u16 rf_ramp_pwm_cband_7090[] = {
626 280, /* max RF gain in 10th of dB */
627 18, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
628 504, /* ramp_max = maximum X used on the ramp */
629 (29 << 10) | 364, /* RF_RAMP5, LNA 1 = 8dB */
630 (0 << 10) | 504, /* RF_RAMP6, LNA 1 */
631 (60 << 10) | 228, /* RF_RAMP7, LNA 2 = 7.7dB */
632 (0 << 10) | 364, /* RF_RAMP8, LNA 2 */
633 (34 << 10) | 109, /* GAIN_4_1, LNA 3 = 6.8dB */
634 (0 << 10) | 228, /* GAIN_4_2, LNA 3 */
635 (37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
636 (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
637};
638
639static const u16 rf_ramp_pwm_cband_8090[] = {
640 345, /* max RF gain in 10th of dB */
641 29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
642 1000, /* ramp_max = maximum X used on the ramp */
643 (35 << 10) | 772, /* RF_RAMP3, LNA 1 = 8dB */
644 (0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
645 (58 << 10) | 496, /* RF_RAMP5, LNA 2 = 9.5dB */
646 (0 << 10) | 772, /* RF_RAMP6, LNA 2 */
647 (27 << 10) | 200, /* RF_RAMP7, LNA 3 = 10.5dB */
648 (0 << 10) | 496, /* RF_RAMP8, LNA 3 */
649 (40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
650 (0 << 10) | 200, /* GAIN_4_2, LNA 4 */
651};
652
653static const u16 rf_ramp_pwm_uhf_7090[] = {
654 407, /* max RF gain in 10th of dB */
655 13, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
656 529, /* ramp_max = maximum X used on the ramp */
657 (23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
658 (0 << 10) | 176, /* RF_RAMP4, LNA 1 */
659 (63 << 10) | 400, /* RF_RAMP5, LNA 2 = 8dB */
660 (0 << 10) | 529, /* RF_RAMP6, LNA 2 */
661 (48 << 10) | 316, /* RF_RAMP7, LNA 3 = 6.8dB */
662 (0 << 10) | 400, /* RF_RAMP8, LNA 3 */
663 (29 << 10) | 176, /* GAIN_4_1, LNA 4 = 11.5dB */
664 (0 << 10) | 316, /* GAIN_4_2, LNA 4 */
665};
666
667static const u16 rf_ramp_pwm_uhf_8090[] = {
668 388, /* max RF gain in 10th of dB */
669 26, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
670 1008, /* ramp_max = maximum X used on the ramp */
671 (11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
672 (0 << 10) | 369, /* RF_RAMP4, LNA 1 */
673 (41 << 10) | 809, /* RF_RAMP5, LNA 2 = 8dB */
674 (0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
675 (27 << 10) | 659, /* RF_RAMP7, LNA 3 = 6dB */
676 (0 << 10) | 809, /* RF_RAMP8, LNA 3 */
677 (14 << 10) | 369, /* GAIN_4_1, LNA 4 = 11.5dB */
678 (0 << 10) | 659, /* GAIN_4_2, LNA 4 */
679};
680
297static const u16 rf_ramp_pwm_cband[] = { 681static const u16 rf_ramp_pwm_cband[] = {
298 0, /* max RF gain in 10th of dB */ 682 0, /* max RF gain in 10th of dB */
299 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */ 683 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
@@ -326,6 +710,16 @@ static const u16 rf_ramp_uhf[] = {
326 0, 0, 127, /* CBAND : 0.0 dB */ 710 0, 0, 127, /* CBAND : 0.0 dB */
327}; 711};
328 712
713static const u16 rf_ramp_cband_broadmatching[] = /* for p1G only */
714{
715 314, /* Calibrated at 200MHz order has been changed g4-g3-g2-g1 */
716 84, 314, 127, /* LNA1 */
717 80, 230, 255, /* LNA2 */
718 80, 150, 127, /* LNA3 It was measured 12dB, do not lock if 120 */
719 70, 70, 127, /* LNA4 */
720 0, 0, 127, /* CBAND */
721};
722
329static const u16 rf_ramp_cband[] = { 723static const u16 rf_ramp_cband[] = {
330 332, /* max RF gain in 10th of dB */ 724 332, /* max RF gain in 10th of dB */
331 132, 252, 127, /* LNA1, dB */ 725 132, 252, 127, /* LNA1, dB */
@@ -380,8 +774,8 @@ static const u16 bb_ramp_pwm_normal[] = {
380}; 774};
381 775
382struct slope { 776struct slope {
383 int16_t range; 777 s16 range;
384 int16_t slope; 778 s16 slope;
385}; 779};
386static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val) 780static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
387{ 781{
@@ -597,19 +991,39 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
597#endif 991#endif
598#ifdef CONFIG_BAND_CBAND 992#ifdef CONFIG_BAND_CBAND
599 if (state->current_band == BAND_CBAND) { 993 if (state->current_band == BAND_CBAND) {
600 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband); 994 if (state->identity.in_soc) {
601 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 995 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
996 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
997 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090);
998 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
999 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090);
1000 } else {
1001 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
1002 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1003 }
602 } else 1004 } else
603#endif 1005#endif
604#ifdef CONFIG_BAND_VHF 1006#ifdef CONFIG_BAND_VHF
605 if (state->current_band == BAND_VHF) { 1007 if (state->current_band == BAND_VHF) {
606 dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf); 1008 if (state->identity.in_soc) {
607 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 1009 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
1010 } else {
1011 dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
1012 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1013 }
608 } else 1014 } else
609#endif 1015#endif
610 { 1016 {
611 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf); 1017 if (state->identity.in_soc) {
612 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 1018 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1019 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_8090);
1020 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
1021 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_7090);
1022 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
1023 } else {
1024 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
1025 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1026 }
613 } 1027 }
614 1028
615 if (state->rf_ramp[0] != 0) 1029 if (state->rf_ramp[0] != 0)
@@ -617,11 +1031,21 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
617 else 1031 else
618 dib0090_write_reg(state, 0x32, (0 << 11)); 1032 dib0090_write_reg(state, 0x32, (0 << 11));
619 1033
1034 dib0090_write_reg(state, 0x04, 0x01);
620 dib0090_write_reg(state, 0x39, (1 << 10)); 1035 dib0090_write_reg(state, 0x39, (1 << 10));
621 } 1036 }
622} 1037}
1038
623EXPORT_SYMBOL(dib0090_pwm_gain_reset); 1039EXPORT_SYMBOL(dib0090_pwm_gain_reset);
624 1040
1041static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
1042{
1043 u16 adc_val = dib0090_read_reg(state, 0x1d);
1044 if (state->identity.in_soc)
1045 adc_val >>= 2;
1046 return adc_val;
1047}
1048
625int dib0090_gain_control(struct dvb_frontend *fe) 1049int dib0090_gain_control(struct dvb_frontend *fe)
626{ 1050{
627 struct dib0090_state *state = fe->tuner_priv; 1051 struct dib0090_state *state = fe->tuner_priv;
@@ -643,18 +1067,21 @@ int dib0090_gain_control(struct dvb_frontend *fe)
643 } else 1067 } else
644#endif 1068#endif
645#ifdef CONFIG_BAND_VHF 1069#ifdef CONFIG_BAND_VHF
646 if (state->current_band == BAND_VHF) { 1070 if (state->current_band == BAND_VHF && !state->identity.p1g) {
647 dib0090_set_rframp(state, rf_ramp_vhf); 1071 dib0090_set_rframp(state, rf_ramp_vhf);
648 dib0090_set_bbramp(state, bb_ramp_boost); 1072 dib0090_set_bbramp(state, bb_ramp_boost);
649 } else 1073 } else
650#endif 1074#endif
651#ifdef CONFIG_BAND_CBAND 1075#ifdef CONFIG_BAND_CBAND
652 if (state->current_band == BAND_CBAND) { 1076 if (state->current_band == BAND_CBAND && !state->identity.p1g) {
653 dib0090_set_rframp(state, rf_ramp_cband); 1077 dib0090_set_rframp(state, rf_ramp_cband);
654 dib0090_set_bbramp(state, bb_ramp_boost); 1078 dib0090_set_bbramp(state, bb_ramp_boost);
655 } else 1079 } else
656#endif 1080#endif
657 { 1081 if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) {
1082 dib0090_set_rframp(state, rf_ramp_cband_broadmatching);
1083 dib0090_set_bbramp(state, bb_ramp_boost);
1084 } else {
658 dib0090_set_rframp(state, rf_ramp_uhf); 1085 dib0090_set_rframp(state, rf_ramp_uhf);
659 dib0090_set_bbramp(state, bb_ramp_boost); 1086 dib0090_set_bbramp(state, bb_ramp_boost);
660 } 1087 }
@@ -669,17 +1096,25 @@ int dib0090_gain_control(struct dvb_frontend *fe)
669 1096
670 *tune_state = CT_AGC_STEP_0; 1097 *tune_state = CT_AGC_STEP_0;
671 } else if (!state->agc_freeze) { 1098 } else if (!state->agc_freeze) {
672 s16 wbd; 1099 s16 wbd = 0, i, cnt;
673 1100
674 int adc; 1101 int adc;
675 wbd_val = dib0090_read_reg(state, 0x1d); 1102 wbd_val = dib0090_get_slow_adc_val(state);
676 1103
677 /* read and calc the wbd power */ 1104 if (*tune_state == CT_AGC_STEP_0)
678 wbd = dib0090_wbd_to_db(state, wbd_val); 1105 cnt = 5;
1106 else
1107 cnt = 1;
1108
1109 for (i = 0; i < cnt; i++) {
1110 wbd_val = dib0090_get_slow_adc_val(state);
1111 wbd += dib0090_wbd_to_db(state, wbd_val);
1112 }
1113 wbd /= cnt;
679 wbd_error = state->wbd_target - wbd; 1114 wbd_error = state->wbd_target - wbd;
680 1115
681 if (*tune_state == CT_AGC_STEP_0) { 1116 if (*tune_state == CT_AGC_STEP_0) {
682 if (wbd_error < 0 && state->rf_gain_limit > 0) { 1117 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {
683#ifdef CONFIG_BAND_CBAND 1118#ifdef CONFIG_BAND_CBAND
684 /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */ 1119 /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
685 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; 1120 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
@@ -700,39 +1135,39 @@ int dib0090_gain_control(struct dvb_frontend *fe)
700 adc_error = (s16) (((s32) ADC_TARGET) - adc); 1135 adc_error = (s16) (((s32) ADC_TARGET) - adc);
701#ifdef CONFIG_STANDARD_DAB 1136#ifdef CONFIG_STANDARD_DAB
702 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) 1137 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
703 adc_error += 130; 1138 adc_error -= 10;
704#endif 1139#endif
705#ifdef CONFIG_STANDARD_DVBT 1140#ifdef CONFIG_STANDARD_DVBT
706 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT && 1141 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
707 (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16)) 1142 (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
708 adc_error += 60; 1143 adc_error += 60;
709#endif 1144#endif
710#ifdef CONFIG_SYS_ISDBT 1145#ifdef CONFIG_SYS_ISDBT
711 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count > 1146 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
712 0) 1147 0)
713 && 1148 &&
714 ((state->fe->dtv_property_cache.layer[0].modulation == 1149 ((state->fe->dtv_property_cache.layer[0].modulation ==
715 QAM_64) 1150 QAM_64)
716 || (state->fe->dtv_property_cache.layer[0]. 1151 || (state->fe->dtv_property_cache.
717 modulation == QAM_16))) 1152 layer[0].modulation == QAM_16)))
718 || 1153 ||
719 ((state->fe->dtv_property_cache.layer[1].segment_count > 1154 ((state->fe->dtv_property_cache.layer[1].segment_count >
720 0) 1155 0)
721 && 1156 &&
722 ((state->fe->dtv_property_cache.layer[1].modulation == 1157 ((state->fe->dtv_property_cache.layer[1].modulation ==
723 QAM_64) 1158 QAM_64)
724 || (state->fe->dtv_property_cache.layer[1]. 1159 || (state->fe->dtv_property_cache.
725 modulation == QAM_16))) 1160 layer[1].modulation == QAM_16)))
726 || 1161 ||
727 ((state->fe->dtv_property_cache.layer[2].segment_count > 1162 ((state->fe->dtv_property_cache.layer[2].segment_count >
728 0) 1163 0)
729 && 1164 &&
730 ((state->fe->dtv_property_cache.layer[2].modulation == 1165 ((state->fe->dtv_property_cache.layer[2].modulation ==
731 QAM_64) 1166 QAM_64)
732 || (state->fe->dtv_property_cache.layer[2]. 1167 || (state->fe->dtv_property_cache.
733 modulation == QAM_16))) 1168 layer[2].modulation == QAM_16)))
734 ) 1169 )
735 ) 1170 )
736 adc_error += 60; 1171 adc_error += 60;
737#endif 1172#endif
738 1173
@@ -760,9 +1195,9 @@ int dib0090_gain_control(struct dvb_frontend *fe)
760 } 1195 }
761#ifdef DEBUG_AGC 1196#ifdef DEBUG_AGC
762 dprintk 1197 dprintk
763 ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm", 1198 ("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
764 (u32) fe->id, (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val, 1199 (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
765 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); 1200 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
766#endif 1201#endif
767 } 1202 }
768 1203
@@ -771,6 +1206,7 @@ int dib0090_gain_control(struct dvb_frontend *fe)
771 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); 1206 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
772 return ret; 1207 return ret;
773} 1208}
1209
774EXPORT_SYMBOL(dib0090_gain_control); 1210EXPORT_SYMBOL(dib0090_gain_control);
775 1211
776void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt) 1212void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
@@ -785,13 +1221,47 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
785 if (rflt) 1221 if (rflt)
786 *rflt = (state->rf_lt_def >> 10) & 0x7; 1222 *rflt = (state->rf_lt_def >> 10) & 0x7;
787} 1223}
1224
788EXPORT_SYMBOL(dib0090_get_current_gain); 1225EXPORT_SYMBOL(dib0090_get_current_gain);
789 1226
790u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner) 1227u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
791{ 1228{
792 struct dib0090_state *st = tuner->tuner_priv; 1229 struct dib0090_state *state = fe->tuner_priv;
793 return st->wbd_offset; 1230 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
1231 s32 current_temp = state->temperature;
1232 s32 wbd_thot, wbd_tcold;
1233 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1234
1235 while (f_MHz > wbd->max_freq)
1236 wbd++;
1237
1238 dprintk("using wbd-table-entry with max freq %d", wbd->max_freq);
1239
1240 if (current_temp < 0)
1241 current_temp = 0;
1242 if (current_temp > 128)
1243 current_temp = 128;
1244
1245 state->wbdmux &= ~(7 << 13);
1246 if (wbd->wbd_gain != 0)
1247 state->wbdmux |= (wbd->wbd_gain << 13);
1248 else
1249 state->wbdmux |= (4 << 13);
1250
1251 dib0090_write_reg(state, 0x10, state->wbdmux);
1252
1253 wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
1254 wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
1255
1256 wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
1257
1258 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);
1259 dprintk("wbd-target: %d dB", (u32) state->wbd_target);
1260 dprintk("wbd offset applied is %d", wbd_tcold);
1261
1262 return state->wbd_offset + wbd_tcold;
794} 1263}
1264
795EXPORT_SYMBOL(dib0090_get_wbd_offset); 1265EXPORT_SYMBOL(dib0090_get_wbd_offset);
796 1266
797static const u16 dib0090_defaults[] = { 1267static const u16 dib0090_defaults[] = {
@@ -801,7 +1271,7 @@ static const u16 dib0090_defaults[] = {
801 0x99a0, 1271 0x99a0,
802 0x6008, 1272 0x6008,
803 0x0000, 1273 0x0000,
804 0x8acb, 1274 0x8bcb,
805 0x0000, 1275 0x0000,
806 0x0405, 1276 0x0405,
807 0x0000, 1277 0x0000,
@@ -829,8 +1299,6 @@ static const u16 dib0090_defaults[] = {
829 1, 0x39, 1299 1, 0x39,
830 0x0000, 1300 0x0000,
831 1301
832 1, 0x1b,
833 EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL,
834 2, 0x1e, 1302 2, 0x1e,
835 0x07FF, 1303 0x07FF,
836 0x0007, 1304 0x0007,
@@ -844,50 +1312,125 @@ static const u16 dib0090_defaults[] = {
844 0 1312 0
845}; 1313};
846 1314
847static int dib0090_reset(struct dvb_frontend *fe) 1315static const u16 dib0090_p1g_additionnal_defaults[] = {
848{ 1316 1, 0x05,
849 struct dib0090_state *state = fe->tuner_priv; 1317 0xabcd,
850 u16 l, r, *n;
851 1318
852 dib0090_reset_digital(fe, state->config); 1319 1, 0x11,
853 state->revision = dib0090_identify(fe); 1320 0x00b4,
854 1321
855 /* Revision definition */ 1322 1, 0x1c,
856 if (state->revision == 0xff) 1323 0xfffd,
857 return -EINVAL;
858#ifdef EFUSE
859 else if ((state->revision & 0x1f) >= 3) /* Update the efuse : Only available for KROSUS > P1C */
860 dib0090_set_EFUSE(state);
861#endif
862 1324
863#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT 1325 1, 0x40,
864 if (!(state->revision & 0x1)) /* it is P1B - reset is already done */ 1326 0x108,
865 return 0; 1327 0
866#endif 1328};
1329
1330static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)
1331{
1332 u16 l, r;
867 1333
868 /* Upload the default values */
869 n = (u16 *) dib0090_defaults;
870 l = pgm_read_word(n++); 1334 l = pgm_read_word(n++);
871 while (l) { 1335 while (l) {
872 r = pgm_read_word(n++); 1336 r = pgm_read_word(n++);
873 do { 1337 do {
874 /* DEBUG_TUNER */
875 /* dprintk("%d, %d, %d", l, r, pgm_read_word(n)); */
876 dib0090_write_reg(state, r, pgm_read_word(n++)); 1338 dib0090_write_reg(state, r, pgm_read_word(n++));
877 r++; 1339 r++;
878 } while (--l); 1340 } while (--l);
879 l = pgm_read_word(n++); 1341 l = pgm_read_word(n++);
880 } 1342 }
1343}
1344
1345#define CAP_VALUE_MIN (u8) 9
1346#define CAP_VALUE_MAX (u8) 40
1347#define HR_MIN (u8) 25
1348#define HR_MAX (u8) 40
1349#define POLY_MIN (u8) 0
1350#define POLY_MAX (u8) 8
1351
1352void dib0090_set_EFUSE(struct dib0090_state *state)
1353{
1354 u8 c, h, n;
1355 u16 e2, e4;
1356 u16 cal;
1357
1358 e2 = dib0090_read_reg(state, 0x26);
1359 e4 = dib0090_read_reg(state, 0x28);
1360
1361 if ((state->identity.version == P1D_E_F) ||
1362 (state->identity.version == P1G) || (e2 == 0xffff)) {
1363
1364 dib0090_write_reg(state, 0x22, 0x10);
1365 cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;
1366
1367 if ((cal < 670) || (cal == 1023))
1368 cal = 850;
1369 n = 165 - ((cal * 10)>>6) ;
1370 e2 = e4 = (3<<12) | (34<<6) | (n);
1371 }
1372
1373 if (e2 != e4)
1374 e2 &= e4; /* Remove the redundancy */
1375
1376 if (e2 != 0xffff) {
1377 c = e2 & 0x3f;
1378 n = (e2 >> 12) & 0xf;
1379 h = (e2 >> 6) & 0x3f;
1380
1381 if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
1382 c = 32;
1383 if ((h >= HR_MAX) || (h <= HR_MIN))
1384 h = 34;
1385 if ((n >= POLY_MAX) || (n <= POLY_MIN))
1386 n = 3;
1387
1388 dib0090_write_reg(state, 0x13, (h << 10)) ;
1389 e2 = (n<<11) | ((h>>2)<<6) | (c);
1390 dib0090_write_reg(state, 0x2, e2) ; /* Load the BB_2 */
1391 }
1392}
1393
1394static int dib0090_reset(struct dvb_frontend *fe)
1395{
1396 struct dib0090_state *state = fe->tuner_priv;
1397
1398 dib0090_reset_digital(fe, state->config);
1399 if (dib0090_identify(fe) < 0)
1400 return -EIO;
1401
1402#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
1403 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */
1404 return 0;
1405#endif
1406
1407 if (!state->identity.in_soc) {
1408 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
1409 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1410 else
1411 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1412 }
1413
1414 dib0090_set_default_config(state, dib0090_defaults);
1415
1416 if (state->identity.in_soc)
1417 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
1418
1419 if (state->identity.p1g)
1420 dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
1421
1422 /* Update the efuse : Only available for KROSUS > P1C and SOC as well*/
1423 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc))
1424 dib0090_set_EFUSE(state);
881 1425
882 /* Congigure in function of the crystal */ 1426 /* Congigure in function of the crystal */
883 if (state->config->io.clock_khz >= 24000) 1427 if (state->config->io.clock_khz >= 24000)
884 l = 1; 1428 dib0090_write_reg(state, 0x14, 1);
885 else 1429 else
886 l = 2; 1430 dib0090_write_reg(state, 0x14, 2);
887 dib0090_write_reg(state, 0x14, l);
888 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); 1431 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
889 1432
890 state->reset = 3; /* enable iq-offset-calibration and wbd-calibration when tuning next time */ 1433 state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
891 1434
892 return 0; 1435 return 0;
893} 1436}
@@ -927,11 +1470,11 @@ static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_st
927} 1470}
928 1471
929struct dc_calibration { 1472struct dc_calibration {
930 uint8_t addr; 1473 u8 addr;
931 uint8_t offset; 1474 u8 offset;
932 uint8_t pga:1; 1475 u8 pga:1;
933 uint16_t bb1; 1476 u16 bb1;
934 uint8_t i:1; 1477 u8 i:1;
935}; 1478};
936 1479
937static const struct dc_calibration dc_table[] = { 1480static const struct dc_calibration dc_table[] = {
@@ -944,6 +1487,17 @@ static const struct dc_calibration dc_table[] = {
944 {0}, 1487 {0},
945}; 1488};
946 1489
1490static const struct dc_calibration dc_p1g_table[] = {
1491 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1492 /* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
1493 {0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1},
1494 {0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0},
1495 /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
1496 {0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1},
1497 {0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0},
1498 {0},
1499};
1500
947static void dib0090_set_trim(struct dib0090_state *state) 1501static void dib0090_set_trim(struct dib0090_state *state)
948{ 1502{
949 u16 *val; 1503 u16 *val;
@@ -962,41 +1516,45 @@ static void dib0090_set_trim(struct dib0090_state *state)
962static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) 1516static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
963{ 1517{
964 int ret = 0; 1518 int ret = 0;
1519 u16 reg;
965 1520
966 switch (*tune_state) { 1521 switch (*tune_state) {
967
968 case CT_TUNER_START: 1522 case CT_TUNER_START:
969 /* init */ 1523 dprintk("Start DC offset calibration");
970 dprintk("Internal DC calibration");
971
972 /* the LNA is off */
973 dib0090_write_reg(state, 0x24, 0x02ed);
974 1524
975 /* force vcm2 = 0.8V */ 1525 /* force vcm2 = 0.8V */
976 state->bb6 = 0; 1526 state->bb6 = 0;
977 state->bb7 = 0x040d; 1527 state->bb7 = 0x040d;
978 1528
1529 /* the LNA AND LO are off */
1530 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
1531 dib0090_write_reg(state, 0x24, reg);
1532
1533 state->wbdmux = dib0090_read_reg(state, 0x10);
1534 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);
1535 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
1536
979 state->dc = dc_table; 1537 state->dc = dc_table;
980 1538
1539 if (state->identity.p1g)
1540 state->dc = dc_p1g_table;
981 *tune_state = CT_TUNER_STEP_0; 1541 *tune_state = CT_TUNER_STEP_0;
982 1542
983 /* fall through */ 1543 /* fall through */
984 1544
985 case CT_TUNER_STEP_0: 1545 case CT_TUNER_STEP_0:
1546 dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q");
986 dib0090_write_reg(state, 0x01, state->dc->bb1); 1547 dib0090_write_reg(state, 0x01, state->dc->bb1);
987 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); 1548 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
988 1549
989 state->step = 0; 1550 state->step = 0;
990
991 state->min_adc_diff = 1023; 1551 state->min_adc_diff = 1023;
992
993 *tune_state = CT_TUNER_STEP_1; 1552 *tune_state = CT_TUNER_STEP_1;
994 ret = 50; 1553 ret = 50;
995 break; 1554 break;
996 1555
997 case CT_TUNER_STEP_1: 1556 case CT_TUNER_STEP_1:
998 dib0090_set_trim(state); 1557 dib0090_set_trim(state);
999
1000 *tune_state = CT_TUNER_STEP_2; 1558 *tune_state = CT_TUNER_STEP_2;
1001 break; 1559 break;
1002 1560
@@ -1007,7 +1565,13 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1007 break; 1565 break;
1008 1566
1009 case CT_TUNER_STEP_5: /* found an offset */ 1567 case CT_TUNER_STEP_5: /* found an offset */
1010 dprintk("FE%d: IQC read=%d, current=%x", state->fe->id, (u32) state->adc_diff, state->step); 1568 dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step);
1569 if (state->step == 0 && state->adc_diff < 0) {
1570 state->min_adc_diff = -1023;
1571 dprintk("Change of sign of the minimum adc diff");
1572 }
1573
1574 dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state->step);
1011 1575
1012 /* first turn for this frequency */ 1576 /* first turn for this frequency */
1013 if (state->step == 0) { 1577 if (state->step == 0) {
@@ -1017,20 +1581,21 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1017 state->step = 0x10; 1581 state->step = 0x10;
1018 } 1582 }
1019 1583
1020 state->adc_diff = ABS(state->adc_diff); 1584 /* Look for a change of Sign in the Adc_diff.min_adc_diff is used to STORE the setp N-1 */
1021 1585 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
1022 if (state->adc_diff < state->min_adc_diff && steps(state->step) < 15) { /* stop search when the delta to 0 is increasing */ 1586 /* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
1023 state->step++; 1587 state->step++;
1024 state->min_adc_diff = state->adc_diff; 1588 state->min_adc_diff = state->adc_diff;
1025 *tune_state = CT_TUNER_STEP_1; 1589 *tune_state = CT_TUNER_STEP_1;
1026 } else { 1590 } else {
1027
1028 /* the minimum was what we have seen in the step before */ 1591 /* the minimum was what we have seen in the step before */
1029 state->step--; 1592 if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) {
1030 dib0090_set_trim(state); 1593 dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_diff);
1594 state->step--;
1595 }
1031 1596
1032 dprintk("FE%d: BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->fe->id, state->dc->addr, state->adc_diff, 1597 dib0090_set_trim(state);
1033 state->step); 1598 dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->step);
1034 1599
1035 state->dc++; 1600 state->dc++;
1036 if (state->dc->addr == 0) /* done */ 1601 if (state->dc->addr == 0) /* done */
@@ -1045,7 +1610,7 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1045 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); 1610 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
1046 dib0090_write_reg(state, 0x1f, 0x7); 1611 dib0090_write_reg(state, 0x1f, 0x7);
1047 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ 1612 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
1048 state->reset &= ~0x1; 1613 state->calibrate &= ~DC_CAL;
1049 default: 1614 default:
1050 break; 1615 break;
1051 } 1616 }
@@ -1054,21 +1619,43 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1054 1619
1055static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) 1620static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1056{ 1621{
1622 u8 wbd_gain;
1623 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1624
1057 switch (*tune_state) { 1625 switch (*tune_state) {
1058 case CT_TUNER_START: 1626 case CT_TUNER_START:
1059 /* WBD-mode=log, Bias=2, Gain=6, Testmode=1, en=1, WBDMUX=1 */ 1627 while (state->current_rf / 1000 > wbd->max_freq)
1060 dib0090_write_reg(state, 0x10, 0xdb09 | (1 << 10)); 1628 wbd++;
1061 dib0090_write_reg(state, 0x24, EN_UHF & 0x0fff); 1629 if (wbd->wbd_gain != 0)
1630 wbd_gain = wbd->wbd_gain;
1631 else {
1632 wbd_gain = 4;
1633#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
1634 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))
1635 wbd_gain = 2;
1636#endif
1637 }
1638
1639 if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */
1640 *tune_state = CT_TUNER_START;
1641 state->calibrate &= ~WBD_CAL;
1642 return 0;
1643 }
1644
1645 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));
1062 1646
1647 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));
1063 *tune_state = CT_TUNER_STEP_0; 1648 *tune_state = CT_TUNER_STEP_0;
1649 state->wbd_calibration_gain = wbd_gain;
1064 return 90; /* wait for the WBDMUX to switch and for the ADC to sample */ 1650 return 90; /* wait for the WBDMUX to switch and for the ADC to sample */
1651
1065 case CT_TUNER_STEP_0: 1652 case CT_TUNER_STEP_0:
1066 state->wbd_offset = dib0090_read_reg(state, 0x1d); 1653 state->wbd_offset = dib0090_get_slow_adc_val(state);
1067 dprintk("WBD calibration offset = %d", state->wbd_offset); 1654 dprintk("WBD calibration offset = %d", state->wbd_offset);
1068
1069 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ 1655 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
1070 state->reset &= ~0x2; 1656 state->calibrate &= ~WBD_CAL;
1071 break; 1657 break;
1658
1072 default: 1659 default:
1073 break; 1660 break;
1074 } 1661 }
@@ -1092,6 +1679,15 @@ static void dib0090_set_bandwidth(struct dib0090_state *state)
1092 state->bb_1_def |= tmp; 1679 state->bb_1_def |= tmp;
1093 1680
1094 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ 1681 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
1682
1683 dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
1684 dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
1685 if (state->identity.in_soc) {
1686 dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
1687 } else {
1688 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
1689 dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
1690 }
1095} 1691}
1096 1692
1097static const struct dib0090_pll dib0090_pll_table[] = { 1693static const struct dib0090_pll dib0090_pll_table[] = {
@@ -1180,6 +1776,255 @@ static const struct dib0090_tuning dib0090_tuning_table[] = {
1180#endif 1776#endif
1181}; 1777};
1182 1778
1779static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
1780#ifdef CONFIG_BAND_CBAND
1781 {170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB},
1782#endif
1783#ifdef CONFIG_BAND_VHF
1784 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1785 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1786 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF},
1787#endif
1788#ifdef CONFIG_BAND_UHF
1789 {510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1790 {540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1791 {600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1792 {630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1793 {680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1794 {720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1795 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1796#endif
1797#ifdef CONFIG_BAND_LBAND
1798 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1799 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1800 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1801#endif
1802#ifdef CONFIG_BAND_SBAND
1803 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1804 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1805#endif
1806};
1807
1808static const struct dib0090_pll dib0090_p1g_pll_table[] = {
1809#ifdef CONFIG_BAND_CBAND
1810 {57000, 0, 11, 48, 6},
1811 {70000, 1, 11, 48, 6},
1812 {86000, 0, 10, 32, 4},
1813 {105000, 1, 10, 32, 4},
1814 {115000, 0, 9, 24, 6},
1815 {140000, 1, 9, 24, 6},
1816 {170000, 0, 8, 16, 4},
1817#endif
1818#ifdef CONFIG_BAND_VHF
1819 {200000, 1, 8, 16, 4},
1820 {230000, 0, 7, 12, 6},
1821 {280000, 1, 7, 12, 6},
1822 {340000, 0, 6, 8, 4},
1823 {380000, 1, 6, 8, 4},
1824 {455000, 0, 5, 6, 6},
1825#endif
1826#ifdef CONFIG_BAND_UHF
1827 {580000, 1, 5, 6, 6},
1828 {680000, 0, 4, 4, 4},
1829 {860000, 1, 4, 4, 4},
1830#endif
1831#ifdef CONFIG_BAND_LBAND
1832 {1800000, 1, 2, 2, 4},
1833#endif
1834#ifdef CONFIG_BAND_SBAND
1835 {2900000, 0, 1, 1, 6},
1836#endif
1837};
1838
1839static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
1840#ifdef CONFIG_BAND_CBAND
1841 {184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
1842 {227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
1843 {380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB},
1844#endif
1845#ifdef CONFIG_BAND_UHF
1846 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1847 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1848 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1849 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1850 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1851 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF},
1852#endif
1853#ifdef CONFIG_BAND_LBAND
1854 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1855 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1856 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD},
1857#endif
1858#ifdef CONFIG_BAND_SBAND
1859 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD},
1860 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD},
1861#endif
1862};
1863
1864static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
1865#ifdef CONFIG_BAND_CBAND
1866 {300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1867 {380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1868 {570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1869 {858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1870#endif
1871};
1872
1873static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1874{
1875 int ret = 0;
1876 u16 lo4 = 0xe900;
1877
1878 s16 adc_target;
1879 u16 adc;
1880 s8 step_sign;
1881 u8 force_soft_search = 0;
1882
1883 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1884 force_soft_search = 1;
1885
1886 if (*tune_state == CT_TUNER_START) {
1887 dprintk("Start Captrim search : %s", (force_soft_search == 1) ? "FORCE SOFT SEARCH" : "AUTO");
1888 dib0090_write_reg(state, 0x10, 0x2B1);
1889 dib0090_write_reg(state, 0x1e, 0x0032);
1890
1891 if (!state->tuner_is_tuned) {
1892 /* prepare a complete captrim */
1893 if (!state->identity.p1g || force_soft_search)
1894 state->step = state->captrim = state->fcaptrim = 64;
1895
1896 state->current_rf = state->rf_request;
1897 } else { /* we are already tuned to this frequency - the configuration is correct */
1898 if (!state->identity.p1g || force_soft_search) {
1899 /* do a minimal captrim even if the frequency has not changed */
1900 state->step = 4;
1901 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
1902 }
1903 }
1904 state->adc_diff = 3000;
1905 *tune_state = CT_TUNER_STEP_0;
1906
1907 } else if (*tune_state == CT_TUNER_STEP_0) {
1908 if (state->identity.p1g && !force_soft_search) {
1909 u8 ratio = 31;
1910
1911 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
1912 dib0090_read_reg(state, 0x40);
1913 ret = 50;
1914 } else {
1915 state->step /= 2;
1916 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
1917
1918 if (state->identity.in_soc)
1919 ret = 25;
1920 }
1921 *tune_state = CT_TUNER_STEP_1;
1922
1923 } else if (*tune_state == CT_TUNER_STEP_1) {
1924 if (state->identity.p1g && !force_soft_search) {
1925 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
1926 dib0090_read_reg(state, 0x40);
1927
1928 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
1929 dprintk("***Final Captrim= 0x%x", state->fcaptrim);
1930 *tune_state = CT_TUNER_STEP_3;
1931
1932 } else {
1933 /* MERGE for all krosus before P1G */
1934 adc = dib0090_get_slow_adc_val(state);
1935 dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024);
1936
1937 if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */
1938 adc_target = 200;
1939 } else
1940 adc_target = 400;
1941
1942 if (adc >= adc_target) {
1943 adc -= adc_target;
1944 step_sign = -1;
1945 } else {
1946 adc = adc_target - adc;
1947 step_sign = 1;
1948 }
1949
1950 if (adc < state->adc_diff) {
1951 dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
1952 state->adc_diff = adc;
1953 state->fcaptrim = state->captrim;
1954 }
1955
1956 state->captrim += step_sign * state->step;
1957 if (state->step >= 1)
1958 *tune_state = CT_TUNER_STEP_0;
1959 else
1960 *tune_state = CT_TUNER_STEP_2;
1961
1962 ret = 25;
1963 }
1964 } else if (*tune_state == CT_TUNER_STEP_2) { /* this step is only used by krosus < P1G */
1965 /*write the final cptrim config */
1966 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
1967
1968 *tune_state = CT_TUNER_STEP_3;
1969
1970 } else if (*tune_state == CT_TUNER_STEP_3) {
1971 state->calibrate &= ~CAPTRIM_CAL;
1972 *tune_state = CT_TUNER_STEP_0;
1973 }
1974
1975 return ret;
1976}
1977
1978static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1979{
1980 int ret = 15;
1981 s16 val;
1982
1983 switch (*tune_state) {
1984 case CT_TUNER_START:
1985 state->wbdmux = dib0090_read_reg(state, 0x10);
1986 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));
1987
1988 state->bias = dib0090_read_reg(state, 0x13);
1989 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));
1990
1991 *tune_state = CT_TUNER_STEP_0;
1992 /* wait for the WBDMUX to switch and for the ADC to sample */
1993 break;
1994
1995 case CT_TUNER_STEP_0:
1996 state->adc_diff = dib0090_get_slow_adc_val(state);
1997 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));
1998 *tune_state = CT_TUNER_STEP_1;
1999 break;
2000
2001 case CT_TUNER_STEP_1:
2002 val = dib0090_get_slow_adc_val(state);
2003 state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;
2004
2005 dprintk("temperature: %d C", state->temperature - 30);
2006
2007 *tune_state = CT_TUNER_STEP_2;
2008 break;
2009
2010 case CT_TUNER_STEP_2:
2011 dib0090_write_reg(state, 0x13, state->bias);
2012 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
2013
2014 *tune_state = CT_TUNER_START;
2015 state->calibrate &= ~TEMP_CAL;
2016 if (state->config->analog_output == 0)
2017 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2018
2019 break;
2020
2021 default:
2022 ret = 0;
2023 break;
2024 }
2025 return ret;
2026}
2027
1183#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */ 2028#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
1184static int dib0090_tune(struct dvb_frontend *fe) 2029static int dib0090_tune(struct dvb_frontend *fe)
1185{ 2030{
@@ -1188,87 +2033,131 @@ static int dib0090_tune(struct dvb_frontend *fe)
1188 const struct dib0090_pll *pll = state->current_pll_table_index; 2033 const struct dib0090_pll *pll = state->current_pll_table_index;
1189 enum frontend_tune_state *tune_state = &state->tune_state; 2034 enum frontend_tune_state *tune_state = &state->tune_state;
1190 2035
1191 u32 rf; 2036 u16 lo5, lo6, Den, tmp;
1192 u16 lo4 = 0xe900, lo5, lo6, Den;
1193 u32 FBDiv, Rest, FREF, VCOF_kHz = 0; 2037 u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
1194 u16 tmp, adc;
1195 int8_t step_sign;
1196 int ret = 10; /* 1ms is the default delay most of the time */ 2038 int ret = 10; /* 1ms is the default delay most of the time */
1197 u8 c, i; 2039 u8 c, i;
1198 2040
1199 state->current_band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000); 2041 /************************* VCO ***************************/
1200 rf = fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
1201 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->freq_offset_khz_vhf);
1202 /* in any case we first need to do a reset if needed */
1203 if (state->reset & 0x1)
1204 return dib0090_dc_offset_calibration(state, tune_state);
1205 else if (state->reset & 0x2)
1206 return dib0090_wbd_calibration(state, tune_state);
1207
1208 /************************* VCO ***************************/
1209 /* Default values for FG */ 2042 /* Default values for FG */
1210 /* from these are needed : */ 2043 /* from these are needed : */
1211 /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */ 2044 /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */
1212 2045
1213#ifdef CONFIG_SYS_ISDBT 2046 /* in any case we first need to do a calibration if needed */
1214 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1) 2047 if (*tune_state == CT_TUNER_START) {
1215 rf += 850; 2048 /* deactivate DataTX before some calibrations */
1216#endif 2049 if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
2050 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
2051 else
2052 /* Activate DataTX in case a calibration has been done before */
2053 if (state->config->analog_output == 0)
2054 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2055 }
1217 2056
1218 if (state->current_rf != rf) { 2057 if (state->calibrate & DC_CAL)
1219 state->tuner_is_tuned = 0; 2058 return dib0090_dc_offset_calibration(state, tune_state);
2059 else if (state->calibrate & WBD_CAL) {
2060 if (state->current_rf == 0)
2061 state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
2062 return dib0090_wbd_calibration(state, tune_state);
2063 } else if (state->calibrate & TEMP_CAL)
2064 return dib0090_get_temperature(state, tune_state);
2065 else if (state->calibrate & CAPTRIM_CAL)
2066 return dib0090_captrim_search(state, tune_state);
1220 2067
1221 tune = dib0090_tuning_table; 2068 if (*tune_state == CT_TUNER_START) {
2069 /* if soc and AGC pwm control, disengage mux to be able to R/W access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, otherwise, SOC SERPAR error when accessing to 0x01 */
2070 if (state->config->use_pwm_agc && state->identity.in_soc) {
2071 tmp = dib0090_read_reg(state, 0x39);
2072 if ((tmp >> 10) & 0x1)
2073 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));
2074 }
1222 2075
1223 tmp = (state->revision >> 5) & 0x7; 2076 state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
1224 if (tmp == 0x4 || tmp == 0x7) { 2077 state->rf_request =
1225 /* CBAND tuner version for VHF */ 2078 state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
1226 if (state->current_band == BAND_FM || state->current_band == BAND_VHF) { 2079 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->
1227 /* Force CBAND */ 2080 freq_offset_khz_vhf);
1228 state->current_band = BAND_CBAND; 2081
1229 tune = dib0090_tuning_table_fm_vhf_on_cband; 2082 /* in ISDB-T 1seg we shift tuning frequency */
2083 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1
2084 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {
2085 const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;
2086 u8 found_offset = 0;
2087 u32 margin_khz = 100;
2088
2089 if (LUT_offset != NULL) {
2090 while (LUT_offset->RF_freq != 0xffff) {
2091 if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))
2092 && (state->rf_request < (LUT_offset->RF_freq + margin_khz)))
2093 && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {
2094 state->rf_request += LUT_offset->offset_khz;
2095 found_offset = 1;
2096 break;
2097 }
2098 LUT_offset++;
2099 }
1230 } 2100 }
2101
2102 if (found_offset == 0)
2103 state->rf_request += 400;
1231 } 2104 }
2105 if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) {
2106 state->tuner_is_tuned = 0;
2107 state->current_rf = 0;
2108 state->current_standard = 0;
1232 2109
1233 pll = dib0090_pll_table; 2110 tune = dib0090_tuning_table;
1234 /* Look for the interval */ 2111 if (state->identity.p1g)
1235 while (rf > tune->max_freq) 2112 tune = dib0090_p1g_tuning_table;
1236 tune++;
1237 while (rf > pll->max_freq)
1238 pll++;
1239 state->current_tune_table_index = tune;
1240 state->current_pll_table_index = pll;
1241 }
1242 2113
1243 if (*tune_state == CT_TUNER_START) { 2114 tmp = (state->identity.version >> 5) & 0x7;
1244 2115
1245 if (state->tuner_is_tuned == 0) 2116 if (state->identity.in_soc) {
1246 state->current_rf = 0; 2117 if (state->config->force_cband_input) { /* Use the CBAND input for all band */
2118 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
2119 || state->current_band & BAND_UHF) {
2120 state->current_band = BAND_CBAND;
2121 tune = dib0090_tuning_table_cband_7090;
2122 }
2123 } else { /* Use the CBAND input for all band under UHF */
2124 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
2125 state->current_band = BAND_CBAND;
2126 tune = dib0090_tuning_table_cband_7090;
2127 }
2128 }
2129 } else
2130 if (tmp == 0x4 || tmp == 0x7) {
2131 /* CBAND tuner version for VHF */
2132 if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) {
2133 state->current_band = BAND_CBAND; /* Force CBAND */
2134
2135 tune = dib0090_tuning_table_fm_vhf_on_cband;
2136 if (state->identity.p1g)
2137 tune = dib0090_p1g_tuning_table_fm_vhf_on_cband;
2138 }
2139 }
1247 2140
1248 if (state->current_rf != rf) { 2141 pll = dib0090_pll_table;
2142 if (state->identity.p1g)
2143 pll = dib0090_p1g_pll_table;
1249 2144
1250 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); 2145 /* Look for the interval */
2146 while (state->rf_request > tune->max_freq)
2147 tune++;
2148 while (state->rf_request > pll->max_freq)
2149 pll++;
1251 2150
1252 /* external loop filter, otherwise: 2151 state->current_tune_table_index = tune;
1253 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4; 2152 state->current_pll_table_index = pll;
1254 * lo6 = 0x0e34 */
1255 if (pll->vco_band)
1256 lo5 = 0x049e;
1257 else if (state->config->analog_output)
1258 lo5 = 0x041d;
1259 else
1260 lo5 = 0x041c;
1261
1262 lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
1263 2153
1264 if (!state->config->io.pll_int_loop_filt) 2154 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
1265 lo6 = 0xff28;
1266 else
1267 lo6 = (state->config->io.pll_int_loop_filt << 3);
1268 2155
1269 VCOF_kHz = (pll->hfdiv * rf) * 2; 2156 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
1270 2157
1271 FREF = state->config->io.clock_khz; 2158 FREF = state->config->io.clock_khz;
2159 if (state->config->fref_clock_ratio != 0)
2160 FREF /= state->config->fref_clock_ratio;
1272 2161
1273 FBDiv = (VCOF_kHz / pll->topresc / FREF); 2162 FBDiv = (VCOF_kHz / pll->topresc / FREF);
1274 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; 2163 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF;
@@ -1283,144 +2172,132 @@ static int dib0090_tune(struct dvb_frontend *fe)
1283 } else if (Rest > (FREF - 2 * LPF)) 2172 } else if (Rest > (FREF - 2 * LPF))
1284 Rest = FREF - 2 * LPF; 2173 Rest = FREF - 2 * LPF;
1285 Rest = (Rest * 6528) / (FREF / 10); 2174 Rest = (Rest * 6528) / (FREF / 10);
2175 state->rest = Rest;
1286 2176
1287 Den = 1; 2177 /* external loop filter, otherwise:
2178 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
2179 * lo6 = 0x0e34 */
2180
2181 if (Rest == 0) {
2182 if (pll->vco_band)
2183 lo5 = 0x049f;
2184 else
2185 lo5 = 0x041f;
2186 } else {
2187 if (pll->vco_band)
2188 lo5 = 0x049e;
2189 else if (state->config->analog_output)
2190 lo5 = 0x041d;
2191 else
2192 lo5 = 0x041c;
2193 }
2194
2195 if (state->identity.p1g) { /* Bias is done automatically in P1G */
2196 if (state->identity.in_soc) {
2197 if (state->identity.version == SOC_8090_P1G_11R1)
2198 lo5 = 0x46f;
2199 else
2200 lo5 = 0x42f;
2201 } else
2202 lo5 = 0x42c;
2203 }
2204
2205 lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
1288 2206
1289 dprintk(" ***** ******* Rest value = %d", Rest); 2207 if (!state->config->io.pll_int_loop_filt) {
2208 if (state->identity.in_soc)
2209 lo6 = 0xff98;
2210 else if (state->identity.p1g || (Rest == 0))
2211 lo6 = 0xfff8;
2212 else
2213 lo6 = 0xff28;
2214 } else
2215 lo6 = (state->config->io.pll_int_loop_filt << 3);
2216
2217 Den = 1;
1290 2218
1291 if (Rest > 0) { 2219 if (Rest > 0) {
1292 if (state->config->analog_output) 2220 if (state->config->analog_output)
1293 lo6 |= (1 << 2) | 2; 2221 lo6 |= (1 << 2) | 2;
1294 else 2222 else {
1295 lo6 |= (1 << 2) | 1; 2223 if (state->identity.in_soc)
2224 lo6 |= (1 << 2) | 2;
2225 else
2226 lo6 |= (1 << 2) | 2;
2227 }
1296 Den = 255; 2228 Den = 255;
1297 } 2229 }
1298#ifdef CONFIG_BAND_SBAND
1299 if (state->current_band == BAND_SBAND)
1300 lo6 &= 0xfffb;
1301#endif
1302
1303 dib0090_write_reg(state, 0x15, (u16) FBDiv); 2230 dib0090_write_reg(state, 0x15, (u16) FBDiv);
1304 2231 if (state->config->fref_clock_ratio != 0)
1305 dib0090_write_reg(state, 0x16, (Den << 8) | 1); 2232 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
1306 2233 else
2234 dib0090_write_reg(state, 0x16, (Den << 8) | 1);
1307 dib0090_write_reg(state, 0x17, (u16) Rest); 2235 dib0090_write_reg(state, 0x17, (u16) Rest);
1308
1309 dib0090_write_reg(state, 0x19, lo5); 2236 dib0090_write_reg(state, 0x19, lo5);
1310
1311 dib0090_write_reg(state, 0x1c, lo6); 2237 dib0090_write_reg(state, 0x1c, lo6);
1312 2238
1313 lo6 = tune->tuner_enable; 2239 lo6 = tune->tuner_enable;
1314 if (state->config->analog_output) 2240 if (state->config->analog_output)
1315 lo6 = (lo6 & 0xff9f) | 0x2; 2241 lo6 = (lo6 & 0xff9f) | 0x2;
1316 2242
1317 dib0090_write_reg(state, 0x24, lo6 | EN_LO 2243 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
1318#ifdef CONFIG_DIB0090_USE_PWM_AGC
1319 | state->config->use_pwm_agc * EN_CRYSTAL
1320#endif
1321 );
1322
1323 state->current_rf = rf;
1324
1325 /* prepare a complete captrim */
1326 state->step = state->captrim = state->fcaptrim = 64;
1327
1328 } else { /* we are already tuned to this frequency - the configuration is correct */
1329 2244
1330 /* do a minimal captrim even if the frequency has not changed */
1331 state->step = 4;
1332 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
1333 } 2245 }
1334 state->adc_diff = 3000;
1335
1336 dib0090_write_reg(state, 0x10, 0x2B1);
1337 2246
1338 dib0090_write_reg(state, 0x1e, 0x0032); 2247 state->current_rf = state->rf_request;
2248 state->current_standard = state->fe->dtv_property_cache.delivery_system;
1339 2249
1340 ret = 20; 2250 ret = 20;
1341 *tune_state = CT_TUNER_STEP_1; 2251 state->calibrate = CAPTRIM_CAL; /* captrim serach now */
1342 } else if (*tune_state == CT_TUNER_STEP_0) { 2252 }
1343 /* nothing */
1344 } else if (*tune_state == CT_TUNER_STEP_1) {
1345 state->step /= 2;
1346 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
1347 *tune_state = CT_TUNER_STEP_2;
1348 } else if (*tune_state == CT_TUNER_STEP_2) {
1349 2253
1350 adc = dib0090_read_reg(state, 0x1d); 2254 else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
1351 dprintk("FE %d CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) fe->id, (u32) state->captrim, (u32) adc, 2255 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1352 (u32) (adc) * (u32) 1800 / (u32) 1024);
1353 2256
1354 if (adc >= 400) { 2257 while (state->current_rf / 1000 > wbd->max_freq)
1355 adc -= 400; 2258 wbd++;
1356 step_sign = -1;
1357 } else {
1358 adc = 400 - adc;
1359 step_sign = 1;
1360 }
1361 2259
1362 if (adc < state->adc_diff) { 2260 dib0090_write_reg(state, 0x1e, 0x07ff);
1363 dprintk("FE %d CAPTRIM=%d is closer to target (%d/%d)", (u32) fe->id, (u32) state->captrim, (u32) adc, (u32) state->adc_diff); 2261 dprintk("Final Captrim: %d", (u32) state->fcaptrim);
1364 state->adc_diff = adc; 2262 dprintk("HFDIV code: %d", (u32) pll->hfdiv_code);
1365 state->fcaptrim = state->captrim; 2263 dprintk("VCO = %d", (u32) pll->vco_band);
1366 2264 dprintk("VCOF in kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
1367 } 2265 dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz);
2266 dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
2267 dprintk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
2268 (u32) dib0090_read_reg(state, 0x1c) & 0x3);
1368 2269
1369 state->captrim += step_sign * state->step; 2270#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
1370 if (state->step >= 1) 2271 c = 4;
1371 *tune_state = CT_TUNER_STEP_1; 2272 i = 3;
1372 else
1373 *tune_state = CT_TUNER_STEP_3;
1374 2273
1375 ret = 15; 2274 if (wbd->wbd_gain != 0)
1376 } else if (*tune_state == CT_TUNER_STEP_3) { 2275 c = wbd->wbd_gain;
1377 /*write the final cptrim config */
1378 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
1379 2276
1380#ifdef CONFIG_TUNER_DIB0090_CAPTRIM_MEMORY 2277 state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
1381 state->memory[state->memory_index].cap = state->fcaptrim; 2278 dib0090_write_reg(state, 0x10, state->wbdmux);
1382#endif
1383 2279
1384 *tune_state = CT_TUNER_STEP_4; 2280 if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {
1385 } else if (*tune_state == CT_TUNER_STEP_4) { 2281 dprintk("P1G : The cable band is selected and lna_tune = %d", tune->lna_tune);
1386 dib0090_write_reg(state, 0x1e, 0x07ff); 2282 dib0090_write_reg(state, 0x09, tune->lna_bias);
1387 2283 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
1388 dprintk("FE %d Final Captrim: %d", (u32) fe->id, (u32) state->fcaptrim); 2284 } else
1389 dprintk("FE %d HFDIV code: %d", (u32) fe->id, (u32) pll->hfdiv_code); 2285 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
1390 dprintk("FE %d VCO = %d", (u32) fe->id, (u32) pll->vco_band);
1391 dprintk("FE %d VCOF in kHz: %d ((%d*%d) << 1))", (u32) fe->id, (u32) ((pll->hfdiv * rf) * 2), (u32) pll->hfdiv, (u32) rf);
1392 dprintk("FE %d REFDIV: %d, FREF: %d", (u32) fe->id, (u32) 1, (u32) state->config->io.clock_khz);
1393 dprintk("FE %d FBDIV: %d, Rest: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
1394 dprintk("FE %d Num: %d, Den: %d, SD: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x17),
1395 (u32) (dib0090_read_reg(state, 0x16) >> 8), (u32) dib0090_read_reg(state, 0x1c) & 0x3);
1396 2286
1397 c = 4;
1398 i = 3;
1399#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
1400 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) {
1401 c = 2;
1402 i = 2;
1403 }
1404#endif
1405 dib0090_write_reg(state, 0x10, (c << 13) | (i << 11) | (WBD
1406#ifdef CONFIG_DIB0090_USE_PWM_AGC
1407 | (state->config->use_pwm_agc << 1)
1408#endif
1409 ));
1410 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | (tune->lna_bias << 0));
1411 dib0090_write_reg(state, 0x0c, tune->v2i); 2287 dib0090_write_reg(state, 0x0c, tune->v2i);
1412 dib0090_write_reg(state, 0x0d, tune->mix); 2288 dib0090_write_reg(state, 0x0d, tune->mix);
1413 dib0090_write_reg(state, 0x0e, tune->load); 2289 dib0090_write_reg(state, 0x0e, tune->load);
2290 *tune_state = CT_TUNER_STEP_1;
1414 2291
1415 *tune_state = CT_TUNER_STEP_5; 2292 } else if (*tune_state == CT_TUNER_STEP_1) {
1416 } else if (*tune_state == CT_TUNER_STEP_5) {
1417
1418 /* initialize the lt gain register */ 2293 /* initialize the lt gain register */
1419 state->rf_lt_def = 0x7c00; 2294 state->rf_lt_def = 0x7c00;
1420 dib0090_write_reg(state, 0x0f, state->rf_lt_def);
1421 2295
1422 dib0090_set_bandwidth(state); 2296 dib0090_set_bandwidth(state);
1423 state->tuner_is_tuned = 1; 2297 state->tuner_is_tuned = 1;
2298
2299 state->calibrate |= WBD_CAL;
2300 state->calibrate |= TEMP_CAL;
1424 *tune_state = CT_TUNER_STOP; 2301 *tune_state = CT_TUNER_STOP;
1425 } else 2302 } else
1426 ret = FE_CALLBACK_TIME_NEVER; 2303 ret = FE_CALLBACK_TIME_NEVER;
@@ -1440,6 +2317,7 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
1440 2317
1441 return state->tune_state; 2318 return state->tune_state;
1442} 2319}
2320
1443EXPORT_SYMBOL(dib0090_get_tune_state); 2321EXPORT_SYMBOL(dib0090_get_tune_state);
1444 2322
1445int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) 2323int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
@@ -1449,6 +2327,7 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
1449 state->tune_state = tune_state; 2327 state->tune_state = tune_state;
1450 return 0; 2328 return 0;
1451} 2329}
2330
1452EXPORT_SYMBOL(dib0090_set_tune_state); 2331EXPORT_SYMBOL(dib0090_set_tune_state);
1453 2332
1454static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency) 2333static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
@@ -1462,7 +2341,7 @@ static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
1462static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 2341static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
1463{ 2342{
1464 struct dib0090_state *state = fe->tuner_priv; 2343 struct dib0090_state *state = fe->tuner_priv;
1465 uint32_t ret; 2344 u32 ret;
1466 2345
1467 state->tune_state = CT_TUNER_START; 2346 state->tune_state = CT_TUNER_START;
1468 2347
@@ -1492,6 +2371,29 @@ static const struct dvb_tuner_ops dib0090_ops = {
1492 .get_frequency = dib0090_get_frequency, 2371 .get_frequency = dib0090_get_frequency,
1493}; 2372};
1494 2373
2374static const struct dvb_tuner_ops dib0090_fw_ops = {
2375 .info = {
2376 .name = "DiBcom DiB0090",
2377 .frequency_min = 45000000,
2378 .frequency_max = 860000000,
2379 .frequency_step = 1000,
2380 },
2381 .release = dib0090_release,
2382
2383 .init = NULL,
2384 .sleep = NULL,
2385 .set_params = NULL,
2386 .get_frequency = NULL,
2387};
2388
2389static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
2390 {470, 0, 250, 0, 100, 4},
2391 {860, 51, 866, 21, 375, 4},
2392 {1700, 0, 800, 0, 850, 4},
2393 {2900, 0, 250, 0, 100, 6},
2394 {0xFFFF, 0, 0, 0, 0, 0},
2395};
2396
1495struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config) 2397struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
1496{ 2398{
1497 struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL); 2399 struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
@@ -1503,6 +2405,11 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
1503 st->fe = fe; 2405 st->fe = fe;
1504 fe->tuner_priv = st; 2406 fe->tuner_priv = st;
1505 2407
2408 if (config->wbd == NULL)
2409 st->current_wbd_table = dib0090_wbd_table_default;
2410 else
2411 st->current_wbd_table = config->wbd;
2412
1506 if (dib0090_reset(fe) != 0) 2413 if (dib0090_reset(fe) != 0)
1507 goto free_mem; 2414 goto free_mem;
1508 2415
@@ -1515,8 +2422,34 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
1515 fe->tuner_priv = NULL; 2422 fe->tuner_priv = NULL;
1516 return NULL; 2423 return NULL;
1517} 2424}
2425
1518EXPORT_SYMBOL(dib0090_register); 2426EXPORT_SYMBOL(dib0090_register);
1519 2427
2428struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
2429{
2430 struct dib0090_fw_state *st = kzalloc(sizeof(struct dib0090_fw_state), GFP_KERNEL);
2431 if (st == NULL)
2432 return NULL;
2433
2434 st->config = config;
2435 st->i2c = i2c;
2436 st->fe = fe;
2437 fe->tuner_priv = st;
2438
2439 if (dib0090_fw_reset_digital(fe, st->config) != 0)
2440 goto free_mem;
2441
2442 dprintk("DiB0090 FW: successfully identified");
2443 memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
2444
2445 return fe;
2446free_mem:
2447 kfree(st);
2448 fe->tuner_priv = NULL;
2449 return NULL;
2450}
2451EXPORT_SYMBOL(dib0090_fw_register);
2452
1520MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); 2453MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
1521MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>"); 2454MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>");
1522MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner"); 2455MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 19:50:55 -0500