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path: root/drivers/media/dvb/frontends/cx24110.c
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-rw-r--r--drivers/media/dvb/frontends/cx24110.c657
1 files changed, 657 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/cx24110.c b/drivers/media/dvb/frontends/cx24110.c
new file mode 100644
index 000000000000..ae16112a0653
--- /dev/null
+++ b/drivers/media/dvb/frontends/cx24110.c
@@ -0,0 +1,657 @@
1/*
2 cx24110 - Single Chip Satellite Channel Receiver driver module
3
4 Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@t-online.de> based on
5 work
6 Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22
23*/
24
25#include <linux/slab.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30
31#include "dvb_frontend.h"
32#include "cx24110.h"
33
34
35struct cx24110_state {
36
37 struct i2c_adapter* i2c;
38
39 struct dvb_frontend_ops ops;
40
41 const struct cx24110_config* config;
42
43 struct dvb_frontend frontend;
44
45 u32 lastber;
46 u32 lastbler;
47 u32 lastesn0;
48};
49
50static int debug;
51#define dprintk(args...) \
52 do { \
53 if (debug) printk(KERN_DEBUG "cx24110: " args); \
54 } while (0)
55
56static struct {u8 reg; u8 data;} cx24110_regdata[]=
57 /* Comments beginning with @ denote this value should
58 be the default */
59 {{0x09,0x01}, /* SoftResetAll */
60 {0x09,0x00}, /* release reset */
61 {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
62 {0x02,0x17}, /* middle byte " */
63 {0x03,0x29}, /* LSB " */
64 {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
65 {0x06,0xa5}, /* @ PLL 60MHz */
66 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
67 {0x0a,0x00}, /* @ partial chip disables, do not set */
68 {0x0b,0x01}, /* set output clock in gapped mode, start signal low
69 active for first byte */
70 {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
71 {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
72 {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
73 to avoid starting the BER counter. Reset the
74 CRC test bit. Finite counting selected */
75 {0x15,0xff}, /* @ size of the limited time window for RS BER
76 estimation. It is <value>*256 RS blocks, this
77 gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
78 {0x16,0x00}, /* @ enable all RS output ports */
79 {0x17,0x04}, /* @ time window allowed for the RS to sync */
80 {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
81 for automatically */
82 /* leave the current code rate and normalization
83 registers as they are after reset... */
84 {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
85 only once */
86 {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
87 estimation. It is <value>*65536 channel bits, i.e.
88 approx. 38ms at 27.5MS/s, rate 3/4 */
89 {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
90 /* leave front-end AGC parameters at default values */
91 /* leave decimation AGC parameters at default values */
92 {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
93 {0x36,0xff}, /* clear all interrupt pending flags */
94 {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
95 {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
96 /* leave the equalizer parameters on their default values */
97 /* leave the final AGC parameters on their default values */
98 {0x41,0x00}, /* @ MSB of front-end derotator frequency */
99 {0x42,0x00}, /* @ middle bytes " */
100 {0x43,0x00}, /* @ LSB " */
101 /* leave the carrier tracking loop parameters on default */
102 /* leave the bit timing loop parameters at gefault */
103 {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
104 /* the cx24108 data sheet for symbol rates above 15MS/s */
105 {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
106 {0x61,0x95}, /* GPIO pins 1-4 have special function */
107 {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
108 {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
109 {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
110 {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
111 {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
112 {0x73,0x00}, /* @ disable several demod bypasses */
113 {0x74,0x00}, /* @ " */
114 {0x75,0x00} /* @ " */
115 /* the remaining registers are for SEC */
116 };
117
118
119static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
120{
121 u8 buf [] = { reg, data };
122 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
123 int err;
124
125 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
126 dprintk ("%s: writereg error (err == %i, reg == 0x%02x,"
127 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
128 return -EREMOTEIO;
129 }
130
131 return 0;
132}
133
134static int cx24110_readreg (struct cx24110_state* state, u8 reg)
135{
136 int ret;
137 u8 b0 [] = { reg };
138 u8 b1 [] = { 0 };
139 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
140 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
141
142 ret = i2c_transfer(state->i2c, msg, 2);
143
144 if (ret != 2) return ret;
145
146 return b1[0];
147}
148
149static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inversion_t inversion)
150{
151/* fixme (low): error handling */
152
153 switch (inversion) {
154 case INVERSION_OFF:
155 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
156 /* AcqSpectrInvDis on. No idea why someone should want this */
157 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
158 /* Initial value 0 at start of acq */
159 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
160 /* current value 0 */
161 /* The cx24110 manual tells us this reg is read-only.
162 But what the heck... set it ayways */
163 break;
164 case INVERSION_ON:
165 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
166 /* AcqSpectrInvDis on. No idea why someone should want this */
167 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
168 /* Initial value 1 at start of acq */
169 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
170 /* current value 1 */
171 break;
172 case INVERSION_AUTO:
173 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
174 /* AcqSpectrInvDis off. Leave initial & current states as is */
175 break;
176 default:
177 return -EINVAL;
178 }
179
180 return 0;
181}
182
183static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
184{
185/* fixme (low): error handling */
186
187 static const int rate[]={-1,1,2,3,5,7,-1};
188 static const int g1[]={-1,0x01,0x02,0x05,0x15,0x45,-1};
189 static const int g2[]={-1,0x01,0x03,0x06,0x1a,0x7a,-1};
190
191 /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
192 searches all enabled viterbi rates, and can handle non-standard
193 rates as well. */
194
195 if (fec>FEC_AUTO)
196 fec=FEC_AUTO;
197
198 if (fec==FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
199 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xdf);
200 /* clear AcqVitDis bit */
201 cx24110_writereg(state,0x18,0xae);
202 /* allow all DVB standard code rates */
203 cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|0x3);
204 /* set nominal Viterbi rate 3/4 */
205 cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|0x3);
206 /* set current Viterbi rate 3/4 */
207 cx24110_writereg(state,0x1a,0x05); cx24110_writereg(state,0x1b,0x06);
208 /* set the puncture registers for code rate 3/4 */
209 return 0;
210 } else {
211 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x20);
212 /* set AcqVitDis bit */
213 if(rate[fec]>0) {
214 cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|rate[fec]);
215 /* set nominal Viterbi rate */
216 cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|rate[fec]);
217 /* set current Viterbi rate */
218 cx24110_writereg(state,0x1a,g1[fec]);
219 cx24110_writereg(state,0x1b,g2[fec]);
220 /* not sure if this is the right way: I always used AutoAcq mode */
221 } else
222 return -EOPNOTSUPP;
223/* fixme (low): which is the correct return code? */
224 };
225 return 0;
226}
227
228static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state)
229{
230 int i;
231
232 i=cx24110_readreg(state,0x22)&0x0f;
233 if(!(i&0x08)) {
234 return FEC_1_2 + i - 1;
235 } else {
236/* fixme (low): a special code rate has been selected. In theory, we need to
237 return a denominator value, a numerator value, and a pair of puncture
238 maps to correctly describe this mode. But this should never happen in
239 practice, because it cannot be set by cx24110_get_fec. */
240 return FEC_NONE;
241 }
242}
243
244static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
245{
246/* fixme (low): add error handling */
247 u32 ratio;
248 u32 tmp, fclk, BDRI;
249
250 static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
251 int i;
252
253dprintk("cx24110 debug: entering %s(%d)\n",__FUNCTION__,srate);
254 if (srate>90999000UL/2)
255 srate=90999000UL/2;
256 if (srate<500000)
257 srate=500000;
258
259 for(i=0;(i<sizeof(bands)/sizeof(bands[0]))&&(srate>bands[i]);i++)
260 ;
261 /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
262 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
263 R06[3:0] PLLphaseDetGain */
264 tmp=cx24110_readreg(state,0x07)&0xfc;
265 if(srate<90999000UL/4) { /* sample rate 45MHz*/
266 cx24110_writereg(state,0x07,tmp);
267 cx24110_writereg(state,0x06,0x78);
268 fclk=90999000UL/2;
269 } else if(srate<60666000UL/2) { /* sample rate 60MHz */
270 cx24110_writereg(state,0x07,tmp|0x1);
271 cx24110_writereg(state,0x06,0xa5);
272 fclk=60666000UL;
273 } else if(srate<80888000UL/2) { /* sample rate 80MHz */
274 cx24110_writereg(state,0x07,tmp|0x2);
275 cx24110_writereg(state,0x06,0x87);
276 fclk=80888000UL;
277 } else { /* sample rate 90MHz */
278 cx24110_writereg(state,0x07,tmp|0x3);
279 cx24110_writereg(state,0x06,0x78);
280 fclk=90999000UL;
281 };
282 dprintk("cx24110 debug: fclk %d Hz\n",fclk);
283 /* we need to divide two integers with approx. 27 bits in 32 bit
284 arithmetic giving a 25 bit result */
285 /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
286 also the most complex divisor. Hence, the dividend has,
287 assuming 32bit unsigned arithmetic, 6 clear bits on top, the
288 divisor 2 unused bits at the bottom. Also, the quotient is
289 always less than 1/2. Borrowed from VES1893.c, of course */
290
291 tmp=srate<<6;
292 BDRI=fclk>>2;
293 ratio=(tmp/BDRI);
294
295 tmp=(tmp%BDRI)<<8;
296 ratio=(ratio<<8)+(tmp/BDRI);
297
298 tmp=(tmp%BDRI)<<8;
299 ratio=(ratio<<8)+(tmp/BDRI);
300
301 tmp=(tmp%BDRI)<<1;
302 ratio=(ratio<<1)+(tmp/BDRI);
303
304 dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
305 dprintk("fclk = %d\n", fclk);
306 dprintk("ratio= %08x\n", ratio);
307
308 cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
309 cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
310 cx24110_writereg(state, 0x3, (ratio)&0xff);
311
312 return 0;
313
314}
315
316int cx24110_pll_write (struct dvb_frontend* fe, u32 data)
317{
318 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
319
320/* tuner data is 21 bits long, must be left-aligned in data */
321/* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
322/* FIXME (low): add error handling, avoid infinite loops if HW fails... */
323
324 dprintk("cx24110 debug: cx24108_write(%8.8x)\n",data);
325
326 cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
327 cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
328
329 /* if the auto tuner writer is still busy, clear it out */
330 while (cx24110_readreg(state,0x6d)&0x80)
331 cx24110_writereg(state,0x72,0);
332
333 /* write the topmost 8 bits */
334 cx24110_writereg(state,0x72,(data>>24)&0xff);
335
336 /* wait for the send to be completed */
337 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
338 ;
339
340 /* send another 8 bytes */
341 cx24110_writereg(state,0x72,(data>>16)&0xff);
342 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
343 ;
344
345 /* and the topmost 5 bits of this byte */
346 cx24110_writereg(state,0x72,(data>>8)&0xff);
347 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
348 ;
349
350 /* now strobe the enable line once */
351 cx24110_writereg(state,0x6d,0x32);
352 cx24110_writereg(state,0x6d,0x30);
353
354 return 0;
355}
356
357static int cx24110_initfe(struct dvb_frontend* fe)
358{
359 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
360/* fixme (low): error handling */
361 int i;
362
363 dprintk("%s: init chip\n", __FUNCTION__);
364
365 for(i=0;i<sizeof(cx24110_regdata)/sizeof(cx24110_regdata[0]);i++) {
366 cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
367 };
368
369 if (state->config->pll_init) state->config->pll_init(fe);
370
371 return 0;
372}
373
374static int cx24110_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
375{
376 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
377
378 switch (voltage) {
379 case SEC_VOLTAGE_13:
380 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
381 case SEC_VOLTAGE_18:
382 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
383 default:
384 return -EINVAL;
385 };
386}
387
388static int cx24110_diseqc_send_burst(struct dvb_frontend* fe,
389 fe_sec_mini_cmd_t burst)
390{
391 int rv, bit, i;
392 struct cx24110_state *state = fe->demodulator_priv;
393
394 if (burst == SEC_MINI_A)
395 bit = 0x00;
396 else if (burst == SEC_MINI_B)
397 bit = 0x08;
398 else
399 return -EINVAL;
400
401 rv = cx24110_readreg(state, 0x77);
402 cx24110_writereg(state, 0x77, rv|0x04);
403
404 rv = cx24110_readreg(state, 0x76);
405 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
406 for (i = 500; i-- > 0 && !(cx24110_readreg(state,0x76)&0x40) ; )
407 ; /* wait for LNB ready */
408
409 return 0;
410}
411
412static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
413 struct dvb_diseqc_master_cmd *cmd)
414{
415 int i, rv;
416 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
417
418 for (i = 0; i < cmd->msg_len; i++)
419 cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
420
421 rv = cx24110_readreg(state, 0x77);
422 cx24110_writereg(state, 0x77, rv|0x04);
423
424 rv = cx24110_readreg(state, 0x76);
425
426 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
427 for (i=500; i-- > 0 && !(cx24110_readreg(state,0x76)&0x40);)
428 ; /* wait for LNB ready */
429
430 return 0;
431}
432
433static int cx24110_read_status(struct dvb_frontend* fe, fe_status_t* status)
434{
435 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
436
437 int sync = cx24110_readreg (state, 0x55);
438
439 *status = 0;
440
441 if (sync & 0x10)
442 *status |= FE_HAS_SIGNAL;
443
444 if (sync & 0x08)
445 *status |= FE_HAS_CARRIER;
446
447 sync = cx24110_readreg (state, 0x08);
448
449 if (sync & 0x40)
450 *status |= FE_HAS_VITERBI;
451
452 if (sync & 0x20)
453 *status |= FE_HAS_SYNC;
454
455 if ((sync & 0x60) == 0x60)
456 *status |= FE_HAS_LOCK;
457
458 return 0;
459}
460
461static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
462{
463 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
464
465 /* fixme (maybe): value range is 16 bit. Scale? */
466 if(cx24110_readreg(state,0x24)&0x10) {
467 /* the Viterbi error counter has finished one counting window */
468 cx24110_writereg(state,0x24,0x04); /* select the ber reg */
469 state->lastber=cx24110_readreg(state,0x25)|
470 (cx24110_readreg(state,0x26)<<8);
471 cx24110_writereg(state,0x24,0x04); /* start new count window */
472 cx24110_writereg(state,0x24,0x14);
473 }
474 *ber = state->lastber;
475
476 return 0;
477}
478
479static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
480{
481 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
482
483/* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
484 u8 signal = cx24110_readreg (state, 0x27)+128;
485 *signal_strength = (signal << 8) | signal;
486
487 return 0;
488}
489
490static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
491{
492 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
493
494 /* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
495 if(cx24110_readreg(state,0x6a)&0x80) {
496 /* the Es/N0 error counter has finished one counting window */
497 state->lastesn0=cx24110_readreg(state,0x69)|
498 (cx24110_readreg(state,0x68)<<8);
499 cx24110_writereg(state,0x6a,0x84); /* start new count window */
500 }
501 *snr = state->lastesn0;
502
503 return 0;
504}
505
506static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
507{
508 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
509 u32 lastbyer;
510
511 if(cx24110_readreg(state,0x10)&0x40) {
512 /* the RS error counter has finished one counting window */
513 cx24110_writereg(state,0x10,0x60); /* select the byer reg */
514 lastbyer=cx24110_readreg(state,0x12)|
515 (cx24110_readreg(state,0x13)<<8)|
516 (cx24110_readreg(state,0x14)<<16);
517 cx24110_writereg(state,0x10,0x70); /* select the bler reg */
518 state->lastbler=cx24110_readreg(state,0x12)|
519 (cx24110_readreg(state,0x13)<<8)|
520 (cx24110_readreg(state,0x14)<<16);
521 cx24110_writereg(state,0x10,0x20); /* start new count window */
522 }
523 *ucblocks = state->lastbler;
524
525 return 0;
526}
527
528static int cx24110_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
529{
530 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
531
532 state->config->pll_set(fe, p);
533 cx24110_set_inversion (state, p->inversion);
534 cx24110_set_fec (state, p->u.qpsk.fec_inner);
535 cx24110_set_symbolrate (state, p->u.qpsk.symbol_rate);
536 cx24110_writereg(state,0x04,0x05); /* start aquisition */
537
538 return 0;
539}
540
541static int cx24110_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
542{
543 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
544 s32 afc; unsigned sclk;
545
546/* cannot read back tuner settings (freq). Need to have some private storage */
547
548 sclk = cx24110_readreg (state, 0x07) & 0x03;
549/* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
550 * Need 64 bit arithmetic. Is thiss possible in the kernel? */
551 if (sclk==0) sclk=90999000L/2L;
552 else if (sclk==1) sclk=60666000L;
553 else if (sclk==2) sclk=80888000L;
554 else sclk=90999000L;
555 sclk>>=8;
556 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
557 ((sclk*cx24110_readreg (state, 0x45))>>8)+
558 ((sclk*cx24110_readreg (state, 0x46))>>16);
559
560 p->frequency += afc;
561 p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
562 INVERSION_ON : INVERSION_OFF;
563 p->u.qpsk.fec_inner = cx24110_get_fec (state);
564
565 return 0;
566}
567
568static int cx24110_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
569{
570 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
571
572 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
573}
574
575static void cx24110_release(struct dvb_frontend* fe)
576{
577 struct cx24110_state* state = (struct cx24110_state*) fe->demodulator_priv;
578 kfree(state);
579}
580
581static struct dvb_frontend_ops cx24110_ops;
582
583struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
584 struct i2c_adapter* i2c)
585{
586 struct cx24110_state* state = NULL;
587 int ret;
588
589 /* allocate memory for the internal state */
590 state = (struct cx24110_state*) kmalloc(sizeof(struct cx24110_state), GFP_KERNEL);
591 if (state == NULL) goto error;
592
593 /* setup the state */
594 state->config = config;
595 state->i2c = i2c;
596 memcpy(&state->ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
597 state->lastber = 0;
598 state->lastbler = 0;
599 state->lastesn0 = 0;
600
601 /* check if the demod is there */
602 ret = cx24110_readreg(state, 0x00);
603 if ((ret != 0x5a) && (ret != 0x69)) goto error;
604
605 /* create dvb_frontend */
606 state->frontend.ops = &state->ops;
607 state->frontend.demodulator_priv = state;
608 return &state->frontend;
609
610error:
611 kfree(state);
612 return NULL;
613}
614
615static struct dvb_frontend_ops cx24110_ops = {
616
617 .info = {
618 .name = "Conexant CX24110 DVB-S",
619 .type = FE_QPSK,
620 .frequency_min = 950000,
621 .frequency_max = 2150000,
622 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
623 .frequency_tolerance = 29500,
624 .symbol_rate_min = 1000000,
625 .symbol_rate_max = 45000000,
626 .caps = FE_CAN_INVERSION_AUTO |
627 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
628 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
629 FE_CAN_QPSK | FE_CAN_RECOVER
630 },
631
632 .release = cx24110_release,
633
634 .init = cx24110_initfe,
635 .set_frontend = cx24110_set_frontend,
636 .get_frontend = cx24110_get_frontend,
637 .read_status = cx24110_read_status,
638 .read_ber = cx24110_read_ber,
639 .read_signal_strength = cx24110_read_signal_strength,
640 .read_snr = cx24110_read_snr,
641 .read_ucblocks = cx24110_read_ucblocks,
642
643 .diseqc_send_master_cmd = cx24110_send_diseqc_msg,
644 .set_tone = cx24110_set_tone,
645 .set_voltage = cx24110_set_voltage,
646 .diseqc_send_burst = cx24110_diseqc_send_burst,
647};
648
649module_param(debug, int, 0644);
650MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
651
652MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
653MODULE_AUTHOR("Peter Hettkamp");
654MODULE_LICENSE("GPL");
655
656EXPORT_SYMBOL(cx24110_attach);
657EXPORT_SYMBOL(cx24110_pll_write);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 14:40:46 -0500