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-rw-r--r--drivers/media/dvb/b2c2/Kconfig14
-rw-r--r--drivers/media/dvb/b2c2/Makefile2
-rw-r--r--drivers/media/dvb/b2c2/flexcop-common.h6
-rw-r--r--drivers/media/dvb/b2c2/flexcop-dma.c165
-rw-r--r--drivers/media/dvb/b2c2/flexcop-hw-filter.c12
-rw-r--r--drivers/media/dvb/b2c2/flexcop-misc.c12
-rw-r--r--drivers/media/dvb/b2c2/flexcop-pci.c122
-rw-r--r--drivers/media/dvb/b2c2/flexcop-reg.h548
-rw-r--r--drivers/media/dvb/b2c2/flexcop-usb.c2
-rw-r--r--drivers/media/dvb/b2c2/flexcop.c34
-rw-r--r--drivers/media/dvb/b2c2/flexcop.h1
-rw-r--r--drivers/media/dvb/b2c2/flexcop_ibi_value_be.h458
-rw-r--r--drivers/media/dvb/b2c2/flexcop_ibi_value_le.h458
-rw-r--r--drivers/media/dvb/b2c2/skystar2.c2644
14 files changed, 1182 insertions, 3296 deletions
diff --git a/drivers/media/dvb/b2c2/Kconfig b/drivers/media/dvb/b2c2/Kconfig
index fafd0ab3a28f..d7417eac2aba 100644
--- a/drivers/media/dvb/b2c2/Kconfig
+++ b/drivers/media/dvb/b2c2/Kconfig
@@ -35,17 +35,3 @@ config DVB_B2C2_FLEXCOP_DEBUG
35 help 35 help
36 Say Y if you want to enable the module option to control debug messages 36 Say Y if you want to enable the module option to control debug messages
37 of all B2C2 FlexCop drivers. 37 of all B2C2 FlexCop drivers.
38
39config DVB_B2C2_SKYSTAR
40 tristate "B2C2/Technisat Air/Sky/CableStar 2 PCI"
41 depends on DVB_CORE && PCI
42 select DVB_STV0299
43 select DVB_MT352
44 select DVB_MT312
45 select DVB_NXT2002
46 help
47 Support for the Skystar2 PCI DVB card by Technisat, which
48 is equipped with the FlexCopII chipset by B2C2, and
49 for the B2C2/BBTI Air2PC-ATSC card.
50
51 Say Y if you own such a device and want to use it.
diff --git a/drivers/media/dvb/b2c2/Makefile b/drivers/media/dvb/b2c2/Makefile
index 7703812af34f..1a1c3bca55fa 100644
--- a/drivers/media/dvb/b2c2/Makefile
+++ b/drivers/media/dvb/b2c2/Makefile
@@ -9,6 +9,4 @@ obj-$(CONFIG_DVB_B2C2_FLEXCOP_PCI) += b2c2-flexcop-pci.o
9b2c2-flexcop-usb-objs = flexcop-usb.o 9b2c2-flexcop-usb-objs = flexcop-usb.o
10obj-$(CONFIG_DVB_B2C2_FLEXCOP_USB) += b2c2-flexcop-usb.o 10obj-$(CONFIG_DVB_B2C2_FLEXCOP_USB) += b2c2-flexcop-usb.o
11 11
12obj-$(CONFIG_DVB_B2C2_SKYSTAR) += skystar2.o
13
14EXTRA_CFLAGS = -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/ 12EXTRA_CFLAGS = -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/
diff --git a/drivers/media/dvb/b2c2/flexcop-common.h b/drivers/media/dvb/b2c2/flexcop-common.h
index 773d158032df..a94912ac1872 100644
--- a/drivers/media/dvb/b2c2/flexcop-common.h
+++ b/drivers/media/dvb/b2c2/flexcop-common.h
@@ -108,6 +108,8 @@ void flexcop_device_kfree(struct flexcop_device*);
108int flexcop_device_initialize(struct flexcop_device*); 108int flexcop_device_initialize(struct flexcop_device*);
109void flexcop_device_exit(struct flexcop_device *fc); 109void flexcop_device_exit(struct flexcop_device *fc);
110 110
111void flexcop_reset_block_300(struct flexcop_device *fc);
112
111/* from flexcop-dma.c */ 113/* from flexcop-dma.c */
112int flexcop_dma_allocate(struct pci_dev *pdev, struct flexcop_dma *dma, u32 size); 114int flexcop_dma_allocate(struct pci_dev *pdev, struct flexcop_dma *dma, u32 size);
113void flexcop_dma_free(struct flexcop_dma *dma); 115void flexcop_dma_free(struct flexcop_dma *dma);
@@ -115,7 +117,8 @@ void flexcop_dma_free(struct flexcop_dma *dma);
115int flexcop_dma_control_timer_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff); 117int flexcop_dma_control_timer_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff);
116int flexcop_dma_control_size_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff); 118int flexcop_dma_control_size_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff);
117int flexcop_dma_control_packet_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff); 119int flexcop_dma_control_packet_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff);
118int flexcop_dma_config(struct flexcop_device *fc, struct flexcop_dma *dma, flexcop_dma_index_t dma_idx,flexcop_dma_addr_index_t index); 120int flexcop_dma_config(struct flexcop_device *fc, struct flexcop_dma *dma, flexcop_dma_index_t dma_idx);
121int flexcop_dma_xfer_control(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, flexcop_dma_addr_index_t index, int onoff);
119int flexcop_dma_config_timer(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, u8 cycles); 122int flexcop_dma_config_timer(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, u8 cycles);
120int flexcop_dma_config_packet_count(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, u8 packets); 123int flexcop_dma_config_packet_count(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, u8 packets);
121 124
@@ -151,6 +154,7 @@ int flexcop_sram_init(struct flexcop_device *fc);
151/* from flexcop-misc.c */ 154/* from flexcop-misc.c */
152void flexcop_determine_revision(struct flexcop_device *fc); 155void flexcop_determine_revision(struct flexcop_device *fc);
153void flexcop_device_name(struct flexcop_device *fc,const char *prefix,const char *suffix); 156void flexcop_device_name(struct flexcop_device *fc,const char *prefix,const char *suffix);
157void flexcop_dump_reg(struct flexcop_device *fc, flexcop_ibi_register reg, int num);
154 158
155/* from flexcop-hw-filter.c */ 159/* from flexcop-hw-filter.c */
156int flexcop_pid_feed_control(struct flexcop_device *fc, struct dvb_demux_feed *dvbdmxfeed, int onoff); 160int flexcop_pid_feed_control(struct flexcop_device *fc, struct dvb_demux_feed *dvbdmxfeed, int onoff);
diff --git a/drivers/media/dvb/b2c2/flexcop-dma.c b/drivers/media/dvb/b2c2/flexcop-dma.c
index 8d2706075360..cf4ed1df6086 100644
--- a/drivers/media/dvb/b2c2/flexcop-dma.c
+++ b/drivers/media/dvb/b2c2/flexcop-dma.c
@@ -37,22 +37,90 @@ void flexcop_dma_free(struct flexcop_dma *dma)
37} 37}
38EXPORT_SYMBOL(flexcop_dma_free); 38EXPORT_SYMBOL(flexcop_dma_free);
39 39
40int flexcop_dma_control_timer_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff) 40int flexcop_dma_config(struct flexcop_device *fc,
41 struct flexcop_dma *dma,
42 flexcop_dma_index_t dma_idx)
41{ 43{
42 flexcop_ibi_value v = fc->read_ibi_reg(fc,ctrl_208); 44 flexcop_ibi_value v0x0,v0x4,v0xc;
45 v0x0.raw = v0x4.raw = v0xc.raw = 0;
43 46
44 if (no & FC_DMA_1) 47 v0x0.dma_0x0.dma_address0 = dma->dma_addr0 >> 2;
45 v.ctrl_208.DMA1_Timer_Enable_sig = onoff; 48 v0xc.dma_0xc.dma_address1 = dma->dma_addr1 >> 2;
49 v0x4.dma_0x4_write.dma_addr_size = dma->size / 4;
46 50
47 if (no & FC_DMA_2) 51 if ((dma_idx & FC_DMA_1) == dma_idx) {
48 v.ctrl_208.DMA2_Timer_Enable_sig = onoff; 52 fc->write_ibi_reg(fc,dma1_000,v0x0);
53 fc->write_ibi_reg(fc,dma1_004,v0x4);
54 fc->write_ibi_reg(fc,dma1_00c,v0xc);
55 } else if ((dma_idx & FC_DMA_2) == dma_idx) {
56 fc->write_ibi_reg(fc,dma2_010,v0x0);
57 fc->write_ibi_reg(fc,dma2_014,v0x4);
58 fc->write_ibi_reg(fc,dma2_01c,v0xc);
59 } else {
60 err("either DMA1 or DMA2 can be configured at the within one flexcop_dma_config call.");
61 return -EINVAL;
62 }
49 63
50 fc->write_ibi_reg(fc,ctrl_208,v);
51 return 0; 64 return 0;
52} 65}
53EXPORT_SYMBOL(flexcop_dma_control_timer_irq); 66EXPORT_SYMBOL(flexcop_dma_config);
67
68/* start the DMA transfers, but not the DMA IRQs */
69int flexcop_dma_xfer_control(struct flexcop_device *fc,
70 flexcop_dma_index_t dma_idx,
71 flexcop_dma_addr_index_t index,
72 int onoff)
73{
74 flexcop_ibi_value v0x0,v0xc;
75 flexcop_ibi_register r0x0,r0xc;
76
77 if ((dma_idx & FC_DMA_1) == dma_idx) {
78 r0x0 = dma1_000;
79 r0xc = dma1_00c;
80 } else if ((dma_idx & FC_DMA_2) == dma_idx) {
81 r0x0 = dma2_010;
82 r0xc = dma2_01c;
83 } else {
84 err("either transfer DMA1 or DMA2 can be started within one flexcop_dma_xfer_control call.");
85 return -EINVAL;
86 }
87
88 v0x0 = fc->read_ibi_reg(fc,r0x0);
89 v0xc = fc->read_ibi_reg(fc,r0xc);
90
91 deb_rdump("reg: %03x: %x\n",r0x0,v0x0.raw);
92 deb_rdump("reg: %03x: %x\n",r0xc,v0xc.raw);
93
94 if (index & FC_DMA_SUBADDR_0)
95 v0x0.dma_0x0.dma_0start = onoff;
96
97 if (index & FC_DMA_SUBADDR_1)
98 v0xc.dma_0xc.dma_1start = onoff;
99
100 fc->write_ibi_reg(fc,r0x0,v0x0);
101 fc->write_ibi_reg(fc,r0xc,v0xc);
102
103 deb_rdump("reg: %03x: %x\n",r0x0,v0x0.raw);
104 deb_rdump("reg: %03x: %x\n",r0xc,v0xc.raw);
105 return 0;
106}
107EXPORT_SYMBOL(flexcop_dma_xfer_control);
108
109static int flexcop_dma_remap(struct flexcop_device *fc,
110 flexcop_dma_index_t dma_idx,
111 int onoff)
112{
113 flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_00c : dma2_01c;
114 flexcop_ibi_value v = fc->read_ibi_reg(fc,r);
115 deb_info("%s\n",__FUNCTION__);
116 v.dma_0xc.remap_enable = onoff;
117 fc->write_ibi_reg(fc,r,v);
118 return 0;
119}
54 120
55int flexcop_dma_control_size_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff) 121int flexcop_dma_control_size_irq(struct flexcop_device *fc,
122 flexcop_dma_index_t no,
123 int onoff)
56{ 124{
57 flexcop_ibi_value v = fc->read_ibi_reg(fc,ctrl_208); 125 flexcop_ibi_value v = fc->read_ibi_reg(fc,ctrl_208);
58 126
@@ -67,75 +135,64 @@ int flexcop_dma_control_size_irq(struct flexcop_device *fc, flexcop_dma_index_t
67} 135}
68EXPORT_SYMBOL(flexcop_dma_control_size_irq); 136EXPORT_SYMBOL(flexcop_dma_control_size_irq);
69 137
70int flexcop_dma_control_packet_irq(struct flexcop_device *fc, flexcop_dma_index_t no, int onoff) 138int flexcop_dma_control_timer_irq(struct flexcop_device *fc,
139 flexcop_dma_index_t no,
140 int onoff)
71{ 141{
72 flexcop_ibi_value v = fc->read_ibi_reg(fc,ctrl_208); 142 flexcop_ibi_value v = fc->read_ibi_reg(fc,ctrl_208);
73 143
74 if (no & FC_DMA_1) 144 if (no & FC_DMA_1)
75 v.ctrl_208.DMA1_Size_IRQ_Enable_sig = onoff; 145 v.ctrl_208.DMA1_Timer_Enable_sig = onoff;
76 146
77 if (no & FC_DMA_2) 147 if (no & FC_DMA_2)
78 v.ctrl_208.DMA2_Size_IRQ_Enable_sig = onoff; 148 v.ctrl_208.DMA2_Timer_Enable_sig = onoff;
79 149
80 fc->write_ibi_reg(fc,ctrl_208,v); 150 fc->write_ibi_reg(fc,ctrl_208,v);
81 return 0; 151 return 0;
82} 152}
83EXPORT_SYMBOL(flexcop_dma_control_packet_irq); 153EXPORT_SYMBOL(flexcop_dma_control_timer_irq);
84 154
85int flexcop_dma_config(struct flexcop_device *fc, struct flexcop_dma *dma, flexcop_dma_index_t dma_idx,flexcop_dma_addr_index_t index) 155/* 1 cycles = 1.97 msec */
156int flexcop_dma_config_timer(struct flexcop_device *fc,
157 flexcop_dma_index_t dma_idx,
158 u8 cycles)
86{ 159{
160 flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_004 : dma2_014;
161 flexcop_ibi_value v = fc->read_ibi_reg(fc,r);
87 162
88 flexcop_ibi_value v0x0,v0x4,v0xc; 163 flexcop_dma_remap(fc,dma_idx,0);
89 v0x0.raw = v0x4.raw = v0xc.raw = 0;
90
91 v0x0.dma_0x0.dma_address0 = dma->dma_addr0 >> 2;
92 v0xc.dma_0xc.dma_address1 = dma->dma_addr1 >> 2;
93 v0x4.dma_0x4_write.dma_addr_size = dma->size / 4;
94
95 if (index & FC_DMA_SUBADDR_0)
96 v0x0.dma_0x0.dma_0start = 1;
97
98 if (index & FC_DMA_SUBADDR_1)
99 v0xc.dma_0xc.dma_1start = 1;
100
101 if (dma_idx & FC_DMA_1) {
102 fc->write_ibi_reg(fc,dma1_000,v0x0);
103 fc->write_ibi_reg(fc,dma1_004,v0x4);
104 fc->write_ibi_reg(fc,dma1_00c,v0xc);
105 } else { /* (dma_idx & FC_DMA_2) */
106 fc->write_ibi_reg(fc,dma2_010,v0x0);
107 fc->write_ibi_reg(fc,dma2_014,v0x4);
108 fc->write_ibi_reg(fc,dma2_01c,v0xc);
109 }
110
111 return 0;
112}
113EXPORT_SYMBOL(flexcop_dma_config);
114 164
115static int flexcop_dma_remap(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, int onoff) 165 deb_info("%s\n",__FUNCTION__);
116{ 166 v.dma_0x4_write.dmatimer = cycles;
117 flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_00c : dma2_01c;
118 flexcop_ibi_value v = fc->read_ibi_reg(fc,r);
119 v.dma_0xc.remap_enable = onoff;
120 fc->write_ibi_reg(fc,r,v); 167 fc->write_ibi_reg(fc,r,v);
121 return 0; 168 return 0;
122} 169}
170EXPORT_SYMBOL(flexcop_dma_config_timer);
123 171
124/* 1 cycles = 1.97 msec */ 172/* packet IRQ does not exist in FCII or FCIIb - according to data book and tests */
125int flexcop_dma_config_timer(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, u8 cycles) 173int flexcop_dma_control_packet_irq(struct flexcop_device *fc,
174 flexcop_dma_index_t no,
175 int onoff)
126{ 176{
127 flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_004 : dma2_014; 177 flexcop_ibi_value v = fc->read_ibi_reg(fc,ctrl_208);
128 flexcop_ibi_value v = fc->read_ibi_reg(fc,r);
129 178
130 flexcop_dma_remap(fc,dma_idx,0); 179 deb_rdump("reg: %03x: %x\n",ctrl_208,v.raw);
180 if (no & FC_DMA_1)
181 v.ctrl_208.DMA1_Size_IRQ_Enable_sig = onoff;
182
183 if (no & FC_DMA_2)
184 v.ctrl_208.DMA2_Size_IRQ_Enable_sig = onoff;
185
186 fc->write_ibi_reg(fc,ctrl_208,v);
187 deb_rdump("reg: %03x: %x\n",ctrl_208,v.raw);
131 188
132 v.dma_0x4_write.dmatimer = cycles >> 1;
133 fc->write_ibi_reg(fc,r,v);
134 return 0; 189 return 0;
135} 190}
136EXPORT_SYMBOL(flexcop_dma_config_timer); 191EXPORT_SYMBOL(flexcop_dma_control_packet_irq);
137 192
138int flexcop_dma_config_packet_count(struct flexcop_device *fc, flexcop_dma_index_t dma_idx, u8 packets) 193int flexcop_dma_config_packet_count(struct flexcop_device *fc,
194 flexcop_dma_index_t dma_idx,
195 u8 packets)
139{ 196{
140 flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_004 : dma2_014; 197 flexcop_ibi_register r = (dma_idx & FC_DMA_1) ? dma1_004 : dma2_014;
141 flexcop_ibi_value v = fc->read_ibi_reg(fc,r); 198 flexcop_ibi_value v = fc->read_ibi_reg(fc,r);
diff --git a/drivers/media/dvb/b2c2/flexcop-hw-filter.c b/drivers/media/dvb/b2c2/flexcop-hw-filter.c
index 2baf43d3ce8f..75cf237196eb 100644
--- a/drivers/media/dvb/b2c2/flexcop-hw-filter.c
+++ b/drivers/media/dvb/b2c2/flexcop-hw-filter.c
@@ -10,6 +10,8 @@
10static void flexcop_rcv_data_ctrl(struct flexcop_device *fc, int onoff) 10static void flexcop_rcv_data_ctrl(struct flexcop_device *fc, int onoff)
11{ 11{
12 flexcop_set_ibi_value(ctrl_208,Rcv_Data_sig,onoff); 12 flexcop_set_ibi_value(ctrl_208,Rcv_Data_sig,onoff);
13
14 deb_ts("rcv_data is now: '%s'\n",onoff ? "on" : "off");
13} 15}
14 16
15void flexcop_smc_ctrl(struct flexcop_device *fc, int onoff) 17void flexcop_smc_ctrl(struct flexcop_device *fc, int onoff)
@@ -151,7 +153,7 @@ int flexcop_pid_feed_control(struct flexcop_device *fc, struct dvb_demux_feed *d
151{ 153{
152 int max_pid_filter = 6 + fc->has_32_hw_pid_filter*32; 154 int max_pid_filter = 6 + fc->has_32_hw_pid_filter*32;
153 155
154 fc->feedcount += onoff ? 1 : -1; 156 fc->feedcount += onoff ? 1 : -1; /* the number of PIDs/Feed currently requested */
155 if (dvbdmxfeed->index >= max_pid_filter) 157 if (dvbdmxfeed->index >= max_pid_filter)
156 fc->extra_feedcount += onoff ? 1 : -1; 158 fc->extra_feedcount += onoff ? 1 : -1;
157 159
@@ -178,8 +180,14 @@ int flexcop_pid_feed_control(struct flexcop_device *fc, struct dvb_demux_feed *d
178 /* if it was the first or last feed request change the stream-status */ 180 /* if it was the first or last feed request change the stream-status */
179 if (fc->feedcount == onoff) { 181 if (fc->feedcount == onoff) {
180 flexcop_rcv_data_ctrl(fc,onoff); 182 flexcop_rcv_data_ctrl(fc,onoff);
181 if (fc->stream_control) 183 if (fc->stream_control) /* device specific stream control */
182 fc->stream_control(fc,onoff); 184 fc->stream_control(fc,onoff);
185
186 /* feeding stopped -> reset the flexcop filter*/
187 if (onoff == 0) {
188 flexcop_reset_block_300(fc);
189 flexcop_hw_filter_init(fc);
190 }
183 } 191 }
184 192
185 return 0; 193 return 0;
diff --git a/drivers/media/dvb/b2c2/flexcop-misc.c b/drivers/media/dvb/b2c2/flexcop-misc.c
index 23082545651f..3a08d38b318a 100644
--- a/drivers/media/dvb/b2c2/flexcop-misc.c
+++ b/drivers/media/dvb/b2c2/flexcop-misc.c
@@ -65,3 +65,15 @@ void flexcop_device_name(struct flexcop_device *fc,const char *prefix,const
65 flexcop_device_names[fc->dev_type],flexcop_bus_names[fc->bus_type], 65 flexcop_device_names[fc->dev_type],flexcop_bus_names[fc->bus_type],
66 flexcop_revision_names[fc->rev],suffix); 66 flexcop_revision_names[fc->rev],suffix);
67} 67}
68
69void flexcop_dump_reg(struct flexcop_device *fc, flexcop_ibi_register reg, int num)
70{
71 flexcop_ibi_value v;
72 int i;
73 for (i = 0; i < num; i++) {
74 v = fc->read_ibi_reg(fc,reg+4*i);
75 deb_rdump("0x%03x: %08x, ",reg+4*i, v.raw);
76 }
77 deb_rdump("\n");
78}
79EXPORT_SYMBOL(flexcop_dump_reg);
diff --git a/drivers/media/dvb/b2c2/flexcop-pci.c b/drivers/media/dvb/b2c2/flexcop-pci.c
index ed717c0073d5..2f76eb3fea40 100644
--- a/drivers/media/dvb/b2c2/flexcop-pci.c
+++ b/drivers/media/dvb/b2c2/flexcop-pci.c
@@ -13,6 +13,10 @@ static int enable_pid_filtering = 1;
13module_param(enable_pid_filtering, int, 0444); 13module_param(enable_pid_filtering, int, 0444);
14MODULE_PARM_DESC(enable_pid_filtering, "enable hardware pid filtering: supported values: 0 (fullts), 1"); 14MODULE_PARM_DESC(enable_pid_filtering, "enable hardware pid filtering: supported values: 0 (fullts), 1");
15 15
16static int irq_chk_intv;
17module_param(irq_chk_intv, int, 0644);
18MODULE_PARM_DESC(irq_chk_intv, "set the interval for IRQ watchdog (currently just debugging).");
19
16#ifdef CONFIG_DVB_B2C2_FLEXCOP_DEBUG 20#ifdef CONFIG_DVB_B2C2_FLEXCOP_DEBUG
17#define dprintk(level,args...) \ 21#define dprintk(level,args...) \
18 do { if ((debug & level)) printk(args); } while (0) 22 do { if ((debug & level)) printk(args); } while (0)
@@ -26,6 +30,7 @@ MODULE_PARM_DESC(enable_pid_filtering, "enable hardware pid filtering: supported
26#define deb_reg(args...) dprintk(0x02,args) 30#define deb_reg(args...) dprintk(0x02,args)
27#define deb_ts(args...) dprintk(0x04,args) 31#define deb_ts(args...) dprintk(0x04,args)
28#define deb_irq(args...) dprintk(0x08,args) 32#define deb_irq(args...) dprintk(0x08,args)
33#define deb_chk(args...) dprintk(0x10,args)
29 34
30static int debug = 0; 35static int debug = 0;
31module_param(debug, int, 0644); 36module_param(debug, int, 0644);
@@ -56,6 +61,10 @@ struct flexcop_pci {
56 61
57 spinlock_t irq_lock; 62 spinlock_t irq_lock;
58 63
64 unsigned long last_irq;
65
66 struct work_struct irq_check_work;
67
59 struct flexcop_device *fc_dev; 68 struct flexcop_device *fc_dev;
60}; 69};
61 70
@@ -88,18 +97,55 @@ static int flexcop_pci_write_ibi_reg(struct flexcop_device *fc, flexcop_ibi_regi
88 return 0; 97 return 0;
89} 98}
90 99
100static void flexcop_pci_irq_check_work(void *data)
101{
102 struct flexcop_pci *fc_pci = data;
103 struct flexcop_device *fc = fc_pci->fc_dev;
104
105 flexcop_ibi_value v = fc->read_ibi_reg(fc,sram_dest_reg_714);
106
107 flexcop_dump_reg(fc_pci->fc_dev,dma1_000,4);
108
109 if (v.sram_dest_reg_714.net_ovflow_error)
110 deb_chk("sram net_ovflow_error\n");
111 if (v.sram_dest_reg_714.media_ovflow_error)
112 deb_chk("sram media_ovflow_error\n");
113 if (v.sram_dest_reg_714.cai_ovflow_error)
114 deb_chk("sram cai_ovflow_error\n");
115 if (v.sram_dest_reg_714.cai_ovflow_error)
116 deb_chk("sram cai_ovflow_error\n");
117
118 schedule_delayed_work(&fc_pci->irq_check_work,
119 msecs_to_jiffies(irq_chk_intv < 100 ? 100 : irq_chk_intv));
120}
121
91/* When PID filtering is turned on, we use the timer IRQ, because small amounts 122/* When PID filtering is turned on, we use the timer IRQ, because small amounts
92 * of data need to be passed to the user space instantly as well. When PID 123 * of data need to be passed to the user space instantly as well. When PID
93 * filtering is turned off, we use the page-change-IRQ */ 124 * filtering is turned off, we use the page-change-IRQ */
94static irqreturn_t flexcop_pci_irq(int irq, void *dev_id, struct pt_regs *regs) 125static irqreturn_t flexcop_pci_isr(int irq, void *dev_id, struct pt_regs *regs)
95{ 126{
96 struct flexcop_pci *fc_pci = dev_id; 127 struct flexcop_pci *fc_pci = dev_id;
97 struct flexcop_device *fc = fc_pci->fc_dev; 128 struct flexcop_device *fc = fc_pci->fc_dev;
98 flexcop_ibi_value v = fc->read_ibi_reg(fc,irq_20c); 129 flexcop_ibi_value v;
99 irqreturn_t ret = IRQ_HANDLED; 130 irqreturn_t ret = IRQ_HANDLED;
100 131
101 spin_lock_irq(&fc_pci->irq_lock); 132 spin_lock_irq(&fc_pci->irq_lock);
102 133
134 v = fc->read_ibi_reg(fc,irq_20c);
135
136 /* errors */
137 if (v.irq_20c.Data_receiver_error)
138 deb_chk("data receiver error\n");
139 if (v.irq_20c.Continuity_error_flag)
140 deb_chk("Contunuity error flag is set\n");
141 if (v.irq_20c.LLC_SNAP_FLAG_set)
142 deb_chk("LLC_SNAP_FLAG_set is set\n");
143 if (v.irq_20c.Transport_Error)
144 deb_chk("Transport error\n");
145
146 if ((fc_pci->count % 1000) == 0)
147 deb_chk("%d valid irq took place so far\n",fc_pci->count);
148
103 if (v.irq_20c.DMA1_IRQ_Status == 1) { 149 if (v.irq_20c.DMA1_IRQ_Status == 1) {
104 if (fc_pci->active_dma1_addr == 0) 150 if (fc_pci->active_dma1_addr == 0)
105 flexcop_pass_dmx_packets(fc_pci->fc_dev,fc_pci->dma[0].cpu_addr0,fc_pci->dma[0].size / 188); 151 flexcop_pass_dmx_packets(fc_pci->fc_dev,fc_pci->dma[0].cpu_addr0,fc_pci->dma[0].size / 188);
@@ -115,8 +161,9 @@ static irqreturn_t flexcop_pci_irq(int irq, void *dev_id, struct pt_regs *regs)
115 fc->read_ibi_reg(fc,dma1_008).dma_0x8.dma_cur_addr << 2; 161 fc->read_ibi_reg(fc,dma1_008).dma_0x8.dma_cur_addr << 2;
116 u32 cur_pos = cur_addr - fc_pci->dma[0].dma_addr0; 162 u32 cur_pos = cur_addr - fc_pci->dma[0].dma_addr0;
117 163
118 deb_irq("irq: %08x cur_addr: %08x: cur_pos: %08x, last_cur_pos: %08x ", 164 deb_irq("%u irq: %08x cur_addr: %08x: cur_pos: %08x, last_cur_pos: %08x ",
119 v.raw,cur_addr,cur_pos,fc_pci->last_dma1_cur_pos); 165 jiffies_to_usecs(jiffies - fc_pci->last_irq),v.raw,cur_addr,cur_pos,fc_pci->last_dma1_cur_pos);
166 fc_pci->last_irq = jiffies;
120 167
121 /* buffer end was reached, restarted from the beginning 168 /* buffer end was reached, restarted from the beginning
122 * pass the data from last_cur_pos to the buffer end to the demux 169 * pass the data from last_cur_pos to the buffer end to the demux
@@ -127,7 +174,6 @@ static irqreturn_t flexcop_pci_irq(int irq, void *dev_id, struct pt_regs *regs)
127 fc_pci->dma[0].cpu_addr0 + fc_pci->last_dma1_cur_pos, 174 fc_pci->dma[0].cpu_addr0 + fc_pci->last_dma1_cur_pos,
128 (fc_pci->dma[0].size*2) - fc_pci->last_dma1_cur_pos); 175 (fc_pci->dma[0].size*2) - fc_pci->last_dma1_cur_pos);
129 fc_pci->last_dma1_cur_pos = 0; 176 fc_pci->last_dma1_cur_pos = 0;
130 fc_pci->count = 0;
131 } 177 }
132 178
133 if (cur_pos > fc_pci->last_dma1_cur_pos) { 179 if (cur_pos > fc_pci->last_dma1_cur_pos) {
@@ -139,16 +185,14 @@ static irqreturn_t flexcop_pci_irq(int irq, void *dev_id, struct pt_regs *regs)
139 deb_irq("\n"); 185 deb_irq("\n");
140 186
141 fc_pci->last_dma1_cur_pos = cur_pos; 187 fc_pci->last_dma1_cur_pos = cur_pos;
142 } else 188 fc_pci->count++;
189 } else {
190 deb_irq("isr for flexcop called, apparently without reason (%08x)\n",v.raw);
143 ret = IRQ_NONE; 191 ret = IRQ_NONE;
192 }
144 193
145 spin_unlock_irq(&fc_pci->irq_lock); 194 spin_unlock_irq(&fc_pci->irq_lock);
146 195
147/* packet count would be ideal for hw filtering, but it isn't working. Either
148 * the data book is wrong, or I'm unable to read it correctly */
149
150/* if (v.irq_20c.DMA1_Size_IRQ_Status == 1) { packet counter */
151
152 return ret; 196 return ret;
153} 197}
154 198
@@ -156,30 +200,35 @@ static int flexcop_pci_stream_control(struct flexcop_device *fc, int onoff)
156{ 200{
157 struct flexcop_pci *fc_pci = fc->bus_specific; 201 struct flexcop_pci *fc_pci = fc->bus_specific;
158 if (onoff) { 202 if (onoff) {
159 flexcop_dma_config(fc,&fc_pci->dma[0],FC_DMA_1,FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1); 203 flexcop_dma_config(fc,&fc_pci->dma[0],FC_DMA_1);
160 flexcop_dma_config(fc,&fc_pci->dma[1],FC_DMA_2,FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1); 204 flexcop_dma_config(fc,&fc_pci->dma[1],FC_DMA_2);
161 flexcop_dma_config_timer(fc,FC_DMA_1,1);
162 205
163 if (fc_pci->fc_dev->pid_filtering) { 206 flexcop_dma_config_timer(fc,FC_DMA_1,0);
164 fc_pci->last_dma1_cur_pos = 0;
165 flexcop_dma_control_timer_irq(fc,FC_DMA_1,1);
166 } else {
167 fc_pci->active_dma1_addr = 0;
168 flexcop_dma_control_size_irq(fc,FC_DMA_1,1);
169 }
170 207
171/* flexcop_dma_config_packet_count(fc,FC_DMA_1,0xc0); 208 flexcop_dma_xfer_control(fc,FC_DMA_1,FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1,1);
172 flexcop_dma_control_packet_irq(fc,FC_DMA_1,1); */ 209 deb_irq("DMA xfer enabled\n");
173 210
174 deb_irq("irqs enabled\n"); 211 fc_pci->last_dma1_cur_pos = 0;
212 flexcop_dma_control_timer_irq(fc,FC_DMA_1,1);
213 deb_irq("IRQ enabled\n");
214
215// fc_pci->active_dma1_addr = 0;
216// flexcop_dma_control_size_irq(fc,FC_DMA_1,1);
217
218 if (irq_chk_intv > 0)
219 schedule_delayed_work(&fc_pci->irq_check_work,
220 msecs_to_jiffies(irq_chk_intv < 100 ? 100 : irq_chk_intv));
175 } else { 221 } else {
176 if (fc_pci->fc_dev->pid_filtering) 222 if (irq_chk_intv > 0)
177 flexcop_dma_control_timer_irq(fc,FC_DMA_1,0); 223 cancel_delayed_work(&fc_pci->irq_check_work);
178 else 224
179 flexcop_dma_control_size_irq(fc,FC_DMA_1,0); 225 flexcop_dma_control_timer_irq(fc,FC_DMA_1,0);
226 deb_irq("IRQ disabled\n");
180 227
181// flexcop_dma_control_packet_irq(fc,FC_DMA_1,0); 228// flexcop_dma_control_size_irq(fc,FC_DMA_1,0);
182 deb_irq("irqs disabled\n"); 229
230 flexcop_dma_xfer_control(fc,FC_DMA_1,FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1,0);
231 deb_irq("DMA xfer disabled\n");
183 } 232 }
184 233
185 return 0; 234 return 0;
@@ -198,6 +247,7 @@ static int flexcop_pci_dma_init(struct flexcop_pci *fc_pci)
198 flexcop_sram_set_dest(fc_pci->fc_dev,FC_SRAM_DEST_CAO | FC_SRAM_DEST_CAI, FC_SRAM_DEST_TARGET_DMA2); 247 flexcop_sram_set_dest(fc_pci->fc_dev,FC_SRAM_DEST_CAO | FC_SRAM_DEST_CAI, FC_SRAM_DEST_TARGET_DMA2);
199 248
200 fc_pci->init_state |= FC_PCI_DMA_INIT; 249 fc_pci->init_state |= FC_PCI_DMA_INIT;
250
201 goto success; 251 goto success;
202dma1_free: 252dma1_free:
203 flexcop_dma_free(&fc_pci->dma[0]); 253 flexcop_dma_free(&fc_pci->dma[0]);
@@ -244,7 +294,7 @@ static int flexcop_pci_init(struct flexcop_pci *fc_pci)
244 294
245 pci_set_drvdata(fc_pci->pdev, fc_pci); 295 pci_set_drvdata(fc_pci->pdev, fc_pci);
246 296
247 if ((ret = request_irq(fc_pci->pdev->irq, flexcop_pci_irq, 297 if ((ret = request_irq(fc_pci->pdev->irq, flexcop_pci_isr,
248 SA_SHIRQ, DRIVER_NAME, fc_pci)) != 0) 298 SA_SHIRQ, DRIVER_NAME, fc_pci)) != 0)
249 goto err_pci_iounmap; 299 goto err_pci_iounmap;
250 300
@@ -324,6 +374,8 @@ static int flexcop_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
324 if ((ret = flexcop_pci_dma_init(fc_pci)) != 0) 374 if ((ret = flexcop_pci_dma_init(fc_pci)) != 0)
325 goto err_fc_exit; 375 goto err_fc_exit;
326 376
377 INIT_WORK(&fc_pci->irq_check_work, flexcop_pci_irq_check_work, fc_pci);
378
327 goto success; 379 goto success;
328err_fc_exit: 380err_fc_exit:
329 flexcop_device_exit(fc); 381 flexcop_device_exit(fc);
@@ -350,17 +402,17 @@ static void flexcop_pci_remove(struct pci_dev *pdev)
350 402
351static struct pci_device_id flexcop_pci_tbl[] = { 403static struct pci_device_id flexcop_pci_tbl[] = {
352 { PCI_DEVICE(0x13d0, 0x2103) }, 404 { PCI_DEVICE(0x13d0, 0x2103) },
353/* { PCI_DEVICE(0x13d0, 0x2200) }, PCI FlexCopIII ? */ 405/* { PCI_DEVICE(0x13d0, 0x2200) }, ? */
354 { }, 406 { },
355}; 407};
356 408
357MODULE_DEVICE_TABLE(pci, flexcop_pci_tbl); 409MODULE_DEVICE_TABLE(pci, flexcop_pci_tbl);
358 410
359static struct pci_driver flexcop_pci_driver = { 411static struct pci_driver flexcop_pci_driver = {
360 .name = "Technisat/B2C2 FlexCop II/IIb/III PCI", 412 .name = "b2c2_flexcop_pci",
361 .id_table = flexcop_pci_tbl, 413 .id_table = flexcop_pci_tbl,
362 .probe = flexcop_pci_probe, 414 .probe = flexcop_pci_probe,
363 .remove = flexcop_pci_remove, 415 .remove = flexcop_pci_remove,
364}; 416};
365 417
366static int __init flexcop_pci_module_init(void) 418static int __init flexcop_pci_module_init(void)
diff --git a/drivers/media/dvb/b2c2/flexcop-reg.h b/drivers/media/dvb/b2c2/flexcop-reg.h
index 75b50f21afe6..4ae1eb5bfe98 100644
--- a/drivers/media/dvb/b2c2/flexcop-reg.h
+++ b/drivers/media/dvb/b2c2/flexcop-reg.h
@@ -36,555 +36,21 @@ typedef enum {
36extern const char *flexcop_device_names[]; 36extern const char *flexcop_device_names[];
37 37
38/* FlexCop IBI Registers */ 38/* FlexCop IBI Registers */
39#if defined(__LITTLE_ENDIAN)
40 #include "flexcop_ibi_value_le.h"
41#elif defined(__BIG_ENDIAN)
42 #include "flexcop_ibi_value_be.h"
43#else
44 #error no endian defined
45#endif
39 46
40/* flexcop_ibi_reg - a huge union representing the register structure */
41typedef union {
42 u32 raw;
43
44/* DMA 0x000 to 0x01c
45 * DMA1 0x000 to 0x00c
46 * DMA2 0x010 to 0x01c
47 */
48 struct {
49 u32 dma_0start : 1; /* set: data will be delivered to dma1_address0 */
50 u32 dma_0No_update : 1; /* set: dma1_cur_address will be updated, unset: no update */
51 u32 dma_address0 :30; /* physical/virtual host memory address0 DMA */
52 } dma_0x0;
53
54 struct {
55 u32 DMA_maxpackets : 8; /* (remapped) PCI DMA1 Packet Count Interrupt. This variable
56 is able to be read and written while bit(1) of register
57 0x00c (remap_enable) is set. This variable represents
58 the number of packets that will be transmitted to the PCI
59 host using PCI DMA1 before an interrupt to the PCI is
60 asserted. This functionality may be enabled using bit(20)
61 of register 0x208. N=0 disables the IRQ. */
62 u32 dma_addr_size :24; /* size of memory buffer in DWORDs (bytesize / 4) for DMA */
63 } dma_0x4_remap;
64
65 struct {
66 u32 dma1timer : 7; /* reading PCI DMA1 timer ... when remap_enable is 0 */
67 u32 unused : 1;
68 u32 dma_addr_size :24;
69 } dma_0x4_read;
70
71 struct {
72 u32 unused : 1;
73 u32 dmatimer : 7; /* writing PCI DMA1 timer ... when remap_enable is 0 */
74 u32 dma_addr_size :24;
75 } dma_0x4_write;
76
77 struct {
78 u32 unused : 2;
79 u32 dma_cur_addr :30; /* current physical host memory address pointer for DMA */
80 } dma_0x8;
81
82 struct {
83 u32 dma_1start : 1; /* set: data will be delivered to dma_address1, when dma_address0 is full */
84 u32 remap_enable : 1; /* remap enable for 0x0x4(7:0) */
85 u32 dma_address1 :30; /* Physical/virtual address 1 on DMA */
86 } dma_0xc;
87
88/* Two-wire Serial Master and Clock 0x100-0x110 */
89 struct {
90// u32 slave_transmitter : 1; /* ???*/
91 u32 chipaddr : 7; /* two-line serial address of the target slave */
92 u32 reserved1 : 1;
93 u32 baseaddr : 8; /* address of the location of the read/write operation */
94 u32 data1_reg : 8; /* first byte in two-line serial read/write operation */
95 u32 working_start : 1; /* when doing a write operation this indicator is 0 when ready
96 * set to 1 when doing a write operation */
97 u32 twoWS_rw : 1; /* read/write indicator (1 = read, 0 write) */
98 u32 total_bytes : 2; /* number of data bytes in each two-line serial transaction (0 = 1 byte, 11 = 4byte)*/
99 u32 twoWS_port_reg : 2; /* port selection: 01 - Front End/Demod, 10 - EEPROM, 11 - Tuner */
100 u32 no_base_addr_ack_error : 1; /* writing: write-req: frame is produced w/o baseaddr, read-req: read-cycles w/o
101 * preceding address assignment write frame
102 * ACK_ERROR = 1 when no ACK from slave in the last transaction */
103 u32 st_done : 1; /* indicator for transaction is done */
104 } tw_sm_c_100;
105
106 struct {
107 u32 data2_reg : 8; /* 2nd data byte */
108 u32 data3_reg : 8; /* 3rd data byte */
109 u32 data4_reg : 8; /* 4th data byte */
110 u32 exlicit_stops : 1; /* when set, transactions are produced w/o trailing STOP flag, then send isolated STOP flags */
111 u32 force_stop : 1; /* isolated stop flag */
112 u32 unused : 6;
113 } tw_sm_c_104;
114
115/* Clock. The register allows the FCIII to convert an incoming Master clock
116 * (MCLK) signal into a lower frequency clock through the use of a LowCounter
117 * (TLO) and a High- Counter (THI). The time counts for THI and TLO are
118 * measured in MCLK; each count represents 4 MCLK input clock cycles.
119 *
120 * The default output for port #1 is set for Front End Demod communication. (0x108)
121 * The default output for port #2 is set for EEPROM communication. (0x10c)
122 * The default output for port #3 is set for Tuner communication. (0x110)
123 */
124 struct {
125 u32 thi1 : 6; /* Thi for port #1 (def: 100110b; 38) */
126 u32 reserved1 : 2;
127 u32 tlo1 : 5; /* Tlo for port #1 (def: 11100b; 28) */
128 u32 reserved2 :19;
129 } tw_sm_c_108;
130
131 struct {
132 u32 thi1 : 6; /* Thi for port #2 (def: 111001b; 57) */
133 u32 reserved1 : 2;
134 u32 tlo1 : 5; /* Tlo for port #2 (def: 11100b; 28) */
135 u32 reserved2 :19;
136 } tw_sm_c_10c;
137
138 struct {
139 u32 thi1 : 6; /* Thi for port #3 (def: 111001b; 57) */
140 u32 reserved1 : 2;
141 u32 tlo1 : 5; /* Tlo for port #3 (def: 11100b; 28) */
142 u32 reserved2 :19;
143 } tw_sm_c_110;
144
145/* LNB Switch Frequency 0x200
146 * Clock that creates the LNB switch tone. The default is set to have a fixed
147 * low output (not oscillating) to the LNB_CTL line.
148 */
149 struct {
150 u32 LNB_CTLHighCount_sig :15; /* It is the number of pre-scaled clock cycles that will be low. */
151 u32 LNB_CTLLowCount_sig :15; /* For example, to obtain a 22KHz output given a 45 Mhz Master
152 Clock signal (MCLK), set PreScalar=01 and LowCounter value to 0x1ff. */
153 u32 LNB_CTLPrescaler_sig : 2; /* pre-scaler divides MCLK: 00 (no division), 01 by 2, 10 by 4, 11 by 12 */
154 } lnb_switch_freq_200;
155
156/* ACPI, Peripheral Reset, LNB Polarity
157 * ACPI power conservation mode, LNB polarity selection (low or high voltage),
158 * and peripheral reset.
159 */
160 struct {
161 u32 ACPI1_sig : 1; /* turn of the power of tuner and LNB, not implemented in FCIII */
162 u32 ACPI3_sig : 1; /* turn of power of the complete satelite receiver board (except FCIII) */
163 u32 LNB_L_H_sig : 1; /* low or high voltage for LNB. (0 = low, 1 = high) */
164 u32 Per_reset_sig : 1; /* misc. init reset (default: 1), to reset set to low and back to high */
165 u32 reserved :20;
166 u32 Rev_N_sig_revision_hi : 4;/* 0xc in case of FCIII */
167 u32 Rev_N_sig_reserved1 : 2;
168 u32 Rev_N_sig_caps : 1; /* if 1, FCIII has 32 PID- and MAC-filters and is capable of IP multicast */
169 u32 Rev_N_sig_reserved2 : 1;
170 } misc_204;
171
172/* Control and Status 0x208 to 0x21c */
173/* Gross enable and disable control */
174 struct {
175 u32 Stream1_filter_sig : 1; /* Stream1 PID filtering */
176 u32 Stream2_filter_sig : 1; /* Stream2 PID filtering */
177 u32 PCR_filter_sig : 1; /* PCR PID filter */
178 u32 PMT_filter_sig : 1; /* PMT PID filter */
179
180 u32 EMM_filter_sig : 1; /* EMM PID filter */
181 u32 ECM_filter_sig : 1; /* ECM PID filter */
182 u32 Null_filter_sig : 1; /* Filters null packets, PID=0x1fff. */
183 u32 Mask_filter_sig : 1; /* mask PID filter */
184
185 u32 WAN_Enable_sig : 1; /* WAN output line through V8 memory space is activated. */
186 u32 WAN_CA_Enable_sig : 1; /* not in FCIII */
187 u32 CA_Enable_sig : 1; /* not in FCIII */
188 u32 SMC_Enable_sig : 1; /* CI stream data (CAI) goes directly to the smart card intf (opposed IBI 0x600 or SC-cmd buf). */
189
190 u32 Per_CA_Enable_sig : 1; /* not in FCIII */
191 u32 Multi2_Enable_sig : 1; /* ? */
192 u32 MAC_filter_Mode_sig : 1; /* (MAC_filter_enable) Globally enables MAC filters for Net PID filteres. */
193 u32 Rcv_Data_sig : 1; /* PID filtering module enable. When this bit is a one, the PID filter will
194 examine and process packets according to all other (individual) PID
195 filtering controls. If it a zero, no packet processing of any kind will
196 take place. All data from the tuner will be thrown away. */
197
198 u32 DMA1_IRQ_Enable_sig : 1; /* When set, a DWORD counter is enabled on PCI DMA1 that asserts the PCI
199 * interrupt after the specified count for filling the buffer. */
200 u32 DMA1_Timer_Enable_sig : 1; /* When set, a timer is enabled on PCI DMA1 that asserts the PCI interrupt
201 after a specified amount of time. */
202 u32 DMA2_IRQ_Enable_sig : 1; /* same as DMA1_IRQ_Enable_sig but for DMA2 */
203 u32 DMA2_Timer_Enable_sig : 1; /* same as DMA1_Timer_Enable_sig but for DMA2 */
204
205 u32 DMA1_Size_IRQ_Enable_sig : 1; /* When set, a packet count detector is enabled on PCI DMA1 that asserts the PCI interrupt. */
206 u32 DMA2_Size_IRQ_Enable_sig : 1; /* When set, a packet count detector is enabled on PCI DMA2 that asserts the PCI interrupt. */
207 u32 Mailbox_from_V8_Enable_sig: 1; /* When set, writes to the mailbox register produce an interrupt to the
208 PCI host to indicate that mailbox data is available. */
209
210 u32 unused : 9;
211 } ctrl_208;
212
213/* General status. When a PCI interrupt occurs, this register is read to
214 * discover the reason for the interrupt.
215 */
216 struct {
217 u32 DMA1_IRQ_Status : 1; /* When set(1) the DMA1 counter had generated an IRQ. Read Only. */
218 u32 DMA1_Timer_Status : 1; /* When set(1) the DMA1 timer had generated an IRQ. Read Only. */
219 u32 DMA2_IRQ_Status : 1; /* When set(1) the DMA2 counter had generated an IRQ. Read Only. */
220 u32 DMA2_Timer_Status : 1; /* When set(1) the DMA2 timer had generated an IRQ. Read Only. */
221 u32 DMA1_Size_IRQ_Status : 1; /* (Read only). This register is read after an interrupt to */
222 u32 DMA2_Size_IRQ_Status : 1; /* find out why we had an IRQ. Reading this register will clear this bit. Packet count*/
223 u32 Mailbox_from_V8_Status_sig: 1; /* Same as above. Reading this register will clear this bit. */
224 u32 Data_receiver_error : 1; /* 1 indicate an error in the receiver Front End (Tuner module) */
225 u32 Continuity_error_flag : 1; /* 1 indicates a continuity error in the TS stream. */
226 u32 LLC_SNAP_FLAG_set : 1; /* 1 indicates that the LCC_SNAP_FLAG was set. */
227 u32 Transport_Error : 1; /* When set indicates that an unexpected packet was received. */
228 u32 reserved :21;
229 } irq_20c;
230
231
232/* Software reset register */
233 struct {
234 u32 reset_blocks : 8; /* Enabled when Block_reset_enable = 0xB2 and 0x208 bits 15:8 = 0x00.
235 Each bit location represents a 0x100 block of registers. Writing
236 a one in a bit location resets that block of registers and the logic
237 that it controls. */
238 u32 Block_reset_enable : 8; /* This variable is set to 0xB2 when the register is written. */
239 u32 Special_controls :16; /* Asserts Reset_V8 => 0xC258; Turns on pci encryption => 0xC25A;
240 Turns off pci encryption => 0xC259 Note: pci_encryption default
241 at power-up is ON. */
242 } sw_reset_210;
243
244 struct {
245 u32 vuart_oe_sig : 1; /* When clear, the V8 processor has sole control of the serial UART
246 (RS-232 Smart Card interface). When set, the IBI interface
247 defined by register 0x600 controls the serial UART. */
248 u32 v2WS_oe_sig : 1; /* When clear, the V8 processor has direct control of the Two-line
249 Serial Master EEPROM target. When set, the Two-line Serial Master
250 EEPROM target interface is controlled by IBI register 0x100. */
251 u32 halt_V8_sig : 1; /* When set, contiguous wait states are applied to the V8-space
252 bus masters. Once this signal is cleared, normal V8-space
253 operations resume. */
254 u32 section_pkg_enable_sig: 1; /* When set, this signal enables the front end translation circuitry
255 to process section packed transport streams. */
256 u32 s2p_sel_sig : 1; /* Serial to parallel conversion. When set, polarized transport data
257 within the FlexCop3 front end circuitry is converted from a serial
258 stream into parallel data before downstream processing otherwise
259 interprets the data. */
260 u32 unused1 : 3;
261 u32 polarity_PS_CLK_sig: 1; /* This signal is used to invert the input polarity of the tranport
262 stream CLOCK signal before any processing occurs on the transport
263 stream within FlexCop3. */
264 u32 polarity_PS_VALID_sig: 1; /* This signal is used to invert the input polarity of the tranport
265 stream VALID signal before any processing occurs on the transport
266 stream within FlexCop3. */
267 u32 polarity_PS_SYNC_sig: 1; /* This signal is used to invert the input polarity of the tranport
268 stream SYNC signal before any processing occurs on the transport
269 stream within FlexCop3. */
270 u32 polarity_PS_ERR_sig: 1; /* This signal is used to invert the input polarity of the tranport
271 stream ERROR signal before any processing occurs on the transport
272 stream within FlexCop3. */
273 u32 unused2 :20;
274 } misc_214;
275
276/* Mailbox from V8 to host */
277 struct {
278 u32 Mailbox_from_V8 :32; /* When this register is written by either the V8 processor or by an
279 end host, an interrupt is generated to the PCI host to indicate
280 that mailbox data is available. Reading register 20c will clear
281 the IRQ. */
282 } mbox_v8_to_host_218;
283
284/* Mailbox from host to v8 Mailbox_to_V8
285 * Mailbox_to_V8 mailbox storage register
286 * used to send messages from PCI to V8. Writing to this register will send an
287 * IRQ to the V8. Then it can read the data from here. Reading this register
288 * will clear the IRQ. If the V8 is halted and bit 31 of this register is set,
289 * then this register is used instead as a direct interface to access the
290 * V8space memory.
291 */
292 struct {
293 u32 sysramaccess_data : 8; /* Data byte written or read from the specified address in V8 SysRAM. */
294 u32 sysramaccess_addr :15; /* 15 bit address used to access V8 Sys-RAM. */
295 u32 unused : 7;
296 u32 sysramaccess_write: 1; /* Write flag used to latch data into the V8 SysRAM. */
297 u32 sysramaccess_busmuster: 1; /* Setting this bit when the V8 is halted at 0x214 Bit(2) allows
298 this IBI register interface to directly drive the V8-space memory. */
299 } mbox_host_to_v8_21c;
300
301
302/* PIDs, Translation Bit, SMC Filter Select 0x300 to 0x31c */
303 struct {
304 u32 Stream1_PID :13; /* Primary use is receiving Net data, so these 13 bits normally
305 hold the PID value for the desired network stream. */
306 u32 Stream1_trans : 1; /* When set, Net translation will take place for Net data ferried in TS packets. */
307 u32 MAC_Multicast_filter : 1; /* When clear, multicast MAC filtering is not allowed for Stream1 and PID_n filters. */
308 u32 debug_flag_pid_saved : 1;
309 u32 Stream2_PID :13; /* 13 bits for Stream 2 PID filter value. General use. */
310 u32 Stream2_trans : 1; /* When set Tables/CAI translation will take place for the data ferried in
311 Stream2_PID TS packets. */
312 u32 debug_flag_write_status00 : 1;
313 u32 debug_fifo_problem : 1;
314 } pid_filter_300;
315
316 struct {
317 u32 PCR_PID :13; /* PCR stream PID filter value. Primary use is Program Clock Reference stream filtering. */
318 u32 PCR_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
319 u32 debug_overrun3 : 1;
320 u32 debug_overrun2 : 1;
321 u32 PMT_PID :13; /* stream PID filter value. Primary use is Program Management Table segment filtering. */
322 u32 PMT_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
323 u32 reserved : 2;
324 } pid_filter_304;
325
326 struct {
327 u32 EMM_PID :13; /* EMM PID filter value. Primary use is Entitlement Management Messaging for
328 conditional access-related data. */
329 u32 EMM_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
330 u32 EMM_filter_4 : 1; /* When set will pass only EMM data possessing the same ID code as the
331 first four bytes (32 bits) of the end-user s 6-byte Smart Card ID number Select */
332 u32 EMM_filter_6 : 1; /* When set will pass only EMM data possessing the same 6-byte code as the end-users
333 complete 6-byte Smart Card ID number. */
334 u32 ECM_PID :13; /* ECM PID filter value. Primary use is Entitlement Control Messaging for conditional
335 access-related data. */
336 u32 ECM_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
337 u32 reserved : 2;
338 } pid_filter_308;
339
340 struct {
341 u32 Group_PID :13; /* PID value for group filtering. */
342 u32 Group_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */
343 u32 unused1 : 2;
344 u32 Group_mask :13; /* Mask value used in logical "and" equation that defines group filtering */
345 u32 unused2 : 3;
346 } pid_filter_30c_ext_ind_0_7;
347
348 struct {
349 u32 net_master_read :17;
350 u32 unused :15;
351 } pid_filter_30c_ext_ind_1;
352
353 struct {
354 u32 net_master_write :17;
355 u32 unused :15;
356 } pid_filter_30c_ext_ind_2;
357
358 struct {
359 u32 next_net_master_write :17;
360 u32 unused :15;
361 } pid_filter_30c_ext_ind_3;
362
363 struct {
364 u32 unused1 : 1;
365 u32 state_write :10;
366 u32 reserved1 : 6; /* default: 000100 */
367 u32 stack_read :10;
368 u32 reserved2 : 5; /* default: 00100 */
369 } pid_filter_30c_ext_ind_4;
370
371 struct {
372 u32 stack_cnt :10;
373 u32 unused :22;
374 } pid_filter_30c_ext_ind_5;
375
376 struct {
377 u32 pid_fsm_save_reg0 : 2;
378 u32 pid_fsm_save_reg1 : 2;
379 u32 pid_fsm_save_reg2 : 2;
380 u32 pid_fsm_save_reg3 : 2;
381 u32 pid_fsm_save_reg4 : 2;
382 u32 pid_fsm_save_reg300 : 2;
383 u32 write_status1 : 2;
384 u32 write_status4 : 2;
385 u32 data_size_reg :12;
386 u32 unused : 4;
387 } pid_filter_30c_ext_ind_6;
388
389 struct {
390 u32 index_reg : 5; /* (Index pointer) Points at an internal PIDn register. A binary code
391 representing one of 32 internal PIDn registers as well as its
392 corresponding internal MAC_lown register. */
393 u32 extra_index_reg : 3; /* This vector is used to select between sets of debug signals routed to register 0x30c. */
394 u32 AB_select : 1; /* Used in conjunction with 0x31c. read/write to the MAC_highA or MAC_highB register
395 0=MAC_highB register, 1=MAC_highA */
396 u32 pass_alltables : 1; /* 1=Net packets are not filtered against the Network Table ID found in register 0x400.
397 All types of networks (DVB, ATSC, ISDB) are passed. */
398 u32 unused :22;
399 } index_reg_310;
400
401 struct {
402 u32 PID :13; /* PID value */
403 u32 PID_trans : 1; /* translation will take place for packets filtered */
404 u32 PID_enable_bit : 1; /* When set this PID filter is enabled */
405 u32 reserved :17;
406 } pid_n_reg_314;
407
408 struct {
409 u32 A4_byte : 8;
410 u32 A5_byte : 8;
411 u32 A6_byte : 8;
412 u32 Enable_bit : 1; /* enabled (1) or disabled (1) */
413 u32 HighAB_bit : 1; /* use MAC_highA (1) or MAC_highB (0) as MSB */
414 u32 reserved : 6;
415 } mac_low_reg_318;
416
417 struct {
418 u32 A1_byte : 8;
419 u32 A2_byte : 8;
420 u32 A3_byte : 8;
421 u32 reserved : 8;
422 } mac_high_reg_31c;
423
424/* Table, SMCID,MACDestination Filters 0x400 to 0x41c */
425 struct {
426 u32 reserved :16;
427#define fc_data_Tag_ID_DVB 0x3e 47#define fc_data_Tag_ID_DVB 0x3e
428#define fc_data_Tag_ID_ATSC 0x3f 48#define fc_data_Tag_ID_ATSC 0x3f
429#define fc_data_Tag_ID_IDSB 0x8b 49#define fc_data_Tag_ID_IDSB 0x8b
430 u32 data_Tag_ID :16;
431 } data_tag_400;
432
433 struct {
434 u32 Card_IDbyte6 : 8;
435 u32 Card_IDbyte5 : 8;
436 u32 Card_IDbyte4 : 8;
437 u32 Card_IDbyte3 : 8;
438 } card_id_408;
439
440 struct {
441 u32 Card_IDbyte2 : 8;
442 u32 Card_IDbyte1 : 8;
443 } card_id_40c;
444
445 /* holding the unique mac address of the receiver which houses the FlexCopIII */
446 struct {
447 u32 MAC1 : 8;
448 u32 MAC2 : 8;
449 u32 MAC3 : 8;
450 u32 MAC6 : 8;
451 } mac_address_418;
452
453 struct {
454 u32 MAC7 : 8;
455 u32 MAC8 : 8;
456 u32 reserved : 16;
457 } mac_address_41c;
458
459 struct {
460 u32 transmitter_data_byte : 8;
461 u32 ReceiveDataReady : 1;
462 u32 ReceiveByteFrameError: 1;
463 u32 txbuffempty : 1;
464 u32 reserved :21;
465 } ci_600;
466
467 struct {
468 u32 pi_d : 8;
469 u32 pi_ha :20;
470 u32 pi_rw : 1;
471 u32 pi_component_reg : 3;
472 } pi_604;
473
474 struct {
475 u32 serialReset : 1;
476 u32 oncecycle_read : 1;
477 u32 Timer_Read_req : 1;
478 u32 Timer_Load_req : 1;
479 u32 timer_data : 7;
480 u32 unused : 1; /* ??? not mentioned in data book */
481 u32 Timer_addr : 5;
482 u32 reserved : 3;
483 u32 pcmcia_a_mod_pwr_n : 1;
484 u32 pcmcia_b_mod_pwr_n : 1;
485 u32 config_Done_stat : 1;
486 u32 config_Init_stat : 1;
487 u32 config_Prog_n : 1;
488 u32 config_wr_n : 1;
489 u32 config_cs_n : 1;
490 u32 config_cclk : 1;
491 u32 pi_CiMax_IRQ_n : 1;
492 u32 pi_timeout_status : 1;
493 u32 pi_wait_n : 1;
494 u32 pi_busy_n : 1;
495 } pi_608;
496 50
497 struct {
498 u32 PID :13;
499 u32 key_enable : 1;
500#define fc_key_code_default 0x1 51#define fc_key_code_default 0x1
501#define fc_key_code_even 0x2 52#define fc_key_code_even 0x2
502#define fc_key_code_odd 0x3 53#define fc_key_code_odd 0x3
503 u32 key_code : 2;
504 u32 key_array_col : 3;
505 u32 key_array_row : 5;
506 u32 dvb_en : 1; /* 0=TS bypasses the Descrambler */
507 u32 rw_flag : 1;
508 u32 reserved : 6;
509 } dvb_reg_60c;
510
511/* SRAM and Output Destination 0x700 to 0x714 */
512 struct {
513 u32 sram_addr :15;
514 u32 sram_rw : 1; /* 0=write, 1=read */
515 u32 sram_data : 8;
516 u32 sc_xfer_bit : 1;
517 u32 reserved1 : 3;
518 u32 oe_pin_reg : 1;
519 u32 ce_pin_reg : 1;
520 u32 reserved2 : 1;
521 u32 start_sram_ibi : 1;
522 } sram_ctrl_reg_700;
523
524 struct {
525 u32 net_addr_read :16;
526 u32 net_addr_write :16;
527 } net_buf_reg_704;
528
529 struct {
530 u32 cai_read :11;
531 u32 reserved1 : 5;
532 u32 cai_write :11;
533 u32 reserved2 : 6;
534 u32 cai_cnt : 4;
535 } cai_buf_reg_708;
536
537 struct {
538 u32 cao_read :11;
539 u32 reserved1 : 5;
540 u32 cap_write :11;
541 u32 reserved2 : 6;
542 u32 cao_cnt : 4;
543 } cao_buf_reg_70c;
544
545 struct {
546 u32 media_read :11;
547 u32 reserved1 : 5;
548 u32 media_write :11;
549 u32 reserved2 : 6;
550 u32 media_cnt : 4;
551 } media_buf_reg_710;
552
553 struct {
554 u32 NET_Dest : 2;
555 u32 CAI_Dest : 2;
556 u32 CAO_Dest : 2;
557 u32 MEDIA_Dest : 2;
558 u32 net_ovflow_error : 1;
559 u32 media_ovflow_error : 1;
560 u32 cai_ovflow_error : 1;
561 u32 cao_ovflow_error : 1;
562 u32 ctrl_usb_wan : 1;
563 u32 ctrl_sramdma : 1;
564 u32 ctrl_maximumfill : 1;
565 u32 reserved :17;
566 } sram_dest_reg_714;
567
568 struct {
569 u32 net_cnt :12;
570 u32 reserved1 : 4;
571 u32 net_addr_read : 1;
572 u32 reserved2 : 3;
573 u32 net_addr_write : 1;
574 u32 reserved3 :11;
575 } net_buf_reg_718;
576
577 struct {
578 u32 wan_speed_sig : 2;
579 u32 reserved1 : 6;
580 u32 wan_wait_state : 8;
581 u32 sram_chip : 2;
582 u32 sram_memmap : 2;
583 u32 reserved2 : 4;
584 u32 wan_pkt_frame : 4;
585 u32 reserved3 : 4;
586 } wan_ctrl_reg_71c;
587} flexcop_ibi_value;
588 54
589extern flexcop_ibi_value ibi_zero; 55extern flexcop_ibi_value ibi_zero;
590 56
diff --git a/drivers/media/dvb/b2c2/flexcop-usb.c b/drivers/media/dvb/b2c2/flexcop-usb.c
index 0113449abd15..0a78ba3737a5 100644
--- a/drivers/media/dvb/b2c2/flexcop-usb.c
+++ b/drivers/media/dvb/b2c2/flexcop-usb.c
@@ -545,7 +545,7 @@ static struct usb_device_id flexcop_usb_table [] = {
545/* usb specific object needed to register this driver with the usb subsystem */ 545/* usb specific object needed to register this driver with the usb subsystem */
546static struct usb_driver flexcop_usb_driver = { 546static struct usb_driver flexcop_usb_driver = {
547 .owner = THIS_MODULE, 547 .owner = THIS_MODULE,
548 .name = "Technisat/B2C2 FlexCop II/IIb/III USB", 548 .name = "b2c2_flexcop_usb",
549 .probe = flexcop_usb_probe, 549 .probe = flexcop_usb_probe,
550 .disconnect = flexcop_usb_disconnect, 550 .disconnect = flexcop_usb_disconnect,
551 .id_table = flexcop_usb_table, 551 .id_table = flexcop_usb_table,
diff --git a/drivers/media/dvb/b2c2/flexcop.c b/drivers/media/dvb/b2c2/flexcop.c
index 8b5d14dd36e3..12873d435406 100644
--- a/drivers/media/dvb/b2c2/flexcop.c
+++ b/drivers/media/dvb/b2c2/flexcop.c
@@ -46,7 +46,7 @@
46 46
47int b2c2_flexcop_debug; 47int b2c2_flexcop_debug;
48module_param_named(debug, b2c2_flexcop_debug, int, 0644); 48module_param_named(debug, b2c2_flexcop_debug, int, 0644);
49MODULE_PARM_DESC(debug, "set debug level (1=info,2=tuner,4=i2c,8=ts,16=sram (|-able))." DEBSTATUS); 49MODULE_PARM_DESC(debug, "set debug level (1=info,2=tuner,4=i2c,8=ts,16=sram,32=reg (|-able))." DEBSTATUS);
50#undef DEBSTATUS 50#undef DEBSTATUS
51 51
52/* global zero for ibi values */ 52/* global zero for ibi values */
@@ -173,9 +173,20 @@ static void flexcop_reset(struct flexcop_device *fc)
173 fc->write_ibi_reg(fc,ctrl_208,ibi_zero); 173 fc->write_ibi_reg(fc,ctrl_208,ibi_zero);
174 174
175 v210.raw = 0; 175 v210.raw = 0;
176 v210.sw_reset_210.reset_blocks = 0xff; 176 v210.sw_reset_210.reset_block_000 = 1;
177 v210.sw_reset_210.reset_block_100 = 1;
178 v210.sw_reset_210.reset_block_200 = 1;
179 v210.sw_reset_210.reset_block_300 = 1;
180 v210.sw_reset_210.reset_block_400 = 1;
181 v210.sw_reset_210.reset_block_500 = 1;
182 v210.sw_reset_210.reset_block_600 = 1;
183 v210.sw_reset_210.reset_block_700 = 1;
177 v210.sw_reset_210.Block_reset_enable = 0xb2; 184 v210.sw_reset_210.Block_reset_enable = 0xb2;
185
186 v210.sw_reset_210.Special_controls = 0xc259;
187
178 fc->write_ibi_reg(fc,sw_reset_210,v210); 188 fc->write_ibi_reg(fc,sw_reset_210,v210);
189 msleep(1);
179 190
180/* reset the periphical devices */ 191/* reset the periphical devices */
181 192
@@ -186,6 +197,25 @@ static void flexcop_reset(struct flexcop_device *fc)
186 fc->write_ibi_reg(fc,misc_204,v204); 197 fc->write_ibi_reg(fc,misc_204,v204);
187} 198}
188 199
200void flexcop_reset_block_300(struct flexcop_device *fc)
201{
202 flexcop_ibi_value v208_save = fc->read_ibi_reg(fc,ctrl_208),
203 v210 = fc->read_ibi_reg(fc,sw_reset_210);
204
205 deb_rdump("208: %08x, 210: %08x\n",v208_save.raw,v210.raw);
206
207 fc->write_ibi_reg(fc,ctrl_208,ibi_zero);
208
209 v210.sw_reset_210.reset_block_300 = 1;
210 v210.sw_reset_210.Block_reset_enable = 0xb2;
211
212 fc->write_ibi_reg(fc,sw_reset_210,v210);
213 msleep(1);
214
215 fc->write_ibi_reg(fc,ctrl_208,v208_save);
216}
217EXPORT_SYMBOL(flexcop_reset_block_300);
218
189struct flexcop_device *flexcop_device_kmalloc(size_t bus_specific_len) 219struct flexcop_device *flexcop_device_kmalloc(size_t bus_specific_len)
190{ 220{
191 void *bus; 221 void *bus;
diff --git a/drivers/media/dvb/b2c2/flexcop.h b/drivers/media/dvb/b2c2/flexcop.h
index caa343a97bdc..0cebe1d92e0b 100644
--- a/drivers/media/dvb/b2c2/flexcop.h
+++ b/drivers/media/dvb/b2c2/flexcop.h
@@ -26,5 +26,6 @@ extern int b2c2_flexcop_debug;
26#define deb_i2c(args...) dprintk(0x04,args) 26#define deb_i2c(args...) dprintk(0x04,args)
27#define deb_ts(args...) dprintk(0x08,args) 27#define deb_ts(args...) dprintk(0x08,args)
28#define deb_sram(args...) dprintk(0x10,args) 28#define deb_sram(args...) dprintk(0x10,args)
29#define deb_rdump(args...) dprintk(0x20,args)
29 30
30#endif 31#endif
diff --git a/drivers/media/dvb/b2c2/flexcop_ibi_value_be.h b/drivers/media/dvb/b2c2/flexcop_ibi_value_be.h
new file mode 100644
index 000000000000..ed9a6756b194
--- /dev/null
+++ b/drivers/media/dvb/b2c2/flexcop_ibi_value_be.h
@@ -0,0 +1,458 @@
1/* This file is part of linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
2 *
3 * register descriptions
4 *
5 * see flexcop.c for copyright information.
6 */
7
8/* This file is automatically generated, do not edit things here. */
9#ifndef __FLEXCOP_IBI_VALUE_INCLUDED__
10#define __FLEXCOP_IBI_VALUE_INCLUDED__
11
12typedef union {
13 u32 raw;
14
15 struct {
16 u32 dma_address0 :30;
17 u32 dma_0No_update : 1;
18 u32 dma_0start : 1;
19 } dma_0x0;
20
21 struct {
22 u32 dma_addr_size :24;
23 u32 DMA_maxpackets : 8;
24 } dma_0x4_remap;
25
26 struct {
27 u32 dma_addr_size :24;
28 u32 unused : 1;
29 u32 dma1timer : 7;
30 } dma_0x4_read;
31
32 struct {
33 u32 dma_addr_size :24;
34 u32 dmatimer : 7;
35 u32 unused : 1;
36 } dma_0x4_write;
37
38 struct {
39 u32 dma_cur_addr :30;
40 u32 unused : 2;
41 } dma_0x8;
42
43 struct {
44 u32 dma_address1 :30;
45 u32 remap_enable : 1;
46 u32 dma_1start : 1;
47 } dma_0xc;
48
49 struct {
50 u32 st_done : 1;
51 u32 no_base_addr_ack_error : 1;
52 u32 twoWS_port_reg : 2;
53 u32 total_bytes : 2;
54 u32 twoWS_rw : 1;
55 u32 working_start : 1;
56 u32 data1_reg : 8;
57 u32 baseaddr : 8;
58 u32 reserved1 : 1;
59 u32 chipaddr : 7;
60 } tw_sm_c_100;
61
62 struct {
63 u32 unused : 6;
64 u32 force_stop : 1;
65 u32 exlicit_stops : 1;
66 u32 data4_reg : 8;
67 u32 data3_reg : 8;
68 u32 data2_reg : 8;
69 } tw_sm_c_104;
70
71 struct {
72 u32 reserved2 :19;
73 u32 tlo1 : 5;
74 u32 reserved1 : 2;
75 u32 thi1 : 6;
76 } tw_sm_c_108;
77
78 struct {
79 u32 reserved2 :19;
80 u32 tlo1 : 5;
81 u32 reserved1 : 2;
82 u32 thi1 : 6;
83 } tw_sm_c_10c;
84
85 struct {
86 u32 reserved2 :19;
87 u32 tlo1 : 5;
88 u32 reserved1 : 2;
89 u32 thi1 : 6;
90 } tw_sm_c_110;
91
92 struct {
93 u32 LNB_CTLPrescaler_sig : 2;
94 u32 LNB_CTLLowCount_sig :15;
95 u32 LNB_CTLHighCount_sig :15;
96 } lnb_switch_freq_200;
97
98 struct {
99 u32 Rev_N_sig_reserved2 : 1;
100 u32 Rev_N_sig_caps : 1;
101 u32 Rev_N_sig_reserved1 : 2;
102 u32 Rev_N_sig_revision_hi : 4;
103 u32 reserved :20;
104 u32 Per_reset_sig : 1;
105 u32 LNB_L_H_sig : 1;
106 u32 ACPI3_sig : 1;
107 u32 ACPI1_sig : 1;
108 } misc_204;
109
110 struct {
111 u32 unused : 9;
112 u32 Mailbox_from_V8_Enable_sig : 1;
113 u32 DMA2_Size_IRQ_Enable_sig : 1;
114 u32 DMA1_Size_IRQ_Enable_sig : 1;
115 u32 DMA2_Timer_Enable_sig : 1;
116 u32 DMA2_IRQ_Enable_sig : 1;
117 u32 DMA1_Timer_Enable_sig : 1;
118 u32 DMA1_IRQ_Enable_sig : 1;
119 u32 Rcv_Data_sig : 1;
120 u32 MAC_filter_Mode_sig : 1;
121 u32 Multi2_Enable_sig : 1;
122 u32 Per_CA_Enable_sig : 1;
123 u32 SMC_Enable_sig : 1;
124 u32 CA_Enable_sig : 1;
125 u32 WAN_CA_Enable_sig : 1;
126 u32 WAN_Enable_sig : 1;
127 u32 Mask_filter_sig : 1;
128 u32 Null_filter_sig : 1;
129 u32 ECM_filter_sig : 1;
130 u32 EMM_filter_sig : 1;
131 u32 PMT_filter_sig : 1;
132 u32 PCR_filter_sig : 1;
133 u32 Stream2_filter_sig : 1;
134 u32 Stream1_filter_sig : 1;
135 } ctrl_208;
136
137 struct {
138 u32 reserved :21;
139 u32 Transport_Error : 1;
140 u32 LLC_SNAP_FLAG_set : 1;
141 u32 Continuity_error_flag : 1;
142 u32 Data_receiver_error : 1;
143 u32 Mailbox_from_V8_Status_sig : 1;
144 u32 DMA2_Size_IRQ_Status : 1;
145 u32 DMA1_Size_IRQ_Status : 1;
146 u32 DMA2_Timer_Status : 1;
147 u32 DMA2_IRQ_Status : 1;
148 u32 DMA1_Timer_Status : 1;
149 u32 DMA1_IRQ_Status : 1;
150 } irq_20c;
151
152 struct {
153 u32 Special_controls :16;
154 u32 Block_reset_enable : 8;
155 u32 reset_block_700 : 1;
156 u32 reset_block_600 : 1;
157 u32 reset_block_500 : 1;
158 u32 reset_block_400 : 1;
159 u32 reset_block_300 : 1;
160 u32 reset_block_200 : 1;
161 u32 reset_block_100 : 1;
162 u32 reset_block_000 : 1;
163 } sw_reset_210;
164
165 struct {
166 u32 unused2 :20;
167 u32 polarity_PS_ERR_sig : 1;
168 u32 polarity_PS_SYNC_sig : 1;
169 u32 polarity_PS_VALID_sig : 1;
170 u32 polarity_PS_CLK_sig : 1;
171 u32 unused1 : 3;
172 u32 s2p_sel_sig : 1;
173 u32 section_pkg_enable_sig : 1;
174 u32 halt_V8_sig : 1;
175 u32 v2WS_oe_sig : 1;
176 u32 vuart_oe_sig : 1;
177 } misc_214;
178
179 struct {
180 u32 Mailbox_from_V8 :32;
181 } mbox_v8_to_host_218;
182
183 struct {
184 u32 sysramaccess_busmuster : 1;
185 u32 sysramaccess_write : 1;
186 u32 unused : 7;
187 u32 sysramaccess_addr :15;
188 u32 sysramaccess_data : 8;
189 } mbox_host_to_v8_21c;
190
191 struct {
192 u32 debug_fifo_problem : 1;
193 u32 debug_flag_write_status00 : 1;
194 u32 Stream2_trans : 1;
195 u32 Stream2_PID :13;
196 u32 debug_flag_pid_saved : 1;
197 u32 MAC_Multicast_filter : 1;
198 u32 Stream1_trans : 1;
199 u32 Stream1_PID :13;
200 } pid_filter_300;
201
202 struct {
203 u32 reserved : 2;
204 u32 PMT_trans : 1;
205 u32 PMT_PID :13;
206 u32 debug_overrun2 : 1;
207 u32 debug_overrun3 : 1;
208 u32 PCR_trans : 1;
209 u32 PCR_PID :13;
210 } pid_filter_304;
211
212 struct {
213 u32 reserved : 2;
214 u32 ECM_trans : 1;
215 u32 ECM_PID :13;
216 u32 EMM_filter_6 : 1;
217 u32 EMM_filter_4 : 1;
218 u32 EMM_trans : 1;
219 u32 EMM_PID :13;
220 } pid_filter_308;
221
222 struct {
223 u32 unused2 : 3;
224 u32 Group_mask :13;
225 u32 unused1 : 2;
226 u32 Group_trans : 1;
227 u32 Group_PID :13;
228 } pid_filter_30c_ext_ind_0_7;
229
230 struct {
231 u32 unused :15;
232 u32 net_master_read :17;
233 } pid_filter_30c_ext_ind_1;
234
235 struct {
236 u32 unused :15;
237 u32 net_master_write :17;
238 } pid_filter_30c_ext_ind_2;
239
240 struct {
241 u32 unused :15;
242 u32 next_net_master_write :17;
243 } pid_filter_30c_ext_ind_3;
244
245 struct {
246 u32 reserved2 : 5;
247 u32 stack_read :10;
248 u32 reserved1 : 6;
249 u32 state_write :10;
250 u32 unused1 : 1;
251 } pid_filter_30c_ext_ind_4;
252
253 struct {
254 u32 unused :22;
255 u32 stack_cnt :10;
256 } pid_filter_30c_ext_ind_5;
257
258 struct {
259 u32 unused : 4;
260 u32 data_size_reg :12;
261 u32 write_status4 : 2;
262 u32 write_status1 : 2;
263 u32 pid_fsm_save_reg300 : 2;
264 u32 pid_fsm_save_reg4 : 2;
265 u32 pid_fsm_save_reg3 : 2;
266 u32 pid_fsm_save_reg2 : 2;
267 u32 pid_fsm_save_reg1 : 2;
268 u32 pid_fsm_save_reg0 : 2;
269 } pid_filter_30c_ext_ind_6;
270
271 struct {
272 u32 unused :22;
273 u32 pass_alltables : 1;
274 u32 AB_select : 1;
275 u32 extra_index_reg : 3;
276 u32 index_reg : 5;
277 } index_reg_310;
278
279 struct {
280 u32 reserved :17;
281 u32 PID_enable_bit : 1;
282 u32 PID_trans : 1;
283 u32 PID :13;
284 } pid_n_reg_314;
285
286 struct {
287 u32 reserved : 6;
288 u32 HighAB_bit : 1;
289 u32 Enable_bit : 1;
290 u32 A6_byte : 8;
291 u32 A5_byte : 8;
292 u32 A4_byte : 8;
293 } mac_low_reg_318;
294
295 struct {
296 u32 reserved : 8;
297 u32 A3_byte : 8;
298 u32 A2_byte : 8;
299 u32 A1_byte : 8;
300 } mac_high_reg_31c;
301
302 struct {
303 u32 data_Tag_ID :16;
304 u32 reserved :16;
305 } data_tag_400;
306
307 struct {
308 u32 Card_IDbyte3 : 8;
309 u32 Card_IDbyte4 : 8;
310 u32 Card_IDbyte5 : 8;
311 u32 Card_IDbyte6 : 8;
312 } card_id_408;
313
314 struct {
315 u32 Card_IDbyte1 : 8;
316 u32 Card_IDbyte2 : 8;
317 } card_id_40c;
318
319 struct {
320 u32 MAC6 : 8;
321 u32 MAC3 : 8;
322 u32 MAC2 : 8;
323 u32 MAC1 : 8;
324 } mac_address_418;
325
326 struct {
327 u32 reserved :16;
328 u32 MAC8 : 8;
329 u32 MAC7 : 8;
330 } mac_address_41c;
331
332 struct {
333 u32 reserved :21;
334 u32 txbuffempty : 1;
335 u32 ReceiveByteFrameError : 1;
336 u32 ReceiveDataReady : 1;
337 u32 transmitter_data_byte : 8;
338 } ci_600;
339
340 struct {
341 u32 pi_component_reg : 3;
342 u32 pi_rw : 1;
343 u32 pi_ha :20;
344 u32 pi_d : 8;
345 } pi_604;
346
347 struct {
348 u32 pi_busy_n : 1;
349 u32 pi_wait_n : 1;
350 u32 pi_timeout_status : 1;
351 u32 pi_CiMax_IRQ_n : 1;
352 u32 config_cclk : 1;
353 u32 config_cs_n : 1;
354 u32 config_wr_n : 1;
355 u32 config_Prog_n : 1;
356 u32 config_Init_stat : 1;
357 u32 config_Done_stat : 1;
358 u32 pcmcia_b_mod_pwr_n : 1;
359 u32 pcmcia_a_mod_pwr_n : 1;
360 u32 reserved : 3;
361 u32 Timer_addr : 5;
362 u32 unused : 1;
363 u32 timer_data : 7;
364 u32 Timer_Load_req : 1;
365 u32 Timer_Read_req : 1;
366 u32 oncecycle_read : 1;
367 u32 serialReset : 1;
368 } pi_608;
369
370 struct {
371 u32 reserved : 6;
372 u32 rw_flag : 1;
373 u32 dvb_en : 1;
374 u32 key_array_row : 5;
375 u32 key_array_col : 3;
376 u32 key_code : 2;
377 u32 key_enable : 1;
378 u32 PID :13;
379 } dvb_reg_60c;
380
381 struct {
382 u32 start_sram_ibi : 1;
383 u32 reserved2 : 1;
384 u32 ce_pin_reg : 1;
385 u32 oe_pin_reg : 1;
386 u32 reserved1 : 3;
387 u32 sc_xfer_bit : 1;
388 u32 sram_data : 8;
389 u32 sram_rw : 1;
390 u32 sram_addr :15;
391 } sram_ctrl_reg_700;
392
393 struct {
394 u32 net_addr_write :16;
395 u32 net_addr_read :16;
396 } net_buf_reg_704;
397
398 struct {
399 u32 cai_cnt : 4;
400 u32 reserved2 : 6;
401 u32 cai_write :11;
402 u32 reserved1 : 5;
403 u32 cai_read :11;
404 } cai_buf_reg_708;
405
406 struct {
407 u32 cao_cnt : 4;
408 u32 reserved2 : 6;
409 u32 cap_write :11;
410 u32 reserved1 : 5;
411 u32 cao_read :11;
412 } cao_buf_reg_70c;
413
414 struct {
415 u32 media_cnt : 4;
416 u32 reserved2 : 6;
417 u32 media_write :11;
418 u32 reserved1 : 5;
419 u32 media_read :11;
420 } media_buf_reg_710;
421
422 struct {
423 u32 reserved :17;
424 u32 ctrl_maximumfill : 1;
425 u32 ctrl_sramdma : 1;
426 u32 ctrl_usb_wan : 1;
427 u32 cao_ovflow_error : 1;
428 u32 cai_ovflow_error : 1;
429 u32 media_ovflow_error : 1;
430 u32 net_ovflow_error : 1;
431 u32 MEDIA_Dest : 2;
432 u32 CAO_Dest : 2;
433 u32 CAI_Dest : 2;
434 u32 NET_Dest : 2;
435 } sram_dest_reg_714;
436
437 struct {
438 u32 reserved3 :11;
439 u32 net_addr_write : 1;
440 u32 reserved2 : 3;
441 u32 net_addr_read : 1;
442 u32 reserved1 : 4;
443 u32 net_cnt :12;
444 } net_buf_reg_718;
445
446 struct {
447 u32 reserved3 : 4;
448 u32 wan_pkt_frame : 4;
449 u32 reserved2 : 4;
450 u32 sram_memmap : 2;
451 u32 sram_chip : 2;
452 u32 wan_wait_state : 8;
453 u32 reserved1 : 6;
454 u32 wan_speed_sig : 2;
455 } wan_ctrl_reg_71c;
456} flexcop_ibi_value;
457
458#endif
diff --git a/drivers/media/dvb/b2c2/flexcop_ibi_value_le.h b/drivers/media/dvb/b2c2/flexcop_ibi_value_le.h
new file mode 100644
index 000000000000..49f2315b6e58
--- /dev/null
+++ b/drivers/media/dvb/b2c2/flexcop_ibi_value_le.h
@@ -0,0 +1,458 @@
1/* This file is part of linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
2 *
3 * register descriptions
4 *
5 * see flexcop.c for copyright information.
6 */
7
8/* This file is automatically generated, do not edit things here. */
9#ifndef __FLEXCOP_IBI_VALUE_INCLUDED__
10#define __FLEXCOP_IBI_VALUE_INCLUDED__
11
12typedef union {
13 u32 raw;
14
15 struct {
16 u32 dma_0start : 1;
17 u32 dma_0No_update : 1;
18 u32 dma_address0 :30;
19 } dma_0x0;
20
21 struct {
22 u32 DMA_maxpackets : 8;
23 u32 dma_addr_size :24;
24 } dma_0x4_remap;
25
26 struct {
27 u32 dma1timer : 7;
28 u32 unused : 1;
29 u32 dma_addr_size :24;
30 } dma_0x4_read;
31
32 struct {
33 u32 unused : 1;
34 u32 dmatimer : 7;
35 u32 dma_addr_size :24;
36 } dma_0x4_write;
37
38 struct {
39 u32 unused : 2;
40 u32 dma_cur_addr :30;
41 } dma_0x8;
42
43 struct {
44 u32 dma_1start : 1;
45 u32 remap_enable : 1;
46 u32 dma_address1 :30;
47 } dma_0xc;
48
49 struct {
50 u32 chipaddr : 7;
51 u32 reserved1 : 1;
52 u32 baseaddr : 8;
53 u32 data1_reg : 8;
54 u32 working_start : 1;
55 u32 twoWS_rw : 1;
56 u32 total_bytes : 2;
57 u32 twoWS_port_reg : 2;
58 u32 no_base_addr_ack_error : 1;
59 u32 st_done : 1;
60 } tw_sm_c_100;
61
62 struct {
63 u32 data2_reg : 8;
64 u32 data3_reg : 8;
65 u32 data4_reg : 8;
66 u32 exlicit_stops : 1;
67 u32 force_stop : 1;
68 u32 unused : 6;
69 } tw_sm_c_104;
70
71 struct {
72 u32 thi1 : 6;
73 u32 reserved1 : 2;
74 u32 tlo1 : 5;
75 u32 reserved2 :19;
76 } tw_sm_c_108;
77
78 struct {
79 u32 thi1 : 6;
80 u32 reserved1 : 2;
81 u32 tlo1 : 5;
82 u32 reserved2 :19;
83 } tw_sm_c_10c;
84
85 struct {
86 u32 thi1 : 6;
87 u32 reserved1 : 2;
88 u32 tlo1 : 5;
89 u32 reserved2 :19;
90 } tw_sm_c_110;
91
92 struct {
93 u32 LNB_CTLHighCount_sig :15;
94 u32 LNB_CTLLowCount_sig :15;
95 u32 LNB_CTLPrescaler_sig : 2;
96 } lnb_switch_freq_200;
97
98 struct {
99 u32 ACPI1_sig : 1;
100 u32 ACPI3_sig : 1;
101 u32 LNB_L_H_sig : 1;
102 u32 Per_reset_sig : 1;
103 u32 reserved :20;
104 u32 Rev_N_sig_revision_hi : 4;
105 u32 Rev_N_sig_reserved1 : 2;
106 u32 Rev_N_sig_caps : 1;
107 u32 Rev_N_sig_reserved2 : 1;
108 } misc_204;
109
110 struct {
111 u32 Stream1_filter_sig : 1;
112 u32 Stream2_filter_sig : 1;
113 u32 PCR_filter_sig : 1;
114 u32 PMT_filter_sig : 1;
115 u32 EMM_filter_sig : 1;
116 u32 ECM_filter_sig : 1;
117 u32 Null_filter_sig : 1;
118 u32 Mask_filter_sig : 1;
119 u32 WAN_Enable_sig : 1;
120 u32 WAN_CA_Enable_sig : 1;
121 u32 CA_Enable_sig : 1;
122 u32 SMC_Enable_sig : 1;
123 u32 Per_CA_Enable_sig : 1;
124 u32 Multi2_Enable_sig : 1;
125 u32 MAC_filter_Mode_sig : 1;
126 u32 Rcv_Data_sig : 1;
127 u32 DMA1_IRQ_Enable_sig : 1;
128 u32 DMA1_Timer_Enable_sig : 1;
129 u32 DMA2_IRQ_Enable_sig : 1;
130 u32 DMA2_Timer_Enable_sig : 1;
131 u32 DMA1_Size_IRQ_Enable_sig : 1;
132 u32 DMA2_Size_IRQ_Enable_sig : 1;
133 u32 Mailbox_from_V8_Enable_sig : 1;
134 u32 unused : 9;
135 } ctrl_208;
136
137 struct {
138 u32 DMA1_IRQ_Status : 1;
139 u32 DMA1_Timer_Status : 1;
140 u32 DMA2_IRQ_Status : 1;
141 u32 DMA2_Timer_Status : 1;
142 u32 DMA1_Size_IRQ_Status : 1;
143 u32 DMA2_Size_IRQ_Status : 1;
144 u32 Mailbox_from_V8_Status_sig : 1;
145 u32 Data_receiver_error : 1;
146 u32 Continuity_error_flag : 1;
147 u32 LLC_SNAP_FLAG_set : 1;
148 u32 Transport_Error : 1;
149 u32 reserved :21;
150 } irq_20c;
151
152 struct {
153 u32 reset_block_000 : 1;
154 u32 reset_block_100 : 1;
155 u32 reset_block_200 : 1;
156 u32 reset_block_300 : 1;
157 u32 reset_block_400 : 1;
158 u32 reset_block_500 : 1;
159 u32 reset_block_600 : 1;
160 u32 reset_block_700 : 1;
161 u32 Block_reset_enable : 8;
162 u32 Special_controls :16;
163 } sw_reset_210;
164
165 struct {
166 u32 vuart_oe_sig : 1;
167 u32 v2WS_oe_sig : 1;
168 u32 halt_V8_sig : 1;
169 u32 section_pkg_enable_sig : 1;
170 u32 s2p_sel_sig : 1;
171 u32 unused1 : 3;
172 u32 polarity_PS_CLK_sig : 1;
173 u32 polarity_PS_VALID_sig : 1;
174 u32 polarity_PS_SYNC_sig : 1;
175 u32 polarity_PS_ERR_sig : 1;
176 u32 unused2 :20;
177 } misc_214;
178
179 struct {
180 u32 Mailbox_from_V8 :32;
181 } mbox_v8_to_host_218;
182
183 struct {
184 u32 sysramaccess_data : 8;
185 u32 sysramaccess_addr :15;
186 u32 unused : 7;
187 u32 sysramaccess_write : 1;
188 u32 sysramaccess_busmuster : 1;
189 } mbox_host_to_v8_21c;
190
191 struct {
192 u32 Stream1_PID :13;
193 u32 Stream1_trans : 1;
194 u32 MAC_Multicast_filter : 1;
195 u32 debug_flag_pid_saved : 1;
196 u32 Stream2_PID :13;
197 u32 Stream2_trans : 1;
198 u32 debug_flag_write_status00 : 1;
199 u32 debug_fifo_problem : 1;
200 } pid_filter_300;
201
202 struct {
203 u32 PCR_PID :13;
204 u32 PCR_trans : 1;
205 u32 debug_overrun3 : 1;
206 u32 debug_overrun2 : 1;
207 u32 PMT_PID :13;
208 u32 PMT_trans : 1;
209 u32 reserved : 2;
210 } pid_filter_304;
211
212 struct {
213 u32 EMM_PID :13;
214 u32 EMM_trans : 1;
215 u32 EMM_filter_4 : 1;
216 u32 EMM_filter_6 : 1;
217 u32 ECM_PID :13;
218 u32 ECM_trans : 1;
219 u32 reserved : 2;
220 } pid_filter_308;
221
222 struct {
223 u32 Group_PID :13;
224 u32 Group_trans : 1;
225 u32 unused1 : 2;
226 u32 Group_mask :13;
227 u32 unused2 : 3;
228 } pid_filter_30c_ext_ind_0_7;
229
230 struct {
231 u32 net_master_read :17;
232 u32 unused :15;
233 } pid_filter_30c_ext_ind_1;
234
235 struct {
236 u32 net_master_write :17;
237 u32 unused :15;
238 } pid_filter_30c_ext_ind_2;
239
240 struct {
241 u32 next_net_master_write :17;
242 u32 unused :15;
243 } pid_filter_30c_ext_ind_3;
244
245 struct {
246 u32 unused1 : 1;
247 u32 state_write :10;
248 u32 reserved1 : 6;
249 u32 stack_read :10;
250 u32 reserved2 : 5;
251 } pid_filter_30c_ext_ind_4;
252
253 struct {
254 u32 stack_cnt :10;
255 u32 unused :22;
256 } pid_filter_30c_ext_ind_5;
257
258 struct {
259 u32 pid_fsm_save_reg0 : 2;
260 u32 pid_fsm_save_reg1 : 2;
261 u32 pid_fsm_save_reg2 : 2;
262 u32 pid_fsm_save_reg3 : 2;
263 u32 pid_fsm_save_reg4 : 2;
264 u32 pid_fsm_save_reg300 : 2;
265 u32 write_status1 : 2;
266 u32 write_status4 : 2;
267 u32 data_size_reg :12;
268 u32 unused : 4;
269 } pid_filter_30c_ext_ind_6;
270
271 struct {
272 u32 index_reg : 5;
273 u32 extra_index_reg : 3;
274 u32 AB_select : 1;
275 u32 pass_alltables : 1;
276 u32 unused :22;
277 } index_reg_310;
278
279 struct {
280 u32 PID :13;
281 u32 PID_trans : 1;
282 u32 PID_enable_bit : 1;
283 u32 reserved :17;
284 } pid_n_reg_314;
285
286 struct {
287 u32 A4_byte : 8;
288 u32 A5_byte : 8;
289 u32 A6_byte : 8;
290 u32 Enable_bit : 1;
291 u32 HighAB_bit : 1;
292 u32 reserved : 6;
293 } mac_low_reg_318;
294
295 struct {
296 u32 A1_byte : 8;
297 u32 A2_byte : 8;
298 u32 A3_byte : 8;
299 u32 reserved : 8;
300 } mac_high_reg_31c;
301
302 struct {
303 u32 reserved :16;
304 u32 data_Tag_ID :16;
305 } data_tag_400;
306
307 struct {
308 u32 Card_IDbyte6 : 8;
309 u32 Card_IDbyte5 : 8;
310 u32 Card_IDbyte4 : 8;
311 u32 Card_IDbyte3 : 8;
312 } card_id_408;
313
314 struct {
315 u32 Card_IDbyte2 : 8;
316 u32 Card_IDbyte1 : 8;
317 } card_id_40c;
318
319 struct {
320 u32 MAC1 : 8;
321 u32 MAC2 : 8;
322 u32 MAC3 : 8;
323 u32 MAC6 : 8;
324 } mac_address_418;
325
326 struct {
327 u32 MAC7 : 8;
328 u32 MAC8 : 8;
329 u32 reserved :16;
330 } mac_address_41c;
331
332 struct {
333 u32 transmitter_data_byte : 8;
334 u32 ReceiveDataReady : 1;
335 u32 ReceiveByteFrameError : 1;
336 u32 txbuffempty : 1;
337 u32 reserved :21;
338 } ci_600;
339
340 struct {
341 u32 pi_d : 8;
342 u32 pi_ha :20;
343 u32 pi_rw : 1;
344 u32 pi_component_reg : 3;
345 } pi_604;
346
347 struct {
348 u32 serialReset : 1;
349 u32 oncecycle_read : 1;
350 u32 Timer_Read_req : 1;
351 u32 Timer_Load_req : 1;
352 u32 timer_data : 7;
353 u32 unused : 1;
354 u32 Timer_addr : 5;
355 u32 reserved : 3;
356 u32 pcmcia_a_mod_pwr_n : 1;
357 u32 pcmcia_b_mod_pwr_n : 1;
358 u32 config_Done_stat : 1;
359 u32 config_Init_stat : 1;
360 u32 config_Prog_n : 1;
361 u32 config_wr_n : 1;
362 u32 config_cs_n : 1;
363 u32 config_cclk : 1;
364 u32 pi_CiMax_IRQ_n : 1;
365 u32 pi_timeout_status : 1;
366 u32 pi_wait_n : 1;
367 u32 pi_busy_n : 1;
368 } pi_608;
369
370 struct {
371 u32 PID :13;
372 u32 key_enable : 1;
373 u32 key_code : 2;
374 u32 key_array_col : 3;
375 u32 key_array_row : 5;
376 u32 dvb_en : 1;
377 u32 rw_flag : 1;
378 u32 reserved : 6;
379 } dvb_reg_60c;
380
381 struct {
382 u32 sram_addr :15;
383 u32 sram_rw : 1;
384 u32 sram_data : 8;
385 u32 sc_xfer_bit : 1;
386 u32 reserved1 : 3;
387 u32 oe_pin_reg : 1;
388 u32 ce_pin_reg : 1;
389 u32 reserved2 : 1;
390 u32 start_sram_ibi : 1;
391 } sram_ctrl_reg_700;
392
393 struct {
394 u32 net_addr_read :16;
395 u32 net_addr_write :16;
396 } net_buf_reg_704;
397
398 struct {
399 u32 cai_read :11;
400 u32 reserved1 : 5;
401 u32 cai_write :11;
402 u32 reserved2 : 6;
403 u32 cai_cnt : 4;
404 } cai_buf_reg_708;
405
406 struct {
407 u32 cao_read :11;
408 u32 reserved1 : 5;
409 u32 cap_write :11;
410 u32 reserved2 : 6;
411 u32 cao_cnt : 4;
412 } cao_buf_reg_70c;
413
414 struct {
415 u32 media_read :11;
416 u32 reserved1 : 5;
417 u32 media_write :11;
418 u32 reserved2 : 6;
419 u32 media_cnt : 4;
420 } media_buf_reg_710;
421
422 struct {
423 u32 NET_Dest : 2;
424 u32 CAI_Dest : 2;
425 u32 CAO_Dest : 2;
426 u32 MEDIA_Dest : 2;
427 u32 net_ovflow_error : 1;
428 u32 media_ovflow_error : 1;
429 u32 cai_ovflow_error : 1;
430 u32 cao_ovflow_error : 1;
431 u32 ctrl_usb_wan : 1;
432 u32 ctrl_sramdma : 1;
433 u32 ctrl_maximumfill : 1;
434 u32 reserved :17;
435 } sram_dest_reg_714;
436
437 struct {
438 u32 net_cnt :12;
439 u32 reserved1 : 4;
440 u32 net_addr_read : 1;
441 u32 reserved2 : 3;
442 u32 net_addr_write : 1;
443 u32 reserved3 :11;
444 } net_buf_reg_718;
445
446 struct {
447 u32 wan_speed_sig : 2;
448 u32 reserved1 : 6;
449 u32 wan_wait_state : 8;
450 u32 sram_chip : 2;
451 u32 sram_memmap : 2;
452 u32 reserved2 : 4;
453 u32 wan_pkt_frame : 4;
454 u32 reserved3 : 4;
455 } wan_ctrl_reg_71c;
456} flexcop_ibi_value;
457
458#endif
diff --git a/drivers/media/dvb/b2c2/skystar2.c b/drivers/media/dvb/b2c2/skystar2.c
deleted file mode 100644
index acbc4c34f72a..000000000000
--- a/drivers/media/dvb/b2c2/skystar2.c
+++ /dev/null
@@ -1,2644 +0,0 @@
1/*
2 * skystar2.c - driver for the Technisat SkyStar2 PCI DVB card
3 * based on the FlexCopII by B2C2,Inc.
4 *
5 * Copyright (C) 2003 Vadim Catana, skystar@moldova.cc
6 *
7 * FIX: DISEQC Tone Burst in flexcop_diseqc_ioctl()
8 * FIX: FULL soft DiSEqC for skystar2 (FlexCopII rev 130) VP310 equipped
9 * Vincenzo Di Massa, hawk.it at tiscalinet.it
10 *
11 * Converted to Linux coding style
12 * Misc reorganization, polishing, restyling
13 * Roberto Ragusa, skystar2-c5b8 at robertoragusa dot it
14 *
15 * Added hardware filtering support,
16 * Niklas Peinecke, peinecke at gdv.uni-hannover.de
17 *
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU Lesser General Public License
21 * as published by the Free Software Foundation; either version 2.1
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU Lesser General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/delay.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/version.h>
40
41#include <asm/io.h>
42
43#include "dvb_frontend.h"
44
45#include <linux/dvb/frontend.h>
46#include <linux/dvb/dmx.h>
47#include "dvb_demux.h"
48#include "dmxdev.h"
49#include "dvb_filter.h"
50#include "dvbdev.h"
51#include "demux.h"
52#include "dvb_net.h"
53#include "stv0299.h"
54#include "mt352.h"
55#include "mt312.h"
56#include "nxt2002.h"
57
58static int debug;
59static int enable_hw_filters = 2;
60
61module_param(debug, int, 0644);
62MODULE_PARM_DESC(debug, "Set debugging level (0 = default, 1 = most messages, 2 = all messages).");
63module_param(enable_hw_filters, int, 0444);
64MODULE_PARM_DESC(enable_hw_filters, "enable hardware filters: supported values: 0 (none), 1, 2");
65
66#define dprintk(x...) do { if (debug>=1) printk(x); } while (0)
67#define ddprintk(x...) do { if (debug>=2) printk(x); } while (0)
68
69#define SIZE_OF_BUF_DMA1 0x3ac00
70#define SIZE_OF_BUF_DMA2 0x758
71
72#define MAX_N_HW_FILTERS (6+32)
73#define N_PID_SLOTS 256
74
75struct dmaq {
76 u32 bus_addr;
77 u32 head;
78 u32 tail;
79 u32 buffer_size;
80 u8 *buffer;
81};
82
83#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9)
84#define __iomem
85#endif
86
87struct adapter {
88 struct pci_dev *pdev;
89
90 u8 card_revision;
91 u32 b2c2_revision;
92 u32 pid_filter_max;
93 u32 mac_filter_max;
94 u32 irq;
95 void __iomem *io_mem;
96 unsigned long io_port;
97 u8 mac_addr[8];
98 u32 dw_sram_type;
99
100 struct dvb_adapter dvb_adapter;
101 struct dvb_demux demux;
102 struct dmxdev dmxdev;
103 struct dmx_frontend hw_frontend;
104 struct dmx_frontend mem_frontend;
105 struct i2c_adapter i2c_adap;
106 struct dvb_net dvbnet;
107
108 struct semaphore i2c_sem;
109
110 struct dmaq dmaq1;
111 struct dmaq dmaq2;
112
113 u32 dma_ctrl;
114 u32 dma_status;
115
116 int capturing;
117
118 spinlock_t lock;
119
120 int useable_hw_filters;
121 u16 hw_pids[MAX_N_HW_FILTERS];
122 u16 pid_list[N_PID_SLOTS];
123 int pid_rc[N_PID_SLOTS]; // ref counters for the pids
124 int pid_count;
125 int whole_bandwidth_count;
126 u32 mac_filter;
127
128 struct dvb_frontend* fe;
129 int (*fe_sleep)(struct dvb_frontend* fe);
130};
131
132#define write_reg_dw(adapter,reg,value) writel(value, adapter->io_mem + reg)
133#define read_reg_dw(adapter,reg) readl(adapter->io_mem + reg)
134
135static void write_reg_bitfield(struct adapter *adapter, u32 reg, u32 zeromask, u32 orvalue)
136{
137 u32 tmp;
138
139 tmp = read_reg_dw(adapter, reg);
140 tmp = (tmp & ~zeromask) | orvalue;
141 write_reg_dw(adapter, reg, tmp);
142}
143
144/* i2c functions */
145static int i2c_main_write_for_flex2(struct adapter *adapter, u32 command, u8 *buf, int retries)
146{
147 int i;
148 u32 value;
149
150 write_reg_dw(adapter, 0x100, 0);
151 write_reg_dw(adapter, 0x100, command);
152
153 for (i = 0; i < retries; i++) {
154 value = read_reg_dw(adapter, 0x100);
155
156 if ((value & 0x40000000) == 0) {
157 if ((value & 0x81000000) == 0x80000000) {
158 if (buf != 0)
159 *buf = (value >> 0x10) & 0xff;
160
161 return 1;
162 }
163 } else {
164 write_reg_dw(adapter, 0x100, 0);
165 write_reg_dw(adapter, 0x100, command);
166 }
167 }
168
169 return 0;
170}
171
172/* device = 0x10000000 for tuner, 0x20000000 for eeprom */
173static void i2c_main_setup(u32 device, u32 chip_addr, u8 op, u8 addr, u32 value, u32 len, u32 *command)
174{
175 *command = device | ((len - 1) << 26) | (value << 16) | (addr << 8) | chip_addr;
176
177 if (op != 0)
178 *command = *command | 0x03000000;
179 else
180 *command = *command | 0x01000000;
181}
182
183static int flex_i2c_read4(struct adapter *adapter, u32 device, u32 chip_addr, u16 addr, u8 *buf, u8 len)
184{
185 u32 command;
186 u32 value;
187
188 int result, i;
189
190 i2c_main_setup(device, chip_addr, 1, addr, 0, len, &command);
191
192 result = i2c_main_write_for_flex2(adapter, command, buf, 100000);
193
194 if ((result & 0xff) != 0) {
195 if (len > 1) {
196 value = read_reg_dw(adapter, 0x104);
197
198 for (i = 1; i < len; i++) {
199 buf[i] = value & 0xff;
200 value = value >> 8;
201 }
202 }
203 }
204
205 return result;
206}
207
208static int flex_i2c_write4(struct adapter *adapter, u32 device, u32 chip_addr, u32 addr, u8 *buf, u8 len)
209{
210 u32 command;
211 u32 value;
212 int i;
213
214 if (len > 1) {
215 value = 0;
216
217 for (i = len; i > 1; i--) {
218 value = value << 8;
219 value = value | buf[i - 1];
220 }
221
222 write_reg_dw(adapter, 0x104, value);
223 }
224
225 i2c_main_setup(device, chip_addr, 0, addr, buf[0], len, &command);
226
227 return i2c_main_write_for_flex2(adapter, command, NULL, 100000);
228}
229
230static void fixchipaddr(u32 device, u32 bus, u32 addr, u32 *ret)
231{
232 if (device == 0x20000000)
233 *ret = bus | ((addr >> 8) & 3);
234 else
235 *ret = bus;
236}
237
238static u32 flex_i2c_read(struct adapter *adapter, u32 device, u32 bus, u32 addr, u8 *buf, u32 len)
239{
240 u32 chipaddr;
241 u32 bytes_to_transfer;
242 u8 *start;
243
244 ddprintk("%s:\n", __FUNCTION__);
245
246 start = buf;
247
248 while (len != 0) {
249 bytes_to_transfer = len;
250
251 if (bytes_to_transfer > 4)
252 bytes_to_transfer = 4;
253
254 fixchipaddr(device, bus, addr, &chipaddr);
255
256 if (flex_i2c_read4(adapter, device, chipaddr, addr, buf, bytes_to_transfer) == 0)
257 return buf - start;
258
259 buf = buf + bytes_to_transfer;
260 addr = addr + bytes_to_transfer;
261 len = len - bytes_to_transfer;
262 };
263
264 return buf - start;
265}
266
267static u32 flex_i2c_write(struct adapter *adapter, u32 device, u32 bus, u32 addr, u8 *buf, u32 len)
268{
269 u32 chipaddr;
270 u32 bytes_to_transfer;
271 u8 *start;
272
273 ddprintk("%s:\n", __FUNCTION__);
274
275 start = buf;
276
277 while (len != 0) {
278 bytes_to_transfer = len;
279
280 if (bytes_to_transfer > 4)
281 bytes_to_transfer = 4;
282
283 fixchipaddr(device, bus, addr, &chipaddr);
284
285 if (flex_i2c_write4(adapter, device, chipaddr, addr, buf, bytes_to_transfer) == 0)
286 return buf - start;
287
288 buf = buf + bytes_to_transfer;
289 addr = addr + bytes_to_transfer;
290 len = len - bytes_to_transfer;
291 }
292
293 return buf - start;
294}
295
296static int master_xfer(struct i2c_adapter* adapter, struct i2c_msg *msgs, int num)
297{
298 struct adapter *tmp = i2c_get_adapdata(adapter);
299 int i, ret = 0;
300
301 if (down_interruptible(&tmp->i2c_sem))
302 return -ERESTARTSYS;
303
304 ddprintk("%s: %d messages to transfer\n", __FUNCTION__, num);
305
306 for (i = 0; i < num; i++) {
307 ddprintk("message %d: flags=0x%x, addr=0x%x, buf=0x%x, len=%d \n", i,
308 msgs[i].flags, msgs[i].addr, msgs[i].buf[0], msgs[i].len);
309 }
310
311 // read command
312 if ((num == 2) && (msgs[0].flags == 0) && (msgs[1].flags == I2C_M_RD) && (msgs[0].buf != NULL) && (msgs[1].buf != NULL)) {
313
314 ret = flex_i2c_read(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], msgs[1].buf, msgs[1].len);
315
316 up(&tmp->i2c_sem);
317
318 if (ret != msgs[1].len) {
319 dprintk("%s: read error !\n", __FUNCTION__);
320
321 for (i = 0; i < 2; i++) {
322 dprintk("message %d: flags=0x%x, addr=0x%x, buf=0x%x, len=%d \n", i,
323 msgs[i].flags, msgs[i].addr, msgs[i].buf[0], msgs[i].len);
324 }
325
326 return -EREMOTEIO;
327 }
328
329 return num;
330 }
331 // write command
332 for (i = 0; i < num; i++) {
333
334 if ((msgs[i].flags != 0) || (msgs[i].buf == NULL) || (msgs[i].len < 2))
335 return -EINVAL;
336
337 ret = flex_i2c_write(tmp, 0x10000000, msgs[i].addr, msgs[i].buf[0], &msgs[i].buf[1], msgs[i].len - 1);
338
339 up(&tmp->i2c_sem);
340
341 if (ret != msgs[0].len - 1) {
342 dprintk("%s: write error %i !\n", __FUNCTION__, ret);
343
344 dprintk("message %d: flags=0x%x, addr=0x%x, buf[0]=0x%x, len=%d \n", i,
345 msgs[i].flags, msgs[i].addr, msgs[i].buf[0], msgs[i].len);
346
347 return -EREMOTEIO;
348 }
349
350 return num;
351 }
352
353 printk("%s: unknown command format !\n", __FUNCTION__);
354
355 return -EINVAL;
356}
357
358/* SRAM (Skystar2 rev2.3 has one "ISSI IS61LV256" chip on board,
359 but it seems that FlexCopII can work with more than one chip) */
360static void sram_set_net_dest(struct adapter *adapter, u8 dest)
361{
362 u32 tmp;
363
364 udelay(1000);
365
366 tmp = (read_reg_dw(adapter, 0x714) & 0xfffffffc) | (dest & 3);
367
368 udelay(1000);
369
370 write_reg_dw(adapter, 0x714, tmp);
371 write_reg_dw(adapter, 0x714, tmp);
372
373 udelay(1000);
374
375 /* return value is never used? */
376/* return tmp; */
377}
378
379static void sram_set_cai_dest(struct adapter *adapter, u8 dest)
380{
381 u32 tmp;
382
383 udelay(1000);
384
385 tmp = (read_reg_dw(adapter, 0x714) & 0xfffffff3) | ((dest & 3) << 2);
386
387 udelay(1000);
388 udelay(1000);
389
390 write_reg_dw(adapter, 0x714, tmp);
391 write_reg_dw(adapter, 0x714, tmp);
392
393 udelay(1000);
394
395 /* return value is never used? */
396/* return tmp; */
397}
398
399static void sram_set_cao_dest(struct adapter *adapter, u8 dest)
400{
401 u32 tmp;
402
403 udelay(1000);
404
405 tmp = (read_reg_dw(adapter, 0x714) & 0xffffffcf) | ((dest & 3) << 4);
406
407 udelay(1000);
408 udelay(1000);
409
410 write_reg_dw(adapter, 0x714, tmp);
411 write_reg_dw(adapter, 0x714, tmp);
412
413 udelay(1000);
414
415 /* return value is never used? */
416/* return tmp; */
417}
418
419static void sram_set_media_dest(struct adapter *adapter, u8 dest)
420{
421 u32 tmp;
422
423 udelay(1000);
424
425 tmp = (read_reg_dw(adapter, 0x714) & 0xffffff3f) | ((dest & 3) << 6);
426
427 udelay(1000);
428 udelay(1000);
429
430 write_reg_dw(adapter, 0x714, tmp);
431 write_reg_dw(adapter, 0x714, tmp);
432
433 udelay(1000);
434
435 /* return value is never used? */
436/* return tmp; */
437}
438
439/* SRAM memory is accessed through a buffer register in the FlexCop
440 chip (0x700). This register has the following structure:
441 bits 0-14 : address
442 bit 15 : read/write flag
443 bits 16-23 : 8-bit word to write
444 bits 24-27 : = 4
445 bits 28-29 : memory bank selector
446 bit 31 : busy flag
447*/
448static void flex_sram_write(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)
449{
450 int i, retries;
451 u32 command;
452
453 for (i = 0; i < len; i++) {
454 command = bank | addr | 0x04000000 | (*buf << 0x10);
455
456 retries = 2;
457
458 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
459 mdelay(1);
460 retries--;
461 };
462
463 if (retries == 0)
464 printk("%s: SRAM timeout\n", __FUNCTION__);
465
466 write_reg_dw(adapter, 0x700, command);
467
468 buf++;
469 addr++;
470 }
471}
472
473static void flex_sram_read(struct adapter *adapter, u32 bank, u32 addr, u8 *buf, u32 len)
474{
475 int i, retries;
476 u32 command, value;
477
478 for (i = 0; i < len; i++) {
479 command = bank | addr | 0x04008000;
480
481 retries = 10000;
482
483 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
484 mdelay(1);
485 retries--;
486 };
487
488 if (retries == 0)
489 printk("%s: SRAM timeout\n", __FUNCTION__);
490
491 write_reg_dw(adapter, 0x700, command);
492
493 retries = 10000;
494
495 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
496 mdelay(1);
497 retries--;
498 };
499
500 if (retries == 0)
501 printk("%s: SRAM timeout\n", __FUNCTION__);
502
503 value = read_reg_dw(adapter, 0x700) >> 0x10;
504
505 *buf = (value & 0xff);
506
507 addr++;
508 buf++;
509 }
510}
511
512static void sram_write_chunk(struct adapter *adapter, u32 addr, u8 *buf, u16 len)
513{
514 u32 bank;
515
516 bank = 0;
517
518 if (adapter->dw_sram_type == 0x20000) {
519 bank = (addr & 0x18000) << 0x0d;
520 }
521
522 if (adapter->dw_sram_type == 0x00000) {
523 if ((addr >> 0x0f) == 0)
524 bank = 0x20000000;
525 else
526 bank = 0x10000000;
527 }
528
529 flex_sram_write(adapter, bank, addr & 0x7fff, buf, len);
530}
531
532static void sram_read_chunk(struct adapter *adapter, u32 addr, u8 *buf, u16 len)
533{
534 u32 bank;
535
536 bank = 0;
537
538 if (adapter->dw_sram_type == 0x20000) {
539 bank = (addr & 0x18000) << 0x0d;
540 }
541
542 if (adapter->dw_sram_type == 0x00000) {
543 if ((addr >> 0x0f) == 0)
544 bank = 0x20000000;
545 else
546 bank = 0x10000000;
547 }
548
549 flex_sram_read(adapter, bank, addr & 0x7fff, buf, len);
550}
551
552static void sram_read(struct adapter *adapter, u32 addr, u8 *buf, u32 len)
553{
554 u32 length;
555
556 while (len != 0) {
557 length = len;
558
559 // check if the address range belongs to the same
560 // 32K memory chip. If not, the data is read from
561 // one chip at a time.
562 if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {
563 length = (((addr >> 0x0f) + 1) << 0x0f) - addr;
564 }
565
566 sram_read_chunk(adapter, addr, buf, length);
567
568 addr = addr + length;
569 buf = buf + length;
570 len = len - length;
571 }
572}
573
574static void sram_write(struct adapter *adapter, u32 addr, u8 *buf, u32 len)
575{
576 u32 length;
577
578 while (len != 0) {
579 length = len;
580
581 // check if the address range belongs to the same
582 // 32K memory chip. If not, the data is written to
583 // one chip at a time.
584 if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {
585 length = (((addr >> 0x0f) + 1) << 0x0f) - addr;
586 }
587
588 sram_write_chunk(adapter, addr, buf, length);
589
590 addr = addr + length;
591 buf = buf + length;
592 len = len - length;
593 }
594}
595
596static void sram_set_size(struct adapter *adapter, u32 mask)
597{
598 write_reg_dw(adapter, 0x71c, (mask | (~0x30000 & read_reg_dw(adapter, 0x71c))));
599}
600
601static void sram_init(struct adapter *adapter)
602{
603 u32 tmp;
604
605 tmp = read_reg_dw(adapter, 0x71c);
606
607 write_reg_dw(adapter, 0x71c, 1);
608
609 if (read_reg_dw(adapter, 0x71c) != 0) {
610 write_reg_dw(adapter, 0x71c, tmp);
611
612 adapter->dw_sram_type = tmp & 0x30000;
613
614 ddprintk("%s: dw_sram_type = %x\n", __FUNCTION__, adapter->dw_sram_type);
615
616 } else {
617
618 adapter->dw_sram_type = 0x10000;
619
620 ddprintk("%s: dw_sram_type = %x\n", __FUNCTION__, adapter->dw_sram_type);
621 }
622
623 /* return value is never used? */
624/* return adapter->dw_sram_type; */
625}
626
627static int sram_test_location(struct adapter *adapter, u32 mask, u32 addr)
628{
629 u8 tmp1, tmp2;
630
631 dprintk("%s: mask = %x, addr = %x\n", __FUNCTION__, mask, addr);
632
633 sram_set_size(adapter, mask);
634 sram_init(adapter);
635
636 tmp2 = 0xa5;
637 tmp1 = 0x4f;
638
639 sram_write(adapter, addr, &tmp2, 1);
640 sram_write(adapter, addr + 4, &tmp1, 1);
641
642 tmp2 = 0;
643
644 mdelay(20);
645
646 sram_read(adapter, addr, &tmp2, 1);
647 sram_read(adapter, addr, &tmp2, 1);
648
649 dprintk("%s: wrote 0xa5, read 0x%2x\n", __FUNCTION__, tmp2);
650
651 if (tmp2 != 0xa5)
652 return 0;
653
654 tmp2 = 0x5a;
655 tmp1 = 0xf4;
656
657 sram_write(adapter, addr, &tmp2, 1);
658 sram_write(adapter, addr + 4, &tmp1, 1);
659
660 tmp2 = 0;
661
662 mdelay(20);
663
664 sram_read(adapter, addr, &tmp2, 1);
665 sram_read(adapter, addr, &tmp2, 1);
666
667 dprintk("%s: wrote 0x5a, read 0x%2x\n", __FUNCTION__, tmp2);
668
669 if (tmp2 != 0x5a)
670 return 0;
671
672 return 1;
673}
674
675static u32 sram_length(struct adapter *adapter)
676{
677 if (adapter->dw_sram_type == 0x10000)
678 return 32768; // 32K
679 if (adapter->dw_sram_type == 0x00000)
680 return 65536; // 64K
681 if (adapter->dw_sram_type == 0x20000)
682 return 131072; // 128K
683
684 return 32768; // 32K
685}
686
687/* FlexcopII can work with 32K, 64K or 128K of external SRAM memory.
688 - for 128K there are 4x32K chips at bank 0,1,2,3.
689 - for 64K there are 2x32K chips at bank 1,2.
690 - for 32K there is one 32K chip at bank 0.
691
692 FlexCop works only with one bank at a time. The bank is selected
693 by bits 28-29 of the 0x700 register.
694
695 bank 0 covers addresses 0x00000-0x07fff
696 bank 1 covers addresses 0x08000-0x0ffff
697 bank 2 covers addresses 0x10000-0x17fff
698 bank 3 covers addresses 0x18000-0x1ffff
699*/
700static int sram_detect_for_flex2(struct adapter *adapter)
701{
702 u32 tmp, tmp2, tmp3;
703
704 dprintk("%s:\n", __FUNCTION__);
705
706 tmp = read_reg_dw(adapter, 0x208);
707 write_reg_dw(adapter, 0x208, 0);
708
709 tmp2 = read_reg_dw(adapter, 0x71c);
710
711 dprintk("%s: tmp2 = %x\n", __FUNCTION__, tmp2);
712
713 write_reg_dw(adapter, 0x71c, 1);
714
715 tmp3 = read_reg_dw(adapter, 0x71c);
716
717 dprintk("%s: tmp3 = %x\n", __FUNCTION__, tmp3);
718
719 write_reg_dw(adapter, 0x71c, tmp2);
720
721 // check for internal SRAM ???
722 tmp3--;
723 if (tmp3 != 0) {
724 sram_set_size(adapter, 0x10000);
725 sram_init(adapter);
726 write_reg_dw(adapter, 0x208, tmp);
727
728 dprintk("%s: sram size = 32K\n", __FUNCTION__);
729
730 return 32;
731 }
732
733 if (sram_test_location(adapter, 0x20000, 0x18000) != 0) {
734 sram_set_size(adapter, 0x20000);
735 sram_init(adapter);
736 write_reg_dw(adapter, 0x208, tmp);
737
738 dprintk("%s: sram size = 128K\n", __FUNCTION__);
739
740 return 128;
741 }
742
743 if (sram_test_location(adapter, 0x00000, 0x10000) != 0) {
744 sram_set_size(adapter, 0x00000);
745 sram_init(adapter);
746 write_reg_dw(adapter, 0x208, tmp);
747
748 dprintk("%s: sram size = 64K\n", __FUNCTION__);
749
750 return 64;
751 }
752
753 if (sram_test_location(adapter, 0x10000, 0x00000) != 0) {
754 sram_set_size(adapter, 0x10000);
755 sram_init(adapter);
756 write_reg_dw(adapter, 0x208, tmp);
757
758 dprintk("%s: sram size = 32K\n", __FUNCTION__);
759
760 return 32;
761 }
762
763 sram_set_size(adapter, 0x10000);
764 sram_init(adapter);
765 write_reg_dw(adapter, 0x208, tmp);
766
767 dprintk("%s: SRAM detection failed. Set to 32K \n", __FUNCTION__);
768
769 return 0;
770}
771
772static void sll_detect_sram_size(struct adapter *adapter)
773{
774 sram_detect_for_flex2(adapter);
775}
776
777/* EEPROM (Skystar2 has one "24LC08B" chip on board) */
778/*
779static int eeprom_write(struct adapter *adapter, u16 addr, u8 *buf, u16 len)
780{
781 return flex_i2c_write(adapter, 0x20000000, 0x50, addr, buf, len);
782}
783*/
784
785static int eeprom_read(struct adapter *adapter, u16 addr, u8 *buf, u16 len)
786{
787 return flex_i2c_read(adapter, 0x20000000, 0x50, addr, buf, len);
788}
789
790static u8 calc_lrc(u8 *buf, int len)
791{
792 int i;
793 u8 sum;
794
795 sum = 0;
796
797 for (i = 0; i < len; i++)
798 sum = sum ^ buf[i];
799
800 return sum;
801}
802
803static int eeprom_lrc_read(struct adapter *adapter, u32 addr, u32 len, u8 *buf, int retries)
804{
805 int i;
806
807 for (i = 0; i < retries; i++) {
808 if (eeprom_read(adapter, addr, buf, len) == len) {
809 if (calc_lrc(buf, len - 1) == buf[len - 1])
810 return 1;
811 }
812 }
813
814 return 0;
815}
816
817/*
818static int eeprom_lrc_write(struct adapter *adapter, u32 addr, u32 len, u8 *wbuf, u8 *rbuf, int retries)
819{
820 int i;
821
822 for (i = 0; i < retries; i++) {
823 if (eeprom_write(adapter, addr, wbuf, len) == len) {
824 if (eeprom_lrc_read(adapter, addr, len, rbuf, retries) == 1)
825 return 1;
826 }
827 }
828
829 return 0;
830}
831*/
832
833
834/* These functions could be used to unlock SkyStar2 cards. */
835
836/*
837static int eeprom_writeKey(struct adapter *adapter, u8 *key, u32 len)
838{
839 u8 rbuf[20];
840 u8 wbuf[20];
841
842 if (len != 16)
843 return 0;
844
845 memcpy(wbuf, key, len);
846
847 wbuf[16] = 0;
848 wbuf[17] = 0;
849 wbuf[18] = 0;
850 wbuf[19] = calc_lrc(wbuf, 19);
851
852 return eeprom_lrc_write(adapter, 0x3e4, 20, wbuf, rbuf, 4);
853}
854
855static int eeprom_readKey(struct adapter *adapter, u8 *key, u32 len)
856{
857 u8 buf[20];
858
859 if (len != 16)
860 return 0;
861
862 if (eeprom_lrc_read(adapter, 0x3e4, 20, buf, 4) == 0)
863 return 0;
864
865 memcpy(key, buf, len);
866
867 return 1;
868}
869*/
870
871static int eeprom_get_mac_addr(struct adapter *adapter, char type, u8 *mac)
872{
873 u8 tmp[8];
874
875 if (eeprom_lrc_read(adapter, 0x3f8, 8, tmp, 4) != 0) {
876 if (type != 0) {
877 mac[0] = tmp[0];
878 mac[1] = tmp[1];
879 mac[2] = tmp[2];
880 mac[3] = 0xfe;
881 mac[4] = 0xff;
882 mac[5] = tmp[3];
883 mac[6] = tmp[4];
884 mac[7] = tmp[5];
885
886 } else {
887
888 mac[0] = tmp[0];
889 mac[1] = tmp[1];
890 mac[2] = tmp[2];
891 mac[3] = tmp[3];
892 mac[4] = tmp[4];
893 mac[5] = tmp[5];
894 }
895
896 return 1;
897
898 } else {
899
900 if (type == 0) {
901 memset(mac, 0, 6);
902
903 } else {
904
905 memset(mac, 0, 8);
906 }
907
908 return 0;
909 }
910}
911
912/*
913static char eeprom_set_mac_addr(struct adapter *adapter, char type, u8 *mac)
914{
915 u8 tmp[8];
916
917 if (type != 0) {
918 tmp[0] = mac[0];
919 tmp[1] = mac[1];
920 tmp[2] = mac[2];
921 tmp[3] = mac[5];
922 tmp[4] = mac[6];
923 tmp[5] = mac[7];
924
925 } else {
926
927 tmp[0] = mac[0];
928 tmp[1] = mac[1];
929 tmp[2] = mac[2];
930 tmp[3] = mac[3];
931 tmp[4] = mac[4];
932 tmp[5] = mac[5];
933 }
934
935 tmp[6] = 0;
936 tmp[7] = calc_lrc(tmp, 7);
937
938 if (eeprom_write(adapter, 0x3f8, tmp, 8) == 8)
939 return 1;
940
941 return 0;
942}
943*/
944
945/* PID filter */
946
947/* every flexcop has 6 "lower" hw PID filters */
948/* these are enabled by setting bits 0-5 of 0x208 */
949/* for the 32 additional filters we have to select one */
950/* of them through 0x310 and modify through 0x314 */
951/* op: 0=disable, 1=enable */
952static void filter_enable_hw_filter(struct adapter *adapter, int id, u8 op)
953{
954 dprintk("%s: id=%d op=%d\n", __FUNCTION__, id, op);
955 if (id <= 5) {
956 u32 mask = (0x00000001 << id);
957 write_reg_bitfield(adapter, 0x208, mask, op ? mask : 0);
958 } else {
959 /* select */
960 write_reg_bitfield(adapter, 0x310, 0x1f, (id - 6) & 0x1f);
961 /* modify */
962 write_reg_bitfield(adapter, 0x314, 0x00006000, op ? 0x00004000 : 0);
963 }
964}
965
966/* this sets the PID that should pass the specified filter */
967static void pid_set_hw_pid(struct adapter *adapter, int id, u16 pid)
968{
969 dprintk("%s: id=%d pid=%d\n", __FUNCTION__, id, pid);
970 if (id <= 5) {
971 u32 adr = 0x300 + ((id & 6) << 1);
972 int shift = (id & 1) ? 16 : 0;
973 dprintk("%s: id=%d addr=%x %c pid=%d\n", __FUNCTION__, id, adr, (id & 1) ? 'h' : 'l', pid);
974 write_reg_bitfield(adapter, adr, (0x7fff) << shift, (pid & 0x1fff) << shift);
975 } else {
976 /* select */
977 write_reg_bitfield(adapter, 0x310, 0x1f, (id - 6) & 0x1f);
978 /* modify */
979 write_reg_bitfield(adapter, 0x314, 0x1fff, pid & 0x1fff);
980 }
981}
982
983
984/*
985static void filter_enable_null_filter(struct adapter *adapter, u32 op)
986{
987 dprintk("%s: op=%x\n", __FUNCTION__, op);
988
989 write_reg_bitfield(adapter, 0x208, 0x00000040, op?0x00000040:0);
990}
991*/
992
993static void filter_enable_mask_filter(struct adapter *adapter, u32 op)
994{
995 dprintk("%s: op=%x\n", __FUNCTION__, op);
996
997 write_reg_bitfield(adapter, 0x208, 0x00000080, op ? 0x00000080 : 0);
998}
999
1000
1001static void ctrl_enable_mac(struct adapter *adapter, u32 op)
1002{
1003 write_reg_bitfield(adapter, 0x208, 0x00004000, op ? 0x00004000 : 0);
1004}
1005
1006static int ca_set_mac_dst_addr_filter(struct adapter *adapter, u8 *mac)
1007{
1008 u32 tmp1, tmp2;
1009
1010 tmp1 = (mac[3] << 0x18) | (mac[2] << 0x10) | (mac[1] << 0x08) | mac[0];
1011 tmp2 = (mac[5] << 0x08) | mac[4];
1012
1013 write_reg_dw(adapter, 0x418, tmp1);
1014 write_reg_dw(adapter, 0x41c, tmp2);
1015
1016 return 0;
1017}
1018
1019/*
1020static void set_ignore_mac_filter(struct adapter *adapter, u8 op)
1021{
1022 if (op != 0) {
1023 write_reg_bitfield(adapter, 0x208, 0x00004000, 0);
1024 adapter->mac_filter = 1;
1025 } else {
1026 if (adapter->mac_filter != 0) {
1027 adapter->mac_filter = 0;
1028 write_reg_bitfield(adapter, 0x208, 0x00004000, 0x00004000);
1029 }
1030 }
1031}
1032*/
1033
1034/*
1035static void check_null_filter_enable(struct adapter *adapter)
1036{
1037 filter_enable_null_filter(adapter, 1);
1038 filter_enable_mask_filter(adapter, 1);
1039}
1040*/
1041
1042static void pid_set_group_pid(struct adapter *adapter, u16 pid)
1043{
1044 u32 value;
1045
1046 dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1047 value = (pid & 0x3fff) | (read_reg_dw(adapter, 0x30c) & 0xffff0000);
1048 write_reg_dw(adapter, 0x30c, value);
1049}
1050
1051static void pid_set_group_mask(struct adapter *adapter, u16 pid)
1052{
1053 u32 value;
1054
1055 dprintk("%s: pid=%x\n", __FUNCTION__, pid);
1056 value = ((pid & 0x3fff) << 0x10) | (read_reg_dw(adapter, 0x30c) & 0xffff);
1057 write_reg_dw(adapter, 0x30c, value);
1058}
1059
1060/*
1061static int pid_get_group_pid(struct adapter *adapter)
1062{
1063 return read_reg_dw(adapter, 0x30c) & 0x00001fff;
1064}
1065
1066static int pid_get_group_mask(struct adapter *adapter)
1067{
1068 return (read_reg_dw(adapter, 0x30c) >> 0x10)& 0x00001fff;
1069}
1070*/
1071
1072/*
1073static void reset_hardware_pid_filter(struct adapter *adapter)
1074{
1075 pid_set_stream1_pid(adapter, 0x1fff);
1076
1077 pid_set_stream2_pid(adapter, 0x1fff);
1078 filter_enable_stream2_filter(adapter, 0);
1079
1080 pid_set_pcr_pid(adapter, 0x1fff);
1081 filter_enable_pcr_filter(adapter, 0);
1082
1083 pid_set_pmt_pid(adapter, 0x1fff);
1084 filter_enable_pmt_filter(adapter, 0);
1085
1086 pid_set_ecm_pid(adapter, 0x1fff);
1087 filter_enable_ecm_filter(adapter, 0);
1088
1089 pid_set_emm_pid(adapter, 0x1fff);
1090 filter_enable_emm_filter(adapter, 0);
1091}
1092*/
1093
1094static void init_pids(struct adapter *adapter)
1095{
1096 int i;
1097
1098 adapter->pid_count = 0;
1099 adapter->whole_bandwidth_count = 0;
1100 for (i = 0; i < adapter->useable_hw_filters; i++) {
1101 dprintk("%s: setting filter %d to 0x1fff\n", __FUNCTION__, i);
1102 adapter->hw_pids[i] = 0x1fff;
1103 pid_set_hw_pid(adapter, i, 0x1fff);
1104}
1105
1106 pid_set_group_pid(adapter, 0);
1107 pid_set_group_mask(adapter, 0x1fe0);
1108}
1109
1110static void open_whole_bandwidth(struct adapter *adapter)
1111{
1112 dprintk("%s:\n", __FUNCTION__);
1113 pid_set_group_pid(adapter, 0);
1114 pid_set_group_mask(adapter, 0);
1115/*
1116 filter_enable_mask_filter(adapter, 1);
1117*/
1118}
1119
1120static void close_whole_bandwidth(struct adapter *adapter)
1121{
1122 dprintk("%s:\n", __FUNCTION__);
1123 pid_set_group_pid(adapter, 0);
1124 pid_set_group_mask(adapter, 0x1fe0);
1125/*
1126 filter_enable_mask_filter(adapter, 1);
1127*/
1128}
1129
1130static void whole_bandwidth_inc(struct adapter *adapter)
1131{
1132 if (adapter->whole_bandwidth_count++ == 0)
1133 open_whole_bandwidth(adapter);
1134}
1135
1136static void whole_bandwidth_dec(struct adapter *adapter)
1137{
1138 if (--adapter->whole_bandwidth_count <= 0)
1139 close_whole_bandwidth(adapter);
1140}
1141
1142/* The specified PID has to be let through the
1143 hw filters.
1144 We try to allocate an hardware filter and open whole
1145 bandwidth when allocation is impossible.
1146 All pids<=0x1f pass through the group filter.
1147 Returns 1 on success, -1 on error */
1148static int add_hw_pid(struct adapter *adapter, u16 pid)
1149{
1150 int i;
1151
1152 dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1153
1154 if (pid <= 0x1f)
1155 return 1;
1156
1157 /* we can't use a filter for 0x2000, so no search */
1158 if (pid != 0x2000) {
1159 /* find an unused hardware filter */
1160 for (i = 0; i < adapter->useable_hw_filters; i++) {
1161 dprintk("%s: pid=%d searching slot=%d\n", __FUNCTION__, pid, i);
1162 if (adapter->hw_pids[i] == 0x1fff) {
1163 dprintk("%s: pid=%d slot=%d\n", __FUNCTION__, pid, i);
1164 adapter->hw_pids[i] = pid;
1165 pid_set_hw_pid(adapter, i, pid);
1166 filter_enable_hw_filter(adapter, i, 1);
1167 return 1;
1168 }
1169 }
1170 }
1171 /* if we have not used a filter, this pid depends on whole bandwidth */
1172 dprintk("%s: pid=%d whole_bandwidth\n", __FUNCTION__, pid);
1173 whole_bandwidth_inc(adapter);
1174 return 1;
1175 }
1176
1177/* returns -1 if the pid was not present in the filters */
1178static int remove_hw_pid(struct adapter *adapter, u16 pid)
1179{
1180 int i;
1181
1182 dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1183
1184 if (pid <= 0x1f)
1185 return 1;
1186
1187 /* we can't use a filter for 0x2000, so no search */
1188 if (pid != 0x2000) {
1189 for (i = 0; i < adapter->useable_hw_filters; i++) {
1190 dprintk("%s: pid=%d searching slot=%d\n", __FUNCTION__, pid, i);
1191 if (adapter->hw_pids[i] == pid) { // find the pid slot
1192 dprintk("%s: pid=%d slot=%d\n", __FUNCTION__, pid, i);
1193 adapter->hw_pids[i] = 0x1fff;
1194 pid_set_hw_pid(adapter, i, 0x1fff);
1195 filter_enable_hw_filter(adapter, i, 0);
1196 return 1;
1197 }
1198 }
1199 }
1200 /* if we have not used a filter, this pid depended on whole bandwith */
1201 dprintk("%s: pid=%d whole_bandwidth\n", __FUNCTION__, pid);
1202 whole_bandwidth_dec(adapter);
1203 return 1;
1204 }
1205
1206/* Adds a PID to the filters.
1207 Adding a pid more than once is possible, we keep reference counts.
1208 Whole stream available through pid==0x2000.
1209 Returns 1 on success, -1 on error */
1210static int add_pid(struct adapter *adapter, u16 pid)
1211{
1212 int i;
1213
1214 dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1215
1216 if (pid > 0x1ffe && pid != 0x2000)
1217 return -1;
1218
1219 // check if the pid is already present
1220 for (i = 0; i < adapter->pid_count; i++)
1221 if (adapter->pid_list[i] == pid) {
1222 adapter->pid_rc[i]++; // increment ref counter
1223 return 1;
1224 }
1225
1226 if (adapter->pid_count == N_PID_SLOTS)
1227 return -1; // no more pids can be added
1228 adapter->pid_list[adapter->pid_count] = pid; // register pid
1229 adapter->pid_rc[adapter->pid_count] = 1;
1230 adapter->pid_count++;
1231 // hardware setting
1232 add_hw_pid(adapter, pid);
1233
1234 return 1;
1235 }
1236
1237/* Removes a PID from the filters. */
1238static int remove_pid(struct adapter *adapter, u16 pid)
1239{
1240 int i;
1241
1242 dprintk("%s: pid=%d\n", __FUNCTION__, pid);
1243
1244 if (pid > 0x1ffe && pid != 0x2000)
1245 return -1;
1246
1247 // check if the pid is present (it must be!)
1248 for (i = 0; i < adapter->pid_count; i++) {
1249 if (adapter->pid_list[i] == pid) {
1250 adapter->pid_rc[i]--;
1251 if (adapter->pid_rc[i] <= 0) {
1252 // remove from the list
1253 adapter->pid_count--;
1254 adapter->pid_list[i]=adapter->pid_list[adapter->pid_count];
1255 adapter->pid_rc[i] = adapter->pid_rc[adapter->pid_count];
1256 // hardware setting
1257 remove_hw_pid(adapter, pid);
1258 }
1259 return 1;
1260 }
1261 }
1262
1263 return -1;
1264}
1265
1266
1267/* dma & irq */
1268static void ctrl_enable_smc(struct adapter *adapter, u32 op)
1269{
1270 write_reg_bitfield(adapter, 0x208, 0x00000800, op ? 0x00000800 : 0);
1271}
1272
1273static void dma_enable_disable_irq(struct adapter *adapter, u32 flag1, u32 flag2, u32 flag3)
1274{
1275 adapter->dma_ctrl = adapter->dma_ctrl & 0x000f0000;
1276
1277 if (flag1 == 0) {
1278 if (flag2 == 0)
1279 adapter->dma_ctrl = adapter->dma_ctrl & ~0x00010000;
1280 else
1281 adapter->dma_ctrl = adapter->dma_ctrl | 0x00010000;
1282
1283 if (flag3 == 0)
1284 adapter->dma_ctrl = adapter->dma_ctrl & ~0x00020000;
1285 else
1286 adapter->dma_ctrl = adapter->dma_ctrl | 0x00020000;
1287
1288 } else {
1289
1290 if (flag2 == 0)
1291 adapter->dma_ctrl = adapter->dma_ctrl & ~0x00040000;
1292 else
1293 adapter->dma_ctrl = adapter->dma_ctrl | 0x00040000;
1294
1295 if (flag3 == 0)
1296 adapter->dma_ctrl = adapter->dma_ctrl & ~0x00080000;
1297 else
1298 adapter->dma_ctrl = adapter->dma_ctrl | 0x00080000;
1299 }
1300}
1301
1302static void irq_dma_enable_disable_irq(struct adapter *adapter, u32 op)
1303{
1304 u32 value;
1305
1306 value = read_reg_dw(adapter, 0x208) & 0xfff0ffff;
1307
1308 if (op != 0)
1309 value = value | (adapter->dma_ctrl & 0x000f0000);
1310
1311 write_reg_dw(adapter, 0x208, value);
1312}
1313
1314/* FlexCopII has 2 dma channels. DMA1 is used to transfer TS data to
1315 system memory.
1316
1317 The DMA1 buffer is divided in 2 subbuffers of equal size.
1318 FlexCopII will transfer TS data to one subbuffer, signal an interrupt
1319 when the subbuffer is full and continue fillig the second subbuffer.
1320
1321 For DMA1:
1322 subbuffer size in 32-bit words is stored in the first 24 bits of
1323 register 0x004. The last 8 bits of register 0x004 contain the number
1324 of subbuffers.
1325
1326 the first 30 bits of register 0x000 contain the address of the first
1327 subbuffer. The last 2 bits contain 0, when dma1 is disabled and 1,
1328 when dma1 is enabled.
1329
1330 the first 30 bits of register 0x00c contain the address of the second
1331 subbuffer. the last 2 bits contain 1.
1332
1333 register 0x008 will contain the address of the subbuffer that was filled
1334 with TS data, when FlexCopII will generate an interrupt.
1335
1336 For DMA2:
1337 subbuffer size in 32-bit words is stored in the first 24 bits of
1338 register 0x014. The last 8 bits of register 0x014 contain the number
1339 of subbuffers.
1340
1341 the first 30 bits of register 0x010 contain the address of the first
1342 subbuffer. The last 2 bits contain 0, when dma1 is disabled and 1,
1343 when dma1 is enabled.
1344
1345 the first 30 bits of register 0x01c contain the address of the second
1346 subbuffer. the last 2 bits contain 1.
1347
1348 register 0x018 contains the address of the subbuffer that was filled
1349 with TS data, when FlexCopII generates an interrupt.
1350*/
1351static int dma_init_dma(struct adapter *adapter, u32 dma_channel)
1352{
1353 u32 subbuffers, subbufsize, subbuf0, subbuf1;
1354
1355 if (dma_channel == 0) {
1356 dprintk("%s: Initializing DMA1 channel\n", __FUNCTION__);
1357
1358 subbuffers = 2;
1359
1360 subbufsize = (((adapter->dmaq1.buffer_size / 2) / 4) << 8) | subbuffers;
1361
1362 subbuf0 = adapter->dmaq1.bus_addr & 0xfffffffc;
1363
1364 subbuf1 = ((adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) & 0xfffffffc) | 1;
1365
1366 dprintk("%s: first subbuffer address = 0x%x\n", __FUNCTION__, subbuf0);
1367 udelay(1000);
1368 write_reg_dw(adapter, 0x000, subbuf0);
1369
1370 dprintk("%s: subbuffer size = 0x%x\n", __FUNCTION__, (subbufsize >> 8) * 4);
1371 udelay(1000);
1372 write_reg_dw(adapter, 0x004, subbufsize);
1373
1374 dprintk("%s: second subbuffer address = 0x%x\n", __FUNCTION__, subbuf1);
1375 udelay(1000);
1376 write_reg_dw(adapter, 0x00c, subbuf1);
1377
1378 dprintk("%s: counter = 0x%x\n", __FUNCTION__, adapter->dmaq1.bus_addr & 0xfffffffc);
1379 write_reg_dw(adapter, 0x008, adapter->dmaq1.bus_addr & 0xfffffffc);
1380 udelay(1000);
1381
1382 dma_enable_disable_irq(adapter, 0, 1, subbuffers ? 1 : 0);
1383
1384 irq_dma_enable_disable_irq(adapter, 1);
1385
1386 sram_set_media_dest(adapter, 1);
1387 sram_set_net_dest(adapter, 1);
1388 sram_set_cai_dest(adapter, 2);
1389 sram_set_cao_dest(adapter, 2);
1390 }
1391
1392 if (dma_channel == 1) {
1393 dprintk("%s: Initializing DMA2 channel\n", __FUNCTION__);
1394
1395 subbuffers = 2;
1396
1397 subbufsize = (((adapter->dmaq2.buffer_size / 2) / 4) << 8) | subbuffers;
1398
1399 subbuf0 = adapter->dmaq2.bus_addr & 0xfffffffc;
1400
1401 subbuf1 = ((adapter->dmaq2.bus_addr + adapter->dmaq2.buffer_size / 2) & 0xfffffffc) | 1;
1402
1403 dprintk("%s: first subbuffer address = 0x%x\n", __FUNCTION__, subbuf0);
1404 udelay(1000);
1405 write_reg_dw(adapter, 0x010, subbuf0);
1406
1407 dprintk("%s: subbuffer size = 0x%x\n", __FUNCTION__, (subbufsize >> 8) * 4);
1408 udelay(1000);
1409 write_reg_dw(adapter, 0x014, subbufsize);
1410
1411 dprintk("%s: second buffer address = 0x%x\n", __FUNCTION__, subbuf1);
1412 udelay(1000);
1413 write_reg_dw(adapter, 0x01c, subbuf1);
1414
1415 sram_set_cai_dest(adapter, 2);
1416 }
1417
1418 return 0;
1419}
1420
1421static void ctrl_enable_receive_data(struct adapter *adapter, u32 op)
1422{
1423 if (op == 0) {
1424 write_reg_bitfield(adapter, 0x208, 0x00008000, 0);
1425 adapter->dma_status = adapter->dma_status & ~0x00000004;
1426 } else {
1427 write_reg_bitfield(adapter, 0x208, 0x00008000, 0x00008000);
1428 adapter->dma_status = adapter->dma_status | 0x00000004;
1429 }
1430}
1431
1432/* bit 0 of dma_mask is set to 1 if dma1 channel has to be enabled/disabled
1433 bit 1 of dma_mask is set to 1 if dma2 channel has to be enabled/disabled
1434*/
1435static void dma_start_stop(struct adapter *adapter, u32 dma_mask, int start_stop)
1436{
1437 u32 dma_enable, dma1_enable, dma2_enable;
1438
1439 dprintk("%s: dma_mask=%x\n", __FUNCTION__, dma_mask);
1440
1441 if (start_stop == 1) {
1442 dprintk("%s: starting dma\n", __FUNCTION__);
1443
1444 dma1_enable = 0;
1445 dma2_enable = 0;
1446
1447 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) == 0) && (adapter->dmaq1.bus_addr != 0)) {
1448 adapter->dma_status = adapter->dma_status | 1;
1449 dma1_enable = 1;
1450 }
1451
1452 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) == 0) && (adapter->dmaq2.bus_addr != 0)) {
1453 adapter->dma_status = adapter->dma_status | 2;
1454 dma2_enable = 1;
1455 }
1456 // enable dma1 and dma2
1457 if ((dma1_enable == 1) && (dma2_enable == 1)) {
1458 write_reg_dw(adapter, 0x000, adapter->dmaq1.bus_addr | 1);
1459 write_reg_dw(adapter, 0x00c, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1460 write_reg_dw(adapter, 0x010, adapter->dmaq2.bus_addr | 1);
1461
1462 ctrl_enable_receive_data(adapter, 1);
1463
1464 return;
1465 }
1466 // enable dma1
1467 if ((dma1_enable == 1) && (dma2_enable == 0)) {
1468 write_reg_dw(adapter, 0x000, adapter->dmaq1.bus_addr | 1);
1469 write_reg_dw(adapter, 0x00c, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1470
1471 ctrl_enable_receive_data(adapter, 1);
1472
1473 return;
1474 }
1475 // enable dma2
1476 if ((dma1_enable == 0) && (dma2_enable == 1)) {
1477 write_reg_dw(adapter, 0x010, adapter->dmaq2.bus_addr | 1);
1478
1479 ctrl_enable_receive_data(adapter, 1);
1480
1481 return;
1482 }
1483 // start dma
1484 if ((dma1_enable == 0) && (dma2_enable == 0)) {
1485 ctrl_enable_receive_data(adapter, 1);
1486
1487 return;
1488 }
1489
1490 } else {
1491
1492 dprintk("%s: stopping dma\n", __FUNCTION__);
1493
1494 dma_enable = adapter->dma_status & 0x00000003;
1495
1496 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) != 0)) {
1497 dma_enable = dma_enable & 0xfffffffe;
1498 }
1499
1500 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) != 0)) {
1501 dma_enable = dma_enable & 0xfffffffd;
1502 }
1503 //stop dma
1504 if ((dma_enable == 0) && ((adapter->dma_status & 4) != 0)) {
1505 ctrl_enable_receive_data(adapter, 0);
1506
1507 udelay(3000);
1508 }
1509 //disable dma1
1510 if (((dma_mask & 1) != 0) && ((adapter->dma_status & 1) != 0) && (adapter->dmaq1.bus_addr != 0)) {
1511 write_reg_dw(adapter, 0x000, adapter->dmaq1.bus_addr);
1512 write_reg_dw(adapter, 0x00c, (adapter->dmaq1.bus_addr + adapter->dmaq1.buffer_size / 2) | 1);
1513
1514 adapter->dma_status = adapter->dma_status & ~0x00000001;
1515 }
1516 //disable dma2
1517 if (((dma_mask & 2) != 0) && ((adapter->dma_status & 2) != 0) && (adapter->dmaq2.bus_addr != 0)) {
1518 write_reg_dw(adapter, 0x010, adapter->dmaq2.bus_addr);
1519
1520 adapter->dma_status = adapter->dma_status & ~0x00000002;
1521 }
1522 }
1523}
1524
1525static void open_stream(struct adapter *adapter, u16 pid)
1526{
1527 u32 dma_mask;
1528
1529 ++adapter->capturing;
1530
1531 filter_enable_mask_filter(adapter, 1);
1532
1533 add_pid(adapter, pid);
1534
1535 dprintk("%s: adapter->dma_status=%x\n", __FUNCTION__, adapter->dma_status);
1536
1537 if ((adapter->dma_status & 7) != 7) {
1538 dma_mask = 0;
1539
1540 if (((adapter->dma_status & 0x10000000) != 0) && ((adapter->dma_status & 1) == 0)) {
1541 dma_mask = dma_mask | 1;
1542
1543 adapter->dmaq1.head = 0;
1544 adapter->dmaq1.tail = 0;
1545
1546 memset(adapter->dmaq1.buffer, 0, adapter->dmaq1.buffer_size);
1547 }
1548
1549 if (((adapter->dma_status & 0x20000000) != 0) && ((adapter->dma_status & 2) == 0)) {
1550 dma_mask = dma_mask | 2;
1551
1552 adapter->dmaq2.head = 0;
1553 adapter->dmaq2.tail = 0;
1554 }
1555
1556 if (dma_mask != 0) {
1557 irq_dma_enable_disable_irq(adapter, 1);
1558
1559 dma_start_stop(adapter, dma_mask, 1);
1560 }
1561 }
1562}
1563
1564static void close_stream(struct adapter *adapter, u16 pid)
1565{
1566 if (adapter->capturing > 0)
1567 --adapter->capturing;
1568
1569 dprintk("%s: dma_status=%x\n", __FUNCTION__, adapter->dma_status);
1570
1571 if (adapter->capturing == 0) {
1572 u32 dma_mask = 0;
1573
1574 if ((adapter->dma_status & 1) != 0)
1575 dma_mask = dma_mask | 0x00000001;
1576 if ((adapter->dma_status & 2) != 0)
1577 dma_mask = dma_mask | 0x00000002;
1578
1579 if (dma_mask != 0) {
1580 dma_start_stop(adapter, dma_mask, 0);
1581 }
1582 }
1583 remove_pid(adapter, pid);
1584}
1585
1586static void interrupt_service_dma1(struct adapter *adapter)
1587{
1588 struct dvb_demux *dvbdmx = &adapter->demux;
1589
1590 int n_cur_dma_counter;
1591 u32 n_num_bytes_parsed;
1592 u32 n_num_new_bytes_transferred;
1593 u32 dw_default_packet_size = 188;
1594 u8 gb_tmp_buffer[188];
1595 u8 *pb_dma_buf_cur_pos;
1596
1597 n_cur_dma_counter = readl(adapter->io_mem + 0x008) - adapter->dmaq1.bus_addr;
1598 n_cur_dma_counter = (n_cur_dma_counter / dw_default_packet_size) * dw_default_packet_size;
1599
1600 if ((n_cur_dma_counter < 0) || (n_cur_dma_counter > adapter->dmaq1.buffer_size)) {
1601 dprintk("%s: dma counter outside dma buffer\n", __FUNCTION__);
1602 return;
1603 }
1604
1605 adapter->dmaq1.head = n_cur_dma_counter;
1606
1607 if (adapter->dmaq1.tail <= n_cur_dma_counter) {
1608 n_num_new_bytes_transferred = n_cur_dma_counter - adapter->dmaq1.tail;
1609
1610 } else {
1611
1612 n_num_new_bytes_transferred = (adapter->dmaq1.buffer_size - adapter->dmaq1.tail) + n_cur_dma_counter;
1613 }
1614
1615 ddprintk("%s: n_cur_dma_counter = %d\n", __FUNCTION__, n_cur_dma_counter);
1616 ddprintk("%s: dmaq1.tail = %d\n", __FUNCTION__, adapter->dmaq1.tail);
1617 ddprintk("%s: bytes_transferred = %d\n", __FUNCTION__, n_num_new_bytes_transferred);
1618
1619 if (n_num_new_bytes_transferred < dw_default_packet_size)
1620 return;
1621
1622 n_num_bytes_parsed = 0;
1623
1624 while (n_num_bytes_parsed < n_num_new_bytes_transferred) {
1625 pb_dma_buf_cur_pos = adapter->dmaq1.buffer + adapter->dmaq1.tail;
1626
1627 if (adapter->dmaq1.buffer + adapter->dmaq1.buffer_size < adapter->dmaq1.buffer + adapter->dmaq1.tail + 188) {
1628 memcpy(gb_tmp_buffer, adapter->dmaq1.buffer + adapter->dmaq1.tail,
1629 adapter->dmaq1.buffer_size - adapter->dmaq1.tail);
1630 memcpy(gb_tmp_buffer + (adapter->dmaq1.buffer_size - adapter->dmaq1.tail), adapter->dmaq1.buffer,
1631 (188 - (adapter->dmaq1.buffer_size - adapter->dmaq1.tail)));
1632
1633 pb_dma_buf_cur_pos = gb_tmp_buffer;
1634 }
1635
1636 if (adapter->capturing != 0) {
1637 dvb_dmx_swfilter_packets(dvbdmx, pb_dma_buf_cur_pos, dw_default_packet_size / 188);
1638 }
1639
1640 n_num_bytes_parsed = n_num_bytes_parsed + dw_default_packet_size;
1641
1642 adapter->dmaq1.tail = adapter->dmaq1.tail + dw_default_packet_size;
1643
1644 if (adapter->dmaq1.tail >= adapter->dmaq1.buffer_size)
1645 adapter->dmaq1.tail = adapter->dmaq1.tail - adapter->dmaq1.buffer_size;
1646 };
1647}
1648
1649static void interrupt_service_dma2(struct adapter *adapter)
1650{
1651 printk("%s:\n", __FUNCTION__);
1652}
1653
1654static irqreturn_t isr(int irq, void *dev_id, struct pt_regs *regs)
1655{
1656 struct adapter *tmp = dev_id;
1657
1658 u32 value;
1659
1660 ddprintk("%s:\n", __FUNCTION__);
1661
1662 spin_lock_irq(&tmp->lock);
1663
1664 if (0 == ((value = read_reg_dw(tmp, 0x20c)) & 0x0f)) {
1665 spin_unlock_irq(&tmp->lock);
1666 return IRQ_NONE;
1667 }
1668
1669 while (value != 0) {
1670 if ((value & 0x03) != 0)
1671 interrupt_service_dma1(tmp);
1672 if ((value & 0x0c) != 0)
1673 interrupt_service_dma2(tmp);
1674 value = read_reg_dw(tmp, 0x20c) & 0x0f;
1675 }
1676
1677 spin_unlock_irq(&tmp->lock);
1678 return IRQ_HANDLED;
1679}
1680
1681static int init_dma_queue_one(struct adapter *adapter, struct dmaq *dmaq,
1682 int size, int dmaq_offset)
1683{
1684 struct pci_dev *pdev = adapter->pdev;
1685 dma_addr_t dma_addr;
1686
1687 dmaq->head = 0;
1688 dmaq->tail = 0;
1689
1690 dmaq->buffer = pci_alloc_consistent(pdev, size + 0x80, &dma_addr);
1691 if (!dmaq->buffer)
1692 return -ENOMEM;
1693
1694 dmaq->bus_addr = dma_addr;
1695 dmaq->buffer_size = size;
1696
1697 dma_init_dma(adapter, dmaq_offset);
1698
1699 ddprintk("%s: allocated dma buffer at 0x%p, length=%d\n",
1700 __FUNCTION__, dmaq->buffer, size);
1701
1702 return 0;
1703 }
1704
1705static int init_dma_queue(struct adapter *adapter)
1706{
1707 struct {
1708 struct dmaq *dmaq;
1709 u32 dma_status;
1710 int size;
1711 } dmaq_desc[] = {
1712 { &adapter->dmaq1, 0x10000000, SIZE_OF_BUF_DMA1 },
1713 { &adapter->dmaq2, 0x20000000, SIZE_OF_BUF_DMA2 }
1714 }, *p = dmaq_desc;
1715 int i;
1716
1717 for (i = 0; i < 2; i++, p++) {
1718 if (init_dma_queue_one(adapter, p->dmaq, p->size, i) < 0)
1719 adapter->dma_status &= ~p->dma_status;
1720 else
1721 adapter->dma_status |= p->dma_status;
1722 }
1723 return (adapter->dma_status & 0x30000000) ? 0 : -ENOMEM;
1724}
1725
1726static void free_dma_queue_one(struct adapter *adapter, struct dmaq *dmaq)
1727{
1728 if (dmaq->buffer) {
1729 pci_free_consistent(adapter->pdev, dmaq->buffer_size + 0x80,
1730 dmaq->buffer, dmaq->bus_addr);
1731 memset(dmaq, 0, sizeof(*dmaq));
1732 }
1733}
1734
1735static void free_dma_queue(struct adapter *adapter)
1736{
1737 struct dmaq *dmaq[] = {
1738 &adapter->dmaq1,
1739 &adapter->dmaq2,
1740 NULL
1741 }, **p;
1742
1743 for (p = dmaq; *p; p++)
1744 free_dma_queue_one(adapter, *p);
1745 }
1746
1747static void release_adapter(struct adapter *adapter)
1748{
1749 struct pci_dev *pdev = adapter->pdev;
1750
1751 iounmap(adapter->io_mem);
1752 pci_disable_device(pdev);
1753 pci_release_region(pdev, 0);
1754 pci_release_region(pdev, 1);
1755}
1756
1757static void free_adapter_object(struct adapter *adapter)
1758{
1759 dprintk("%s:\n", __FUNCTION__);
1760
1761 close_stream(adapter, 0);
1762 free_irq(adapter->irq, adapter);
1763 free_dma_queue(adapter);
1764 release_adapter(adapter);
1765 kfree(adapter);
1766}
1767
1768static struct pci_driver skystar2_pci_driver;
1769
1770static int claim_adapter(struct adapter *adapter)
1771{
1772 struct pci_dev *pdev = adapter->pdev;
1773 u16 var;
1774 int ret;
1775
1776 ret = pci_request_region(pdev, 1, skystar2_pci_driver.name);
1777 if (ret < 0)
1778 goto out;
1779
1780 ret = pci_request_region(pdev, 0, skystar2_pci_driver.name);
1781 if (ret < 0)
1782 goto err_pci_release_1;
1783
1784 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &adapter->card_revision);
1785
1786 dprintk("%s: card revision %x \n", __FUNCTION__, adapter->card_revision);
1787
1788 ret = pci_enable_device(pdev);
1789 if (ret < 0)
1790 goto err_pci_release_0;
1791
1792 pci_read_config_word(pdev, 4, &var);
1793
1794 if ((var & 4) == 0)
1795 pci_set_master(pdev);
1796
1797 adapter->io_port = pdev->resource[1].start;
1798
1799 adapter->io_mem = ioremap(pdev->resource[0].start, 0x800);
1800
1801 if (!adapter->io_mem) {
1802 dprintk("%s: can not map io memory\n", __FUNCTION__);
1803 ret = -EIO;
1804 goto err_pci_disable;
1805 }
1806
1807 dprintk("%s: io memory maped at %p\n", __FUNCTION__, adapter->io_mem);
1808
1809 ret = 1;
1810out:
1811 return ret;
1812
1813err_pci_disable:
1814 pci_disable_device(pdev);
1815err_pci_release_0:
1816 pci_release_region(pdev, 0);
1817err_pci_release_1:
1818 pci_release_region(pdev, 1);
1819 goto out;
1820}
1821
1822/*
1823static int sll_reset_flexcop(struct adapter *adapter)
1824{
1825 write_reg_dw(adapter, 0x208, 0);
1826 write_reg_dw(adapter, 0x210, 0xb2ff);
1827
1828 return 0;
1829}
1830*/
1831
1832static void decide_how_many_hw_filters(struct adapter *adapter)
1833{
1834 int hw_filters;
1835 int mod_option_hw_filters;
1836
1837 // FlexCop IIb & III have 6+32 hw filters
1838 // FlexCop II has 6 hw filters, every other should have at least 6
1839 switch (adapter->b2c2_revision) {
1840 case 0x82: /* II */
1841 hw_filters = 6;
1842 break;
1843 case 0xc3: /* IIB */
1844 hw_filters = 6 + 32;
1845 break;
1846 case 0xc0: /* III */
1847 hw_filters = 6 + 32;
1848 break;
1849 default:
1850 hw_filters = 6;
1851 break;
1852 }
1853 printk("%s: the chip has %i hardware filters", __FILE__, hw_filters);
1854
1855 mod_option_hw_filters = 0;
1856 if (enable_hw_filters >= 1)
1857 mod_option_hw_filters += 6;
1858 if (enable_hw_filters >= 2)
1859 mod_option_hw_filters += 32;
1860
1861 if (mod_option_hw_filters >= hw_filters) {
1862 adapter->useable_hw_filters = hw_filters;
1863 } else {
1864 adapter->useable_hw_filters = mod_option_hw_filters;
1865 printk(", but only %d will be used because of module option", mod_option_hw_filters);
1866 }
1867 printk("\n");
1868 dprintk("%s: useable_hardware_filters set to %i\n", __FILE__, adapter->useable_hw_filters);
1869}
1870
1871static int driver_initialize(struct pci_dev *pdev)
1872{
1873 struct adapter *adapter;
1874 u32 tmp;
1875 int ret = -ENOMEM;
1876
1877 adapter = kmalloc(sizeof(struct adapter), GFP_KERNEL);
1878 if (!adapter) {
1879 dprintk("%s: out of memory!\n", __FUNCTION__);
1880 goto out;
1881 }
1882
1883 memset(adapter, 0, sizeof(struct adapter));
1884
1885 pci_set_drvdata(pdev,adapter);
1886
1887 adapter->pdev = pdev;
1888 adapter->irq = pdev->irq;
1889
1890 ret = claim_adapter(adapter);
1891 if (ret < 0)
1892 goto err_kfree;
1893
1894 irq_dma_enable_disable_irq(adapter, 0);
1895
1896 ret = request_irq(pdev->irq, isr, 0x4000000, "Skystar2", adapter);
1897 if (ret < 0) {
1898 dprintk("%s: unable to allocate irq=%d !\n", __FUNCTION__, pdev->irq);
1899 goto err_release_adapter;
1900 }
1901
1902 read_reg_dw(adapter, 0x208);
1903 write_reg_dw(adapter, 0x208, 0);
1904 write_reg_dw(adapter, 0x210, 0xb2ff);
1905 write_reg_dw(adapter, 0x208, 0x40);
1906
1907 ret = init_dma_queue(adapter);
1908 if (ret < 0)
1909 goto err_free_irq;
1910
1911 adapter->b2c2_revision = (read_reg_dw(adapter, 0x204) >> 0x18);
1912
1913 switch (adapter->b2c2_revision) {
1914 case 0x82:
1915 printk("%s: FlexCopII(rev.130) chip found\n", __FILE__);
1916 break;
1917 case 0xc3:
1918 printk("%s: FlexCopIIB(rev.195) chip found\n", __FILE__);
1919 break;
1920 case 0xc0:
1921 printk("%s: FlexCopIII(rev.192) chip found\n", __FILE__);
1922 break;
1923 default:
1924 printk("%s: The revision of the FlexCop chip on your card is %d\n", __FILE__, adapter->b2c2_revision);
1925 printk("%s: This driver works only with FlexCopII(rev.130), FlexCopIIB(rev.195) and FlexCopIII(rev.192).\n", __FILE__);
1926 ret = -ENODEV;
1927 goto err_free_dma_queue;
1928 }
1929
1930 decide_how_many_hw_filters(adapter);
1931
1932 init_pids(adapter);
1933
1934 tmp = read_reg_dw(adapter, 0x204);
1935
1936 write_reg_dw(adapter, 0x204, 0);
1937 mdelay(20);
1938
1939 write_reg_dw(adapter, 0x204, tmp);
1940 mdelay(10);
1941
1942 tmp = read_reg_dw(adapter, 0x308);
1943 write_reg_dw(adapter, 0x308, 0x4000 | tmp);
1944
1945 adapter->dw_sram_type = 0x10000;
1946
1947 sll_detect_sram_size(adapter);
1948
1949 dprintk("%s sram length = %d, sram type= %x\n", __FUNCTION__, sram_length(adapter), adapter->dw_sram_type);
1950
1951 sram_set_media_dest(adapter, 1);
1952 sram_set_net_dest(adapter, 1);
1953
1954 ctrl_enable_smc(adapter, 0);
1955
1956 sram_set_cai_dest(adapter, 2);
1957 sram_set_cao_dest(adapter, 2);
1958
1959 dma_enable_disable_irq(adapter, 1, 0, 0);
1960
1961 if (eeprom_get_mac_addr(adapter, 0, adapter->mac_addr) != 0) {
1962 printk("%s MAC address = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x \n", __FUNCTION__, adapter->mac_addr[0],
1963 adapter->mac_addr[1], adapter->mac_addr[2], adapter->mac_addr[3], adapter->mac_addr[4], adapter->mac_addr[5],
1964 adapter->mac_addr[6], adapter->mac_addr[7]
1965 );
1966
1967 ca_set_mac_dst_addr_filter(adapter, adapter->mac_addr);
1968 ctrl_enable_mac(adapter, 1);
1969 }
1970
1971 spin_lock_init(&adapter->lock);
1972
1973out:
1974 return ret;
1975
1976err_free_dma_queue:
1977 free_dma_queue(adapter);
1978err_free_irq:
1979 free_irq(pdev->irq, adapter);
1980err_release_adapter:
1981 release_adapter(adapter);
1982err_kfree:
1983 pci_set_drvdata(pdev, NULL);
1984 kfree(adapter);
1985 goto out;
1986}
1987
1988static void driver_halt(struct pci_dev *pdev)
1989{
1990 struct adapter *adapter = pci_get_drvdata(pdev);
1991
1992 irq_dma_enable_disable_irq(adapter, 0);
1993
1994 ctrl_enable_receive_data(adapter, 0);
1995
1996 free_adapter_object(adapter);
1997
1998 pci_set_drvdata(pdev, NULL);
1999}
2000
2001static int dvb_start_feed(struct dvb_demux_feed *dvbdmxfeed)
2002{
2003 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
2004 struct adapter *adapter = (struct adapter *) dvbdmx->priv;
2005
2006 dprintk("%s: PID=%d, type=%d\n", __FUNCTION__, dvbdmxfeed->pid, dvbdmxfeed->type);
2007
2008 open_stream(adapter, dvbdmxfeed->pid);
2009
2010 return 0;
2011}
2012
2013static int dvb_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
2014{
2015 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
2016 struct adapter *adapter = (struct adapter *) dvbdmx->priv;
2017
2018 dprintk("%s: PID=%d, type=%d\n", __FUNCTION__, dvbdmxfeed->pid, dvbdmxfeed->type);
2019
2020 close_stream(adapter, dvbdmxfeed->pid);
2021
2022 return 0;
2023}
2024
2025/* lnb control */
2026static void set_tuner_tone(struct adapter *adapter, u8 tone)
2027{
2028 u16 wz_half_period_for_45_mhz[] = { 0x01ff, 0x0154, 0x00ff, 0x00cc };
2029 u16 ax;
2030
2031 dprintk("%s: %u\n", __FUNCTION__, tone);
2032
2033 switch (tone) {
2034 case 1:
2035 ax = wz_half_period_for_45_mhz[0];
2036 break;
2037 case 2:
2038 ax = wz_half_period_for_45_mhz[1];
2039 break;
2040 case 3:
2041 ax = wz_half_period_for_45_mhz[2];
2042 break;
2043 case 4:
2044 ax = wz_half_period_for_45_mhz[3];
2045 break;
2046
2047 default:
2048 ax = 0;
2049 }
2050
2051 if (ax != 0) {
2052 write_reg_dw(adapter, 0x200, ((ax << 0x0f) + (ax & 0x7fff)) | 0x40000000);
2053
2054 } else {
2055
2056 write_reg_dw(adapter, 0x200, 0x40ff8000);
2057 }
2058}
2059
2060static void set_tuner_polarity(struct adapter *adapter, u8 polarity)
2061{
2062 u32 var;
2063
2064 dprintk("%s : polarity = %u \n", __FUNCTION__, polarity);
2065
2066 var = read_reg_dw(adapter, 0x204);
2067
2068 if (polarity == 0) {
2069 dprintk("%s: LNB power off\n", __FUNCTION__);
2070 var = var | 1;
2071 };
2072
2073 if (polarity == 1) {
2074 var = var & ~1;
2075 var = var & ~4;
2076 };
2077
2078 if (polarity == 2) {
2079 var = var & ~1;
2080 var = var | 4;
2081 }
2082
2083 write_reg_dw(adapter, 0x204, var);
2084}
2085
2086static void diseqc_send_bit(struct adapter *adapter, int data)
2087{
2088 set_tuner_tone(adapter, 1);
2089 udelay(data ? 500 : 1000);
2090 set_tuner_tone(adapter, 0);
2091 udelay(data ? 1000 : 500);
2092}
2093
2094
2095static void diseqc_send_byte(struct adapter *adapter, int data)
2096 {
2097 int i, par = 1, d;
2098
2099 for (i = 7; i >= 0; i--) {
2100 d = (data >> i) & 1;
2101 par ^= d;
2102 diseqc_send_bit(adapter, d);
2103 }
2104
2105 diseqc_send_bit(adapter, par);
2106 }
2107
2108
2109static int send_diseqc_msg(struct adapter *adapter, int len, u8 *msg, unsigned long burst)
2110{
2111 int i;
2112
2113 set_tuner_tone(adapter, 0);
2114 mdelay(16);
2115
2116 for (i = 0; i < len; i++)
2117 diseqc_send_byte(adapter, msg[i]);
2118
2119 mdelay(16);
2120
2121 if (burst != -1) {
2122 if (burst)
2123 diseqc_send_byte(adapter, 0xff);
2124 else {
2125 set_tuner_tone(adapter, 1);
2126 udelay(12500);
2127 set_tuner_tone(adapter, 0);
2128 }
2129 msleep(20);
2130 }
2131
2132 return 0;
2133}
2134
2135static int flexcop_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
2136{
2137 struct adapter* adapter = (struct adapter*) fe->dvb->priv;
2138
2139 switch(tone) {
2140 case SEC_TONE_ON:
2141 set_tuner_tone(adapter, 1);
2142 break;
2143 case SEC_TONE_OFF:
2144 set_tuner_tone(adapter, 0);
2145 break;
2146 default:
2147 return -EINVAL;
2148 };
2149
2150 return 0;
2151}
2152
2153static int flexcop_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd)
2154 {
2155 struct adapter* adapter = (struct adapter*) fe->dvb->priv;
2156
2157 send_diseqc_msg(adapter, cmd->msg_len, cmd->msg, 0);
2158
2159 return 0;
2160 }
2161
2162static int flexcop_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd)
2163{
2164 struct adapter* adapter = (struct adapter*) fe->dvb->priv;
2165
2166 send_diseqc_msg(adapter, 0, NULL, minicmd);
2167
2168 return 0;
2169}
2170
2171static int flexcop_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
2172 {
2173 struct adapter* adapter = (struct adapter*) fe->dvb->priv;
2174
2175 dprintk("%s: FE_SET_VOLTAGE\n", __FUNCTION__);
2176
2177 switch (voltage) {
2178 case SEC_VOLTAGE_13:
2179 dprintk("%s: SEC_VOLTAGE_13, %x\n", __FUNCTION__, SEC_VOLTAGE_13);
2180 set_tuner_polarity(adapter, 1);
2181 return 0;
2182
2183 case SEC_VOLTAGE_18:
2184 dprintk("%s: SEC_VOLTAGE_18, %x\n", __FUNCTION__, SEC_VOLTAGE_18);
2185 set_tuner_polarity(adapter, 2);
2186 return 0;
2187
2188 default:
2189 return -EINVAL;
2190 }
2191 }
2192
2193static int flexcop_sleep(struct dvb_frontend* fe)
2194 {
2195 struct adapter* adapter = (struct adapter*) fe->dvb->priv;
2196
2197 dprintk("%s: FE_SLEEP\n", __FUNCTION__);
2198 set_tuner_polarity(adapter, 0);
2199
2200 if (adapter->fe_sleep) return adapter->fe_sleep(fe);
2201 return 0;
2202 }
2203
2204static u32 flexcop_i2c_func(struct i2c_adapter *adapter)
2205 {
2206 printk("flexcop_i2c_func\n");
2207
2208 return I2C_FUNC_I2C;
2209}
2210
2211static struct i2c_algorithm flexcop_algo = {
2212 .name = "flexcop i2c algorithm",
2213 .id = I2C_ALGO_BIT,
2214 .master_xfer = master_xfer,
2215 .functionality = flexcop_i2c_func,
2216};
2217
2218
2219
2220
2221static int samsung_tbmu24112_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ratio)
2222{
2223 u8 aclk = 0;
2224 u8 bclk = 0;
2225
2226 if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; }
2227 else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; }
2228 else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; }
2229 else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; }
2230 else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; }
2231 else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; }
2232
2233 stv0299_writereg (fe, 0x13, aclk);
2234 stv0299_writereg (fe, 0x14, bclk);
2235 stv0299_writereg (fe, 0x1f, (ratio >> 16) & 0xff);
2236 stv0299_writereg (fe, 0x20, (ratio >> 8) & 0xff);
2237 stv0299_writereg (fe, 0x21, (ratio ) & 0xf0);
2238
2239 return 0;
2240}
2241
2242static int samsung_tbmu24112_pll_set(struct dvb_frontend* fe, struct dvb_frontend_parameters* params)
2243{
2244 u8 buf[4];
2245 u32 div;
2246 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
2247 struct adapter* adapter = (struct adapter*) fe->dvb->priv;
2248
2249 div = params->frequency / 125;
2250
2251 buf[0] = (div >> 8) & 0x7f;
2252 buf[1] = div & 0xff;
2253 buf[2] = 0x84; // 0xC4
2254 buf[3] = 0x08;
2255
2256 if (params->frequency < 1500000) buf[3] |= 0x10;
2257
2258 if (i2c_transfer (&adapter->i2c_adap, &msg, 1) != 1) return -EIO;
2259 return 0;
2260}
2261
2262static u8 samsung_tbmu24112_inittab[] = {
2263 0x01, 0x15,
2264 0x02, 0x30,
2265 0x03, 0x00,
2266 0x04, 0x7D,
2267 0x05, 0x35,
2268 0x06, 0x02,
2269 0x07, 0x00,
2270 0x08, 0xC3,
2271 0x0C, 0x00,
2272 0x0D, 0x81,
2273 0x0E, 0x23,
2274 0x0F, 0x12,
2275 0x10, 0x7E,
2276 0x11, 0x84,
2277 0x12, 0xB9,
2278 0x13, 0x88,
2279 0x14, 0x89,
2280 0x15, 0xC9,
2281 0x16, 0x00,
2282 0x17, 0x5C,
2283 0x18, 0x00,
2284 0x19, 0x00,
2285 0x1A, 0x00,
2286 0x1C, 0x00,
2287 0x1D, 0x00,
2288 0x1E, 0x00,
2289 0x1F, 0x3A,
2290 0x20, 0x2E,
2291 0x21, 0x80,
2292 0x22, 0xFF,
2293 0x23, 0xC1,
2294 0x28, 0x00,
2295 0x29, 0x1E,
2296 0x2A, 0x14,
2297 0x2B, 0x0F,
2298 0x2C, 0x09,
2299 0x2D, 0x05,
2300 0x31, 0x1F,
2301 0x32, 0x19,
2302 0x33, 0xFE,
2303 0x34, 0x93,
2304 0xff, 0xff,
2305 };
2306
2307static struct stv0299_config samsung_tbmu24112_config = {
2308 .demod_address = 0x68,
2309 .inittab = samsung_tbmu24112_inittab,
2310 .mclk = 88000000UL,
2311 .invert = 0,
2312 .enhanced_tuning = 0,
2313 .skip_reinit = 0,
2314 .lock_output = STV0229_LOCKOUTPUT_LK,
2315 .volt13_op0_op1 = STV0299_VOLT13_OP1,
2316 .min_delay_ms = 100,
2317 .set_symbol_rate = samsung_tbmu24112_set_symbol_rate,
2318 .pll_set = samsung_tbmu24112_pll_set,
2319};
2320
2321
2322
2323static int nxt2002_request_firmware(struct dvb_frontend* fe, const struct firmware **fw, char* name)
2324{
2325 struct adapter* adapter = (struct adapter*) fe->dvb->priv;
2326
2327 return request_firmware(fw, name, &adapter->pdev->dev);
2328}
2329
2330
2331static struct nxt2002_config samsung_tbmv_config = {
2332 .demod_address = 0x0A,
2333 .request_firmware = nxt2002_request_firmware,
2334};
2335
2336static int samsung_tdtc9251dh0_demod_init(struct dvb_frontend* fe)
2337{
2338 static u8 mt352_clock_config [] = { 0x89, 0x18, 0x2d };
2339 static u8 mt352_reset [] = { 0x50, 0x80 };
2340 static u8 mt352_adc_ctl_1_cfg [] = { 0x8E, 0x40 };
2341 static u8 mt352_agc_cfg [] = { 0x67, 0x28, 0xa1 };
2342 static u8 mt352_capt_range_cfg[] = { 0x75, 0x32 };
2343
2344 mt352_write(fe, mt352_clock_config, sizeof(mt352_clock_config));
2345 udelay(2000);
2346 mt352_write(fe, mt352_reset, sizeof(mt352_reset));
2347 mt352_write(fe, mt352_adc_ctl_1_cfg, sizeof(mt352_adc_ctl_1_cfg));
2348
2349 mt352_write(fe, mt352_agc_cfg, sizeof(mt352_agc_cfg));
2350 mt352_write(fe, mt352_capt_range_cfg, sizeof(mt352_capt_range_cfg));
2351
2352 return 0;
2353}
2354
2355static int samsung_tdtc9251dh0_pll_set(struct dvb_frontend* fe, struct dvb_frontend_parameters* params, u8* pllbuf)
2356{
2357 u32 div;
2358 unsigned char bs = 0;
2359
2360 #define IF_FREQUENCYx6 217 /* 6 * 36.16666666667MHz */
2361 div = (((params->frequency + 83333) * 3) / 500000) + IF_FREQUENCYx6;
2362
2363 if (params->frequency >= 48000000 && params->frequency <= 154000000) bs = 0x09;
2364 if (params->frequency >= 161000000 && params->frequency <= 439000000) bs = 0x0a;
2365 if (params->frequency >= 447000000 && params->frequency <= 863000000) bs = 0x08;
2366
2367 pllbuf[0] = 0xc2; // Note: non-linux standard PLL i2c address
2368 pllbuf[1] = div >> 8;
2369 pllbuf[2] = div & 0xff;
2370 pllbuf[3] = 0xcc;
2371 pllbuf[4] = bs;
2372
2373 return 0;
2374}
2375
2376static struct mt352_config samsung_tdtc9251dh0_config = {
2377
2378 .demod_address = 0x0f,
2379 .demod_init = samsung_tdtc9251dh0_demod_init,
2380 .pll_set = samsung_tdtc9251dh0_pll_set,
2381};
2382
2383static int skystar23_samsung_tbdu18132_pll_set(struct dvb_frontend* fe, struct dvb_frontend_parameters* params)
2384{
2385 u8 buf[4];
2386 u32 div;
2387 struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
2388 struct adapter* adapter = (struct adapter*) fe->dvb->priv;
2389
2390 div = (params->frequency + (125/2)) / 125;
2391
2392 buf[0] = (div >> 8) & 0x7f;
2393 buf[1] = (div >> 0) & 0xff;
2394 buf[2] = 0x84 | ((div >> 10) & 0x60);
2395 buf[3] = 0x80;
2396
2397 if (params->frequency < 1550000)
2398 buf[3] |= 0x02;
2399
2400 if (i2c_transfer (&adapter->i2c_adap, &msg, 1) != 1) return -EIO;
2401 return 0;
2402}
2403
2404static struct mt312_config skystar23_samsung_tbdu18132_config = {
2405
2406 .demod_address = 0x0e,
2407 .pll_set = skystar23_samsung_tbdu18132_pll_set,
2408};
2409
2410
2411
2412
2413static void frontend_init(struct adapter *skystar2)
2414{
2415 switch(skystar2->pdev->device) {
2416 case 0x2103: // Technisat Skystar2 OR Technisat Airstar2 (DVB-T or ATSC)
2417
2418 // Attempt to load the Nextwave nxt2002 for ATSC support
2419 skystar2->fe = nxt2002_attach(&samsung_tbmv_config, &skystar2->i2c_adap);
2420 if (skystar2->fe != NULL) {
2421 skystar2->fe_sleep = skystar2->fe->ops->sleep;
2422 skystar2->fe->ops->sleep = flexcop_sleep;
2423 break;
2424 }
2425
2426 // try the skystar2 v2.6 first (stv0299/Samsung tbmu24112(sl1935))
2427 skystar2->fe = stv0299_attach(&samsung_tbmu24112_config, &skystar2->i2c_adap);
2428 if (skystar2->fe != NULL) {
2429 skystar2->fe->ops->set_voltage = flexcop_set_voltage;
2430 skystar2->fe_sleep = skystar2->fe->ops->sleep;
2431 skystar2->fe->ops->sleep = flexcop_sleep;
2432 break;
2433}
2434
2435 // try the airstar2 (mt352/Samsung tdtc9251dh0(??))
2436 skystar2->fe = mt352_attach(&samsung_tdtc9251dh0_config, &skystar2->i2c_adap);
2437 if (skystar2->fe != NULL) {
2438 skystar2->fe->ops->info.frequency_min = 474000000;
2439 skystar2->fe->ops->info.frequency_max = 858000000;
2440 break;
2441 }
2442
2443 // try the skystar2 v2.3 (vp310/Samsung tbdu18132(tsa5059))
2444 skystar2->fe = vp310_attach(&skystar23_samsung_tbdu18132_config, &skystar2->i2c_adap);
2445 if (skystar2->fe != NULL) {
2446 skystar2->fe->ops->diseqc_send_master_cmd = flexcop_diseqc_send_master_cmd;
2447 skystar2->fe->ops->diseqc_send_burst = flexcop_diseqc_send_burst;
2448 skystar2->fe->ops->set_tone = flexcop_set_tone;
2449 skystar2->fe->ops->set_voltage = flexcop_set_voltage;
2450 skystar2->fe_sleep = skystar2->fe->ops->sleep;
2451 skystar2->fe->ops->sleep = flexcop_sleep;
2452 break;
2453 }
2454 break;
2455 }
2456
2457 if (skystar2->fe == NULL) {
2458 printk("skystar2: A frontend driver was not found for device %04x/%04x subsystem %04x/%04x\n",
2459 skystar2->pdev->vendor,
2460 skystar2->pdev->device,
2461 skystar2->pdev->subsystem_vendor,
2462 skystar2->pdev->subsystem_device);
2463 } else {
2464 if (dvb_register_frontend(&skystar2->dvb_adapter, skystar2->fe)) {
2465 printk("skystar2: Frontend registration failed!\n");
2466 if (skystar2->fe->ops->release)
2467 skystar2->fe->ops->release(skystar2->fe);
2468 skystar2->fe = NULL;
2469 }
2470 }
2471}
2472
2473
2474static int skystar2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2475{
2476 struct adapter *adapter;
2477 struct dvb_adapter *dvb_adapter;
2478 struct dvb_demux *dvbdemux;
2479 struct dmx_demux *dmx;
2480 int ret = -ENODEV;
2481
2482 if (!pdev)
2483 goto out;
2484
2485 ret = driver_initialize(pdev);
2486 if (ret < 0)
2487 goto out;
2488
2489 adapter = pci_get_drvdata(pdev);
2490 dvb_adapter = &adapter->dvb_adapter;
2491
2492 ret = dvb_register_adapter(dvb_adapter, skystar2_pci_driver.name,
2493 THIS_MODULE);
2494 if (ret < 0) {
2495 printk("%s: Error registering DVB adapter\n", __FUNCTION__);
2496 goto err_halt;
2497 }
2498
2499 dvb_adapter->priv = adapter;
2500
2501
2502 init_MUTEX(&adapter->i2c_sem);
2503
2504
2505 memset(&adapter->i2c_adap, 0, sizeof(struct i2c_adapter));
2506 strcpy(adapter->i2c_adap.name, "SkyStar2");
2507
2508 i2c_set_adapdata(&adapter->i2c_adap, adapter);
2509
2510#ifdef I2C_ADAP_CLASS_TV_DIGITAL
2511 adapter->i2c_adap.class = I2C_ADAP_CLASS_TV_DIGITAL;
2512#else
2513 adapter->i2c_adap.class = I2C_CLASS_TV_DIGITAL;
2514#endif
2515 adapter->i2c_adap.algo = &flexcop_algo;
2516 adapter->i2c_adap.algo_data = NULL;
2517 adapter->i2c_adap.id = I2C_ALGO_BIT;
2518
2519 ret = i2c_add_adapter(&adapter->i2c_adap);
2520 if (ret < 0)
2521 goto err_dvb_unregister;
2522
2523 dvbdemux = &adapter->demux;
2524
2525 dvbdemux->priv = adapter;
2526 dvbdemux->filternum = N_PID_SLOTS;
2527 dvbdemux->feednum = N_PID_SLOTS;
2528 dvbdemux->start_feed = dvb_start_feed;
2529 dvbdemux->stop_feed = dvb_stop_feed;
2530 dvbdemux->write_to_decoder = NULL;
2531 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
2532
2533 ret = dvb_dmx_init(&adapter->demux);
2534 if (ret < 0)
2535 goto err_i2c_del;
2536
2537 dmx = &dvbdemux->dmx;
2538
2539 adapter->hw_frontend.source = DMX_FRONTEND_0;
2540 adapter->dmxdev.filternum = N_PID_SLOTS;
2541 adapter->dmxdev.demux = dmx;
2542 adapter->dmxdev.capabilities = 0;
2543
2544 ret = dvb_dmxdev_init(&adapter->dmxdev, &adapter->dvb_adapter);
2545 if (ret < 0)
2546 goto err_dmx_release;
2547
2548 ret = dmx->add_frontend(dmx, &adapter->hw_frontend);
2549 if (ret < 0)
2550 goto err_dmxdev_release;
2551
2552 adapter->mem_frontend.source = DMX_MEMORY_FE;
2553
2554 ret = dmx->add_frontend(dmx, &adapter->mem_frontend);
2555 if (ret < 0)
2556 goto err_remove_hw_frontend;
2557
2558 ret = dmx->connect_frontend(dmx, &adapter->hw_frontend);
2559 if (ret < 0)
2560 goto err_remove_mem_frontend;
2561
2562 dvb_net_init(&adapter->dvb_adapter, &adapter->dvbnet, &dvbdemux->dmx);
2563
2564 frontend_init(adapter);
2565out:
2566 return ret;
2567
2568err_remove_mem_frontend:
2569 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &adapter->mem_frontend);
2570err_remove_hw_frontend:
2571 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &adapter->hw_frontend);
2572err_dmxdev_release:
2573 dvb_dmxdev_release(&adapter->dmxdev);
2574err_dmx_release:
2575 dvb_dmx_release(&adapter->demux);
2576err_i2c_del:
2577 i2c_del_adapter(&adapter->i2c_adap);
2578err_dvb_unregister:
2579 dvb_unregister_adapter(&adapter->dvb_adapter);
2580err_halt:
2581 driver_halt(pdev);
2582 goto out;
2583}
2584
2585static void skystar2_remove(struct pci_dev *pdev)
2586{
2587 struct adapter *adapter = pci_get_drvdata(pdev);
2588 struct dvb_demux *dvbdemux;
2589 struct dmx_demux *dmx;
2590
2591 if (!adapter)
2592 return;
2593
2594 dvb_net_release(&adapter->dvbnet);
2595 dvbdemux = &adapter->demux;
2596 dmx = &dvbdemux->dmx;
2597
2598 dmx->close(dmx);
2599 dmx->remove_frontend(dmx, &adapter->hw_frontend);
2600 dmx->remove_frontend(dmx, &adapter->mem_frontend);
2601
2602 dvb_dmxdev_release(&adapter->dmxdev);
2603 dvb_dmx_release(dvbdemux);
2604
2605 if (adapter->fe != NULL)
2606 dvb_unregister_frontend(adapter->fe);
2607
2608 dvb_unregister_adapter(&adapter->dvb_adapter);
2609
2610 i2c_del_adapter(&adapter->i2c_adap);
2611
2612 driver_halt(pdev);
2613 }
2614
2615static struct pci_device_id skystar2_pci_tbl[] = {
2616 {0x000013d0, 0x00002103, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000},
2617/* {0x000013d0, 0x00002200, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000}, UNDEFINED HARDWARE - mail linuxtv.org list */ //FCIII
2618 {0,},
2619};
2620
2621MODULE_DEVICE_TABLE(pci, skystar2_pci_tbl);
2622
2623static struct pci_driver skystar2_pci_driver = {
2624 .name = "SkyStar2",
2625 .id_table = skystar2_pci_tbl,
2626 .probe = skystar2_probe,
2627 .remove = skystar2_remove,
2628};
2629
2630static int skystar2_init(void)
2631{
2632 return pci_register_driver(&skystar2_pci_driver);
2633}
2634
2635static void skystar2_cleanup(void)
2636{
2637 pci_unregister_driver(&skystar2_pci_driver);
2638}
2639
2640module_init(skystar2_init);
2641module_exit(skystar2_cleanup);
2642
2643MODULE_DESCRIPTION("Technisat SkyStar2 DVB PCI Driver");
2644MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 06:51:14 -0500