1 files changed, 451 insertions, 0 deletions
diff --git a/drivers/media/dvb-frontends/drxk_map.h b/drivers/media/dvb-frontends/drxk_map.h
new file mode 100644
index 000000000000..23e16c12f234
--- /dev/null
+++ b/drivers/media/dvb-frontends/drxk_map.h
@@ -0,0 +1,451 @@
+#define  AUD_COMM_EXEC__A                                                  0x1000000
+#define    AUD_COMM_EXEC_STOP                                              0x0
+#define  FEC_COMM_EXEC__A                                                  0x1C00000
+#define    FEC_COMM_EXEC_STOP                                              0x0
+#define    FEC_COMM_EXEC_ACTIVE                                            0x1
+#define  FEC_DI_COMM_EXEC__A                                               0x1C20000
+#define    FEC_DI_COMM_EXEC_STOP                                           0x0
+#define  FEC_DI_INPUT_CTL__A                                               0x1C20016
+#define  FEC_RS_COMM_EXEC__A                                               0x1C30000
+#define    FEC_RS_COMM_EXEC_STOP                                           0x0
+#define  FEC_RS_MEASUREMENT_PERIOD__A                                      0x1C30012
+#define  FEC_RS_MEASUREMENT_PRESCALE__A                                    0x1C30013
+#define  FEC_OC_MODE__A                                                    0x1C40011
+#define    FEC_OC_MODE_PARITY__M                                           0x1
+#define  FEC_OC_DTO_MODE__A                                                0x1C40014
+#define    FEC_OC_DTO_MODE_DYNAMIC__M                                      0x1
+#define    FEC_OC_DTO_MODE_OFFSET_ENABLE__M                                0x4
+#define  FEC_OC_DTO_PERIOD__A                                              0x1C40015
+#define  FEC_OC_DTO_BURST_LEN__A                                           0x1C40018
+#define  FEC_OC_FCT_MODE__A                                                0x1C4001A
+#define  FEC_OC_FCT_MODE__PRE                                              0x0
+#define    FEC_OC_FCT_MODE_RAT_ENA__M                                      0x1
+#define    FEC_OC_FCT_MODE_VIRT_ENA__M                                     0x2
+#define  FEC_OC_TMD_MODE__A                                                0x1C4001E
+#define  FEC_OC_TMD_COUNT__A                                               0x1C4001F
+#define  FEC_OC_TMD_HI_MARGIN__A                                           0x1C40020
+#define  FEC_OC_TMD_LO_MARGIN__A                                           0x1C40021
+#define  FEC_OC_TMD_INT_UPD_RATE__A                                        0x1C40023
+#define  FEC_OC_AVR_PARM_A__A                                              0x1C40026
+#define  FEC_OC_AVR_PARM_B__A                                              0x1C40027
+#define  FEC_OC_RCN_GAIN__A                                                0x1C4002E
+#define  FEC_OC_RCN_CTL_RATE_LO__A                                         0x1C40030
+#define  FEC_OC_RCN_CTL_STEP_LO__A                                         0x1C40032
+#define  FEC_OC_RCN_CTL_STEP_HI__A                                         0x1C40033
+#define  FEC_OC_SNC_MODE__A                                                0x1C40040
+#define    FEC_OC_SNC_MODE_SHUTDOWN__M                                     0x10
+#define  FEC_OC_SNC_LWM__A                                                 0x1C40041
+#define  FEC_OC_SNC_HWM__A                                                 0x1C40042
+#define  FEC_OC_SNC_UNLOCK__A                                              0x1C40043
+#define  FEC_OC_SNC_FAIL_PERIOD__A                                         0x1C40046
+#define  FEC_OC_IPR_MODE__A                                                0x1C40048
+#define    FEC_OC_IPR_MODE_SERIAL__M                                       0x1
+#define    FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M                             0x4
+#define    FEC_OC_IPR_MODE_MVAL_DIS_PAR__M                                 0x10
+#define  FEC_OC_IPR_INVERT__A                                              0x1C40049
+#define    FEC_OC_IPR_INVERT_MD0__M                                        0x1
+#define    FEC_OC_IPR_INVERT_MD1__M                                        0x2
+#define    FEC_OC_IPR_INVERT_MD2__M                                        0x4
+#define    FEC_OC_IPR_INVERT_MD3__M                                        0x8
+#define    FEC_OC_IPR_INVERT_MD4__M                                        0x10
+#define    FEC_OC_IPR_INVERT_MD5__M                                        0x20
+#define    FEC_OC_IPR_INVERT_MD6__M                                        0x40
+#define    FEC_OC_IPR_INVERT_MD7__M                                        0x80
+#define    FEC_OC_IPR_INVERT_MERR__M                                       0x100
+#define    FEC_OC_IPR_INVERT_MSTRT__M                                      0x200
+#define    FEC_OC_IPR_INVERT_MVAL__M                                       0x400
+#define    FEC_OC_IPR_INVERT_MCLK__M                                       0x800
+#define  FEC_OC_OCR_INVERT__A                                              0x1C40052
+#define  IQM_COMM_EXEC__A                                                  0x1800000
+#define      IQM_COMM_EXEC_B_STOP                                          0x0
+#define      IQM_COMM_EXEC_B_ACTIVE                                        0x1
+#define  IQM_FS_RATE_OFS_LO__A                                             0x1820010
+#define  IQM_FS_ADJ_SEL__A                                                 0x1820014
+#define      IQM_FS_ADJ_SEL_B_OFF                                          0x0
+#define      IQM_FS_ADJ_SEL_B_QAM                                          0x1
+#define      IQM_FS_ADJ_SEL_B_VSB                                          0x2
+#define  IQM_FD_RATESEL__A                                                 0x1830010
+#define  IQM_RC_RATE_OFS_LO__A                                             0x1840010
+#define  IQM_RC_RATE_OFS_LO__W                                             16
+#define  IQM_RC_RATE_OFS_LO__M                                             0xFFFF
+#define  IQM_RC_RATE_OFS_HI__M                                             0xFF
+#define  IQM_RC_ADJ_SEL__A                                                 0x1840014
+#define      IQM_RC_ADJ_SEL_B_OFF                                          0x0
+#define      IQM_RC_ADJ_SEL_B_QAM                                          0x1
+#define      IQM_RC_ADJ_SEL_B_VSB                                          0x2
+#define  IQM_RC_STRETCH__A                                                 0x1840016
+#define  IQM_CF_COMM_INT_MSK__A                                            0x1860006
+#define  IQM_CF_SYMMETRIC__A                                               0x1860010
+#define  IQM_CF_MIDTAP__A                                                  0x1860011
+#define    IQM_CF_MIDTAP_RE__B                                             0
+#define    IQM_CF_MIDTAP_IM__B                                             1
+#define  IQM_CF_OUT_ENA__A                                                 0x1860012
+#define    IQM_CF_OUT_ENA_QAM__B                                           1
+#define    IQM_CF_OUT_ENA_OFDM__M                                          0x4
+#define  IQM_CF_ADJ_SEL__A                                                 0x1860013
+#define  IQM_CF_SCALE__A                                                   0x1860014
+#define  IQM_CF_SCALE_SH__A                                                0x1860015
+#define  IQM_CF_SCALE_SH__PRE                                              0x0
+#define  IQM_CF_POW_MEAS_LEN__A                                            0x1860017
+#define  IQM_CF_DS_ENA__A                                                  0x1860019
+#define  IQM_CF_TAP_RE0__A                                                 0x1860020
+#define  IQM_CF_TAP_IM0__A                                                 0x1860040
+#define  IQM_CF_CLP_VAL__A                                                 0x1860060
+#define  IQM_CF_DATATH__A                                                  0x1860061
+#define  IQM_CF_PKDTH__A                                                   0x1860062
+#define  IQM_CF_WND_LEN__A                                                 0x1860063
+#define  IQM_CF_DET_LCT__A                                                 0x1860064
+#define  IQM_CF_BYPASSDET__A                                               0x1860067
+#define  IQM_AF_COMM_EXEC__A                                               0x1870000
+#define    IQM_AF_COMM_EXEC_ACTIVE                                         0x1
+#define  IQM_AF_CLKNEG__A                                                  0x1870012
+#define    IQM_AF_CLKNEG_CLKNEGDATA__M                                     0x2
+#define      IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS                     0x0
+#define      IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG                     0x2
+#define  IQM_AF_START_LOCK__A                                              0x187001B
+#define  IQM_AF_PHASE0__A                                                  0x187001C
+#define  IQM_AF_PHASE1__A                                                  0x187001D
+#define  IQM_AF_PHASE2__A                                                  0x187001E
+#define  IQM_AF_CLP_LEN__A                                                 0x1870023
+#define  IQM_AF_CLP_TH__A                                                  0x1870024
+#define  IQM_AF_SNS_LEN__A                                                 0x1870026
+#define  IQM_AF_AGC_IF__A                                                  0x1870028
+#define  IQM_AF_AGC_RF__A                                                  0x1870029
+#define  IQM_AF_PDREF__A                                                   0x187002B
+#define  IQM_AF_PDREF__M                                                   0x1F
+#define  IQM_AF_STDBY__A                                                   0x187002C
+#define      IQM_AF_STDBY_STDBY_ADC_STANDBY                                0x2
+#define      IQM_AF_STDBY_STDBY_AMP_STANDBY                                0x4
+#define      IQM_AF_STDBY_STDBY_PD_STANDBY                                 0x8
+#define      IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY                            0x10
+#define      IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY                            0x20
+#define  IQM_AF_AMUX__A                                                    0x187002D
+#define    IQM_AF_AMUX_SIGNAL2ADC                                          0x1
+#define  IQM_AF_UPD_SEL__A                                                 0x187002F
+#define  IQM_AF_INC_LCT__A                                                 0x1870034
+#define  IQM_AF_INC_BYPASS__A                                              0x1870036
+#define  OFDM_CP_COMM_EXEC__A                                              0x2800000
+#define    OFDM_CP_COMM_EXEC_STOP                                          0x0
+#define  OFDM_EC_SB_PRIOR__A                                               0x3410013
+#define    OFDM_EC_SB_PRIOR_HI                                             0x0
+#define    OFDM_EC_SB_PRIOR_LO                                             0x1
+#define  OFDM_EQ_TOP_TD_TPS_CONST__A                                       0x3010054
+#define  OFDM_EQ_TOP_TD_TPS_CONST__M                                       0x3
+#define    OFDM_EQ_TOP_TD_TPS_CONST_64QAM                                  0x2
+#define  OFDM_EQ_TOP_TD_TPS_CODE_HP__A                                     0x3010056
+#define  OFDM_EQ_TOP_TD_TPS_CODE_HP__M                                     0x7
+#define    OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8                                  0x4
+#define  OFDM_EQ_TOP_TD_SQR_ERR_I__A                                       0x301005E
+#define  OFDM_EQ_TOP_TD_SQR_ERR_Q__A                                       0x301005F
+#define  OFDM_EQ_TOP_TD_SQR_ERR_EXP__A                                     0x3010060
+#define  OFDM_EQ_TOP_TD_REQ_SMB_CNT__A                                     0x3010061
+#define  OFDM_EQ_TOP_TD_TPS_PWR_OFS__A                                     0x3010062
+#define  OFDM_LC_COMM_EXEC__A                                              0x3800000
+#define    OFDM_LC_COMM_EXEC_STOP                                          0x0
+#define  OFDM_SC_COMM_EXEC__A                                              0x3C00000
+#define    OFDM_SC_COMM_EXEC_STOP                                          0x0
+#define  OFDM_SC_COMM_STATE__A                                             0x3C00001
+#define  OFDM_SC_RA_RAM_PARAM0__A                                          0x3C20040
+#define  OFDM_SC_RA_RAM_PARAM1__A                                          0x3C20041
+#define  OFDM_SC_RA_RAM_CMD_ADDR__A                                        0x3C20042
+#define  OFDM_SC_RA_RAM_CMD__A                                             0x3C20043
+#define    OFDM_SC_RA_RAM_CMD_NULL                                         0x0
+#define    OFDM_SC_RA_RAM_CMD_PROC_START                                   0x1
+#define    OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM                               0x3
+#define    OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM                                0x4
+#define    OFDM_SC_RA_RAM_CMD_GET_OP_PARAM                                 0x5
+#define    OFDM_SC_RA_RAM_CMD_USER_IO                                      0x6
+#define    OFDM_SC_RA_RAM_CMD_SET_TIMER                                    0x7
+#define    OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING                              0x8
+#define    OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M                            0x1
+#define    OFDM_SC_RA_RAM_LOCKTRACK_MIN                                    0x1
+#define  OFDM_SC_RA_RAM_OP_PARAM__A                                        0x3C20048
+#define    OFDM_SC_RA_RAM_OP_PARAM_MODE__M                                 0x3
+#define      OFDM_SC_RA_RAM_OP_PARAM_MODE_2K                               0x0
+#define      OFDM_SC_RA_RAM_OP_PARAM_MODE_8K                               0x1
+#define      OFDM_SC_RA_RAM_OP_PARAM_GUARD_32                              0x0
+#define      OFDM_SC_RA_RAM_OP_PARAM_GUARD_16                              0x4
+#define      OFDM_SC_RA_RAM_OP_PARAM_GUARD_8                               0x8
+#define      OFDM_SC_RA_RAM_OP_PARAM_GUARD_4                               0xC
+#define      OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK                            0x0
+#define      OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16                           0x10
+#define      OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64                           0x20
+#define      OFDM_SC_RA_RAM_OP_PARAM_HIER_NO                               0x0
+#define      OFDM_SC_RA_RAM_OP_PARAM_HIER_A1                               0x40
+#define      OFDM_SC_RA_RAM_OP_PARAM_HIER_A2                               0x80
+#define      OFDM_SC_RA_RAM_OP_PARAM_HIER_A4                               0xC0
+#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2                              0x0
+#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3                              0x200
+#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4                              0x400
+#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6                              0x600
+#define      OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8                              0x800
+#define      OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI                               0x0
+#define      OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO                               0x1000
+#define    OFDM_SC_RA_RAM_OP_AUTO_MODE__M                                  0x1
+#define    OFDM_SC_RA_RAM_OP_AUTO_GUARD__M                                 0x2
+#define    OFDM_SC_RA_RAM_OP_AUTO_CONST__M                                 0x4
+#define    OFDM_SC_RA_RAM_OP_AUTO_HIER__M                                  0x8
+#define    OFDM_SC_RA_RAM_OP_AUTO_RATE__M                                  0x10
+#define  OFDM_SC_RA_RAM_LOCK__A                                            0x3C2004B
+#define    OFDM_SC_RA_RAM_LOCK_DEMOD__M                                    0x1
+#define    OFDM_SC_RA_RAM_LOCK_FEC__M                                      0x2
+#define    OFDM_SC_RA_RAM_LOCK_MPEG__M                                     0x4
+#define    OFDM_SC_RA_RAM_LOCK_NODVBT__M                                   0x8
+#define  OFDM_SC_RA_RAM_BE_OPT_DELAY__A                                    0x3C2004D
+#define  OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A                               0x3C2004E
+#define  OFDM_SC_RA_RAM_ECHO_THRES__A                                      0x3C2004F
+#define    OFDM_SC_RA_RAM_ECHO_THRES_8K__B                                 0
+#define    OFDM_SC_RA_RAM_ECHO_THRES_8K__M                                 0xFF
+#define    OFDM_SC_RA_RAM_ECHO_THRES_2K__B                                 8
+#define    OFDM_SC_RA_RAM_ECHO_THRES_2K__M                                 0xFF00
+#define  OFDM_SC_RA_RAM_CONFIG__A                                          0x3C20050
+#define    OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M                          0x800
+#define  OFDM_SC_RA_RAM_FR_THRES_8K__A                                     0x3C2007D
+#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A                             0x3C200E0
+#define  OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A                            0x3C200E1
+#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A                             0x3C200E3
+#define  OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A                            0x3C200E4
+#define  OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A                                0x3C200F8
+#define  QAM_COMM_EXEC__A                                                  0x1400000
+#define    QAM_COMM_EXEC_STOP                                              0x0
+#define    QAM_COMM_EXEC_ACTIVE                                            0x1
+#define    QAM_TOP_ANNEX_A                                                 0x0
+#define    QAM_TOP_ANNEX_C                                                 0x2
+#define  QAM_SL_ERR_POWER__A                                               0x1430017
+#define  QAM_DQ_QUAL_FUN0__A                                               0x1440018
+#define  QAM_DQ_QUAL_FUN1__A                                               0x1440019
+#define  QAM_DQ_QUAL_FUN2__A                                               0x144001A
+#define  QAM_DQ_QUAL_FUN3__A                                               0x144001B
+#define  QAM_DQ_QUAL_FUN4__A                                               0x144001C
+#define  QAM_DQ_QUAL_FUN5__A                                               0x144001D
+#define  QAM_LC_MODE__A                                                    0x1450010
+#define  QAM_LC_QUAL_TAB0__A                                               0x1450018
+#define  QAM_LC_QUAL_TAB1__A                                               0x1450019
+#define  QAM_LC_QUAL_TAB2__A                                               0x145001A
+#define  QAM_LC_QUAL_TAB3__A                                               0x145001B
+#define  QAM_LC_QUAL_TAB4__A                                               0x145001C
+#define  QAM_LC_QUAL_TAB5__A                                               0x145001D
+#define  QAM_LC_QUAL_TAB6__A                                               0x145001E
+#define  QAM_LC_QUAL_TAB8__A                                               0x145001F
+#define  QAM_LC_QUAL_TAB9__A                                               0x1450020
+#define  QAM_LC_QUAL_TAB10__A                                              0x1450021
+#define  QAM_LC_QUAL_TAB12__A                                              0x1450022
+#define  QAM_LC_QUAL_TAB15__A                                              0x1450023
+#define  QAM_LC_QUAL_TAB16__A                                              0x1450024
+#define  QAM_LC_QUAL_TAB20__A                                              0x1450025
+#define  QAM_LC_QUAL_TAB25__A                                              0x1450026
+#define  QAM_LC_LPF_FACTORP__A                                             0x1450028
+#define  QAM_LC_LPF_FACTORI__A                                             0x1450029
+#define  QAM_LC_RATE_LIMIT__A                                              0x145002A
+#define  QAM_LC_SYMBOL_FREQ__A                                             0x145002B
+#define  QAM_SY_TIMEOUT__A                                                 0x1470011
+#define  QAM_SY_TIMEOUT__PRE                                               0x3A98
+#define  QAM_SY_SYNC_LWM__A                                                0x1470012
+#define  QAM_SY_SYNC_AWM__A                                                0x1470013
+#define  QAM_SY_SYNC_HWM__A                                                0x1470014
+#define  QAM_SY_SP_INV__A                                                  0x1470017
+#define    QAM_SY_SP_INV_SPECTRUM_INV_DIS                                  0x0
+#define  SCU_COMM_EXEC__A                                                  0x800000
+#define    SCU_COMM_EXEC_STOP                                              0x0
+#define    SCU_COMM_EXEC_ACTIVE                                            0x1
+#define    SCU_COMM_EXEC_HOLD                                              0x2
+#define  SCU_RAM_DRIVER_DEBUG__A                                           0x831EBF
+#define  SCU_RAM_QAM_FSM_STEP_PERIOD__A                                    0x831EC4
+#define  SCU_RAM_GPIO__A                                                   0x831EC7
+#define      SCU_RAM_GPIO_HW_LOCK_IND_DISABLE                              0x0
+#define  SCU_RAM_AGC_CLP_CTRL_MODE__A                                      0x831EC8
+#define  SCU_RAM_FEC_ACCUM_PKT_FAILURES__A                                 0x831ECB
+#define  SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A                               0x831F05
+#define  SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A                                0x831F15
+#define  SCU_RAM_AGC_KI_CYCLEN__A                                          0x831F17
+#define  SCU_RAM_AGC_SNS_CYCLEN__A                                         0x831F18
+#define  SCU_RAM_AGC_RF_SNS_DEV_MAX__A                                     0x831F19
+#define  SCU_RAM_AGC_RF_SNS_DEV_MIN__A                                     0x831F1A
+#define  SCU_RAM_AGC_RF_MAX__A                                             0x831F1B
+#define  SCU_RAM_AGC_CONFIG__A                                             0x831F24
+#define    SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M                            0x1
+#define    SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M                            0x2
+#define    SCU_RAM_AGC_CONFIG_INV_IF_POL__M                                0x100
+#define    SCU_RAM_AGC_CONFIG_INV_RF_POL__M                                0x200
+#define  SCU_RAM_AGC_KI__A                                                 0x831F25
+#define    SCU_RAM_AGC_KI_RF__B                                            4
+#define    SCU_RAM_AGC_KI_RF__M                                            0xF0
+#define    SCU_RAM_AGC_KI_IF__B                                            8
+#define    SCU_RAM_AGC_KI_IF__M                                            0xF00
+#define  SCU_RAM_AGC_KI_RED__A                                             0x831F26
+#define    SCU_RAM_AGC_KI_RED_RAGC_RED__B                                  2
+#define    SCU_RAM_AGC_KI_RED_RAGC_RED__M                                  0xC
+#define    SCU_RAM_AGC_KI_RED_IAGC_RED__B                                  4
+#define    SCU_RAM_AGC_KI_RED_IAGC_RED__M                                  0x30
+#define  SCU_RAM_AGC_KI_INNERGAIN_MIN__A                                   0x831F27
+#define  SCU_RAM_AGC_KI_MINGAIN__A                                         0x831F28
+#define  SCU_RAM_AGC_KI_MAXGAIN__A                                         0x831F29
+#define  SCU_RAM_AGC_KI_MAXMINGAIN_TH__A                                   0x831F2A
+#define  SCU_RAM_AGC_KI_MIN__A                                             0x831F2B
+#define  SCU_RAM_AGC_KI_MAX__A                                             0x831F2C
+#define  SCU_RAM_AGC_CLP_SUM__A                                            0x831F2D
+#define  SCU_RAM_AGC_CLP_SUM_MIN__A                                        0x831F2E
+#define  SCU_RAM_AGC_CLP_SUM_MAX__A                                        0x831F2F
+#define  SCU_RAM_AGC_CLP_CYCLEN__A                                         0x831F30
+#define  SCU_RAM_AGC_CLP_CYCCNT__A                                         0x831F31
+#define  SCU_RAM_AGC_CLP_DIR_TO__A                                         0x831F32
+#define  SCU_RAM_AGC_CLP_DIR_WD__A                                         0x831F33
+#define  SCU_RAM_AGC_CLP_DIR_STP__A                                        0x831F34
+#define  SCU_RAM_AGC_SNS_SUM__A                                            0x831F35
+#define  SCU_RAM_AGC_SNS_SUM_MIN__A                                        0x831F36
+#define  SCU_RAM_AGC_SNS_SUM_MAX__A                                        0x831F37
+#define  SCU_RAM_AGC_SNS_CYCCNT__A                                         0x831F38
+#define  SCU_RAM_AGC_SNS_DIR_TO__A                                         0x831F39
+#define  SCU_RAM_AGC_SNS_DIR_WD__A                                         0x831F3A
+#define  SCU_RAM_AGC_SNS_DIR_STP__A                                        0x831F3B
+#define  SCU_RAM_AGC_INGAIN_TGT__A                                         0x831F3D
+#define  SCU_RAM_AGC_INGAIN_TGT_MIN__A                                     0x831F3E
+#define  SCU_RAM_AGC_INGAIN_TGT_MAX__A                                     0x831F3F
+#define  SCU_RAM_AGC_IF_IACCU_HI__A                                        0x831F40
+#define  SCU_RAM_AGC_IF_IACCU_LO__A                                        0x831F41
+#define  SCU_RAM_AGC_IF_IACCU_HI_TGT__A                                    0x831F42
+#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A                                0x831F43
+#define  SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A                                0x831F44
+#define  SCU_RAM_AGC_RF_IACCU_HI__A                                        0x831F45
+#define  SCU_RAM_AGC_RF_IACCU_LO__A                                        0x831F46
+#define  SCU_RAM_AGC_RF_IACCU_HI_CO__A                                     0x831F47
+#define  SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A                                 0x831F84
+#define  SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A                                0x831F85
+#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A                                  0x831F86
+#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A                                  0x831F87
+#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A                                  0x831F88
+#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A                                  0x831F89
+#define  SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A                                  0x831F8A
+#define  SCU_RAM_QAM_FSM_RTH__A                                            0x831F8E
+#define  SCU_RAM_QAM_FSM_FTH__A                                            0x831F8F
+#define  SCU_RAM_QAM_FSM_PTH__A                                            0x831F90
+#define  SCU_RAM_QAM_FSM_MTH__A                                            0x831F91
+#define  SCU_RAM_QAM_FSM_CTH__A                                            0x831F92
+#define  SCU_RAM_QAM_FSM_QTH__A                                            0x831F93
+#define  SCU_RAM_QAM_FSM_RATE_LIM__A                                       0x831F94
+#define  SCU_RAM_QAM_FSM_FREQ_LIM__A                                       0x831F95
+#define  SCU_RAM_QAM_FSM_COUNT_LIM__A                                      0x831F96
+#define  SCU_RAM_QAM_LC_CA_COARSE__A                                       0x831F97
+#define  SCU_RAM_QAM_LC_CA_FINE__A                                         0x831F99
+#define  SCU_RAM_QAM_LC_CP_COARSE__A                                       0x831F9A
+#define  SCU_RAM_QAM_LC_CP_MEDIUM__A                                       0x831F9B
+#define  SCU_RAM_QAM_LC_CP_FINE__A                                         0x831F9C
+#define  SCU_RAM_QAM_LC_CI_COARSE__A                                       0x831F9D
+#define  SCU_RAM_QAM_LC_CI_MEDIUM__A                                       0x831F9E
+#define  SCU_RAM_QAM_LC_CI_FINE__A                                         0x831F9F
+#define  SCU_RAM_QAM_LC_EP_COARSE__A                                       0x831FA0
+#define  SCU_RAM_QAM_LC_EP_MEDIUM__A                                       0x831FA1
+#define  SCU_RAM_QAM_LC_EP_FINE__A                                         0x831FA2
+#define  SCU_RAM_QAM_LC_EI_COARSE__A                                       0x831FA3
+#define  SCU_RAM_QAM_LC_EI_MEDIUM__A                                       0x831FA4
+#define  SCU_RAM_QAM_LC_EI_FINE__A                                         0x831FA5
+#define  SCU_RAM_QAM_LC_CF_COARSE__A                                       0x831FA6
+#define  SCU_RAM_QAM_LC_CF_MEDIUM__A                                       0x831FA7
+#define  SCU_RAM_QAM_LC_CF_FINE__A                                         0x831FA8
+#define  SCU_RAM_QAM_LC_CF1_COARSE__A                                      0x831FA9
+#define  SCU_RAM_QAM_LC_CF1_MEDIUM__A                                      0x831FAA
+#define  SCU_RAM_QAM_LC_CF1_FINE__A                                        0x831FAB
+#define  SCU_RAM_QAM_SL_SIG_POWER__A                                       0x831FAC
+#define  SCU_RAM_QAM_EQ_CMA_RAD0__A                                        0x831FAD
+#define  SCU_RAM_QAM_EQ_CMA_RAD1__A                                        0x831FAE
+#define  SCU_RAM_QAM_EQ_CMA_RAD2__A                                        0x831FAF
+#define  SCU_RAM_QAM_EQ_CMA_RAD3__A                                        0x831FB0
+#define  SCU_RAM_QAM_EQ_CMA_RAD4__A                                        0x831FB1
+#define  SCU_RAM_QAM_EQ_CMA_RAD5__A                                        0x831FB2
+#define      SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED                        0x4000
+#define      SCU_RAM_QAM_LOCKED_LOCKED_LOCKED                              0x8000
+#define      SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK                          0xC000
+#define  SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A                                0x831FEA
+#define  SCU_RAM_DRIVER_VER_HI__A                                          0x831FEB
+#define  SCU_RAM_DRIVER_VER_LO__A                                          0x831FEC
+#define  SCU_RAM_PARAM_15__A                                               0x831FED
+#define  SCU_RAM_PARAM_0__A                                                0x831FFC
+#define  SCU_RAM_COMMAND__A                                                0x831FFD
+#define    SCU_RAM_COMMAND_CMD_DEMOD_RESET                                 0x1
+#define    SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV                               0x2
+#define    SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM                             0x3
+#define    SCU_RAM_COMMAND_CMD_DEMOD_START                                 0x4
+#define    SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK                              0x5
+#define    SCU_RAM_COMMAND_CMD_DEMOD_STOP                                  0x9
+#define      SCU_RAM_COMMAND_STANDARD_QAM                                  0x200
+#define      SCU_RAM_COMMAND_STANDARD_OFDM                                 0x400
+#define  SIO_TOP_COMM_KEY__A                                               0x41000F
+#define    SIO_TOP_COMM_KEY_KEY                                            0xFABA
+#define  SIO_TOP_JTAGID_LO__A                                              0x410012
+#define  SIO_HI_RA_RAM_RES__A                                              0x420031
+#define  SIO_HI_RA_RAM_CMD__A                                              0x420032
+#define    SIO_HI_RA_RAM_CMD_RESET                                         0x2
+#define    SIO_HI_RA_RAM_CMD_CONFIG                                        0x3
+#define    SIO_HI_RA_RAM_CMD_BRDCTRL                                       0x7
+#define  SIO_HI_RA_RAM_PAR_1__A                                            0x420033
+#define      SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY                              0x3945
+#define  SIO_HI_RA_RAM_PAR_2__A                                            0x420034
+#define    SIO_HI_RA_RAM_PAR_2_CFG_DIV__M                                  0x7F
+#define      SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN                              0x0
+#define      SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED                            0x4
+#define  SIO_HI_RA_RAM_PAR_3__A                                            0x420035
+#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M                              0x7F
+#define    SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B                              7
+#define      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ                               0x0
+#define      SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE                              0x8
+#define  SIO_HI_RA_RAM_PAR_4__A                                            0x420036
+#define  SIO_HI_RA_RAM_PAR_5__A                                            0x420037
+#define      SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE                            0x1
+#define    SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M                                0x8
+#define      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ                             0x8
+#define  SIO_HI_RA_RAM_PAR_6__A                                            0x420038
+#define  SIO_CC_PLL_LOCK__A                                                0x450012
+#define  SIO_CC_PWD_MODE__A                                                0x450015
+#define      SIO_CC_PWD_MODE_LEVEL_NONE                                    0x0
+#define      SIO_CC_PWD_MODE_LEVEL_OFDM                                    0x1
+#define      SIO_CC_PWD_MODE_LEVEL_CLOCK                                   0x2
+#define      SIO_CC_PWD_MODE_LEVEL_PLL                                     0x3
+#define      SIO_CC_PWD_MODE_LEVEL_OSC                                     0x4
+#define  SIO_CC_SOFT_RST__A                                                0x450016
+#define    SIO_CC_SOFT_RST_OFDM__M                                         0x1
+#define    SIO_CC_SOFT_RST_SYS__M                                          0x2
+#define    SIO_CC_SOFT_RST_OSC__M                                          0x4
+#define  SIO_CC_UPDATE__A                                                  0x450017
+#define    SIO_CC_UPDATE_KEY                                               0xFABA
+#define  SIO_OFDM_SH_OFDM_RING_ENABLE__A                                   0x470010
+#define    SIO_OFDM_SH_OFDM_RING_ENABLE_OFF                                0x0
+#define    SIO_OFDM_SH_OFDM_RING_ENABLE_ON                                 0x1
+#define  SIO_OFDM_SH_OFDM_RING_STATUS__A                                   0x470012
+#define    SIO_OFDM_SH_OFDM_RING_STATUS_DOWN                               0x0
+#define    SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED                            0x1
+#define  SIO_BL_COMM_EXEC__A                                               0x480000
+#define    SIO_BL_COMM_EXEC_ACTIVE                                         0x1
+#define  SIO_BL_STATUS__A                                                  0x480010
+#define  SIO_BL_MODE__A                                                    0x480011
+#define    SIO_BL_MODE_DIRECT                                              0x0
+#define    SIO_BL_MODE_CHAIN                                               0x1
+#define  SIO_BL_ENABLE__A                                                  0x480012
+#define    SIO_BL_ENABLE_ON                                                0x1
+#define  SIO_BL_TGT_HDR__A                                                 0x480014
+#define  SIO_BL_TGT_ADDR__A                                                0x480015
+#define  SIO_BL_SRC_ADDR__A                                                0x480016
+#define  SIO_BL_SRC_LEN__A                                                 0x480017
+#define  SIO_BL_CHAIN_ADDR__A                                              0x480018
+#define  SIO_BL_CHAIN_LEN__A                                               0x480019
+#define  SIO_PDR_MON_CFG__A                                                0x7F0010
+#define  SIO_PDR_UIO_IN_HI__A                                              0x7F0015
+#define  SIO_PDR_UIO_OUT_LO__A                                             0x7F0016
+#define  SIO_PDR_OHW_CFG__A                                                0x7F001F
+#define    SIO_PDR_OHW_CFG_FREF_SEL__M                                     0x3
+#define  SIO_PDR_GPIO_CFG__A                                               0x7F0021
+#define  SIO_PDR_MSTRT_CFG__A                                              0x7F0025
+#define  SIO_PDR_MERR_CFG__A                                               0x7F0026
+#define  SIO_PDR_MCLK_CFG__A                                               0x7F0028
+#define    SIO_PDR_MCLK_CFG_DRIVE__B                                       3
+#define  SIO_PDR_MVAL_CFG__A                                               0x7F0029
+#define  SIO_PDR_MD0_CFG__A                                                0x7F002A
+#define    SIO_PDR_MD0_CFG_DRIVE__B                                        3
+#define  SIO_PDR_MD1_CFG__A                                                0x7F002B
+#define  SIO_PDR_MD2_CFG__A                                                0x7F002C
+#define  SIO_PDR_MD3_CFG__A                                                0x7F002D
+#define  SIO_PDR_MD4_CFG__A                                                0x7F002F
+#define  SIO_PDR_MD5_CFG__A                                                0x7F0030
+#define  SIO_PDR_MD6_CFG__A                                                0x7F0031
+#define  SIO_PDR_MD7_CFG__A                                                0x7F0032
+#define  SIO_PDR_SMA_RX_CFG__A                                             0x7F0037
+#define  SIO_PDR_SMA_TX_CFG__A                                             0x7F0038

diff --git a/drivers/media/dvb-frontends/drxk_map.h b/drivers/media/dvb-frontends/drxk_map.h new file mode 100644 index 000000000000..23e16c12f234 --- /dev/null +++ b/drivers/media/dvb-frontends/drxk_map.h
@@ -0,0 +1,451 @@
	1	#define AUD_COMM_EXEC__A 0x1000000
	2	#define AUD_COMM_EXEC_STOP 0x0
	3	#define FEC_COMM_EXEC__A 0x1C00000
	4	#define FEC_COMM_EXEC_STOP 0x0
	5	#define FEC_COMM_EXEC_ACTIVE 0x1
	6	#define FEC_DI_COMM_EXEC__A 0x1C20000
	7	#define FEC_DI_COMM_EXEC_STOP 0x0
	8	#define FEC_DI_INPUT_CTL__A 0x1C20016
	9	#define FEC_RS_COMM_EXEC__A 0x1C30000
	10	#define FEC_RS_COMM_EXEC_STOP 0x0
	11	#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012
	12	#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013
	13	#define FEC_OC_MODE__A 0x1C40011
	14	#define FEC_OC_MODE_PARITY__M 0x1
	15	#define FEC_OC_DTO_MODE__A 0x1C40014
	16	#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1
	17	#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
	18	#define FEC_OC_DTO_PERIOD__A 0x1C40015
	19	#define FEC_OC_DTO_BURST_LEN__A 0x1C40018
	20	#define FEC_OC_FCT_MODE__A 0x1C4001A
	21	#define FEC_OC_FCT_MODE__PRE 0x0
	22	#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1
	23	#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2
	24	#define FEC_OC_TMD_MODE__A 0x1C4001E
	25	#define FEC_OC_TMD_COUNT__A 0x1C4001F
	26	#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020
	27	#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021
	28	#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023
	29	#define FEC_OC_AVR_PARM_A__A 0x1C40026
	30	#define FEC_OC_AVR_PARM_B__A 0x1C40027
	31	#define FEC_OC_RCN_GAIN__A 0x1C4002E
	32	#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030
	33	#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032
	34	#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033
	35	#define FEC_OC_SNC_MODE__A 0x1C40040
	36	#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10
	37	#define FEC_OC_SNC_LWM__A 0x1C40041
	38	#define FEC_OC_SNC_HWM__A 0x1C40042
	39	#define FEC_OC_SNC_UNLOCK__A 0x1C40043
	40	#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046
	41	#define FEC_OC_IPR_MODE__A 0x1C40048
	42	#define FEC_OC_IPR_MODE_SERIAL__M 0x1
	43	#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4
	44	#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10
	45	#define FEC_OC_IPR_INVERT__A 0x1C40049
	46	#define FEC_OC_IPR_INVERT_MD0__M 0x1
	47	#define FEC_OC_IPR_INVERT_MD1__M 0x2
	48	#define FEC_OC_IPR_INVERT_MD2__M 0x4
	49	#define FEC_OC_IPR_INVERT_MD3__M 0x8
	50	#define FEC_OC_IPR_INVERT_MD4__M 0x10
	51	#define FEC_OC_IPR_INVERT_MD5__M 0x20
	52	#define FEC_OC_IPR_INVERT_MD6__M 0x40
	53	#define FEC_OC_IPR_INVERT_MD7__M 0x80
	54	#define FEC_OC_IPR_INVERT_MERR__M 0x100
	55	#define FEC_OC_IPR_INVERT_MSTRT__M 0x200
	56	#define FEC_OC_IPR_INVERT_MVAL__M 0x400
	57	#define FEC_OC_IPR_INVERT_MCLK__M 0x800
	58	#define FEC_OC_OCR_INVERT__A 0x1C40052
	59	#define IQM_COMM_EXEC__A 0x1800000
	60	#define IQM_COMM_EXEC_B_STOP 0x0
	61	#define IQM_COMM_EXEC_B_ACTIVE 0x1
	62	#define IQM_FS_RATE_OFS_LO__A 0x1820010
	63	#define IQM_FS_ADJ_SEL__A 0x1820014
	64	#define IQM_FS_ADJ_SEL_B_OFF 0x0
	65	#define IQM_FS_ADJ_SEL_B_QAM 0x1
	66	#define IQM_FS_ADJ_SEL_B_VSB 0x2
	67	#define IQM_FD_RATESEL__A 0x1830010
	68	#define IQM_RC_RATE_OFS_LO__A 0x1840010
	69	#define IQM_RC_RATE_OFS_LO__W 16
	70	#define IQM_RC_RATE_OFS_LO__M 0xFFFF
	71	#define IQM_RC_RATE_OFS_HI__M 0xFF
	72	#define IQM_RC_ADJ_SEL__A 0x1840014
	73	#define IQM_RC_ADJ_SEL_B_OFF 0x0
	74	#define IQM_RC_ADJ_SEL_B_QAM 0x1
	75	#define IQM_RC_ADJ_SEL_B_VSB 0x2
	76	#define IQM_RC_STRETCH__A 0x1840016
	77	#define IQM_CF_COMM_INT_MSK__A 0x1860006
	78	#define IQM_CF_SYMMETRIC__A 0x1860010
	79	#define IQM_CF_MIDTAP__A 0x1860011
	80	#define IQM_CF_MIDTAP_RE__B 0
	81	#define IQM_CF_MIDTAP_IM__B 1
	82	#define IQM_CF_OUT_ENA__A 0x1860012
	83	#define IQM_CF_OUT_ENA_QAM__B 1
	84	#define IQM_CF_OUT_ENA_OFDM__M 0x4
	85	#define IQM_CF_ADJ_SEL__A 0x1860013
	86	#define IQM_CF_SCALE__A 0x1860014
	87	#define IQM_CF_SCALE_SH__A 0x1860015
	88	#define IQM_CF_SCALE_SH__PRE 0x0
	89	#define IQM_CF_POW_MEAS_LEN__A 0x1860017
	90	#define IQM_CF_DS_ENA__A 0x1860019
	91	#define IQM_CF_TAP_RE0__A 0x1860020
	92	#define IQM_CF_TAP_IM0__A 0x1860040
	93	#define IQM_CF_CLP_VAL__A 0x1860060
	94	#define IQM_CF_DATATH__A 0x1860061
	95	#define IQM_CF_PKDTH__A 0x1860062
	96	#define IQM_CF_WND_LEN__A 0x1860063
	97	#define IQM_CF_DET_LCT__A 0x1860064
	98	#define IQM_CF_BYPASSDET__A 0x1860067
	99	#define IQM_AF_COMM_EXEC__A 0x1870000
	100	#define IQM_AF_COMM_EXEC_ACTIVE 0x1
	101	#define IQM_AF_CLKNEG__A 0x1870012
	102	#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2
	103	#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0
	104	#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
	105	#define IQM_AF_START_LOCK__A 0x187001B
	106	#define IQM_AF_PHASE0__A 0x187001C
	107	#define IQM_AF_PHASE1__A 0x187001D
	108	#define IQM_AF_PHASE2__A 0x187001E
	109	#define IQM_AF_CLP_LEN__A 0x1870023
	110	#define IQM_AF_CLP_TH__A 0x1870024
	111	#define IQM_AF_SNS_LEN__A 0x1870026
	112	#define IQM_AF_AGC_IF__A 0x1870028
	113	#define IQM_AF_AGC_RF__A 0x1870029
	114	#define IQM_AF_PDREF__A 0x187002B
	115	#define IQM_AF_PDREF__M 0x1F
	116	#define IQM_AF_STDBY__A 0x187002C
	117	#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2
	118	#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4
	119	#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8
	120	#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10
	121	#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20
	122	#define IQM_AF_AMUX__A 0x187002D
	123	#define IQM_AF_AMUX_SIGNAL2ADC 0x1
	124	#define IQM_AF_UPD_SEL__A 0x187002F
	125	#define IQM_AF_INC_LCT__A 0x1870034
	126	#define IQM_AF_INC_BYPASS__A 0x1870036
	127	#define OFDM_CP_COMM_EXEC__A 0x2800000
	128	#define OFDM_CP_COMM_EXEC_STOP 0x0
	129	#define OFDM_EC_SB_PRIOR__A 0x3410013
	130	#define OFDM_EC_SB_PRIOR_HI 0x0
	131	#define OFDM_EC_SB_PRIOR_LO 0x1
	132	#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054
	133	#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3
	134	#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2
	135	#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056
	136	#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7
	137	#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4
	138	#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E
	139	#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F
	140	#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060
	141	#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061
	142	#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062
	143	#define OFDM_LC_COMM_EXEC__A 0x3800000
	144	#define OFDM_LC_COMM_EXEC_STOP 0x0
	145	#define OFDM_SC_COMM_EXEC__A 0x3C00000
	146	#define OFDM_SC_COMM_EXEC_STOP 0x0
	147	#define OFDM_SC_COMM_STATE__A 0x3C00001
	148	#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040
	149	#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041
	150	#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042
	151	#define OFDM_SC_RA_RAM_CMD__A 0x3C20043
	152	#define OFDM_SC_RA_RAM_CMD_NULL 0x0
	153	#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1
	154	#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
	155	#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
	156	#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
	157	#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6
	158	#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7
	159	#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
	160	#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
	161	#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1
	162	#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048
	163	#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3
	164	#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
	165	#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
	166	#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
	167	#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
	168	#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
	169	#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
	170	#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
	171	#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
	172	#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
	173	#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0
	174	#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
	175	#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
	176	#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
	177	#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
	178	#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
	179	#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
	180	#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
	181	#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
	182	#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
	183	#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
	184	#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1
	185	#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
	186	#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4
	187	#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8
	188	#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10
	189	#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B
	190	#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1
	191	#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2
	192	#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4
	193	#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8
	194	#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D
	195	#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E
	196	#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F
	197	#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0
	198	#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF
	199	#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8
	200	#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00
	201	#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050
	202	#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800
	203	#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D
	204	#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0
	205	#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1
	206	#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3
	207	#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4
	208	#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8
	209	#define QAM_COMM_EXEC__A 0x1400000
	210	#define QAM_COMM_EXEC_STOP 0x0
	211	#define QAM_COMM_EXEC_ACTIVE 0x1
	212	#define QAM_TOP_ANNEX_A 0x0
	213	#define QAM_TOP_ANNEX_C 0x2
	214	#define QAM_SL_ERR_POWER__A 0x1430017
	215	#define QAM_DQ_QUAL_FUN0__A 0x1440018
	216	#define QAM_DQ_QUAL_FUN1__A 0x1440019
	217	#define QAM_DQ_QUAL_FUN2__A 0x144001A
	218	#define QAM_DQ_QUAL_FUN3__A 0x144001B
	219	#define QAM_DQ_QUAL_FUN4__A 0x144001C
	220	#define QAM_DQ_QUAL_FUN5__A 0x144001D
	221	#define QAM_LC_MODE__A 0x1450010
	222	#define QAM_LC_QUAL_TAB0__A 0x1450018
	223	#define QAM_LC_QUAL_TAB1__A 0x1450019
	224	#define QAM_LC_QUAL_TAB2__A 0x145001A
	225	#define QAM_LC_QUAL_TAB3__A 0x145001B
	226	#define QAM_LC_QUAL_TAB4__A 0x145001C
	227	#define QAM_LC_QUAL_TAB5__A 0x145001D
	228	#define QAM_LC_QUAL_TAB6__A 0x145001E
	229	#define QAM_LC_QUAL_TAB8__A 0x145001F
	230	#define QAM_LC_QUAL_TAB9__A 0x1450020
	231	#define QAM_LC_QUAL_TAB10__A 0x1450021
	232	#define QAM_LC_QUAL_TAB12__A 0x1450022
	233	#define QAM_LC_QUAL_TAB15__A 0x1450023
	234	#define QAM_LC_QUAL_TAB16__A 0x1450024
	235	#define QAM_LC_QUAL_TAB20__A 0x1450025
	236	#define QAM_LC_QUAL_TAB25__A 0x1450026
	237	#define QAM_LC_LPF_FACTORP__A 0x1450028
	238	#define QAM_LC_LPF_FACTORI__A 0x1450029
	239	#define QAM_LC_RATE_LIMIT__A 0x145002A
	240	#define QAM_LC_SYMBOL_FREQ__A 0x145002B
	241	#define QAM_SY_TIMEOUT__A 0x1470011
	242	#define QAM_SY_TIMEOUT__PRE 0x3A98
	243	#define QAM_SY_SYNC_LWM__A 0x1470012
	244	#define QAM_SY_SYNC_AWM__A 0x1470013
	245	#define QAM_SY_SYNC_HWM__A 0x1470014
	246	#define QAM_SY_SP_INV__A 0x1470017
	247	#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0
	248	#define SCU_COMM_EXEC__A 0x800000
	249	#define SCU_COMM_EXEC_STOP 0x0
	250	#define SCU_COMM_EXEC_ACTIVE 0x1
	251	#define SCU_COMM_EXEC_HOLD 0x2
	252	#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF
	253	#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4
	254	#define SCU_RAM_GPIO__A 0x831EC7
	255	#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0
	256	#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8
	257	#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB
	258	#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05
	259	#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15
	260	#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17
	261	#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18
	262	#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19
	263	#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A
	264	#define SCU_RAM_AGC_RF_MAX__A 0x831F1B
	265	#define SCU_RAM_AGC_CONFIG__A 0x831F24
	266	#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1
	267	#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2
	268	#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100
	269	#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200
	270	#define SCU_RAM_AGC_KI__A 0x831F25
	271	#define SCU_RAM_AGC_KI_RF__B 4
	272	#define SCU_RAM_AGC_KI_RF__M 0xF0
	273	#define SCU_RAM_AGC_KI_IF__B 8
	274	#define SCU_RAM_AGC_KI_IF__M 0xF00
	275	#define SCU_RAM_AGC_KI_RED__A 0x831F26
	276	#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2
	277	#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC
	278	#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4
	279	#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30
	280	#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27
	281	#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28
	282	#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29
	283	#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A
	284	#define SCU_RAM_AGC_KI_MIN__A 0x831F2B
	285	#define SCU_RAM_AGC_KI_MAX__A 0x831F2C
	286	#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D
	287	#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E
	288	#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F
	289	#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30
	290	#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31
	291	#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32
	292	#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33
	293	#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34
	294	#define SCU_RAM_AGC_SNS_SUM__A 0x831F35
	295	#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36
	296	#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37
	297	#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38
	298	#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39
	299	#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A
	300	#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B
	301	#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D
	302	#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E
	303	#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F
	304	#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40
	305	#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41
	306	#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42
	307	#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43
	308	#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44
	309	#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45
	310	#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46
	311	#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47
	312	#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84
	313	#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85
	314	#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86
	315	#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87
	316	#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88
	317	#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89
	318	#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A
	319	#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E
	320	#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F
	321	#define SCU_RAM_QAM_FSM_PTH__A 0x831F90
	322	#define SCU_RAM_QAM_FSM_MTH__A 0x831F91
	323	#define SCU_RAM_QAM_FSM_CTH__A 0x831F92
	324	#define SCU_RAM_QAM_FSM_QTH__A 0x831F93
	325	#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94
	326	#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95
	327	#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96
	328	#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97
	329	#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99
	330	#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A
	331	#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B
	332	#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C
	333	#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D
	334	#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E
	335	#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F
	336	#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0
	337	#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1
	338	#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2
	339	#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3
	340	#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4
	341	#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5
	342	#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6
	343	#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7
	344	#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8
	345	#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9
	346	#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA
	347	#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB
	348	#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC
	349	#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD
	350	#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE
	351	#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF
	352	#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0
	353	#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1
	354	#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2
	355	#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000
	356	#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000
	357	#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000
	358	#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA
	359	#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB
	360	#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC
	361	#define SCU_RAM_PARAM_15__A 0x831FED
	362	#define SCU_RAM_PARAM_0__A 0x831FFC
	363	#define SCU_RAM_COMMAND__A 0x831FFD
	364	#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1
	365	#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2
	366	#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3
	367	#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4
	368	#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5
	369	#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9
	370	#define SCU_RAM_COMMAND_STANDARD_QAM 0x200
	371	#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400
	372	#define SIO_TOP_COMM_KEY__A 0x41000F
	373	#define SIO_TOP_COMM_KEY_KEY 0xFABA
	374	#define SIO_TOP_JTAGID_LO__A 0x410012
	375	#define SIO_HI_RA_RAM_RES__A 0x420031
	376	#define SIO_HI_RA_RAM_CMD__A 0x420032
	377	#define SIO_HI_RA_RAM_CMD_RESET 0x2
	378	#define SIO_HI_RA_RAM_CMD_CONFIG 0x3
	379	#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7
	380	#define SIO_HI_RA_RAM_PAR_1__A 0x420033
	381	#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945
	382	#define SIO_HI_RA_RAM_PAR_2__A 0x420034
	383	#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F
	384	#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0
	385	#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4
	386	#define SIO_HI_RA_RAM_PAR_3__A 0x420035
	387	#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F
	388	#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7
	389	#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0
	390	#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8
	391	#define SIO_HI_RA_RAM_PAR_4__A 0x420036
	392	#define SIO_HI_RA_RAM_PAR_5__A 0x420037
	393	#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1
	394	#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8
	395	#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8
	396	#define SIO_HI_RA_RAM_PAR_6__A 0x420038
	397	#define SIO_CC_PLL_LOCK__A 0x450012
	398	#define SIO_CC_PWD_MODE__A 0x450015
	399	#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0
	400	#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1
	401	#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2
	402	#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3
	403	#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4
	404	#define SIO_CC_SOFT_RST__A 0x450016
	405	#define SIO_CC_SOFT_RST_OFDM__M 0x1
	406	#define SIO_CC_SOFT_RST_SYS__M 0x2
	407	#define SIO_CC_SOFT_RST_OSC__M 0x4
	408	#define SIO_CC_UPDATE__A 0x450017
	409	#define SIO_CC_UPDATE_KEY 0xFABA
	410	#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010
	411	#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0
	412	#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1
	413	#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012
	414	#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0
	415	#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1
	416	#define SIO_BL_COMM_EXEC__A 0x480000
	417	#define SIO_BL_COMM_EXEC_ACTIVE 0x1
	418	#define SIO_BL_STATUS__A 0x480010
	419	#define SIO_BL_MODE__A 0x480011
	420	#define SIO_BL_MODE_DIRECT 0x0
	421	#define SIO_BL_MODE_CHAIN 0x1
	422	#define SIO_BL_ENABLE__A 0x480012
	423	#define SIO_BL_ENABLE_ON 0x1
	424	#define SIO_BL_TGT_HDR__A 0x480014
	425	#define SIO_BL_TGT_ADDR__A 0x480015
	426	#define SIO_BL_SRC_ADDR__A 0x480016
	427	#define SIO_BL_SRC_LEN__A 0x480017
	428	#define SIO_BL_CHAIN_ADDR__A 0x480018
	429	#define SIO_BL_CHAIN_LEN__A 0x480019
	430	#define SIO_PDR_MON_CFG__A 0x7F0010
	431	#define SIO_PDR_UIO_IN_HI__A 0x7F0015
	432	#define SIO_PDR_UIO_OUT_LO__A 0x7F0016
	433	#define SIO_PDR_OHW_CFG__A 0x7F001F
	434	#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3
	435	#define SIO_PDR_GPIO_CFG__A 0x7F0021
	436	#define SIO_PDR_MSTRT_CFG__A 0x7F0025
	437	#define SIO_PDR_MERR_CFG__A 0x7F0026
	438	#define SIO_PDR_MCLK_CFG__A 0x7F0028
	439	#define SIO_PDR_MCLK_CFG_DRIVE__B 3
	440	#define SIO_PDR_MVAL_CFG__A 0x7F0029
	441	#define SIO_PDR_MD0_CFG__A 0x7F002A
	442	#define SIO_PDR_MD0_CFG_DRIVE__B 3
	443	#define SIO_PDR_MD1_CFG__A 0x7F002B
	444	#define SIO_PDR_MD2_CFG__A 0x7F002C
	445	#define SIO_PDR_MD3_CFG__A 0x7F002D
	446	#define SIO_PDR_MD4_CFG__A 0x7F002F
	447	#define SIO_PDR_MD5_CFG__A 0x7F0030
	448	#define SIO_PDR_MD6_CFG__A 0x7F0031
	449	#define SIO_PDR_MD7_CFG__A 0x7F0032
	450	#define SIO_PDR_SMA_RX_CFG__A 0x7F0037
	451	#define SIO_PDR_SMA_TX_CFG__A 0x7F0038