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-rw-r--r--drivers/media/common/tuners/Kconfig9
-rw-r--r--drivers/media/common/tuners/Makefile1
-rw-r--r--drivers/media/common/tuners/max2165.c39
-rw-r--r--drivers/media/common/tuners/mc44s803.c10
-rw-r--r--drivers/media/common/tuners/mt2060.c13
-rw-r--r--drivers/media/common/tuners/mt2060_priv.h1
-rw-r--r--drivers/media/common/tuners/mt2063.c2307
-rw-r--r--drivers/media/common/tuners/mt2063.h36
-rw-r--r--drivers/media/common/tuners/mt2131.c20
-rw-r--r--drivers/media/common/tuners/mt2131_priv.h1
-rw-r--r--drivers/media/common/tuners/mt2266.c25
-rw-r--r--drivers/media/common/tuners/mxl5005s.c69
-rw-r--r--drivers/media/common/tuners/mxl5007t.c98
-rw-r--r--drivers/media/common/tuners/qt1010.c21
-rw-r--r--drivers/media/common/tuners/qt1010_priv.h1
-rw-r--r--drivers/media/common/tuners/tda18212.c72
-rw-r--r--drivers/media/common/tuners/tda18212.h4
-rw-r--r--drivers/media/common/tuners/tda18218.c34
-rw-r--r--drivers/media/common/tuners/tda18218_priv.h2
-rw-r--r--drivers/media/common/tuners/tda18271-fe.c83
-rw-r--r--drivers/media/common/tuners/tda18271-maps.c4
-rw-r--r--drivers/media/common/tuners/tda18271-priv.h2
-rw-r--r--drivers/media/common/tuners/tda18271.h1
-rw-r--r--drivers/media/common/tuners/tda827x.c52
-rw-r--r--drivers/media/common/tuners/tuner-simple.c68
-rw-r--r--drivers/media/common/tuners/tuner-xc2028.c116
-rw-r--r--drivers/media/common/tuners/xc4000.c105
-rw-r--r--drivers/media/common/tuners/xc5000.c147
28 files changed, 2874 insertions, 467 deletions
diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig
index 996302ae210e..4a6d5cef3964 100644
--- a/drivers/media/common/tuners/Kconfig
+++ b/drivers/media/common/tuners/Kconfig
@@ -26,7 +26,7 @@ config MEDIA_TUNER
26 select MEDIA_TUNER_XC4000 if !MEDIA_TUNER_CUSTOMISE 26 select MEDIA_TUNER_XC4000 if !MEDIA_TUNER_CUSTOMISE
27 select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMISE 27 select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMISE
28 select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMISE 28 select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMISE
29 select MEDIA_TUNER_TEA5761 if !MEDIA_TUNER_CUSTOMISE 29 select MEDIA_TUNER_TEA5761 if !MEDIA_TUNER_CUSTOMISE && EXPERIMENTAL
30 select MEDIA_TUNER_TEA5767 if !MEDIA_TUNER_CUSTOMISE 30 select MEDIA_TUNER_TEA5767 if !MEDIA_TUNER_CUSTOMISE
31 select MEDIA_TUNER_SIMPLE if !MEDIA_TUNER_CUSTOMISE 31 select MEDIA_TUNER_SIMPLE if !MEDIA_TUNER_CUSTOMISE
32 select MEDIA_TUNER_TDA9887 if !MEDIA_TUNER_CUSTOMISE 32 select MEDIA_TUNER_TDA9887 if !MEDIA_TUNER_CUSTOMISE
@@ -116,6 +116,13 @@ config MEDIA_TUNER_MT2060
116 help 116 help
117 A driver for the silicon IF tuner MT2060 from Microtune. 117 A driver for the silicon IF tuner MT2060 from Microtune.
118 118
119config MEDIA_TUNER_MT2063
120 tristate "Microtune MT2063 silicon IF tuner"
121 depends on VIDEO_MEDIA && I2C
122 default m if MEDIA_TUNER_CUSTOMISE
123 help
124 A driver for the silicon IF tuner MT2063 from Microtune.
125
119config MEDIA_TUNER_MT2266 126config MEDIA_TUNER_MT2266
120 tristate "Microtune MT2266 silicon tuner" 127 tristate "Microtune MT2266 silicon tuner"
121 depends on VIDEO_MEDIA && I2C 128 depends on VIDEO_MEDIA && I2C
diff --git a/drivers/media/common/tuners/Makefile b/drivers/media/common/tuners/Makefile
index 196c12a55f9a..8295854ab94b 100644
--- a/drivers/media/common/tuners/Makefile
+++ b/drivers/media/common/tuners/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_MEDIA_TUNER_TDA18271) += tda18271.o
18obj-$(CONFIG_MEDIA_TUNER_XC5000) += xc5000.o 18obj-$(CONFIG_MEDIA_TUNER_XC5000) += xc5000.o
19obj-$(CONFIG_MEDIA_TUNER_XC4000) += xc4000.o 19obj-$(CONFIG_MEDIA_TUNER_XC4000) += xc4000.o
20obj-$(CONFIG_MEDIA_TUNER_MT2060) += mt2060.o 20obj-$(CONFIG_MEDIA_TUNER_MT2060) += mt2060.o
21obj-$(CONFIG_MEDIA_TUNER_MT2063) += mt2063.o
21obj-$(CONFIG_MEDIA_TUNER_MT2266) += mt2266.o 22obj-$(CONFIG_MEDIA_TUNER_MT2266) += mt2266.o
22obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o 23obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o
23obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o 24obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o
diff --git a/drivers/media/common/tuners/max2165.c b/drivers/media/common/tuners/max2165.c
index 9883617b7862..cb2c98fbad1b 100644
--- a/drivers/media/common/tuners/max2165.c
+++ b/drivers/media/common/tuners/max2165.c
@@ -151,7 +151,7 @@ static int max2165_set_bandwidth(struct max2165_priv *priv, u32 bw)
151{ 151{
152 u8 val; 152 u8 val;
153 153
154 if (bw == BANDWIDTH_8_MHZ) 154 if (bw == 8000000)
155 val = priv->bb_filter_8mhz_cfg; 155 val = priv->bb_filter_8mhz_cfg;
156 else 156 else
157 val = priv->bb_filter_7mhz_cfg; 157 val = priv->bb_filter_7mhz_cfg;
@@ -257,39 +257,28 @@ static void max2165_debug_status(struct max2165_priv *priv)
257 dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc); 257 dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc);
258} 258}
259 259
260static int max2165_set_params(struct dvb_frontend *fe, 260static int max2165_set_params(struct dvb_frontend *fe)
261 struct dvb_frontend_parameters *params)
262{ 261{
263 struct max2165_priv *priv = fe->tuner_priv; 262 struct max2165_priv *priv = fe->tuner_priv;
263 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
264 int ret; 264 int ret;
265 265
266 dprintk("%s() frequency=%d (Hz)\n", __func__, params->frequency); 266 switch (c->bandwidth_hz) {
267 if (fe->ops.info.type == FE_ATSC) { 267 case 7000000:
268 return -EINVAL; 268 case 8000000:
269 } else if (fe->ops.info.type == FE_OFDM) { 269 priv->frequency = c->frequency;
270 dprintk("%s() OFDM\n", __func__); 270 break;
271 switch (params->u.ofdm.bandwidth) { 271 default:
272 case BANDWIDTH_6_MHZ: 272 printk(KERN_INFO "MAX2165: bandwidth %d Hz not supported.\n",
273 return -EINVAL; 273 c->bandwidth_hz);
274 case BANDWIDTH_7_MHZ:
275 case BANDWIDTH_8_MHZ:
276 priv->frequency = params->frequency;
277 priv->bandwidth = params->u.ofdm.bandwidth;
278 break;
279 default:
280 printk(KERN_ERR "MAX2165 bandwidth not set!\n");
281 return -EINVAL;
282 }
283 } else {
284 printk(KERN_ERR "MAX2165 modulation type not supported!\n");
285 return -EINVAL; 274 return -EINVAL;
286 } 275 }
287 276
288 dprintk("%s() frequency=%d\n", __func__, priv->frequency); 277 dprintk("%s() frequency=%d\n", __func__, c->frequency);
289 278
290 if (fe->ops.i2c_gate_ctrl) 279 if (fe->ops.i2c_gate_ctrl)
291 fe->ops.i2c_gate_ctrl(fe, 1); 280 fe->ops.i2c_gate_ctrl(fe, 1);
292 max2165_set_bandwidth(priv, priv->bandwidth); 281 max2165_set_bandwidth(priv, c->bandwidth_hz);
293 ret = max2165_set_rf(priv, priv->frequency); 282 ret = max2165_set_rf(priv, priv->frequency);
294 mdelay(50); 283 mdelay(50);
295 max2165_debug_status(priv); 284 max2165_debug_status(priv);
@@ -370,7 +359,7 @@ static int max2165_init(struct dvb_frontend *fe)
370 359
371 max2165_read_rom_table(priv); 360 max2165_read_rom_table(priv);
372 361
373 max2165_set_bandwidth(priv, BANDWIDTH_8_MHZ); 362 max2165_set_bandwidth(priv, 8000000);
374 363
375 if (fe->ops.i2c_gate_ctrl) 364 if (fe->ops.i2c_gate_ctrl)
376 fe->ops.i2c_gate_ctrl(fe, 0); 365 fe->ops.i2c_gate_ctrl(fe, 0);
diff --git a/drivers/media/common/tuners/mc44s803.c b/drivers/media/common/tuners/mc44s803.c
index fe5c4b8d83ee..5ddce7e326f7 100644
--- a/drivers/media/common/tuners/mc44s803.c
+++ b/drivers/media/common/tuners/mc44s803.c
@@ -214,22 +214,22 @@ exit:
214 return err; 214 return err;
215} 215}
216 216
217static int mc44s803_set_params(struct dvb_frontend *fe, 217static int mc44s803_set_params(struct dvb_frontend *fe)
218 struct dvb_frontend_parameters *params)
219{ 218{
220 struct mc44s803_priv *priv = fe->tuner_priv; 219 struct mc44s803_priv *priv = fe->tuner_priv;
220 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
221 u32 r1, r2, n1, n2, lo1, lo2, freq, val; 221 u32 r1, r2, n1, n2, lo1, lo2, freq, val;
222 int err; 222 int err;
223 223
224 priv->frequency = params->frequency; 224 priv->frequency = c->frequency;
225 225
226 r1 = MC44S803_OSC / 1000000; 226 r1 = MC44S803_OSC / 1000000;
227 r2 = MC44S803_OSC / 100000; 227 r2 = MC44S803_OSC / 100000;
228 228
229 n1 = (params->frequency + MC44S803_IF1 + 500000) / 1000000; 229 n1 = (c->frequency + MC44S803_IF1 + 500000) / 1000000;
230 freq = MC44S803_OSC / r1 * n1; 230 freq = MC44S803_OSC / r1 * n1;
231 lo1 = ((60 * n1) + (r1 / 2)) / r1; 231 lo1 = ((60 * n1) + (r1 / 2)) / r1;
232 freq = freq - params->frequency; 232 freq = freq - c->frequency;
233 233
234 n2 = (freq - MC44S803_IF2 + 50000) / 100000; 234 n2 = (freq - MC44S803_IF2 + 50000) / 100000;
235 lo2 = ((60 * n2) + (r2 / 2)) / r2; 235 lo2 = ((60 * n2) + (r2 / 2)) / r2;
diff --git a/drivers/media/common/tuners/mt2060.c b/drivers/media/common/tuners/mt2060.c
index 2d0e7689c6a2..13381de58a84 100644
--- a/drivers/media/common/tuners/mt2060.c
+++ b/drivers/media/common/tuners/mt2060.c
@@ -153,8 +153,9 @@ static int mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2)
153#define IF2 36150 // IF2 frequency = 36.150 MHz 153#define IF2 36150 // IF2 frequency = 36.150 MHz
154#define FREF 16000 // Quartz oscillator 16 MHz 154#define FREF 16000 // Quartz oscillator 16 MHz
155 155
156static int mt2060_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) 156static int mt2060_set_params(struct dvb_frontend *fe)
157{ 157{
158 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
158 struct mt2060_priv *priv; 159 struct mt2060_priv *priv;
159 int ret=0; 160 int ret=0;
160 int i=0; 161 int i=0;
@@ -176,8 +177,7 @@ static int mt2060_set_params(struct dvb_frontend *fe, struct dvb_frontend_parame
176 177
177 mt2060_writeregs(priv,b,2); 178 mt2060_writeregs(priv,b,2);
178 179
179 freq = params->frequency / 1000; // Hz -> kHz 180 freq = c->frequency / 1000; /* Hz -> kHz */
180 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0;
181 181
182 f_lo1 = freq + if1 * 1000; 182 f_lo1 = freq + if1 * 1000;
183 f_lo1 = (f_lo1 / 250) * 250; 183 f_lo1 = (f_lo1 / 250) * 250;
@@ -293,10 +293,9 @@ static int mt2060_get_frequency(struct dvb_frontend *fe, u32 *frequency)
293 return 0; 293 return 0;
294} 294}
295 295
296static int mt2060_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 296static int mt2060_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
297{ 297{
298 struct mt2060_priv *priv = fe->tuner_priv; 298 *frequency = IF2 * 1000;
299 *bandwidth = priv->bandwidth;
300 return 0; 299 return 0;
301} 300}
302 301
@@ -356,7 +355,7 @@ static const struct dvb_tuner_ops mt2060_tuner_ops = {
356 355
357 .set_params = mt2060_set_params, 356 .set_params = mt2060_set_params,
358 .get_frequency = mt2060_get_frequency, 357 .get_frequency = mt2060_get_frequency,
359 .get_bandwidth = mt2060_get_bandwidth 358 .get_if_frequency = mt2060_get_if_frequency,
360}; 359};
361 360
362/* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */ 361/* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */
diff --git a/drivers/media/common/tuners/mt2060_priv.h b/drivers/media/common/tuners/mt2060_priv.h
index 5eaccdefd0b0..2b60de6c707d 100644
--- a/drivers/media/common/tuners/mt2060_priv.h
+++ b/drivers/media/common/tuners/mt2060_priv.h
@@ -97,7 +97,6 @@ struct mt2060_priv {
97 struct i2c_adapter *i2c; 97 struct i2c_adapter *i2c;
98 98
99 u32 frequency; 99 u32 frequency;
100 u32 bandwidth;
101 u16 if1_freq; 100 u16 if1_freq;
102 u8 fmfreq; 101 u8 fmfreq;
103}; 102};
diff --git a/drivers/media/common/tuners/mt2063.c b/drivers/media/common/tuners/mt2063.c
new file mode 100644
index 000000000000..c89af3cd5eba
--- /dev/null
+++ b/drivers/media/common/tuners/mt2063.c
@@ -0,0 +1,2307 @@
1/*
2 * Driver for mt2063 Micronas tuner
3 *
4 * Copyright (c) 2011 Mauro Carvalho Chehab <mchehab@redhat.com>
5 *
6 * This driver came from a driver originally written by:
7 * Henry Wang <Henry.wang@AzureWave.com>
8 * Made publicly available by Terratec, at:
9 * http://linux.terratec.de/files/TERRATEC_H7/20110323_TERRATEC_H7_Linux.tar.gz
10 * The original driver's license is GPL, as declared with MODULE_LICENSE()
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation under version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/videodev2.h>
27
28#include "mt2063.h"
29
30static unsigned int debug;
31module_param(debug, int, 0644);
32MODULE_PARM_DESC(debug, "Set Verbosity level");
33
34#define dprintk(level, fmt, arg...) do { \
35if (debug >= level) \
36 printk(KERN_DEBUG "mt2063 %s: " fmt, __func__, ## arg); \
37} while (0)
38
39
40/* positive error codes used internally */
41
42/* Info: Unavoidable LO-related spur may be present in the output */
43#define MT2063_SPUR_PRESENT_ERR (0x00800000)
44
45/* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */
46#define MT2063_SPUR_CNT_MASK (0x001f0000)
47#define MT2063_SPUR_SHIFT (16)
48
49/* Info: Upconverter frequency is out of range (may be reason for MT_UPC_UNLOCK) */
50#define MT2063_UPC_RANGE (0x04000000)
51
52/* Info: Downconverter frequency is out of range (may be reason for MT_DPC_UNLOCK) */
53#define MT2063_DNC_RANGE (0x08000000)
54
55/*
56 * Constant defining the version of the following structure
57 * and therefore the API for this code.
58 *
59 * When compiling the tuner driver, the preprocessor will
60 * check against this version number to make sure that
61 * it matches the version that the tuner driver knows about.
62 */
63
64/* DECT Frequency Avoidance */
65#define MT2063_DECT_AVOID_US_FREQS 0x00000001
66
67#define MT2063_DECT_AVOID_EURO_FREQS 0x00000002
68
69#define MT2063_EXCLUDE_US_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_US_FREQS) != 0)
70
71#define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
72
73enum MT2063_DECT_Avoid_Type {
74 MT2063_NO_DECT_AVOIDANCE = 0, /* Do not create DECT exclusion zones. */
75 MT2063_AVOID_US_DECT = MT2063_DECT_AVOID_US_FREQS, /* Avoid US DECT frequencies. */
76 MT2063_AVOID_EURO_DECT = MT2063_DECT_AVOID_EURO_FREQS, /* Avoid European DECT frequencies. */
77 MT2063_AVOID_BOTH /* Avoid both regions. Not typically used. */
78};
79
80#define MT2063_MAX_ZONES 48
81
82struct MT2063_ExclZone_t {
83 u32 min_;
84 u32 max_;
85 struct MT2063_ExclZone_t *next_;
86};
87
88/*
89 * Structure of data needed for Spur Avoidance
90 */
91struct MT2063_AvoidSpursData_t {
92 u32 f_ref;
93 u32 f_in;
94 u32 f_LO1;
95 u32 f_if1_Center;
96 u32 f_if1_Request;
97 u32 f_if1_bw;
98 u32 f_LO2;
99 u32 f_out;
100 u32 f_out_bw;
101 u32 f_LO1_Step;
102 u32 f_LO2_Step;
103 u32 f_LO1_FracN_Avoid;
104 u32 f_LO2_FracN_Avoid;
105 u32 f_zif_bw;
106 u32 f_min_LO_Separation;
107 u32 maxH1;
108 u32 maxH2;
109 enum MT2063_DECT_Avoid_Type avoidDECT;
110 u32 bSpurPresent;
111 u32 bSpurAvoided;
112 u32 nSpursFound;
113 u32 nZones;
114 struct MT2063_ExclZone_t *freeZones;
115 struct MT2063_ExclZone_t *usedZones;
116 struct MT2063_ExclZone_t MT2063_ExclZones[MT2063_MAX_ZONES];
117};
118
119/*
120 * Parameter for function MT2063_SetPowerMask that specifies the power down
121 * of various sections of the MT2063.
122 */
123enum MT2063_Mask_Bits {
124 MT2063_REG_SD = 0x0040, /* Shutdown regulator */
125 MT2063_SRO_SD = 0x0020, /* Shutdown SRO */
126 MT2063_AFC_SD = 0x0010, /* Shutdown AFC A/D */
127 MT2063_PD_SD = 0x0002, /* Enable power detector shutdown */
128 MT2063_PDADC_SD = 0x0001, /* Enable power detector A/D shutdown */
129 MT2063_VCO_SD = 0x8000, /* Enable VCO shutdown */
130 MT2063_LTX_SD = 0x4000, /* Enable LTX shutdown */
131 MT2063_LT1_SD = 0x2000, /* Enable LT1 shutdown */
132 MT2063_LNA_SD = 0x1000, /* Enable LNA shutdown */
133 MT2063_UPC_SD = 0x0800, /* Enable upconverter shutdown */
134 MT2063_DNC_SD = 0x0400, /* Enable downconverter shutdown */
135 MT2063_VGA_SD = 0x0200, /* Enable VGA shutdown */
136 MT2063_AMP_SD = 0x0100, /* Enable AMP shutdown */
137 MT2063_ALL_SD = 0xFF73, /* All shutdown bits for this tuner */
138 MT2063_NONE_SD = 0x0000 /* No shutdown bits */
139};
140
141/*
142 * Possible values for MT2063_DNC_OUTPUT
143 */
144enum MT2063_DNC_Output_Enable {
145 MT2063_DNC_NONE = 0,
146 MT2063_DNC_1,
147 MT2063_DNC_2,
148 MT2063_DNC_BOTH
149};
150
151/*
152 * Two-wire serial bus subaddresses of the tuner registers.
153 * Also known as the tuner's register addresses.
154 */
155enum MT2063_Register_Offsets {
156 MT2063_REG_PART_REV = 0, /* 0x00: Part/Rev Code */
157 MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
158 MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
159 MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
160 MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
161 MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
162 MT2063_REG_RSVD_06, /* 0x06: Reserved */
163 MT2063_REG_LO_STATUS, /* 0x07: LO Status */
164 MT2063_REG_FIFFC, /* 0x08: FIFF Center */
165 MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
166 MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
167 MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
168 MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
169 MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
170 MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
171 MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
172 MT2063_REG_RSVD_10, /* 0x10: Reserved */
173 MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
174 MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
175 MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
176 MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
177 MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
178 MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
179 MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
180 MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
181 MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
182 MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
183 MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
184 MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
185 MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
186 MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
187 MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
188 MT2063_REG_RSVD_20, /* 0x20: Reserved */
189 MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
190 MT2063_REG_RSVD_22, /* 0x22: Reserved */
191 MT2063_REG_RSVD_23, /* 0x23: Reserved */
192 MT2063_REG_RSVD_24, /* 0x24: Reserved */
193 MT2063_REG_RSVD_25, /* 0x25: Reserved */
194 MT2063_REG_RSVD_26, /* 0x26: Reserved */
195 MT2063_REG_RSVD_27, /* 0x27: Reserved */
196 MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
197 MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
198 MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
199 MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
200 MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
201 MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
202 MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
203 MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
204 MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
205 MT2063_REG_RSVD_31, /* 0x31: Reserved */
206 MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
207 MT2063_REG_RSVD_33, /* 0x33: Reserved */
208 MT2063_REG_RSVD_34, /* 0x34: Reserved */
209 MT2063_REG_RSVD_35, /* 0x35: Reserved */
210 MT2063_REG_RSVD_36, /* 0x36: Reserved */
211 MT2063_REG_RSVD_37, /* 0x37: Reserved */
212 MT2063_REG_RSVD_38, /* 0x38: Reserved */
213 MT2063_REG_RSVD_39, /* 0x39: Reserved */
214 MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
215 MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
216 MT2063_REG_RSVD_3C, /* 0x3C: Reserved */
217 MT2063_REG_END_REGS
218};
219
220struct mt2063_state {
221 struct i2c_adapter *i2c;
222
223 bool init;
224
225 const struct mt2063_config *config;
226 struct dvb_tuner_ops ops;
227 struct dvb_frontend *frontend;
228 struct tuner_state status;
229
230 u32 frequency;
231 u32 srate;
232 u32 bandwidth;
233 u32 reference;
234
235 u32 tuner_id;
236 struct MT2063_AvoidSpursData_t AS_Data;
237 u32 f_IF1_actual;
238 u32 rcvr_mode;
239 u32 ctfilt_sw;
240 u32 CTFiltMax[31];
241 u32 num_regs;
242 u8 reg[MT2063_REG_END_REGS];
243};
244
245/*
246 * mt2063_write - Write data into the I2C bus
247 */
248static u32 mt2063_write(struct mt2063_state *state, u8 reg, u8 *data, u32 len)
249{
250 struct dvb_frontend *fe = state->frontend;
251 int ret;
252 u8 buf[60];
253 struct i2c_msg msg = {
254 .addr = state->config->tuner_address,
255 .flags = 0,
256 .buf = buf,
257 .len = len + 1
258 };
259
260 dprintk(2, "\n");
261
262 msg.buf[0] = reg;
263 memcpy(msg.buf + 1, data, len);
264
265 if (fe->ops.i2c_gate_ctrl)
266 fe->ops.i2c_gate_ctrl(fe, 1);
267 ret = i2c_transfer(state->i2c, &msg, 1);
268 if (fe->ops.i2c_gate_ctrl)
269 fe->ops.i2c_gate_ctrl(fe, 0);
270
271 if (ret < 0)
272 printk(KERN_ERR "%s error ret=%d\n", __func__, ret);
273
274 return ret;
275}
276
277/*
278 * mt2063_write - Write register data into the I2C bus, caching the value
279 */
280static u32 mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val)
281{
282 u32 status;
283
284 dprintk(2, "\n");
285
286 if (reg >= MT2063_REG_END_REGS)
287 return -ERANGE;
288
289 status = mt2063_write(state, reg, &val, 1);
290 if (status < 0)
291 return status;
292
293 state->reg[reg] = val;
294
295 return 0;
296}
297
298/*
299 * mt2063_read - Read data from the I2C bus
300 */
301static u32 mt2063_read(struct mt2063_state *state,
302 u8 subAddress, u8 *pData, u32 cnt)
303{
304 u32 status = 0; /* Status to be returned */
305 struct dvb_frontend *fe = state->frontend;
306 u32 i = 0;
307
308 dprintk(2, "addr 0x%02x, cnt %d\n", subAddress, cnt);
309
310 if (fe->ops.i2c_gate_ctrl)
311 fe->ops.i2c_gate_ctrl(fe, 1);
312
313 for (i = 0; i < cnt; i++) {
314 u8 b0[] = { subAddress + i };
315 struct i2c_msg msg[] = {
316 {
317 .addr = state->config->tuner_address,
318 .flags = 0,
319 .buf = b0,
320 .len = 1
321 }, {
322 .addr = state->config->tuner_address,
323 .flags = I2C_M_RD,
324 .buf = pData + i,
325 .len = 1
326 }
327 };
328
329 status = i2c_transfer(state->i2c, msg, 2);
330 dprintk(2, "addr 0x%02x, ret = %d, val = 0x%02x\n",
331 subAddress + i, status, *(pData + i));
332 if (status < 0)
333 break;
334 }
335 if (fe->ops.i2c_gate_ctrl)
336 fe->ops.i2c_gate_ctrl(fe, 0);
337
338 if (status < 0)
339 printk(KERN_ERR "Can't read from address 0x%02x,\n",
340 subAddress + i);
341
342 return status;
343}
344
345/*
346 * FIXME: Is this really needed?
347 */
348static int MT2063_Sleep(struct dvb_frontend *fe)
349{
350 /*
351 * ToDo: Add code here to implement a OS blocking
352 */
353 msleep(10);
354
355 return 0;
356}
357
358/*
359 * Microtune spur avoidance
360 */
361
362/* Implement ceiling, floor functions. */
363#define ceil(n, d) (((n) < 0) ? (-((-(n))/(d))) : (n)/(d) + ((n)%(d) != 0))
364#define floor(n, d) (((n) < 0) ? (-((-(n))/(d))) - ((n)%(d) != 0) : (n)/(d))
365
366struct MT2063_FIFZone_t {
367 s32 min_;
368 s32 max_;
369};
370
371static struct MT2063_ExclZone_t *InsertNode(struct MT2063_AvoidSpursData_t
372 *pAS_Info,
373 struct MT2063_ExclZone_t *pPrevNode)
374{
375 struct MT2063_ExclZone_t *pNode;
376
377 dprintk(2, "\n");
378
379 /* Check for a node in the free list */
380 if (pAS_Info->freeZones != NULL) {
381 /* Use one from the free list */
382 pNode = pAS_Info->freeZones;
383 pAS_Info->freeZones = pNode->next_;
384 } else {
385 /* Grab a node from the array */
386 pNode = &pAS_Info->MT2063_ExclZones[pAS_Info->nZones];
387 }
388
389 if (pPrevNode != NULL) {
390 pNode->next_ = pPrevNode->next_;
391 pPrevNode->next_ = pNode;
392 } else { /* insert at the beginning of the list */
393
394 pNode->next_ = pAS_Info->usedZones;
395 pAS_Info->usedZones = pNode;
396 }
397
398 pAS_Info->nZones++;
399 return pNode;
400}
401
402static struct MT2063_ExclZone_t *RemoveNode(struct MT2063_AvoidSpursData_t
403 *pAS_Info,
404 struct MT2063_ExclZone_t *pPrevNode,
405 struct MT2063_ExclZone_t
406 *pNodeToRemove)
407{
408 struct MT2063_ExclZone_t *pNext = pNodeToRemove->next_;
409
410 dprintk(2, "\n");
411
412 /* Make previous node point to the subsequent node */
413 if (pPrevNode != NULL)
414 pPrevNode->next_ = pNext;
415
416 /* Add pNodeToRemove to the beginning of the freeZones */
417 pNodeToRemove->next_ = pAS_Info->freeZones;
418 pAS_Info->freeZones = pNodeToRemove;
419
420 /* Decrement node count */
421 pAS_Info->nZones--;
422
423 return pNext;
424}
425
426/*
427 * MT_AddExclZone()
428 *
429 * Add (and merge) an exclusion zone into the list.
430 * If the range (f_min, f_max) is totally outside the
431 * 1st IF BW, ignore the entry.
432 * If the range (f_min, f_max) is negative, ignore the entry.
433 */
434static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
435 u32 f_min, u32 f_max)
436{
437 struct MT2063_ExclZone_t *pNode = pAS_Info->usedZones;
438 struct MT2063_ExclZone_t *pPrev = NULL;
439 struct MT2063_ExclZone_t *pNext = NULL;
440
441 dprintk(2, "\n");
442
443 /* Check to see if this overlaps the 1st IF filter */
444 if ((f_max > (pAS_Info->f_if1_Center - (pAS_Info->f_if1_bw / 2)))
445 && (f_min < (pAS_Info->f_if1_Center + (pAS_Info->f_if1_bw / 2)))
446 && (f_min < f_max)) {
447 /*
448 * 1 2 3 4 5 6
449 *
450 * New entry: |---| |--| |--| |-| |---| |--|
451 * or or or or or
452 * Existing: |--| |--| |--| |---| |-| |--|
453 */
454
455 /* Check for our place in the list */
456 while ((pNode != NULL) && (pNode->max_ < f_min)) {
457 pPrev = pNode;
458 pNode = pNode->next_;
459 }
460
461 if ((pNode != NULL) && (pNode->min_ < f_max)) {
462 /* Combine me with pNode */
463 if (f_min < pNode->min_)
464 pNode->min_ = f_min;
465 if (f_max > pNode->max_)
466 pNode->max_ = f_max;
467 } else {
468 pNode = InsertNode(pAS_Info, pPrev);
469 pNode->min_ = f_min;
470 pNode->max_ = f_max;
471 }
472
473 /* Look for merging possibilities */
474 pNext = pNode->next_;
475 while ((pNext != NULL) && (pNext->min_ < pNode->max_)) {
476 if (pNext->max_ > pNode->max_)
477 pNode->max_ = pNext->max_;
478 /* Remove pNext, return ptr to pNext->next */
479 pNext = RemoveNode(pAS_Info, pNode, pNext);
480 }
481 }
482}
483
484/*
485 * Reset all exclusion zones.
486 * Add zones to protect the PLL FracN regions near zero
487 */
488static void MT2063_ResetExclZones(struct MT2063_AvoidSpursData_t *pAS_Info)
489{
490 u32 center;
491
492 dprintk(2, "\n");
493
494 pAS_Info->nZones = 0; /* this clears the used list */
495 pAS_Info->usedZones = NULL; /* reset ptr */
496 pAS_Info->freeZones = NULL; /* reset ptr */
497
498 center =
499 pAS_Info->f_ref *
500 ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 +
501 pAS_Info->f_in) / pAS_Info->f_ref) - pAS_Info->f_in;
502 while (center <
503 pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
504 pAS_Info->f_LO1_FracN_Avoid) {
505 /* Exclude LO1 FracN */
506 MT2063_AddExclZone(pAS_Info,
507 center - pAS_Info->f_LO1_FracN_Avoid,
508 center - 1);
509 MT2063_AddExclZone(pAS_Info, center + 1,
510 center + pAS_Info->f_LO1_FracN_Avoid);
511 center += pAS_Info->f_ref;
512 }
513
514 center =
515 pAS_Info->f_ref *
516 ((pAS_Info->f_if1_Center - pAS_Info->f_if1_bw / 2 -
517 pAS_Info->f_out) / pAS_Info->f_ref) + pAS_Info->f_out;
518 while (center <
519 pAS_Info->f_if1_Center + pAS_Info->f_if1_bw / 2 +
520 pAS_Info->f_LO2_FracN_Avoid) {
521 /* Exclude LO2 FracN */
522 MT2063_AddExclZone(pAS_Info,
523 center - pAS_Info->f_LO2_FracN_Avoid,
524 center - 1);
525 MT2063_AddExclZone(pAS_Info, center + 1,
526 center + pAS_Info->f_LO2_FracN_Avoid);
527 center += pAS_Info->f_ref;
528 }
529
530 if (MT2063_EXCLUDE_US_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
531 /* Exclude LO1 values that conflict with DECT channels */
532 MT2063_AddExclZone(pAS_Info, 1920836000 - pAS_Info->f_in, 1922236000 - pAS_Info->f_in); /* Ctr = 1921.536 */
533 MT2063_AddExclZone(pAS_Info, 1922564000 - pAS_Info->f_in, 1923964000 - pAS_Info->f_in); /* Ctr = 1923.264 */
534 MT2063_AddExclZone(pAS_Info, 1924292000 - pAS_Info->f_in, 1925692000 - pAS_Info->f_in); /* Ctr = 1924.992 */
535 MT2063_AddExclZone(pAS_Info, 1926020000 - pAS_Info->f_in, 1927420000 - pAS_Info->f_in); /* Ctr = 1926.720 */
536 MT2063_AddExclZone(pAS_Info, 1927748000 - pAS_Info->f_in, 1929148000 - pAS_Info->f_in); /* Ctr = 1928.448 */
537 }
538
539 if (MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(pAS_Info->avoidDECT)) {
540 MT2063_AddExclZone(pAS_Info, 1896644000 - pAS_Info->f_in, 1898044000 - pAS_Info->f_in); /* Ctr = 1897.344 */
541 MT2063_AddExclZone(pAS_Info, 1894916000 - pAS_Info->f_in, 1896316000 - pAS_Info->f_in); /* Ctr = 1895.616 */
542 MT2063_AddExclZone(pAS_Info, 1893188000 - pAS_Info->f_in, 1894588000 - pAS_Info->f_in); /* Ctr = 1893.888 */
543 MT2063_AddExclZone(pAS_Info, 1891460000 - pAS_Info->f_in, 1892860000 - pAS_Info->f_in); /* Ctr = 1892.16 */
544 MT2063_AddExclZone(pAS_Info, 1889732000 - pAS_Info->f_in, 1891132000 - pAS_Info->f_in); /* Ctr = 1890.432 */
545 MT2063_AddExclZone(pAS_Info, 1888004000 - pAS_Info->f_in, 1889404000 - pAS_Info->f_in); /* Ctr = 1888.704 */
546 MT2063_AddExclZone(pAS_Info, 1886276000 - pAS_Info->f_in, 1887676000 - pAS_Info->f_in); /* Ctr = 1886.976 */
547 MT2063_AddExclZone(pAS_Info, 1884548000 - pAS_Info->f_in, 1885948000 - pAS_Info->f_in); /* Ctr = 1885.248 */
548 MT2063_AddExclZone(pAS_Info, 1882820000 - pAS_Info->f_in, 1884220000 - pAS_Info->f_in); /* Ctr = 1883.52 */
549 MT2063_AddExclZone(pAS_Info, 1881092000 - pAS_Info->f_in, 1882492000 - pAS_Info->f_in); /* Ctr = 1881.792 */
550 }
551}
552
553/*
554 * MT_ChooseFirstIF - Choose the best available 1st IF
555 * If f_Desired is not excluded, choose that first.
556 * Otherwise, return the value closest to f_Center that is
557 * not excluded
558 */
559static u32 MT2063_ChooseFirstIF(struct MT2063_AvoidSpursData_t *pAS_Info)
560{
561 /*
562 * Update "f_Desired" to be the nearest "combinational-multiple" of
563 * "f_LO1_Step".
564 * The resulting number, F_LO1 must be a multiple of f_LO1_Step.
565 * And F_LO1 is the arithmetic sum of f_in + f_Center.
566 * Neither f_in, nor f_Center must be a multiple of f_LO1_Step.
567 * However, the sum must be.
568 */
569 const u32 f_Desired =
570 pAS_Info->f_LO1_Step *
571 ((pAS_Info->f_if1_Request + pAS_Info->f_in +
572 pAS_Info->f_LO1_Step / 2) / pAS_Info->f_LO1_Step) -
573 pAS_Info->f_in;
574 const u32 f_Step =
575 (pAS_Info->f_LO1_Step >
576 pAS_Info->f_LO2_Step) ? pAS_Info->f_LO1_Step : pAS_Info->
577 f_LO2_Step;
578 u32 f_Center;
579 s32 i;
580 s32 j = 0;
581 u32 bDesiredExcluded = 0;
582 u32 bZeroExcluded = 0;
583 s32 tmpMin, tmpMax;
584 s32 bestDiff;
585 struct MT2063_ExclZone_t *pNode = pAS_Info->usedZones;
586 struct MT2063_FIFZone_t zones[MT2063_MAX_ZONES];
587
588 dprintk(2, "\n");
589
590 if (pAS_Info->nZones == 0)
591 return f_Desired;
592
593 /*
594 * f_Center needs to be an integer multiple of f_Step away
595 * from f_Desired
596 */
597 if (pAS_Info->f_if1_Center > f_Desired)
598 f_Center =
599 f_Desired +
600 f_Step *
601 ((pAS_Info->f_if1_Center - f_Desired +
602 f_Step / 2) / f_Step);
603 else
604 f_Center =
605 f_Desired -
606 f_Step *
607 ((f_Desired - pAS_Info->f_if1_Center +
608 f_Step / 2) / f_Step);
609
610 /*
611 * Take MT_ExclZones, center around f_Center and change the
612 * resolution to f_Step
613 */
614 while (pNode != NULL) {
615 /* floor function */
616 tmpMin =
617 floor((s32) (pNode->min_ - f_Center), (s32) f_Step);
618
619 /* ceil function */
620 tmpMax =
621 ceil((s32) (pNode->max_ - f_Center), (s32) f_Step);
622
623 if ((pNode->min_ < f_Desired) && (pNode->max_ > f_Desired))
624 bDesiredExcluded = 1;
625
626 if ((tmpMin < 0) && (tmpMax > 0))
627 bZeroExcluded = 1;
628
629 /* See if this zone overlaps the previous */
630 if ((j > 0) && (tmpMin < zones[j - 1].max_))
631 zones[j - 1].max_ = tmpMax;
632 else {
633 /* Add new zone */
634 zones[j].min_ = tmpMin;
635 zones[j].max_ = tmpMax;
636 j++;
637 }
638 pNode = pNode->next_;
639 }
640
641 /*
642 * If the desired is okay, return with it
643 */
644 if (bDesiredExcluded == 0)
645 return f_Desired;
646
647 /*
648 * If the desired is excluded and the center is okay, return with it
649 */
650 if (bZeroExcluded == 0)
651 return f_Center;
652
653 /* Find the value closest to 0 (f_Center) */
654 bestDiff = zones[0].min_;
655 for (i = 0; i < j; i++) {
656 if (abs(zones[i].min_) < abs(bestDiff))
657 bestDiff = zones[i].min_;
658 if (abs(zones[i].max_) < abs(bestDiff))
659 bestDiff = zones[i].max_;
660 }
661
662 if (bestDiff < 0)
663 return f_Center - ((u32) (-bestDiff) * f_Step);
664
665 return f_Center + (bestDiff * f_Step);
666}
667
668/**
669 * gcd() - Uses Euclid's algorithm
670 *
671 * @u, @v: Unsigned values whose GCD is desired.
672 *
673 * Returns THE greatest common divisor of u and v, if either value is 0,
674 * the other value is returned as the result.
675 */
676static u32 MT2063_gcd(u32 u, u32 v)
677{
678 u32 r;
679
680 while (v != 0) {
681 r = u % v;
682 u = v;
683 v = r;
684 }
685
686 return u;
687}
688
689/**
690 * IsSpurInBand() - Checks to see if a spur will be present within the IF's
691 * bandwidth. (fIFOut +/- fIFBW, -fIFOut +/- fIFBW)
692 *
693 * ma mb mc md
694 * <--+-+-+-------------------+-------------------+-+-+-->
695 * | ^ 0 ^ |
696 * ^ b=-fIFOut+fIFBW/2 -b=+fIFOut-fIFBW/2 ^
697 * a=-fIFOut-fIFBW/2 -a=+fIFOut+fIFBW/2
698 *
699 * Note that some equations are doubled to prevent round-off
700 * problems when calculating fIFBW/2
701 *
702 * @pAS_Info: Avoid Spurs information block
703 * @fm: If spur, amount f_IF1 has to move negative
704 * @fp: If spur, amount f_IF1 has to move positive
705 *
706 * Returns 1 if an LO spur would be present, otherwise 0.
707 */
708static u32 IsSpurInBand(struct MT2063_AvoidSpursData_t *pAS_Info,
709 u32 *fm, u32 * fp)
710{
711 /*
712 ** Calculate LO frequency settings.
713 */
714 u32 n, n0;
715 const u32 f_LO1 = pAS_Info->f_LO1;
716 const u32 f_LO2 = pAS_Info->f_LO2;
717 const u32 d = pAS_Info->f_out + pAS_Info->f_out_bw / 2;
718 const u32 c = d - pAS_Info->f_out_bw;
719 const u32 f = pAS_Info->f_zif_bw / 2;
720 const u32 f_Scale = (f_LO1 / (UINT_MAX / 2 / pAS_Info->maxH1)) + 1;
721 s32 f_nsLO1, f_nsLO2;
722 s32 f_Spur;
723 u32 ma, mb, mc, md, me, mf;
724 u32 lo_gcd, gd_Scale, gc_Scale, gf_Scale, hgds, hgfs, hgcs;
725
726 dprintk(2, "\n");
727
728 *fm = 0;
729
730 /*
731 ** For each edge (d, c & f), calculate a scale, based on the gcd
732 ** of f_LO1, f_LO2 and the edge value. Use the larger of this
733 ** gcd-based scale factor or f_Scale.
734 */
735 lo_gcd = MT2063_gcd(f_LO1, f_LO2);
736 gd_Scale = max((u32) MT2063_gcd(lo_gcd, d), f_Scale);
737 hgds = gd_Scale / 2;
738 gc_Scale = max((u32) MT2063_gcd(lo_gcd, c), f_Scale);
739 hgcs = gc_Scale / 2;
740 gf_Scale = max((u32) MT2063_gcd(lo_gcd, f), f_Scale);
741 hgfs = gf_Scale / 2;
742
743 n0 = DIV_ROUND_UP(f_LO2 - d, f_LO1 - f_LO2);
744
745 /* Check out all multiples of LO1 from n0 to m_maxLOSpurHarmonic */
746 for (n = n0; n <= pAS_Info->maxH1; ++n) {
747 md = (n * ((f_LO1 + hgds) / gd_Scale) -
748 ((d + hgds) / gd_Scale)) / ((f_LO2 + hgds) / gd_Scale);
749
750 /* If # fLO2 harmonics > m_maxLOSpurHarmonic, then no spurs present */
751 if (md >= pAS_Info->maxH1)
752 break;
753
754 ma = (n * ((f_LO1 + hgds) / gd_Scale) +
755 ((d + hgds) / gd_Scale)) / ((f_LO2 + hgds) / gd_Scale);
756
757 /* If no spurs between +/- (f_out + f_IFBW/2), then try next harmonic */
758 if (md == ma)
759 continue;
760
761 mc = (n * ((f_LO1 + hgcs) / gc_Scale) -
762 ((c + hgcs) / gc_Scale)) / ((f_LO2 + hgcs) / gc_Scale);
763 if (mc != md) {
764 f_nsLO1 = (s32) (n * (f_LO1 / gc_Scale));
765 f_nsLO2 = (s32) (mc * (f_LO2 / gc_Scale));
766 f_Spur =
767 (gc_Scale * (f_nsLO1 - f_nsLO2)) +
768 n * (f_LO1 % gc_Scale) - mc * (f_LO2 % gc_Scale);
769
770 *fp = ((f_Spur - (s32) c) / (mc - n)) + 1;
771 *fm = (((s32) d - f_Spur) / (mc - n)) + 1;
772 return 1;
773 }
774
775 /* Location of Zero-IF-spur to be checked */
776 me = (n * ((f_LO1 + hgfs) / gf_Scale) +
777 ((f + hgfs) / gf_Scale)) / ((f_LO2 + hgfs) / gf_Scale);
778 mf = (n * ((f_LO1 + hgfs) / gf_Scale) -
779 ((f + hgfs) / gf_Scale)) / ((f_LO2 + hgfs) / gf_Scale);
780 if (me != mf) {
781 f_nsLO1 = n * (f_LO1 / gf_Scale);
782 f_nsLO2 = me * (f_LO2 / gf_Scale);
783 f_Spur =
784 (gf_Scale * (f_nsLO1 - f_nsLO2)) +
785 n * (f_LO1 % gf_Scale) - me * (f_LO2 % gf_Scale);
786
787 *fp = ((f_Spur + (s32) f) / (me - n)) + 1;
788 *fm = (((s32) f - f_Spur) / (me - n)) + 1;
789 return 1;
790 }
791
792 mb = (n * ((f_LO1 + hgcs) / gc_Scale) +
793 ((c + hgcs) / gc_Scale)) / ((f_LO2 + hgcs) / gc_Scale);
794 if (ma != mb) {
795 f_nsLO1 = n * (f_LO1 / gc_Scale);
796 f_nsLO2 = ma * (f_LO2 / gc_Scale);
797 f_Spur =
798 (gc_Scale * (f_nsLO1 - f_nsLO2)) +
799 n * (f_LO1 % gc_Scale) - ma * (f_LO2 % gc_Scale);
800
801 *fp = (((s32) d + f_Spur) / (ma - n)) + 1;
802 *fm = (-(f_Spur + (s32) c) / (ma - n)) + 1;
803 return 1;
804 }
805 }
806
807 /* No spurs found */
808 return 0;
809}
810
811/*
812 * MT_AvoidSpurs() - Main entry point to avoid spurs.
813 * Checks for existing spurs in present LO1, LO2 freqs
814 * and if present, chooses spur-free LO1, LO2 combination
815 * that tunes the same input/output frequencies.
816 */
817static u32 MT2063_AvoidSpurs(struct MT2063_AvoidSpursData_t *pAS_Info)
818{
819 u32 status = 0;
820 u32 fm, fp; /* restricted range on LO's */
821 pAS_Info->bSpurAvoided = 0;
822 pAS_Info->nSpursFound = 0;
823
824 dprintk(2, "\n");
825
826 if (pAS_Info->maxH1 == 0)
827 return 0;
828
829 /*
830 * Avoid LO Generated Spurs
831 *
832 * Make sure that have no LO-related spurs within the IF output
833 * bandwidth.
834 *
835 * If there is an LO spur in this band, start at the current IF1 frequency
836 * and work out until we find a spur-free frequency or run up against the
837 * 1st IF SAW band edge. Use temporary copies of fLO1 and fLO2 so that they
838 * will be unchanged if a spur-free setting is not found.
839 */
840 pAS_Info->bSpurPresent = IsSpurInBand(pAS_Info, &fm, &fp);
841 if (pAS_Info->bSpurPresent) {
842 u32 zfIF1 = pAS_Info->f_LO1 - pAS_Info->f_in; /* current attempt at a 1st IF */
843 u32 zfLO1 = pAS_Info->f_LO1; /* current attempt at an LO1 freq */
844 u32 zfLO2 = pAS_Info->f_LO2; /* current attempt at an LO2 freq */
845 u32 delta_IF1;
846 u32 new_IF1;
847
848 /*
849 ** Spur was found, attempt to find a spur-free 1st IF
850 */
851 do {
852 pAS_Info->nSpursFound++;
853
854 /* Raise f_IF1_upper, if needed */
855 MT2063_AddExclZone(pAS_Info, zfIF1 - fm, zfIF1 + fp);
856
857 /* Choose next IF1 that is closest to f_IF1_CENTER */
858 new_IF1 = MT2063_ChooseFirstIF(pAS_Info);
859
860 if (new_IF1 > zfIF1) {
861 pAS_Info->f_LO1 += (new_IF1 - zfIF1);
862 pAS_Info->f_LO2 += (new_IF1 - zfIF1);
863 } else {
864 pAS_Info->f_LO1 -= (zfIF1 - new_IF1);
865 pAS_Info->f_LO2 -= (zfIF1 - new_IF1);
866 }
867 zfIF1 = new_IF1;
868
869 if (zfIF1 > pAS_Info->f_if1_Center)
870 delta_IF1 = zfIF1 - pAS_Info->f_if1_Center;
871 else
872 delta_IF1 = pAS_Info->f_if1_Center - zfIF1;
873
874 pAS_Info->bSpurPresent = IsSpurInBand(pAS_Info, &fm, &fp);
875 /*
876 * Continue while the new 1st IF is still within the 1st IF bandwidth
877 * and there is a spur in the band (again)
878 */
879 } while ((2 * delta_IF1 + pAS_Info->f_out_bw <= pAS_Info->f_if1_bw) && pAS_Info->bSpurPresent);
880
881 /*
882 * Use the LO-spur free values found. If the search went all
883 * the way to the 1st IF band edge and always found spurs, just
884 * leave the original choice. It's as "good" as any other.
885 */
886 if (pAS_Info->bSpurPresent == 1) {
887 status |= MT2063_SPUR_PRESENT_ERR;
888 pAS_Info->f_LO1 = zfLO1;
889 pAS_Info->f_LO2 = zfLO2;
890 } else
891 pAS_Info->bSpurAvoided = 1;
892 }
893
894 status |=
895 ((pAS_Info->
896 nSpursFound << MT2063_SPUR_SHIFT) & MT2063_SPUR_CNT_MASK);
897
898 return status;
899}
900
901/*
902 * Constants used by the tuning algorithm
903 */
904#define MT2063_REF_FREQ (16000000UL) /* Reference oscillator Frequency (in Hz) */
905#define MT2063_IF1_BW (22000000UL) /* The IF1 filter bandwidth (in Hz) */
906#define MT2063_TUNE_STEP_SIZE (50000UL) /* Tune in steps of 50 kHz */
907#define MT2063_SPUR_STEP_HZ (250000UL) /* Step size (in Hz) to move IF1 when avoiding spurs */
908#define MT2063_ZIF_BW (2000000UL) /* Zero-IF spur-free bandwidth (in Hz) */
909#define MT2063_MAX_HARMONICS_1 (15UL) /* Highest intra-tuner LO Spur Harmonic to be avoided */
910#define MT2063_MAX_HARMONICS_2 (5UL) /* Highest inter-tuner LO Spur Harmonic to be avoided */
911#define MT2063_MIN_LO_SEP (1000000UL) /* Minimum inter-tuner LO frequency separation */
912#define MT2063_LO1_FRACN_AVOID (0UL) /* LO1 FracN numerator avoid region (in Hz) */
913#define MT2063_LO2_FRACN_AVOID (199999UL) /* LO2 FracN numerator avoid region (in Hz) */
914#define MT2063_MIN_FIN_FREQ (44000000UL) /* Minimum input frequency (in Hz) */
915#define MT2063_MAX_FIN_FREQ (1100000000UL) /* Maximum input frequency (in Hz) */
916#define MT2063_MIN_FOUT_FREQ (36000000UL) /* Minimum output frequency (in Hz) */
917#define MT2063_MAX_FOUT_FREQ (57000000UL) /* Maximum output frequency (in Hz) */
918#define MT2063_MIN_DNC_FREQ (1293000000UL) /* Minimum LO2 frequency (in Hz) */
919#define MT2063_MAX_DNC_FREQ (1614000000UL) /* Maximum LO2 frequency (in Hz) */
920#define MT2063_MIN_UPC_FREQ (1396000000UL) /* Minimum LO1 frequency (in Hz) */
921#define MT2063_MAX_UPC_FREQ (2750000000UL) /* Maximum LO1 frequency (in Hz) */
922
923/*
924 * Define the supported Part/Rev codes for the MT2063
925 */
926#define MT2063_B0 (0x9B)
927#define MT2063_B1 (0x9C)
928#define MT2063_B2 (0x9D)
929#define MT2063_B3 (0x9E)
930
931/**
932 * mt2063_lockStatus - Checks to see if LO1 and LO2 are locked
933 *
934 * @state: struct mt2063_state pointer
935 *
936 * This function returns 0, if no lock, 1 if locked and a value < 1 if error
937 */
938static unsigned int mt2063_lockStatus(struct mt2063_state *state)
939{
940 const u32 nMaxWait = 100; /* wait a maximum of 100 msec */
941 const u32 nPollRate = 2; /* poll status bits every 2 ms */
942 const u32 nMaxLoops = nMaxWait / nPollRate;
943 const u8 LO1LK = 0x80;
944 u8 LO2LK = 0x08;
945 u32 status;
946 u32 nDelays = 0;
947
948 dprintk(2, "\n");
949
950 /* LO2 Lock bit was in a different place for B0 version */
951 if (state->tuner_id == MT2063_B0)
952 LO2LK = 0x40;
953
954 do {
955 status = mt2063_read(state, MT2063_REG_LO_STATUS,
956 &state->reg[MT2063_REG_LO_STATUS], 1);
957
958 if (status < 0)
959 return status;
960
961 if ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) ==
962 (LO1LK | LO2LK)) {
963 return TUNER_STATUS_LOCKED | TUNER_STATUS_STEREO;
964 }
965 msleep(nPollRate); /* Wait between retries */
966 } while (++nDelays < nMaxLoops);
967
968 /*
969 * Got no lock or partial lock
970 */
971 return 0;
972}
973
974/*
975 * Constants for setting receiver modes.
976 * (6 modes defined at this time, enumerated by mt2063_delivery_sys)
977 * (DNC1GC & DNC2GC are the values, which are used, when the specific
978 * DNC Output is selected, the other is always off)
979 *
980 * enum mt2063_delivery_sys
981 * -------------+----------------------------------------------
982 * Mode 0 : | MT2063_CABLE_QAM
983 * Mode 1 : | MT2063_CABLE_ANALOG
984 * Mode 2 : | MT2063_OFFAIR_COFDM
985 * Mode 3 : | MT2063_OFFAIR_COFDM_SAWLESS
986 * Mode 4 : | MT2063_OFFAIR_ANALOG
987 * Mode 5 : | MT2063_OFFAIR_8VSB
988 * --------------+----------------------------------------------
989 *
990 * |<---------- Mode -------------->|
991 * Reg Field | 0 | 1 | 2 | 3 | 4 | 5 |
992 * ------------+-----+-----+-----+-----+-----+-----+
993 * RFAGCen | OFF | OFF | OFF | OFF | OFF | OFF
994 * LNARin | 0 | 0 | 3 | 3 | 3 | 3
995 * FIFFQen | 1 | 1 | 1 | 1 | 1 | 1
996 * FIFFq | 0 | 0 | 0 | 0 | 0 | 0
997 * DNC1gc | 0 | 0 | 0 | 0 | 0 | 0
998 * DNC2gc | 0 | 0 | 0 | 0 | 0 | 0
999 * GCU Auto | 1 | 1 | 1 | 1 | 1 | 1
1000 * LNA max Atn | 31 | 31 | 31 | 31 | 31 | 31
1001 * LNA Target | 44 | 43 | 43 | 43 | 43 | 43
1002 * ign RF Ovl | 0 | 0 | 0 | 0 | 0 | 0
1003 * RF max Atn | 31 | 31 | 31 | 31 | 31 | 31
1004 * PD1 Target | 36 | 36 | 38 | 38 | 36 | 38
1005 * ign FIF Ovl | 0 | 0 | 0 | 0 | 0 | 0
1006 * FIF max Atn | 5 | 5 | 5 | 5 | 5 | 5
1007 * PD2 Target | 40 | 33 | 42 | 42 | 33 | 42
1008 */
1009
1010enum mt2063_delivery_sys {
1011 MT2063_CABLE_QAM = 0,
1012 MT2063_CABLE_ANALOG,
1013 MT2063_OFFAIR_COFDM,
1014 MT2063_OFFAIR_COFDM_SAWLESS,
1015 MT2063_OFFAIR_ANALOG,
1016 MT2063_OFFAIR_8VSB,
1017 MT2063_NUM_RCVR_MODES
1018};
1019
1020static const char *mt2063_mode_name[] = {
1021 [MT2063_CABLE_QAM] = "digital cable",
1022 [MT2063_CABLE_ANALOG] = "analog cable",
1023 [MT2063_OFFAIR_COFDM] = "digital offair",
1024 [MT2063_OFFAIR_COFDM_SAWLESS] = "digital offair without SAW",
1025 [MT2063_OFFAIR_ANALOG] = "analog offair",
1026 [MT2063_OFFAIR_8VSB] = "analog offair 8vsb",
1027};
1028
1029static const u8 RFAGCEN[] = { 0, 0, 0, 0, 0, 0 };
1030static const u8 LNARIN[] = { 0, 0, 3, 3, 3, 3 };
1031static const u8 FIFFQEN[] = { 1, 1, 1, 1, 1, 1 };
1032static const u8 FIFFQ[] = { 0, 0, 0, 0, 0, 0 };
1033static const u8 DNC1GC[] = { 0, 0, 0, 0, 0, 0 };
1034static const u8 DNC2GC[] = { 0, 0, 0, 0, 0, 0 };
1035static const u8 ACLNAMAX[] = { 31, 31, 31, 31, 31, 31 };
1036static const u8 LNATGT[] = { 44, 43, 43, 43, 43, 43 };
1037static const u8 RFOVDIS[] = { 0, 0, 0, 0, 0, 0 };
1038static const u8 ACRFMAX[] = { 31, 31, 31, 31, 31, 31 };
1039static const u8 PD1TGT[] = { 36, 36, 38, 38, 36, 38 };
1040static const u8 FIFOVDIS[] = { 0, 0, 0, 0, 0, 0 };
1041static const u8 ACFIFMAX[] = { 29, 29, 29, 29, 29, 29 };
1042static const u8 PD2TGT[] = { 40, 33, 38, 42, 30, 38 };
1043
1044/*
1045 * mt2063_set_dnc_output_enable()
1046 */
1047static u32 mt2063_get_dnc_output_enable(struct mt2063_state *state,
1048 enum MT2063_DNC_Output_Enable *pValue)
1049{
1050 dprintk(2, "\n");
1051
1052 if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */
1053 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
1054 *pValue = MT2063_DNC_NONE;
1055 else
1056 *pValue = MT2063_DNC_2;
1057 } else { /* DNC1 is on */
1058 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
1059 *pValue = MT2063_DNC_1;
1060 else
1061 *pValue = MT2063_DNC_BOTH;
1062 }
1063 return 0;
1064}
1065
1066/*
1067 * mt2063_set_dnc_output_enable()
1068 */
1069static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1070 enum MT2063_DNC_Output_Enable nValue)
1071{
1072 u32 status = 0; /* Status to be returned */
1073 u8 val = 0;
1074
1075 dprintk(2, "\n");
1076
1077 /* selects, which DNC output is used */
1078 switch (nValue) {
1079 case MT2063_DNC_NONE:
1080 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
1081 if (state->reg[MT2063_REG_DNC_GAIN] !=
1082 val)
1083 status |=
1084 mt2063_setreg(state,
1085 MT2063_REG_DNC_GAIN,
1086 val);
1087
1088 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1089 if (state->reg[MT2063_REG_VGA_GAIN] !=
1090 val)
1091 status |=
1092 mt2063_setreg(state,
1093 MT2063_REG_VGA_GAIN,
1094 val);
1095
1096 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
1097 if (state->reg[MT2063_REG_RSVD_20] !=
1098 val)
1099 status |=
1100 mt2063_setreg(state,
1101 MT2063_REG_RSVD_20,
1102 val);
1103
1104 break;
1105 case MT2063_DNC_1:
1106 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
1107 if (state->reg[MT2063_REG_DNC_GAIN] !=
1108 val)
1109 status |=
1110 mt2063_setreg(state,
1111 MT2063_REG_DNC_GAIN,
1112 val);
1113
1114 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1115 if (state->reg[MT2063_REG_VGA_GAIN] !=
1116 val)
1117 status |=
1118 mt2063_setreg(state,
1119 MT2063_REG_VGA_GAIN,
1120 val);
1121
1122 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
1123 if (state->reg[MT2063_REG_RSVD_20] !=
1124 val)
1125 status |=
1126 mt2063_setreg(state,
1127 MT2063_REG_RSVD_20,
1128 val);
1129
1130 break;
1131 case MT2063_DNC_2:
1132 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
1133 if (state->reg[MT2063_REG_DNC_GAIN] !=
1134 val)
1135 status |=
1136 mt2063_setreg(state,
1137 MT2063_REG_DNC_GAIN,
1138 val);
1139
1140 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
1141 if (state->reg[MT2063_REG_VGA_GAIN] !=
1142 val)
1143 status |=
1144 mt2063_setreg(state,
1145 MT2063_REG_VGA_GAIN,
1146 val);
1147
1148 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
1149 if (state->reg[MT2063_REG_RSVD_20] !=
1150 val)
1151 status |=
1152 mt2063_setreg(state,
1153 MT2063_REG_RSVD_20,
1154 val);
1155
1156 break;
1157 case MT2063_DNC_BOTH:
1158 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
1159 if (state->reg[MT2063_REG_DNC_GAIN] !=
1160 val)
1161 status |=
1162 mt2063_setreg(state,
1163 MT2063_REG_DNC_GAIN,
1164 val);
1165
1166 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
1167 if (state->reg[MT2063_REG_VGA_GAIN] !=
1168 val)
1169 status |=
1170 mt2063_setreg(state,
1171 MT2063_REG_VGA_GAIN,
1172 val);
1173
1174 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
1175 if (state->reg[MT2063_REG_RSVD_20] !=
1176 val)
1177 status |=
1178 mt2063_setreg(state,
1179 MT2063_REG_RSVD_20,
1180 val);
1181
1182 break;
1183 default:
1184 break;
1185 }
1186
1187 return status;
1188}
1189
1190/*
1191 * MT2063_SetReceiverMode() - Set the MT2063 receiver mode, according with
1192 * the selected enum mt2063_delivery_sys type.
1193 *
1194 * (DNC1GC & DNC2GC are the values, which are used, when the specific
1195 * DNC Output is selected, the other is always off)
1196 *
1197 * @state: ptr to mt2063_state structure
1198 * @Mode: desired reciever delivery system
1199 *
1200 * Note: Register cache must be valid for it to work
1201 */
1202
1203static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1204 enum mt2063_delivery_sys Mode)
1205{
1206 u32 status = 0; /* Status to be returned */
1207 u8 val;
1208 u32 longval;
1209
1210 dprintk(2, "\n");
1211
1212 if (Mode >= MT2063_NUM_RCVR_MODES)
1213 status = -ERANGE;
1214
1215 /* RFAGCen */
1216 if (status >= 0) {
1217 val =
1218 (state->
1219 reg[MT2063_REG_PD1_TGT] & (u8) ~0x40) | (RFAGCEN[Mode]
1220 ? 0x40 :
1221 0x00);
1222 if (state->reg[MT2063_REG_PD1_TGT] != val)
1223 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1224 }
1225
1226 /* LNARin */
1227 if (status >= 0) {
1228 u8 val = (state->reg[MT2063_REG_CTRL_2C] & (u8) ~0x03) |
1229 (LNARIN[Mode] & 0x03);
1230 if (state->reg[MT2063_REG_CTRL_2C] != val)
1231 status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val);
1232 }
1233
1234 /* FIFFQEN and FIFFQ */
1235 if (status >= 0) {
1236 val =
1237 (state->
1238 reg[MT2063_REG_FIFF_CTRL2] & (u8) ~0xF0) |
1239 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4);
1240 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) {
1241 status |=
1242 mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val);
1243 /* trigger FIFF calibration, needed after changing FIFFQ */
1244 val =
1245 (state->reg[MT2063_REG_FIFF_CTRL] | (u8) 0x01);
1246 status |=
1247 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1248 val =
1249 (state->
1250 reg[MT2063_REG_FIFF_CTRL] & (u8) ~0x01);
1251 status |=
1252 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1253 }
1254 }
1255
1256 /* DNC1GC & DNC2GC */
1257 status |= mt2063_get_dnc_output_enable(state, &longval);
1258 status |= mt2063_set_dnc_output_enable(state, longval);
1259
1260 /* acLNAmax */
1261 if (status >= 0) {
1262 u8 val = (state->reg[MT2063_REG_LNA_OV] & (u8) ~0x1F) |
1263 (ACLNAMAX[Mode] & 0x1F);
1264 if (state->reg[MT2063_REG_LNA_OV] != val)
1265 status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val);
1266 }
1267
1268 /* LNATGT */
1269 if (status >= 0) {
1270 u8 val = (state->reg[MT2063_REG_LNA_TGT] & (u8) ~0x3F) |
1271 (LNATGT[Mode] & 0x3F);
1272 if (state->reg[MT2063_REG_LNA_TGT] != val)
1273 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
1274 }
1275
1276 /* ACRF */
1277 if (status >= 0) {
1278 u8 val = (state->reg[MT2063_REG_RF_OV] & (u8) ~0x1F) |
1279 (ACRFMAX[Mode] & 0x1F);
1280 if (state->reg[MT2063_REG_RF_OV] != val)
1281 status |= mt2063_setreg(state, MT2063_REG_RF_OV, val);
1282 }
1283
1284 /* PD1TGT */
1285 if (status >= 0) {
1286 u8 val = (state->reg[MT2063_REG_PD1_TGT] & (u8) ~0x3F) |
1287 (PD1TGT[Mode] & 0x3F);
1288 if (state->reg[MT2063_REG_PD1_TGT] != val)
1289 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1290 }
1291
1292 /* FIFATN */
1293 if (status >= 0) {
1294 u8 val = ACFIFMAX[Mode];
1295 if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5)
1296 val = 5;
1297 val = (state->reg[MT2063_REG_FIF_OV] & (u8) ~0x1F) |
1298 (val & 0x1F);
1299 if (state->reg[MT2063_REG_FIF_OV] != val)
1300 status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val);
1301 }
1302
1303 /* PD2TGT */
1304 if (status >= 0) {
1305 u8 val = (state->reg[MT2063_REG_PD2_TGT] & (u8) ~0x3F) |
1306 (PD2TGT[Mode] & 0x3F);
1307 if (state->reg[MT2063_REG_PD2_TGT] != val)
1308 status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val);
1309 }
1310
1311 /* Ignore ATN Overload */
1312 if (status >= 0) {
1313 val = (state->reg[MT2063_REG_LNA_TGT] & (u8) ~0x80) |
1314 (RFOVDIS[Mode] ? 0x80 : 0x00);
1315 if (state->reg[MT2063_REG_LNA_TGT] != val)
1316 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
1317 }
1318
1319 /* Ignore FIF Overload */
1320 if (status >= 0) {
1321 val = (state->reg[MT2063_REG_PD1_TGT] & (u8) ~0x80) |
1322 (FIFOVDIS[Mode] ? 0x80 : 0x00);
1323 if (state->reg[MT2063_REG_PD1_TGT] != val)
1324 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1325 }
1326
1327 if (status >= 0) {
1328 state->rcvr_mode = Mode;
1329 dprintk(1, "mt2063 mode changed to %s\n",
1330 mt2063_mode_name[state->rcvr_mode]);
1331 }
1332
1333 return status;
1334}
1335
1336/*
1337 * MT2063_ClearPowerMaskBits () - Clears the power-down mask bits for various
1338 * sections of the MT2063
1339 *
1340 * @Bits: Mask bits to be cleared.
1341 *
1342 * See definition of MT2063_Mask_Bits type for description
1343 * of each of the power bits.
1344 */
1345static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state,
1346 enum MT2063_Mask_Bits Bits)
1347{
1348 u32 status = 0;
1349
1350 dprintk(2, "\n");
1351 Bits = (enum MT2063_Mask_Bits)(Bits & MT2063_ALL_SD); /* Only valid bits for this tuner */
1352 if ((Bits & 0xFF00) != 0) {
1353 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8);
1354 status |=
1355 mt2063_write(state,
1356 MT2063_REG_PWR_2,
1357 &state->reg[MT2063_REG_PWR_2], 1);
1358 }
1359 if ((Bits & 0xFF) != 0) {
1360 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF);
1361 status |=
1362 mt2063_write(state,
1363 MT2063_REG_PWR_1,
1364 &state->reg[MT2063_REG_PWR_1], 1);
1365 }
1366
1367 return status;
1368}
1369
1370/*
1371 * MT2063_SoftwareShutdown() - Enables or disables software shutdown function.
1372 * When Shutdown is 1, any section whose power
1373 * mask is set will be shutdown.
1374 */
1375static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown)
1376{
1377 u32 status;
1378
1379 dprintk(2, "\n");
1380 if (Shutdown == 1)
1381 state->reg[MT2063_REG_PWR_1] |= 0x04;
1382 else
1383 state->reg[MT2063_REG_PWR_1] &= ~0x04;
1384
1385 status = mt2063_write(state,
1386 MT2063_REG_PWR_1,
1387 &state->reg[MT2063_REG_PWR_1], 1);
1388
1389 if (Shutdown != 1) {
1390 state->reg[MT2063_REG_BYP_CTRL] =
1391 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40;
1392 status |=
1393 mt2063_write(state,
1394 MT2063_REG_BYP_CTRL,
1395 &state->reg[MT2063_REG_BYP_CTRL],
1396 1);
1397 state->reg[MT2063_REG_BYP_CTRL] =
1398 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F);
1399 status |=
1400 mt2063_write(state,
1401 MT2063_REG_BYP_CTRL,
1402 &state->reg[MT2063_REG_BYP_CTRL],
1403 1);
1404 }
1405
1406 return status;
1407}
1408
1409static u32 MT2063_Round_fLO(u32 f_LO, u32 f_LO_Step, u32 f_ref)
1410{
1411 return f_ref * (f_LO / f_ref)
1412 + f_LO_Step * (((f_LO % f_ref) + (f_LO_Step / 2)) / f_LO_Step);
1413}
1414
1415/**
1416 * fLO_FractionalTerm() - Calculates the portion contributed by FracN / denom.
1417 * This function preserves maximum precision without
1418 * risk of overflow. It accurately calculates
1419 * f_ref * num / denom to within 1 HZ with fixed math.
1420 *
1421 * @num : Fractional portion of the multiplier
1422 * @denom: denominator portion of the ratio
1423 * @f_Ref: SRO frequency.
1424 *
1425 * This calculation handles f_ref as two separate 14-bit fields.
1426 * Therefore, a maximum value of 2^28-1 may safely be used for f_ref.
1427 * This is the genesis of the magic number "14" and the magic mask value of
1428 * 0x03FFF.
1429 *
1430 * This routine successfully handles denom values up to and including 2^18.
1431 * Returns: f_ref * num / denom
1432 */
1433static u32 MT2063_fLO_FractionalTerm(u32 f_ref, u32 num, u32 denom)
1434{
1435 u32 t1 = (f_ref >> 14) * num;
1436 u32 term1 = t1 / denom;
1437 u32 loss = t1 % denom;
1438 u32 term2 =
1439 (((f_ref & 0x00003FFF) * num + (loss << 14)) + (denom / 2)) / denom;
1440 return (term1 << 14) + term2;
1441}
1442
1443/*
1444 * CalcLO1Mult()- Calculates Integer divider value and the numerator
1445 * value for a FracN PLL.
1446 *
1447 * This function assumes that the f_LO and f_Ref are
1448 * evenly divisible by f_LO_Step.
1449 *
1450 * @Div: OUTPUT: Whole number portion of the multiplier
1451 * @FracN: OUTPUT: Fractional portion of the multiplier
1452 * @f_LO: desired LO frequency.
1453 * @f_LO_Step: Minimum step size for the LO (in Hz).
1454 * @f_Ref: SRO frequency.
1455 * @f_Avoid: Range of PLL frequencies to avoid near integer multiples
1456 * of f_Ref (in Hz).
1457 *
1458 * Returns: Recalculated LO frequency.
1459 */
1460static u32 MT2063_CalcLO1Mult(u32 *Div,
1461 u32 *FracN,
1462 u32 f_LO,
1463 u32 f_LO_Step, u32 f_Ref)
1464{
1465 /* Calculate the whole number portion of the divider */
1466 *Div = f_LO / f_Ref;
1467
1468 /* Calculate the numerator value (round to nearest f_LO_Step) */
1469 *FracN =
1470 (64 * (((f_LO % f_Ref) + (f_LO_Step / 2)) / f_LO_Step) +
1471 (f_Ref / f_LO_Step / 2)) / (f_Ref / f_LO_Step);
1472
1473 return (f_Ref * (*Div)) + MT2063_fLO_FractionalTerm(f_Ref, *FracN, 64);
1474}
1475
1476/**
1477 * CalcLO2Mult() - Calculates Integer divider value and the numerator
1478 * value for a FracN PLL.
1479 *
1480 * This function assumes that the f_LO and f_Ref are
1481 * evenly divisible by f_LO_Step.
1482 *
1483 * @Div: OUTPUT: Whole number portion of the multiplier
1484 * @FracN: OUTPUT: Fractional portion of the multiplier
1485 * @f_LO: desired LO frequency.
1486 * @f_LO_Step: Minimum step size for the LO (in Hz).
1487 * @f_Ref: SRO frequency.
1488 * @f_Avoid: Range of PLL frequencies to avoid near
1489 * integer multiples of f_Ref (in Hz).
1490 *
1491 * Returns: Recalculated LO frequency.
1492 */
1493static u32 MT2063_CalcLO2Mult(u32 *Div,
1494 u32 *FracN,
1495 u32 f_LO,
1496 u32 f_LO_Step, u32 f_Ref)
1497{
1498 /* Calculate the whole number portion of the divider */
1499 *Div = f_LO / f_Ref;
1500
1501 /* Calculate the numerator value (round to nearest f_LO_Step) */
1502 *FracN =
1503 (8191 * (((f_LO % f_Ref) + (f_LO_Step / 2)) / f_LO_Step) +
1504 (f_Ref / f_LO_Step / 2)) / (f_Ref / f_LO_Step);
1505
1506 return (f_Ref * (*Div)) + MT2063_fLO_FractionalTerm(f_Ref, *FracN,
1507 8191);
1508}
1509
1510/*
1511 * FindClearTuneFilter() - Calculate the corrrect ClearTune filter to be
1512 * used for a given input frequency.
1513 *
1514 * @state: ptr to tuner data structure
1515 * @f_in: RF input center frequency (in Hz).
1516 *
1517 * Returns: ClearTune filter number (0-31)
1518 */
1519static u32 FindClearTuneFilter(struct mt2063_state *state, u32 f_in)
1520{
1521 u32 RFBand;
1522 u32 idx; /* index loop */
1523
1524 /*
1525 ** Find RF Band setting
1526 */
1527 RFBand = 31; /* def when f_in > all */
1528 for (idx = 0; idx < 31; ++idx) {
1529 if (state->CTFiltMax[idx] >= f_in) {
1530 RFBand = idx;
1531 break;
1532 }
1533 }
1534 return RFBand;
1535}
1536
1537/*
1538 * MT2063_Tune() - Change the tuner's tuned frequency to RFin.
1539 */
1540static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
1541{ /* RF input center frequency */
1542
1543 u32 status = 0;
1544 u32 LO1; /* 1st LO register value */
1545 u32 Num1; /* Numerator for LO1 reg. value */
1546 u32 f_IF1; /* 1st IF requested */
1547 u32 LO2; /* 2nd LO register value */
1548 u32 Num2; /* Numerator for LO2 reg. value */
1549 u32 ofLO1, ofLO2; /* last time's LO frequencies */
1550 u8 fiffc = 0x80; /* FIFF center freq from tuner */
1551 u32 fiffof; /* Offset from FIFF center freq */
1552 const u8 LO1LK = 0x80; /* Mask for LO1 Lock bit */
1553 u8 LO2LK = 0x08; /* Mask for LO2 Lock bit */
1554 u8 val;
1555 u32 RFBand;
1556
1557 dprintk(2, "\n");
1558 /* Check the input and output frequency ranges */
1559 if ((f_in < MT2063_MIN_FIN_FREQ) || (f_in > MT2063_MAX_FIN_FREQ))
1560 return -EINVAL;
1561
1562 if ((state->AS_Data.f_out < MT2063_MIN_FOUT_FREQ)
1563 || (state->AS_Data.f_out > MT2063_MAX_FOUT_FREQ))
1564 return -EINVAL;
1565
1566 /*
1567 * Save original LO1 and LO2 register values
1568 */
1569 ofLO1 = state->AS_Data.f_LO1;
1570 ofLO2 = state->AS_Data.f_LO2;
1571
1572 /*
1573 * Find and set RF Band setting
1574 */
1575 if (state->ctfilt_sw == 1) {
1576 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08);
1577 if (state->reg[MT2063_REG_CTUNE_CTRL] != val) {
1578 status |=
1579 mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val);
1580 }
1581 val = state->reg[MT2063_REG_CTUNE_OV];
1582 RFBand = FindClearTuneFilter(state, f_in);
1583 state->reg[MT2063_REG_CTUNE_OV] =
1584 (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F)
1585 | RFBand);
1586 if (state->reg[MT2063_REG_CTUNE_OV] != val) {
1587 status |=
1588 mt2063_setreg(state, MT2063_REG_CTUNE_OV, val);
1589 }
1590 }
1591
1592 /*
1593 * Read the FIFF Center Frequency from the tuner
1594 */
1595 if (status >= 0) {
1596 status |=
1597 mt2063_read(state,
1598 MT2063_REG_FIFFC,
1599 &state->reg[MT2063_REG_FIFFC], 1);
1600 fiffc = state->reg[MT2063_REG_FIFFC];
1601 }
1602 /*
1603 * Assign in the requested values
1604 */
1605 state->AS_Data.f_in = f_in;
1606 /* Request a 1st IF such that LO1 is on a step size */
1607 state->AS_Data.f_if1_Request =
1608 MT2063_Round_fLO(state->AS_Data.f_if1_Request + f_in,
1609 state->AS_Data.f_LO1_Step,
1610 state->AS_Data.f_ref) - f_in;
1611
1612 /*
1613 * Calculate frequency settings. f_IF1_FREQ + f_in is the
1614 * desired LO1 frequency
1615 */
1616 MT2063_ResetExclZones(&state->AS_Data);
1617
1618 f_IF1 = MT2063_ChooseFirstIF(&state->AS_Data);
1619
1620 state->AS_Data.f_LO1 =
1621 MT2063_Round_fLO(f_IF1 + f_in, state->AS_Data.f_LO1_Step,
1622 state->AS_Data.f_ref);
1623
1624 state->AS_Data.f_LO2 =
1625 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
1626 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
1627
1628 /*
1629 * Check for any LO spurs in the output bandwidth and adjust
1630 * the LO settings to avoid them if needed
1631 */
1632 status |= MT2063_AvoidSpurs(&state->AS_Data);
1633 /*
1634 * MT_AvoidSpurs spurs may have changed the LO1 & LO2 values.
1635 * Recalculate the LO frequencies and the values to be placed
1636 * in the tuning registers.
1637 */
1638 state->AS_Data.f_LO1 =
1639 MT2063_CalcLO1Mult(&LO1, &Num1, state->AS_Data.f_LO1,
1640 state->AS_Data.f_LO1_Step, state->AS_Data.f_ref);
1641 state->AS_Data.f_LO2 =
1642 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
1643 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
1644 state->AS_Data.f_LO2 =
1645 MT2063_CalcLO2Mult(&LO2, &Num2, state->AS_Data.f_LO2,
1646 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
1647
1648 /*
1649 * Check the upconverter and downconverter frequency ranges
1650 */
1651 if ((state->AS_Data.f_LO1 < MT2063_MIN_UPC_FREQ)
1652 || (state->AS_Data.f_LO1 > MT2063_MAX_UPC_FREQ))
1653 status |= MT2063_UPC_RANGE;
1654 if ((state->AS_Data.f_LO2 < MT2063_MIN_DNC_FREQ)
1655 || (state->AS_Data.f_LO2 > MT2063_MAX_DNC_FREQ))
1656 status |= MT2063_DNC_RANGE;
1657 /* LO2 Lock bit was in a different place for B0 version */
1658 if (state->tuner_id == MT2063_B0)
1659 LO2LK = 0x40;
1660
1661 /*
1662 * If we have the same LO frequencies and we're already locked,
1663 * then skip re-programming the LO registers.
1664 */
1665 if ((ofLO1 != state->AS_Data.f_LO1)
1666 || (ofLO2 != state->AS_Data.f_LO2)
1667 || ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) !=
1668 (LO1LK | LO2LK))) {
1669 /*
1670 * Calculate the FIFFOF register value
1671 *
1672 * IF1_Actual
1673 * FIFFOF = ------------ - 8 * FIFFC - 4992
1674 * f_ref/64
1675 */
1676 fiffof =
1677 (state->AS_Data.f_LO1 -
1678 f_in) / (state->AS_Data.f_ref / 64) - 8 * (u32) fiffc -
1679 4992;
1680 if (fiffof > 0xFF)
1681 fiffof = 0xFF;
1682
1683 /*
1684 * Place all of the calculated values into the local tuner
1685 * register fields.
1686 */
1687 if (status >= 0) {
1688 state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */
1689 state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */
1690 state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */
1691 |(Num2 >> 12)); /* NUM2q (hi) */
1692 state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */
1693 state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */
1694
1695 /*
1696 * Now write out the computed register values
1697 * IMPORTANT: There is a required order for writing
1698 * (0x05 must follow all the others).
1699 */
1700 status |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */
1701 if (state->tuner_id == MT2063_B0) {
1702 /* Re-write the one-shot bits to trigger the tune operation */
1703 status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */
1704 }
1705 /* Write out the FIFF offset only if it's changing */
1706 if (state->reg[MT2063_REG_FIFF_OFFSET] !=
1707 (u8) fiffof) {
1708 state->reg[MT2063_REG_FIFF_OFFSET] =
1709 (u8) fiffof;
1710 status |=
1711 mt2063_write(state,
1712 MT2063_REG_FIFF_OFFSET,
1713 &state->
1714 reg[MT2063_REG_FIFF_OFFSET],
1715 1);
1716 }
1717 }
1718
1719 /*
1720 * Check for LO's locking
1721 */
1722
1723 if (status < 0)
1724 return status;
1725
1726 status = mt2063_lockStatus(state);
1727 if (status < 0)
1728 return status;
1729 if (!status)
1730 return -EINVAL; /* Couldn't lock */
1731
1732 /*
1733 * If we locked OK, assign calculated data to mt2063_state structure
1734 */
1735 state->f_IF1_actual = state->AS_Data.f_LO1 - f_in;
1736 }
1737
1738 return status;
1739}
1740
1741static const u8 MT2063B0_defaults[] = {
1742 /* Reg, Value */
1743 0x19, 0x05,
1744 0x1B, 0x1D,
1745 0x1C, 0x1F,
1746 0x1D, 0x0F,
1747 0x1E, 0x3F,
1748 0x1F, 0x0F,
1749 0x20, 0x3F,
1750 0x22, 0x21,
1751 0x23, 0x3F,
1752 0x24, 0x20,
1753 0x25, 0x3F,
1754 0x27, 0xEE,
1755 0x2C, 0x27, /* bit at 0x20 is cleared below */
1756 0x30, 0x03,
1757 0x2C, 0x07, /* bit at 0x20 is cleared here */
1758 0x2D, 0x87,
1759 0x2E, 0xAA,
1760 0x28, 0xE1, /* Set the FIFCrst bit here */
1761 0x28, 0xE0, /* Clear the FIFCrst bit here */
1762 0x00
1763};
1764
1765/* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
1766static const u8 MT2063B1_defaults[] = {
1767 /* Reg, Value */
1768 0x05, 0xF0,
1769 0x11, 0x10, /* New Enable AFCsd */
1770 0x19, 0x05,
1771 0x1A, 0x6C,
1772 0x1B, 0x24,
1773 0x1C, 0x28,
1774 0x1D, 0x8F,
1775 0x1E, 0x14,
1776 0x1F, 0x8F,
1777 0x20, 0x57,
1778 0x22, 0x21, /* New - ver 1.03 */
1779 0x23, 0x3C, /* New - ver 1.10 */
1780 0x24, 0x20, /* New - ver 1.03 */
1781 0x2C, 0x24, /* bit at 0x20 is cleared below */
1782 0x2D, 0x87, /* FIFFQ=0 */
1783 0x2F, 0xF3,
1784 0x30, 0x0C, /* New - ver 1.11 */
1785 0x31, 0x1B, /* New - ver 1.11 */
1786 0x2C, 0x04, /* bit at 0x20 is cleared here */
1787 0x28, 0xE1, /* Set the FIFCrst bit here */
1788 0x28, 0xE0, /* Clear the FIFCrst bit here */
1789 0x00
1790};
1791
1792/* writing 0x05 0xf0 sw-resets all registers, so we write only needed changes */
1793static const u8 MT2063B3_defaults[] = {
1794 /* Reg, Value */
1795 0x05, 0xF0,
1796 0x19, 0x3D,
1797 0x2C, 0x24, /* bit at 0x20 is cleared below */
1798 0x2C, 0x04, /* bit at 0x20 is cleared here */
1799 0x28, 0xE1, /* Set the FIFCrst bit here */
1800 0x28, 0xE0, /* Clear the FIFCrst bit here */
1801 0x00
1802};
1803
1804static int mt2063_init(struct dvb_frontend *fe)
1805{
1806 u32 status;
1807 struct mt2063_state *state = fe->tuner_priv;
1808 u8 all_resets = 0xF0; /* reset/load bits */
1809 const u8 *def = NULL;
1810 char *step;
1811 u32 FCRUN;
1812 s32 maxReads;
1813 u32 fcu_osc;
1814 u32 i;
1815
1816 dprintk(2, "\n");
1817
1818 state->rcvr_mode = MT2063_CABLE_QAM;
1819
1820 /* Read the Part/Rev code from the tuner */
1821 status = mt2063_read(state, MT2063_REG_PART_REV,
1822 &state->reg[MT2063_REG_PART_REV], 1);
1823 if (status < 0) {
1824 printk(KERN_ERR "Can't read mt2063 part ID\n");
1825 return status;
1826 }
1827
1828 /* Check the part/rev code */
1829 switch (state->reg[MT2063_REG_PART_REV]) {
1830 case MT2063_B0:
1831 step = "B0";
1832 break;
1833 case MT2063_B1:
1834 step = "B1";
1835 break;
1836 case MT2063_B2:
1837 step = "B2";
1838 break;
1839 case MT2063_B3:
1840 step = "B3";
1841 break;
1842 default:
1843 printk(KERN_ERR "mt2063: Unknown mt2063 device ID (0x%02x)\n",
1844 state->reg[MT2063_REG_PART_REV]);
1845 return -ENODEV; /* Wrong tuner Part/Rev code */
1846 }
1847
1848 /* Check the 2nd byte of the Part/Rev code from the tuner */
1849 status = mt2063_read(state, MT2063_REG_RSVD_3B,
1850 &state->reg[MT2063_REG_RSVD_3B], 1);
1851
1852 /* b7 != 0 ==> NOT MT2063 */
1853 if (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) {
1854 printk(KERN_ERR "mt2063: Unknown part ID (0x%02x%02x)\n",
1855 state->reg[MT2063_REG_PART_REV],
1856 state->reg[MT2063_REG_RSVD_3B]);
1857 return -ENODEV; /* Wrong tuner Part/Rev code */
1858 }
1859
1860 printk(KERN_INFO "mt2063: detected a mt2063 %s\n", step);
1861
1862 /* Reset the tuner */
1863 status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1);
1864 if (status < 0)
1865 return status;
1866
1867 /* change all of the default values that vary from the HW reset values */
1868 /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
1869 switch (state->reg[MT2063_REG_PART_REV]) {
1870 case MT2063_B3:
1871 def = MT2063B3_defaults;
1872 break;
1873
1874 case MT2063_B1:
1875 def = MT2063B1_defaults;
1876 break;
1877
1878 case MT2063_B0:
1879 def = MT2063B0_defaults;
1880 break;
1881
1882 default:
1883 return -ENODEV;
1884 break;
1885 }
1886
1887 while (status >= 0 && *def) {
1888 u8 reg = *def++;
1889 u8 val = *def++;
1890 status = mt2063_write(state, reg, &val, 1);
1891 }
1892 if (status < 0)
1893 return status;
1894
1895 /* Wait for FIFF location to complete. */
1896 FCRUN = 1;
1897 maxReads = 10;
1898 while (status >= 0 && (FCRUN != 0) && (maxReads-- > 0)) {
1899 msleep(2);
1900 status = mt2063_read(state,
1901 MT2063_REG_XO_STATUS,
1902 &state->
1903 reg[MT2063_REG_XO_STATUS], 1);
1904 FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
1905 }
1906
1907 if (FCRUN != 0 || status < 0)
1908 return -ENODEV;
1909
1910 status = mt2063_read(state,
1911 MT2063_REG_FIFFC,
1912 &state->reg[MT2063_REG_FIFFC], 1);
1913 if (status < 0)
1914 return status;
1915
1916 /* Read back all the registers from the tuner */
1917 status = mt2063_read(state,
1918 MT2063_REG_PART_REV,
1919 state->reg, MT2063_REG_END_REGS);
1920 if (status < 0)
1921 return status;
1922
1923 /* Initialize the tuner state. */
1924 state->tuner_id = state->reg[MT2063_REG_PART_REV];
1925 state->AS_Data.f_ref = MT2063_REF_FREQ;
1926 state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) *
1927 ((u32) state->reg[MT2063_REG_FIFFC] + 640);
1928 state->AS_Data.f_if1_bw = MT2063_IF1_BW;
1929 state->AS_Data.f_out = 43750000UL;
1930 state->AS_Data.f_out_bw = 6750000UL;
1931 state->AS_Data.f_zif_bw = MT2063_ZIF_BW;
1932 state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64;
1933 state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
1934 state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
1935 state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
1936 state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
1937 state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center;
1938 state->AS_Data.f_LO1 = 2181000000UL;
1939 state->AS_Data.f_LO2 = 1486249786UL;
1940 state->f_IF1_actual = state->AS_Data.f_if1_Center;
1941 state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual;
1942 state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
1943 state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
1944 state->num_regs = MT2063_REG_END_REGS;
1945 state->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
1946 state->ctfilt_sw = 0;
1947
1948 state->CTFiltMax[0] = 69230000;
1949 state->CTFiltMax[1] = 105770000;
1950 state->CTFiltMax[2] = 140350000;
1951 state->CTFiltMax[3] = 177110000;
1952 state->CTFiltMax[4] = 212860000;
1953 state->CTFiltMax[5] = 241130000;
1954 state->CTFiltMax[6] = 274370000;
1955 state->CTFiltMax[7] = 309820000;
1956 state->CTFiltMax[8] = 342450000;
1957 state->CTFiltMax[9] = 378870000;
1958 state->CTFiltMax[10] = 416210000;
1959 state->CTFiltMax[11] = 456500000;
1960 state->CTFiltMax[12] = 495790000;
1961 state->CTFiltMax[13] = 534530000;
1962 state->CTFiltMax[14] = 572610000;
1963 state->CTFiltMax[15] = 598970000;
1964 state->CTFiltMax[16] = 635910000;
1965 state->CTFiltMax[17] = 672130000;
1966 state->CTFiltMax[18] = 714840000;
1967 state->CTFiltMax[19] = 739660000;
1968 state->CTFiltMax[20] = 770410000;
1969 state->CTFiltMax[21] = 814660000;
1970 state->CTFiltMax[22] = 846950000;
1971 state->CTFiltMax[23] = 867820000;
1972 state->CTFiltMax[24] = 915980000;
1973 state->CTFiltMax[25] = 947450000;
1974 state->CTFiltMax[26] = 983110000;
1975 state->CTFiltMax[27] = 1021630000;
1976 state->CTFiltMax[28] = 1061870000;
1977 state->CTFiltMax[29] = 1098330000;
1978 state->CTFiltMax[30] = 1138990000;
1979
1980 /*
1981 ** Fetch the FCU osc value and use it and the fRef value to
1982 ** scale all of the Band Max values
1983 */
1984
1985 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
1986 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
1987 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
1988 if (status < 0)
1989 return status;
1990
1991 /* Read the ClearTune filter calibration value */
1992 status = mt2063_read(state, MT2063_REG_FIFFC,
1993 &state->reg[MT2063_REG_FIFFC], 1);
1994 if (status < 0)
1995 return status;
1996
1997 fcu_osc = state->reg[MT2063_REG_FIFFC];
1998
1999 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
2000 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
2001 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
2002 if (status < 0)
2003 return status;
2004
2005 /* Adjust each of the values in the ClearTune filter cross-over table */
2006 for (i = 0; i < 31; i++)
2007 state->CTFiltMax[i] = (state->CTFiltMax[i] / 768) * (fcu_osc + 640);
2008
2009 status = MT2063_SoftwareShutdown(state, 1);
2010 if (status < 0)
2011 return status;
2012 status = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
2013 if (status < 0)
2014 return status;
2015
2016 state->init = true;
2017
2018 return 0;
2019}
2020
2021static int mt2063_get_status(struct dvb_frontend *fe, u32 *tuner_status)
2022{
2023 struct mt2063_state *state = fe->tuner_priv;
2024 int status;
2025
2026 dprintk(2, "\n");
2027
2028 if (!state->init)
2029 return -ENODEV;
2030
2031 *tuner_status = 0;
2032 status = mt2063_lockStatus(state);
2033 if (status < 0)
2034 return status;
2035 if (status)
2036 *tuner_status = TUNER_STATUS_LOCKED;
2037
2038 dprintk(1, "Tuner status: %d", *tuner_status);
2039
2040 return 0;
2041}
2042
2043static int mt2063_release(struct dvb_frontend *fe)
2044{
2045 struct mt2063_state *state = fe->tuner_priv;
2046
2047 dprintk(2, "\n");
2048
2049 fe->tuner_priv = NULL;
2050 kfree(state);
2051
2052 return 0;
2053}
2054
2055static int mt2063_set_analog_params(struct dvb_frontend *fe,
2056 struct analog_parameters *params)
2057{
2058 struct mt2063_state *state = fe->tuner_priv;
2059 s32 pict_car;
2060 s32 pict2chanb_vsb;
2061 s32 ch_bw;
2062 s32 if_mid;
2063 s32 rcvr_mode;
2064 int status;
2065
2066 dprintk(2, "\n");
2067
2068 if (!state->init) {
2069 status = mt2063_init(fe);
2070 if (status < 0)
2071 return status;
2072 }
2073
2074 switch (params->mode) {
2075 case V4L2_TUNER_RADIO:
2076 pict_car = 38900000;
2077 ch_bw = 8000000;
2078 pict2chanb_vsb = -(ch_bw / 2);
2079 rcvr_mode = MT2063_OFFAIR_ANALOG;
2080 break;
2081 case V4L2_TUNER_ANALOG_TV:
2082 rcvr_mode = MT2063_CABLE_ANALOG;
2083 if (params->std & ~V4L2_STD_MN) {
2084 pict_car = 38900000;
2085 ch_bw = 6000000;
2086 pict2chanb_vsb = -1250000;
2087 } else if (params->std & V4L2_STD_PAL_G) {
2088 pict_car = 38900000;
2089 ch_bw = 7000000;
2090 pict2chanb_vsb = -1250000;
2091 } else { /* PAL/SECAM standards */
2092 pict_car = 38900000;
2093 ch_bw = 8000000;
2094 pict2chanb_vsb = -1250000;
2095 }
2096 break;
2097 default:
2098 return -EINVAL;
2099 }
2100 if_mid = pict_car - (pict2chanb_vsb + (ch_bw / 2));
2101
2102 state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */
2103 state->AS_Data.f_out = if_mid;
2104 state->AS_Data.f_out_bw = ch_bw + 750000;
2105 status = MT2063_SetReceiverMode(state, rcvr_mode);
2106 if (status < 0)
2107 return status;
2108
2109 dprintk(1, "Tuning to frequency: %d, bandwidth %d, foffset %d\n",
2110 params->frequency, ch_bw, pict2chanb_vsb);
2111
2112 status = MT2063_Tune(state, (params->frequency + (pict2chanb_vsb + (ch_bw / 2))));
2113 if (status < 0)
2114 return status;
2115
2116 state->frequency = params->frequency;
2117 return 0;
2118}
2119
2120/*
2121 * As defined on EN 300 429, the DVB-C roll-off factor is 0.15.
2122 * So, the amount of the needed bandwith is given by:
2123 * Bw = Symbol_rate * (1 + 0.15)
2124 * As such, the maximum symbol rate supported by 6 MHz is given by:
2125 * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds
2126 */
2127#define MAX_SYMBOL_RATE_6MHz 5217391
2128
2129static int mt2063_set_params(struct dvb_frontend *fe)
2130{
2131 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2132 struct mt2063_state *state = fe->tuner_priv;
2133 int status;
2134 s32 pict_car;
2135 s32 pict2chanb_vsb;
2136 s32 ch_bw;
2137 s32 if_mid;
2138 s32 rcvr_mode;
2139
2140 if (!state->init) {
2141 status = mt2063_init(fe);
2142 if (status < 0)
2143 return status;
2144 }
2145
2146 dprintk(2, "\n");
2147
2148 if (c->bandwidth_hz == 0)
2149 return -EINVAL;
2150 if (c->bandwidth_hz <= 6000000)
2151 ch_bw = 6000000;
2152 else if (c->bandwidth_hz <= 7000000)
2153 ch_bw = 7000000;
2154 else
2155 ch_bw = 8000000;
2156
2157 switch (c->delivery_system) {
2158 case SYS_DVBT:
2159 rcvr_mode = MT2063_OFFAIR_COFDM;
2160 pict_car = 36125000;
2161 pict2chanb_vsb = -(ch_bw / 2);
2162 break;
2163 case SYS_DVBC_ANNEX_A:
2164 case SYS_DVBC_ANNEX_C:
2165 rcvr_mode = MT2063_CABLE_QAM;
2166 pict_car = 36125000;
2167 pict2chanb_vsb = -(ch_bw / 2);
2168 break;
2169 default:
2170 return -EINVAL;
2171 }
2172 if_mid = pict_car - (pict2chanb_vsb + (ch_bw / 2));
2173
2174 state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */
2175 state->AS_Data.f_out = if_mid;
2176 state->AS_Data.f_out_bw = ch_bw + 750000;
2177 status = MT2063_SetReceiverMode(state, rcvr_mode);
2178 if (status < 0)
2179 return status;
2180
2181 dprintk(1, "Tuning to frequency: %d, bandwidth %d, foffset %d\n",
2182 c->frequency, ch_bw, pict2chanb_vsb);
2183
2184 status = MT2063_Tune(state, (c->frequency + (pict2chanb_vsb + (ch_bw / 2))));
2185
2186 if (status < 0)
2187 return status;
2188
2189 state->frequency = c->frequency;
2190 return 0;
2191}
2192
2193static int mt2063_get_if_frequency(struct dvb_frontend *fe, u32 *freq)
2194{
2195 struct mt2063_state *state = fe->tuner_priv;
2196
2197 dprintk(2, "\n");
2198
2199 if (!state->init)
2200 return -ENODEV;
2201
2202 *freq = state->AS_Data.f_out;
2203
2204 dprintk(1, "IF frequency: %d\n", *freq);
2205
2206 return 0;
2207}
2208
2209static int mt2063_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
2210{
2211 struct mt2063_state *state = fe->tuner_priv;
2212
2213 dprintk(2, "\n");
2214
2215 if (!state->init)
2216 return -ENODEV;
2217
2218 *bw = state->AS_Data.f_out_bw - 750000;
2219
2220 dprintk(1, "bandwidth: %d\n", *bw);
2221
2222 return 0;
2223}
2224
2225static struct dvb_tuner_ops mt2063_ops = {
2226 .info = {
2227 .name = "MT2063 Silicon Tuner",
2228 .frequency_min = 45000000,
2229 .frequency_max = 850000000,
2230 .frequency_step = 0,
2231 },
2232
2233 .init = mt2063_init,
2234 .sleep = MT2063_Sleep,
2235 .get_status = mt2063_get_status,
2236 .set_analog_params = mt2063_set_analog_params,
2237 .set_params = mt2063_set_params,
2238 .get_if_frequency = mt2063_get_if_frequency,
2239 .get_bandwidth = mt2063_get_bandwidth,
2240 .release = mt2063_release,
2241};
2242
2243struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
2244 struct mt2063_config *config,
2245 struct i2c_adapter *i2c)
2246{
2247 struct mt2063_state *state = NULL;
2248
2249 dprintk(2, "\n");
2250
2251 state = kzalloc(sizeof(struct mt2063_state), GFP_KERNEL);
2252 if (state == NULL)
2253 goto error;
2254
2255 state->config = config;
2256 state->i2c = i2c;
2257 state->frontend = fe;
2258 state->reference = config->refclock / 1000; /* kHz */
2259 fe->tuner_priv = state;
2260 fe->ops.tuner_ops = mt2063_ops;
2261
2262 printk(KERN_INFO "%s: Attaching MT2063\n", __func__);
2263 return fe;
2264
2265error:
2266 kfree(state);
2267 return NULL;
2268}
2269EXPORT_SYMBOL_GPL(mt2063_attach);
2270
2271/*
2272 * Ancillary routines visible outside mt2063
2273 * FIXME: Remove them in favor of using standard tuner callbacks
2274 */
2275unsigned int tuner_MT2063_SoftwareShutdown(struct dvb_frontend *fe)
2276{
2277 struct mt2063_state *state = fe->tuner_priv;
2278 int err = 0;
2279
2280 dprintk(2, "\n");
2281
2282 err = MT2063_SoftwareShutdown(state, 1);
2283 if (err < 0)
2284 printk(KERN_ERR "%s: Couldn't shutdown\n", __func__);
2285
2286 return err;
2287}
2288EXPORT_SYMBOL_GPL(tuner_MT2063_SoftwareShutdown);
2289
2290unsigned int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe)
2291{
2292 struct mt2063_state *state = fe->tuner_priv;
2293 int err = 0;
2294
2295 dprintk(2, "\n");
2296
2297 err = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
2298 if (err < 0)
2299 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
2300
2301 return err;
2302}
2303EXPORT_SYMBOL_GPL(tuner_MT2063_ClearPowerMaskBits);
2304
2305MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2306MODULE_DESCRIPTION("MT2063 Silicon tuner");
2307MODULE_LICENSE("GPL");
diff --git a/drivers/media/common/tuners/mt2063.h b/drivers/media/common/tuners/mt2063.h
new file mode 100644
index 000000000000..62d0e8ec4e99
--- /dev/null
+++ b/drivers/media/common/tuners/mt2063.h
@@ -0,0 +1,36 @@
1#ifndef __MT2063_H__
2#define __MT2063_H__
3
4#include "dvb_frontend.h"
5
6struct mt2063_config {
7 u8 tuner_address;
8 u32 refclock;
9};
10
11#if defined(CONFIG_MEDIA_TUNER_MT2063) || (defined(CONFIG_MEDIA_TUNER_MT2063_MODULE) && defined(MODULE))
12struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
13 struct mt2063_config *config,
14 struct i2c_adapter *i2c);
15
16#else
17
18static inline struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
19 struct mt2063_config *config,
20 struct i2c_adapter *i2c)
21{
22 printk(KERN_WARNING "%s: Driver disabled by Kconfig\n", __func__);
23 return NULL;
24}
25
26int mt2063_setTune(struct dvb_frontend *fe, u32 f_in,
27 u32 bw_in,
28 enum MTTune_atv_standard tv_type);
29
30/* FIXME: Should use the standard DVB attachment interfaces */
31unsigned int tuner_MT2063_SoftwareShutdown(struct dvb_frontend *fe);
32unsigned int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe);
33
34#endif /* CONFIG_DVB_MT2063 */
35
36#endif /* __MT2063_H__ */
diff --git a/drivers/media/common/tuners/mt2131.c b/drivers/media/common/tuners/mt2131.c
index a4f830bb25d1..f83b0c1ea6c8 100644
--- a/drivers/media/common/tuners/mt2131.c
+++ b/drivers/media/common/tuners/mt2131.c
@@ -92,9 +92,9 @@ static int mt2131_writeregs(struct mt2131_priv *priv,u8 *buf, u8 len)
92 return 0; 92 return 0;
93} 93}
94 94
95static int mt2131_set_params(struct dvb_frontend *fe, 95static int mt2131_set_params(struct dvb_frontend *fe)
96 struct dvb_frontend_parameters *params)
97{ 96{
97 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
98 struct mt2131_priv *priv; 98 struct mt2131_priv *priv;
99 int ret=0, i; 99 int ret=0, i;
100 u32 freq; 100 u32 freq;
@@ -105,12 +105,8 @@ static int mt2131_set_params(struct dvb_frontend *fe,
105 u8 lockval = 0; 105 u8 lockval = 0;
106 106
107 priv = fe->tuner_priv; 107 priv = fe->tuner_priv;
108 if (fe->ops.info.type == FE_OFDM)
109 priv->bandwidth = params->u.ofdm.bandwidth;
110 else
111 priv->bandwidth = 0;
112 108
113 freq = params->frequency / 1000; // Hz -> kHz 109 freq = c->frequency / 1000; /* Hz -> kHz */
114 dprintk(1, "%s() freq=%d\n", __func__, freq); 110 dprintk(1, "%s() freq=%d\n", __func__, freq);
115 111
116 f_lo1 = freq + MT2131_IF1 * 1000; 112 f_lo1 = freq + MT2131_IF1 * 1000;
@@ -193,14 +189,6 @@ static int mt2131_get_frequency(struct dvb_frontend *fe, u32 *frequency)
193 return 0; 189 return 0;
194} 190}
195 191
196static int mt2131_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
197{
198 struct mt2131_priv *priv = fe->tuner_priv;
199 dprintk(1, "%s()\n", __func__);
200 *bandwidth = priv->bandwidth;
201 return 0;
202}
203
204static int mt2131_get_status(struct dvb_frontend *fe, u32 *status) 192static int mt2131_get_status(struct dvb_frontend *fe, u32 *status)
205{ 193{
206 struct mt2131_priv *priv = fe->tuner_priv; 194 struct mt2131_priv *priv = fe->tuner_priv;
@@ -263,7 +251,6 @@ static const struct dvb_tuner_ops mt2131_tuner_ops = {
263 251
264 .set_params = mt2131_set_params, 252 .set_params = mt2131_set_params,
265 .get_frequency = mt2131_get_frequency, 253 .get_frequency = mt2131_get_frequency,
266 .get_bandwidth = mt2131_get_bandwidth,
267 .get_status = mt2131_get_status 254 .get_status = mt2131_get_status
268}; 255};
269 256
@@ -281,7 +268,6 @@ struct dvb_frontend * mt2131_attach(struct dvb_frontend *fe,
281 return NULL; 268 return NULL;
282 269
283 priv->cfg = cfg; 270 priv->cfg = cfg;
284 priv->bandwidth = 6000000; /* 6MHz */
285 priv->i2c = i2c; 271 priv->i2c = i2c;
286 272
287 if (mt2131_readreg(priv, 0, &id) != 0) { 273 if (mt2131_readreg(priv, 0, &id) != 0) {
diff --git a/drivers/media/common/tuners/mt2131_priv.h b/drivers/media/common/tuners/mt2131_priv.h
index 4e05a67e88c1..62aeedf5c550 100644
--- a/drivers/media/common/tuners/mt2131_priv.h
+++ b/drivers/media/common/tuners/mt2131_priv.h
@@ -38,7 +38,6 @@ struct mt2131_priv {
38 struct i2c_adapter *i2c; 38 struct i2c_adapter *i2c;
39 39
40 u32 frequency; 40 u32 frequency;
41 u32 bandwidth;
42}; 41};
43 42
44#endif /* __MT2131_PRIV_H__ */ 43#endif /* __MT2131_PRIV_H__ */
diff --git a/drivers/media/common/tuners/mt2266.c b/drivers/media/common/tuners/mt2266.c
index 25a8ea342c46..bca4d75e42d4 100644
--- a/drivers/media/common/tuners/mt2266.c
+++ b/drivers/media/common/tuners/mt2266.c
@@ -122,8 +122,9 @@ static u8 mt2266_vhf[] = { 0x1d, 0xfe, 0x00, 0x00, 0xb4, 0x03, 0xa5, 0xa5,
122 122
123#define FREF 30000 // Quartz oscillator 30 MHz 123#define FREF 30000 // Quartz oscillator 30 MHz
124 124
125static int mt2266_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) 125static int mt2266_set_params(struct dvb_frontend *fe)
126{ 126{
127 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
127 struct mt2266_priv *priv; 128 struct mt2266_priv *priv;
128 int ret=0; 129 int ret=0;
129 u32 freq; 130 u32 freq;
@@ -135,32 +136,32 @@ static int mt2266_set_params(struct dvb_frontend *fe, struct dvb_frontend_parame
135 136
136 priv = fe->tuner_priv; 137 priv = fe->tuner_priv;
137 138
138 freq = params->frequency / 1000; // Hz -> kHz 139 freq = priv->frequency / 1000; /* Hz -> kHz */
139 if (freq < 470000 && freq > 230000) 140 if (freq < 470000 && freq > 230000)
140 return -EINVAL; /* Gap between VHF and UHF bands */ 141 return -EINVAL; /* Gap between VHF and UHF bands */
141 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0;
142 priv->frequency = freq * 1000;
143 142
143 priv->frequency = c->frequency;
144 tune = 2 * freq * (8192/16) / (FREF/16); 144 tune = 2 * freq * (8192/16) / (FREF/16);
145 band = (freq < 300000) ? MT2266_VHF : MT2266_UHF; 145 band = (freq < 300000) ? MT2266_VHF : MT2266_UHF;
146 if (band == MT2266_VHF) 146 if (band == MT2266_VHF)
147 tune *= 2; 147 tune *= 2;
148 148
149 switch (params->u.ofdm.bandwidth) { 149 switch (c->bandwidth_hz) {
150 case BANDWIDTH_6_MHZ: 150 case 6000000:
151 mt2266_writeregs(priv, mt2266_init_6mhz, 151 mt2266_writeregs(priv, mt2266_init_6mhz,
152 sizeof(mt2266_init_6mhz)); 152 sizeof(mt2266_init_6mhz));
153 break; 153 break;
154 case BANDWIDTH_7_MHZ: 154 case 8000000:
155 mt2266_writeregs(priv, mt2266_init_7mhz,
156 sizeof(mt2266_init_7mhz));
157 break;
158 case BANDWIDTH_8_MHZ:
159 default:
160 mt2266_writeregs(priv, mt2266_init_8mhz, 155 mt2266_writeregs(priv, mt2266_init_8mhz,
161 sizeof(mt2266_init_8mhz)); 156 sizeof(mt2266_init_8mhz));
162 break; 157 break;
158 case 7000000:
159 default:
160 mt2266_writeregs(priv, mt2266_init_7mhz,
161 sizeof(mt2266_init_7mhz));
162 break;
163 } 163 }
164 priv->bandwidth = c->bandwidth_hz;
164 165
165 if (band == MT2266_VHF && priv->band == MT2266_UHF) { 166 if (band == MT2266_VHF && priv->band == MT2266_UHF) {
166 dprintk("Switch from UHF to VHF"); 167 dprintk("Switch from UHF to VHF");
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index 54be9e6faaaf..6133315fb0e3 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -3979,54 +3979,47 @@ static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
3979 return 0; 3979 return 0;
3980} 3980}
3981 3981
3982static int mxl5005s_set_params(struct dvb_frontend *fe, 3982static int mxl5005s_set_params(struct dvb_frontend *fe)
3983 struct dvb_frontend_parameters *params)
3984{ 3983{
3985 struct mxl5005s_state *state = fe->tuner_priv; 3984 struct mxl5005s_state *state = fe->tuner_priv;
3985 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
3986 u32 delsys = c->delivery_system;
3987 u32 bw = c->bandwidth_hz;
3986 u32 req_mode, req_bw = 0; 3988 u32 req_mode, req_bw = 0;
3987 int ret; 3989 int ret;
3988 3990
3989 dprintk(1, "%s()\n", __func__); 3991 dprintk(1, "%s()\n", __func__);
3990 3992
3991 if (fe->ops.info.type == FE_ATSC) { 3993 switch (delsys) {
3992 switch (params->u.vsb.modulation) { 3994 case SYS_ATSC:
3993 case VSB_8: 3995 req_mode = MXL_ATSC;
3994 req_mode = MXL_ATSC; break; 3996 req_bw = MXL5005S_BANDWIDTH_6MHZ;
3995 default: 3997 break;
3996 case QAM_64: 3998 case SYS_DVBC_ANNEX_B:
3997 case QAM_256: 3999 req_mode = MXL_QAM;
3998 case QAM_AUTO: 4000 req_bw = MXL5005S_BANDWIDTH_6MHZ;
3999 req_mode = MXL_QAM; break; 4001 break;
4000 } 4002 default: /* Assume DVB-T */
4001 } else
4002 req_mode = MXL_DVBT; 4003 req_mode = MXL_DVBT;
4003 4004 switch (bw) {
4004 /* Change tuner for new modulation type if reqd */ 4005 case 6000000:
4005 if (req_mode != state->current_mode) { 4006 req_bw = MXL5005S_BANDWIDTH_6MHZ;
4006 switch (req_mode) { 4007 break;
4007 case MXL_ATSC: 4008 case 7000000:
4008 case MXL_QAM: 4009 req_bw = MXL5005S_BANDWIDTH_7MHZ;
4009 req_bw = MXL5005S_BANDWIDTH_6MHZ; 4010 break;
4011 case 8000000:
4012 case 0:
4013 req_bw = MXL5005S_BANDWIDTH_8MHZ;
4010 break; 4014 break;
4011 case MXL_DVBT:
4012 default: 4015 default:
4013 /* Assume DVB-T */ 4016 return -EINVAL;
4014 switch (params->u.ofdm.bandwidth) {
4015 case BANDWIDTH_6_MHZ:
4016 req_bw = MXL5005S_BANDWIDTH_6MHZ;
4017 break;
4018 case BANDWIDTH_7_MHZ:
4019 req_bw = MXL5005S_BANDWIDTH_7MHZ;
4020 break;
4021 case BANDWIDTH_AUTO:
4022 case BANDWIDTH_8_MHZ:
4023 req_bw = MXL5005S_BANDWIDTH_8MHZ;
4024 break;
4025 default:
4026 return -EINVAL;
4027 }
4028 } 4017 }
4018 }
4029 4019
4020 /* Change tuner for new modulation type if reqd */
4021 if (req_mode != state->current_mode ||
4022 req_bw != state->Chan_Bandwidth) {
4030 state->current_mode = req_mode; 4023 state->current_mode = req_mode;
4031 ret = mxl5005s_reconfigure(fe, req_mode, req_bw); 4024 ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
4032 4025
@@ -4034,8 +4027,8 @@ static int mxl5005s_set_params(struct dvb_frontend *fe,
4034 ret = 0; 4027 ret = 0;
4035 4028
4036 if (ret == 0) { 4029 if (ret == 0) {
4037 dprintk(1, "%s() freq=%d\n", __func__, params->frequency); 4030 dprintk(1, "%s() freq=%d\n", __func__, c->frequency);
4038 ret = mxl5005s_SetRfFreqHz(fe, params->frequency); 4031 ret = mxl5005s_SetRfFreqHz(fe, c->frequency);
4039 } 4032 }
4040 4033
4041 return ret; 4034 return ret;
diff --git a/drivers/media/common/tuners/mxl5007t.c b/drivers/media/common/tuners/mxl5007t.c
index 5d02221e99dd..69e453ef0a1a 100644
--- a/drivers/media/common/tuners/mxl5007t.c
+++ b/drivers/media/common/tuners/mxl5007t.c
@@ -165,6 +165,8 @@ struct mxl5007t_state {
165 struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)]; 165 struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
166 struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)]; 166 struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
167 167
168 enum mxl5007t_if_freq if_freq;
169
168 u32 frequency; 170 u32 frequency;
169 u32 bandwidth; 171 u32 bandwidth;
170}; 172};
@@ -286,6 +288,8 @@ static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
286 /* set inverted IF or normal IF */ 288 /* set inverted IF or normal IF */
287 set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00); 289 set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
288 290
291 state->if_freq = if_freq;
292
289 return; 293 return;
290} 294}
291 295
@@ -612,47 +616,43 @@ fail:
612 616
613/* ------------------------------------------------------------------------- */ 617/* ------------------------------------------------------------------------- */
614 618
615static int mxl5007t_set_params(struct dvb_frontend *fe, 619static int mxl5007t_set_params(struct dvb_frontend *fe)
616 struct dvb_frontend_parameters *params)
617{ 620{
621 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
622 u32 delsys = c->delivery_system;
618 struct mxl5007t_state *state = fe->tuner_priv; 623 struct mxl5007t_state *state = fe->tuner_priv;
619 enum mxl5007t_bw_mhz bw; 624 enum mxl5007t_bw_mhz bw;
620 enum mxl5007t_mode mode; 625 enum mxl5007t_mode mode;
621 int ret; 626 int ret;
622 u32 freq = params->frequency; 627 u32 freq = c->frequency;
623 628
624 if (fe->ops.info.type == FE_ATSC) { 629 switch (delsys) {
625 switch (params->u.vsb.modulation) { 630 case SYS_ATSC:
626 case VSB_8: 631 mode = MxL_MODE_ATSC;
627 case VSB_16: 632 bw = MxL_BW_6MHz;
628 mode = MxL_MODE_ATSC; 633 break;
629 break; 634 case SYS_DVBC_ANNEX_B:
630 case QAM_64: 635 mode = MxL_MODE_CABLE;
631 case QAM_256:
632 mode = MxL_MODE_CABLE;
633 break;
634 default:
635 mxl_err("modulation not set!");
636 return -EINVAL;
637 }
638 bw = MxL_BW_6MHz; 636 bw = MxL_BW_6MHz;
639 } else if (fe->ops.info.type == FE_OFDM) { 637 break;
640 switch (params->u.ofdm.bandwidth) { 638 case SYS_DVBT:
641 case BANDWIDTH_6_MHZ: 639 case SYS_DVBT2:
640 mode = MxL_MODE_DVBT;
641 switch (c->bandwidth_hz) {
642 case 6000000:
642 bw = MxL_BW_6MHz; 643 bw = MxL_BW_6MHz;
643 break; 644 break;
644 case BANDWIDTH_7_MHZ: 645 case 7000000:
645 bw = MxL_BW_7MHz; 646 bw = MxL_BW_7MHz;
646 break; 647 break;
647 case BANDWIDTH_8_MHZ: 648 case 8000000:
648 bw = MxL_BW_8MHz; 649 bw = MxL_BW_8MHz;
649 break; 650 break;
650 default: 651 default:
651 mxl_err("bandwidth not set!");
652 return -EINVAL; 652 return -EINVAL;
653 } 653 }
654 mode = MxL_MODE_DVBT; 654 break;
655 } else { 655 default:
656 mxl_err("modulation type not supported!"); 656 mxl_err("modulation type not supported!");
657 return -EINVAL; 657 return -EINVAL;
658 } 658 }
@@ -671,8 +671,7 @@ static int mxl5007t_set_params(struct dvb_frontend *fe,
671 goto fail; 671 goto fail;
672 672
673 state->frequency = freq; 673 state->frequency = freq;
674 state->bandwidth = (fe->ops.info.type == FE_OFDM) ? 674 state->bandwidth = c->bandwidth_hz;
675 params->u.ofdm.bandwidth : 0;
676fail: 675fail:
677 mutex_unlock(&state->lock); 676 mutex_unlock(&state->lock);
678 677
@@ -738,6 +737,50 @@ static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
738 return 0; 737 return 0;
739} 738}
740 739
740static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
741{
742 struct mxl5007t_state *state = fe->tuner_priv;
743
744 *frequency = 0;
745
746 switch (state->if_freq) {
747 case MxL_IF_4_MHZ:
748 *frequency = 4000000;
749 break;
750 case MxL_IF_4_5_MHZ:
751 *frequency = 4500000;
752 break;
753 case MxL_IF_4_57_MHZ:
754 *frequency = 4570000;
755 break;
756 case MxL_IF_5_MHZ:
757 *frequency = 5000000;
758 break;
759 case MxL_IF_5_38_MHZ:
760 *frequency = 5380000;
761 break;
762 case MxL_IF_6_MHZ:
763 *frequency = 6000000;
764 break;
765 case MxL_IF_6_28_MHZ:
766 *frequency = 6280000;
767 break;
768 case MxL_IF_9_1915_MHZ:
769 *frequency = 9191500;
770 break;
771 case MxL_IF_35_25_MHZ:
772 *frequency = 35250000;
773 break;
774 case MxL_IF_36_15_MHZ:
775 *frequency = 36150000;
776 break;
777 case MxL_IF_44_MHZ:
778 *frequency = 44000000;
779 break;
780 }
781 return 0;
782}
783
741static int mxl5007t_release(struct dvb_frontend *fe) 784static int mxl5007t_release(struct dvb_frontend *fe)
742{ 785{
743 struct mxl5007t_state *state = fe->tuner_priv; 786 struct mxl5007t_state *state = fe->tuner_priv;
@@ -767,6 +810,7 @@ static struct dvb_tuner_ops mxl5007t_tuner_ops = {
767 .get_frequency = mxl5007t_get_frequency, 810 .get_frequency = mxl5007t_get_frequency,
768 .get_bandwidth = mxl5007t_get_bandwidth, 811 .get_bandwidth = mxl5007t_get_bandwidth,
769 .release = mxl5007t_release, 812 .release = mxl5007t_release,
813 .get_if_frequency = mxl5007t_get_if_frequency,
770}; 814};
771 815
772static int mxl5007t_get_chip_id(struct mxl5007t_state *state) 816static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
diff --git a/drivers/media/common/tuners/qt1010.c b/drivers/media/common/tuners/qt1010.c
index 9f5dba244cb8..2d79b1f5d5eb 100644
--- a/drivers/media/common/tuners/qt1010.c
+++ b/drivers/media/common/tuners/qt1010.c
@@ -82,9 +82,9 @@ static void qt1010_dump_regs(struct qt1010_priv *priv)
82 printk(KERN_CONT "\n"); 82 printk(KERN_CONT "\n");
83} 83}
84 84
85static int qt1010_set_params(struct dvb_frontend *fe, 85static int qt1010_set_params(struct dvb_frontend *fe)
86 struct dvb_frontend_parameters *params)
87{ 86{
87 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
88 struct qt1010_priv *priv; 88 struct qt1010_priv *priv;
89 int err; 89 int err;
90 u32 freq, div, mod1, mod2; 90 u32 freq, div, mod1, mod2;
@@ -144,13 +144,11 @@ static int qt1010_set_params(struct dvb_frontend *fe,
144#define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */ 144#define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */
145 145
146 priv = fe->tuner_priv; 146 priv = fe->tuner_priv;
147 freq = params->frequency; 147 freq = c->frequency;
148 div = (freq + QT1010_OFFSET) / QT1010_STEP; 148 div = (freq + QT1010_OFFSET) / QT1010_STEP;
149 freq = (div * QT1010_STEP) - QT1010_OFFSET; 149 freq = (div * QT1010_STEP) - QT1010_OFFSET;
150 mod1 = (freq + QT1010_OFFSET) % FREQ1; 150 mod1 = (freq + QT1010_OFFSET) % FREQ1;
151 mod2 = (freq + QT1010_OFFSET) % FREQ2; 151 mod2 = (freq + QT1010_OFFSET) % FREQ2;
152 priv->bandwidth =
153 (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0;
154 priv->frequency = freq; 152 priv->frequency = freq;
155 153
156 if (fe->ops.i2c_gate_ctrl) 154 if (fe->ops.i2c_gate_ctrl)
@@ -320,7 +318,7 @@ static u8 qt1010_init_meas2(struct qt1010_priv *priv,
320static int qt1010_init(struct dvb_frontend *fe) 318static int qt1010_init(struct dvb_frontend *fe)
321{ 319{
322 struct qt1010_priv *priv = fe->tuner_priv; 320 struct qt1010_priv *priv = fe->tuner_priv;
323 struct dvb_frontend_parameters params; 321 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
324 int err = 0; 322 int err = 0;
325 u8 i, tmpval, *valptr = NULL; 323 u8 i, tmpval, *valptr = NULL;
326 324
@@ -397,9 +395,9 @@ static int qt1010_init(struct dvb_frontend *fe)
397 if ((err = qt1010_init_meas2(priv, i, &tmpval))) 395 if ((err = qt1010_init_meas2(priv, i, &tmpval)))
398 return err; 396 return err;
399 397
400 params.frequency = 545000000; /* Sigmatek DVB-110 545000000 */ 398 c->frequency = 545000000; /* Sigmatek DVB-110 545000000 */
401 /* MSI Megasky 580 GL861 533000000 */ 399 /* MSI Megasky 580 GL861 533000000 */
402 return qt1010_set_params(fe, &params); 400 return qt1010_set_params(fe);
403} 401}
404 402
405static int qt1010_release(struct dvb_frontend *fe) 403static int qt1010_release(struct dvb_frontend *fe)
@@ -416,10 +414,9 @@ static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
416 return 0; 414 return 0;
417} 415}
418 416
419static int qt1010_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 417static int qt1010_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
420{ 418{
421 struct qt1010_priv *priv = fe->tuner_priv; 419 *frequency = 36125000;
422 *bandwidth = priv->bandwidth;
423 return 0; 420 return 0;
424} 421}
425 422
@@ -437,7 +434,7 @@ static const struct dvb_tuner_ops qt1010_tuner_ops = {
437 434
438 .set_params = qt1010_set_params, 435 .set_params = qt1010_set_params,
439 .get_frequency = qt1010_get_frequency, 436 .get_frequency = qt1010_get_frequency,
440 .get_bandwidth = qt1010_get_bandwidth 437 .get_if_frequency = qt1010_get_if_frequency,
441}; 438};
442 439
443struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe, 440struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
diff --git a/drivers/media/common/tuners/qt1010_priv.h b/drivers/media/common/tuners/qt1010_priv.h
index 090cf475f099..2c42d3f01636 100644
--- a/drivers/media/common/tuners/qt1010_priv.h
+++ b/drivers/media/common/tuners/qt1010_priv.h
@@ -99,7 +99,6 @@ struct qt1010_priv {
99 u8 reg25_init_val; 99 u8 reg25_init_val;
100 100
101 u32 frequency; 101 u32 frequency;
102 u32 bandwidth;
103}; 102};
104 103
105#endif 104#endif
diff --git a/drivers/media/common/tuners/tda18212.c b/drivers/media/common/tuners/tda18212.c
index e29cc2bc113a..602c2e392b17 100644
--- a/drivers/media/common/tuners/tda18212.c
+++ b/drivers/media/common/tuners/tda18212.c
@@ -25,6 +25,8 @@
25struct tda18212_priv { 25struct tda18212_priv {
26 struct tda18212_config *cfg; 26 struct tda18212_config *cfg;
27 struct i2c_adapter *i2c; 27 struct i2c_adapter *i2c;
28
29 u32 if_frequency;
28}; 30};
29 31
30#define dbg(fmt, arg...) \ 32#define dbg(fmt, arg...) \
@@ -128,20 +130,31 @@ static void tda18212_dump_regs(struct tda18212_priv *priv)
128} 130}
129#endif 131#endif
130 132
131static int tda18212_set_params(struct dvb_frontend *fe, 133static int tda18212_set_params(struct dvb_frontend *fe)
132 struct dvb_frontend_parameters *p)
133{ 134{
134 struct tda18212_priv *priv = fe->tuner_priv; 135 struct tda18212_priv *priv = fe->tuner_priv;
135 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 136 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
136 int ret, i; 137 int ret, i;
137 u32 if_khz; 138 u32 if_khz;
138 u8 buf[9]; 139 u8 buf[9];
140 #define DVBT_6 0
141 #define DVBT_7 1
142 #define DVBT_8 2
143 #define DVBT2_6 3
144 #define DVBT2_7 4
145 #define DVBT2_8 5
146 #define DVBC_6 6
147 #define DVBC_8 7
139 static const u8 bw_params[][3] = { 148 static const u8 bw_params[][3] = {
140 /* 0f 13 23 */ 149 /* reg: 0f 13 23 */
141 { 0xb3, 0x20, 0x03 }, /* DVB-T 6 MHz */ 150 [DVBT_6] = { 0xb3, 0x20, 0x03 },
142 { 0xb3, 0x31, 0x01 }, /* DVB-T 7 MHz */ 151 [DVBT_7] = { 0xb3, 0x31, 0x01 },
143 { 0xb3, 0x22, 0x01 }, /* DVB-T 8 MHz */ 152 [DVBT_8] = { 0xb3, 0x22, 0x01 },
144 { 0x92, 0x53, 0x03 }, /* DVB-C */ 153 [DVBT2_6] = { 0xbc, 0x20, 0x03 },
154 [DVBT2_7] = { 0xbc, 0x72, 0x03 },
155 [DVBT2_8] = { 0xbc, 0x22, 0x01 },
156 [DVBC_6] = { 0x92, 0x50, 0x03 },
157 [DVBC_8] = { 0x92, 0x53, 0x03 },
145 }; 158 };
146 159
147 dbg("delsys=%d RF=%d BW=%d\n", 160 dbg("delsys=%d RF=%d BW=%d\n",
@@ -155,24 +168,44 @@ static int tda18212_set_params(struct dvb_frontend *fe,
155 switch (c->bandwidth_hz) { 168 switch (c->bandwidth_hz) {
156 case 6000000: 169 case 6000000:
157 if_khz = priv->cfg->if_dvbt_6; 170 if_khz = priv->cfg->if_dvbt_6;
158 i = 0; 171 i = DVBT_6;
159 break; 172 break;
160 case 7000000: 173 case 7000000:
161 if_khz = priv->cfg->if_dvbt_7; 174 if_khz = priv->cfg->if_dvbt_7;
162 i = 1; 175 i = DVBT_7;
163 break; 176 break;
164 case 8000000: 177 case 8000000:
165 if_khz = priv->cfg->if_dvbt_8; 178 if_khz = priv->cfg->if_dvbt_8;
166 i = 2; 179 i = DVBT_8;
167 break; 180 break;
168 default: 181 default:
169 ret = -EINVAL; 182 ret = -EINVAL;
170 goto error; 183 goto error;
171 } 184 }
172 break; 185 break;
173 case SYS_DVBC_ANNEX_AC: 186 case SYS_DVBT2:
187 switch (c->bandwidth_hz) {
188 case 6000000:
189 if_khz = priv->cfg->if_dvbt2_6;
190 i = DVBT2_6;
191 break;
192 case 7000000:
193 if_khz = priv->cfg->if_dvbt2_7;
194 i = DVBT2_7;
195 break;
196 case 8000000:
197 if_khz = priv->cfg->if_dvbt2_8;
198 i = DVBT2_8;
199 break;
200 default:
201 ret = -EINVAL;
202 goto error;
203 }
204 break;
205 case SYS_DVBC_ANNEX_A:
206 case SYS_DVBC_ANNEX_C:
174 if_khz = priv->cfg->if_dvbc; 207 if_khz = priv->cfg->if_dvbc;
175 i = 3; 208 i = DVBC_8;
176 break; 209 break;
177 default: 210 default:
178 ret = -EINVAL; 211 ret = -EINVAL;
@@ -194,7 +227,7 @@ static int tda18212_set_params(struct dvb_frontend *fe,
194 buf[0] = 0x02; 227 buf[0] = 0x02;
195 buf[1] = bw_params[i][1]; 228 buf[1] = bw_params[i][1];
196 buf[2] = 0x03; /* default value */ 229 buf[2] = 0x03; /* default value */
197 buf[3] = if_khz / 50; 230 buf[3] = DIV_ROUND_CLOSEST(if_khz, 50);
198 buf[4] = ((c->frequency / 1000) >> 16) & 0xff; 231 buf[4] = ((c->frequency / 1000) >> 16) & 0xff;
199 buf[5] = ((c->frequency / 1000) >> 8) & 0xff; 232 buf[5] = ((c->frequency / 1000) >> 8) & 0xff;
200 buf[6] = ((c->frequency / 1000) >> 0) & 0xff; 233 buf[6] = ((c->frequency / 1000) >> 0) & 0xff;
@@ -204,6 +237,9 @@ static int tda18212_set_params(struct dvb_frontend *fe,
204 if (ret) 237 if (ret)
205 goto error; 238 goto error;
206 239
240 /* actual IF rounded as it is on register */
241 priv->if_frequency = buf[3] * 50 * 1000;
242
207exit: 243exit:
208 if (fe->ops.i2c_gate_ctrl) 244 if (fe->ops.i2c_gate_ctrl)
209 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ 245 fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
@@ -215,6 +251,15 @@ error:
215 goto exit; 251 goto exit;
216} 252}
217 253
254static int tda18212_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
255{
256 struct tda18212_priv *priv = fe->tuner_priv;
257
258 *frequency = priv->if_frequency;
259
260 return 0;
261}
262
218static int tda18212_release(struct dvb_frontend *fe) 263static int tda18212_release(struct dvb_frontend *fe)
219{ 264{
220 kfree(fe->tuner_priv); 265 kfree(fe->tuner_priv);
@@ -234,6 +279,7 @@ static const struct dvb_tuner_ops tda18212_tuner_ops = {
234 .release = tda18212_release, 279 .release = tda18212_release,
235 280
236 .set_params = tda18212_set_params, 281 .set_params = tda18212_set_params,
282 .get_if_frequency = tda18212_get_if_frequency,
237}; 283};
238 284
239struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe, 285struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe,
diff --git a/drivers/media/common/tuners/tda18212.h b/drivers/media/common/tuners/tda18212.h
index 83b497f59e1b..9bd5da4aabb7 100644
--- a/drivers/media/common/tuners/tda18212.h
+++ b/drivers/media/common/tuners/tda18212.h
@@ -29,6 +29,10 @@ struct tda18212_config {
29 u16 if_dvbt_6; 29 u16 if_dvbt_6;
30 u16 if_dvbt_7; 30 u16 if_dvbt_7;
31 u16 if_dvbt_8; 31 u16 if_dvbt_8;
32 u16 if_dvbt2_5;
33 u16 if_dvbt2_6;
34 u16 if_dvbt2_7;
35 u16 if_dvbt2_8;
32 u16 if_dvbc; 36 u16 if_dvbc;
33}; 37};
34 38
diff --git a/drivers/media/common/tuners/tda18218.c b/drivers/media/common/tuners/tda18218.c
index 4fc29730a12c..dfb3a831df45 100644
--- a/drivers/media/common/tuners/tda18218.c
+++ b/drivers/media/common/tuners/tda18218.c
@@ -109,10 +109,11 @@ static int tda18218_rd_reg(struct tda18218_priv *priv, u8 reg, u8 *val)
109 return tda18218_rd_regs(priv, reg, val, 1); 109 return tda18218_rd_regs(priv, reg, val, 1);
110} 110}
111 111
112static int tda18218_set_params(struct dvb_frontend *fe, 112static int tda18218_set_params(struct dvb_frontend *fe)
113 struct dvb_frontend_parameters *params)
114{ 113{
115 struct tda18218_priv *priv = fe->tuner_priv; 114 struct tda18218_priv *priv = fe->tuner_priv;
115 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
116 u32 bw = c->bandwidth_hz;
116 int ret; 117 int ret;
117 u8 buf[3], i, BP_Filter, LP_Fc; 118 u8 buf[3], i, BP_Filter, LP_Fc;
118 u32 LO_Frac; 119 u32 LO_Frac;
@@ -138,22 +139,19 @@ static int tda18218_set_params(struct dvb_frontend *fe,
138 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ 139 fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
139 140
140 /* low-pass filter cut-off frequency */ 141 /* low-pass filter cut-off frequency */
141 switch (params->u.ofdm.bandwidth) { 142 if (bw <= 6000000) {
142 case BANDWIDTH_6_MHZ:
143 LP_Fc = 0; 143 LP_Fc = 0;
144 LO_Frac = params->frequency + 3000000; 144 priv->if_frequency = 3000000;
145 break; 145 } else if (bw <= 7000000) {
146 case BANDWIDTH_7_MHZ:
147 LP_Fc = 1; 146 LP_Fc = 1;
148 LO_Frac = params->frequency + 3500000; 147 priv->if_frequency = 3500000;
149 break; 148 } else {
150 case BANDWIDTH_8_MHZ:
151 default:
152 LP_Fc = 2; 149 LP_Fc = 2;
153 LO_Frac = params->frequency + 4000000; 150 priv->if_frequency = 4000000;
154 break;
155 } 151 }
156 152
153 LO_Frac = c->frequency + priv->if_frequency;
154
157 /* band-pass filter */ 155 /* band-pass filter */
158 if (LO_Frac < 188000000) 156 if (LO_Frac < 188000000)
159 BP_Filter = 3; 157 BP_Filter = 3;
@@ -206,6 +204,14 @@ error:
206 return ret; 204 return ret;
207} 205}
208 206
207static int tda18218_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
208{
209 struct tda18218_priv *priv = fe->tuner_priv;
210 *frequency = priv->if_frequency;
211 dbg("%s: if=%d", __func__, *frequency);
212 return 0;
213}
214
209static int tda18218_sleep(struct dvb_frontend *fe) 215static int tda18218_sleep(struct dvb_frontend *fe)
210{ 216{
211 struct tda18218_priv *priv = fe->tuner_priv; 217 struct tda18218_priv *priv = fe->tuner_priv;
@@ -268,6 +274,8 @@ static const struct dvb_tuner_ops tda18218_tuner_ops = {
268 .sleep = tda18218_sleep, 274 .sleep = tda18218_sleep,
269 275
270 .set_params = tda18218_set_params, 276 .set_params = tda18218_set_params,
277
278 .get_if_frequency = tda18218_get_if_frequency,
271}; 279};
272 280
273struct dvb_frontend *tda18218_attach(struct dvb_frontend *fe, 281struct dvb_frontend *tda18218_attach(struct dvb_frontend *fe,
diff --git a/drivers/media/common/tuners/tda18218_priv.h b/drivers/media/common/tuners/tda18218_priv.h
index 904e5365c78c..dc52b72e1407 100644
--- a/drivers/media/common/tuners/tda18218_priv.h
+++ b/drivers/media/common/tuners/tda18218_priv.h
@@ -100,6 +100,8 @@ struct tda18218_priv {
100 struct tda18218_config *cfg; 100 struct tda18218_config *cfg;
101 struct i2c_adapter *i2c; 101 struct i2c_adapter *i2c;
102 102
103 u32 if_frequency;
104
103 u8 regs[TDA18218_NUM_REGS]; 105 u8 regs[TDA18218_NUM_REGS];
104}; 106};
105 107
diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c
index 63cc4004e211..2e67f4459904 100644
--- a/drivers/media/common/tuners/tda18271-fe.c
+++ b/drivers/media/common/tuners/tda18271-fe.c
@@ -928,59 +928,49 @@ fail:
928 928
929/* ------------------------------------------------------------------ */ 929/* ------------------------------------------------------------------ */
930 930
931static int tda18271_set_params(struct dvb_frontend *fe, 931static int tda18271_set_params(struct dvb_frontend *fe)
932 struct dvb_frontend_parameters *params)
933{ 932{
933 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
934 u32 delsys = c->delivery_system;
935 u32 bw = c->bandwidth_hz;
936 u32 freq = c->frequency;
934 struct tda18271_priv *priv = fe->tuner_priv; 937 struct tda18271_priv *priv = fe->tuner_priv;
935 struct tda18271_std_map *std_map = &priv->std; 938 struct tda18271_std_map *std_map = &priv->std;
936 struct tda18271_std_map_item *map; 939 struct tda18271_std_map_item *map;
937 int ret; 940 int ret;
938 u32 bw, freq = params->frequency;
939 941
940 priv->mode = TDA18271_DIGITAL; 942 priv->mode = TDA18271_DIGITAL;
941 943
942 if (fe->ops.info.type == FE_ATSC) { 944 switch (delsys) {
943 switch (params->u.vsb.modulation) { 945 case SYS_ATSC:
944 case VSB_8: 946 map = &std_map->atsc_6;
945 case VSB_16:
946 map = &std_map->atsc_6;
947 break;
948 case QAM_64:
949 case QAM_256:
950 map = &std_map->qam_6;
951 break;
952 default:
953 tda_warn("modulation not set!\n");
954 return -EINVAL;
955 }
956#if 0
957 /* userspace request is already center adjusted */
958 freq += 1750000; /* Adjust to center (+1.75MHZ) */
959#endif
960 bw = 6000000; 947 bw = 6000000;
961 } else if (fe->ops.info.type == FE_OFDM) { 948 break;
962 switch (params->u.ofdm.bandwidth) { 949 case SYS_ISDBT:
963 case BANDWIDTH_6_MHZ: 950 case SYS_DVBT:
964 bw = 6000000; 951 case SYS_DVBT2:
952 if (bw <= 6000000) {
965 map = &std_map->dvbt_6; 953 map = &std_map->dvbt_6;
966 break; 954 } else if (bw <= 7000000) {
967 case BANDWIDTH_7_MHZ:
968 bw = 7000000;
969 map = &std_map->dvbt_7; 955 map = &std_map->dvbt_7;
970 break; 956 } else {
971 case BANDWIDTH_8_MHZ:
972 bw = 8000000;
973 map = &std_map->dvbt_8; 957 map = &std_map->dvbt_8;
974 break;
975 default:
976 tda_warn("bandwidth not set!\n");
977 return -EINVAL;
978 } 958 }
979 } else if (fe->ops.info.type == FE_QAM) { 959 break;
980 /* DVB-C */ 960 case SYS_DVBC_ANNEX_B:
981 map = &std_map->qam_8; 961 bw = 6000000;
982 bw = 8000000; 962 /* falltrough */
983 } else { 963 case SYS_DVBC_ANNEX_A:
964 case SYS_DVBC_ANNEX_C:
965 if (bw <= 6000000) {
966 map = &std_map->qam_6;
967 } else if (bw <= 7000000) {
968 map = &std_map->qam_7;
969 } else {
970 map = &std_map->qam_8;
971 }
972 break;
973 default:
984 tda_warn("modulation type not supported!\n"); 974 tda_warn("modulation type not supported!\n");
985 return -EINVAL; 975 return -EINVAL;
986 } 976 }
@@ -994,9 +984,9 @@ static int tda18271_set_params(struct dvb_frontend *fe,
994 if (tda_fail(ret)) 984 if (tda_fail(ret))
995 goto fail; 985 goto fail;
996 986
987 priv->if_freq = map->if_freq;
997 priv->frequency = freq; 988 priv->frequency = freq;
998 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? 989 priv->bandwidth = bw;
999 params->u.ofdm.bandwidth : 0;
1000fail: 990fail:
1001 return ret; 991 return ret;
1002} 992}
@@ -1050,6 +1040,7 @@ static int tda18271_set_analog_params(struct dvb_frontend *fe,
1050 if (tda_fail(ret)) 1040 if (tda_fail(ret))
1051 goto fail; 1041 goto fail;
1052 1042
1043 priv->if_freq = map->if_freq;
1053 priv->frequency = freq; 1044 priv->frequency = freq;
1054 priv->bandwidth = 0; 1045 priv->bandwidth = 0;
1055fail: 1046fail:
@@ -1086,6 +1077,13 @@ static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
1086 return 0; 1077 return 0;
1087} 1078}
1088 1079
1080static int tda18271_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
1081{
1082 struct tda18271_priv *priv = fe->tuner_priv;
1083 *frequency = (u32)priv->if_freq * 1000;
1084 return 0;
1085}
1086
1089/* ------------------------------------------------------------------ */ 1087/* ------------------------------------------------------------------ */
1090 1088
1091#define tda18271_update_std(std_cfg, name) do { \ 1089#define tda18271_update_std(std_cfg, name) do { \
@@ -1245,6 +1243,7 @@ static const struct dvb_tuner_ops tda18271_tuner_ops = {
1245 .set_config = tda18271_set_config, 1243 .set_config = tda18271_set_config,
1246 .get_frequency = tda18271_get_frequency, 1244 .get_frequency = tda18271_get_frequency,
1247 .get_bandwidth = tda18271_get_bandwidth, 1245 .get_bandwidth = tda18271_get_bandwidth,
1246 .get_if_frequency = tda18271_get_if_frequency,
1248}; 1247};
1249 1248
1250struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, 1249struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
diff --git a/drivers/media/common/tuners/tda18271-maps.c b/drivers/media/common/tuners/tda18271-maps.c
index 3d5b6ab7e332..fb881c667c94 100644
--- a/drivers/media/common/tuners/tda18271-maps.c
+++ b/drivers/media/common/tuners/tda18271-maps.c
@@ -1213,6 +1213,8 @@ static struct tda18271_std_map tda18271c1_std_map = {
1213 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1e */ 1213 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1e */
1214 .qam_6 = { .if_freq = 4000, .fm_rfn = 0, .agc_mode = 3, .std = 5, 1214 .qam_6 = { .if_freq = 4000, .fm_rfn = 0, .agc_mode = 3, .std = 5,
1215 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ 1215 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */
1216 .qam_7 = { .if_freq = 4500, .fm_rfn = 0, .agc_mode = 3, .std = 6,
1217 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1e */
1216 .qam_8 = { .if_freq = 5000, .fm_rfn = 0, .agc_mode = 3, .std = 7, 1218 .qam_8 = { .if_freq = 5000, .fm_rfn = 0, .agc_mode = 3, .std = 7,
1217 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1f */ 1219 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1f */
1218}; 1220};
@@ -1244,6 +1246,8 @@ static struct tda18271_std_map tda18271c2_std_map = {
1244 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ 1246 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */
1245 .qam_6 = { .if_freq = 4000, .fm_rfn = 0, .agc_mode = 3, .std = 5, 1247 .qam_6 = { .if_freq = 4000, .fm_rfn = 0, .agc_mode = 3, .std = 5,
1246 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ 1248 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */
1249 .qam_7 = { .if_freq = 4500, .fm_rfn = 0, .agc_mode = 3, .std = 6,
1250 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1e */
1247 .qam_8 = { .if_freq = 5000, .fm_rfn = 0, .agc_mode = 3, .std = 7, 1251 .qam_8 = { .if_freq = 5000, .fm_rfn = 0, .agc_mode = 3, .std = 7,
1248 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1f */ 1252 .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1f */
1249}; 1253};
diff --git a/drivers/media/common/tuners/tda18271-priv.h b/drivers/media/common/tuners/tda18271-priv.h
index 94340f47562b..454c152ccaa0 100644
--- a/drivers/media/common/tuners/tda18271-priv.h
+++ b/drivers/media/common/tuners/tda18271-priv.h
@@ -122,6 +122,8 @@ struct tda18271_priv {
122 122
123 struct mutex lock; 123 struct mutex lock;
124 124
125 u16 if_freq;
126
125 u32 frequency; 127 u32 frequency;
126 u32 bandwidth; 128 u32 bandwidth;
127}; 129};
diff --git a/drivers/media/common/tuners/tda18271.h b/drivers/media/common/tuners/tda18271.h
index 50cfa8cebb93..640bae4e6a5a 100644
--- a/drivers/media/common/tuners/tda18271.h
+++ b/drivers/media/common/tuners/tda18271.h
@@ -53,6 +53,7 @@ struct tda18271_std_map {
53 struct tda18271_std_map_item dvbt_7; 53 struct tda18271_std_map_item dvbt_7;
54 struct tda18271_std_map_item dvbt_8; 54 struct tda18271_std_map_item dvbt_8;
55 struct tda18271_std_map_item qam_6; 55 struct tda18271_std_map_item qam_6;
56 struct tda18271_std_map_item qam_7;
56 struct tda18271_std_map_item qam_8; 57 struct tda18271_std_map_item qam_8;
57}; 58};
58 59
diff --git a/drivers/media/common/tuners/tda827x.c b/drivers/media/common/tuners/tda827x.c
index e0d5b43772b8..a0d176267470 100644
--- a/drivers/media/common/tuners/tda827x.c
+++ b/drivers/media/common/tuners/tda827x.c
@@ -152,9 +152,9 @@ static int tuner_transfer(struct dvb_frontend *fe,
152 return rc; 152 return rc;
153} 153}
154 154
155static int tda827xo_set_params(struct dvb_frontend *fe, 155static int tda827xo_set_params(struct dvb_frontend *fe)
156 struct dvb_frontend_parameters *params)
157{ 156{
157 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
158 struct tda827x_priv *priv = fe->tuner_priv; 158 struct tda827x_priv *priv = fe->tuner_priv;
159 u8 buf[14]; 159 u8 buf[14];
160 int rc; 160 int rc;
@@ -165,18 +165,16 @@ static int tda827xo_set_params(struct dvb_frontend *fe,
165 u32 N; 165 u32 N;
166 166
167 dprintk("%s:\n", __func__); 167 dprintk("%s:\n", __func__);
168 switch (params->u.ofdm.bandwidth) { 168 if (c->bandwidth_hz == 0) {
169 case BANDWIDTH_6_MHZ: 169 if_freq = 5000000;
170 } else if (c->bandwidth_hz <= 6000000) {
170 if_freq = 4000000; 171 if_freq = 4000000;
171 break; 172 } else if (c->bandwidth_hz <= 7000000) {
172 case BANDWIDTH_7_MHZ:
173 if_freq = 4500000; 173 if_freq = 4500000;
174 break; 174 } else { /* 8 MHz */
175 default: /* 8 MHz or Auto */
176 if_freq = 5000000; 175 if_freq = 5000000;
177 break;
178 } 176 }
179 tuner_freq = params->frequency; 177 tuner_freq = c->frequency;
180 178
181 i = 0; 179 i = 0;
182 while (tda827x_table[i].lomax < tuner_freq) { 180 while (tda827x_table[i].lomax < tuner_freq) {
@@ -220,8 +218,8 @@ static int tda827xo_set_params(struct dvb_frontend *fe,
220 if (rc < 0) 218 if (rc < 0)
221 goto err; 219 goto err;
222 220
223 priv->frequency = params->frequency; 221 priv->frequency = c->frequency;
224 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; 222 priv->bandwidth = c->bandwidth_hz;
225 223
226 return 0; 224 return 0;
227 225
@@ -513,9 +511,9 @@ static void tda827xa_lna_gain(struct dvb_frontend *fe, int high,
513 } 511 }
514} 512}
515 513
516static int tda827xa_set_params(struct dvb_frontend *fe, 514static int tda827xa_set_params(struct dvb_frontend *fe)
517 struct dvb_frontend_parameters *params)
518{ 515{
516 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
519 struct tda827x_priv *priv = fe->tuner_priv; 517 struct tda827x_priv *priv = fe->tuner_priv;
520 struct tda827xa_data *frequency_map = tda827xa_dvbt; 518 struct tda827xa_data *frequency_map = tda827xa_dvbt;
521 u8 buf[11]; 519 u8 buf[11];
@@ -531,22 +529,25 @@ static int tda827xa_set_params(struct dvb_frontend *fe,
531 tda827xa_lna_gain(fe, 1, NULL); 529 tda827xa_lna_gain(fe, 1, NULL);
532 msleep(20); 530 msleep(20);
533 531
534 switch (params->u.ofdm.bandwidth) { 532 if (c->bandwidth_hz == 0) {
535 case BANDWIDTH_6_MHZ: 533 if_freq = 5000000;
534 } else if (c->bandwidth_hz <= 6000000) {
536 if_freq = 4000000; 535 if_freq = 4000000;
537 break; 536 } else if (c->bandwidth_hz <= 7000000) {
538 case BANDWIDTH_7_MHZ:
539 if_freq = 4500000; 537 if_freq = 4500000;
540 break; 538 } else { /* 8 MHz */
541 default: /* 8 MHz or Auto */
542 if_freq = 5000000; 539 if_freq = 5000000;
543 break;
544 } 540 }
545 tuner_freq = params->frequency; 541 tuner_freq = c->frequency;
546 542
547 if (fe->ops.info.type == FE_QAM) { 543 switch (c->delivery_system) {
544 case SYS_DVBC_ANNEX_A:
545 case SYS_DVBC_ANNEX_C:
548 dprintk("%s select tda827xa_dvbc\n", __func__); 546 dprintk("%s select tda827xa_dvbc\n", __func__);
549 frequency_map = tda827xa_dvbc; 547 frequency_map = tda827xa_dvbc;
548 break;
549 default:
550 break;
550 } 551 }
551 552
552 i = 0; 553 i = 0;
@@ -645,9 +646,8 @@ static int tda827xa_set_params(struct dvb_frontend *fe,
645 if (rc < 0) 646 if (rc < 0)
646 goto err; 647 goto err;
647 648
648 priv->frequency = params->frequency; 649 priv->frequency = c->frequency;
649 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; 650 priv->bandwidth = c->bandwidth_hz;
650
651 651
652 return 0; 652 return 0;
653 653
diff --git a/drivers/media/common/tuners/tuner-simple.c b/drivers/media/common/tuners/tuner-simple.c
index f8ee29e6059c..39e7e583c8c0 100644
--- a/drivers/media/common/tuners/tuner-simple.c
+++ b/drivers/media/common/tuners/tuner-simple.c
@@ -751,6 +751,17 @@ static int simple_set_radio_freq(struct dvb_frontend *fe,
751 if (4 != rc) 751 if (4 != rc)
752 tuner_warn("i2c i/o error: rc == %d (should be 4)\n", rc); 752 tuner_warn("i2c i/o error: rc == %d (should be 4)\n", rc);
753 753
754 /* Write AUX byte */
755 switch (priv->type) {
756 case TUNER_PHILIPS_FM1216ME_MK3:
757 buffer[2] = 0x98;
758 buffer[3] = 0x20; /* set TOP AGC */
759 rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 4);
760 if (4 != rc)
761 tuner_warn("i2c i/o error: rc == %d (should be 4)\n", rc);
762 break;
763 }
764
754 return 0; 765 return 0;
755} 766}
756 767
@@ -780,24 +791,26 @@ static int simple_set_params(struct dvb_frontend *fe,
780} 791}
781 792
782static void simple_set_dvb(struct dvb_frontend *fe, u8 *buf, 793static void simple_set_dvb(struct dvb_frontend *fe, u8 *buf,
783 const struct dvb_frontend_parameters *params) 794 const u32 delsys,
795 const u32 frequency,
796 const u32 bandwidth)
784{ 797{
785 struct tuner_simple_priv *priv = fe->tuner_priv; 798 struct tuner_simple_priv *priv = fe->tuner_priv;
786 799
787 switch (priv->type) { 800 switch (priv->type) {
788 case TUNER_PHILIPS_FMD1216ME_MK3: 801 case TUNER_PHILIPS_FMD1216ME_MK3:
789 case TUNER_PHILIPS_FMD1216MEX_MK3: 802 case TUNER_PHILIPS_FMD1216MEX_MK3:
790 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ && 803 if (bandwidth == 8000000 &&
791 params->frequency >= 158870000) 804 frequency >= 158870000)
792 buf[3] |= 0x08; 805 buf[3] |= 0x08;
793 break; 806 break;
794 case TUNER_PHILIPS_TD1316: 807 case TUNER_PHILIPS_TD1316:
795 /* determine band */ 808 /* determine band */
796 buf[3] |= (params->frequency < 161000000) ? 1 : 809 buf[3] |= (frequency < 161000000) ? 1 :
797 (params->frequency < 444000000) ? 2 : 4; 810 (frequency < 444000000) ? 2 : 4;
798 811
799 /* setup PLL filter */ 812 /* setup PLL filter */
800 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) 813 if (bandwidth == 8000000)
801 buf[3] |= 1 << 3; 814 buf[3] |= 1 << 3;
802 break; 815 break;
803 case TUNER_PHILIPS_TUV1236D: 816 case TUNER_PHILIPS_TUV1236D:
@@ -808,12 +821,11 @@ static void simple_set_dvb(struct dvb_frontend *fe, u8 *buf,
808 if (dtv_input[priv->nr]) 821 if (dtv_input[priv->nr])
809 new_rf = dtv_input[priv->nr]; 822 new_rf = dtv_input[priv->nr];
810 else 823 else
811 switch (params->u.vsb.modulation) { 824 switch (delsys) {
812 case QAM_64: 825 case SYS_DVBC_ANNEX_B:
813 case QAM_256:
814 new_rf = 1; 826 new_rf = 1;
815 break; 827 break;
816 case VSB_8: 828 case SYS_ATSC:
817 default: 829 default:
818 new_rf = 0; 830 new_rf = 0;
819 break; 831 break;
@@ -827,7 +839,9 @@ static void simple_set_dvb(struct dvb_frontend *fe, u8 *buf,
827} 839}
828 840
829static u32 simple_dvb_configure(struct dvb_frontend *fe, u8 *buf, 841static u32 simple_dvb_configure(struct dvb_frontend *fe, u8 *buf,
830 const struct dvb_frontend_parameters *params) 842 const u32 delsys,
843 const u32 freq,
844 const u32 bw)
831{ 845{
832 /* This function returns the tuned frequency on success, 0 on error */ 846 /* This function returns the tuned frequency on success, 0 on error */
833 struct tuner_simple_priv *priv = fe->tuner_priv; 847 struct tuner_simple_priv *priv = fe->tuner_priv;
@@ -836,7 +850,7 @@ static u32 simple_dvb_configure(struct dvb_frontend *fe, u8 *buf,
836 u8 config, cb; 850 u8 config, cb;
837 u32 div; 851 u32 div;
838 int ret; 852 int ret;
839 unsigned frequency = params->frequency / 62500; 853 u32 frequency = freq / 62500;
840 854
841 if (!tun->stepsize) { 855 if (!tun->stepsize) {
842 /* tuner-core was loaded before the digital tuner was 856 /* tuner-core was loaded before the digital tuner was
@@ -860,7 +874,7 @@ static u32 simple_dvb_configure(struct dvb_frontend *fe, u8 *buf,
860 buf[2] = config; 874 buf[2] = config;
861 buf[3] = cb; 875 buf[3] = cb;
862 876
863 simple_set_dvb(fe, buf, params); 877 simple_set_dvb(fe, buf, delsys, freq, bw);
864 878
865 tuner_dbg("%s: div=%d | buf=0x%02x,0x%02x,0x%02x,0x%02x\n", 879 tuner_dbg("%s: div=%d | buf=0x%02x,0x%02x,0x%02x,0x%02x\n",
866 tun->name, div, buf[0], buf[1], buf[2], buf[3]); 880 tun->name, div, buf[0], buf[1], buf[2], buf[3]);
@@ -870,32 +884,37 @@ static u32 simple_dvb_configure(struct dvb_frontend *fe, u8 *buf,
870} 884}
871 885
872static int simple_dvb_calc_regs(struct dvb_frontend *fe, 886static int simple_dvb_calc_regs(struct dvb_frontend *fe,
873 struct dvb_frontend_parameters *params,
874 u8 *buf, int buf_len) 887 u8 *buf, int buf_len)
875{ 888{
889 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
890 u32 delsys = c->delivery_system;
891 u32 bw = c->bandwidth_hz;
876 struct tuner_simple_priv *priv = fe->tuner_priv; 892 struct tuner_simple_priv *priv = fe->tuner_priv;
877 u32 frequency; 893 u32 frequency;
878 894
879 if (buf_len < 5) 895 if (buf_len < 5)
880 return -EINVAL; 896 return -EINVAL;
881 897
882 frequency = simple_dvb_configure(fe, buf+1, params); 898 frequency = simple_dvb_configure(fe, buf+1, delsys, c->frequency, bw);
883 if (frequency == 0) 899 if (frequency == 0)
884 return -EINVAL; 900 return -EINVAL;
885 901
886 buf[0] = priv->i2c_props.addr; 902 buf[0] = priv->i2c_props.addr;
887 903
888 priv->frequency = frequency; 904 priv->frequency = frequency;
889 priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? 905 priv->bandwidth = c->bandwidth_hz;
890 params->u.ofdm.bandwidth : 0;
891 906
892 return 5; 907 return 5;
893} 908}
894 909
895static int simple_dvb_set_params(struct dvb_frontend *fe, 910static int simple_dvb_set_params(struct dvb_frontend *fe)
896 struct dvb_frontend_parameters *params)
897{ 911{
912 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
913 u32 delsys = c->delivery_system;
914 u32 bw = c->bandwidth_hz;
915 u32 freq = c->frequency;
898 struct tuner_simple_priv *priv = fe->tuner_priv; 916 struct tuner_simple_priv *priv = fe->tuner_priv;
917 u32 frequency;
899 u32 prev_freq, prev_bw; 918 u32 prev_freq, prev_bw;
900 int ret; 919 int ret;
901 u8 buf[5]; 920 u8 buf[5];
@@ -906,9 +925,14 @@ static int simple_dvb_set_params(struct dvb_frontend *fe,
906 prev_freq = priv->frequency; 925 prev_freq = priv->frequency;
907 prev_bw = priv->bandwidth; 926 prev_bw = priv->bandwidth;
908 927
909 ret = simple_dvb_calc_regs(fe, params, buf, 5); 928 frequency = simple_dvb_configure(fe, buf+1, delsys, freq, bw);
910 if (ret != 5) 929 if (frequency == 0)
911 goto fail; 930 return -EINVAL;
931
932 buf[0] = priv->i2c_props.addr;
933
934 priv->frequency = frequency;
935 priv->bandwidth = bw;
912 936
913 /* put analog demod in standby when tuning digital */ 937 /* put analog demod in standby when tuning digital */
914 if (fe->ops.analog_ops.standby) 938 if (fe->ops.analog_ops.standby)
diff --git a/drivers/media/common/tuners/tuner-xc2028.c b/drivers/media/common/tuners/tuner-xc2028.c
index 3acbaa04e1b3..27555995f7e4 100644
--- a/drivers/media/common/tuners/tuner-xc2028.c
+++ b/drivers/media/common/tuners/tuner-xc2028.c
@@ -311,7 +311,7 @@ static int load_all_firmwares(struct dvb_frontend *fe)
311 n_array, fname, name, 311 n_array, fname, name,
312 priv->firm_version >> 8, priv->firm_version & 0xff); 312 priv->firm_version >> 8, priv->firm_version & 0xff);
313 313
314 priv->firm = kzalloc(sizeof(*priv->firm) * n_array, GFP_KERNEL); 314 priv->firm = kcalloc(n_array, sizeof(*priv->firm), GFP_KERNEL);
315 if (priv->firm == NULL) { 315 if (priv->firm == NULL) {
316 tuner_err("Not enough memory to load firmware file.\n"); 316 tuner_err("Not enough memory to load firmware file.\n");
317 rc = -ENOMEM; 317 rc = -ENOMEM;
@@ -891,7 +891,7 @@ static int xc2028_signal(struct dvb_frontend *fe, u16 *strength)
891 891
892 /* Frequency is locked */ 892 /* Frequency is locked */
893 if (frq_lock == 1) 893 if (frq_lock == 1)
894 signal = 32768; 894 signal = 1 << 11;
895 895
896 /* Get SNR of the video signal */ 896 /* Get SNR of the video signal */
897 rc = xc2028_get_reg(priv, 0x0040, &signal); 897 rc = xc2028_get_reg(priv, 0x0040, &signal);
@@ -962,14 +962,24 @@ static int generic_set_freq(struct dvb_frontend *fe, u32 freq /* in HZ */,
962 * For DTV 7/8, the firmware uses BW = 8000, so it needs a 962 * For DTV 7/8, the firmware uses BW = 8000, so it needs a
963 * further adjustment to get the frequency center on VHF 963 * further adjustment to get the frequency center on VHF
964 */ 964 */
965
966 /*
967 * The firmware DTV78 used to work fine in UHF band (8 MHz
968 * bandwidth) but not at all in VHF band (7 MHz bandwidth).
969 * The real problem was connected to the formula used to
970 * calculate the center frequency offset in VHF band.
971 * In fact, removing the 500KHz adjustment fixed the problem.
972 * This is coherent to what was implemented for the DTV7
973 * firmware.
974 * In the end, now the center frequency is the same for all 3
975 * firmwares (DTV7, DTV8, DTV78) and doesn't depend on channel
976 * bandwidth.
977 */
978
965 if (priv->cur_fw.type & DTV6) 979 if (priv->cur_fw.type & DTV6)
966 offset = 1750000; 980 offset = 1750000;
967 else if (priv->cur_fw.type & DTV7) 981 else /* DTV7 or DTV8 or DTV78 */
968 offset = 2250000;
969 else /* DTV8 or DTV78 */
970 offset = 2750000; 982 offset = 2750000;
971 if ((priv->cur_fw.type & DTV78) && freq < 470000000)
972 offset -= 500000;
973 983
974 /* 984 /*
975 * xc3028 additional "magic" 985 * xc3028 additional "magic"
@@ -979,17 +989,13 @@ static int generic_set_freq(struct dvb_frontend *fe, u32 freq /* in HZ */,
979 * newer firmwares 989 * newer firmwares
980 */ 990 */
981 991
982#if 1
983 /* 992 /*
984 * The proper adjustment would be to do it at s-code table. 993 * The proper adjustment would be to do it at s-code table.
985 * However, this didn't work, as reported by 994 * However, this didn't work, as reported by
986 * Robert Lowery <rglowery@exemail.com.au> 995 * Robert Lowery <rglowery@exemail.com.au>
987 */ 996 */
988 997
989 if (priv->cur_fw.type & DTV7) 998#if 0
990 offset += 500000;
991
992#else
993 /* 999 /*
994 * Still need tests for XC3028L (firmware 3.2 or upper) 1000 * Still need tests for XC3028L (firmware 3.2 or upper)
995 * So, for now, let's just comment the per-firmware 1001 * So, for now, let's just comment the per-firmware
@@ -1084,68 +1090,28 @@ static int xc2028_set_analog_freq(struct dvb_frontend *fe,
1084 V4L2_TUNER_ANALOG_TV, type, p->std, 0); 1090 V4L2_TUNER_ANALOG_TV, type, p->std, 0);
1085} 1091}
1086 1092
1087static int xc2028_set_params(struct dvb_frontend *fe, 1093static int xc2028_set_params(struct dvb_frontend *fe)
1088 struct dvb_frontend_parameters *p)
1089{ 1094{
1095 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1096 u32 delsys = c->delivery_system;
1097 u32 bw = c->bandwidth_hz;
1090 struct xc2028_data *priv = fe->tuner_priv; 1098 struct xc2028_data *priv = fe->tuner_priv;
1091 unsigned int type=0; 1099 unsigned int type=0;
1092 fe_bandwidth_t bw = BANDWIDTH_8_MHZ;
1093 u16 demod = 0; 1100 u16 demod = 0;
1094 1101
1095 tuner_dbg("%s called\n", __func__); 1102 tuner_dbg("%s called\n", __func__);
1096 1103
1097 switch(fe->ops.info.type) { 1104 switch (delsys) {
1098 case FE_OFDM: 1105 case SYS_DVBT:
1099 bw = p->u.ofdm.bandwidth; 1106 case SYS_DVBT2:
1100 /* 1107 /*
1101 * The only countries with 6MHz seem to be Taiwan/Uruguay. 1108 * The only countries with 6MHz seem to be Taiwan/Uruguay.
1102 * Both seem to require QAM firmware for OFDM decoding 1109 * Both seem to require QAM firmware for OFDM decoding
1103 * Tested in Taiwan by Terry Wu <terrywu2009@gmail.com> 1110 * Tested in Taiwan by Terry Wu <terrywu2009@gmail.com>
1104 */ 1111 */
1105 if (bw == BANDWIDTH_6_MHZ) 1112 if (bw <= 6000000)
1106 type |= QAM; 1113 type |= QAM;
1107 break;
1108 case FE_ATSC:
1109 bw = BANDWIDTH_6_MHZ;
1110 /* The only ATSC firmware (at least on v2.7) is D2633 */
1111 type |= ATSC | D2633;
1112 break;
1113 /* DVB-S and pure QAM (FE_QAM) are not supported */
1114 default:
1115 return -EINVAL;
1116 }
1117
1118 switch (bw) {
1119 case BANDWIDTH_8_MHZ:
1120 if (p->frequency < 470000000)
1121 priv->ctrl.vhfbw7 = 0;
1122 else
1123 priv->ctrl.uhfbw8 = 1;
1124 type |= (priv->ctrl.vhfbw7 && priv->ctrl.uhfbw8) ? DTV78 : DTV8;
1125 type |= F8MHZ;
1126 break;
1127 case BANDWIDTH_7_MHZ:
1128 if (p->frequency < 470000000)
1129 priv->ctrl.vhfbw7 = 1;
1130 else
1131 priv->ctrl.uhfbw8 = 0;
1132 type |= (priv->ctrl.vhfbw7 && priv->ctrl.uhfbw8) ? DTV78 : DTV7;
1133 type |= F8MHZ;
1134 break;
1135 case BANDWIDTH_6_MHZ:
1136 type |= DTV6;
1137 priv->ctrl.vhfbw7 = 0;
1138 priv->ctrl.uhfbw8 = 0;
1139 break;
1140 default:
1141 tuner_err("error: bandwidth not supported.\n");
1142 };
1143 1114
1144 /*
1145 Selects between D2633 or D2620 firmware.
1146 It doesn't make sense for ATSC, since it should be D2633 on all cases
1147 */
1148 if (fe->ops.info.type != FE_ATSC) {
1149 switch (priv->ctrl.type) { 1115 switch (priv->ctrl.type) {
1150 case XC2028_D2633: 1116 case XC2028_D2633:
1151 type |= D2633; 1117 type |= D2633;
@@ -1161,6 +1127,34 @@ static int xc2028_set_params(struct dvb_frontend *fe,
1161 else 1127 else
1162 type |= D2620; 1128 type |= D2620;
1163 } 1129 }
1130 break;
1131 case SYS_ATSC:
1132 /* The only ATSC firmware (at least on v2.7) is D2633 */
1133 type |= ATSC | D2633;
1134 break;
1135 /* DVB-S and pure QAM (FE_QAM) are not supported */
1136 default:
1137 return -EINVAL;
1138 }
1139
1140 if (bw <= 6000000) {
1141 type |= DTV6;
1142 priv->ctrl.vhfbw7 = 0;
1143 priv->ctrl.uhfbw8 = 0;
1144 } else if (bw <= 7000000) {
1145 if (c->frequency < 470000000)
1146 priv->ctrl.vhfbw7 = 1;
1147 else
1148 priv->ctrl.uhfbw8 = 0;
1149 type |= (priv->ctrl.vhfbw7 && priv->ctrl.uhfbw8) ? DTV78 : DTV7;
1150 type |= F8MHZ;
1151 } else {
1152 if (c->frequency < 470000000)
1153 priv->ctrl.vhfbw7 = 0;
1154 else
1155 priv->ctrl.uhfbw8 = 1;
1156 type |= (priv->ctrl.vhfbw7 && priv->ctrl.uhfbw8) ? DTV78 : DTV8;
1157 type |= F8MHZ;
1164 } 1158 }
1165 1159
1166 /* All S-code tables need a 200kHz shift */ 1160 /* All S-code tables need a 200kHz shift */
@@ -1185,7 +1179,7 @@ static int xc2028_set_params(struct dvb_frontend *fe,
1185 */ 1179 */
1186 } 1180 }
1187 1181
1188 return generic_set_freq(fe, p->frequency, 1182 return generic_set_freq(fe, c->frequency,
1189 V4L2_TUNER_DIGITAL_TV, type, 0, demod); 1183 V4L2_TUNER_DIGITAL_TV, type, 0, demod);
1190} 1184}
1191 1185
diff --git a/drivers/media/common/tuners/xc4000.c b/drivers/media/common/tuners/xc4000.c
index 634f4d9b6c63..d218c1d68c33 100644
--- a/drivers/media/common/tuners/xc4000.c
+++ b/drivers/media/common/tuners/xc4000.c
@@ -758,7 +758,7 @@ static int xc4000_fwupload(struct dvb_frontend *fe)
758 n_array, fname, name, 758 n_array, fname, name,
759 priv->firm_version >> 8, priv->firm_version & 0xff); 759 priv->firm_version >> 8, priv->firm_version & 0xff);
760 760
761 priv->firm = kzalloc(sizeof(*priv->firm) * n_array, GFP_KERNEL); 761 priv->firm = kcalloc(n_array, sizeof(*priv->firm), GFP_KERNEL);
762 if (priv->firm == NULL) { 762 if (priv->firm == NULL) {
763 printk(KERN_ERR "Not enough memory to load firmware file.\n"); 763 printk(KERN_ERR "Not enough memory to load firmware file.\n");
764 rc = -ENOMEM; 764 rc = -ENOMEM;
@@ -1121,83 +1121,62 @@ static void xc_debug_dump(struct xc4000_priv *priv)
1121 dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality); 1121 dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality);
1122} 1122}
1123 1123
1124static int xc4000_set_params(struct dvb_frontend *fe, 1124static int xc4000_set_params(struct dvb_frontend *fe)
1125 struct dvb_frontend_parameters *params)
1126{ 1125{
1126 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1127 u32 delsys = c->delivery_system;
1128 u32 bw = c->bandwidth_hz;
1127 struct xc4000_priv *priv = fe->tuner_priv; 1129 struct xc4000_priv *priv = fe->tuner_priv;
1128 unsigned int type; 1130 unsigned int type;
1129 int ret = -EREMOTEIO; 1131 int ret = -EREMOTEIO;
1130 1132
1131 dprintk(1, "%s() frequency=%d (Hz)\n", __func__, params->frequency); 1133 dprintk(1, "%s() frequency=%d (Hz)\n", __func__, c->frequency);
1132 1134
1133 mutex_lock(&priv->lock); 1135 mutex_lock(&priv->lock);
1134 1136
1135 if (fe->ops.info.type == FE_ATSC) { 1137 switch (delsys) {
1136 dprintk(1, "%s() ATSC\n", __func__); 1138 case SYS_ATSC:
1137 switch (params->u.vsb.modulation) { 1139 dprintk(1, "%s() VSB modulation\n", __func__);
1138 case VSB_8: 1140 priv->rf_mode = XC_RF_MODE_AIR;
1139 case VSB_16: 1141 priv->freq_hz = c->frequency - 1750000;
1140 dprintk(1, "%s() VSB modulation\n", __func__); 1142 priv->video_standard = XC4000_DTV6;
1141 priv->rf_mode = XC_RF_MODE_AIR; 1143 type = DTV6;
1142 priv->freq_hz = params->frequency - 1750000; 1144 break;
1143 priv->bandwidth = BANDWIDTH_6_MHZ; 1145 case SYS_DVBC_ANNEX_B:
1144 priv->video_standard = XC4000_DTV6; 1146 dprintk(1, "%s() QAM modulation\n", __func__);
1145 type = DTV6; 1147 priv->rf_mode = XC_RF_MODE_CABLE;
1146 break; 1148 priv->freq_hz = c->frequency - 1750000;
1147 case QAM_64: 1149 priv->video_standard = XC4000_DTV6;
1148 case QAM_256: 1150 type = DTV6;
1149 case QAM_AUTO: 1151 break;
1150 dprintk(1, "%s() QAM modulation\n", __func__); 1152 case SYS_DVBT:
1151 priv->rf_mode = XC_RF_MODE_CABLE; 1153 case SYS_DVBT2:
1152 priv->freq_hz = params->frequency - 1750000;
1153 priv->bandwidth = BANDWIDTH_6_MHZ;
1154 priv->video_standard = XC4000_DTV6;
1155 type = DTV6;
1156 break;
1157 default:
1158 ret = -EINVAL;
1159 goto fail;
1160 }
1161 } else if (fe->ops.info.type == FE_OFDM) {
1162 dprintk(1, "%s() OFDM\n", __func__); 1154 dprintk(1, "%s() OFDM\n", __func__);
1163 switch (params->u.ofdm.bandwidth) { 1155 if (bw == 0) {
1164 case BANDWIDTH_6_MHZ: 1156 if (c->frequency < 400000000) {
1165 priv->bandwidth = BANDWIDTH_6_MHZ; 1157 priv->freq_hz = c->frequency - 2250000;
1158 } else {
1159 priv->freq_hz = c->frequency - 2750000;
1160 }
1161 priv->video_standard = XC4000_DTV7_8;
1162 type = DTV78;
1163 } else if (bw <= 6000000) {
1166 priv->video_standard = XC4000_DTV6; 1164 priv->video_standard = XC4000_DTV6;
1167 priv->freq_hz = params->frequency - 1750000; 1165 priv->freq_hz = c->frequency - 1750000;
1168 type = DTV6; 1166 type = DTV6;
1169 break; 1167 } else if (bw <= 7000000) {
1170 case BANDWIDTH_7_MHZ:
1171 priv->bandwidth = BANDWIDTH_7_MHZ;
1172 priv->video_standard = XC4000_DTV7; 1168 priv->video_standard = XC4000_DTV7;
1173 priv->freq_hz = params->frequency - 2250000; 1169 priv->freq_hz = c->frequency - 2250000;
1174 type = DTV7; 1170 type = DTV7;
1175 break; 1171 } else {
1176 case BANDWIDTH_8_MHZ:
1177 priv->bandwidth = BANDWIDTH_8_MHZ;
1178 priv->video_standard = XC4000_DTV8; 1172 priv->video_standard = XC4000_DTV8;
1179 priv->freq_hz = params->frequency - 2750000; 1173 priv->freq_hz = c->frequency - 2750000;
1180 type = DTV8; 1174 type = DTV8;
1181 break;
1182 case BANDWIDTH_AUTO:
1183 if (params->frequency < 400000000) {
1184 priv->bandwidth = BANDWIDTH_7_MHZ;
1185 priv->freq_hz = params->frequency - 2250000;
1186 } else {
1187 priv->bandwidth = BANDWIDTH_8_MHZ;
1188 priv->freq_hz = params->frequency - 2750000;
1189 }
1190 priv->video_standard = XC4000_DTV7_8;
1191 type = DTV78;
1192 break;
1193 default:
1194 printk(KERN_ERR "xc4000 bandwidth not set!\n");
1195 ret = -EINVAL;
1196 goto fail;
1197 } 1175 }
1198 priv->rf_mode = XC_RF_MODE_AIR; 1176 priv->rf_mode = XC_RF_MODE_AIR;
1199 } else { 1177 break;
1200 printk(KERN_ERR "xc4000 modulation type not supported!\n"); 1178 default:
1179 printk(KERN_ERR "xc4000 delivery system not supported!\n");
1201 ret = -EINVAL; 1180 ret = -EINVAL;
1202 goto fail; 1181 goto fail;
1203 } 1182 }
@@ -1209,6 +1188,8 @@ static int xc4000_set_params(struct dvb_frontend *fe,
1209 if (check_firmware(fe, type, 0, priv->if_khz) != 0) 1188 if (check_firmware(fe, type, 0, priv->if_khz) != 0)
1210 goto fail; 1189 goto fail;
1211 1190
1191 priv->bandwidth = c->bandwidth_hz;
1192
1212 ret = xc_set_signal_source(priv, priv->rf_mode); 1193 ret = xc_set_signal_source(priv, priv->rf_mode);
1213 if (ret != 0) { 1194 if (ret != 0) {
1214 printk(KERN_ERR "xc4000: xc_set_signal_source(%d) failed\n", 1195 printk(KERN_ERR "xc4000: xc_set_signal_source(%d) failed\n",
@@ -1605,7 +1586,7 @@ struct dvb_frontend *xc4000_attach(struct dvb_frontend *fe,
1605 break; 1586 break;
1606 case 1: 1587 case 1:
1607 /* new tuner instance */ 1588 /* new tuner instance */
1608 priv->bandwidth = BANDWIDTH_6_MHZ; 1589 priv->bandwidth = 6000000;
1609 /* set default configuration */ 1590 /* set default configuration */
1610 priv->if_khz = 4560; 1591 priv->if_khz = 4560;
1611 priv->default_pm = 0; 1592 priv->default_pm = 0;
diff --git a/drivers/media/common/tuners/xc5000.c b/drivers/media/common/tuners/xc5000.c
index aa1b2e844d32..296df05b8cda 100644
--- a/drivers/media/common/tuners/xc5000.c
+++ b/drivers/media/common/tuners/xc5000.c
@@ -628,20 +628,13 @@ static void xc_debug_dump(struct xc5000_priv *priv)
628 dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality); 628 dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality);
629} 629}
630 630
631/* 631static int xc5000_set_params(struct dvb_frontend *fe)
632 * As defined on EN 300 429, the DVB-C roll-off factor is 0.15.
633 * So, the amount of the needed bandwith is given by:
634 * Bw = Symbol_rate * (1 + 0.15)
635 * As such, the maximum symbol rate supported by 6 MHz is given by:
636 * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds
637 */
638#define MAX_SYMBOL_RATE_6MHz 5217391
639
640static int xc5000_set_params(struct dvb_frontend *fe,
641 struct dvb_frontend_parameters *params)
642{ 632{
633 int ret, b;
643 struct xc5000_priv *priv = fe->tuner_priv; 634 struct xc5000_priv *priv = fe->tuner_priv;
644 int ret; 635 u32 bw = fe->dtv_property_cache.bandwidth_hz;
636 u32 freq = fe->dtv_property_cache.frequency;
637 u32 delsys = fe->dtv_property_cache.delivery_system;
645 638
646 if (xc5000_is_firmware_loaded(fe) != XC_RESULT_SUCCESS) { 639 if (xc5000_is_firmware_loaded(fe) != XC_RESULT_SUCCESS) {
647 if (xc_load_fw_and_init_tuner(fe) != XC_RESULT_SUCCESS) { 640 if (xc_load_fw_and_init_tuner(fe) != XC_RESULT_SUCCESS) {
@@ -650,88 +643,69 @@ static int xc5000_set_params(struct dvb_frontend *fe,
650 } 643 }
651 } 644 }
652 645
653 dprintk(1, "%s() frequency=%d (Hz)\n", __func__, params->frequency); 646 dprintk(1, "%s() frequency=%d (Hz)\n", __func__, freq);
654 647
655 if (fe->ops.info.type == FE_ATSC) { 648 switch (delsys) {
656 dprintk(1, "%s() ATSC\n", __func__); 649 case SYS_ATSC:
657 switch (params->u.vsb.modulation) { 650 dprintk(1, "%s() VSB modulation\n", __func__);
658 case VSB_8: 651 priv->rf_mode = XC_RF_MODE_AIR;
659 case VSB_16: 652 priv->freq_hz = freq - 1750000;
660 dprintk(1, "%s() VSB modulation\n", __func__); 653 priv->video_standard = DTV6;
661 priv->rf_mode = XC_RF_MODE_AIR; 654 break;
662 priv->freq_hz = params->frequency - 1750000; 655 case SYS_DVBC_ANNEX_B:
663 priv->bandwidth = BANDWIDTH_6_MHZ; 656 dprintk(1, "%s() QAM modulation\n", __func__);
664 priv->video_standard = DTV6; 657 priv->rf_mode = XC_RF_MODE_CABLE;
665 break; 658 priv->freq_hz = freq - 1750000;
666 case QAM_64: 659 priv->video_standard = DTV6;
667 case QAM_256: 660 break;
668 case QAM_AUTO: 661 case SYS_DVBT:
669 dprintk(1, "%s() QAM modulation\n", __func__); 662 case SYS_DVBT2:
670 priv->rf_mode = XC_RF_MODE_CABLE;
671 priv->freq_hz = params->frequency - 1750000;
672 priv->bandwidth = BANDWIDTH_6_MHZ;
673 priv->video_standard = DTV6;
674 break;
675 default:
676 return -EINVAL;
677 }
678 } else if (fe->ops.info.type == FE_OFDM) {
679 dprintk(1, "%s() OFDM\n", __func__); 663 dprintk(1, "%s() OFDM\n", __func__);
680 switch (params->u.ofdm.bandwidth) { 664 switch (bw) {
681 case BANDWIDTH_6_MHZ: 665 case 6000000:
682 priv->bandwidth = BANDWIDTH_6_MHZ;
683 priv->video_standard = DTV6; 666 priv->video_standard = DTV6;
684 priv->freq_hz = params->frequency - 1750000; 667 priv->freq_hz = freq - 1750000;
685 break; 668 break;
686 case BANDWIDTH_7_MHZ: 669 case 7000000:
687 printk(KERN_ERR "xc5000 bandwidth 7MHz not supported\n"); 670 priv->video_standard = DTV7;
688 return -EINVAL; 671 priv->freq_hz = freq - 2250000;
689 case BANDWIDTH_8_MHZ: 672 break;
690 priv->bandwidth = BANDWIDTH_8_MHZ; 673 case 8000000:
691 priv->video_standard = DTV8; 674 priv->video_standard = DTV8;
692 priv->freq_hz = params->frequency - 2750000; 675 priv->freq_hz = freq - 2750000;
693 break; 676 break;
694 default: 677 default:
695 printk(KERN_ERR "xc5000 bandwidth not set!\n"); 678 printk(KERN_ERR "xc5000 bandwidth not set!\n");
696 return -EINVAL; 679 return -EINVAL;
697 } 680 }
698 priv->rf_mode = XC_RF_MODE_AIR; 681 priv->rf_mode = XC_RF_MODE_AIR;
699 } else if (fe->ops.info.type == FE_QAM) { 682 case SYS_DVBC_ANNEX_A:
700 switch (params->u.qam.modulation) { 683 case SYS_DVBC_ANNEX_C:
701 case QAM_256: 684 dprintk(1, "%s() QAM modulation\n", __func__);
702 case QAM_AUTO: 685 priv->rf_mode = XC_RF_MODE_CABLE;
703 case QAM_16: 686 if (bw <= 6000000) {
704 case QAM_32: 687 priv->video_standard = DTV6;
705 case QAM_64: 688 priv->freq_hz = freq - 1750000;
706 case QAM_128: 689 b = 6;
707 dprintk(1, "%s() QAM modulation\n", __func__); 690 } else if (bw <= 7000000) {
708 priv->rf_mode = XC_RF_MODE_CABLE; 691 priv->video_standard = DTV7;
709 /* 692 priv->freq_hz = freq - 2250000;
710 * Using a 8MHz bandwidth sometimes fail 693 b = 7;
711 * with 6MHz-spaced channels, due to inter-carrier 694 } else {
712 * interference. So, use DTV6 firmware 695 priv->video_standard = DTV7_8;
713 */ 696 priv->freq_hz = freq - 2750000;
714 if (params->u.qam.symbol_rate <= MAX_SYMBOL_RATE_6MHz) { 697 b = 8;
715 priv->bandwidth = BANDWIDTH_6_MHZ;
716 priv->video_standard = DTV6;
717 priv->freq_hz = params->frequency - 1750000;
718 } else {
719 priv->bandwidth = BANDWIDTH_8_MHZ;
720 priv->video_standard = DTV7_8;
721 priv->freq_hz = params->frequency - 2750000;
722 }
723 break;
724 default:
725 dprintk(1, "%s() Unsupported QAM type\n", __func__);
726 return -EINVAL;
727 } 698 }
728 } else { 699 dprintk(1, "%s() Bandwidth %dMHz (%d)\n", __func__,
729 printk(KERN_ERR "xc5000 modulation type not supported!\n"); 700 b, bw);
701 break;
702 default:
703 printk(KERN_ERR "xc5000: delivery system is not supported!\n");
730 return -EINVAL; 704 return -EINVAL;
731 } 705 }
732 706
733 dprintk(1, "%s() frequency=%d (compensated)\n", 707 dprintk(1, "%s() frequency=%d (compensated to %d)\n",
734 __func__, priv->freq_hz); 708 __func__, freq, priv->freq_hz);
735 709
736 ret = xc_SetSignalSource(priv, priv->rf_mode); 710 ret = xc_SetSignalSource(priv, priv->rf_mode);
737 if (ret != XC_RESULT_SUCCESS) { 711 if (ret != XC_RESULT_SUCCESS) {
@@ -763,6 +737,8 @@ static int xc5000_set_params(struct dvb_frontend *fe,
763 if (debug) 737 if (debug)
764 xc_debug_dump(priv); 738 xc_debug_dump(priv);
765 739
740 priv->bandwidth = bw;
741
766 return 0; 742 return 0;
767} 743}
768 744
@@ -968,6 +944,14 @@ static int xc5000_get_frequency(struct dvb_frontend *fe, u32 *freq)
968 return 0; 944 return 0;
969} 945}
970 946
947static int xc5000_get_if_frequency(struct dvb_frontend *fe, u32 *freq)
948{
949 struct xc5000_priv *priv = fe->tuner_priv;
950 dprintk(1, "%s()\n", __func__);
951 *freq = priv->if_khz * 1000;
952 return 0;
953}
954
971static int xc5000_get_bandwidth(struct dvb_frontend *fe, u32 *bw) 955static int xc5000_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
972{ 956{
973 struct xc5000_priv *priv = fe->tuner_priv; 957 struct xc5000_priv *priv = fe->tuner_priv;
@@ -1108,6 +1092,7 @@ static const struct dvb_tuner_ops xc5000_tuner_ops = {
1108 .set_params = xc5000_set_params, 1092 .set_params = xc5000_set_params,
1109 .set_analog_params = xc5000_set_analog_params, 1093 .set_analog_params = xc5000_set_analog_params,
1110 .get_frequency = xc5000_get_frequency, 1094 .get_frequency = xc5000_get_frequency,
1095 .get_if_frequency = xc5000_get_if_frequency,
1111 .get_bandwidth = xc5000_get_bandwidth, 1096 .get_bandwidth = xc5000_get_bandwidth,
1112 .get_status = xc5000_get_status 1097 .get_status = xc5000_get_status
1113}; 1098};
@@ -1135,7 +1120,7 @@ struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe,
1135 break; 1120 break;
1136 case 1: 1121 case 1:
1137 /* new tuner instance */ 1122 /* new tuner instance */
1138 priv->bandwidth = BANDWIDTH_6_MHZ; 1123 priv->bandwidth = 6000000;
1139 fe->tuner_priv = priv; 1124 fe->tuner_priv = priv;
1140 break; 1125 break;
1141 default: 1126 default:
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 08:57:51 -0500