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-rw-r--r--drivers/media/common/tuners/mxl5005s.c926
1 files changed, 603 insertions, 323 deletions
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index d8885484cfbd..7e687171301b 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -24,6 +24,270 @@
24 24
25#include "mxl5005s.h" 25#include "mxl5005s.h"
26 26
27static int debug;
28
29#define dprintk(level, arg...) do { \
30 if (debug >= level) \
31 printk(arg); \
32 } while (0)
33
34#define TUNER_REGS_NUM 104
35#define INITCTRL_NUM 40
36
37#ifdef _MXL_PRODUCTION
38#define CHCTRL_NUM 39
39#else
40#define CHCTRL_NUM 36
41#endif
42
43#define MXLCTRL_NUM 189
44#define MASTER_CONTROL_ADDR 9
45
46/* Enumeration of AGC Mode */
47typedef enum
48{
49 MXL_DUAL_AGC = 0,
50 MXL_SINGLE_AGC
51} AGC_Mode;
52
53/* Enumeration of Master Control Register State */
54typedef enum
55{
56 MC_LOAD_START = 1,
57 MC_POWER_DOWN,
58 MC_SYNTH_RESET,
59 MC_SEQ_OFF
60} Master_Control_State;
61
62/* Enumeration of MXL5005 Tuner Mode */
63typedef enum
64{
65 MXL_ANALOG_MODE = 0,
66 MXL_DIGITAL_MODE
67} Tuner_Mode;
68
69/* Enumeration of MXL5005 Tuner IF Mode */
70typedef enum
71{
72 MXL_ZERO_IF = 0,
73 MXL_LOW_IF
74} Tuner_IF_Mode;
75
76/* Enumeration of MXL5005 Tuner Clock Out Mode */
77typedef enum
78{
79 MXL_CLOCK_OUT_DISABLE = 0,
80 MXL_CLOCK_OUT_ENABLE
81} Tuner_Clock_Out;
82
83/* Enumeration of MXL5005 Tuner Div Out Mode */
84typedef enum
85{
86 MXL_DIV_OUT_1 = 0,
87 MXL_DIV_OUT_4
88
89} Tuner_Div_Out;
90
91/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */
92typedef enum
93{
94 MXL_CAP_SEL_DISABLE = 0,
95 MXL_CAP_SEL_ENABLE
96
97} Tuner_Cap_Select;
98
99/* Enumeration of MXL5005 Tuner RSSI Mode */
100typedef enum
101{
102 MXL_RSSI_DISABLE = 0,
103 MXL_RSSI_ENABLE
104
105} Tuner_RSSI;
106
107/* Enumeration of MXL5005 Tuner Modulation Type */
108typedef enum
109{
110 MXL_DEFAULT_MODULATION = 0,
111 MXL_DVBT,
112 MXL_ATSC,
113 MXL_QAM,
114 MXL_ANALOG_CABLE,
115 MXL_ANALOG_OTA
116} Tuner_Modu_Type;
117
118/* Enumeration of MXL5005 Tuner Tracking Filter Type */
119typedef enum
120{
121 MXL_TF_DEFAULT = 0,
122 MXL_TF_OFF,
123 MXL_TF_C,
124 MXL_TF_C_H,
125 MXL_TF_D,
126 MXL_TF_D_L,
127 MXL_TF_E,
128 MXL_TF_F,
129 MXL_TF_E_2,
130 MXL_TF_E_NA,
131 MXL_TF_G
132} Tuner_TF_Type;
133
134/* MXL5005 Tuner Register Struct */
135typedef struct _TunerReg_struct
136{
137 u16 Reg_Num; /* Tuner Register Address */
138 u16 Reg_Val; /* Current sofware programmed value waiting to be writen */
139} TunerReg_struct;
140
141typedef enum
142{
143 /* Initialization Control Names */
144 DN_IQTN_AMP_CUT = 1, /* 1 */
145 BB_MODE, /* 2 */
146 BB_BUF, /* 3 */
147 BB_BUF_OA, /* 4 */
148 BB_ALPF_BANDSELECT, /* 5 */
149 BB_IQSWAP, /* 6 */
150 BB_DLPF_BANDSEL, /* 7 */
151 RFSYN_CHP_GAIN, /* 8 */
152 RFSYN_EN_CHP_HIGAIN, /* 9 */
153 AGC_IF, /* 10 */
154 AGC_RF, /* 11 */
155 IF_DIVVAL, /* 12 */
156 IF_VCO_BIAS, /* 13 */
157 CHCAL_INT_MOD_IF, /* 14 */
158 CHCAL_FRAC_MOD_IF, /* 15 */
159 DRV_RES_SEL, /* 16 */
160 I_DRIVER, /* 17 */
161 EN_AAF, /* 18 */
162 EN_3P, /* 19 */
163 EN_AUX_3P, /* 20 */
164 SEL_AAF_BAND, /* 21 */
165 SEQ_ENCLK16_CLK_OUT, /* 22 */
166 SEQ_SEL4_16B, /* 23 */
167 XTAL_CAPSELECT, /* 24 */
168 IF_SEL_DBL, /* 25 */
169 RFSYN_R_DIV, /* 26 */
170 SEQ_EXTSYNTHCALIF, /* 27 */
171 SEQ_EXTDCCAL, /* 28 */
172 AGC_EN_RSSI, /* 29 */
173 RFA_ENCLKRFAGC, /* 30 */
174 RFA_RSSI_REFH, /* 31 */
175 RFA_RSSI_REF, /* 32 */
176 RFA_RSSI_REFL, /* 33 */
177 RFA_FLR, /* 34 */
178 RFA_CEIL, /* 35 */
179 SEQ_EXTIQFSMPULSE, /* 36 */
180 OVERRIDE_1, /* 37 */
181 BB_INITSTATE_DLPF_TUNE, /* 38 */
182 TG_R_DIV, /* 39 */
183 EN_CHP_LIN_B, /* 40 */
184
185 /* Channel Change Control Names */
186 DN_POLY = 51, /* 51 */
187 DN_RFGAIN, /* 52 */
188 DN_CAP_RFLPF, /* 53 */
189 DN_EN_VHFUHFBAR, /* 54 */
190 DN_GAIN_ADJUST, /* 55 */
191 DN_IQTNBUF_AMP, /* 56 */
192 DN_IQTNGNBFBIAS_BST, /* 57 */
193 RFSYN_EN_OUTMUX, /* 58 */
194 RFSYN_SEL_VCO_OUT, /* 59 */
195 RFSYN_SEL_VCO_HI, /* 60 */
196 RFSYN_SEL_DIVM, /* 61 */
197 RFSYN_RF_DIV_BIAS, /* 62 */
198 DN_SEL_FREQ, /* 63 */
199 RFSYN_VCO_BIAS, /* 64 */
200 CHCAL_INT_MOD_RF, /* 65 */
201 CHCAL_FRAC_MOD_RF, /* 66 */
202 RFSYN_LPF_R, /* 67 */
203 CHCAL_EN_INT_RF, /* 68 */
204 TG_LO_DIVVAL, /* 69 */
205 TG_LO_SELVAL, /* 70 */
206 TG_DIV_VAL, /* 71 */
207 TG_VCO_BIAS, /* 72 */
208 SEQ_EXTPOWERUP, /* 73 */
209 OVERRIDE_2, /* 74 */
210 OVERRIDE_3, /* 75 */
211 OVERRIDE_4, /* 76 */
212 SEQ_FSM_PULSE, /* 77 */
213 GPIO_4B, /* 78 */
214 GPIO_3B, /* 79 */
215 GPIO_4, /* 80 */
216 GPIO_3, /* 81 */
217 GPIO_1B, /* 82 */
218 DAC_A_ENABLE, /* 83 */
219 DAC_B_ENABLE, /* 84 */
220 DAC_DIN_A, /* 85 */
221 DAC_DIN_B, /* 86 */
222#ifdef _MXL_PRODUCTION
223 RFSYN_EN_DIV, /* 87 */
224 RFSYN_DIVM, /* 88 */
225 DN_BYPASS_AGC_I2C /* 89 */
226#endif
227} MXL5005_ControlName;
228
229/*
230 * The following context is source code provided by MaxLinear.
231 * MaxLinear source code - Common_MXL.h (?)
232 */
233
234/* Constants */
235#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
236#define MXL5005S_LATCH_BYTE 0xfe
237
238/* Register address, MSB, and LSB */
239#define MXL5005S_BB_IQSWAP_ADDR 59
240#define MXL5005S_BB_IQSWAP_MSB 0
241#define MXL5005S_BB_IQSWAP_LSB 0
242
243#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
244#define MXL5005S_BB_DLPF_BANDSEL_MSB 4
245#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
246
247/* Standard modes */
248enum
249{
250 MXL5005S_STANDARD_DVBT,
251 MXL5005S_STANDARD_ATSC,
252};
253#define MXL5005S_STANDARD_MODE_NUM 2
254
255/* Bandwidth modes */
256enum
257{
258 MXL5005S_BANDWIDTH_6MHZ = 6000000,
259 MXL5005S_BANDWIDTH_7MHZ = 7000000,
260 MXL5005S_BANDWIDTH_8MHZ = 8000000,
261};
262#define MXL5005S_BANDWIDTH_MODE_NUM 3
263
264/* Top modes */
265enum
266{
267 MXL5005S_TOP_5P5 = 55,
268 MXL5005S_TOP_7P2 = 72,
269 MXL5005S_TOP_9P2 = 92,
270 MXL5005S_TOP_11P0 = 110,
271 MXL5005S_TOP_12P9 = 129,
272 MXL5005S_TOP_14P7 = 147,
273 MXL5005S_TOP_16P8 = 168,
274 MXL5005S_TOP_19P4 = 194,
275 MXL5005S_TOP_21P2 = 212,
276 MXL5005S_TOP_23P2 = 232,
277 MXL5005S_TOP_25P2 = 252,
278 MXL5005S_TOP_27P1 = 271,
279 MXL5005S_TOP_29P2 = 292,
280 MXL5005S_TOP_31P7 = 317,
281 MXL5005S_TOP_34P9 = 349,
282};
283
284/* IF output load */
285enum
286{
287 MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
288 MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
289};
290
27/* MXL5005 Tuner Control Struct */ 291/* MXL5005 Tuner Control Struct */
28typedef struct _TunerControl_struct { 292typedef struct _TunerControl_struct {
29 u16 Ctrl_Num; /* Control Number */ 293 u16 Ctrl_Num; /* Control Number */
@@ -77,241 +341,138 @@ struct mxl5005s_state
77 TunerReg_struct 341 TunerReg_struct
78 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ 342 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
79 343
80}; 344 /* Linux driver framework specific */
81 345 const struct mxl5005s_config *config;
82
83int mxl5005s_Initialize(
84 struct dvb_usb_device* dib,
85 TUNER_MODULE *pTuner
86 )
87{
88 MXL5005S_EXTRA_MODULE *pExtra;
89
90 unsigned char AgcMasterByte;
91 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
92 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
93 int TableLen;
94
95 // Get tuner extra module.
96 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
97
98 // Get AGC master byte
99 AgcMasterByte = pExtra->AgcMasterByte;
100 346
101 // Initialize MxL5005S tuner according to MxL5005S tuner example code. 347 struct dvb_frontend *frontend;
102 348 struct i2c_adapter *i2c;
103 // Tuner initialization stage 0 349};
104 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
105 AddrTable[0] = MASTER_CONTROL_ADDR;
106 ByteTable[0] |= AgcMasterByte;
107
108 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS)
109 goto error_status_set_tuner_registers;
110
111 // Tuner initialization stage 1
112 MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen);
113
114 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS)
115 goto error_status_set_tuner_registers;
116
117 return FUNCTION_SUCCESS;
118
119error_status_set_tuner_registers:
120 return FUNCTION_ERROR;
121}
122 350
123int mxl5005s_SetRfFreqHz( 351// funcs
124 struct dvb_usb_device* dib, 352u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
125 TUNER_MODULE *pTuner, 353u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
126 unsigned long RfFreqHz 354u16 MXL_GetMasterControl(u8 *MasterReg, int state);
127 ) 355void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal);
356u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
357u32 MXL_Ceiling(u32 value, u32 resolution);
358u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
359u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal);
360u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup);
361u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
362u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count);
363u32 MXL_GetXtalInt(u32 Xtal_Freq);
364u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
365void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
366void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
367u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
368int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen);
369u16 MXL_IFSynthInit(struct dvb_frontend *fe);
370
371int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
128{ 372{
129 MXL5005S_EXTRA_MODULE *pExtra; 373 struct mxl5005s_state *state = fe->tuner_priv;
130 BASE_INTERFACE_MODULE *pBaseInterface; 374 u8 AgcMasterByte = state->config->AgcMasterByte;
131
132 unsigned char AgcMasterByte;
133 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; 375 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
134 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; 376 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
135 int TableLen; 377 int TableLen;
136 378
137 unsigned long IfDivval; 379 u32 IfDivval;
138 unsigned char MasterControlByte; 380 unsigned char MasterControlByte;
139 381
140 // Get tuner extra module and base interface module. 382 dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
141 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
142 pBaseInterface = pTuner->pBaseInterface;
143
144
145 // Get AGC master byte
146 AgcMasterByte = pExtra->AgcMasterByte;
147
148 383
149 // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. 384 // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code.
150 385
151 // Tuner RF frequency setting stage 0 386 // Tuner RF frequency setting stage 0
152 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; 387 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ;
153 AddrTable[0] = MASTER_CONTROL_ADDR; 388 AddrTable[0] = MASTER_CONTROL_ADDR;
154 ByteTable[0] |= AgcMasterByte; 389 ByteTable[0] |= state->config->AgcMasterByte;
155
156 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS)
157 goto error_status_set_tuner_registers;
158 390
391 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
159 392
160 // Tuner RF frequency setting stage 1 393 // Tuner RF frequency setting stage 1
161 MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz); 394 MXL_TuneRF(fe, RfFreqHz);
162
163 MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval);
164 395
165 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0); 396 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
166 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1);
167 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8);
168 397
169 MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; 398 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
399 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
400 MXL_ControlWrite(fe, IF_DIVVAL, 8);
401 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ;
170 402
171 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; 403 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
172 AddrTable[TableLen] = MASTER_CONTROL_ADDR ; 404 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
173 ByteTable[TableLen] = MasterControlByte | AgcMasterByte; 405 ByteTable[TableLen] = MasterControlByte | AgcMasterByte;
174 TableLen += 1; 406 TableLen += 1;
175 407
176 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) 408 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
177 goto error_status_set_tuner_registers;
178
179 409
180 // Wait 30 ms. 410 // Wait 30 ms.
181 pBaseInterface->WaitMs(pBaseInterface, 30); 411 msleep(30);
182
183 412
184 // Tuner RF frequency setting stage 2 413 // Tuner RF frequency setting stage 2
185 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ; 414 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ;
186 MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ; 415 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ;
187 MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; 416 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ;
188 417
189 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; 418 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
190 AddrTable[TableLen] = MASTER_CONTROL_ADDR ; 419 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
191 ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; 420 ByteTable[TableLen] = MasterControlByte | AgcMasterByte ;
192 TableLen += 1; 421 TableLen += 1;
193 422
194 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) 423 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
195 goto error_status_set_tuner_registers;
196
197
198 // Set tuner RF frequency parameter.
199 pTuner->RfFreqHz = RfFreqHz;
200 pTuner->IsRfFreqHzSet = YES;
201
202
203 return FUNCTION_SUCCESS;
204
205 424
206error_status_set_tuner_registers: 425 return 0;
207 return FUNCTION_ERROR;
208} 426}
209 427
210// DONE 428/* Write a single byte to a single reg */
211int mxl5005s_GetRfFreqHz(struct dvb_frontend *fe, unsigned long *pRfFreqHz) 429static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val)
212{ 430{
213 struct mxl5005s_state *state = fe->demodulator_priv; 431 struct mxl5005s_state *state = fe->tuner_priv;
214 int ret = -1; 432 u8 buf[2] = { reg, val };
215 433 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
216 /* Get tuner RF frequency in Hz from tuner module. */ 434 .buf = buf, .len = 2 };
217 if(state->IsRfFreqHzSet == YES) { 435
218 *pRfFreqHz = state->RfFreqHz; 436 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
219 ret = 0; 437 printk(KERN_WARNING "mxl5005s I2C write failed\n");
438 return -EREMOTEIO;
220 } 439 }
221 440 return 0;
222 return -1;
223} 441}
224 442
225int mxl5005s_SetRegsWithTable( 443/* Write a word to a single reg */
226 struct dvb_usb_device* dib, 444static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val)
227 TUNER_MODULE *pTuner,
228 unsigned char *pAddrTable,
229 unsigned char *pByteTable,
230 int TableLen
231 )
232{ 445{
233 BASE_INTERFACE_MODULE *pBaseInterface; 446 struct mxl5005s_state *state = fe->tuner_priv;
234 I2C_BRIDGE_MODULE *pI2cBridge; 447 u8 buf[3] = { reg, val >> 8 , val & 0xff };
235 unsigned char WritingByteNumMax; 448 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
236 449 .buf = buf, .len = 3 };
237 int i; 450
238 unsigned char WritingBuffer[I2C_BUFFER_LEN]; 451 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
239 unsigned char WritingIndex; 452 printk(KERN_WARNING "mxl5005s I2C write16 failed\n");
240 453 return -EREMOTEIO;
241
242
243 // Get base interface, I2C bridge, and maximum writing byte number.
244 pBaseInterface = pTuner->pBaseInterface;
245 pI2cBridge = pTuner->pI2cBridge;
246 WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax;
247
248
249 // Set registers with table.
250 // Note: 1. The I2C format of MxL5005S is described as follows:
251 // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit
252 // ...
253 // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit
254 // 2. The latch_byte is 0xfe.
255 // 3. The following writing byte separating scheme takes latch_byte as two byte data.
256 for(i = 0, WritingIndex = 0; i < TableLen; i++)
257 {
258 // Put register address and register byte value into writing buffer.
259 WritingBuffer[WritingIndex] = pAddrTable[i];
260 WritingBuffer[WritingIndex + 1] = pByteTable[i];
261 WritingIndex += 2;
262
263 // If writing buffer is full, send the I2C writing command with writing buffer.
264 if(WritingIndex > (WritingByteNumMax - 2))
265 {
266 if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS)
267 goto error_status_set_tuner_registers;
268
269 WritingIndex = 0;
270 }
271 } 454 }
272 455 return 0;
273
274 // Send the last I2C writing command with writing buffer and latch byte.
275 WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE;
276 WritingIndex += 1;
277
278 if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS)
279 goto error_status_set_tuner_registers;
280
281
282 return FUNCTION_SUCCESS;
283
284
285error_status_set_tuner_registers:
286 return FUNCTION_ERROR;
287} 456}
288 457
289int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, 458int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen)
290 unsigned char *pAddrTable,
291 unsigned char *pByteTable,
292 int TableLen
293 )
294{ 459{
295 struct mxl5005s_state *state = fe->demodulator_priv; 460 int i, ret;
296 int i;
297 u8 end_two_bytes_buf[]={ 0 , 0 }; 461 u8 end_two_bytes_buf[]={ 0 , 0 };
298 u8 tuner_addr=0x00;
299
300 pTuner->GetDeviceAddr(pTuner , &tuner_addr);
301 462
302 for( i = 0 ; i < TableLen - 1 ; i++) 463 for( i = 0 ; i < TableLen - 1 ; i++)
303 { 464 {
304 if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) 465 ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]);
305 return FUNCTION_ERROR; 466 if (!ret)
467 return ret;
306 } 468 }
307 469
308 end_two_bytes_buf[0] = pByteTable[i]; 470 end_two_bytes_buf[0] = pByteTable[i];
309 end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; 471 end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE;
310 472
311 if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) 473 ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]);
312 return FUNCTION_ERROR;
313 474
314 return FUNCTION_SUCCESS; 475 return ret;
315} 476}
316 477
317int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, 478int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe,
@@ -321,7 +482,6 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe,
321 const unsigned char WritingValue 482 const unsigned char WritingValue
322 ) 483 )
323{ 484{
324 struct mxl5005s_state *state = fe->demodulator_priv;
325 int i; 485 int i;
326 486
327 unsigned char Mask; 487 unsigned char Mask;
@@ -335,82 +495,18 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe,
335 495
336 Shift = Lsb; 496 Shift = Lsb;
337 497
338
339 /* Get tuner register byte according to register adddress. */ 498 /* Get tuner register byte according to register adddress. */
340 MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); 499 MXL_RegRead(fe, RegAddr, &RegByte);
341 500
342 /* Reserve register byte unmask bit with mask and inlay writing value into it. */ 501 /* Reserve register byte unmask bit with mask and inlay writing value into it. */
343 RegByte &= ~Mask; 502 RegByte &= ~Mask;
344 RegByte |= (WritingValue << Shift) & Mask; 503 RegByte |= (WritingValue << Shift) & Mask;
345 504
346 /* Update tuner register byte table. */ 505 /* Update tuner register byte table. */
347 MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); 506 MXL_RegWrite(fe, RegAddr, RegByte);
348 507
349 /* Write tuner register byte with writing byte. */ 508 /* Write tuner register byte with writing byte. */
350 if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) 509 return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1);
351 goto error_status_set_tuner_registers;
352
353
354 return FUNCTION_SUCCESS;
355
356
357error_status_set_tuner_registers:
358 return FUNCTION_ERROR;
359}
360
361// DONE
362int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode)
363{
364 struct mxl5005s_state *state = fe->demodulator_priv;
365 static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] =
366 {
367 /* BB_IQSWAP */
368 0, /* Normal spectrum */
369 1, /* Inverse spectrum */
370 };
371
372 /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */
373 mxl5005s_SetRegMaskBits(fe,
374 MXL5005S_BB_IQSWAP_ADDR,
375 MXL5005S_BB_IQSWAP_MSB,
376 MXL5005S_BB_IQSWAP_LSB,
377 BbIqswapTable[SpectrumMode]);
378
379 return FUNCTION_SUCCESS;
380}
381
382// DONE
383int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz)
384{
385 struct mxl5005s_state *state = fe->demodulator_priv;
386
387 unsigned char BbDlpfBandsel;
388
389 /* Set BB_DLPF_BANDSEL according to bandwidth. */
390 switch(BandwidthHz)
391 {
392 default:
393 case MXL5005S_BANDWIDTH_6MHZ:
394 BbDlpfBandsel = 3;
395 break;
396 case MXL5005S_BANDWIDTH_7MHZ:
397 BbDlpfBandsel = 2;
398 break;
399 case MXL5005S_BANDWIDTH_8MHZ:
400 BbDlpfBandsel = 0;
401 break;
402 }
403
404 if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB,
405 MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0)
406 goto error_status_set_tuner_registers;
407
408
409 return 0;
410
411
412error_status_set_tuner_registers:
413 return -1;
414} 510}
415 511
416// The following context is source code provided by MaxLinear. 512// The following context is source code provided by MaxLinear.
@@ -418,7 +514,7 @@ error_status_set_tuner_registers:
418// DONE 514// DONE
419u16 MXL5005_RegisterInit(struct dvb_frontend *fe) 515u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
420{ 516{
421 struct mxl5005s_state *state = fe->demodulator_priv; 517 struct mxl5005s_state *state = fe->tuner_priv;
422 state->TunerRegs_Num = TUNER_REGS_NUM ; 518 state->TunerRegs_Num = TUNER_REGS_NUM ;
423// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; 519// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
424 520
@@ -740,7 +836,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
740// DONE 836// DONE
741u16 MXL5005_ControlInit(struct dvb_frontend *fe) 837u16 MXL5005_ControlInit(struct dvb_frontend *fe)
742{ 838{
743 struct mxl5005s_state *state = fe->demodulator_priv; 839 struct mxl5005s_state *state = fe->tuner_priv;
744 state->Init_Ctrl_Num = INITCTRL_NUM; 840 state->Init_Ctrl_Num = INITCTRL_NUM;
745 841
746 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; 842 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
@@ -1684,7 +1780,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe)
1684// DONE 1780// DONE
1685void InitTunerControls(struct dvb_frontend *fe) 1781void InitTunerControls(struct dvb_frontend *fe)
1686{ 1782{
1687 struct mxl5005s_state *state = fe->demodulator_priv;
1688 MXL5005_RegisterInit(fe); 1783 MXL5005_RegisterInit(fe);
1689 MXL5005_ControlInit(fe); 1784 MXL5005_ControlInit(fe);
1690#ifdef _MXL_INTERNAL 1785#ifdef _MXL_INTERNAL
@@ -1745,7 +1840,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1745 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ 1840 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
1746 ) 1841 )
1747{ 1842{
1748 struct mxl5005s_state *state = fe->demodulator_priv; 1843 struct mxl5005s_state *state = fe->tuner_priv;
1749 u16 status = 0; 1844 u16 status = 0;
1750 1845
1751 state->Mode = Mode; 1846 state->Mode = Mode;
@@ -1798,8 +1893,8 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1798// DONE 1893// DONE
1799void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) 1894void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1800{ 1895{
1801 struct mxl5005s_state *state = fe->demodulator_priv; 1896 struct mxl5005s_state *state = fe->tuner_priv;
1802 if (Tuner->Mode == 1) /* Digital Mode */ 1897 if (state->Mode == 1) /* Digital Mode */
1803 state->IF_LO = state->IF_OUT; 1898 state->IF_LO = state->IF_OUT;
1804 else /* Analog Mode */ 1899 else /* Analog Mode */
1805 { 1900 {
@@ -1837,7 +1932,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1837// DONE 1932// DONE
1838void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) 1933void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1839{ 1934{
1840 struct mxl5005s_state *state = fe->demodulator_priv; 1935 struct mxl5005s_state *state = fe->tuner_priv;
1841 1936
1842 if (state->Mode == 1) /* Digital Mode */ { 1937 if (state->Mode == 1) /* Digital Mode */ {
1843 //remove 20.48MHz setting for 2.6.10 1938 //remove 20.48MHz setting for 2.6.10
@@ -1876,7 +1971,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1876// DONE 1971// DONE
1877u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) 1972u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1878{ 1973{
1879 struct mxl5005s_state *state = fe->demodulator_priv;
1880 u16 status = 0; 1974 u16 status = 0;
1881 1975
1882 status += MXL_ControlWrite(fe, OVERRIDE_1, 1); 1976 status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
@@ -1915,7 +2009,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1915// DONE 2009// DONE
1916u16 MXL_BlockInit(struct dvb_frontend *fe) 2010u16 MXL_BlockInit(struct dvb_frontend *fe)
1917{ 2011{
1918 struct mxl5005s_state *state = fe->demodulator_priv; 2012 struct mxl5005s_state *state = fe->tuner_priv;
1919 u16 status = 0; 2013 u16 status = 0;
1920 2014
1921 status += MXL_OverwriteICDefault(fe); 2015 status += MXL_OverwriteICDefault(fe);
@@ -2096,7 +2190,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2096 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); 2190 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
2097 2191
2098 /* Misc Controls */ 2192 /* Misc Controls */
2099 if (state->Mode == 0 && Tuner->IF_Mode == 1) /* Analog LowIF mode */ 2193 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
2100 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); 2194 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
2101 else 2195 else
2102 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); 2196 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
@@ -2155,7 +2249,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2155 } 2249 }
2156 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ 2250 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */
2157 { 2251 {
2158 Tuner->AGC_Mode = 1; /* Single AGC Mode */ 2252 state->AGC_Mode = 1; /* Single AGC Mode */
2159 2253
2160 /* Enable RSSI */ 2254 /* Enable RSSI */
2161 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 2255 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
@@ -2203,7 +2297,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2203 } 2297 }
2204 if (state->Mod_Type == MXL_ANALOG_CABLE) { 2298 if (state->Mod_Type == MXL_ANALOG_CABLE) {
2205 /* Analog Cable Mode */ 2299 /* Analog Cable Mode */
2206 /* Tuner->Mode = MXL_DIGITAL_MODE; */ 2300 /* state->Mode = MXL_DIGITAL_MODE; */
2207 2301
2208 state->AGC_Mode = 1; /* Single AGC Mode */ 2302 state->AGC_Mode = 1; /* Single AGC Mode */
2209 2303
@@ -2269,8 +2363,9 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
2269// > 0 : Failed // 2363// > 0 : Failed //
2270// // 2364// //
2271/////////////////////////////////////////////////////////////////////////////// 2365///////////////////////////////////////////////////////////////////////////////
2272u16 MXL_IFSynthInit(Tuner_struct * Tuner) 2366u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2273{ 2367{
2368 struct mxl5005s_state *state = fe->tuner_priv;
2274 u16 status = 0 ; 2369 u16 status = 0 ;
2275 // Declare Local Variables 2370 // Declare Local Variables
2276 u32 Fref = 0 ; 2371 u32 Fref = 0 ;
@@ -2286,186 +2381,186 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner)
2286 // 2381 //
2287 // IF Synthesizer Control 2382 // IF Synthesizer Control
2288 // 2383 //
2289 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode 2384 if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode
2290 { 2385 {
2291 if (Tuner->IF_LO == 41000000UL) { 2386 if (state->IF_LO == 41000000UL) {
2292 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2387 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2293 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2388 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2294 Fref = 328000000UL ; 2389 Fref = 328000000UL ;
2295 } 2390 }
2296 if (Tuner->IF_LO == 47000000UL) { 2391 if (state->IF_LO == 47000000UL) {
2297 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2392 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2298 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2393 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2299 Fref = 376000000UL ; 2394 Fref = 376000000UL ;
2300 } 2395 }
2301 if (Tuner->IF_LO == 54000000UL) { 2396 if (state->IF_LO == 54000000UL) {
2302 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; 2397 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2303 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2398 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2304 Fref = 324000000UL ; 2399 Fref = 324000000UL ;
2305 } 2400 }
2306 if (Tuner->IF_LO == 60000000UL) { 2401 if (state->IF_LO == 60000000UL) {
2307 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; 2402 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2308 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2403 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2309 Fref = 360000000UL ; 2404 Fref = 360000000UL ;
2310 } 2405 }
2311 if (Tuner->IF_LO == 39250000UL) { 2406 if (state->IF_LO == 39250000UL) {
2312 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2407 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2313 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2408 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2314 Fref = 314000000UL ; 2409 Fref = 314000000UL ;
2315 } 2410 }
2316 if (Tuner->IF_LO == 39650000UL) { 2411 if (state->IF_LO == 39650000UL) {
2317 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2412 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2318 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2413 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2319 Fref = 317200000UL ; 2414 Fref = 317200000UL ;
2320 } 2415 }
2321 if (Tuner->IF_LO == 40150000UL) { 2416 if (state->IF_LO == 40150000UL) {
2322 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2417 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2323 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2418 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2324 Fref = 321200000UL ; 2419 Fref = 321200000UL ;
2325 } 2420 }
2326 if (Tuner->IF_LO == 40650000UL) { 2421 if (state->IF_LO == 40650000UL) {
2327 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2422 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2328 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2423 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2329 Fref = 325200000UL ; 2424 Fref = 325200000UL ;
2330 } 2425 }
2331 } 2426 }
2332 2427
2333 if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) 2428 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0))
2334 { 2429 {
2335 if (Tuner->IF_LO == 57000000UL) { 2430 if (state->IF_LO == 57000000UL) {
2336 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; 2431 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2337 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2432 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2338 Fref = 342000000UL ; 2433 Fref = 342000000UL ;
2339 } 2434 }
2340 if (Tuner->IF_LO == 44000000UL) { 2435 if (state->IF_LO == 44000000UL) {
2341 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2436 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2342 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2437 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2343 Fref = 352000000UL ; 2438 Fref = 352000000UL ;
2344 } 2439 }
2345 if (Tuner->IF_LO == 43750000UL) { 2440 if (state->IF_LO == 43750000UL) {
2346 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2441 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2347 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2442 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2348 Fref = 350000000UL ; 2443 Fref = 350000000UL ;
2349 } 2444 }
2350 if (Tuner->IF_LO == 36650000UL) { 2445 if (state->IF_LO == 36650000UL) {
2351 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2446 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2352 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2447 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2353 Fref = 366500000UL ; 2448 Fref = 366500000UL ;
2354 } 2449 }
2355 if (Tuner->IF_LO == 36150000UL) { 2450 if (state->IF_LO == 36150000UL) {
2356 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2451 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2357 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2452 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2358 Fref = 361500000UL ; 2453 Fref = 361500000UL ;
2359 } 2454 }
2360 if (Tuner->IF_LO == 36000000UL) { 2455 if (state->IF_LO == 36000000UL) {
2361 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2456 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2362 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2457 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2363 Fref = 360000000UL ; 2458 Fref = 360000000UL ;
2364 } 2459 }
2365 if (Tuner->IF_LO == 35250000UL) { 2460 if (state->IF_LO == 35250000UL) {
2366 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2461 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2367 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2462 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2368 Fref = 352500000UL ; 2463 Fref = 352500000UL ;
2369 } 2464 }
2370 if (Tuner->IF_LO == 34750000UL) { 2465 if (state->IF_LO == 34750000UL) {
2371 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2466 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2372 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2467 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2373 Fref = 347500000UL ; 2468 Fref = 347500000UL ;
2374 } 2469 }
2375 if (Tuner->IF_LO == 6280000UL) { 2470 if (state->IF_LO == 6280000UL) {
2376 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2471 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2377 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2472 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2378 Fref = 376800000UL ; 2473 Fref = 376800000UL ;
2379 } 2474 }
2380 if (Tuner->IF_LO == 5000000UL) { 2475 if (state->IF_LO == 5000000UL) {
2381 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; 2476 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2382 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2477 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2383 Fref = 360000000UL ; 2478 Fref = 360000000UL ;
2384 } 2479 }
2385 if (Tuner->IF_LO == 4500000UL) { 2480 if (state->IF_LO == 4500000UL) {
2386 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; 2481 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2387 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2482 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2388 Fref = 360000000UL ; 2483 Fref = 360000000UL ;
2389 } 2484 }
2390 if (Tuner->IF_LO == 4570000UL) { 2485 if (state->IF_LO == 4570000UL) {
2391 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; 2486 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2392 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2487 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2393 Fref = 365600000UL ; 2488 Fref = 365600000UL ;
2394 } 2489 }
2395 if (Tuner->IF_LO == 4000000UL) { 2490 if (state->IF_LO == 4000000UL) {
2396 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; 2491 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ;
2397 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2492 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2398 Fref = 360000000UL ; 2493 Fref = 360000000UL ;
2399 } 2494 }
2400 if (Tuner->IF_LO == 57400000UL) 2495 if (state->IF_LO == 57400000UL)
2401 { 2496 {
2402 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; 2497 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2403 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2498 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2404 Fref = 344400000UL ; 2499 Fref = 344400000UL ;
2405 } 2500 }
2406 if (Tuner->IF_LO == 44400000UL) 2501 if (state->IF_LO == 44400000UL)
2407 { 2502 {
2408 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2503 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2409 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2504 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2410 Fref = 355200000UL ; 2505 Fref = 355200000UL ;
2411 } 2506 }
2412 if (Tuner->IF_LO == 44150000UL) 2507 if (state->IF_LO == 44150000UL)
2413 { 2508 {
2414 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; 2509 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2415 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2510 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2416 Fref = 353200000UL ; 2511 Fref = 353200000UL ;
2417 } 2512 }
2418 if (Tuner->IF_LO == 37050000UL) 2513 if (state->IF_LO == 37050000UL)
2419 { 2514 {
2420 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2515 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2421 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2516 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2422 Fref = 370500000UL ; 2517 Fref = 370500000UL ;
2423 } 2518 }
2424 if (Tuner->IF_LO == 36550000UL) 2519 if (state->IF_LO == 36550000UL)
2425 { 2520 {
2426 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2521 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2427 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2522 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2428 Fref = 365500000UL ; 2523 Fref = 365500000UL ;
2429 } 2524 }
2430 if (Tuner->IF_LO == 36125000UL) { 2525 if (state->IF_LO == 36125000UL) {
2431 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; 2526 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2432 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2527 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2433 Fref = 361250000UL ; 2528 Fref = 361250000UL ;
2434 } 2529 }
2435 if (Tuner->IF_LO == 6000000UL) { 2530 if (state->IF_LO == 6000000UL) {
2436 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2531 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2437 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2532 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2438 Fref = 360000000UL ; 2533 Fref = 360000000UL ;
2439 } 2534 }
2440 if (Tuner->IF_LO == 5400000UL) 2535 if (state->IF_LO == 5400000UL)
2441 { 2536 {
2442 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2537 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2443 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2538 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2444 Fref = 324000000UL ; 2539 Fref = 324000000UL ;
2445 } 2540 }
2446 if (Tuner->IF_LO == 5380000UL) { 2541 if (state->IF_LO == 5380000UL) {
2447 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; 2542 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2448 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; 2543 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
2449 Fref = 322800000UL ; 2544 Fref = 322800000UL ;
2450 } 2545 }
2451 if (Tuner->IF_LO == 5200000UL) { 2546 if (state->IF_LO == 5200000UL) {
2452 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; 2547 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2453 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2548 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2454 Fref = 374400000UL ; 2549 Fref = 374400000UL ;
2455 } 2550 }
2456 if (Tuner->IF_LO == 4900000UL) 2551 if (state->IF_LO == 4900000UL)
2457 { 2552 {
2458 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; 2553 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2459 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2554 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2460 Fref = 352800000UL ; 2555 Fref = 352800000UL ;
2461 } 2556 }
2462 if (Tuner->IF_LO == 4400000UL) 2557 if (state->IF_LO == 4400000UL)
2463 { 2558 {
2464 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; 2559 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2465 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2560 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
2466 Fref = 352000000UL ; 2561 Fref = 352000000UL ;
2467 } 2562 }
2468 if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 2563 if (state->IF_LO == 4063000UL) //add for 2.6.8
2469 { 2564 {
2470 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; 2565 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ;
2471 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; 2566 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
@@ -2542,7 +2637,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq)
2542/////////////////////////////////////////////////////////////////////////////// 2637///////////////////////////////////////////////////////////////////////////////
2543u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) 2638u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2544{ 2639{
2545 struct mxl5005s_state *state = fe->demodulator_priv; 2640 struct mxl5005s_state *state = fe->tuner_priv;
2546 // Declare Local Variables 2641 // Declare Local Variables
2547 u16 status = 0; 2642 u16 status = 0;
2548 u32 divider_val, E3, E4, E5, E5A; 2643 u32 divider_val, E3, E4, E5, E5A;
@@ -3034,7 +3129,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3034 // 3129 //
3035 // Off Chip Tracking Filter Control 3130 // Off Chip Tracking Filter Control
3036 // 3131 //
3037 if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks 3132 if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks
3038 { 3133 {
3039 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; 3134 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ;
3040 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; 3135 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ;
@@ -3044,7 +3139,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3044 status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 3139 status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3
3045 } 3140 }
3046 3141
3047 if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C 3142 if (state->TF_Type == MXL_TF_C) // Tracking Filter type C
3048 { 3143 {
3049 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; 3144 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ;
3050 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; 3145 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
@@ -3124,7 +3219,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3124 } 3219 }
3125 } 3220 }
3126 3221
3127 if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only 3222 if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
3128 { 3223 {
3129 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; 3224 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
3130 3225
@@ -3194,7 +3289,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3194 } 3289 }
3195 } 3290 }
3196 3291
3197 if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D 3292 if (state->TF_Type == MXL_TF_D) // Tracking Filter type D
3198 { 3293 {
3199 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3294 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3200 3295
@@ -3251,7 +3346,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3251 } 3346 }
3252 3347
3253 3348
3254 if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 3349 if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3
3255 { 3350 {
3256 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; 3351 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
3257 3352
@@ -3336,7 +3431,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3336 } 3431 }
3337 } 3432 }
3338 3433
3339 if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E 3434 if (state->TF_Type == MXL_TF_E) // Tracking Filter type E
3340 { 3435 {
3341 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3436 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3342 3437
@@ -3392,7 +3487,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3392 } 3487 }
3393 } 3488 }
3394 3489
3395 if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F 3490 if (state->TF_Type == MXL_TF_F) // Tracking Filter type F
3396 { 3491 {
3397 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3492 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3398 3493
@@ -3448,7 +3543,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3448 } 3543 }
3449 } 3544 }
3450 3545
3451 if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 3546 if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2
3452 { 3547 {
3453 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3548 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3454 3549
@@ -3504,7 +3599,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3504 } 3599 }
3505 } 3600 }
3506 3601
3507 if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 3602 if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8
3508 { 3603 {
3509 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3604 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3510 3605
@@ -3567,7 +3662,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3567 } 3662 }
3568 } 3663 }
3569 3664
3570 if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 3665 if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8
3571 { 3666 {
3572 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; 3667 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3573 3668
@@ -3667,7 +3762,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
3667// DONE 3762// DONE
3668u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) 3763u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3669{ 3764{
3670 struct mxl5005s_state *state = fe->demodulator_priv;
3671 u16 status = 0; 3765 u16 status = 0;
3672 3766
3673 if (GPIO_Num == 1) 3767 if (GPIO_Num == 1)
@@ -3735,14 +3829,13 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3735// DONE 3829// DONE
3736u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) 3830u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3737{ 3831{
3738 struct mxl5005s_state *state = fe->demodulator_priv;
3739 u16 status = 0; 3832 u16 status = 0;
3740 3833
3741 /* Will write ALL Matching Control Name */ 3834 /* Will write ALL Matching Control Name */
3742 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control * 3835 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */
3743 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control * 3836 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */
3744#ifdef _MXL_INTERNAL 3837#ifdef _MXL_INTERNAL
3745 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control * 3838 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */
3746#endif 3839#endif
3747 return status; 3840 return status;
3748} 3841}
@@ -3777,7 +3870,7 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3777// DONE 3870// DONE
3778u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) 3871u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup)
3779{ 3872{
3780 struct mxl5005s_state *state = fe->demodulator_priv; 3873 struct mxl5005s_state *state = fe->tuner_priv;
3781 u16 i, j, k; 3874 u16 i, j, k;
3782 u32 highLimit; 3875 u32 highLimit;
3783 u32 ctrlVal; 3876 u32 ctrlVal;
@@ -3884,7 +3977,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u
3884// DONE 3977// DONE
3885u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) 3978u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
3886{ 3979{
3887 struct mxl5005s_state *state = fe->demodulator_priv; 3980 struct mxl5005s_state *state = fe->tuner_priv;
3888 int i ; 3981 int i ;
3889 3982
3890 for (i = 0; i < 104; i++) { 3983 for (i = 0; i < 104; i++) {
@@ -3924,7 +4017,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
3924// DONE 4017// DONE
3925u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) 4018u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3926{ 4019{
3927 struct mxl5005s_state *state = fe->demodulator_priv; 4020 struct mxl5005s_state *state = fe->tuner_priv;
3928 int i ; 4021 int i ;
3929 4022
3930 for (i = 0; i < 104; i++) { 4023 for (i = 0; i < 104; i++) {
@@ -3959,9 +4052,9 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3959// // 4052// //
3960/////////////////////////////////////////////////////////////////////////////// 4053///////////////////////////////////////////////////////////////////////////////
3961// DONE 4054// DONE
3962u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) 4055u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3963{ 4056{
3964 struct mxl5005s_state *state = fe->demodulator_priv; 4057 struct mxl5005s_state *state = fe->tuner_priv;
3965 u32 ctrlVal ; 4058 u32 ctrlVal ;
3966 u16 i, k ; 4059 u16 i, k ;
3967 4060
@@ -4033,7 +4126,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value)
4033// DONE 4126// DONE
4034u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) 4127u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count)
4035{ 4128{
4036 struct mxl5005s_state *state = fe->demodulator_priv; 4129 struct mxl5005s_state *state = fe->tuner_priv;
4037 u16 i, j, k ; 4130 u16 i, j, k ;
4038 u16 Count ; 4131 u16 Count ;
4039 4132
@@ -4139,7 +4232,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int
4139// DONE 4232// DONE
4140void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) 4233void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal)
4141{ 4234{
4142 struct mxl5005s_state *state = fe->demodulator_priv; 4235 struct mxl5005s_state *state = fe->tuner_priv;
4143 int i ; 4236 int i ;
4144 4237
4145 const u8 AND_MAP[8] = { 4238 const u8 AND_MAP[8] = {
@@ -4196,7 +4289,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution)
4196// DONE 4289// DONE
4197u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) 4290u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4198{ 4291{
4199 struct mxl5005s_state *state = fe->demodulator_priv;
4200 u16 status = 0; 4292 u16 status = 0;
4201 int i ; 4293 int i ;
4202 4294
@@ -4220,7 +4312,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c
4220// DONE 4312// DONE
4221u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) 4313u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4222{ 4314{
4223 struct mxl5005s_state *state = fe->demodulator_priv;
4224 u16 status = 0; 4315 u16 status = 0;
4225 int i ; 4316 int i ;
4226 4317
@@ -4249,7 +4340,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou
4249// DONE 4340// DONE
4250u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) 4341u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4251{ 4342{
4252 struct mxl5005s_state *state = fe->demodulator_priv;
4253 u16 status = 0; 4343 u16 status = 0;
4254 int i; 4344 int i;
4255 4345
@@ -4268,7 +4358,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i
4268// DONE 4358// DONE
4269u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) 4359u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
4270{ 4360{
4271 struct mxl5005s_state *state = fe->demodulator_priv;
4272 u16 status = 0; 4361 u16 status = 0;
4273 int i; 4362 int i;
4274 4363
@@ -4302,7 +4391,7 @@ u16 MXL_GetMasterControl(u8 *MasterReg, int state)
4302#ifdef _MXL_PRODUCTION 4391#ifdef _MXL_PRODUCTION
4303u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) 4392u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
4304{ 4393{
4305 struct mxl5005s_state *state = fe->demodulator_priv; 4394 struct mxl5005s_state *state = fe->tuner_priv;
4306 u16 status = 0 ; 4395 u16 status = 0 ;
4307 4396
4308 if (VCO_Range == 1) { 4397 if (VCO_Range == 1) {
@@ -4432,7 +4521,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
4432// DONE 4521// DONE
4433u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) 4522u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
4434{ 4523{
4435 struct mxl5005s_state *state = fe->demodulator_priv; 4524 struct mxl5005s_state *state = fe->tuner_priv;
4436 u16 status = 0; 4525 u16 status = 0;
4437 4526
4438 if (Hystersis == 1) 4527 if (Hystersis == 1)
@@ -4443,3 +4532,194 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
4443 4532
4444#endif 4533#endif
4445 4534
4535/* Linux driver related functions */
4536
4537
4538int mxl5005s_init2(struct dvb_frontend *fe)
4539{
4540 int MxlModMode;
4541 int MxlIfMode;
4542 unsigned long MxlBandwitdh;
4543 unsigned long MxlIfFreqHz;
4544 unsigned long MxlCrystalFreqHz;
4545 int MxlAgcMode;
4546 unsigned short MxlTop;
4547 unsigned short MxlIfOutputLoad;
4548 int MxlClockOut;
4549 int MxlDivOut;
4550 int MxlCapSel;
4551 int MxlRssiOnOff;
4552 unsigned char MxlStandard;
4553 unsigned char MxlTfType;
4554
4555 /* Set MxL5005S parameters. */
4556 MxlModMode = MXL_DIGITAL_MODE;
4557 MxlIfMode = MXL_ZERO_IF;
4558// steve
4559 //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ;
4560 //MxlIfFreqHz = IF_FREQ_4570000HZ;
4561 MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config
4562 MxlIfFreqHz = IF_FREQ_5380000HZ; // config
4563 MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config
4564 MxlAgcMode = MXL_SINGLE_AGC;
4565 MxlTop = MXL5005S_TOP_25P2;
4566 MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM;
4567 MxlClockOut = MXL_CLOCK_OUT_DISABLE;
4568 MxlDivOut = MXL_DIV_OUT_4;
4569 MxlCapSel = MXL_CAP_SEL_ENABLE;
4570 MxlRssiOnOff = MXL_RSSI_ENABLE; // config
4571 MxlTfType = MXL_TF_C_H; // config
4572
4573 MxlStandard = MXL_ATSC; // config
4574
4575 // TODO: this is bad, it trashes other configs
4576 // Set MxL5005S extra module.
4577 //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0;
4578
4579 MXL5005_TunerConfig(
4580 fe,
4581 (unsigned char)MxlModMode,
4582 (unsigned char)MxlIfMode,
4583 MxlBandwitdh,
4584 MxlIfFreqHz,
4585 MxlCrystalFreqHz,
4586 (unsigned char)MxlAgcMode,
4587 MxlTop,
4588 MxlIfOutputLoad,
4589 (unsigned char)MxlClockOut,
4590 (unsigned char)MxlDivOut,
4591 (unsigned char)MxlCapSel,
4592 (unsigned char)MxlRssiOnOff,
4593 MxlStandard, MxlTfType);
4594
4595 return 0;
4596}
4597
4598static int mxl5005s_set_params(struct dvb_frontend *fe,
4599 struct dvb_frontend_parameters *params)
4600{
4601 u32 freq;
4602 u32 bw;
4603
4604 if (fe->ops.info.type == FE_OFDM)
4605 bw = params->u.ofdm.bandwidth;
4606 else
4607 bw = MXL5005S_BANDWIDTH_6MHZ;
4608
4609 freq = params->frequency; /* Hz */
4610 dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw);
4611
4612 return mxl5005s_SetRfFreqHz(fe, freq);
4613}
4614
4615static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4616{
4617 struct mxl5005s_state *state = fe->tuner_priv;
4618 dprintk(1, "%s()\n", __func__);
4619
4620 *frequency = state->RF_IN;
4621
4622 return 0;
4623}
4624
4625static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4626{
4627 struct mxl5005s_state *state = fe->tuner_priv;
4628 dprintk(1, "%s()\n", __func__);
4629
4630 *bandwidth = state->Chan_Bandwidth;
4631
4632 return 0;
4633}
4634
4635static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status)
4636{
4637 dprintk(1, "%s()\n", __func__);
4638
4639 *status = 0;
4640 // *status = TUNER_STATUS_LOCKED;
4641
4642 return 0;
4643}
4644
4645static int mxl5005s_init(struct dvb_frontend *fe)
4646{
4647 struct mxl5005s_state *state = fe->tuner_priv;
4648 u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4649 u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4650 int TableLen;
4651
4652 dprintk(1, "%s()\n", __func__);
4653
4654 /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */
4655
4656 /* Tuner initialization stage 0 */
4657 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
4658 AddrTable[0] = MASTER_CONTROL_ADDR;
4659 ByteTable[0] |= state->config->AgcMasterByte;
4660
4661 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
4662
4663 /* Tuner initialization stage 1 */
4664 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
4665
4666 mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
4667
4668 return mxl5005s_init2(fe);
4669}
4670
4671static int mxl5005s_release(struct dvb_frontend *fe)
4672{
4673 dprintk(1, "%s()\n", __func__);
4674 kfree(fe->tuner_priv);
4675 fe->tuner_priv = NULL;
4676 return 0;
4677}
4678
4679static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
4680 .info = {
4681 .name = "MaxLinear MXL5005S",
4682 .frequency_min = 48000000,
4683 .frequency_max = 860000000,
4684 .frequency_step = 50000,
4685 },
4686
4687 .release = mxl5005s_release,
4688 .init = mxl5005s_init,
4689
4690 .set_params = mxl5005s_set_params,
4691 .get_frequency = mxl5005s_get_frequency,
4692 .get_bandwidth = mxl5005s_get_bandwidth,
4693 .get_status = mxl5005s_get_status
4694};
4695
4696struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4697 struct i2c_adapter *i2c,
4698 struct mxl5005s_config *config)
4699{
4700 struct mxl5005s_state *state = NULL;
4701 dprintk(1, "%s()\n", __func__);
4702
4703 state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4704 if (state == NULL)
4705 return NULL;
4706
4707 state->frontend = fe;
4708 state->config = config;
4709 state->i2c = i2c;
4710
4711 printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address);
4712
4713 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops));
4714
4715 fe->tuner_priv = state;
4716 return fe;
4717}
4718EXPORT_SYMBOL(mxl5005s_attach);
4719
4720MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
4721MODULE_AUTHOR("Jan Hoogenraad");
4722MODULE_AUTHOR("Barnaby Shearer");
4723MODULE_AUTHOR("Andy Hasper");
4724MODULE_AUTHOR("Steven Toth");
4725MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 13:44:06 -0500