diff options
Diffstat (limited to 'drivers/kvm')
-rw-r--r-- | drivers/kvm/vmx.c | 16 | ||||
-rw-r--r-- | drivers/kvm/vmx.h | 69 |
2 files changed, 55 insertions, 30 deletions
diff --git a/drivers/kvm/vmx.c b/drivers/kvm/vmx.c index 79674a7a92bb..dac2f93d1a07 100644 --- a/drivers/kvm/vmx.c +++ b/drivers/kvm/vmx.c | |||
@@ -751,7 +751,10 @@ static __init int vmx_disabled_by_bios(void) | |||
751 | u64 msr; | 751 | u64 msr; |
752 | 752 | ||
753 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | 753 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); |
754 | return (msr & 5) == 1; /* locked but not enabled */ | 754 | return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
755 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | ||
756 | == MSR_IA32_FEATURE_CONTROL_LOCKED; | ||
757 | /* locked but not enabled */ | ||
755 | } | 758 | } |
756 | 759 | ||
757 | static void hardware_enable(void *garbage) | 760 | static void hardware_enable(void *garbage) |
@@ -761,9 +764,14 @@ static void hardware_enable(void *garbage) | |||
761 | u64 old; | 764 | u64 old; |
762 | 765 | ||
763 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); | 766 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
764 | if ((old & 5) != 5) | 767 | if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED | |
768 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | ||
769 | != (MSR_IA32_FEATURE_CONTROL_LOCKED | | ||
770 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED)) | ||
765 | /* enable and lock */ | 771 | /* enable and lock */ |
766 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5); | 772 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
773 | MSR_IA32_FEATURE_CONTROL_LOCKED | | ||
774 | MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED); | ||
767 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ | 775 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
768 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) | 776 | asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr) |
769 | : "memory", "cc"); | 777 | : "memory", "cc"); |
@@ -1326,7 +1334,7 @@ static int vmx_vcpu_setup(struct kvm_vcpu *vcpu) | |||
1326 | CPU_BASED_HLT_EXITING /* 20.6.2 */ | 1334 | CPU_BASED_HLT_EXITING /* 20.6.2 */ |
1327 | | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */ | 1335 | | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */ |
1328 | | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */ | 1336 | | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */ |
1329 | | CPU_BASED_ACTIVATE_IO_BITMAP /* 20.6.2 */ | 1337 | | CPU_BASED_USE_IO_BITMAPS /* 20.6.2 */ |
1330 | | CPU_BASED_MOV_DR_EXITING | 1338 | | CPU_BASED_MOV_DR_EXITING |
1331 | | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */ | 1339 | | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */ |
1332 | ); | 1340 | ); |
diff --git a/drivers/kvm/vmx.h b/drivers/kvm/vmx.h index 76ad7933cded..7e4dc1208dd4 100644 --- a/drivers/kvm/vmx.h +++ b/drivers/kvm/vmx.h | |||
@@ -25,29 +25,36 @@ | |||
25 | * | 25 | * |
26 | */ | 26 | */ |
27 | 27 | ||
28 | #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 | 28 | #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 |
29 | #define CPU_BASED_USE_TSC_OFFSETING 0x00000008 | 29 | #define CPU_BASED_USE_TSC_OFFSETING 0x00000008 |
30 | #define CPU_BASED_HLT_EXITING 0x00000080 | 30 | #define CPU_BASED_HLT_EXITING 0x00000080 |
31 | #define CPU_BASED_INVDPG_EXITING 0x00000200 | 31 | #define CPU_BASED_INVLPG_EXITING 0x00000200 |
32 | #define CPU_BASED_MWAIT_EXITING 0x00000400 | 32 | #define CPU_BASED_MWAIT_EXITING 0x00000400 |
33 | #define CPU_BASED_RDPMC_EXITING 0x00000800 | 33 | #define CPU_BASED_RDPMC_EXITING 0x00000800 |
34 | #define CPU_BASED_RDTSC_EXITING 0x00001000 | 34 | #define CPU_BASED_RDTSC_EXITING 0x00001000 |
35 | #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 | 35 | #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 |
36 | #define CPU_BASED_CR8_STORE_EXITING 0x00100000 | 36 | #define CPU_BASED_CR8_STORE_EXITING 0x00100000 |
37 | #define CPU_BASED_TPR_SHADOW 0x00200000 | 37 | #define CPU_BASED_TPR_SHADOW 0x00200000 |
38 | #define CPU_BASED_MOV_DR_EXITING 0x00800000 | 38 | #define CPU_BASED_MOV_DR_EXITING 0x00800000 |
39 | #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 | 39 | #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 |
40 | #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000 | 40 | #define CPU_BASED_USE_IO_BITMAPS 0x02000000 |
41 | #define CPU_BASED_MSR_BITMAPS 0x10000000 | 41 | #define CPU_BASED_USE_MSR_BITMAPS 0x10000000 |
42 | #define CPU_BASED_MONITOR_EXITING 0x20000000 | 42 | #define CPU_BASED_MONITOR_EXITING 0x20000000 |
43 | #define CPU_BASED_PAUSE_EXITING 0x40000000 | 43 | #define CPU_BASED_PAUSE_EXITING 0x40000000 |
44 | #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 | ||
44 | 45 | ||
45 | #define PIN_BASED_EXT_INTR_MASK 0x1 | 46 | #define PIN_BASED_EXT_INTR_MASK 0x00000001 |
46 | #define PIN_BASED_NMI_EXITING 0x8 | 47 | #define PIN_BASED_NMI_EXITING 0x00000008 |
48 | #define PIN_BASED_VIRTUAL_NMIS 0x00000020 | ||
47 | 49 | ||
48 | #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 | 50 | #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 |
49 | #define VM_EXIT_HOST_ADD_SPACE_SIZE 0x00000200 | 51 | #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 |
50 | 52 | ||
53 | #define VM_ENTRY_IA32E_MODE 0x00000200 | ||
54 | #define VM_ENTRY_SMM 0x00000400 | ||
55 | #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 | ||
56 | |||
57 | #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 | ||
51 | 58 | ||
52 | /* VMCS Encodings */ | 59 | /* VMCS Encodings */ |
53 | enum vmcs_field { | 60 | enum vmcs_field { |
@@ -285,11 +292,21 @@ enum vmcs_field { | |||
285 | 292 | ||
286 | #define AR_RESERVD_MASK 0xfffe0f00 | 293 | #define AR_RESERVD_MASK 0xfffe0f00 |
287 | 294 | ||
288 | #define MSR_IA32_VMX_BASIC 0x480 | 295 | #define MSR_IA32_VMX_BASIC 0x480 |
289 | #define MSR_IA32_FEATURE_CONTROL 0x03a | 296 | #define MSR_IA32_VMX_PINBASED_CTLS 0x481 |
290 | #define MSR_IA32_VMX_PINBASED_CTLS 0x481 | 297 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 |
291 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 | 298 | #define MSR_IA32_VMX_EXIT_CTLS 0x483 |
292 | #define MSR_IA32_VMX_EXIT_CTLS 0x483 | 299 | #define MSR_IA32_VMX_ENTRY_CTLS 0x484 |
293 | #define MSR_IA32_VMX_ENTRY_CTLS 0x484 | 300 | #define MSR_IA32_VMX_MISC 0x485 |
301 | #define MSR_IA32_VMX_CR0_FIXED0 0x486 | ||
302 | #define MSR_IA32_VMX_CR0_FIXED1 0x487 | ||
303 | #define MSR_IA32_VMX_CR4_FIXED0 0x488 | ||
304 | #define MSR_IA32_VMX_CR4_FIXED1 0x489 | ||
305 | #define MSR_IA32_VMX_VMCS_ENUM 0x48a | ||
306 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b | ||
307 | |||
308 | #define MSR_IA32_FEATURE_CONTROL 0x3a | ||
309 | #define MSR_IA32_FEATURE_CONTROL_LOCKED 0x1 | ||
310 | #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED 0x4 | ||
294 | 311 | ||
295 | #endif | 312 | #endif |