aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/isdn/hisax/hfc_sx.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/isdn/hisax/hfc_sx.c')
-rw-r--r--drivers/isdn/hisax/hfc_sx.c1126
1 files changed, 563 insertions, 563 deletions
diff --git a/drivers/isdn/hisax/hfc_sx.c b/drivers/isdn/hisax/hfc_sx.c
index 156d7c63d944..4db846be4369 100644
--- a/drivers/isdn/hisax/hfc_sx.c
+++ b/drivers/isdn/hisax/hfc_sx.c
@@ -5,7 +5,7 @@
5 * Author Werner Cornelius 5 * Author Werner Cornelius
6 * based on existing driver for CCD HFC PCI cards 6 * based on existing driver for CCD HFC PCI cards
7 * Copyright by Werner Cornelius <werner@isdn4linux.de> 7 * Copyright by Werner Cornelius <werner@isdn4linux.de>
8 * 8 *
9 * This software may be used and distributed according to the terms 9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference. 10 * of the GNU General Public License, incorporated herein by reference.
11 * 11 *
@@ -43,16 +43,16 @@ static const char *hfcsx_revision = "$Revision: 1.12.2.5 $";
43#undef CCD_DEMO_BOARD 43#undef CCD_DEMO_BOARD
44#ifdef CCD_DEMO_BOARD 44#ifdef CCD_DEMO_BOARD
45static u_char ccd_sp_irqtab[16] = { 45static u_char ccd_sp_irqtab[16] = {
46 0,0,0,0,0,2,1,0,0,0,3,4,5,0,0,6 46 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 4, 5, 0, 0, 6
47}; 47};
48#else /* Teles 16.3c */ 48#else /* Teles 16.3c */
49static u_char ccd_sp_irqtab[16] = { 49static u_char ccd_sp_irqtab[16] = {
50 0,0,0,7,0,1,0,0,0,2,3,4,5,0,0,6 50 0, 0, 0, 7, 0, 1, 0, 0, 0, 2, 3, 4, 5, 0, 0, 6
51}; 51};
52#endif 52#endif
53#define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */ 53#define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
54 54
55#define byteout(addr,val) outb(val,addr) 55#define byteout(addr, val) outb(val, addr)
56#define bytein(addr) inb(addr) 56#define bytein(addr) inb(addr)
57 57
58/******************************/ 58/******************************/
@@ -61,19 +61,19 @@ static u_char ccd_sp_irqtab[16] = {
61static inline void 61static inline void
62Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) 62Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val)
63{ 63{
64 byteout(cs->hw.hfcsx.base+1, regnum); 64 byteout(cs->hw.hfcsx.base + 1, regnum);
65 byteout(cs->hw.hfcsx.base, val); 65 byteout(cs->hw.hfcsx.base, val);
66} 66}
67 67
68static inline u_char 68static inline u_char
69Read_hfc(struct IsdnCardState *cs, u_char regnum) 69Read_hfc(struct IsdnCardState *cs, u_char regnum)
70{ 70{
71 u_char ret; 71 u_char ret;
72 72
73 byteout(cs->hw.hfcsx.base+1, regnum); 73 byteout(cs->hw.hfcsx.base + 1, regnum);
74 ret = bytein(cs->hw.hfcsx.base); 74 ret = bytein(cs->hw.hfcsx.base);
75 return(ret); 75 return (ret);
76} 76}
77 77
78 78
79/**************************************************/ 79/**************************************************/
@@ -82,15 +82,15 @@ Read_hfc(struct IsdnCardState *cs, u_char regnum)
82static void 82static void
83fifo_select(struct IsdnCardState *cs, u_char fifo) 83fifo_select(struct IsdnCardState *cs, u_char fifo)
84{ 84{
85 if (fifo == cs->hw.hfcsx.last_fifo) 85 if (fifo == cs->hw.hfcsx.last_fifo)
86 return; /* still valid */ 86 return; /* still valid */
87 87
88 byteout(cs->hw.hfcsx.base+1, HFCSX_FIF_SEL); 88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL);
89 byteout(cs->hw.hfcsx.base, fifo); 89 byteout(cs->hw.hfcsx.base, fifo);
90 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 90 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
91 udelay(4); 91 udelay(4);
92 byteout(cs->hw.hfcsx.base, fifo); 92 byteout(cs->hw.hfcsx.base, fifo);
93 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 93 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
94} 94}
95 95
96/******************************************/ 96/******************************************/
@@ -101,11 +101,11 @@ static void
101reset_fifo(struct IsdnCardState *cs, u_char fifo) 101reset_fifo(struct IsdnCardState *cs, u_char fifo)
102{ 102{
103 fifo_select(cs, fifo); /* first select the fifo */ 103 fifo_select(cs, fifo); /* first select the fifo */
104 byteout(cs->hw.hfcsx.base+1, HFCSX_CIRM); 104 byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM);
105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ 105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
106 udelay(1); 106 udelay(1);
107 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 107 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
108} 108}
109 109
110 110
111/*************************************************************/ 111/*************************************************************/
@@ -116,56 +116,56 @@ reset_fifo(struct IsdnCardState *cs, u_char fifo)
116static int 116static int
117write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max) 117write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max)
118{ 118{
119 unsigned short *msp; 119 unsigned short *msp;
120 int fifo_size, count, z1, z2; 120 int fifo_size, count, z1, z2;
121 u_char f_msk, f1, f2, *src; 121 u_char f_msk, f1, f2, *src;
122 122
123 if (skb->len <= 0) return(0); 123 if (skb->len <= 0) return (0);
124 if (fifo & 1) return(0); /* no write fifo */ 124 if (fifo & 1) return (0); /* no write fifo */
125 125
126 fifo_select(cs, fifo); 126 fifo_select(cs, fifo);
127 if (fifo & 4) { 127 if (fifo & 4) {
128 fifo_size = D_FIFO_SIZE; /* D-channel */ 128 fifo_size = D_FIFO_SIZE; /* D-channel */
129 f_msk = MAX_D_FRAMES; 129 f_msk = MAX_D_FRAMES;
130 if (trans_max) return(0); /* only HDLC */ 130 if (trans_max) return (0); /* only HDLC */
131 } 131 }
132 else { 132 else {
133 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ 133 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
134 f_msk = MAX_B_FRAMES; 134 f_msk = MAX_B_FRAMES;
135 } 135 }
136 136
137 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); 137 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
138 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); 138 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
139 139
140 /* Check for transparent mode */ 140 /* Check for transparent mode */
141 if (trans_max) { 141 if (trans_max) {
142 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); 142 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
143 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); 143 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
144 count = z2 - z1; 144 count = z2 - z1;
145 if (count <= 0) 145 if (count <= 0)
146 count += fifo_size; /* free bytes */ 146 count += fifo_size; /* free bytes */
147 if (count < skb->len+1) return(0); /* no room */ 147 if (count < skb->len + 1) return (0); /* no room */
148 count = fifo_size - count; /* bytes still not send */ 148 count = fifo_size - count; /* bytes still not send */
149 if (count > 2 * trans_max) return(0); /* delay to long */ 149 if (count > 2 * trans_max) return (0); /* delay to long */
150 count = skb->len; 150 count = skb->len;
151 src = skb->data; 151 src = skb->data;
152 while (count--) 152 while (count--)
153 Write_hfc(cs, HFCSX_FIF_DWR, *src++); 153 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
154 return(1); /* success */ 154 return (1); /* success */
155 } 155 }
156 156
157 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker; 157 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker;
158 msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES+1)); 158 msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES + 1));
159 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; 159 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
160 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; 160 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
161 161
162 count = f1 - f2; /* frame count actually buffered */ 162 count = f1 - f2; /* frame count actually buffered */
163 if (count < 0) 163 if (count < 0)
164 count += (f_msk + 1); /* if wrap around */ 164 count += (f_msk + 1); /* if wrap around */
165 if (count > f_msk-1) { 165 if (count > f_msk - 1) {
166 if (cs->debug & L1_DEB_ISAC_FIFO) 166 if (cs->debug & L1_DEB_ISAC_FIFO)
167 debugl1(cs, "hfcsx_write_fifo %d more as %d frames",fifo,f_msk-1); 167 debugl1(cs, "hfcsx_write_fifo %d more as %d frames", fifo, f_msk - 1);
168 return(0); 168 return (0);
169 } 169 }
170 170
171 *(msp + f1) = z1; /* remember marker */ 171 *(msp + f1) = z1; /* remember marker */
@@ -176,134 +176,134 @@ write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans
176 /* now determine free bytes in FIFO buffer */ 176 /* now determine free bytes in FIFO buffer */
177 count = *(msp + f2) - z1; 177 count = *(msp + f2) - z1;
178 if (count <= 0) 178 if (count <= 0)
179 count += fifo_size; /* count now contains available bytes */ 179 count += fifo_size; /* count now contains available bytes */
180 180
181 if (cs->debug & L1_DEB_ISAC_FIFO) 181 if (cs->debug & L1_DEB_ISAC_FIFO)
182 debugl1(cs, "hfcsx_write_fifo %d count(%u/%d)", 182 debugl1(cs, "hfcsx_write_fifo %d count(%u/%d)",
183 fifo, skb->len, count); 183 fifo, skb->len, count);
184 if (count < skb->len) { 184 if (count < skb->len) {
185 if (cs->debug & L1_DEB_ISAC_FIFO) 185 if (cs->debug & L1_DEB_ISAC_FIFO)
186 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo); 186 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo);
187 return(0); 187 return (0);
188 } 188 }
189 189
190 count = skb->len; /* get frame len */ 190 count = skb->len; /* get frame len */
191 src = skb->data; /* source pointer */ 191 src = skb->data; /* source pointer */
192 while (count--) 192 while (count--)
193 Write_hfc(cs, HFCSX_FIF_DWR, *src++); 193 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
194 194
195 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */ 195 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */
196 udelay(1); 196 udelay(1);
197 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 197 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
198 return(1); 198 return (1);
199} 199}
200 200
201/***************************************************************/ 201/***************************************************************/
202/* read_fifo reads data to an skb from the desired fifo */ 202/* read_fifo reads data to an skb from the desired fifo */
203/* if no data is available or an error occurs NULL is returned */ 203/* if no data is available or an error occurs NULL is returned */
204/* the skb is not released in any way. */ 204/* the skb is not released in any way. */
205/***************************************************************/ 205/***************************************************************/
206static struct sk_buff * 206static struct sk_buff *
207read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max) 207read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max)
208{ int fifo_size, count, z1, z2; 208{ int fifo_size, count, z1, z2;
209 u_char f_msk, f1, f2, *dst; 209 u_char f_msk, f1, f2, *dst;
210 struct sk_buff *skb; 210 struct sk_buff *skb;
211 211
212 if (!(fifo & 1)) return(NULL); /* no read fifo */ 212 if (!(fifo & 1)) return (NULL); /* no read fifo */
213 fifo_select(cs, fifo); 213 fifo_select(cs, fifo);
214 if (fifo & 4) { 214 if (fifo & 4) {
215 fifo_size = D_FIFO_SIZE; /* D-channel */ 215 fifo_size = D_FIFO_SIZE; /* D-channel */
216 f_msk = MAX_D_FRAMES; 216 f_msk = MAX_D_FRAMES;
217 if (trans_max) return(NULL); /* only hdlc */ 217 if (trans_max) return (NULL); /* only hdlc */
218 } 218 }
219 else { 219 else {
220 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ 220 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
221 f_msk = MAX_B_FRAMES; 221 f_msk = MAX_B_FRAMES;
222 } 222 }
223 223
224 /* transparent mode */ 224 /* transparent mode */
225 if (trans_max) { 225 if (trans_max) {
226 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); 226 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
227 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); 227 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
228 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); 228 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
229 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); 229 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
230 /* now determine bytes in actual FIFO buffer */ 230 /* now determine bytes in actual FIFO buffer */
231 count = z1 - z2; 231 count = z1 - z2;
232 if (count <= 0) 232 if (count <= 0)
233 count += fifo_size; /* count now contains buffered bytes */ 233 count += fifo_size; /* count now contains buffered bytes */
234 count++; 234 count++;
235 if (count > trans_max) 235 if (count > trans_max)
236 count = trans_max; /* limit length */ 236 count = trans_max; /* limit length */
237 skb = dev_alloc_skb(count); 237 skb = dev_alloc_skb(count);
238 if (skb) { 238 if (skb) {
239 dst = skb_put(skb, count); 239 dst = skb_put(skb, count);
240 while (count--) 240 while (count--)
241 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); 241 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
242 return skb; 242 return skb;
243 } else 243 } else
244 return NULL; /* no memory */ 244 return NULL; /* no memory */
245 } 245 }
246 246
247 do { 247 do {
248 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; 248 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
249 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; 249 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
250 250
251 if (f1 == f2) return(NULL); /* no frame available */ 251 if (f1 == f2) return (NULL); /* no frame available */
252 252
253 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); 253 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
254 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); 254 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
255 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); 255 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
256 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); 256 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
257 257
258 if (cs->debug & L1_DEB_ISAC_FIFO)
259 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)",
260 fifo, f1, f2, z1, z2);
261 /* now determine bytes in actual FIFO buffer */
262 count = z1 - z2;
263 if (count <= 0)
264 count += fifo_size; /* count now contains buffered bytes */
265 count++;
266
267 if (cs->debug & L1_DEB_ISAC_FIFO)
268 debugl1(cs, "hfcsx_read_fifo %d count %u)",
269 fifo, count);
270
271 if ((count > fifo_size) || (count < 4)) {
272 if (cs->debug & L1_DEB_WARN)
273 debugl1(cs, "hfcsx_read_fifo %d paket inv. len %d ", fifo , count);
274 while (count) {
275 count--; /* empty fifo */
276 Read_hfc(cs, HFCSX_FIF_DRD);
277 }
278 skb = NULL;
279 } else
280 if ((skb = dev_alloc_skb(count - 3))) {
281 count -= 3;
282 dst = skb_put(skb, count);
283
284 while (count--)
285 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
286
287 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */
288 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */
289 if (Read_hfc(cs, HFCSX_FIF_DRD)) {
290 dev_kfree_skb_irq(skb);
291 if (cs->debug & L1_DEB_ISAC_FIFO) 258 if (cs->debug & L1_DEB_ISAC_FIFO)
292 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo); 259 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)",
293 skb = NULL; 260 fifo, f1, f2, z1, z2);
294 } 261 /* now determine bytes in actual FIFO buffer */
295 } else { 262 count = z1 - z2;
296 printk(KERN_WARNING "HFC-SX: receive out of memory\n"); 263 if (count <= 0)
297 return(NULL); 264 count += fifo_size; /* count now contains buffered bytes */
298 } 265 count++;
299 266
300 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */ 267 if (cs->debug & L1_DEB_ISAC_FIFO)
301 udelay(1); 268 debugl1(cs, "hfcsx_read_fifo %d count %u)",
302 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ 269 fifo, count);
303 udelay(1); 270
271 if ((count > fifo_size) || (count < 4)) {
272 if (cs->debug & L1_DEB_WARN)
273 debugl1(cs, "hfcsx_read_fifo %d paket inv. len %d ", fifo , count);
274 while (count) {
275 count--; /* empty fifo */
276 Read_hfc(cs, HFCSX_FIF_DRD);
277 }
278 skb = NULL;
279 } else
280 if ((skb = dev_alloc_skb(count - 3))) {
281 count -= 3;
282 dst = skb_put(skb, count);
283
284 while (count--)
285 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
286
287 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */
288 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */
289 if (Read_hfc(cs, HFCSX_FIF_DRD)) {
290 dev_kfree_skb_irq(skb);
291 if (cs->debug & L1_DEB_ISAC_FIFO)
292 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo);
293 skb = NULL;
294 }
295 } else {
296 printk(KERN_WARNING "HFC-SX: receive out of memory\n");
297 return (NULL);
298 }
299
300 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */
301 udelay(1);
302 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
303 udelay(1);
304 } while (!skb); /* retry in case of crc error */ 304 } while (!skb); /* retry in case of crc error */
305 return(skb); 305 return (skb);
306} 306}
307 307
308/******************************************/ 308/******************************************/
309/* free hardware resources used by driver */ 309/* free hardware resources used by driver */
@@ -328,17 +328,17 @@ release_io_hfcsx(struct IsdnCardState *cs)
328/**********************************************************/ 328/**********************************************************/
329static int set_fifo_size(struct IsdnCardState *cs) 329static int set_fifo_size(struct IsdnCardState *cs)
330{ 330{
331 331
332 if (cs->hw.hfcsx.b_fifo_size) return(1); /* already determined */ 332 if (cs->hw.hfcsx.b_fifo_size) return (1); /* already determined */
333 333
334 if ((cs->hw.hfcsx.chip >> 4) == 9) { 334 if ((cs->hw.hfcsx.chip >> 4) == 9) {
335 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K; 335 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K;
336 return(1); 336 return (1);
337 } 337 }
338 338
339 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K; 339 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K;
340 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */ 340 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */
341 return(0); 341 return (0);
342 342
343} 343}
344 344
@@ -354,15 +354,15 @@ reset_hfcsx(struct IsdnCardState *cs)
354 354
355 printk(KERN_INFO "HFC_SX: resetting card\n"); 355 printk(KERN_INFO "HFC_SX: resetting card\n");
356 while (1) { 356 while (1) {
357 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */ 357 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm); /* Reset */
358 mdelay(30); 358 mdelay(30);
359 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ 359 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */
360 mdelay(20); 360 mdelay(20);
361 if (Read_hfc(cs, HFCSX_STATUS) & 2) 361 if (Read_hfc(cs, HFCSX_STATUS) & 2)
362 printk(KERN_WARNING "HFC-SX init bit busy\n"); 362 printk(KERN_WARNING "HFC-SX init bit busy\n");
363 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */ 363 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */
364 if (!set_fifo_size(cs)) continue; 364 if (!set_fifo_size(cs)) continue;
365 break; 365 break;
366 } 366 }
367 367
368 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */ 368 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */
@@ -376,8 +376,8 @@ reset_hfcsx(struct IsdnCardState *cs)
376 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER; 376 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER;
377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); 377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
378 378
379 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC | 379 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC |
380 HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER; 380 HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER;
381 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 381 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
382 382
383 /* Clear already pending ints */ 383 /* Clear already pending ints */
@@ -423,8 +423,8 @@ hfcsx_Timer(struct IsdnCardState *cs)
423 cs->hw.hfcsx.timer.expires = jiffies + 75; 423 cs->hw.hfcsx.timer.expires = jiffies + 75;
424 /* WD RESET */ 424 /* WD RESET */
425/* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80); 425/* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80);
426 add_timer(&cs->hw.hfcsx.timer); 426 add_timer(&cs->hw.hfcsx.timer);
427 */ 427*/
428} 428}
429 429
430/************************************************/ 430/************************************************/
@@ -458,11 +458,11 @@ receive_dmsg(struct IsdnCardState *cs)
458 } 458 }
459 459
460 do { 460 do {
461 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0); 461 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0);
462 if (skb) { 462 if (skb) {
463 skb_queue_tail(&cs->rq, skb); 463 skb_queue_tail(&cs->rq, skb);
464 schedule_event(cs, D_RCVBUFREADY); 464 schedule_event(cs, D_RCVBUFREADY);
465 } 465 }
466 } while (--count && skb); 466 } while (--count && skb);
467 467
468 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 468 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
@@ -479,20 +479,20 @@ main_rec_hfcsx(struct BCState *bcs)
479 int count = 5; 479 int count = 5;
480 struct sk_buff *skb; 480 struct sk_buff *skb;
481 481
482 Begin: 482Begin:
483 count--; 483 count--;
484 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 484 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
485 debugl1(cs, "rec_data %d blocked", bcs->channel); 485 debugl1(cs, "rec_data %d blocked", bcs->channel);
486 return; 486 return;
487 } 487 }
488 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? 488 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
489 HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX, 489 HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX,
490 (bcs->mode == L1_MODE_TRANS) ? 490 (bcs->mode == L1_MODE_TRANS) ?
491 HFCSX_BTRANS_THRESHOLD : 0); 491 HFCSX_BTRANS_THRESHOLD : 0);
492 492
493 if (skb) { 493 if (skb) {
494 skb_queue_tail(&bcs->rqueue, skb); 494 skb_queue_tail(&bcs->rqueue, skb);
495 schedule_event(bcs, B_RCVBUFREADY); 495 schedule_event(bcs, B_RCVBUFREADY);
496 } 496 }
497 497
498 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 498 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
@@ -513,8 +513,8 @@ hfcsx_fill_dfifo(struct IsdnCardState *cs)
513 return; 513 return;
514 514
515 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) { 515 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) {
516 dev_kfree_skb_any(cs->tx_skb); 516 dev_kfree_skb_any(cs->tx_skb);
517 cs->tx_skb = NULL; 517 cs->tx_skb = NULL;
518 } 518 }
519 return; 519 return;
520} 520}
@@ -532,24 +532,24 @@ hfcsx_fill_fifo(struct BCState *bcs)
532 if (bcs->tx_skb->len <= 0) 532 if (bcs->tx_skb->len <= 0)
533 return; 533 return;
534 534
535 if (write_fifo(cs, bcs->tx_skb, 535 if (write_fifo(cs, bcs->tx_skb,
536 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? 536 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
537 HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX, 537 HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX,
538 (bcs->mode == L1_MODE_TRANS) ? 538 (bcs->mode == L1_MODE_TRANS) ?
539 HFCSX_BTRANS_THRESHOLD : 0)) { 539 HFCSX_BTRANS_THRESHOLD : 0)) {
540 540
541 bcs->tx_cnt -= bcs->tx_skb->len; 541 bcs->tx_cnt -= bcs->tx_skb->len;
542 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) && 542 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
543 (PACKET_NOACK != bcs->tx_skb->pkt_type)) { 543 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
544 u_long flags; 544 u_long flags;
545 spin_lock_irqsave(&bcs->aclock, flags); 545 spin_lock_irqsave(&bcs->aclock, flags);
546 bcs->ackcnt += bcs->tx_skb->len; 546 bcs->ackcnt += bcs->tx_skb->len;
547 spin_unlock_irqrestore(&bcs->aclock, flags); 547 spin_unlock_irqrestore(&bcs->aclock, flags);
548 schedule_event(bcs, B_ACKPENDING); 548 schedule_event(bcs, B_ACKPENDING);
549 } 549 }
550 dev_kfree_skb_any(bcs->tx_skb); 550 dev_kfree_skb_any(bcs->tx_skb);
551 bcs->tx_skb = NULL; 551 bcs->tx_skb = NULL;
552 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); 552 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
553 } 553 }
554} 554}
555 555
@@ -562,27 +562,27 @@ dch_nt_l2l1(struct PStack *st, int pr, void *arg)
562 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; 562 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
563 563
564 switch (pr) { 564 switch (pr) {
565 case (PH_DATA | REQUEST): 565 case (PH_DATA | REQUEST):
566 case (PH_PULL | REQUEST): 566 case (PH_PULL | REQUEST):
567 case (PH_PULL | INDICATION): 567 case (PH_PULL | INDICATION):
568 st->l1.l1hw(st, pr, arg); 568 st->l1.l1hw(st, pr, arg);
569 break; 569 break;
570 case (PH_ACTIVATE | REQUEST): 570 case (PH_ACTIVATE | REQUEST):
571 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL); 571 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
572 break; 572 break;
573 case (PH_TESTLOOP | REQUEST): 573 case (PH_TESTLOOP | REQUEST):
574 if (1 & (long) arg) 574 if (1 & (long) arg)
575 debugl1(cs, "PH_TEST_LOOP B1"); 575 debugl1(cs, "PH_TEST_LOOP B1");
576 if (2 & (long) arg) 576 if (2 & (long) arg)
577 debugl1(cs, "PH_TEST_LOOP B2"); 577 debugl1(cs, "PH_TEST_LOOP B2");
578 if (!(3 & (long) arg)) 578 if (!(3 & (long) arg))
579 debugl1(cs, "PH_TEST_LOOP DISABLED"); 579 debugl1(cs, "PH_TEST_LOOP DISABLED");
580 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg); 580 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
581 break; 581 break;
582 default: 582 default:
583 if (cs->debug) 583 if (cs->debug)
584 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr); 584 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
585 break; 585 break;
586 } 586 }
587} 587}
588 588
@@ -592,14 +592,14 @@ dch_nt_l2l1(struct PStack *st, int pr, void *arg)
592/* set/reset echo mode */ 592/* set/reset echo mode */
593/***********************/ 593/***********************/
594static int 594static int
595hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic) 595hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic)
596{ 596{
597 unsigned long flags; 597 unsigned long flags;
598 int i = *(unsigned int *) ic->parm.num; 598 int i = *(unsigned int *) ic->parm.num;
599 599
600 if ((ic->arg == 98) && 600 if ((ic->arg == 98) &&
601 (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) { 601 (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) {
602 spin_lock_irqsave(&cs->lock, flags); 602 spin_lock_irqsave(&cs->lock, flags);
603 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */ 603 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */
604 udelay(10); 604 udelay(10);
605 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT; 605 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT;
@@ -660,26 +660,26 @@ receive_emsg(struct IsdnCardState *cs)
660 return; 660 return;
661 } 661 }
662 do { 662 do {
663 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0); 663 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0);
664 if (skb) { 664 if (skb) {
665 if (cs->debug & DEB_DLOG_HEX) { 665 if (cs->debug & DEB_DLOG_HEX) {
666 ptr = cs->dlog; 666 ptr = cs->dlog;
667 if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) { 667 if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) {
668 *ptr++ = 'E'; 668 *ptr++ = 'E';
669 *ptr++ = 'C'; 669 *ptr++ = 'C';
670 *ptr++ = 'H'; 670 *ptr++ = 'H';
671 *ptr++ = 'O'; 671 *ptr++ = 'O';
672 *ptr++ = ':'; 672 *ptr++ = ':';
673 ptr += QuickHex(ptr, skb->data, skb->len); 673 ptr += QuickHex(ptr, skb->data, skb->len);
674 ptr--; 674 ptr--;
675 *ptr++ = '\n'; 675 *ptr++ = '\n';
676 *ptr = 0; 676 *ptr = 0;
677 HiSax_putstatus(cs, NULL, cs->dlog); 677 HiSax_putstatus(cs, NULL, cs->dlog);
678 } else 678 } else
679 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len); 679 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);
680 } 680 }
681 dev_kfree_skb_any(skb); 681 dev_kfree_skb_any(skb);
682 } 682 }
683 } while (--count && skb); 683 } while (--count && skb);
684 684
685 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 685 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
@@ -843,7 +843,7 @@ hfcsx_interrupt(int intno, void *dev_id)
843 } else 843 } else
844 schedule_event(cs, D_XMTBUFREADY); 844 schedule_event(cs, D_XMTBUFREADY);
845 } 845 }
846 afterXPR: 846 afterXPR:
847 if (cs->hw.hfcsx.int_s1 && count--) { 847 if (cs->hw.hfcsx.int_s1 && count--) {
848 val = cs->hw.hfcsx.int_s1; 848 val = cs->hw.hfcsx.int_s1;
849 cs->hw.hfcsx.int_s1 = 0; 849 cs->hw.hfcsx.int_s1 = 0;
@@ -875,128 +875,128 @@ HFCSX_l1hw(struct PStack *st, int pr, void *arg)
875 u_long flags; 875 u_long flags;
876 876
877 switch (pr) { 877 switch (pr) {
878 case (PH_DATA | REQUEST): 878 case (PH_DATA | REQUEST):
879 if (cs->debug & DEB_DLOG_HEX) 879 if (cs->debug & DEB_DLOG_HEX)
880 LogFrame(cs, skb->data, skb->len); 880 LogFrame(cs, skb->data, skb->len);
881 if (cs->debug & DEB_DLOG_VERBOSE) 881 if (cs->debug & DEB_DLOG_VERBOSE)
882 dlogframe(cs, skb, 0); 882 dlogframe(cs, skb, 0);
883 spin_lock_irqsave(&cs->lock, flags); 883 spin_lock_irqsave(&cs->lock, flags);
884 if (cs->tx_skb) { 884 if (cs->tx_skb) {
885 skb_queue_tail(&cs->sq, skb); 885 skb_queue_tail(&cs->sq, skb);
886#ifdef L2FRAME_DEBUG /* psa */
887 if (cs->debug & L1_DEB_LAPD)
888 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
889#endif
890 } else {
891 cs->tx_skb = skb;
892 cs->tx_cnt = 0;
893#ifdef L2FRAME_DEBUG /* psa */ 886#ifdef L2FRAME_DEBUG /* psa */
894 if (cs->debug & L1_DEB_LAPD) 887 if (cs->debug & L1_DEB_LAPD)
895 Logl2Frame(cs, skb, "PH_DATA", 0); 888 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
896#endif 889#endif
897 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 890 } else {
898 hfcsx_fill_dfifo(cs);
899 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
900 } else
901 debugl1(cs, "hfcsx_fill_dfifo blocked");
902
903 }
904 spin_unlock_irqrestore(&cs->lock, flags);
905 break;
906 case (PH_PULL | INDICATION):
907 spin_lock_irqsave(&cs->lock, flags);
908 if (cs->tx_skb) {
909 if (cs->debug & L1_DEB_WARN)
910 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
911 skb_queue_tail(&cs->sq, skb);
912 spin_unlock_irqrestore(&cs->lock, flags);
913 break;
914 }
915 if (cs->debug & DEB_DLOG_HEX)
916 LogFrame(cs, skb->data, skb->len);
917 if (cs->debug & DEB_DLOG_VERBOSE)
918 dlogframe(cs, skb, 0);
919 cs->tx_skb = skb; 891 cs->tx_skb = skb;
920 cs->tx_cnt = 0; 892 cs->tx_cnt = 0;
921#ifdef L2FRAME_DEBUG /* psa */ 893#ifdef L2FRAME_DEBUG /* psa */
922 if (cs->debug & L1_DEB_LAPD) 894 if (cs->debug & L1_DEB_LAPD)
923 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); 895 Logl2Frame(cs, skb, "PH_DATA", 0);
924#endif 896#endif
925 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 897 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
926 hfcsx_fill_dfifo(cs); 898 hfcsx_fill_dfifo(cs);
927 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 899 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
928 } else 900 } else
929 debugl1(cs, "hfcsx_fill_dfifo blocked"); 901 debugl1(cs, "hfcsx_fill_dfifo blocked");
902
903 }
904 spin_unlock_irqrestore(&cs->lock, flags);
905 break;
906 case (PH_PULL | INDICATION):
907 spin_lock_irqsave(&cs->lock, flags);
908 if (cs->tx_skb) {
909 if (cs->debug & L1_DEB_WARN)
910 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
911 skb_queue_tail(&cs->sq, skb);
930 spin_unlock_irqrestore(&cs->lock, flags); 912 spin_unlock_irqrestore(&cs->lock, flags);
931 break; 913 break;
932 case (PH_PULL | REQUEST): 914 }
915 if (cs->debug & DEB_DLOG_HEX)
916 LogFrame(cs, skb->data, skb->len);
917 if (cs->debug & DEB_DLOG_VERBOSE)
918 dlogframe(cs, skb, 0);
919 cs->tx_skb = skb;
920 cs->tx_cnt = 0;
933#ifdef L2FRAME_DEBUG /* psa */ 921#ifdef L2FRAME_DEBUG /* psa */
934 if (cs->debug & L1_DEB_LAPD) 922 if (cs->debug & L1_DEB_LAPD)
935 debugl1(cs, "-> PH_REQUEST_PULL"); 923 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
936#endif 924#endif
937 if (!cs->tx_skb) { 925 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
938 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 926 hfcsx_fill_dfifo(cs);
939 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); 927 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
940 } else 928 } else
941 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 929 debugl1(cs, "hfcsx_fill_dfifo blocked");
942 break; 930 spin_unlock_irqrestore(&cs->lock, flags);
943 case (HW_RESET | REQUEST): 931 break;
944 spin_lock_irqsave(&cs->lock, flags); 932 case (PH_PULL | REQUEST):
945 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */ 933#ifdef L2FRAME_DEBUG /* psa */
946 udelay(6); 934 if (cs->debug & L1_DEB_LAPD)
947 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */ 935 debugl1(cs, "-> PH_REQUEST_PULL");
948 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; 936#endif
949 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 937 if (!cs->tx_skb) {
950 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); 938 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
951 spin_unlock_irqrestore(&cs->lock, flags); 939 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
952 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); 940 } else
953 break; 941 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
954 case (HW_ENABLE | REQUEST): 942 break;
955 spin_lock_irqsave(&cs->lock, flags); 943 case (HW_RESET | REQUEST):
956 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); 944 spin_lock_irqsave(&cs->lock, flags);
957 spin_unlock_irqrestore(&cs->lock, flags); 945 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */
958 break; 946 udelay(6);
959 case (HW_DEACTIVATE | REQUEST): 947 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */
960 spin_lock_irqsave(&cs->lock, flags); 948 cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
961 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER; 949 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
962 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 950 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
963 spin_unlock_irqrestore(&cs->lock, flags); 951 spin_unlock_irqrestore(&cs->lock, flags);
964 break; 952 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
965 case (HW_INFO3 | REQUEST): 953 break;
966 spin_lock_irqsave(&cs->lock, flags); 954 case (HW_ENABLE | REQUEST):
967 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; 955 spin_lock_irqsave(&cs->lock, flags);
968 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 956 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
969 spin_unlock_irqrestore(&cs->lock, flags); 957 spin_unlock_irqrestore(&cs->lock, flags);
958 break;
959 case (HW_DEACTIVATE | REQUEST):
960 spin_lock_irqsave(&cs->lock, flags);
961 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER;
962 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
963 spin_unlock_irqrestore(&cs->lock, flags);
964 break;
965 case (HW_INFO3 | REQUEST):
966 spin_lock_irqsave(&cs->lock, flags);
967 cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
968 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
969 spin_unlock_irqrestore(&cs->lock, flags);
970 break;
971 case (HW_TESTLOOP | REQUEST):
972 spin_lock_irqsave(&cs->lock, flags);
973 switch ((long) arg) {
974 case (1):
975 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */
976 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */
977 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1;
978 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
970 break; 979 break;
971 case (HW_TESTLOOP | REQUEST): 980 case (2):
972 spin_lock_irqsave(&cs->lock, flags); 981 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */
973 switch ((long) arg) { 982 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */
974 case (1): 983 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08;
975 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */ 984 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
976 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */
977 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1;
978 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
979 break;
980 case (2):
981 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */
982 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */
983 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08;
984 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
985 break;
986 default:
987 spin_unlock_irqrestore(&cs->lock, flags);
988 if (cs->debug & L1_DEB_WARN)
989 debugl1(cs, "hfcsx_l1hw loop invalid %4lx", (unsigned long)arg);
990 return;
991 }
992 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */
993 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
994 spin_unlock_irqrestore(&cs->lock, flags);
995 break; 985 break;
996 default: 986 default:
987 spin_unlock_irqrestore(&cs->lock, flags);
997 if (cs->debug & L1_DEB_WARN) 988 if (cs->debug & L1_DEB_WARN)
998 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr); 989 debugl1(cs, "hfcsx_l1hw loop invalid %4lx", (unsigned long)arg);
999 break; 990 return;
991 }
992 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */
993 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
994 spin_unlock_irqrestore(&cs->lock, flags);
995 break;
996 default:
997 if (cs->debug & L1_DEB_WARN)
998 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr);
999 break;
1000 } 1000 }
1001} 1001}
1002 1002
@@ -1018,7 +1018,7 @@ hfcsx_send_data(struct BCState *bcs)
1018 struct IsdnCardState *cs = bcs->cs; 1018 struct IsdnCardState *cs = bcs->cs;
1019 1019
1020 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { 1020 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1021 hfcsx_fill_fifo(bcs); 1021 hfcsx_fill_fifo(bcs);
1022 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); 1022 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1023 } else 1023 } else
1024 debugl1(cs, "send_data %d blocked", bcs->channel); 1024 debugl1(cs, "send_data %d blocked", bcs->channel);
@@ -1058,69 +1058,69 @@ mode_hfcsx(struct BCState *bcs, int mode, int bc)
1058 } 1058 }
1059 } 1059 }
1060 switch (mode) { 1060 switch (mode) {
1061 case (L1_MODE_NULL): 1061 case (L1_MODE_NULL):
1062 if (bc) { 1062 if (bc) {
1063 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; 1063 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
1064 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; 1064 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
1065 } else { 1065 } else {
1066 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA; 1066 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA;
1067 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA; 1067 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA;
1068 } 1068 }
1069 if (fifo2) { 1069 if (fifo2) {
1070 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); 1070 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1071 } else { 1071 } else {
1072 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); 1072 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1073 } 1073 }
1074 break; 1074 break;
1075 case (L1_MODE_TRANS): 1075 case (L1_MODE_TRANS):
1076 if (bc) { 1076 if (bc) {
1077 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; 1077 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1078 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; 1078 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1079 } else { 1079 } else {
1080 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; 1080 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1081 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; 1081 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1082 } 1082 }
1083 if (fifo2) { 1083 if (fifo2) {
1084 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); 1084 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1085 cs->hw.hfcsx.ctmt |= 2; 1085 cs->hw.hfcsx.ctmt |= 2;
1086 cs->hw.hfcsx.conn &= ~0x18; 1086 cs->hw.hfcsx.conn &= ~0x18;
1087 } else { 1087 } else {
1088 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); 1088 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1089 cs->hw.hfcsx.ctmt |= 1; 1089 cs->hw.hfcsx.ctmt |= 1;
1090 cs->hw.hfcsx.conn &= ~0x03; 1090 cs->hw.hfcsx.conn &= ~0x03;
1091 } 1091 }
1092 break; 1092 break;
1093 case (L1_MODE_HDLC): 1093 case (L1_MODE_HDLC):
1094 if (bc) { 1094 if (bc) {
1095 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; 1095 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1096 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; 1096 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1097 } else { 1097 } else {
1098 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; 1098 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1099 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; 1099 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1100 } 1100 }
1101 if (fifo2) { 1101 if (fifo2) {
1102 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); 1102 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1103 cs->hw.hfcsx.ctmt &= ~2; 1103 cs->hw.hfcsx.ctmt &= ~2;
1104 cs->hw.hfcsx.conn &= ~0x18; 1104 cs->hw.hfcsx.conn &= ~0x18;
1105 } else { 1105 } else {
1106 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); 1106 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1107 cs->hw.hfcsx.ctmt &= ~1; 1107 cs->hw.hfcsx.ctmt &= ~1;
1108 cs->hw.hfcsx.conn &= ~0x03; 1108 cs->hw.hfcsx.conn &= ~0x03;
1109 } 1109 }
1110 break; 1110 break;
1111 case (L1_MODE_EXTRN): 1111 case (L1_MODE_EXTRN):
1112 if (bc) { 1112 if (bc) {
1113 cs->hw.hfcsx.conn |= 0x10; 1113 cs->hw.hfcsx.conn |= 0x10;
1114 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; 1114 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1115 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; 1115 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1116 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); 1116 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1117 } else { 1117 } else {
1118 cs->hw.hfcsx.conn |= 0x02; 1118 cs->hw.hfcsx.conn |= 0x02;
1119 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; 1119 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1120 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; 1120 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1121 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); 1121 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1122 } 1122 }
1123 break; 1123 break;
1124 } 1124 }
1125 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); 1125 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);
1126 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1126 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
@@ -1129,8 +1129,8 @@ mode_hfcsx(struct BCState *bcs, int mode, int bc)
1129 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); 1129 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
1130 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); 1130 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1131 if (mode != L1_MODE_EXTRN) { 1131 if (mode != L1_MODE_EXTRN) {
1132 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX); 1132 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX);
1133 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX); 1133 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX);
1134 } 1134 }
1135} 1135}
1136 1136
@@ -1145,53 +1145,53 @@ hfcsx_l2l1(struct PStack *st, int pr, void *arg)
1145 u_long flags; 1145 u_long flags;
1146 1146
1147 switch (pr) { 1147 switch (pr) {
1148 case (PH_DATA | REQUEST): 1148 case (PH_DATA | REQUEST):
1149 spin_lock_irqsave(&bcs->cs->lock, flags); 1149 spin_lock_irqsave(&bcs->cs->lock, flags);
1150 if (bcs->tx_skb) { 1150 if (bcs->tx_skb) {
1151 skb_queue_tail(&bcs->squeue, skb); 1151 skb_queue_tail(&bcs->squeue, skb);
1152 } else { 1152 } else {
1153 bcs->tx_skb = skb; 1153 bcs->tx_skb = skb;
1154// test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); 1154// test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1155 bcs->cs->BC_Send_Data(bcs); 1155 bcs->cs->BC_Send_Data(bcs);
1156 } 1156 }
1157 spin_unlock_irqrestore(&bcs->cs->lock, flags); 1157 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1158 break; 1158 break;
1159 case (PH_PULL | INDICATION): 1159 case (PH_PULL | INDICATION):
1160 spin_lock_irqsave(&bcs->cs->lock, flags); 1160 spin_lock_irqsave(&bcs->cs->lock, flags);
1161 if (bcs->tx_skb) { 1161 if (bcs->tx_skb) {
1162 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n"); 1162 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1163 } else { 1163 } else {
1164// test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); 1164// test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1165 bcs->tx_skb = skb; 1165 bcs->tx_skb = skb;
1166 bcs->cs->BC_Send_Data(bcs); 1166 bcs->cs->BC_Send_Data(bcs);
1167 } 1167 }
1168 spin_unlock_irqrestore(&bcs->cs->lock, flags); 1168 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1169 break; 1169 break;
1170 case (PH_PULL | REQUEST): 1170 case (PH_PULL | REQUEST):
1171 if (!bcs->tx_skb) { 1171 if (!bcs->tx_skb) {
1172 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 1172 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1173 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); 1173 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1174 } else 1174 } else
1175 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); 1175 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1176 break; 1176 break;
1177 case (PH_ACTIVATE | REQUEST): 1177 case (PH_ACTIVATE | REQUEST):
1178 spin_lock_irqsave(&bcs->cs->lock, flags); 1178 spin_lock_irqsave(&bcs->cs->lock, flags);
1179 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag); 1179 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1180 mode_hfcsx(bcs, st->l1.mode, st->l1.bc); 1180 mode_hfcsx(bcs, st->l1.mode, st->l1.bc);
1181 spin_unlock_irqrestore(&bcs->cs->lock, flags); 1181 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1182 l1_msg_b(st, pr, arg); 1182 l1_msg_b(st, pr, arg);
1183 break; 1183 break;
1184 case (PH_DEACTIVATE | REQUEST): 1184 case (PH_DEACTIVATE | REQUEST):
1185 l1_msg_b(st, pr, arg); 1185 l1_msg_b(st, pr, arg);
1186 break; 1186 break;
1187 case (PH_DEACTIVATE | CONFIRM): 1187 case (PH_DEACTIVATE | CONFIRM):
1188 spin_lock_irqsave(&bcs->cs->lock, flags); 1188 spin_lock_irqsave(&bcs->cs->lock, flags);
1189 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag); 1189 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1190 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); 1190 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1191 mode_hfcsx(bcs, 0, st->l1.bc); 1191 mode_hfcsx(bcs, 0, st->l1.bc);
1192 spin_unlock_irqrestore(&bcs->cs->lock, flags); 1192 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1193 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL); 1193 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1194 break; 1194 break;
1195 } 1195 }
1196} 1196}
1197 1197
@@ -1260,61 +1260,61 @@ hfcsx_bh(struct work_struct *work)
1260 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { 1260 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1261 if (!cs->hw.hfcsx.nt_mode) 1261 if (!cs->hw.hfcsx.nt_mode)
1262 switch (cs->dc.hfcsx.ph_state) { 1262 switch (cs->dc.hfcsx.ph_state) {
1263 case (0): 1263 case (0):
1264 l1_msg(cs, HW_RESET | INDICATION, NULL); 1264 l1_msg(cs, HW_RESET | INDICATION, NULL);
1265 break; 1265 break;
1266 case (3): 1266 case (3):
1267 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); 1267 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1268 break; 1268 break;
1269 case (8): 1269 case (8):
1270 l1_msg(cs, HW_RSYNC | INDICATION, NULL); 1270 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1271 break; 1271 break;
1272 case (6): 1272 case (6):
1273 l1_msg(cs, HW_INFO2 | INDICATION, NULL); 1273 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1274 break; 1274 break;
1275 case (7): 1275 case (7):
1276 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); 1276 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1277 break; 1277 break;
1278 default: 1278 default:
1279 break; 1279 break;
1280 } else { 1280 } else {
1281 switch (cs->dc.hfcsx.ph_state) { 1281 switch (cs->dc.hfcsx.ph_state) {
1282 case (2): 1282 case (2):
1283 spin_lock_irqsave(&cs->lock, flags); 1283 spin_lock_irqsave(&cs->lock, flags);
1284 if (cs->hw.hfcsx.nt_timer < 0) { 1284 if (cs->hw.hfcsx.nt_timer < 0) {
1285 cs->hw.hfcsx.nt_timer = 0;
1286 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1287 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1288 /* Clear already pending ints */
1289 if (Read_hfc(cs, HFCSX_INT_S1));
1290
1291 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1292 udelay(10);
1293 Write_hfc(cs, HFCSX_STATES, 4);
1294 cs->dc.hfcsx.ph_state = 4;
1295 } else {
1296 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER;
1297 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1298 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER;
1299 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125;
1300 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1301 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1302 cs->hw.hfcsx.nt_timer = NT_T1_COUNT;
1303 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */
1304 }
1305 spin_unlock_irqrestore(&cs->lock, flags);
1306 break;
1307 case (1):
1308 case (3):
1309 case (4):
1310 spin_lock_irqsave(&cs->lock, flags);
1311 cs->hw.hfcsx.nt_timer = 0; 1285 cs->hw.hfcsx.nt_timer = 0;
1312 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; 1286 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1313 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1287 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1314 spin_unlock_irqrestore(&cs->lock, flags); 1288 /* Clear already pending ints */
1315 break; 1289 if (Read_hfc(cs, HFCSX_INT_S1));
1316 default: 1290
1317 break; 1291 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1292 udelay(10);
1293 Write_hfc(cs, HFCSX_STATES, 4);
1294 cs->dc.hfcsx.ph_state = 4;
1295 } else {
1296 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER;
1297 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1298 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER;
1299 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125;
1300 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1301 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1302 cs->hw.hfcsx.nt_timer = NT_T1_COUNT;
1303 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */
1304 }
1305 spin_unlock_irqrestore(&cs->lock, flags);
1306 break;
1307 case (1):
1308 case (3):
1309 case (4):
1310 spin_lock_irqsave(&cs->lock, flags);
1311 cs->hw.hfcsx.nt_timer = 0;
1312 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1313 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1314 spin_unlock_irqrestore(&cs->lock, flags);
1315 break;
1316 default:
1317 break;
1318 } 1318 }
1319 } 1319 }
1320 } 1320 }
@@ -1353,29 +1353,29 @@ hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1353 if (cs->debug & L1_DEB_ISAC) 1353 if (cs->debug & L1_DEB_ISAC)
1354 debugl1(cs, "HFCSX: card_msg %x", mt); 1354 debugl1(cs, "HFCSX: card_msg %x", mt);
1355 switch (mt) { 1355 switch (mt) {
1356 case CARD_RESET: 1356 case CARD_RESET:
1357 spin_lock_irqsave(&cs->lock, flags); 1357 spin_lock_irqsave(&cs->lock, flags);
1358 reset_hfcsx(cs); 1358 reset_hfcsx(cs);
1359 spin_unlock_irqrestore(&cs->lock, flags); 1359 spin_unlock_irqrestore(&cs->lock, flags);
1360 return (0); 1360 return (0);
1361 case CARD_RELEASE: 1361 case CARD_RELEASE:
1362 release_io_hfcsx(cs); 1362 release_io_hfcsx(cs);
1363 return (0); 1363 return (0);
1364 case CARD_INIT: 1364 case CARD_INIT:
1365 spin_lock_irqsave(&cs->lock, flags); 1365 spin_lock_irqsave(&cs->lock, flags);
1366 inithfcsx(cs); 1366 inithfcsx(cs);
1367 spin_unlock_irqrestore(&cs->lock, flags); 1367 spin_unlock_irqrestore(&cs->lock, flags);
1368 msleep(80); /* Timeout 80ms */ 1368 msleep(80); /* Timeout 80ms */
1369 /* now switch timer interrupt off */ 1369 /* now switch timer interrupt off */
1370 spin_lock_irqsave(&cs->lock, flags); 1370 spin_lock_irqsave(&cs->lock, flags);
1371 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; 1371 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1372 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1372 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1373 /* reinit mode reg */ 1373 /* reinit mode reg */
1374 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); 1374 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1375 spin_unlock_irqrestore(&cs->lock, flags); 1375 spin_unlock_irqrestore(&cs->lock, flags);
1376 return (0); 1376 return (0);
1377 case CARD_TEST: 1377 case CARD_TEST:
1378 return (0); 1378 return (0);
1379 } 1379 }
1380 return (0); 1380 return (0);
1381} 1381}
@@ -1383,7 +1383,7 @@ hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1383#ifdef __ISAPNP__ 1383#ifdef __ISAPNP__
1384static struct isapnp_device_id hfc_ids[] __devinitdata = { 1384static struct isapnp_device_id hfc_ids[] __devinitdata = {
1385 { ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620), 1385 { ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1386 ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620), 1386 ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1387 (unsigned long) "Teles 16.3c2" }, 1387 (unsigned long) "Teles 16.3c2" },
1388 { 0, } 1388 { 0, }
1389}; 1389};
@@ -1403,30 +1403,30 @@ setup_hfcsx(struct IsdnCard *card)
1403#ifdef __ISAPNP__ 1403#ifdef __ISAPNP__
1404 if (!card->para[1] && isapnp_present()) { 1404 if (!card->para[1] && isapnp_present()) {
1405 struct pnp_dev *pnp_d; 1405 struct pnp_dev *pnp_d;
1406 while(ipid->card_vendor) { 1406 while (ipid->card_vendor) {
1407 if ((pnp_c = pnp_find_card(ipid->card_vendor, 1407 if ((pnp_c = pnp_find_card(ipid->card_vendor,
1408 ipid->card_device, pnp_c))) { 1408 ipid->card_device, pnp_c))) {
1409 pnp_d = NULL; 1409 pnp_d = NULL;
1410 if ((pnp_d = pnp_find_dev(pnp_c, 1410 if ((pnp_d = pnp_find_dev(pnp_c,
1411 ipid->vendor, ipid->function, pnp_d))) { 1411 ipid->vendor, ipid->function, pnp_d))) {
1412 int err; 1412 int err;
1413 1413
1414 printk(KERN_INFO "HiSax: %s detected\n", 1414 printk(KERN_INFO "HiSax: %s detected\n",
1415 (char *)ipid->driver_data); 1415 (char *)ipid->driver_data);
1416 pnp_disable_dev(pnp_d); 1416 pnp_disable_dev(pnp_d);
1417 err = pnp_activate_dev(pnp_d); 1417 err = pnp_activate_dev(pnp_d);
1418 if (err<0) { 1418 if (err < 0) {
1419 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n", 1419 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
1420 __func__, err); 1420 __func__, err);
1421 return(0); 1421 return (0);
1422 } 1422 }
1423 card->para[1] = pnp_port_start(pnp_d, 0); 1423 card->para[1] = pnp_port_start(pnp_d, 0);
1424 card->para[0] = pnp_irq(pnp_d, 0); 1424 card->para[0] = pnp_irq(pnp_d, 0);
1425 if (!card->para[0] || !card->para[1]) { 1425 if (!card->para[0] || !card->para[1]) {
1426 printk(KERN_ERR "HFC PnP:some resources are missing %ld/%lx\n", 1426 printk(KERN_ERR "HFC PnP:some resources are missing %ld/%lx\n",
1427 card->para[0], card->para[1]); 1427 card->para[0], card->para[1]);
1428 pnp_disable_dev(pnp_d); 1428 pnp_disable_dev(pnp_d);
1429 return(0); 1429 return (0);
1430 } 1430 }
1431 break; 1431 break;
1432 } else { 1432 } else {
@@ -1435,10 +1435,10 @@ setup_hfcsx(struct IsdnCard *card)
1435 } 1435 }
1436 ipid++; 1436 ipid++;
1437 pnp_c = NULL; 1437 pnp_c = NULL;
1438 } 1438 }
1439 if (!ipid->card_vendor) { 1439 if (!ipid->card_vendor) {
1440 printk(KERN_INFO "HFC PnP: no ISAPnP card found\n"); 1440 printk(KERN_INFO "HFC PnP: no ISAPnP card found\n");
1441 return(0); 1441 return (0);
1442 } 1442 }
1443 } 1443 }
1444#endif 1444#endif
@@ -1447,47 +1447,47 @@ setup_hfcsx(struct IsdnCard *card)
1447 cs->hw.hfcsx.int_s1 = 0; 1447 cs->hw.hfcsx.int_s1 = 0;
1448 cs->dc.hfcsx.ph_state = 0; 1448 cs->dc.hfcsx.ph_state = 0;
1449 cs->hw.hfcsx.fifo = 255; 1449 cs->hw.hfcsx.fifo = 255;
1450 if ((cs->typ == ISDN_CTYPE_HFC_SX) || 1450 if ((cs->typ == ISDN_CTYPE_HFC_SX) ||
1451 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) { 1451 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) {
1452 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) { 1452 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) {
1453 printk(KERN_WARNING 1453 printk(KERN_WARNING
1454 "HiSax: HFC-SX io-base %#lx already in use\n", 1454 "HiSax: HFC-SX io-base %#lx already in use\n",
1455 cs->hw.hfcsx.base); 1455 cs->hw.hfcsx.base);
1456 return(0); 1456 return (0);
1457 } 1457 }
1458 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); 1458 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF);
1459 byteout(cs->hw.hfcsx.base + 1, 1459 byteout(cs->hw.hfcsx.base + 1,
1460 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54); 1460 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54);
1461 udelay(10); 1461 udelay(10);
1462 cs->hw.hfcsx.chip = Read_hfc(cs,HFCSX_CHIP_ID); 1462 cs->hw.hfcsx.chip = Read_hfc(cs, HFCSX_CHIP_ID);
1463 switch (cs->hw.hfcsx.chip >> 4) { 1463 switch (cs->hw.hfcsx.chip >> 4) {
1464 case 1: 1464 case 1:
1465 tmp[0] ='+'; 1465 tmp[0] = '+';
1466 break; 1466 break;
1467 case 9: 1467 case 9:
1468 tmp[0] ='P'; 1468 tmp[0] = 'P';
1469 break; 1469 break;
1470 default: 1470 default:
1471 printk(KERN_WARNING 1471 printk(KERN_WARNING
1472 "HFC-SX: invalid chip id 0x%x\n", 1472 "HFC-SX: invalid chip id 0x%x\n",
1473 cs->hw.hfcsx.chip >> 4); 1473 cs->hw.hfcsx.chip >> 4);
1474 release_region(cs->hw.hfcsx.base, 2); 1474 release_region(cs->hw.hfcsx.base, 2);
1475 return(0); 1475 return (0);
1476 } 1476 }
1477 if (!ccd_sp_irqtab[cs->irq & 0xF]) { 1477 if (!ccd_sp_irqtab[cs->irq & 0xF]) {
1478 printk(KERN_WARNING 1478 printk(KERN_WARNING
1479 "HFC_SX: invalid irq %d specified\n",cs->irq & 0xF); 1479 "HFC_SX: invalid irq %d specified\n", cs->irq & 0xF);
1480 release_region(cs->hw.hfcsx.base, 2); 1480 release_region(cs->hw.hfcsx.base, 2);
1481 return(0); 1481 return (0);
1482 } 1482 }
1483 if (!(cs->hw.hfcsx.extra = (void *) 1483 if (!(cs->hw.hfcsx.extra = (void *)
1484 kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) { 1484 kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) {
1485 release_region(cs->hw.hfcsx.base, 2); 1485 release_region(cs->hw.hfcsx.base, 2);
1486 printk(KERN_WARNING "HFC-SX: unable to allocate memory\n"); 1486 printk(KERN_WARNING "HFC-SX: unable to allocate memory\n");
1487 return(0); 1487 return (0);
1488 } 1488 }
1489 printk(KERN_INFO "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n", 1489 printk(KERN_INFO "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n",
1490 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ); 1490 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ);
1491 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */ 1491 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */
1492 cs->hw.hfcsx.int_m1 = 0; 1492 cs->hw.hfcsx.int_m1 = 0;
1493 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); 1493 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 16:49:16 -0500