7 files changed, 181 insertions, 28 deletions

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 07bc79c34012..61ffdca96e25 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,10 @@ config ARM_VIC_NR
           The maximum number of VICs available in the system, for
           power management.
 
+config DW_APB_ICTL
+        bool
+        select IRQ_DOMAIN
+
 config IMGPDC_IRQ
         bool
         select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 66913f9587b3..86b484cb3ec2 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)			+= irq-mmp.o
 obj-$(CONFIG_ARCH_MVEBU)                += irq-armada-370-xp.o
 obj-$(CONFIG_ARCH_MXS)                  += irq-mxs.o
 obj-$(CONFIG_ARCH_S3C24XX)              += irq-s3c24xx.o
+obj-$(CONFIG_DW_APB_ICTL)               += irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)                     += irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)    += irq-metag.o
 obj-$(CONFIG_ARCH_MOXART)               += irq-moxart.o
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 868ed40cb6bf..40e6440348ff 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -171,8 +171,7 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
 
 static void __init combiner_init(void __iomem *combiner_base,
                                  struct device_node *np,
-                                 unsigned int max_nr,
-                                 int irq_base)
+                                 unsigned int max_nr)
 {
         int i, irq;
         unsigned int nr_irq;
@@ -186,7 +185,7 @@ static void __init combiner_init(void __iomem *combiner_base,
                 return;
         }
 
-        combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base,
+        combiner_irq_domain = irq_domain_add_linear(np, nr_irq,
                                 &combiner_irq_domain_ops, combiner_data);
         if (WARN_ON(!combiner_irq_domain)) {
                 pr_warning("%s: irq domain init failed\n", __func__);
@@ -207,7 +206,6 @@ static int __init combiner_of_init(struct device_node *np,
 {
         void __iomem *combiner_base;
         unsigned int max_nr = 20;
-        int irq_base = -1;
 
         combiner_base = of_iomap(np, 0);
         if (!combiner_base) {
@@ -221,14 +219,7 @@ static int __init combiner_of_init(struct device_node *np,
                         __func__, max_nr);
         }
 
-        /* 
-         * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices
-         * get their IRQ from DT, remove this in order to get dynamic
-         * allocation.
-         */
-        irq_base = 160;
-
-        combiner_init(combiner_base, np, max_nr, irq_base);
+        combiner_init(combiner_base, np, max_nr);
 
         return 0;
 }
diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
new file mode 100644
index 000000000000..31e231e1f566
--- /dev/null
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -0,0 +1,150 @@
+/*
+ * Synopsys DW APB ICTL irqchip driver.
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include "irqchip.h"
+
+#define APB_INT_ENABLE_L        0x00
+#define APB_INT_ENABLE_H        0x04
+#define APB_INT_MASK_L          0x08
+#define APB_INT_MASK_H          0x0c
+#define APB_INT_FINALSTATUS_L   0x30
+#define APB_INT_FINALSTATUS_H   0x34
+
+static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_get_chip(irq);
+        struct irq_chip_generic *gc = irq_get_handler_data(irq);
+        struct irq_domain *d = gc->private;
+        u32 stat;
+        int n;
+
+        chained_irq_enter(chip, desc);
+
+        for (n = 0; n < gc->num_ct; n++) {
+                stat = readl_relaxed(gc->reg_base +
+                                     APB_INT_FINALSTATUS_L + 4 * n);
+                while (stat) {
+                        u32 hwirq = ffs(stat) - 1;
+                        generic_handle_irq(irq_find_mapping(d,
+                                            gc->irq_base + hwirq + 32 * n));
+                        stat &= ~(1 << hwirq);
+                }
+        }
+
+        chained_irq_exit(chip, desc);
+}
+
+static int __init dw_apb_ictl_init(struct device_node *np,
+                                   struct device_node *parent)
+{
+        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+        struct resource r;
+        struct irq_domain *domain;
+        struct irq_chip_generic *gc;
+        void __iomem *iobase;
+        int ret, nrirqs, irq;
+        u32 reg;
+
+        /* Map the parent interrupt for the chained handler */
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq <= 0) {
+                pr_err("%s: unable to parse irq\n", np->full_name);
+                return -EINVAL;
+        }
+
+        ret = of_address_to_resource(np, 0, &r);
+        if (ret) {
+                pr_err("%s: unable to get resource\n", np->full_name);
+                return ret;
+        }
+
+        if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
+                pr_err("%s: unable to request mem region\n", np->full_name);
+                return -ENOMEM;
+        }
+
+        iobase = ioremap(r.start, resource_size(&r));
+        if (!iobase) {
+                pr_err("%s: unable to map resource\n", np->full_name);
+                ret = -ENOMEM;
+                goto err_release;
+        }
+
+        /*
+         * DW IP can be configured to allow 2-64 irqs. We can determine
+         * the number of irqs supported by writing into enable register
+         * and look for bits not set, as corresponding flip-flops will
+         * have been removed by sythesis tool.
+         */
+
+        /* mask and enable all interrupts */
+        writel(~0, iobase + APB_INT_MASK_L);
+        writel(~0, iobase + APB_INT_MASK_H);
+        writel(~0, iobase + APB_INT_ENABLE_L);
+        writel(~0, iobase + APB_INT_ENABLE_H);
+
+        reg = readl(iobase + APB_INT_ENABLE_H);
+        if (reg)
+                nrirqs = 32 + fls(reg);
+        else
+                nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
+
+        domain = irq_domain_add_linear(np, nrirqs,
+                                       &irq_generic_chip_ops, NULL);
+        if (!domain) {
+                pr_err("%s: unable to add irq domain\n", np->full_name);
+                ret = -ENOMEM;
+                goto err_unmap;
+        }
+
+        ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
+                                             np->name, handle_level_irq, clr, 0,
+                                             IRQ_GC_INIT_MASK_CACHE);
+        if (ret) {
+                pr_err("%s: unable to alloc irq domain gc\n", np->full_name);
+                goto err_unmap;
+        }
+
+        gc = irq_get_domain_generic_chip(domain, 0);
+        gc->private = domain;
+        gc->reg_base = iobase;
+
+        gc->chip_types[0].regs.mask = APB_INT_MASK_L;
+        gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
+        gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
+
+        if (nrirqs > 32) {
+                gc->chip_types[1].regs.mask = APB_INT_MASK_H;
+                gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
+                gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
+        }
+
+        irq_set_handler_data(irq, gc);
+        irq_set_chained_handler(irq, dw_apb_ictl_handler);
+
+        return 0;
+
+err_unmap:
+        iounmap(iobase);
+err_release:
+        release_mem_region(r.start, resource_size(&r));
+        return ret;
+}
+IRQCHIP_DECLARE(dw_apb_ictl,
+                "snps,dw-apb-ictl", dw_apb_ictl_init);
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c
index 2f404ba61c6c..8777065012a5 100644
--- a/drivers/irqchip/irq-renesas-irqc.c
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -81,15 +81,12 @@ static void irqc_irq_disable(struct irq_data *d)
         iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
 }
 
-#define INTC_IRQ_SENSE_VALID 0x10
-#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
-
 static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
-        [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01),
-        [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02),
-        [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */
-        [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */
-        [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c),  /* Synchronous */
+        [IRQ_TYPE_LEVEL_LOW]    = 0x01,
+        [IRQ_TYPE_LEVEL_HIGH]   = 0x02,
+        [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
+        [IRQ_TYPE_EDGE_RISING]  = 0x08, /* Synchronous */
+        [IRQ_TYPE_EDGE_BOTH]    = 0x0c, /* Synchronous */
 };
 
 static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
@@ -101,12 +98,12 @@ static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
 
         irqc_dbg(&p->irq[hw_irq], "sense");
 
-        if (!(value & INTC_IRQ_SENSE_VALID))
+        if (!value)
                 return -EINVAL;
 
         tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
         tmp &= ~0x3f;
-        tmp |= value ^ INTC_IRQ_SENSE_VALID;
+        tmp |= value;
         iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
         return 0;
 }
@@ -212,10 +209,8 @@ static int irqc_probe(struct platform_device *pdev)
         irq_chip->name = name;
         irq_chip->irq_mask = irqc_irq_disable;
         irq_chip->irq_unmask = irqc_irq_enable;
-        irq_chip->irq_enable = irqc_irq_enable;
-        irq_chip->irq_disable = irqc_irq_disable;
         irq_chip->irq_set_type = irqc_irq_set_type;
-        irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
+        irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
 
         p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
                                               p->number_of_irqs,
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c
index 4851afae38dc..3a070c587ed9 100644
--- a/drivers/irqchip/irq-sirfsoc.c
+++ b/drivers/irqchip/irq-sirfsoc.c
@@ -34,9 +34,10 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
         struct irq_chip_type *ct;
         int ret;
         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+        unsigned int set = IRQ_LEVEL;
 
         ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
-                handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
+                handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);
 
         gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
         gc->reg_base = base;
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
index 47a52ab580d8..3ae2bb8d9cf2 100644
--- a/drivers/irqchip/irq-versatile-fpga.c
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -9,6 +9,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
@@ -167,8 +168,12 @@ void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
                         f->used_irqs++;
                 }
 
-        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
+        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
                 fpga_irq_id, name, base, f->used_irqs);
+        if (parent_irq != -1)
+                pr_cont(", parent IRQ: %d\n", parent_irq);
+        else
+                pr_cont("\n");
 
         fpga_irq_id++;
 }
@@ -180,6 +185,7 @@ int __init fpga_irq_of_init(struct device_node *node,
         void __iomem *base;
         u32 clear_mask;
         u32 valid_mask;
+        int parent_irq;
 
         if (WARN_ON(!node))
                 return -ENODEV;
@@ -193,7 +199,12 @@ int __init fpga_irq_of_init(struct device_node *node,
         if (of_property_read_u32(node, "valid-mask", &valid_mask))
                 valid_mask = 0;
 
-        fpga_irq_init(base, node->name, 0, -1, valid_mask, node);
+        /* Some chips are cascaded from a parent IRQ */
+        parent_irq = irq_of_parse_and_map(node, 0);
+        if (!parent_irq)
+                parent_irq = -1;
+
+        fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
 
         writel(clear_mask, base + IRQ_ENABLE_CLEAR);
         writel(clear_mask, base + FIQ_ENABLE_CLEAR);