6 files changed, 151 insertions, 7 deletions

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 86b484cb3ec2..5194afb39e78 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
 obj-$(CONFIG_RENESAS_INTC_IRQPIN)       += irq-renesas-intc-irqpin.o
 obj-$(CONFIG_RENESAS_IRQC)              += irq-renesas-irqc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)        += irq-versatile-fpga.o
+obj-$(CONFIG_ARCH_NSPIRE)               += irq-zevio.o
 obj-$(CONFIG_ARCH_VT8500)               += irq-vt8500.o
 obj-$(CONFIG_TB10X_IRQC)                += irq-tb10x.o
 obj-$(CONFIG_XTENSA)                    += irq-xtensa-pic.o
diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 9300bc32784e..540956465ed2 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -381,7 +381,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
                                 & PCI_MSI_DOORBELL_MASK;
 
-                        writel(~PCI_MSI_DOORBELL_MASK, per_cpu_int_base +
+                        writel(~msimask, per_cpu_int_base +
                                ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 
                         for (msinr = PCI_MSI_DOORBELL_START;
@@ -407,7 +407,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
                                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
                                 & IPI_DOORBELL_MASK;
 
-                        writel(~IPI_DOORBELL_MASK, per_cpu_int_base +
+                        writel(~ipimask, per_cpu_int_base +
                                 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
 
                         /* Handle all pending doorbells */
diff --git a/drivers/irqchip/irq-metag-ext.c b/drivers/irqchip/irq-metag-ext.c
index 92c41ab4dbfd..2cb474ad8809 100644
--- a/drivers/irqchip/irq-metag-ext.c
+++ b/drivers/irqchip/irq-metag-ext.c
@@ -515,7 +515,7 @@ static int meta_intc_set_affinity(struct irq_data *data,
          * one cpu (the interrupt code doesn't support it), so we just
          * pick the first cpu we find in 'cpumask'.
          */
-        cpu = cpumask_any(cpumask);
+        cpu = cpumask_any_and(cpumask, cpu_online_mask);
         thread = cpu_2_hwthread_id[cpu];
 
         metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr);
diff --git a/drivers/irqchip/irq-metag.c b/drivers/irqchip/irq-metag.c
index 8e94d7a3b20d..c16c186d97d3 100644
--- a/drivers/irqchip/irq-metag.c
+++ b/drivers/irqchip/irq-metag.c
@@ -201,7 +201,7 @@ static int metag_internal_irq_set_affinity(struct irq_data *data,
          * one cpu (the interrupt code doesn't support it), so we just
          * pick the first cpu we find in 'cpumask'.
          */
-        cpu = cpumask_any(cpumask);
+        cpu = cpumask_any_and(cpumask, cpu_online_mask);
         thread = cpu_2_hwthread_id[cpu];
 
         metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR1(thread)),
diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
index e51d40031884..8e41be62812e 100644
--- a/drivers/irqchip/irq-orion.c
+++ b/drivers/irqchip/irq-orion.c
@@ -111,7 +111,8 @@ IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init);
 static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         struct irq_domain *d = irq_get_handler_data(irq);
-        struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, irq);
+
+        struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
         u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &
                    gc->mask_cache;
 
@@ -123,6 +124,19 @@ static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)
         }
 }
 
+/*
+ * Bridge IRQ_CAUSE is asserted regardless of IRQ_MASK register.
+ * To avoid interrupt events on stale irqs, we clear them before unmask.
+ */
+static unsigned int orion_bridge_irq_startup(struct irq_data *d)
+{
+        struct irq_chip_type *ct = irq_data_get_chip_type(d);
+
+        ct->chip.irq_ack(d);
+        ct->chip.irq_unmask(d);
+        return 0;
+}
+
 static int __init orion_bridge_irq_init(struct device_node *np,
                                         struct device_node *parent)
 {
@@ -143,7 +157,7 @@ static int __init orion_bridge_irq_init(struct device_node *np,
         }
 
         ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
-                             handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
+                             handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
         if (ret) {
                 pr_err("%s: unable to alloc irq domain gc\n", np->name);
                 return ret;
@@ -176,12 +190,14 @@ static int __init orion_bridge_irq_init(struct device_node *np,
 
         gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;
         gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;
+        gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup;
         gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
         gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
         gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
 
-        /* mask all interrupts */
+        /* mask and clear all interrupts */
         writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
+        writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
 
         irq_set_handler_data(irq, domain);
         irq_set_chained_handler(irq, orion_bridge_irq_handler);
diff --git a/drivers/irqchip/irq-zevio.c b/drivers/irqchip/irq-zevio.c
new file mode 100644
index 000000000000..8ed04c4a43ee
--- /dev/null
+++ b/drivers/irqchip/irq-zevio.c
@@ -0,0 +1,127 @@
+/*
+ *  linux/drivers/irqchip/irq-zevio.c
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <asm/mach/irq.h>
+#include <asm/exception.h>
+
+#include "irqchip.h"
+
+#define IO_STATUS       0x000
+#define IO_RAW_STATUS   0x004
+#define IO_ENABLE       0x008
+#define IO_DISABLE      0x00C
+#define IO_CURRENT      0x020
+#define IO_RESET        0x028
+#define IO_MAX_PRIOTY   0x02C
+
+#define IO_IRQ_BASE     0x000
+#define IO_FIQ_BASE     0x100
+
+#define IO_INVERT_SEL   0x200
+#define IO_STICKY_SEL   0x204
+#define IO_PRIORITY_SEL 0x300
+
+#define MAX_INTRS       32
+#define FIQ_START       MAX_INTRS
+
+static struct irq_domain *zevio_irq_domain;
+static void __iomem *zevio_irq_io;
+
+static void zevio_irq_ack(struct irq_data *irqd)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(irqd);
+        struct irq_chip_regs *regs =
+                &container_of(irqd->chip, struct irq_chip_type, chip)->regs;
+
+        readl(gc->reg_base + regs->ack);
+}
+
+static asmlinkage void __exception_irq_entry zevio_handle_irq(struct pt_regs *regs)
+{
+        int irqnr;
+
+        while (readl(zevio_irq_io + IO_STATUS)) {
+                irqnr = readl(zevio_irq_io + IO_CURRENT);
+                irqnr = irq_find_mapping(zevio_irq_domain, irqnr);
+                handle_IRQ(irqnr, regs);
+        };
+}
+
+static void __init zevio_init_irq_base(void __iomem *base)
+{
+        /* Disable all interrupts */
+        writel(~0, base + IO_DISABLE);
+
+        /* Accept interrupts of all priorities */
+        writel(0xF, base + IO_MAX_PRIOTY);
+
+        /* Reset existing interrupts */
+        readl(base + IO_RESET);
+}
+
+static int __init zevio_of_init(struct device_node *node,
+                                struct device_node *parent)
+{
+        unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+        struct irq_chip_generic *gc;
+        int ret;
+
+        if (WARN_ON(zevio_irq_io || zevio_irq_domain))
+                return -EBUSY;
+
+        zevio_irq_io = of_iomap(node, 0);
+        BUG_ON(!zevio_irq_io);
+
+        /* Do not invert interrupt status bits */
+        writel(~0, zevio_irq_io + IO_INVERT_SEL);
+
+        /* Disable sticky interrupts */
+        writel(0, zevio_irq_io + IO_STICKY_SEL);
+
+        /* We don't use IRQ priorities. Set each IRQ to highest priority. */
+        memset_io(zevio_irq_io + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32));
+
+        /* Init IRQ and FIQ */
+        zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE);
+        zevio_init_irq_base(zevio_irq_io + IO_FIQ_BASE);
+
+        zevio_irq_domain = irq_domain_add_linear(node, MAX_INTRS,
+                                                 &irq_generic_chip_ops, NULL);
+        BUG_ON(!zevio_irq_domain);
+
+        ret = irq_alloc_domain_generic_chips(zevio_irq_domain, MAX_INTRS, 1,
+                                             "zevio_intc", handle_level_irq,
+                                             clr, 0, IRQ_GC_INIT_MASK_CACHE);
+        BUG_ON(ret);
+
+        gc = irq_get_domain_generic_chip(zevio_irq_domain, 0);
+        gc->reg_base                            = zevio_irq_io;
+        gc->chip_types[0].chip.irq_ack          = zevio_irq_ack;
+        gc->chip_types[0].chip.irq_mask         = irq_gc_mask_disable_reg;
+        gc->chip_types[0].chip.irq_unmask       = irq_gc_unmask_enable_reg;
+        gc->chip_types[0].regs.mask             = IO_IRQ_BASE + IO_ENABLE;
+        gc->chip_types[0].regs.enable           = IO_IRQ_BASE + IO_ENABLE;
+        gc->chip_types[0].regs.disable          = IO_IRQ_BASE + IO_DISABLE;
+        gc->chip_types[0].regs.ack              = IO_IRQ_BASE + IO_RESET;
+
+        set_handle_irq(zevio_handle_irq);
+
+        pr_info("TI-NSPIRE classic IRQ controller\n");
+        return 0;
+}
+
+IRQCHIP_DECLARE(zevio_irq, "lsi,zevio-intc", zevio_of_init);