diff options
Diffstat (limited to 'drivers/irqchip')
-rw-r--r-- | drivers/irqchip/irq-gic.c | 9 | ||||
-rw-r--r-- | drivers/irqchip/irq-renesas-intc-irqpin.c | 8 |
2 files changed, 10 insertions, 7 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 9031171c141b..341c6016812d 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c | |||
@@ -957,12 +957,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, | |||
957 | if (WARN_ON(!gic->domain)) | 957 | if (WARN_ON(!gic->domain)) |
958 | return; | 958 | return; |
959 | 959 | ||
960 | if (gic_nr == 0) { | ||
960 | #ifdef CONFIG_SMP | 961 | #ifdef CONFIG_SMP |
961 | set_smp_cross_call(gic_raise_softirq); | 962 | set_smp_cross_call(gic_raise_softirq); |
962 | register_cpu_notifier(&gic_cpu_notifier); | 963 | register_cpu_notifier(&gic_cpu_notifier); |
963 | #endif | 964 | #endif |
964 | 965 | set_handle_irq(gic_handle_irq); | |
965 | set_handle_irq(gic_handle_irq); | 966 | } |
966 | 967 | ||
967 | gic_chip.flags |= gic_arch_extn.flags; | 968 | gic_chip.flags |= gic_arch_extn.flags; |
968 | gic_dist_init(gic); | 969 | gic_dist_init(gic); |
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 82cec63a9011..3ee78f02e5d7 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c | |||
@@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, | |||
149 | static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, | 149 | static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, |
150 | int irq, int do_mask) | 150 | int irq, int do_mask) |
151 | { | 151 | { |
152 | int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ | 152 | /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */ |
153 | int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ | 153 | int bitfield_width = 4; |
154 | int shift = 32 - (irq + 1) * bitfield_width; | ||
154 | 155 | ||
155 | intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, | 156 | intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, |
156 | shift, bitfield_width, | 157 | shift, bitfield_width, |
@@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, | |||
159 | 160 | ||
160 | static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) | 161 | static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) |
161 | { | 162 | { |
163 | /* The SENSE register is assumed to be 32-bit. */ | ||
162 | int bitfield_width = p->config.sense_bitfield_width; | 164 | int bitfield_width = p->config.sense_bitfield_width; |
163 | int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ | 165 | int shift = 32 - (irq + 1) * bitfield_width; |
164 | 166 | ||
165 | dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); | 167 | dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); |
166 | 168 | ||