1 files changed, 35 insertions, 16 deletions

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 3826698b5890..38493ff28fa5 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -270,8 +270,7 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
                 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 
                 if (likely(irqnr > 15 && irqnr < 1021)) {
-                        irqnr = irq_find_mapping(gic->domain, irqnr);
-                        handle_IRQ(irqnr, regs);
+                        handle_domain_irq(gic->domain, irqnr, regs);
                         continue;
                 }
                 if (irqnr < 16) {
@@ -298,8 +297,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
         raw_spin_unlock(&irq_controller_lock);
 
-        gic_irq = (status & 0x3ff);
-        if (gic_irq == 1023)
+        gic_irq = (status & GICC_IAR_INT_ID_MASK);
+        if (gic_irq == GICC_INT_SPURIOUS)
                 goto out;
 
         cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
@@ -353,6 +352,21 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
         return mask;
 }
 
+static void gic_cpu_if_up(void)
+{
+        void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
+        u32 bypass = 0;
+
+        /*
+        * Preserve bypass disable bits to be written back later
+        */
+        bypass = readl(cpu_base + GIC_CPU_CTRL);
+        bypass &= GICC_DIS_BYPASS_MASK;
+
+        writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
+}
+
+
 static void __init gic_dist_init(struct gic_chip_data *gic)
 {
         unsigned int i;
@@ -360,7 +374,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
         unsigned int gic_irqs = gic->gic_irqs;
         void __iomem *base = gic_data_dist_base(gic);
 
-        writel_relaxed(0, base + GIC_DIST_CTRL);
+        writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
 
         /*
          * Set all global interrupts to this CPU only.
@@ -373,7 +387,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
 
         gic_dist_config(base, gic_irqs, NULL);
 
-        writel_relaxed(1, base + GIC_DIST_CTRL);
+        writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
 }
 
 static void gic_cpu_init(struct gic_chip_data *gic)
@@ -400,14 +414,18 @@ static void gic_cpu_init(struct gic_chip_data *gic)
 
         gic_cpu_config(dist_base, NULL);
 
-        writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
-        writel_relaxed(1, base + GIC_CPU_CTRL);
+        writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
+        gic_cpu_if_up();
 }
 
 void gic_cpu_if_down(void)
 {
         void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
-        writel_relaxed(0, cpu_base + GIC_CPU_CTRL);
+        u32 val = 0;
+
+        val = readl(cpu_base + GIC_CPU_CTRL);
+        val &= ~GICC_ENABLE;
+        writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
 }
 
 #ifdef CONFIG_CPU_PM
@@ -467,14 +485,14 @@ static void gic_dist_restore(unsigned int gic_nr)
         if (!dist_base)
                 return;
 
-        writel_relaxed(0, dist_base + GIC_DIST_CTRL);
+        writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
 
         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
                 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
                         dist_base + GIC_DIST_CONFIG + i * 4);
 
         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
-                writel_relaxed(0xa0a0a0a0,
+                writel_relaxed(GICD_INT_DEF_PRI_X4,
                         dist_base + GIC_DIST_PRI + i * 4);
 
         for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
@@ -485,7 +503,7 @@ static void gic_dist_restore(unsigned int gic_nr)
                 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
                         dist_base + GIC_DIST_ENABLE_SET + i * 4);
 
-        writel_relaxed(1, dist_base + GIC_DIST_CTRL);
+        writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
 }
 
 static void gic_cpu_save(unsigned int gic_nr)
@@ -539,10 +557,11 @@ static void gic_cpu_restore(unsigned int gic_nr)
                 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
 
         for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
-                writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
+                writel_relaxed(GICD_INT_DEF_PRI_X4,
+                                        dist_base + GIC_DIST_PRI + i * 4);
 
-        writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
-        writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
+        writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
+        gic_cpu_if_up();
 }
 
 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
@@ -867,7 +886,7 @@ static int gic_routable_irq_domain_xlate(struct irq_domain *d,
         return 0;
 }
 
-const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
+static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
         .map = gic_routable_irq_domain_map,
         .unmap = gic_routable_irq_domain_unmap,
         .xlate = gic_routable_irq_domain_xlate,