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path: root/drivers/irqchip/irq-atmel-aic.c
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Diffstat (limited to 'drivers/irqchip/irq-atmel-aic.c')
-rw-r--r--drivers/irqchip/irq-atmel-aic.c40
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/irqchip/irq-atmel-aic.c b/drivers/irqchip/irq-atmel-aic.c
index 9a2cf3c1a3a5..27fdd8c3e7b4 100644
--- a/drivers/irqchip/irq-atmel-aic.c
+++ b/drivers/irqchip/irq-atmel-aic.c
@@ -65,11 +65,11 @@ aic_handle(struct pt_regs *regs)
65 u32 irqnr; 65 u32 irqnr;
66 u32 irqstat; 66 u32 irqstat;
67 67
68 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC_IVR); 68 irqnr = irq_reg_readl(gc, AT91_AIC_IVR);
69 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC_ISR); 69 irqstat = irq_reg_readl(gc, AT91_AIC_ISR);
70 70
71 if (!irqstat) 71 if (!irqstat)
72 irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR); 72 irq_reg_writel(gc, 0, AT91_AIC_EOICR);
73 else 73 else
74 handle_domain_irq(aic_domain, irqnr, regs); 74 handle_domain_irq(aic_domain, irqnr, regs);
75} 75}
@@ -80,7 +80,7 @@ static int aic_retrigger(struct irq_data *d)
80 80
81 /* Enable interrupt on AIC5 */ 81 /* Enable interrupt on AIC5 */
82 irq_gc_lock(gc); 82 irq_gc_lock(gc);
83 irq_reg_writel(d->mask, gc->reg_base + AT91_AIC_ISCR); 83 irq_reg_writel(gc, d->mask, AT91_AIC_ISCR);
84 irq_gc_unlock(gc); 84 irq_gc_unlock(gc);
85 85
86 return 0; 86 return 0;
@@ -92,12 +92,12 @@ static int aic_set_type(struct irq_data *d, unsigned type)
92 unsigned int smr; 92 unsigned int smr;
93 int ret; 93 int ret;
94 94
95 smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(d->hwirq)); 95 smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq));
96 ret = aic_common_set_type(d, type, &smr); 96 ret = aic_common_set_type(d, type, &smr);
97 if (ret) 97 if (ret)
98 return ret; 98 return ret;
99 99
100 irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(d->hwirq)); 100 irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq));
101 101
102 return 0; 102 return 0;
103} 103}
@@ -108,8 +108,8 @@ static void aic_suspend(struct irq_data *d)
108 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 108 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
109 109
110 irq_gc_lock(gc); 110 irq_gc_lock(gc);
111 irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IDCR); 111 irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);
112 irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IECR); 112 irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR);
113 irq_gc_unlock(gc); 113 irq_gc_unlock(gc);
114} 114}
115 115
@@ -118,8 +118,8 @@ static void aic_resume(struct irq_data *d)
118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
119 119
120 irq_gc_lock(gc); 120 irq_gc_lock(gc);
121 irq_reg_writel(gc->wake_active, gc->reg_base + AT91_AIC_IDCR); 121 irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR);
122 irq_reg_writel(gc->mask_cache, gc->reg_base + AT91_AIC_IECR); 122 irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);
123 irq_gc_unlock(gc); 123 irq_gc_unlock(gc);
124} 124}
125 125
@@ -128,8 +128,8 @@ static void aic_pm_shutdown(struct irq_data *d)
128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
129 129
130 irq_gc_lock(gc); 130 irq_gc_lock(gc);
131 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR); 131 irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
132 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR); 132 irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
133 irq_gc_unlock(gc); 133 irq_gc_unlock(gc);
134} 134}
135#else 135#else
@@ -148,24 +148,24 @@ static void __init aic_hw_init(struct irq_domain *domain)
148 * will not Lock out nIRQ 148 * will not Lock out nIRQ
149 */ 149 */
150 for (i = 0; i < 8; i++) 150 for (i = 0; i < 8; i++)
151 irq_reg_writel(0, gc->reg_base + AT91_AIC_EOICR); 151 irq_reg_writel(gc, 0, AT91_AIC_EOICR);
152 152
153 /* 153 /*
154 * Spurious Interrupt ID in Spurious Vector Register. 154 * Spurious Interrupt ID in Spurious Vector Register.
155 * When there is no current interrupt, the IRQ Vector Register 155 * When there is no current interrupt, the IRQ Vector Register
156 * reads the value stored in AIC_SPU 156 * reads the value stored in AIC_SPU
157 */ 157 */
158 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_SPU); 158 irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);
159 159
160 /* No debugging in AIC: Debug (Protect) Control Register */ 160 /* No debugging in AIC: Debug (Protect) Control Register */
161 irq_reg_writel(0, gc->reg_base + AT91_AIC_DCR); 161 irq_reg_writel(gc, 0, AT91_AIC_DCR);
162 162
163 /* Disable and clear all interrupts initially */ 163 /* Disable and clear all interrupts initially */
164 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_IDCR); 164 irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
165 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC_ICCR); 165 irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
166 166
167 for (i = 0; i < 32; i++) 167 for (i = 0; i < 32; i++)
168 irq_reg_writel(i, gc->reg_base + AT91_AIC_SVR(i)); 168 irq_reg_writel(gc, i, AT91_AIC_SVR(i));
169} 169}
170 170
171static int aic_irq_domain_xlate(struct irq_domain *d, 171static int aic_irq_domain_xlate(struct irq_domain *d,
@@ -195,10 +195,10 @@ static int aic_irq_domain_xlate(struct irq_domain *d,
195 gc = dgc->gc[idx]; 195 gc = dgc->gc[idx];
196 196
197 irq_gc_lock(gc); 197 irq_gc_lock(gc);
198 smr = irq_reg_readl(gc->reg_base + AT91_AIC_SMR(*out_hwirq)); 198 smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq));
199 ret = aic_common_set_priority(intspec[2], &smr); 199 ret = aic_common_set_priority(intspec[2], &smr);
200 if (!ret) 200 if (!ret)
201 irq_reg_writel(smr, gc->reg_base + AT91_AIC_SMR(*out_hwirq)); 201 irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));
202 irq_gc_unlock(gc); 202 irq_gc_unlock(gc);
203 203
204 return ret; 204 return ret;