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-rw-r--r--drivers/iommu/amd_iommu_init.c9
-rw-r--r--drivers/iommu/amd_iommu_types.h1
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 60716cefa7af..2c25ae306e7c 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -623,6 +623,14 @@ static void __init free_ppr_log(struct amd_iommu *iommu)
623 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); 623 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
624} 624}
625 625
626static void iommu_enable_gt(struct amd_iommu *iommu)
627{
628 if (!iommu_feature(iommu, FEATURE_GT))
629 return;
630
631 iommu_feature_enable(iommu, CONTROL_GT_EN);
632}
633
626/* sets a specific bit in the device table entry. */ 634/* sets a specific bit in the device table entry. */
627static void set_dev_entry_bit(u16 devid, u8 bit) 635static void set_dev_entry_bit(u16 devid, u8 bit)
628{ 636{
@@ -1338,6 +1346,7 @@ static void enable_iommus(void)
1338 iommu_enable_command_buffer(iommu); 1346 iommu_enable_command_buffer(iommu);
1339 iommu_enable_event_buffer(iommu); 1347 iommu_enable_event_buffer(iommu);
1340 iommu_enable_ppr_log(iommu); 1348 iommu_enable_ppr_log(iommu);
1349 iommu_enable_gt(iommu);
1341 iommu_set_exclusion_range(iommu); 1350 iommu_set_exclusion_range(iommu);
1342 iommu_init_msi(iommu); 1351 iommu_init_msi(iommu);
1343 iommu_enable(iommu); 1352 iommu_enable(iommu);
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index 4dc230904fe9..a6e1dc616afe 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -129,6 +129,7 @@
129#define CONTROL_PPFLOG_EN 0x0dULL 129#define CONTROL_PPFLOG_EN 0x0dULL
130#define CONTROL_PPFINT_EN 0x0eULL 130#define CONTROL_PPFINT_EN 0x0eULL
131#define CONTROL_PPR_EN 0x0fULL 131#define CONTROL_PPR_EN 0x0fULL
132#define CONTROL_GT_EN 0x10ULL
132 133
133/* command specific defines */ 134/* command specific defines */
134#define CMD_COMPL_WAIT 0x01 135#define CMD_COMPL_WAIT 0x01