diff options
Diffstat (limited to 'drivers/iommu')
-rw-r--r-- | drivers/iommu/Makefile | 2 | ||||
-rw-r--r-- | drivers/iommu/amd_iommu.c | 7 | ||||
-rw-r--r-- | drivers/iommu/amd_iommu_init.c | 1574 | ||||
-rw-r--r-- | drivers/iommu/amd_iommu_proto.h | 54 | ||||
-rw-r--r-- | drivers/iommu/amd_iommu_types.h | 580 |
5 files changed, 2213 insertions, 4 deletions
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 49e9c0f46bd5..4d4d77df7cac 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile | |||
@@ -1,5 +1,5 @@ | |||
1 | obj-$(CONFIG_IOMMU_API) += iommu.o | 1 | obj-$(CONFIG_IOMMU_API) += iommu.o |
2 | obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_dev.o | 2 | obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o msm_iommu_dev.o |
3 | obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o | 3 | obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o |
4 | obj-$(CONFIG_DMAR) += dmar.o iova.o intel-iommu.o | 4 | obj-$(CONFIG_DMAR) += dmar.o iova.o intel-iommu.o |
5 | obj-$(CONFIG_INTR_REMAP) += dmar.o intr_remapping.o | 5 | obj-$(CONFIG_INTR_REMAP) += dmar.o intr_remapping.o |
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index 7c3a95e54ec5..5aa12eaabd21 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c | |||
@@ -27,13 +27,14 @@ | |||
27 | #include <linux/iommu-helper.h> | 27 | #include <linux/iommu-helper.h> |
28 | #include <linux/iommu.h> | 28 | #include <linux/iommu.h> |
29 | #include <linux/delay.h> | 29 | #include <linux/delay.h> |
30 | #include <linux/amd-iommu.h> | ||
30 | #include <asm/proto.h> | 31 | #include <asm/proto.h> |
31 | #include <asm/iommu.h> | 32 | #include <asm/iommu.h> |
32 | #include <asm/gart.h> | 33 | #include <asm/gart.h> |
33 | #include <asm/dma.h> | 34 | #include <asm/dma.h> |
34 | #include <asm/amd_iommu_proto.h> | 35 | |
35 | #include <asm/amd_iommu_types.h> | 36 | #include "amd_iommu_proto.h" |
36 | #include <asm/amd_iommu.h> | 37 | #include "amd_iommu_types.h" |
37 | 38 | ||
38 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | 39 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) |
39 | 40 | ||
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c new file mode 100644 index 000000000000..82d2410f4205 --- /dev/null +++ b/drivers/iommu/amd_iommu_init.c | |||
@@ -0,0 +1,1574 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. | ||
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | ||
4 | * Leo Duran <leo.duran@amd.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License version 2 as published | ||
8 | * by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
18 | */ | ||
19 | |||
20 | #include <linux/pci.h> | ||
21 | #include <linux/acpi.h> | ||
22 | #include <linux/list.h> | ||
23 | #include <linux/slab.h> | ||
24 | #include <linux/syscore_ops.h> | ||
25 | #include <linux/interrupt.h> | ||
26 | #include <linux/msi.h> | ||
27 | #include <linux/amd-iommu.h> | ||
28 | #include <asm/pci-direct.h> | ||
29 | #include <asm/iommu.h> | ||
30 | #include <asm/gart.h> | ||
31 | #include <asm/x86_init.h> | ||
32 | #include <asm/iommu_table.h> | ||
33 | |||
34 | #include "amd_iommu_proto.h" | ||
35 | #include "amd_iommu_types.h" | ||
36 | |||
37 | /* | ||
38 | * definitions for the ACPI scanning code | ||
39 | */ | ||
40 | #define IVRS_HEADER_LENGTH 48 | ||
41 | |||
42 | #define ACPI_IVHD_TYPE 0x10 | ||
43 | #define ACPI_IVMD_TYPE_ALL 0x20 | ||
44 | #define ACPI_IVMD_TYPE 0x21 | ||
45 | #define ACPI_IVMD_TYPE_RANGE 0x22 | ||
46 | |||
47 | #define IVHD_DEV_ALL 0x01 | ||
48 | #define IVHD_DEV_SELECT 0x02 | ||
49 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | ||
50 | #define IVHD_DEV_RANGE_END 0x04 | ||
51 | #define IVHD_DEV_ALIAS 0x42 | ||
52 | #define IVHD_DEV_ALIAS_RANGE 0x43 | ||
53 | #define IVHD_DEV_EXT_SELECT 0x46 | ||
54 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | ||
55 | |||
56 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 | ||
57 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | ||
58 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | ||
59 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | ||
60 | |||
61 | #define IVMD_FLAG_EXCL_RANGE 0x08 | ||
62 | #define IVMD_FLAG_UNITY_MAP 0x01 | ||
63 | |||
64 | #define ACPI_DEVFLAG_INITPASS 0x01 | ||
65 | #define ACPI_DEVFLAG_EXTINT 0x02 | ||
66 | #define ACPI_DEVFLAG_NMI 0x04 | ||
67 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | ||
68 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | ||
69 | #define ACPI_DEVFLAG_LINT0 0x40 | ||
70 | #define ACPI_DEVFLAG_LINT1 0x80 | ||
71 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | ||
72 | |||
73 | /* | ||
74 | * ACPI table definitions | ||
75 | * | ||
76 | * These data structures are laid over the table to parse the important values | ||
77 | * out of it. | ||
78 | */ | ||
79 | |||
80 | /* | ||
81 | * structure describing one IOMMU in the ACPI table. Typically followed by one | ||
82 | * or more ivhd_entrys. | ||
83 | */ | ||
84 | struct ivhd_header { | ||
85 | u8 type; | ||
86 | u8 flags; | ||
87 | u16 length; | ||
88 | u16 devid; | ||
89 | u16 cap_ptr; | ||
90 | u64 mmio_phys; | ||
91 | u16 pci_seg; | ||
92 | u16 info; | ||
93 | u32 reserved; | ||
94 | } __attribute__((packed)); | ||
95 | |||
96 | /* | ||
97 | * A device entry describing which devices a specific IOMMU translates and | ||
98 | * which requestor ids they use. | ||
99 | */ | ||
100 | struct ivhd_entry { | ||
101 | u8 type; | ||
102 | u16 devid; | ||
103 | u8 flags; | ||
104 | u32 ext; | ||
105 | } __attribute__((packed)); | ||
106 | |||
107 | /* | ||
108 | * An AMD IOMMU memory definition structure. It defines things like exclusion | ||
109 | * ranges for devices and regions that should be unity mapped. | ||
110 | */ | ||
111 | struct ivmd_header { | ||
112 | u8 type; | ||
113 | u8 flags; | ||
114 | u16 length; | ||
115 | u16 devid; | ||
116 | u16 aux; | ||
117 | u64 resv; | ||
118 | u64 range_start; | ||
119 | u64 range_length; | ||
120 | } __attribute__((packed)); | ||
121 | |||
122 | bool amd_iommu_dump; | ||
123 | |||
124 | static int __initdata amd_iommu_detected; | ||
125 | static bool __initdata amd_iommu_disabled; | ||
126 | |||
127 | u16 amd_iommu_last_bdf; /* largest PCI device id we have | ||
128 | to handle */ | ||
129 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings | ||
130 | we find in ACPI */ | ||
131 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ | ||
132 | |||
133 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the | ||
134 | system */ | ||
135 | |||
136 | /* Array to assign indices to IOMMUs*/ | ||
137 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | ||
138 | int amd_iommus_present; | ||
139 | |||
140 | /* IOMMUs have a non-present cache? */ | ||
141 | bool amd_iommu_np_cache __read_mostly; | ||
142 | bool amd_iommu_iotlb_sup __read_mostly = true; | ||
143 | |||
144 | /* | ||
145 | * The ACPI table parsing functions set this variable on an error | ||
146 | */ | ||
147 | static int __initdata amd_iommu_init_err; | ||
148 | |||
149 | /* | ||
150 | * List of protection domains - used during resume | ||
151 | */ | ||
152 | LIST_HEAD(amd_iommu_pd_list); | ||
153 | spinlock_t amd_iommu_pd_lock; | ||
154 | |||
155 | /* | ||
156 | * Pointer to the device table which is shared by all AMD IOMMUs | ||
157 | * it is indexed by the PCI device id or the HT unit id and contains | ||
158 | * information about the domain the device belongs to as well as the | ||
159 | * page table root pointer. | ||
160 | */ | ||
161 | struct dev_table_entry *amd_iommu_dev_table; | ||
162 | |||
163 | /* | ||
164 | * The alias table is a driver specific data structure which contains the | ||
165 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | ||
166 | * More than one device can share the same requestor id. | ||
167 | */ | ||
168 | u16 *amd_iommu_alias_table; | ||
169 | |||
170 | /* | ||
171 | * The rlookup table is used to find the IOMMU which is responsible | ||
172 | * for a specific device. It is also indexed by the PCI device id. | ||
173 | */ | ||
174 | struct amd_iommu **amd_iommu_rlookup_table; | ||
175 | |||
176 | /* | ||
177 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | ||
178 | * to know which ones are already in use. | ||
179 | */ | ||
180 | unsigned long *amd_iommu_pd_alloc_bitmap; | ||
181 | |||
182 | static u32 dev_table_size; /* size of the device table */ | ||
183 | static u32 alias_table_size; /* size of the alias table */ | ||
184 | static u32 rlookup_table_size; /* size if the rlookup table */ | ||
185 | |||
186 | /* | ||
187 | * This function flushes all internal caches of | ||
188 | * the IOMMU used by this driver. | ||
189 | */ | ||
190 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); | ||
191 | |||
192 | static inline void update_last_devid(u16 devid) | ||
193 | { | ||
194 | if (devid > amd_iommu_last_bdf) | ||
195 | amd_iommu_last_bdf = devid; | ||
196 | } | ||
197 | |||
198 | static inline unsigned long tbl_size(int entry_size) | ||
199 | { | ||
200 | unsigned shift = PAGE_SHIFT + | ||
201 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); | ||
202 | |||
203 | return 1UL << shift; | ||
204 | } | ||
205 | |||
206 | /* Access to l1 and l2 indexed register spaces */ | ||
207 | |||
208 | static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) | ||
209 | { | ||
210 | u32 val; | ||
211 | |||
212 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | ||
213 | pci_read_config_dword(iommu->dev, 0xfc, &val); | ||
214 | return val; | ||
215 | } | ||
216 | |||
217 | static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) | ||
218 | { | ||
219 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); | ||
220 | pci_write_config_dword(iommu->dev, 0xfc, val); | ||
221 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | ||
222 | } | ||
223 | |||
224 | static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) | ||
225 | { | ||
226 | u32 val; | ||
227 | |||
228 | pci_write_config_dword(iommu->dev, 0xf0, address); | ||
229 | pci_read_config_dword(iommu->dev, 0xf4, &val); | ||
230 | return val; | ||
231 | } | ||
232 | |||
233 | static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) | ||
234 | { | ||
235 | pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); | ||
236 | pci_write_config_dword(iommu->dev, 0xf4, val); | ||
237 | } | ||
238 | |||
239 | /**************************************************************************** | ||
240 | * | ||
241 | * AMD IOMMU MMIO register space handling functions | ||
242 | * | ||
243 | * These functions are used to program the IOMMU device registers in | ||
244 | * MMIO space required for that driver. | ||
245 | * | ||
246 | ****************************************************************************/ | ||
247 | |||
248 | /* | ||
249 | * This function set the exclusion range in the IOMMU. DMA accesses to the | ||
250 | * exclusion range are passed through untranslated | ||
251 | */ | ||
252 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) | ||
253 | { | ||
254 | u64 start = iommu->exclusion_start & PAGE_MASK; | ||
255 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | ||
256 | u64 entry; | ||
257 | |||
258 | if (!iommu->exclusion_start) | ||
259 | return; | ||
260 | |||
261 | entry = start | MMIO_EXCL_ENABLE_MASK; | ||
262 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | ||
263 | &entry, sizeof(entry)); | ||
264 | |||
265 | entry = limit; | ||
266 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | ||
267 | &entry, sizeof(entry)); | ||
268 | } | ||
269 | |||
270 | /* Programs the physical address of the device table into the IOMMU hardware */ | ||
271 | static void __init iommu_set_device_table(struct amd_iommu *iommu) | ||
272 | { | ||
273 | u64 entry; | ||
274 | |||
275 | BUG_ON(iommu->mmio_base == NULL); | ||
276 | |||
277 | entry = virt_to_phys(amd_iommu_dev_table); | ||
278 | entry |= (dev_table_size >> 12) - 1; | ||
279 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | ||
280 | &entry, sizeof(entry)); | ||
281 | } | ||
282 | |||
283 | /* Generic functions to enable/disable certain features of the IOMMU. */ | ||
284 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) | ||
285 | { | ||
286 | u32 ctrl; | ||
287 | |||
288 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | ||
289 | ctrl |= (1 << bit); | ||
290 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | ||
291 | } | ||
292 | |||
293 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | ||
294 | { | ||
295 | u32 ctrl; | ||
296 | |||
297 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | ||
298 | ctrl &= ~(1 << bit); | ||
299 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | ||
300 | } | ||
301 | |||
302 | /* Function to enable the hardware */ | ||
303 | static void iommu_enable(struct amd_iommu *iommu) | ||
304 | { | ||
305 | static const char * const feat_str[] = { | ||
306 | "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", | ||
307 | "IA", "GA", "HE", "PC", NULL | ||
308 | }; | ||
309 | int i; | ||
310 | |||
311 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx", | ||
312 | dev_name(&iommu->dev->dev), iommu->cap_ptr); | ||
313 | |||
314 | if (iommu->cap & (1 << IOMMU_CAP_EFR)) { | ||
315 | printk(KERN_CONT " extended features: "); | ||
316 | for (i = 0; feat_str[i]; ++i) | ||
317 | if (iommu_feature(iommu, (1ULL << i))) | ||
318 | printk(KERN_CONT " %s", feat_str[i]); | ||
319 | } | ||
320 | printk(KERN_CONT "\n"); | ||
321 | |||
322 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | ||
323 | } | ||
324 | |||
325 | static void iommu_disable(struct amd_iommu *iommu) | ||
326 | { | ||
327 | /* Disable command buffer */ | ||
328 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | ||
329 | |||
330 | /* Disable event logging and event interrupts */ | ||
331 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | ||
332 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | ||
333 | |||
334 | /* Disable IOMMU hardware itself */ | ||
335 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); | ||
336 | } | ||
337 | |||
338 | /* | ||
339 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | ||
340 | * the system has one. | ||
341 | */ | ||
342 | static u8 * __init iommu_map_mmio_space(u64 address) | ||
343 | { | ||
344 | u8 *ret; | ||
345 | |||
346 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) { | ||
347 | pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n", | ||
348 | address); | ||
349 | pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); | ||
350 | return NULL; | ||
351 | } | ||
352 | |||
353 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | ||
354 | if (ret != NULL) | ||
355 | return ret; | ||
356 | |||
357 | release_mem_region(address, MMIO_REGION_LENGTH); | ||
358 | |||
359 | return NULL; | ||
360 | } | ||
361 | |||
362 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | ||
363 | { | ||
364 | if (iommu->mmio_base) | ||
365 | iounmap(iommu->mmio_base); | ||
366 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | ||
367 | } | ||
368 | |||
369 | /**************************************************************************** | ||
370 | * | ||
371 | * The functions below belong to the first pass of AMD IOMMU ACPI table | ||
372 | * parsing. In this pass we try to find out the highest device id this | ||
373 | * code has to handle. Upon this information the size of the shared data | ||
374 | * structures is determined later. | ||
375 | * | ||
376 | ****************************************************************************/ | ||
377 | |||
378 | /* | ||
379 | * This function calculates the length of a given IVHD entry | ||
380 | */ | ||
381 | static inline int ivhd_entry_length(u8 *ivhd) | ||
382 | { | ||
383 | return 0x04 << (*ivhd >> 6); | ||
384 | } | ||
385 | |||
386 | /* | ||
387 | * This function reads the last device id the IOMMU has to handle from the PCI | ||
388 | * capability header for this IOMMU | ||
389 | */ | ||
390 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) | ||
391 | { | ||
392 | u32 cap; | ||
393 | |||
394 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | ||
395 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); | ||
396 | |||
397 | return 0; | ||
398 | } | ||
399 | |||
400 | /* | ||
401 | * After reading the highest device id from the IOMMU PCI capability header | ||
402 | * this function looks if there is a higher device id defined in the ACPI table | ||
403 | */ | ||
404 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) | ||
405 | { | ||
406 | u8 *p = (void *)h, *end = (void *)h; | ||
407 | struct ivhd_entry *dev; | ||
408 | |||
409 | p += sizeof(*h); | ||
410 | end += h->length; | ||
411 | |||
412 | find_last_devid_on_pci(PCI_BUS(h->devid), | ||
413 | PCI_SLOT(h->devid), | ||
414 | PCI_FUNC(h->devid), | ||
415 | h->cap_ptr); | ||
416 | |||
417 | while (p < end) { | ||
418 | dev = (struct ivhd_entry *)p; | ||
419 | switch (dev->type) { | ||
420 | case IVHD_DEV_SELECT: | ||
421 | case IVHD_DEV_RANGE_END: | ||
422 | case IVHD_DEV_ALIAS: | ||
423 | case IVHD_DEV_EXT_SELECT: | ||
424 | /* all the above subfield types refer to device ids */ | ||
425 | update_last_devid(dev->devid); | ||
426 | break; | ||
427 | default: | ||
428 | break; | ||
429 | } | ||
430 | p += ivhd_entry_length(p); | ||
431 | } | ||
432 | |||
433 | WARN_ON(p != end); | ||
434 | |||
435 | return 0; | ||
436 | } | ||
437 | |||
438 | /* | ||
439 | * Iterate over all IVHD entries in the ACPI table and find the highest device | ||
440 | * id which we need to handle. This is the first of three functions which parse | ||
441 | * the ACPI table. So we check the checksum here. | ||
442 | */ | ||
443 | static int __init find_last_devid_acpi(struct acpi_table_header *table) | ||
444 | { | ||
445 | int i; | ||
446 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | ||
447 | struct ivhd_header *h; | ||
448 | |||
449 | /* | ||
450 | * Validate checksum here so we don't need to do it when | ||
451 | * we actually parse the table | ||
452 | */ | ||
453 | for (i = 0; i < table->length; ++i) | ||
454 | checksum += p[i]; | ||
455 | if (checksum != 0) { | ||
456 | /* ACPI table corrupt */ | ||
457 | amd_iommu_init_err = -ENODEV; | ||
458 | return 0; | ||
459 | } | ||
460 | |||
461 | p += IVRS_HEADER_LENGTH; | ||
462 | |||
463 | end += table->length; | ||
464 | while (p < end) { | ||
465 | h = (struct ivhd_header *)p; | ||
466 | switch (h->type) { | ||
467 | case ACPI_IVHD_TYPE: | ||
468 | find_last_devid_from_ivhd(h); | ||
469 | break; | ||
470 | default: | ||
471 | break; | ||
472 | } | ||
473 | p += h->length; | ||
474 | } | ||
475 | WARN_ON(p != end); | ||
476 | |||
477 | return 0; | ||
478 | } | ||
479 | |||
480 | /**************************************************************************** | ||
481 | * | ||
482 | * The following functions belong the the code path which parses the ACPI table | ||
483 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | ||
484 | * data structures, initialize the device/alias/rlookup table and also | ||
485 | * basically initialize the hardware. | ||
486 | * | ||
487 | ****************************************************************************/ | ||
488 | |||
489 | /* | ||
490 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | ||
491 | * write commands to that buffer later and the IOMMU will execute them | ||
492 | * asynchronously | ||
493 | */ | ||
494 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) | ||
495 | { | ||
496 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | ||
497 | get_order(CMD_BUFFER_SIZE)); | ||
498 | |||
499 | if (cmd_buf == NULL) | ||
500 | return NULL; | ||
501 | |||
502 | iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; | ||
503 | |||
504 | return cmd_buf; | ||
505 | } | ||
506 | |||
507 | /* | ||
508 | * This function resets the command buffer if the IOMMU stopped fetching | ||
509 | * commands from it. | ||
510 | */ | ||
511 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | ||
512 | { | ||
513 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | ||
514 | |||
515 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | ||
516 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | ||
517 | |||
518 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | ||
519 | } | ||
520 | |||
521 | /* | ||
522 | * This function writes the command buffer address to the hardware and | ||
523 | * enables it. | ||
524 | */ | ||
525 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | ||
526 | { | ||
527 | u64 entry; | ||
528 | |||
529 | BUG_ON(iommu->cmd_buf == NULL); | ||
530 | |||
531 | entry = (u64)virt_to_phys(iommu->cmd_buf); | ||
532 | entry |= MMIO_CMD_SIZE_512; | ||
533 | |||
534 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, | ||
535 | &entry, sizeof(entry)); | ||
536 | |||
537 | amd_iommu_reset_cmd_buffer(iommu); | ||
538 | iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); | ||
539 | } | ||
540 | |||
541 | static void __init free_command_buffer(struct amd_iommu *iommu) | ||
542 | { | ||
543 | free_pages((unsigned long)iommu->cmd_buf, | ||
544 | get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); | ||
545 | } | ||
546 | |||
547 | /* allocates the memory where the IOMMU will log its events to */ | ||
548 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | ||
549 | { | ||
550 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | ||
551 | get_order(EVT_BUFFER_SIZE)); | ||
552 | |||
553 | if (iommu->evt_buf == NULL) | ||
554 | return NULL; | ||
555 | |||
556 | iommu->evt_buf_size = EVT_BUFFER_SIZE; | ||
557 | |||
558 | return iommu->evt_buf; | ||
559 | } | ||
560 | |||
561 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | ||
562 | { | ||
563 | u64 entry; | ||
564 | |||
565 | BUG_ON(iommu->evt_buf == NULL); | ||
566 | |||
567 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; | ||
568 | |||
569 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, | ||
570 | &entry, sizeof(entry)); | ||
571 | |||
572 | /* set head and tail to zero manually */ | ||
573 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | ||
574 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | ||
575 | |||
576 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); | ||
577 | } | ||
578 | |||
579 | static void __init free_event_buffer(struct amd_iommu *iommu) | ||
580 | { | ||
581 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | ||
582 | } | ||
583 | |||
584 | /* sets a specific bit in the device table entry. */ | ||
585 | static void set_dev_entry_bit(u16 devid, u8 bit) | ||
586 | { | ||
587 | int i = (bit >> 5) & 0x07; | ||
588 | int _bit = bit & 0x1f; | ||
589 | |||
590 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | ||
591 | } | ||
592 | |||
593 | static int get_dev_entry_bit(u16 devid, u8 bit) | ||
594 | { | ||
595 | int i = (bit >> 5) & 0x07; | ||
596 | int _bit = bit & 0x1f; | ||
597 | |||
598 | return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit; | ||
599 | } | ||
600 | |||
601 | |||
602 | void amd_iommu_apply_erratum_63(u16 devid) | ||
603 | { | ||
604 | int sysmgt; | ||
605 | |||
606 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | ||
607 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | ||
608 | |||
609 | if (sysmgt == 0x01) | ||
610 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | ||
611 | } | ||
612 | |||
613 | /* Writes the specific IOMMU for a device into the rlookup table */ | ||
614 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | ||
615 | { | ||
616 | amd_iommu_rlookup_table[devid] = iommu; | ||
617 | } | ||
618 | |||
619 | /* | ||
620 | * This function takes the device specific flags read from the ACPI | ||
621 | * table and sets up the device table entry with that information | ||
622 | */ | ||
623 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, | ||
624 | u16 devid, u32 flags, u32 ext_flags) | ||
625 | { | ||
626 | if (flags & ACPI_DEVFLAG_INITPASS) | ||
627 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | ||
628 | if (flags & ACPI_DEVFLAG_EXTINT) | ||
629 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | ||
630 | if (flags & ACPI_DEVFLAG_NMI) | ||
631 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | ||
632 | if (flags & ACPI_DEVFLAG_SYSMGT1) | ||
633 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | ||
634 | if (flags & ACPI_DEVFLAG_SYSMGT2) | ||
635 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | ||
636 | if (flags & ACPI_DEVFLAG_LINT0) | ||
637 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | ||
638 | if (flags & ACPI_DEVFLAG_LINT1) | ||
639 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | ||
640 | |||
641 | amd_iommu_apply_erratum_63(devid); | ||
642 | |||
643 | set_iommu_for_device(iommu, devid); | ||
644 | } | ||
645 | |||
646 | /* | ||
647 | * Reads the device exclusion range from ACPI and initialize IOMMU with | ||
648 | * it | ||
649 | */ | ||
650 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) | ||
651 | { | ||
652 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | ||
653 | |||
654 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | ||
655 | return; | ||
656 | |||
657 | if (iommu) { | ||
658 | /* | ||
659 | * We only can configure exclusion ranges per IOMMU, not | ||
660 | * per device. But we can enable the exclusion range per | ||
661 | * device. This is done here | ||
662 | */ | ||
663 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); | ||
664 | iommu->exclusion_start = m->range_start; | ||
665 | iommu->exclusion_length = m->range_length; | ||
666 | } | ||
667 | } | ||
668 | |||
669 | /* | ||
670 | * This function reads some important data from the IOMMU PCI space and | ||
671 | * initializes the driver data structure with it. It reads the hardware | ||
672 | * capabilities and the first/last device entries | ||
673 | */ | ||
674 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) | ||
675 | { | ||
676 | int cap_ptr = iommu->cap_ptr; | ||
677 | u32 range, misc, low, high; | ||
678 | int i, j; | ||
679 | |||
680 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, | ||
681 | &iommu->cap); | ||
682 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | ||
683 | &range); | ||
684 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, | ||
685 | &misc); | ||
686 | |||
687 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), | ||
688 | MMIO_GET_FD(range)); | ||
689 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | ||
690 | MMIO_GET_LD(range)); | ||
691 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); | ||
692 | |||
693 | if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) | ||
694 | amd_iommu_iotlb_sup = false; | ||
695 | |||
696 | /* read extended feature bits */ | ||
697 | low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); | ||
698 | high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); | ||
699 | |||
700 | iommu->features = ((u64)high << 32) | low; | ||
701 | |||
702 | if (!is_rd890_iommu(iommu->dev)) | ||
703 | return; | ||
704 | |||
705 | /* | ||
706 | * Some rd890 systems may not be fully reconfigured by the BIOS, so | ||
707 | * it's necessary for us to store this information so it can be | ||
708 | * reprogrammed on resume | ||
709 | */ | ||
710 | |||
711 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, | ||
712 | &iommu->stored_addr_lo); | ||
713 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, | ||
714 | &iommu->stored_addr_hi); | ||
715 | |||
716 | /* Low bit locks writes to configuration space */ | ||
717 | iommu->stored_addr_lo &= ~1; | ||
718 | |||
719 | for (i = 0; i < 6; i++) | ||
720 | for (j = 0; j < 0x12; j++) | ||
721 | iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); | ||
722 | |||
723 | for (i = 0; i < 0x83; i++) | ||
724 | iommu->stored_l2[i] = iommu_read_l2(iommu, i); | ||
725 | } | ||
726 | |||
727 | /* | ||
728 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | ||
729 | * initializes the hardware and our data structures with it. | ||
730 | */ | ||
731 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, | ||
732 | struct ivhd_header *h) | ||
733 | { | ||
734 | u8 *p = (u8 *)h; | ||
735 | u8 *end = p, flags = 0; | ||
736 | u16 devid = 0, devid_start = 0, devid_to = 0; | ||
737 | u32 dev_i, ext_flags = 0; | ||
738 | bool alias = false; | ||
739 | struct ivhd_entry *e; | ||
740 | |||
741 | /* | ||
742 | * First save the recommended feature enable bits from ACPI | ||
743 | */ | ||
744 | iommu->acpi_flags = h->flags; | ||
745 | |||
746 | /* | ||
747 | * Done. Now parse the device entries | ||
748 | */ | ||
749 | p += sizeof(struct ivhd_header); | ||
750 | end += h->length; | ||
751 | |||
752 | |||
753 | while (p < end) { | ||
754 | e = (struct ivhd_entry *)p; | ||
755 | switch (e->type) { | ||
756 | case IVHD_DEV_ALL: | ||
757 | |||
758 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | ||
759 | " last device %02x:%02x.%x flags: %02x\n", | ||
760 | PCI_BUS(iommu->first_device), | ||
761 | PCI_SLOT(iommu->first_device), | ||
762 | PCI_FUNC(iommu->first_device), | ||
763 | PCI_BUS(iommu->last_device), | ||
764 | PCI_SLOT(iommu->last_device), | ||
765 | PCI_FUNC(iommu->last_device), | ||
766 | e->flags); | ||
767 | |||
768 | for (dev_i = iommu->first_device; | ||
769 | dev_i <= iommu->last_device; ++dev_i) | ||
770 | set_dev_entry_from_acpi(iommu, dev_i, | ||
771 | e->flags, 0); | ||
772 | break; | ||
773 | case IVHD_DEV_SELECT: | ||
774 | |||
775 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | ||
776 | "flags: %02x\n", | ||
777 | PCI_BUS(e->devid), | ||
778 | PCI_SLOT(e->devid), | ||
779 | PCI_FUNC(e->devid), | ||
780 | e->flags); | ||
781 | |||
782 | devid = e->devid; | ||
783 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); | ||
784 | break; | ||
785 | case IVHD_DEV_SELECT_RANGE_START: | ||
786 | |||
787 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | ||
788 | "devid: %02x:%02x.%x flags: %02x\n", | ||
789 | PCI_BUS(e->devid), | ||
790 | PCI_SLOT(e->devid), | ||
791 | PCI_FUNC(e->devid), | ||
792 | e->flags); | ||
793 | |||
794 | devid_start = e->devid; | ||
795 | flags = e->flags; | ||
796 | ext_flags = 0; | ||
797 | alias = false; | ||
798 | break; | ||
799 | case IVHD_DEV_ALIAS: | ||
800 | |||
801 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | ||
802 | "flags: %02x devid_to: %02x:%02x.%x\n", | ||
803 | PCI_BUS(e->devid), | ||
804 | PCI_SLOT(e->devid), | ||
805 | PCI_FUNC(e->devid), | ||
806 | e->flags, | ||
807 | PCI_BUS(e->ext >> 8), | ||
808 | PCI_SLOT(e->ext >> 8), | ||
809 | PCI_FUNC(e->ext >> 8)); | ||
810 | |||
811 | devid = e->devid; | ||
812 | devid_to = e->ext >> 8; | ||
813 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); | ||
814 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); | ||
815 | amd_iommu_alias_table[devid] = devid_to; | ||
816 | break; | ||
817 | case IVHD_DEV_ALIAS_RANGE: | ||
818 | |||
819 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | ||
820 | "devid: %02x:%02x.%x flags: %02x " | ||
821 | "devid_to: %02x:%02x.%x\n", | ||
822 | PCI_BUS(e->devid), | ||
823 | PCI_SLOT(e->devid), | ||
824 | PCI_FUNC(e->devid), | ||
825 | e->flags, | ||
826 | PCI_BUS(e->ext >> 8), | ||
827 | PCI_SLOT(e->ext >> 8), | ||
828 | PCI_FUNC(e->ext >> 8)); | ||
829 | |||
830 | devid_start = e->devid; | ||
831 | flags = e->flags; | ||
832 | devid_to = e->ext >> 8; | ||
833 | ext_flags = 0; | ||
834 | alias = true; | ||
835 | break; | ||
836 | case IVHD_DEV_EXT_SELECT: | ||
837 | |||
838 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | ||
839 | "flags: %02x ext: %08x\n", | ||
840 | PCI_BUS(e->devid), | ||
841 | PCI_SLOT(e->devid), | ||
842 | PCI_FUNC(e->devid), | ||
843 | e->flags, e->ext); | ||
844 | |||
845 | devid = e->devid; | ||
846 | set_dev_entry_from_acpi(iommu, devid, e->flags, | ||
847 | e->ext); | ||
848 | break; | ||
849 | case IVHD_DEV_EXT_SELECT_RANGE: | ||
850 | |||
851 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | ||
852 | "%02x:%02x.%x flags: %02x ext: %08x\n", | ||
853 | PCI_BUS(e->devid), | ||
854 | PCI_SLOT(e->devid), | ||
855 | PCI_FUNC(e->devid), | ||
856 | e->flags, e->ext); | ||
857 | |||
858 | devid_start = e->devid; | ||
859 | flags = e->flags; | ||
860 | ext_flags = e->ext; | ||
861 | alias = false; | ||
862 | break; | ||
863 | case IVHD_DEV_RANGE_END: | ||
864 | |||
865 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | ||
866 | PCI_BUS(e->devid), | ||
867 | PCI_SLOT(e->devid), | ||
868 | PCI_FUNC(e->devid)); | ||
869 | |||
870 | devid = e->devid; | ||
871 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | ||
872 | if (alias) { | ||
873 | amd_iommu_alias_table[dev_i] = devid_to; | ||
874 | set_dev_entry_from_acpi(iommu, | ||
875 | devid_to, flags, ext_flags); | ||
876 | } | ||
877 | set_dev_entry_from_acpi(iommu, dev_i, | ||
878 | flags, ext_flags); | ||
879 | } | ||
880 | break; | ||
881 | default: | ||
882 | break; | ||
883 | } | ||
884 | |||
885 | p += ivhd_entry_length(p); | ||
886 | } | ||
887 | } | ||
888 | |||
889 | /* Initializes the device->iommu mapping for the driver */ | ||
890 | static int __init init_iommu_devices(struct amd_iommu *iommu) | ||
891 | { | ||
892 | u32 i; | ||
893 | |||
894 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | ||
895 | set_iommu_for_device(iommu, i); | ||
896 | |||
897 | return 0; | ||
898 | } | ||
899 | |||
900 | static void __init free_iommu_one(struct amd_iommu *iommu) | ||
901 | { | ||
902 | free_command_buffer(iommu); | ||
903 | free_event_buffer(iommu); | ||
904 | iommu_unmap_mmio_space(iommu); | ||
905 | } | ||
906 | |||
907 | static void __init free_iommu_all(void) | ||
908 | { | ||
909 | struct amd_iommu *iommu, *next; | ||
910 | |||
911 | for_each_iommu_safe(iommu, next) { | ||
912 | list_del(&iommu->list); | ||
913 | free_iommu_one(iommu); | ||
914 | kfree(iommu); | ||
915 | } | ||
916 | } | ||
917 | |||
918 | /* | ||
919 | * This function clues the initialization function for one IOMMU | ||
920 | * together and also allocates the command buffer and programs the | ||
921 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | ||
922 | */ | ||
923 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) | ||
924 | { | ||
925 | spin_lock_init(&iommu->lock); | ||
926 | |||
927 | /* Add IOMMU to internal data structures */ | ||
928 | list_add_tail(&iommu->list, &amd_iommu_list); | ||
929 | iommu->index = amd_iommus_present++; | ||
930 | |||
931 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | ||
932 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | ||
933 | return -ENOSYS; | ||
934 | } | ||
935 | |||
936 | /* Index is fine - add IOMMU to the array */ | ||
937 | amd_iommus[iommu->index] = iommu; | ||
938 | |||
939 | /* | ||
940 | * Copy data from ACPI table entry to the iommu struct | ||
941 | */ | ||
942 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); | ||
943 | if (!iommu->dev) | ||
944 | return 1; | ||
945 | |||
946 | iommu->cap_ptr = h->cap_ptr; | ||
947 | iommu->pci_seg = h->pci_seg; | ||
948 | iommu->mmio_phys = h->mmio_phys; | ||
949 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | ||
950 | if (!iommu->mmio_base) | ||
951 | return -ENOMEM; | ||
952 | |||
953 | iommu->cmd_buf = alloc_command_buffer(iommu); | ||
954 | if (!iommu->cmd_buf) | ||
955 | return -ENOMEM; | ||
956 | |||
957 | iommu->evt_buf = alloc_event_buffer(iommu); | ||
958 | if (!iommu->evt_buf) | ||
959 | return -ENOMEM; | ||
960 | |||
961 | iommu->int_enabled = false; | ||
962 | |||
963 | init_iommu_from_pci(iommu); | ||
964 | init_iommu_from_acpi(iommu, h); | ||
965 | init_iommu_devices(iommu); | ||
966 | |||
967 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) | ||
968 | amd_iommu_np_cache = true; | ||
969 | |||
970 | return pci_enable_device(iommu->dev); | ||
971 | } | ||
972 | |||
973 | /* | ||
974 | * Iterates over all IOMMU entries in the ACPI table, allocates the | ||
975 | * IOMMU structure and initializes it with init_iommu_one() | ||
976 | */ | ||
977 | static int __init init_iommu_all(struct acpi_table_header *table) | ||
978 | { | ||
979 | u8 *p = (u8 *)table, *end = (u8 *)table; | ||
980 | struct ivhd_header *h; | ||
981 | struct amd_iommu *iommu; | ||
982 | int ret; | ||
983 | |||
984 | end += table->length; | ||
985 | p += IVRS_HEADER_LENGTH; | ||
986 | |||
987 | while (p < end) { | ||
988 | h = (struct ivhd_header *)p; | ||
989 | switch (*p) { | ||
990 | case ACPI_IVHD_TYPE: | ||
991 | |||
992 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " | ||
993 | "seg: %d flags: %01x info %04x\n", | ||
994 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | ||
995 | PCI_FUNC(h->devid), h->cap_ptr, | ||
996 | h->pci_seg, h->flags, h->info); | ||
997 | DUMP_printk(" mmio-addr: %016llx\n", | ||
998 | h->mmio_phys); | ||
999 | |||
1000 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); | ||
1001 | if (iommu == NULL) { | ||
1002 | amd_iommu_init_err = -ENOMEM; | ||
1003 | return 0; | ||
1004 | } | ||
1005 | |||
1006 | ret = init_iommu_one(iommu, h); | ||
1007 | if (ret) { | ||
1008 | amd_iommu_init_err = ret; | ||
1009 | return 0; | ||
1010 | } | ||
1011 | break; | ||
1012 | default: | ||
1013 | break; | ||
1014 | } | ||
1015 | p += h->length; | ||
1016 | |||
1017 | } | ||
1018 | WARN_ON(p != end); | ||
1019 | |||
1020 | return 0; | ||
1021 | } | ||
1022 | |||
1023 | /**************************************************************************** | ||
1024 | * | ||
1025 | * The following functions initialize the MSI interrupts for all IOMMUs | ||
1026 | * in the system. Its a bit challenging because there could be multiple | ||
1027 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | ||
1028 | * pci_dev. | ||
1029 | * | ||
1030 | ****************************************************************************/ | ||
1031 | |||
1032 | static int iommu_setup_msi(struct amd_iommu *iommu) | ||
1033 | { | ||
1034 | int r; | ||
1035 | |||
1036 | if (pci_enable_msi(iommu->dev)) | ||
1037 | return 1; | ||
1038 | |||
1039 | r = request_threaded_irq(iommu->dev->irq, | ||
1040 | amd_iommu_int_handler, | ||
1041 | amd_iommu_int_thread, | ||
1042 | 0, "AMD-Vi", | ||
1043 | iommu->dev); | ||
1044 | |||
1045 | if (r) { | ||
1046 | pci_disable_msi(iommu->dev); | ||
1047 | return 1; | ||
1048 | } | ||
1049 | |||
1050 | iommu->int_enabled = true; | ||
1051 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); | ||
1052 | |||
1053 | return 0; | ||
1054 | } | ||
1055 | |||
1056 | static int iommu_init_msi(struct amd_iommu *iommu) | ||
1057 | { | ||
1058 | if (iommu->int_enabled) | ||
1059 | return 0; | ||
1060 | |||
1061 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) | ||
1062 | return iommu_setup_msi(iommu); | ||
1063 | |||
1064 | return 1; | ||
1065 | } | ||
1066 | |||
1067 | /**************************************************************************** | ||
1068 | * | ||
1069 | * The next functions belong to the third pass of parsing the ACPI | ||
1070 | * table. In this last pass the memory mapping requirements are | ||
1071 | * gathered (like exclusion and unity mapping reanges). | ||
1072 | * | ||
1073 | ****************************************************************************/ | ||
1074 | |||
1075 | static void __init free_unity_maps(void) | ||
1076 | { | ||
1077 | struct unity_map_entry *entry, *next; | ||
1078 | |||
1079 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | ||
1080 | list_del(&entry->list); | ||
1081 | kfree(entry); | ||
1082 | } | ||
1083 | } | ||
1084 | |||
1085 | /* called when we find an exclusion range definition in ACPI */ | ||
1086 | static int __init init_exclusion_range(struct ivmd_header *m) | ||
1087 | { | ||
1088 | int i; | ||
1089 | |||
1090 | switch (m->type) { | ||
1091 | case ACPI_IVMD_TYPE: | ||
1092 | set_device_exclusion_range(m->devid, m); | ||
1093 | break; | ||
1094 | case ACPI_IVMD_TYPE_ALL: | ||
1095 | for (i = 0; i <= amd_iommu_last_bdf; ++i) | ||
1096 | set_device_exclusion_range(i, m); | ||
1097 | break; | ||
1098 | case ACPI_IVMD_TYPE_RANGE: | ||
1099 | for (i = m->devid; i <= m->aux; ++i) | ||
1100 | set_device_exclusion_range(i, m); | ||
1101 | break; | ||
1102 | default: | ||
1103 | break; | ||
1104 | } | ||
1105 | |||
1106 | return 0; | ||
1107 | } | ||
1108 | |||
1109 | /* called for unity map ACPI definition */ | ||
1110 | static int __init init_unity_map_range(struct ivmd_header *m) | ||
1111 | { | ||
1112 | struct unity_map_entry *e = 0; | ||
1113 | char *s; | ||
1114 | |||
1115 | e = kzalloc(sizeof(*e), GFP_KERNEL); | ||
1116 | if (e == NULL) | ||
1117 | return -ENOMEM; | ||
1118 | |||
1119 | switch (m->type) { | ||
1120 | default: | ||
1121 | kfree(e); | ||
1122 | return 0; | ||
1123 | case ACPI_IVMD_TYPE: | ||
1124 | s = "IVMD_TYPEi\t\t\t"; | ||
1125 | e->devid_start = e->devid_end = m->devid; | ||
1126 | break; | ||
1127 | case ACPI_IVMD_TYPE_ALL: | ||
1128 | s = "IVMD_TYPE_ALL\t\t"; | ||
1129 | e->devid_start = 0; | ||
1130 | e->devid_end = amd_iommu_last_bdf; | ||
1131 | break; | ||
1132 | case ACPI_IVMD_TYPE_RANGE: | ||
1133 | s = "IVMD_TYPE_RANGE\t\t"; | ||
1134 | e->devid_start = m->devid; | ||
1135 | e->devid_end = m->aux; | ||
1136 | break; | ||
1137 | } | ||
1138 | e->address_start = PAGE_ALIGN(m->range_start); | ||
1139 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | ||
1140 | e->prot = m->flags >> 1; | ||
1141 | |||
1142 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" | ||
1143 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | ||
1144 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | ||
1145 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | ||
1146 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | ||
1147 | e->address_start, e->address_end, m->flags); | ||
1148 | |||
1149 | list_add_tail(&e->list, &amd_iommu_unity_map); | ||
1150 | |||
1151 | return 0; | ||
1152 | } | ||
1153 | |||
1154 | /* iterates over all memory definitions we find in the ACPI table */ | ||
1155 | static int __init init_memory_definitions(struct acpi_table_header *table) | ||
1156 | { | ||
1157 | u8 *p = (u8 *)table, *end = (u8 *)table; | ||
1158 | struct ivmd_header *m; | ||
1159 | |||
1160 | end += table->length; | ||
1161 | p += IVRS_HEADER_LENGTH; | ||
1162 | |||
1163 | while (p < end) { | ||
1164 | m = (struct ivmd_header *)p; | ||
1165 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | ||
1166 | init_exclusion_range(m); | ||
1167 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | ||
1168 | init_unity_map_range(m); | ||
1169 | |||
1170 | p += m->length; | ||
1171 | } | ||
1172 | |||
1173 | return 0; | ||
1174 | } | ||
1175 | |||
1176 | /* | ||
1177 | * Init the device table to not allow DMA access for devices and | ||
1178 | * suppress all page faults | ||
1179 | */ | ||
1180 | static void init_device_table(void) | ||
1181 | { | ||
1182 | u32 devid; | ||
1183 | |||
1184 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | ||
1185 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | ||
1186 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | ||
1187 | } | ||
1188 | } | ||
1189 | |||
1190 | static void iommu_init_flags(struct amd_iommu *iommu) | ||
1191 | { | ||
1192 | iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? | ||
1193 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | ||
1194 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | ||
1195 | |||
1196 | iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? | ||
1197 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | ||
1198 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | ||
1199 | |||
1200 | iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? | ||
1201 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | ||
1202 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | ||
1203 | |||
1204 | iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? | ||
1205 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | ||
1206 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | ||
1207 | |||
1208 | /* | ||
1209 | * make IOMMU memory accesses cache coherent | ||
1210 | */ | ||
1211 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | ||
1212 | } | ||
1213 | |||
1214 | static void iommu_apply_resume_quirks(struct amd_iommu *iommu) | ||
1215 | { | ||
1216 | int i, j; | ||
1217 | u32 ioc_feature_control; | ||
1218 | struct pci_dev *pdev = NULL; | ||
1219 | |||
1220 | /* RD890 BIOSes may not have completely reconfigured the iommu */ | ||
1221 | if (!is_rd890_iommu(iommu->dev)) | ||
1222 | return; | ||
1223 | |||
1224 | /* | ||
1225 | * First, we need to ensure that the iommu is enabled. This is | ||
1226 | * controlled by a register in the northbridge | ||
1227 | */ | ||
1228 | pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0)); | ||
1229 | |||
1230 | if (!pdev) | ||
1231 | return; | ||
1232 | |||
1233 | /* Select Northbridge indirect register 0x75 and enable writing */ | ||
1234 | pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); | ||
1235 | pci_read_config_dword(pdev, 0x64, &ioc_feature_control); | ||
1236 | |||
1237 | /* Enable the iommu */ | ||
1238 | if (!(ioc_feature_control & 0x1)) | ||
1239 | pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); | ||
1240 | |||
1241 | pci_dev_put(pdev); | ||
1242 | |||
1243 | /* Restore the iommu BAR */ | ||
1244 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | ||
1245 | iommu->stored_addr_lo); | ||
1246 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, | ||
1247 | iommu->stored_addr_hi); | ||
1248 | |||
1249 | /* Restore the l1 indirect regs for each of the 6 l1s */ | ||
1250 | for (i = 0; i < 6; i++) | ||
1251 | for (j = 0; j < 0x12; j++) | ||
1252 | iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); | ||
1253 | |||
1254 | /* Restore the l2 indirect regs */ | ||
1255 | for (i = 0; i < 0x83; i++) | ||
1256 | iommu_write_l2(iommu, i, iommu->stored_l2[i]); | ||
1257 | |||
1258 | /* Lock PCI setup registers */ | ||
1259 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | ||
1260 | iommu->stored_addr_lo | 1); | ||
1261 | } | ||
1262 | |||
1263 | /* | ||
1264 | * This function finally enables all IOMMUs found in the system after | ||
1265 | * they have been initialized | ||
1266 | */ | ||
1267 | static void enable_iommus(void) | ||
1268 | { | ||
1269 | struct amd_iommu *iommu; | ||
1270 | |||
1271 | for_each_iommu(iommu) { | ||
1272 | iommu_disable(iommu); | ||
1273 | iommu_init_flags(iommu); | ||
1274 | iommu_set_device_table(iommu); | ||
1275 | iommu_enable_command_buffer(iommu); | ||
1276 | iommu_enable_event_buffer(iommu); | ||
1277 | iommu_set_exclusion_range(iommu); | ||
1278 | iommu_init_msi(iommu); | ||
1279 | iommu_enable(iommu); | ||
1280 | iommu_flush_all_caches(iommu); | ||
1281 | } | ||
1282 | } | ||
1283 | |||
1284 | static void disable_iommus(void) | ||
1285 | { | ||
1286 | struct amd_iommu *iommu; | ||
1287 | |||
1288 | for_each_iommu(iommu) | ||
1289 | iommu_disable(iommu); | ||
1290 | } | ||
1291 | |||
1292 | /* | ||
1293 | * Suspend/Resume support | ||
1294 | * disable suspend until real resume implemented | ||
1295 | */ | ||
1296 | |||
1297 | static void amd_iommu_resume(void) | ||
1298 | { | ||
1299 | struct amd_iommu *iommu; | ||
1300 | |||
1301 | for_each_iommu(iommu) | ||
1302 | iommu_apply_resume_quirks(iommu); | ||
1303 | |||
1304 | /* re-load the hardware */ | ||
1305 | enable_iommus(); | ||
1306 | |||
1307 | /* | ||
1308 | * we have to flush after the IOMMUs are enabled because a | ||
1309 | * disabled IOMMU will never execute the commands we send | ||
1310 | */ | ||
1311 | for_each_iommu(iommu) | ||
1312 | iommu_flush_all_caches(iommu); | ||
1313 | } | ||
1314 | |||
1315 | static int amd_iommu_suspend(void) | ||
1316 | { | ||
1317 | /* disable IOMMUs to go out of the way for BIOS */ | ||
1318 | disable_iommus(); | ||
1319 | |||
1320 | return 0; | ||
1321 | } | ||
1322 | |||
1323 | static struct syscore_ops amd_iommu_syscore_ops = { | ||
1324 | .suspend = amd_iommu_suspend, | ||
1325 | .resume = amd_iommu_resume, | ||
1326 | }; | ||
1327 | |||
1328 | /* | ||
1329 | * This is the core init function for AMD IOMMU hardware in the system. | ||
1330 | * This function is called from the generic x86 DMA layer initialization | ||
1331 | * code. | ||
1332 | * | ||
1333 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | ||
1334 | * three times: | ||
1335 | * | ||
1336 | * 1 pass) Find the highest PCI device id the driver has to handle. | ||
1337 | * Upon this information the size of the data structures is | ||
1338 | * determined that needs to be allocated. | ||
1339 | * | ||
1340 | * 2 pass) Initialize the data structures just allocated with the | ||
1341 | * information in the ACPI table about available AMD IOMMUs | ||
1342 | * in the system. It also maps the PCI devices in the | ||
1343 | * system to specific IOMMUs | ||
1344 | * | ||
1345 | * 3 pass) After the basic data structures are allocated and | ||
1346 | * initialized we update them with information about memory | ||
1347 | * remapping requirements parsed out of the ACPI table in | ||
1348 | * this last pass. | ||
1349 | * | ||
1350 | * After that the hardware is initialized and ready to go. In the last | ||
1351 | * step we do some Linux specific things like registering the driver in | ||
1352 | * the dma_ops interface and initializing the suspend/resume support | ||
1353 | * functions. Finally it prints some information about AMD IOMMUs and | ||
1354 | * the driver state and enables the hardware. | ||
1355 | */ | ||
1356 | static int __init amd_iommu_init(void) | ||
1357 | { | ||
1358 | int i, ret = 0; | ||
1359 | |||
1360 | /* | ||
1361 | * First parse ACPI tables to find the largest Bus/Dev/Func | ||
1362 | * we need to handle. Upon this information the shared data | ||
1363 | * structures for the IOMMUs in the system will be allocated | ||
1364 | */ | ||
1365 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | ||
1366 | return -ENODEV; | ||
1367 | |||
1368 | ret = amd_iommu_init_err; | ||
1369 | if (ret) | ||
1370 | goto out; | ||
1371 | |||
1372 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); | ||
1373 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | ||
1374 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | ||
1375 | |||
1376 | ret = -ENOMEM; | ||
1377 | |||
1378 | /* Device table - directly used by all IOMMUs */ | ||
1379 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | ||
1380 | get_order(dev_table_size)); | ||
1381 | if (amd_iommu_dev_table == NULL) | ||
1382 | goto out; | ||
1383 | |||
1384 | /* | ||
1385 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | ||
1386 | * IOMMU see for that device | ||
1387 | */ | ||
1388 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | ||
1389 | get_order(alias_table_size)); | ||
1390 | if (amd_iommu_alias_table == NULL) | ||
1391 | goto free; | ||
1392 | |||
1393 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | ||
1394 | amd_iommu_rlookup_table = (void *)__get_free_pages( | ||
1395 | GFP_KERNEL | __GFP_ZERO, | ||
1396 | get_order(rlookup_table_size)); | ||
1397 | if (amd_iommu_rlookup_table == NULL) | ||
1398 | goto free; | ||
1399 | |||
1400 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( | ||
1401 | GFP_KERNEL | __GFP_ZERO, | ||
1402 | get_order(MAX_DOMAIN_ID/8)); | ||
1403 | if (amd_iommu_pd_alloc_bitmap == NULL) | ||
1404 | goto free; | ||
1405 | |||
1406 | /* init the device table */ | ||
1407 | init_device_table(); | ||
1408 | |||
1409 | /* | ||
1410 | * let all alias entries point to itself | ||
1411 | */ | ||
1412 | for (i = 0; i <= amd_iommu_last_bdf; ++i) | ||
1413 | amd_iommu_alias_table[i] = i; | ||
1414 | |||
1415 | /* | ||
1416 | * never allocate domain 0 because its used as the non-allocated and | ||
1417 | * error value placeholder | ||
1418 | */ | ||
1419 | amd_iommu_pd_alloc_bitmap[0] = 1; | ||
1420 | |||
1421 | spin_lock_init(&amd_iommu_pd_lock); | ||
1422 | |||
1423 | /* | ||
1424 | * now the data structures are allocated and basically initialized | ||
1425 | * start the real acpi table scan | ||
1426 | */ | ||
1427 | ret = -ENODEV; | ||
1428 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | ||
1429 | goto free; | ||
1430 | |||
1431 | if (amd_iommu_init_err) { | ||
1432 | ret = amd_iommu_init_err; | ||
1433 | goto free; | ||
1434 | } | ||
1435 | |||
1436 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | ||
1437 | goto free; | ||
1438 | |||
1439 | if (amd_iommu_init_err) { | ||
1440 | ret = amd_iommu_init_err; | ||
1441 | goto free; | ||
1442 | } | ||
1443 | |||
1444 | ret = amd_iommu_init_devices(); | ||
1445 | if (ret) | ||
1446 | goto free; | ||
1447 | |||
1448 | enable_iommus(); | ||
1449 | |||
1450 | if (iommu_pass_through) | ||
1451 | ret = amd_iommu_init_passthrough(); | ||
1452 | else | ||
1453 | ret = amd_iommu_init_dma_ops(); | ||
1454 | |||
1455 | if (ret) | ||
1456 | goto free_disable; | ||
1457 | |||
1458 | amd_iommu_init_api(); | ||
1459 | |||
1460 | amd_iommu_init_notifier(); | ||
1461 | |||
1462 | register_syscore_ops(&amd_iommu_syscore_ops); | ||
1463 | |||
1464 | if (iommu_pass_through) | ||
1465 | goto out; | ||
1466 | |||
1467 | if (amd_iommu_unmap_flush) | ||
1468 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); | ||
1469 | else | ||
1470 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); | ||
1471 | |||
1472 | x86_platform.iommu_shutdown = disable_iommus; | ||
1473 | out: | ||
1474 | return ret; | ||
1475 | |||
1476 | free_disable: | ||
1477 | disable_iommus(); | ||
1478 | |||
1479 | free: | ||
1480 | amd_iommu_uninit_devices(); | ||
1481 | |||
1482 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, | ||
1483 | get_order(MAX_DOMAIN_ID/8)); | ||
1484 | |||
1485 | free_pages((unsigned long)amd_iommu_rlookup_table, | ||
1486 | get_order(rlookup_table_size)); | ||
1487 | |||
1488 | free_pages((unsigned long)amd_iommu_alias_table, | ||
1489 | get_order(alias_table_size)); | ||
1490 | |||
1491 | free_pages((unsigned long)amd_iommu_dev_table, | ||
1492 | get_order(dev_table_size)); | ||
1493 | |||
1494 | free_iommu_all(); | ||
1495 | |||
1496 | free_unity_maps(); | ||
1497 | |||
1498 | #ifdef CONFIG_GART_IOMMU | ||
1499 | /* | ||
1500 | * We failed to initialize the AMD IOMMU - try fallback to GART | ||
1501 | * if possible. | ||
1502 | */ | ||
1503 | gart_iommu_init(); | ||
1504 | |||
1505 | #endif | ||
1506 | |||
1507 | goto out; | ||
1508 | } | ||
1509 | |||
1510 | /**************************************************************************** | ||
1511 | * | ||
1512 | * Early detect code. This code runs at IOMMU detection time in the DMA | ||
1513 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | ||
1514 | * IOMMUs | ||
1515 | * | ||
1516 | ****************************************************************************/ | ||
1517 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) | ||
1518 | { | ||
1519 | return 0; | ||
1520 | } | ||
1521 | |||
1522 | int __init amd_iommu_detect(void) | ||
1523 | { | ||
1524 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) | ||
1525 | return -ENODEV; | ||
1526 | |||
1527 | if (amd_iommu_disabled) | ||
1528 | return -ENODEV; | ||
1529 | |||
1530 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { | ||
1531 | iommu_detected = 1; | ||
1532 | amd_iommu_detected = 1; | ||
1533 | x86_init.iommu.iommu_init = amd_iommu_init; | ||
1534 | |||
1535 | /* Make sure ACS will be enabled */ | ||
1536 | pci_request_acs(); | ||
1537 | return 1; | ||
1538 | } | ||
1539 | return -ENODEV; | ||
1540 | } | ||
1541 | |||
1542 | /**************************************************************************** | ||
1543 | * | ||
1544 | * Parsing functions for the AMD IOMMU specific kernel command line | ||
1545 | * options. | ||
1546 | * | ||
1547 | ****************************************************************************/ | ||
1548 | |||
1549 | static int __init parse_amd_iommu_dump(char *str) | ||
1550 | { | ||
1551 | amd_iommu_dump = true; | ||
1552 | |||
1553 | return 1; | ||
1554 | } | ||
1555 | |||
1556 | static int __init parse_amd_iommu_options(char *str) | ||
1557 | { | ||
1558 | for (; *str; ++str) { | ||
1559 | if (strncmp(str, "fullflush", 9) == 0) | ||
1560 | amd_iommu_unmap_flush = true; | ||
1561 | if (strncmp(str, "off", 3) == 0) | ||
1562 | amd_iommu_disabled = true; | ||
1563 | } | ||
1564 | |||
1565 | return 1; | ||
1566 | } | ||
1567 | |||
1568 | __setup("amd_iommu_dump", parse_amd_iommu_dump); | ||
1569 | __setup("amd_iommu=", parse_amd_iommu_options); | ||
1570 | |||
1571 | IOMMU_INIT_FINISH(amd_iommu_detect, | ||
1572 | gart_iommu_hole_init, | ||
1573 | 0, | ||
1574 | 0); | ||
diff --git a/drivers/iommu/amd_iommu_proto.h b/drivers/iommu/amd_iommu_proto.h new file mode 100644 index 000000000000..7ffaa64410b0 --- /dev/null +++ b/drivers/iommu/amd_iommu_proto.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2009-2010 Advanced Micro Devices, Inc. | ||
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms of the GNU General Public License version 2 as published | ||
7 | * by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | */ | ||
18 | |||
19 | #ifndef _ASM_X86_AMD_IOMMU_PROTO_H | ||
20 | #define _ASM_X86_AMD_IOMMU_PROTO_H | ||
21 | |||
22 | #include "amd_iommu_types.h" | ||
23 | |||
24 | extern int amd_iommu_init_dma_ops(void); | ||
25 | extern int amd_iommu_init_passthrough(void); | ||
26 | extern irqreturn_t amd_iommu_int_thread(int irq, void *data); | ||
27 | extern irqreturn_t amd_iommu_int_handler(int irq, void *data); | ||
28 | extern void amd_iommu_apply_erratum_63(u16 devid); | ||
29 | extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu); | ||
30 | extern int amd_iommu_init_devices(void); | ||
31 | extern void amd_iommu_uninit_devices(void); | ||
32 | extern void amd_iommu_init_notifier(void); | ||
33 | extern void amd_iommu_init_api(void); | ||
34 | #ifndef CONFIG_AMD_IOMMU_STATS | ||
35 | |||
36 | static inline void amd_iommu_stats_init(void) { } | ||
37 | |||
38 | #endif /* !CONFIG_AMD_IOMMU_STATS */ | ||
39 | |||
40 | static inline bool is_rd890_iommu(struct pci_dev *pdev) | ||
41 | { | ||
42 | return (pdev->vendor == PCI_VENDOR_ID_ATI) && | ||
43 | (pdev->device == PCI_DEVICE_ID_RD890_IOMMU); | ||
44 | } | ||
45 | |||
46 | static inline bool iommu_feature(struct amd_iommu *iommu, u64 f) | ||
47 | { | ||
48 | if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) | ||
49 | return false; | ||
50 | |||
51 | return !!(iommu->features & f); | ||
52 | } | ||
53 | |||
54 | #endif /* _ASM_X86_AMD_IOMMU_PROTO_H */ | ||
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h new file mode 100644 index 000000000000..4c9982995414 --- /dev/null +++ b/drivers/iommu/amd_iommu_types.h | |||
@@ -0,0 +1,580 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. | ||
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | ||
4 | * Leo Duran <leo.duran@amd.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License version 2 as published | ||
8 | * by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
18 | */ | ||
19 | |||
20 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H | ||
21 | #define _ASM_X86_AMD_IOMMU_TYPES_H | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | #include <linux/mutex.h> | ||
25 | #include <linux/list.h> | ||
26 | #include <linux/spinlock.h> | ||
27 | |||
28 | /* | ||
29 | * Maximum number of IOMMUs supported | ||
30 | */ | ||
31 | #define MAX_IOMMUS 32 | ||
32 | |||
33 | /* | ||
34 | * some size calculation constants | ||
35 | */ | ||
36 | #define DEV_TABLE_ENTRY_SIZE 32 | ||
37 | #define ALIAS_TABLE_ENTRY_SIZE 2 | ||
38 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) | ||
39 | |||
40 | /* Length of the MMIO region for the AMD IOMMU */ | ||
41 | #define MMIO_REGION_LENGTH 0x4000 | ||
42 | |||
43 | /* Capability offsets used by the driver */ | ||
44 | #define MMIO_CAP_HDR_OFFSET 0x00 | ||
45 | #define MMIO_RANGE_OFFSET 0x0c | ||
46 | #define MMIO_MISC_OFFSET 0x10 | ||
47 | |||
48 | /* Masks, shifts and macros to parse the device range capability */ | ||
49 | #define MMIO_RANGE_LD_MASK 0xff000000 | ||
50 | #define MMIO_RANGE_FD_MASK 0x00ff0000 | ||
51 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 | ||
52 | #define MMIO_RANGE_LD_SHIFT 24 | ||
53 | #define MMIO_RANGE_FD_SHIFT 16 | ||
54 | #define MMIO_RANGE_BUS_SHIFT 8 | ||
55 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) | ||
56 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) | ||
57 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) | ||
58 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) | ||
59 | |||
60 | /* Flag masks for the AMD IOMMU exclusion range */ | ||
61 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL | ||
62 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL | ||
63 | |||
64 | /* Used offsets into the MMIO space */ | ||
65 | #define MMIO_DEV_TABLE_OFFSET 0x0000 | ||
66 | #define MMIO_CMD_BUF_OFFSET 0x0008 | ||
67 | #define MMIO_EVT_BUF_OFFSET 0x0010 | ||
68 | #define MMIO_CONTROL_OFFSET 0x0018 | ||
69 | #define MMIO_EXCL_BASE_OFFSET 0x0020 | ||
70 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 | ||
71 | #define MMIO_EXT_FEATURES 0x0030 | ||
72 | #define MMIO_CMD_HEAD_OFFSET 0x2000 | ||
73 | #define MMIO_CMD_TAIL_OFFSET 0x2008 | ||
74 | #define MMIO_EVT_HEAD_OFFSET 0x2010 | ||
75 | #define MMIO_EVT_TAIL_OFFSET 0x2018 | ||
76 | #define MMIO_STATUS_OFFSET 0x2020 | ||
77 | |||
78 | |||
79 | /* Extended Feature Bits */ | ||
80 | #define FEATURE_PREFETCH (1ULL<<0) | ||
81 | #define FEATURE_PPR (1ULL<<1) | ||
82 | #define FEATURE_X2APIC (1ULL<<2) | ||
83 | #define FEATURE_NX (1ULL<<3) | ||
84 | #define FEATURE_GT (1ULL<<4) | ||
85 | #define FEATURE_IA (1ULL<<6) | ||
86 | #define FEATURE_GA (1ULL<<7) | ||
87 | #define FEATURE_HE (1ULL<<8) | ||
88 | #define FEATURE_PC (1ULL<<9) | ||
89 | |||
90 | /* MMIO status bits */ | ||
91 | #define MMIO_STATUS_COM_WAIT_INT_MASK 0x04 | ||
92 | |||
93 | /* event logging constants */ | ||
94 | #define EVENT_ENTRY_SIZE 0x10 | ||
95 | #define EVENT_TYPE_SHIFT 28 | ||
96 | #define EVENT_TYPE_MASK 0xf | ||
97 | #define EVENT_TYPE_ILL_DEV 0x1 | ||
98 | #define EVENT_TYPE_IO_FAULT 0x2 | ||
99 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 | ||
100 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 | ||
101 | #define EVENT_TYPE_ILL_CMD 0x5 | ||
102 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 | ||
103 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 | ||
104 | #define EVENT_TYPE_INV_DEV_REQ 0x8 | ||
105 | #define EVENT_DEVID_MASK 0xffff | ||
106 | #define EVENT_DEVID_SHIFT 0 | ||
107 | #define EVENT_DOMID_MASK 0xffff | ||
108 | #define EVENT_DOMID_SHIFT 0 | ||
109 | #define EVENT_FLAGS_MASK 0xfff | ||
110 | #define EVENT_FLAGS_SHIFT 0x10 | ||
111 | |||
112 | /* feature control bits */ | ||
113 | #define CONTROL_IOMMU_EN 0x00ULL | ||
114 | #define CONTROL_HT_TUN_EN 0x01ULL | ||
115 | #define CONTROL_EVT_LOG_EN 0x02ULL | ||
116 | #define CONTROL_EVT_INT_EN 0x03ULL | ||
117 | #define CONTROL_COMWAIT_EN 0x04ULL | ||
118 | #define CONTROL_PASSPW_EN 0x08ULL | ||
119 | #define CONTROL_RESPASSPW_EN 0x09ULL | ||
120 | #define CONTROL_COHERENT_EN 0x0aULL | ||
121 | #define CONTROL_ISOC_EN 0x0bULL | ||
122 | #define CONTROL_CMDBUF_EN 0x0cULL | ||
123 | #define CONTROL_PPFLOG_EN 0x0dULL | ||
124 | #define CONTROL_PPFINT_EN 0x0eULL | ||
125 | |||
126 | /* command specific defines */ | ||
127 | #define CMD_COMPL_WAIT 0x01 | ||
128 | #define CMD_INV_DEV_ENTRY 0x02 | ||
129 | #define CMD_INV_IOMMU_PAGES 0x03 | ||
130 | #define CMD_INV_IOTLB_PAGES 0x04 | ||
131 | #define CMD_INV_ALL 0x08 | ||
132 | |||
133 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 | ||
134 | #define CMD_COMPL_WAIT_INT_MASK 0x02 | ||
135 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 | ||
136 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 | ||
137 | |||
138 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL | ||
139 | |||
140 | /* macros and definitions for device table entries */ | ||
141 | #define DEV_ENTRY_VALID 0x00 | ||
142 | #define DEV_ENTRY_TRANSLATION 0x01 | ||
143 | #define DEV_ENTRY_IR 0x3d | ||
144 | #define DEV_ENTRY_IW 0x3e | ||
145 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 | ||
146 | #define DEV_ENTRY_EX 0x67 | ||
147 | #define DEV_ENTRY_SYSMGT1 0x68 | ||
148 | #define DEV_ENTRY_SYSMGT2 0x69 | ||
149 | #define DEV_ENTRY_INIT_PASS 0xb8 | ||
150 | #define DEV_ENTRY_EINT_PASS 0xb9 | ||
151 | #define DEV_ENTRY_NMI_PASS 0xba | ||
152 | #define DEV_ENTRY_LINT0_PASS 0xbe | ||
153 | #define DEV_ENTRY_LINT1_PASS 0xbf | ||
154 | #define DEV_ENTRY_MODE_MASK 0x07 | ||
155 | #define DEV_ENTRY_MODE_SHIFT 0x09 | ||
156 | |||
157 | /* constants to configure the command buffer */ | ||
158 | #define CMD_BUFFER_SIZE 8192 | ||
159 | #define CMD_BUFFER_UNINITIALIZED 1 | ||
160 | #define CMD_BUFFER_ENTRIES 512 | ||
161 | #define MMIO_CMD_SIZE_SHIFT 56 | ||
162 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) | ||
163 | |||
164 | /* constants for event buffer handling */ | ||
165 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ | ||
166 | #define EVT_LEN_MASK (0x9ULL << 56) | ||
167 | |||
168 | #define PAGE_MODE_NONE 0x00 | ||
169 | #define PAGE_MODE_1_LEVEL 0x01 | ||
170 | #define PAGE_MODE_2_LEVEL 0x02 | ||
171 | #define PAGE_MODE_3_LEVEL 0x03 | ||
172 | #define PAGE_MODE_4_LEVEL 0x04 | ||
173 | #define PAGE_MODE_5_LEVEL 0x05 | ||
174 | #define PAGE_MODE_6_LEVEL 0x06 | ||
175 | |||
176 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) | ||
177 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ | ||
178 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ | ||
179 | (0xffffffffffffffffULL)) | ||
180 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) | ||
181 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) | ||
182 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ | ||
183 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) | ||
184 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) | ||
185 | |||
186 | #define PM_MAP_4k 0 | ||
187 | #define PM_ADDR_MASK 0x000ffffffffff000ULL | ||
188 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ | ||
189 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) | ||
190 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) | ||
191 | |||
192 | /* | ||
193 | * Returns the page table level to use for a given page size | ||
194 | * Pagesize is expected to be a power-of-two | ||
195 | */ | ||
196 | #define PAGE_SIZE_LEVEL(pagesize) \ | ||
197 | ((__ffs(pagesize) - 12) / 9) | ||
198 | /* | ||
199 | * Returns the number of ptes to use for a given page size | ||
200 | * Pagesize is expected to be a power-of-two | ||
201 | */ | ||
202 | #define PAGE_SIZE_PTE_COUNT(pagesize) \ | ||
203 | (1ULL << ((__ffs(pagesize) - 12) % 9)) | ||
204 | |||
205 | /* | ||
206 | * Aligns a given io-virtual address to a given page size | ||
207 | * Pagesize is expected to be a power-of-two | ||
208 | */ | ||
209 | #define PAGE_SIZE_ALIGN(address, pagesize) \ | ||
210 | ((address) & ~((pagesize) - 1)) | ||
211 | /* | ||
212 | * Creates an IOMMU PTE for an address an a given pagesize | ||
213 | * The PTE has no permission bits set | ||
214 | * Pagesize is expected to be a power-of-two larger than 4096 | ||
215 | */ | ||
216 | #define PAGE_SIZE_PTE(address, pagesize) \ | ||
217 | (((address) | ((pagesize) - 1)) & \ | ||
218 | (~(pagesize >> 1)) & PM_ADDR_MASK) | ||
219 | |||
220 | /* | ||
221 | * Takes a PTE value with mode=0x07 and returns the page size it maps | ||
222 | */ | ||
223 | #define PTE_PAGE_SIZE(pte) \ | ||
224 | (1ULL << (1 + ffz(((pte) | 0xfffULL)))) | ||
225 | |||
226 | #define IOMMU_PTE_P (1ULL << 0) | ||
227 | #define IOMMU_PTE_TV (1ULL << 1) | ||
228 | #define IOMMU_PTE_U (1ULL << 59) | ||
229 | #define IOMMU_PTE_FC (1ULL << 60) | ||
230 | #define IOMMU_PTE_IR (1ULL << 61) | ||
231 | #define IOMMU_PTE_IW (1ULL << 62) | ||
232 | |||
233 | #define DTE_FLAG_IOTLB 0x01 | ||
234 | |||
235 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) | ||
236 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) | ||
237 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) | ||
238 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) | ||
239 | |||
240 | #define IOMMU_PROT_MASK 0x03 | ||
241 | #define IOMMU_PROT_IR 0x01 | ||
242 | #define IOMMU_PROT_IW 0x02 | ||
243 | |||
244 | /* IOMMU capabilities */ | ||
245 | #define IOMMU_CAP_IOTLB 24 | ||
246 | #define IOMMU_CAP_NPCACHE 26 | ||
247 | #define IOMMU_CAP_EFR 27 | ||
248 | |||
249 | #define MAX_DOMAIN_ID 65536 | ||
250 | |||
251 | /* FIXME: move this macro to <linux/pci.h> */ | ||
252 | #define PCI_BUS(x) (((x) >> 8) & 0xff) | ||
253 | |||
254 | /* Protection domain flags */ | ||
255 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ | ||
256 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops | ||
257 | domain for an IOMMU */ | ||
258 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page | ||
259 | translation */ | ||
260 | |||
261 | extern bool amd_iommu_dump; | ||
262 | #define DUMP_printk(format, arg...) \ | ||
263 | do { \ | ||
264 | if (amd_iommu_dump) \ | ||
265 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ | ||
266 | } while(0); | ||
267 | |||
268 | /* global flag if IOMMUs cache non-present entries */ | ||
269 | extern bool amd_iommu_np_cache; | ||
270 | /* Only true if all IOMMUs support device IOTLBs */ | ||
271 | extern bool amd_iommu_iotlb_sup; | ||
272 | |||
273 | /* | ||
274 | * Make iterating over all IOMMUs easier | ||
275 | */ | ||
276 | #define for_each_iommu(iommu) \ | ||
277 | list_for_each_entry((iommu), &amd_iommu_list, list) | ||
278 | #define for_each_iommu_safe(iommu, next) \ | ||
279 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) | ||
280 | |||
281 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ | ||
282 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) | ||
283 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) | ||
284 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ | ||
285 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) | ||
286 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) | ||
287 | |||
288 | /* | ||
289 | * This structure contains generic data for IOMMU protection domains | ||
290 | * independent of their use. | ||
291 | */ | ||
292 | struct protection_domain { | ||
293 | struct list_head list; /* for list of all protection domains */ | ||
294 | struct list_head dev_list; /* List of all devices in this domain */ | ||
295 | spinlock_t lock; /* mostly used to lock the page table*/ | ||
296 | struct mutex api_lock; /* protect page tables in the iommu-api path */ | ||
297 | u16 id; /* the domain id written to the device table */ | ||
298 | int mode; /* paging mode (0-6 levels) */ | ||
299 | u64 *pt_root; /* page table root pointer */ | ||
300 | unsigned long flags; /* flags to find out type of domain */ | ||
301 | bool updated; /* complete domain flush required */ | ||
302 | unsigned dev_cnt; /* devices assigned to this domain */ | ||
303 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ | ||
304 | void *priv; /* private data */ | ||
305 | |||
306 | }; | ||
307 | |||
308 | /* | ||
309 | * This struct contains device specific data for the IOMMU | ||
310 | */ | ||
311 | struct iommu_dev_data { | ||
312 | struct list_head list; /* For domain->dev_list */ | ||
313 | struct device *dev; /* Device this data belong to */ | ||
314 | struct device *alias; /* The Alias Device */ | ||
315 | struct protection_domain *domain; /* Domain the device is bound to */ | ||
316 | atomic_t bind; /* Domain attach reverent count */ | ||
317 | }; | ||
318 | |||
319 | /* | ||
320 | * For dynamic growth the aperture size is split into ranges of 128MB of | ||
321 | * DMA address space each. This struct represents one such range. | ||
322 | */ | ||
323 | struct aperture_range { | ||
324 | |||
325 | /* address allocation bitmap */ | ||
326 | unsigned long *bitmap; | ||
327 | |||
328 | /* | ||
329 | * Array of PTE pages for the aperture. In this array we save all the | ||
330 | * leaf pages of the domain page table used for the aperture. This way | ||
331 | * we don't need to walk the page table to find a specific PTE. We can | ||
332 | * just calculate its address in constant time. | ||
333 | */ | ||
334 | u64 *pte_pages[64]; | ||
335 | |||
336 | unsigned long offset; | ||
337 | }; | ||
338 | |||
339 | /* | ||
340 | * Data container for a dma_ops specific protection domain | ||
341 | */ | ||
342 | struct dma_ops_domain { | ||
343 | struct list_head list; | ||
344 | |||
345 | /* generic protection domain information */ | ||
346 | struct protection_domain domain; | ||
347 | |||
348 | /* size of the aperture for the mappings */ | ||
349 | unsigned long aperture_size; | ||
350 | |||
351 | /* address we start to search for free addresses */ | ||
352 | unsigned long next_address; | ||
353 | |||
354 | /* address space relevant data */ | ||
355 | struct aperture_range *aperture[APERTURE_MAX_RANGES]; | ||
356 | |||
357 | /* This will be set to true when TLB needs to be flushed */ | ||
358 | bool need_flush; | ||
359 | |||
360 | /* | ||
361 | * if this is a preallocated domain, keep the device for which it was | ||
362 | * preallocated in this variable | ||
363 | */ | ||
364 | u16 target_dev; | ||
365 | }; | ||
366 | |||
367 | /* | ||
368 | * Structure where we save information about one hardware AMD IOMMU in the | ||
369 | * system. | ||
370 | */ | ||
371 | struct amd_iommu { | ||
372 | struct list_head list; | ||
373 | |||
374 | /* Index within the IOMMU array */ | ||
375 | int index; | ||
376 | |||
377 | /* locks the accesses to the hardware */ | ||
378 | spinlock_t lock; | ||
379 | |||
380 | /* Pointer to PCI device of this IOMMU */ | ||
381 | struct pci_dev *dev; | ||
382 | |||
383 | /* physical address of MMIO space */ | ||
384 | u64 mmio_phys; | ||
385 | /* virtual address of MMIO space */ | ||
386 | u8 *mmio_base; | ||
387 | |||
388 | /* capabilities of that IOMMU read from ACPI */ | ||
389 | u32 cap; | ||
390 | |||
391 | /* flags read from acpi table */ | ||
392 | u8 acpi_flags; | ||
393 | |||
394 | /* Extended features */ | ||
395 | u64 features; | ||
396 | |||
397 | /* | ||
398 | * Capability pointer. There could be more than one IOMMU per PCI | ||
399 | * device function if there are more than one AMD IOMMU capability | ||
400 | * pointers. | ||
401 | */ | ||
402 | u16 cap_ptr; | ||
403 | |||
404 | /* pci domain of this IOMMU */ | ||
405 | u16 pci_seg; | ||
406 | |||
407 | /* first device this IOMMU handles. read from PCI */ | ||
408 | u16 first_device; | ||
409 | /* last device this IOMMU handles. read from PCI */ | ||
410 | u16 last_device; | ||
411 | |||
412 | /* start of exclusion range of that IOMMU */ | ||
413 | u64 exclusion_start; | ||
414 | /* length of exclusion range of that IOMMU */ | ||
415 | u64 exclusion_length; | ||
416 | |||
417 | /* command buffer virtual address */ | ||
418 | u8 *cmd_buf; | ||
419 | /* size of command buffer */ | ||
420 | u32 cmd_buf_size; | ||
421 | |||
422 | /* size of event buffer */ | ||
423 | u32 evt_buf_size; | ||
424 | /* event buffer virtual address */ | ||
425 | u8 *evt_buf; | ||
426 | /* MSI number for event interrupt */ | ||
427 | u16 evt_msi_num; | ||
428 | |||
429 | /* true if interrupts for this IOMMU are already enabled */ | ||
430 | bool int_enabled; | ||
431 | |||
432 | /* if one, we need to send a completion wait command */ | ||
433 | bool need_sync; | ||
434 | |||
435 | /* default dma_ops domain for that IOMMU */ | ||
436 | struct dma_ops_domain *default_dom; | ||
437 | |||
438 | /* | ||
439 | * We can't rely on the BIOS to restore all values on reinit, so we | ||
440 | * need to stash them | ||
441 | */ | ||
442 | |||
443 | /* The iommu BAR */ | ||
444 | u32 stored_addr_lo; | ||
445 | u32 stored_addr_hi; | ||
446 | |||
447 | /* | ||
448 | * Each iommu has 6 l1s, each of which is documented as having 0x12 | ||
449 | * registers | ||
450 | */ | ||
451 | u32 stored_l1[6][0x12]; | ||
452 | |||
453 | /* The l2 indirect registers */ | ||
454 | u32 stored_l2[0x83]; | ||
455 | }; | ||
456 | |||
457 | /* | ||
458 | * List with all IOMMUs in the system. This list is not locked because it is | ||
459 | * only written and read at driver initialization or suspend time | ||
460 | */ | ||
461 | extern struct list_head amd_iommu_list; | ||
462 | |||
463 | /* | ||
464 | * Array with pointers to each IOMMU struct | ||
465 | * The indices are referenced in the protection domains | ||
466 | */ | ||
467 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; | ||
468 | |||
469 | /* Number of IOMMUs present in the system */ | ||
470 | extern int amd_iommus_present; | ||
471 | |||
472 | /* | ||
473 | * Declarations for the global list of all protection domains | ||
474 | */ | ||
475 | extern spinlock_t amd_iommu_pd_lock; | ||
476 | extern struct list_head amd_iommu_pd_list; | ||
477 | |||
478 | /* | ||
479 | * Structure defining one entry in the device table | ||
480 | */ | ||
481 | struct dev_table_entry { | ||
482 | u32 data[8]; | ||
483 | }; | ||
484 | |||
485 | /* | ||
486 | * One entry for unity mappings parsed out of the ACPI table. | ||
487 | */ | ||
488 | struct unity_map_entry { | ||
489 | struct list_head list; | ||
490 | |||
491 | /* starting device id this entry is used for (including) */ | ||
492 | u16 devid_start; | ||
493 | /* end device id this entry is used for (including) */ | ||
494 | u16 devid_end; | ||
495 | |||
496 | /* start address to unity map (including) */ | ||
497 | u64 address_start; | ||
498 | /* end address to unity map (including) */ | ||
499 | u64 address_end; | ||
500 | |||
501 | /* required protection */ | ||
502 | int prot; | ||
503 | }; | ||
504 | |||
505 | /* | ||
506 | * List of all unity mappings. It is not locked because as runtime it is only | ||
507 | * read. It is created at ACPI table parsing time. | ||
508 | */ | ||
509 | extern struct list_head amd_iommu_unity_map; | ||
510 | |||
511 | /* | ||
512 | * Data structures for device handling | ||
513 | */ | ||
514 | |||
515 | /* | ||
516 | * Device table used by hardware. Read and write accesses by software are | ||
517 | * locked with the amd_iommu_pd_table lock. | ||
518 | */ | ||
519 | extern struct dev_table_entry *amd_iommu_dev_table; | ||
520 | |||
521 | /* | ||
522 | * Alias table to find requestor ids to device ids. Not locked because only | ||
523 | * read on runtime. | ||
524 | */ | ||
525 | extern u16 *amd_iommu_alias_table; | ||
526 | |||
527 | /* | ||
528 | * Reverse lookup table to find the IOMMU which translates a specific device. | ||
529 | */ | ||
530 | extern struct amd_iommu **amd_iommu_rlookup_table; | ||
531 | |||
532 | /* size of the dma_ops aperture as power of 2 */ | ||
533 | extern unsigned amd_iommu_aperture_order; | ||
534 | |||
535 | /* largest PCI device id we expect translation requests for */ | ||
536 | extern u16 amd_iommu_last_bdf; | ||
537 | |||
538 | /* allocation bitmap for domain ids */ | ||
539 | extern unsigned long *amd_iommu_pd_alloc_bitmap; | ||
540 | |||
541 | /* | ||
542 | * If true, the addresses will be flushed on unmap time, not when | ||
543 | * they are reused | ||
544 | */ | ||
545 | extern bool amd_iommu_unmap_flush; | ||
546 | |||
547 | /* takes bus and device/function and returns the device id | ||
548 | * FIXME: should that be in generic PCI code? */ | ||
549 | static inline u16 calc_devid(u8 bus, u8 devfn) | ||
550 | { | ||
551 | return (((u16)bus) << 8) | devfn; | ||
552 | } | ||
553 | |||
554 | #ifdef CONFIG_AMD_IOMMU_STATS | ||
555 | |||
556 | struct __iommu_counter { | ||
557 | char *name; | ||
558 | struct dentry *dent; | ||
559 | u64 value; | ||
560 | }; | ||
561 | |||
562 | #define DECLARE_STATS_COUNTER(nm) \ | ||
563 | static struct __iommu_counter nm = { \ | ||
564 | .name = #nm, \ | ||
565 | } | ||
566 | |||
567 | #define INC_STATS_COUNTER(name) name.value += 1 | ||
568 | #define ADD_STATS_COUNTER(name, x) name.value += (x) | ||
569 | #define SUB_STATS_COUNTER(name, x) name.value -= (x) | ||
570 | |||
571 | #else /* CONFIG_AMD_IOMMU_STATS */ | ||
572 | |||
573 | #define DECLARE_STATS_COUNTER(name) | ||
574 | #define INC_STATS_COUNTER(name) | ||
575 | #define ADD_STATS_COUNTER(name, x) | ||
576 | #define SUB_STATS_COUNTER(name, x) | ||
577 | |||
578 | #endif /* CONFIG_AMD_IOMMU_STATS */ | ||
579 | |||
580 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ | ||