1 files changed, 5 insertions, 8 deletions

diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index c56790375e0f..542024ba6dba 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -1029,6 +1029,9 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
         if (!iommu->dev)
                 return 1;
 
+        iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
+                                                PCI_DEVFN(0, 0));
+
         iommu->cap_ptr = h->cap_ptr;
         iommu->pci_seg = h->pci_seg;
         iommu->mmio_phys = h->mmio_phys;
@@ -1323,20 +1326,16 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
 {
         int i, j;
         u32 ioc_feature_control;
-        struct pci_dev *pdev = NULL;
+        struct pci_dev *pdev = iommu->root_pdev;
 
         /* RD890 BIOSes may not have completely reconfigured the iommu */
-        if (!is_rd890_iommu(iommu->dev))
+        if (!is_rd890_iommu(iommu->dev) || !pdev)
                 return;
 
         /*
          * First, we need to ensure that the iommu is enabled. This is
          * controlled by a register in the northbridge
          */
-        pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
-
-        if (!pdev)
-                return;
 
         /* Select Northbridge indirect register 0x75 and enable writing */
         pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
@@ -1346,8 +1345,6 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
         if (!(ioc_feature_control & 0x1))
                 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
 
-        pci_dev_put(pdev);
-
         /* Restore the iommu BAR */
         pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
                                iommu->stored_addr_lo);