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Diffstat (limited to 'drivers/infiniband/hw/qib/qib_diag.c')
-rw-r--r--drivers/infiniband/hw/qib/qib_diag.c894
1 files changed, 894 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/qib/qib_diag.c b/drivers/infiniband/hw/qib/qib_diag.c
new file mode 100644
index 000000000000..ca98dd523752
--- /dev/null
+++ b/drivers/infiniband/hw/qib/qib_diag.c
@@ -0,0 +1,894 @@
1/*
2 * Copyright (c) 2010 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2006, 2007, 2008, 2009 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35/*
36 * This file contains support for diagnostic functions. It is accessed by
37 * opening the qib_diag device, normally minor number 129. Diagnostic use
38 * of the QLogic_IB chip may render the chip or board unusable until the
39 * driver is unloaded, or in some cases, until the system is rebooted.
40 *
41 * Accesses to the chip through this interface are not similar to going
42 * through the /sys/bus/pci resource mmap interface.
43 */
44
45#include <linux/io.h>
46#include <linux/pci.h>
47#include <linux/poll.h>
48#include <linux/vmalloc.h>
49#include <linux/fs.h>
50#include <linux/uaccess.h>
51
52#include "qib.h"
53#include "qib_common.h"
54
55/*
56 * Each client that opens the diag device must read then write
57 * offset 0, to prevent lossage from random cat or od. diag_state
58 * sequences this "handshake".
59 */
60enum diag_state { UNUSED = 0, OPENED, INIT, READY };
61
62/* State for an individual client. PID so children cannot abuse handshake */
63static struct qib_diag_client {
64 struct qib_diag_client *next;
65 struct qib_devdata *dd;
66 pid_t pid;
67 enum diag_state state;
68} *client_pool;
69
70/*
71 * Get a client struct. Recycled if possible, else kmalloc.
72 * Must be called with qib_mutex held
73 */
74static struct qib_diag_client *get_client(struct qib_devdata *dd)
75{
76 struct qib_diag_client *dc;
77
78 dc = client_pool;
79 if (dc)
80 /* got from pool remove it and use */
81 client_pool = dc->next;
82 else
83 /* None in pool, alloc and init */
84 dc = kmalloc(sizeof *dc, GFP_KERNEL);
85
86 if (dc) {
87 dc->next = NULL;
88 dc->dd = dd;
89 dc->pid = current->pid;
90 dc->state = OPENED;
91 }
92 return dc;
93}
94
95/*
96 * Return to pool. Must be called with qib_mutex held
97 */
98static void return_client(struct qib_diag_client *dc)
99{
100 struct qib_devdata *dd = dc->dd;
101 struct qib_diag_client *tdc, *rdc;
102
103 rdc = NULL;
104 if (dc == dd->diag_client) {
105 dd->diag_client = dc->next;
106 rdc = dc;
107 } else {
108 tdc = dc->dd->diag_client;
109 while (tdc) {
110 if (dc == tdc->next) {
111 tdc->next = dc->next;
112 rdc = dc;
113 break;
114 }
115 tdc = tdc->next;
116 }
117 }
118 if (rdc) {
119 rdc->state = UNUSED;
120 rdc->dd = NULL;
121 rdc->pid = 0;
122 rdc->next = client_pool;
123 client_pool = rdc;
124 }
125}
126
127static int qib_diag_open(struct inode *in, struct file *fp);
128static int qib_diag_release(struct inode *in, struct file *fp);
129static ssize_t qib_diag_read(struct file *fp, char __user *data,
130 size_t count, loff_t *off);
131static ssize_t qib_diag_write(struct file *fp, const char __user *data,
132 size_t count, loff_t *off);
133
134static const struct file_operations diag_file_ops = {
135 .owner = THIS_MODULE,
136 .write = qib_diag_write,
137 .read = qib_diag_read,
138 .open = qib_diag_open,
139 .release = qib_diag_release
140};
141
142static atomic_t diagpkt_count = ATOMIC_INIT(0);
143static struct cdev *diagpkt_cdev;
144static struct device *diagpkt_device;
145
146static ssize_t qib_diagpkt_write(struct file *fp, const char __user *data,
147 size_t count, loff_t *off);
148
149static const struct file_operations diagpkt_file_ops = {
150 .owner = THIS_MODULE,
151 .write = qib_diagpkt_write,
152};
153
154int qib_diag_add(struct qib_devdata *dd)
155{
156 char name[16];
157 int ret = 0;
158
159 if (atomic_inc_return(&diagpkt_count) == 1) {
160 ret = qib_cdev_init(QIB_DIAGPKT_MINOR, "ipath_diagpkt",
161 &diagpkt_file_ops, &diagpkt_cdev,
162 &diagpkt_device);
163 if (ret)
164 goto done;
165 }
166
167 snprintf(name, sizeof(name), "ipath_diag%d", dd->unit);
168 ret = qib_cdev_init(QIB_DIAG_MINOR_BASE + dd->unit, name,
169 &diag_file_ops, &dd->diag_cdev,
170 &dd->diag_device);
171done:
172 return ret;
173}
174
175static void qib_unregister_observers(struct qib_devdata *dd);
176
177void qib_diag_remove(struct qib_devdata *dd)
178{
179 struct qib_diag_client *dc;
180
181 if (atomic_dec_and_test(&diagpkt_count))
182 qib_cdev_cleanup(&diagpkt_cdev, &diagpkt_device);
183
184 qib_cdev_cleanup(&dd->diag_cdev, &dd->diag_device);
185
186 /*
187 * Return all diag_clients of this device. There should be none,
188 * as we are "guaranteed" that no clients are still open
189 */
190 while (dd->diag_client)
191 return_client(dd->diag_client);
192
193 /* Now clean up all unused client structs */
194 while (client_pool) {
195 dc = client_pool;
196 client_pool = dc->next;
197 kfree(dc);
198 }
199 /* Clean up observer list */
200 qib_unregister_observers(dd);
201}
202
203/* qib_remap_ioaddr32 - remap an offset into chip address space to __iomem *
204 *
205 * @dd: the qlogic_ib device
206 * @offs: the offset in chip-space
207 * @cntp: Pointer to max (byte) count for transfer starting at offset
208 * This returns a u32 __iomem * so it can be used for both 64 and 32-bit
209 * mapping. It is needed because with the use of PAT for control of
210 * write-combining, the logically contiguous address-space of the chip
211 * may be split into virtually non-contiguous spaces, with different
212 * attributes, which are them mapped to contiguous physical space
213 * based from the first BAR.
214 *
215 * The code below makes the same assumptions as were made in
216 * init_chip_wc_pat() (qib_init.c), copied here:
217 * Assumes chip address space looks like:
218 * - kregs + sregs + cregs + uregs (in any order)
219 * - piobufs (2K and 4K bufs in either order)
220 * or:
221 * - kregs + sregs + cregs (in any order)
222 * - piobufs (2K and 4K bufs in either order)
223 * - uregs
224 *
225 * If cntp is non-NULL, returns how many bytes from offset can be accessed
226 * Returns 0 if the offset is not mapped.
227 */
228static u32 __iomem *qib_remap_ioaddr32(struct qib_devdata *dd, u32 offset,
229 u32 *cntp)
230{
231 u32 kreglen;
232 u32 snd_bottom, snd_lim = 0;
233 u32 __iomem *krb32 = (u32 __iomem *)dd->kregbase;
234 u32 __iomem *map = NULL;
235 u32 cnt = 0;
236
237 /* First, simplest case, offset is within the first map. */
238 kreglen = (dd->kregend - dd->kregbase) * sizeof(u64);
239 if (offset < kreglen) {
240 map = krb32 + (offset / sizeof(u32));
241 cnt = kreglen - offset;
242 goto mapped;
243 }
244
245 /*
246 * Next check for user regs, the next most common case,
247 * and a cheap check because if they are not in the first map
248 * they are last in chip.
249 */
250 if (dd->userbase) {
251 /* If user regs mapped, they are after send, so set limit. */
252 u32 ulim = (dd->cfgctxts * dd->ureg_align) + dd->uregbase;
253 snd_lim = dd->uregbase;
254 krb32 = (u32 __iomem *)dd->userbase;
255 if (offset >= dd->uregbase && offset < ulim) {
256 map = krb32 + (offset - dd->uregbase) / sizeof(u32);
257 cnt = ulim - offset;
258 goto mapped;
259 }
260 }
261
262 /*
263 * Lastly, check for offset within Send Buffers.
264 * This is gnarly because struct devdata is deliberately vague
265 * about things like 7322 VL15 buffers, and we are not in
266 * chip-specific code here, so should not make many assumptions.
267 * The one we _do_ make is that the only chip that has more sndbufs
268 * than we admit is the 7322, and it has userregs above that, so
269 * we know the snd_lim.
270 */
271 /* Assume 2K buffers are first. */
272 snd_bottom = dd->pio2k_bufbase;
273 if (snd_lim == 0) {
274 u32 tot2k = dd->piobcnt2k * ALIGN(dd->piosize2k, dd->palign);
275 snd_lim = snd_bottom + tot2k;
276 }
277 /* If 4k buffers exist, account for them by bumping
278 * appropriate limit.
279 */
280 if (dd->piobcnt4k) {
281 u32 tot4k = dd->piobcnt4k * dd->align4k;
282 u32 offs4k = dd->piobufbase >> 32;
283 if (snd_bottom > offs4k)
284 snd_bottom = offs4k;
285 else {
286 /* 4k above 2k. Bump snd_lim, if needed*/
287 if (!dd->userbase)
288 snd_lim = offs4k + tot4k;
289 }
290 }
291 /*
292 * Judgement call: can we ignore the space between SendBuffs and
293 * UserRegs, where we would like to see vl15 buffs, but not more?
294 */
295 if (offset >= snd_bottom && offset < snd_lim) {
296 offset -= snd_bottom;
297 map = (u32 __iomem *)dd->piobase + (offset / sizeof(u32));
298 cnt = snd_lim - offset;
299 }
300
301mapped:
302 if (cntp)
303 *cntp = cnt;
304 return map;
305}
306
307/*
308 * qib_read_umem64 - read a 64-bit quantity from the chip into user space
309 * @dd: the qlogic_ib device
310 * @uaddr: the location to store the data in user memory
311 * @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore)
312 * @count: number of bytes to copy (multiple of 32 bits)
313 *
314 * This function also localizes all chip memory accesses.
315 * The copy should be written such that we read full cacheline packets
316 * from the chip. This is usually used for a single qword
317 *
318 * NOTE: This assumes the chip address is 64-bit aligned.
319 */
320static int qib_read_umem64(struct qib_devdata *dd, void __user *uaddr,
321 u32 regoffs, size_t count)
322{
323 const u64 __iomem *reg_addr;
324 const u64 __iomem *reg_end;
325 u32 limit;
326 int ret;
327
328 reg_addr = (const u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit);
329 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {
330 ret = -EINVAL;
331 goto bail;
332 }
333 if (count >= limit)
334 count = limit;
335 reg_end = reg_addr + (count / sizeof(u64));
336
337 /* not very efficient, but it works for now */
338 while (reg_addr < reg_end) {
339 u64 data = readq(reg_addr);
340
341 if (copy_to_user(uaddr, &data, sizeof(u64))) {
342 ret = -EFAULT;
343 goto bail;
344 }
345 reg_addr++;
346 uaddr += sizeof(u64);
347 }
348 ret = 0;
349bail:
350 return ret;
351}
352
353/*
354 * qib_write_umem64 - write a 64-bit quantity to the chip from user space
355 * @dd: the qlogic_ib device
356 * @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore)
357 * @uaddr: the source of the data in user memory
358 * @count: the number of bytes to copy (multiple of 32 bits)
359 *
360 * This is usually used for a single qword
361 * NOTE: This assumes the chip address is 64-bit aligned.
362 */
363
364static int qib_write_umem64(struct qib_devdata *dd, u32 regoffs,
365 const void __user *uaddr, size_t count)
366{
367 u64 __iomem *reg_addr;
368 const u64 __iomem *reg_end;
369 u32 limit;
370 int ret;
371
372 reg_addr = (u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit);
373 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {
374 ret = -EINVAL;
375 goto bail;
376 }
377 if (count >= limit)
378 count = limit;
379 reg_end = reg_addr + (count / sizeof(u64));
380
381 /* not very efficient, but it works for now */
382 while (reg_addr < reg_end) {
383 u64 data;
384 if (copy_from_user(&data, uaddr, sizeof(data))) {
385 ret = -EFAULT;
386 goto bail;
387 }
388 writeq(data, reg_addr);
389
390 reg_addr++;
391 uaddr += sizeof(u64);
392 }
393 ret = 0;
394bail:
395 return ret;
396}
397
398/*
399 * qib_read_umem32 - read a 32-bit quantity from the chip into user space
400 * @dd: the qlogic_ib device
401 * @uaddr: the location to store the data in user memory
402 * @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore)
403 * @count: number of bytes to copy
404 *
405 * read 32 bit values, not 64 bit; for memories that only
406 * support 32 bit reads; usually a single dword.
407 */
408static int qib_read_umem32(struct qib_devdata *dd, void __user *uaddr,
409 u32 regoffs, size_t count)
410{
411 const u32 __iomem *reg_addr;
412 const u32 __iomem *reg_end;
413 u32 limit;
414 int ret;
415
416 reg_addr = qib_remap_ioaddr32(dd, regoffs, &limit);
417 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {
418 ret = -EINVAL;
419 goto bail;
420 }
421 if (count >= limit)
422 count = limit;
423 reg_end = reg_addr + (count / sizeof(u32));
424
425 /* not very efficient, but it works for now */
426 while (reg_addr < reg_end) {
427 u32 data = readl(reg_addr);
428
429 if (copy_to_user(uaddr, &data, sizeof(data))) {
430 ret = -EFAULT;
431 goto bail;
432 }
433
434 reg_addr++;
435 uaddr += sizeof(u32);
436
437 }
438 ret = 0;
439bail:
440 return ret;
441}
442
443/*
444 * qib_write_umem32 - write a 32-bit quantity to the chip from user space
445 * @dd: the qlogic_ib device
446 * @regoffs: the offset from BAR0 (_NOT_ full pointer, anymore)
447 * @uaddr: the source of the data in user memory
448 * @count: number of bytes to copy
449 *
450 * write 32 bit values, not 64 bit; for memories that only
451 * support 32 bit write; usually a single dword.
452 */
453
454static int qib_write_umem32(struct qib_devdata *dd, u32 regoffs,
455 const void __user *uaddr, size_t count)
456{
457 u32 __iomem *reg_addr;
458 const u32 __iomem *reg_end;
459 u32 limit;
460 int ret;
461
462 reg_addr = qib_remap_ioaddr32(dd, regoffs, &limit);
463 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) {
464 ret = -EINVAL;
465 goto bail;
466 }
467 if (count >= limit)
468 count = limit;
469 reg_end = reg_addr + (count / sizeof(u32));
470
471 while (reg_addr < reg_end) {
472 u32 data;
473
474 if (copy_from_user(&data, uaddr, sizeof(data))) {
475 ret = -EFAULT;
476 goto bail;
477 }
478 writel(data, reg_addr);
479
480 reg_addr++;
481 uaddr += sizeof(u32);
482 }
483 ret = 0;
484bail:
485 return ret;
486}
487
488static int qib_diag_open(struct inode *in, struct file *fp)
489{
490 int unit = iminor(in) - QIB_DIAG_MINOR_BASE;
491 struct qib_devdata *dd;
492 struct qib_diag_client *dc;
493 int ret;
494
495 mutex_lock(&qib_mutex);
496
497 dd = qib_lookup(unit);
498
499 if (dd == NULL || !(dd->flags & QIB_PRESENT) ||
500 !dd->kregbase) {
501 ret = -ENODEV;
502 goto bail;
503 }
504
505 dc = get_client(dd);
506 if (!dc) {
507 ret = -ENOMEM;
508 goto bail;
509 }
510 dc->next = dd->diag_client;
511 dd->diag_client = dc;
512 fp->private_data = dc;
513 ret = 0;
514bail:
515 mutex_unlock(&qib_mutex);
516
517 return ret;
518}
519
520/**
521 * qib_diagpkt_write - write an IB packet
522 * @fp: the diag data device file pointer
523 * @data: qib_diag_pkt structure saying where to get the packet
524 * @count: size of data to write
525 * @off: unused by this code
526 */
527static ssize_t qib_diagpkt_write(struct file *fp,
528 const char __user *data,
529 size_t count, loff_t *off)
530{
531 u32 __iomem *piobuf;
532 u32 plen, clen, pbufn;
533 struct qib_diag_xpkt dp;
534 u32 *tmpbuf = NULL;
535 struct qib_devdata *dd;
536 struct qib_pportdata *ppd;
537 ssize_t ret = 0;
538
539 if (count != sizeof(dp)) {
540 ret = -EINVAL;
541 goto bail;
542 }
543 if (copy_from_user(&dp, data, sizeof(dp))) {
544 ret = -EFAULT;
545 goto bail;
546 }
547
548 dd = qib_lookup(dp.unit);
549 if (!dd || !(dd->flags & QIB_PRESENT) || !dd->kregbase) {
550 ret = -ENODEV;
551 goto bail;
552 }
553 if (!(dd->flags & QIB_INITTED)) {
554 /* no hardware, freeze, etc. */
555 ret = -ENODEV;
556 goto bail;
557 }
558
559 if (dp.version != _DIAG_XPKT_VERS) {
560 qib_dev_err(dd, "Invalid version %u for diagpkt_write\n",
561 dp.version);
562 ret = -EINVAL;
563 goto bail;
564 }
565 /* send count must be an exact number of dwords */
566 if (dp.len & 3) {
567 ret = -EINVAL;
568 goto bail;
569 }
570 if (!dp.port || dp.port > dd->num_pports) {
571 ret = -EINVAL;
572 goto bail;
573 }
574 ppd = &dd->pport[dp.port - 1];
575
576 /* need total length before first word written */
577 /* +1 word is for the qword padding */
578 plen = sizeof(u32) + dp.len;
579 clen = dp.len >> 2;
580
581 if ((plen + 4) > ppd->ibmaxlen) {
582 ret = -EINVAL;
583 goto bail; /* before writing pbc */
584 }
585 tmpbuf = vmalloc(plen);
586 if (!tmpbuf) {
587 qib_devinfo(dd->pcidev, "Unable to allocate tmp buffer, "
588 "failing\n");
589 ret = -ENOMEM;
590 goto bail;
591 }
592
593 if (copy_from_user(tmpbuf,
594 (const void __user *) (unsigned long) dp.data,
595 dp.len)) {
596 ret = -EFAULT;
597 goto bail;
598 }
599
600 plen >>= 2; /* in dwords */
601
602 if (dp.pbc_wd == 0)
603 dp.pbc_wd = plen;
604
605 piobuf = dd->f_getsendbuf(ppd, dp.pbc_wd, &pbufn);
606 if (!piobuf) {
607 ret = -EBUSY;
608 goto bail;
609 }
610 /* disarm it just to be extra sure */
611 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbufn));
612
613 /* disable header check on pbufn for this packet */
614 dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_DIS1, NULL);
615
616 writeq(dp.pbc_wd, piobuf);
617 /*
618 * Copy all but the trigger word, then flush, so it's written
619 * to chip before trigger word, then write trigger word, then
620 * flush again, so packet is sent.
621 */
622 if (dd->flags & QIB_PIO_FLUSH_WC) {
623 qib_flush_wc();
624 qib_pio_copy(piobuf + 2, tmpbuf, clen - 1);
625 qib_flush_wc();
626 __raw_writel(tmpbuf[clen - 1], piobuf + clen + 1);
627 } else
628 qib_pio_copy(piobuf + 2, tmpbuf, clen);
629
630 if (dd->flags & QIB_USE_SPCL_TRIG) {
631 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
632
633 qib_flush_wc();
634 __raw_writel(0xaebecede, piobuf + spcl_off);
635 }
636
637 /*
638 * Ensure buffer is written to the chip, then re-enable
639 * header checks (if supported by chip). The txchk
640 * code will ensure seen by chip before returning.
641 */
642 qib_flush_wc();
643 qib_sendbuf_done(dd, pbufn);
644 dd->f_txchk_change(dd, pbufn, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
645
646 ret = sizeof(dp);
647
648bail:
649 vfree(tmpbuf);
650 return ret;
651}
652
653static int qib_diag_release(struct inode *in, struct file *fp)
654{
655 mutex_lock(&qib_mutex);
656 return_client(fp->private_data);
657 fp->private_data = NULL;
658 mutex_unlock(&qib_mutex);
659 return 0;
660}
661
662/*
663 * Chip-specific code calls to register its interest in
664 * a specific range.
665 */
666struct diag_observer_list_elt {
667 struct diag_observer_list_elt *next;
668 const struct diag_observer *op;
669};
670
671int qib_register_observer(struct qib_devdata *dd,
672 const struct diag_observer *op)
673{
674 struct diag_observer_list_elt *olp;
675 int ret = -EINVAL;
676
677 if (!dd || !op)
678 goto bail;
679 ret = -ENOMEM;
680 olp = vmalloc(sizeof *olp);
681 if (!olp) {
682 printk(KERN_ERR QIB_DRV_NAME ": vmalloc for observer failed\n");
683 goto bail;
684 }
685 if (olp) {
686 unsigned long flags;
687
688 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
689 olp->op = op;
690 olp->next = dd->diag_observer_list;
691 dd->diag_observer_list = olp;
692 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
693 ret = 0;
694 }
695bail:
696 return ret;
697}
698
699/* Remove all registered observers when device is closed */
700static void qib_unregister_observers(struct qib_devdata *dd)
701{
702 struct diag_observer_list_elt *olp;
703 unsigned long flags;
704
705 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
706 olp = dd->diag_observer_list;
707 while (olp) {
708 /* Pop one observer, let go of lock */
709 dd->diag_observer_list = olp->next;
710 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
711 vfree(olp);
712 /* try again. */
713 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
714 olp = dd->diag_observer_list;
715 }
716 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
717}
718
719/*
720 * Find the observer, if any, for the specified address. Initial implementation
721 * is simple stack of observers. This must be called with diag transaction
722 * lock held.
723 */
724static const struct diag_observer *diag_get_observer(struct qib_devdata *dd,
725 u32 addr)
726{
727 struct diag_observer_list_elt *olp;
728 const struct diag_observer *op = NULL;
729
730 olp = dd->diag_observer_list;
731 while (olp) {
732 op = olp->op;
733 if (addr >= op->bottom && addr <= op->top)
734 break;
735 olp = olp->next;
736 }
737 if (!olp)
738 op = NULL;
739
740 return op;
741}
742
743static ssize_t qib_diag_read(struct file *fp, char __user *data,
744 size_t count, loff_t *off)
745{
746 struct qib_diag_client *dc = fp->private_data;
747 struct qib_devdata *dd = dc->dd;
748 void __iomem *kreg_base;
749 ssize_t ret;
750
751 if (dc->pid != current->pid) {
752 ret = -EPERM;
753 goto bail;
754 }
755
756 kreg_base = dd->kregbase;
757
758 if (count == 0)
759 ret = 0;
760 else if ((count % 4) || (*off % 4))
761 /* address or length is not 32-bit aligned, hence invalid */
762 ret = -EINVAL;
763 else if (dc->state < READY && (*off || count != 8))
764 ret = -EINVAL; /* prevent cat /dev/qib_diag* */
765 else {
766 unsigned long flags;
767 u64 data64 = 0;
768 int use_32;
769 const struct diag_observer *op;
770
771 use_32 = (count % 8) || (*off % 8);
772 ret = -1;
773 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
774 /*
775 * Check for observer on this address range.
776 * we only support a single 32 or 64-bit read
777 * via observer, currently.
778 */
779 op = diag_get_observer(dd, *off);
780 if (op) {
781 u32 offset = *off;
782 ret = op->hook(dd, op, offset, &data64, 0, use_32);
783 }
784 /*
785 * We need to release lock before any copy_to_user(),
786 * whether implicit in qib_read_umem* or explicit below.
787 */
788 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
789 if (!op) {
790 if (use_32)
791 /*
792 * Address or length is not 64-bit aligned;
793 * do 32-bit rd
794 */
795 ret = qib_read_umem32(dd, data, (u32) *off,
796 count);
797 else
798 ret = qib_read_umem64(dd, data, (u32) *off,
799 count);
800 } else if (ret == count) {
801 /* Below finishes case where observer existed */
802 ret = copy_to_user(data, &data64, use_32 ?
803 sizeof(u32) : sizeof(u64));
804 if (ret)
805 ret = -EFAULT;
806 }
807 }
808
809 if (ret >= 0) {
810 *off += count;
811 ret = count;
812 if (dc->state == OPENED)
813 dc->state = INIT;
814 }
815bail:
816 return ret;
817}
818
819static ssize_t qib_diag_write(struct file *fp, const char __user *data,
820 size_t count, loff_t *off)
821{
822 struct qib_diag_client *dc = fp->private_data;
823 struct qib_devdata *dd = dc->dd;
824 void __iomem *kreg_base;
825 ssize_t ret;
826
827 if (dc->pid != current->pid) {
828 ret = -EPERM;
829 goto bail;
830 }
831
832 kreg_base = dd->kregbase;
833
834 if (count == 0)
835 ret = 0;
836 else if ((count % 4) || (*off % 4))
837 /* address or length is not 32-bit aligned, hence invalid */
838 ret = -EINVAL;
839 else if (dc->state < READY &&
840 ((*off || count != 8) || dc->state != INIT))
841 /* No writes except second-step of init seq */
842 ret = -EINVAL; /* before any other write allowed */
843 else {
844 unsigned long flags;
845 const struct diag_observer *op = NULL;
846 int use_32 = (count % 8) || (*off % 8);
847
848 /*
849 * Check for observer on this address range.
850 * We only support a single 32 or 64-bit write
851 * via observer, currently. This helps, because
852 * we would otherwise have to jump through hoops
853 * to make "diag transaction" meaningful when we
854 * cannot do a copy_from_user while holding the lock.
855 */
856 if (count == 4 || count == 8) {
857 u64 data64;
858 u32 offset = *off;
859 ret = copy_from_user(&data64, data, count);
860 if (ret) {
861 ret = -EFAULT;
862 goto bail;
863 }
864 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
865 op = diag_get_observer(dd, *off);
866 if (op)
867 ret = op->hook(dd, op, offset, &data64, ~0Ull,
868 use_32);
869 spin_unlock_irqrestore(&dd->qib_diag_trans_lock, flags);
870 }
871
872 if (!op) {
873 if (use_32)
874 /*
875 * Address or length is not 64-bit aligned;
876 * do 32-bit write
877 */
878 ret = qib_write_umem32(dd, (u32) *off, data,
879 count);
880 else
881 ret = qib_write_umem64(dd, (u32) *off, data,
882 count);
883 }
884 }
885
886 if (ret >= 0) {
887 *off += count;
888 ret = count;
889 if (dc->state == INIT)
890 dc->state = READY; /* all read/write OK now */
891 }
892bail:
893 return ret;
894}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 08:53:58 -0500