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diff --git a/drivers/infiniband/hw/qib/qib.h b/drivers/infiniband/hw/qib/qib.h
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1#ifndef _QIB_KERNEL_H
2#define _QIB_KERNEL_H
3/*
4 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
5 * All rights reserved.
6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37/*
38 * This header file is the base header file for qlogic_ib kernel code
39 * qib_user.h serves a similar purpose for user code.
40 */
41
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/dma-mapping.h>
45#include <linux/mutex.h>
46#include <linux/list.h>
47#include <linux/scatterlist.h>
48#include <linux/io.h>
49#include <linux/fs.h>
50#include <linux/completion.h>
51#include <linux/kref.h>
52#include <linux/sched.h>
53
54#include "qib_common.h"
55#include "qib_verbs.h"
56
57/* only s/w major version of QLogic_IB we can handle */
58#define QIB_CHIP_VERS_MAJ 2U
59
60/* don't care about this except printing */
61#define QIB_CHIP_VERS_MIN 0U
62
63/* The Organization Unique Identifier (Mfg code), and its position in GUID */
64#define QIB_OUI 0x001175
65#define QIB_OUI_LSB 40
66
67/*
68 * per driver stats, either not device nor port-specific, or
69 * summed over all of the devices and ports.
70 * They are described by name via ipathfs filesystem, so layout
71 * and number of elements can change without breaking compatibility.
72 * If members are added or deleted qib_statnames[] in qib_fs.c must
73 * change to match.
74 */
75struct qlogic_ib_stats {
76 __u64 sps_ints; /* number of interrupts handled */
77 __u64 sps_errints; /* number of error interrupts */
78 __u64 sps_txerrs; /* tx-related packet errors */
79 __u64 sps_rcverrs; /* non-crc rcv packet errors */
80 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
81 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
82 __u64 sps_ctxts; /* number of contexts currently open */
83 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
84 __u64 sps_buffull;
85 __u64 sps_hdrfull;
86};
87
88extern struct qlogic_ib_stats qib_stats;
89extern struct pci_error_handlers qib_pci_err_handler;
90extern struct pci_driver qib_driver;
91
92#define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
93/*
94 * First-cut critierion for "device is active" is
95 * two thousand dwords combined Tx, Rx traffic per
96 * 5-second interval. SMA packets are 64 dwords,
97 * and occur "a few per second", presumably each way.
98 */
99#define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
100
101/*
102 * Struct used to indicate which errors are logged in each of the
103 * error-counters that are logged to EEPROM. A counter is incremented
104 * _once_ (saturating at 255) for each event with any bits set in
105 * the error or hwerror register masks below.
106 */
107#define QIB_EEP_LOG_CNT (4)
108struct qib_eep_log_mask {
109 u64 errs_to_log;
110 u64 hwerrs_to_log;
111};
112
113/*
114 * Below contains all data related to a single context (formerly called port).
115 */
116struct qib_ctxtdata {
117 void **rcvegrbuf;
118 dma_addr_t *rcvegrbuf_phys;
119 /* rcvhdrq base, needs mmap before useful */
120 void *rcvhdrq;
121 /* kernel virtual address where hdrqtail is updated */
122 void *rcvhdrtail_kvaddr;
123 /*
124 * temp buffer for expected send setup, allocated at open, instead
125 * of each setup call
126 */
127 void *tid_pg_list;
128 /*
129 * Shared page for kernel to signal user processes that send buffers
130 * need disarming. The process should call QIB_CMD_DISARM_BUFS
131 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
132 */
133 unsigned long *user_event_mask;
134 /* when waiting for rcv or pioavail */
135 wait_queue_head_t wait;
136 /*
137 * rcvegr bufs base, physical, must fit
138 * in 44 bits so 32 bit programs mmap64 44 bit works)
139 */
140 dma_addr_t rcvegr_phys;
141 /* mmap of hdrq, must fit in 44 bits */
142 dma_addr_t rcvhdrq_phys;
143 dma_addr_t rcvhdrqtailaddr_phys;
144
145 /*
146 * number of opens (including slave sub-contexts) on this instance
147 * (ignoring forks, dup, etc. for now)
148 */
149 int cnt;
150 /*
151 * how much space to leave at start of eager TID entries for
152 * protocol use, on each TID
153 */
154 /* instead of calculating it */
155 unsigned ctxt;
156 /* non-zero if ctxt is being shared. */
157 u16 subctxt_cnt;
158 /* non-zero if ctxt is being shared. */
159 u16 subctxt_id;
160 /* number of eager TID entries. */
161 u16 rcvegrcnt;
162 /* index of first eager TID entry. */
163 u16 rcvegr_tid_base;
164 /* number of pio bufs for this ctxt (all procs, if shared) */
165 u32 piocnt;
166 /* first pio buffer for this ctxt */
167 u32 pio_base;
168 /* chip offset of PIO buffers for this ctxt */
169 u32 piobufs;
170 /* how many alloc_pages() chunks in rcvegrbuf_pages */
171 u32 rcvegrbuf_chunks;
172 /* how many egrbufs per chunk */
173 u32 rcvegrbufs_perchunk;
174 /* order for rcvegrbuf_pages */
175 size_t rcvegrbuf_size;
176 /* rcvhdrq size (for freeing) */
177 size_t rcvhdrq_size;
178 /* per-context flags for fileops/intr communication */
179 unsigned long flag;
180 /* next expected TID to check when looking for free */
181 u32 tidcursor;
182 /* WAIT_RCV that timed out, no interrupt */
183 u32 rcvwait_to;
184 /* WAIT_PIO that timed out, no interrupt */
185 u32 piowait_to;
186 /* WAIT_RCV already happened, no wait */
187 u32 rcvnowait;
188 /* WAIT_PIO already happened, no wait */
189 u32 pionowait;
190 /* total number of polled urgent packets */
191 u32 urgent;
192 /* saved total number of polled urgent packets for poll edge trigger */
193 u32 urgent_poll;
194 /* pid of process using this ctxt */
195 pid_t pid;
196 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
197 /* same size as task_struct .comm[], command that opened context */
198 char comm[16];
199 /* pkeys set by this use of this ctxt */
200 u16 pkeys[4];
201 /* so file ops can get at unit */
202 struct qib_devdata *dd;
203 /* so funcs that need physical port can get it easily */
204 struct qib_pportdata *ppd;
205 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
206 void *subctxt_uregbase;
207 /* An array of pages for the eager receive buffers * N */
208 void *subctxt_rcvegrbuf;
209 /* An array of pages for the eager header queue entries * N */
210 void *subctxt_rcvhdr_base;
211 /* The version of the library which opened this ctxt */
212 u32 userversion;
213 /* Bitmask of active slaves */
214 u32 active_slaves;
215 /* Type of packets or conditions we want to poll for */
216 u16 poll_type;
217 /* receive packet sequence counter */
218 u8 seq_cnt;
219 u8 redirect_seq_cnt;
220 /* ctxt rcvhdrq head offset */
221 u32 head;
222 u32 pkt_count;
223 /* QPs waiting for context processing */
224 struct list_head qp_wait_list;
225};
226
227struct qib_sge_state;
228
229struct qib_sdma_txreq {
230 int flags;
231 int sg_count;
232 dma_addr_t addr;
233 void (*callback)(struct qib_sdma_txreq *, int);
234 u16 start_idx; /* sdma private */
235 u16 next_descq_idx; /* sdma private */
236 struct list_head list; /* sdma private */
237};
238
239struct qib_sdma_desc {
240 __le64 qw[2];
241};
242
243struct qib_verbs_txreq {
244 struct qib_sdma_txreq txreq;
245 struct qib_qp *qp;
246 struct qib_swqe *wqe;
247 u32 dwords;
248 u16 hdr_dwords;
249 u16 hdr_inx;
250 struct qib_pio_header *align_buf;
251 struct qib_mregion *mr;
252 struct qib_sge_state *ss;
253};
254
255#define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
256#define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
257#define QIB_SDMA_TXREQ_F_INTREQ 0x4
258#define QIB_SDMA_TXREQ_F_FREEBUF 0x8
259#define QIB_SDMA_TXREQ_F_FREEDESC 0x10
260
261#define QIB_SDMA_TXREQ_S_OK 0
262#define QIB_SDMA_TXREQ_S_SENDERROR 1
263#define QIB_SDMA_TXREQ_S_ABORTED 2
264#define QIB_SDMA_TXREQ_S_SHUTDOWN 3
265
266/*
267 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
268 * Mostly for MADs that set or query link parameters, also ipath
269 * config interfaces
270 */
271#define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
272#define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */
273#define QIB_IB_CFG_LWID 3 /* currently active Link-width */
274#define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
275#define QIB_IB_CFG_SPD 5 /* current Link spd */
276#define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
277#define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
278#define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
279#define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
280#define QIB_IB_CFG_OP_VLS 10 /* operational VLs */
281#define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
282#define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
283#define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
284#define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
285#define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
286#define QIB_IB_CFG_PKEYS 16 /* update partition keys */
287#define QIB_IB_CFG_MTU 17 /* update MTU in IBC */
288#define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */
289#define QIB_IB_CFG_VL_HIGH_LIMIT 19
290#define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
291#define QIB_IB_CFG_PORT 21 /* switch port we are connected to */
292
293/*
294 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16
295 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for
296 * QIB_IB_CFG_LINKDEFAULT cmd
297 */
298#define IB_LINKCMD_DOWN (0 << 16)
299#define IB_LINKCMD_ARMED (1 << 16)
300#define IB_LINKCMD_ACTIVE (2 << 16)
301#define IB_LINKINITCMD_NOP 0
302#define IB_LINKINITCMD_POLL 1
303#define IB_LINKINITCMD_SLEEP 2
304#define IB_LINKINITCMD_DISABLE 3
305
306/*
307 * valid states passed to qib_set_linkstate() user call
308 */
309#define QIB_IB_LINKDOWN 0
310#define QIB_IB_LINKARM 1
311#define QIB_IB_LINKACTIVE 2
312#define QIB_IB_LINKDOWN_ONLY 3
313#define QIB_IB_LINKDOWN_SLEEP 4
314#define QIB_IB_LINKDOWN_DISABLE 5
315
316/*
317 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed
318 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg
319 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They
320 * are also the the possible values for qib_link_speed_enabled and active
321 * The values were chosen to match values used within the IB spec.
322 */
323#define QIB_IB_SDR 1
324#define QIB_IB_DDR 2
325#define QIB_IB_QDR 4
326
327#define QIB_DEFAULT_MTU 4096
328
329/*
330 * Possible IB config parameters for f_get/set_ib_table()
331 */
332#define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */
333#define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */
334
335/*
336 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
337 * these are bits so they can be combined, e.g.
338 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB
339 */
340#define QIB_RCVCTRL_TAILUPD_ENB 0x01
341#define QIB_RCVCTRL_TAILUPD_DIS 0x02
342#define QIB_RCVCTRL_CTXT_ENB 0x04
343#define QIB_RCVCTRL_CTXT_DIS 0x08
344#define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
345#define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
346#define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
347#define QIB_RCVCTRL_PKEY_DIS 0x80
348#define QIB_RCVCTRL_BP_ENB 0x0100
349#define QIB_RCVCTRL_BP_DIS 0x0200
350#define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
351#define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
352
353/*
354 * Possible "operations" for f_sendctrl(ppd, op, var)
355 * these are bits so they can be combined, e.g.
356 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB
357 * Some operations (e.g. DISARM, ABORT) are known to
358 * be "one-shot", so do not modify shadow.
359 */
360#define QIB_SENDCTRL_DISARM (0x1000)
361#define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
362 /* available (0x2000) */
363#define QIB_SENDCTRL_AVAIL_DIS (0x4000)
364#define QIB_SENDCTRL_AVAIL_ENB (0x8000)
365#define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
366#define QIB_SENDCTRL_SEND_DIS (0x20000)
367#define QIB_SENDCTRL_SEND_ENB (0x40000)
368#define QIB_SENDCTRL_FLUSH (0x80000)
369#define QIB_SENDCTRL_CLEAR (0x100000)
370#define QIB_SENDCTRL_DISARM_ALL (0x200000)
371
372/*
373 * These are the generic indices for requesting per-port
374 * counter values via the f_portcntr function. They
375 * are always returned as 64 bit values, although most
376 * are 32 bit counters.
377 */
378/* send-related counters */
379#define QIBPORTCNTR_PKTSEND 0U
380#define QIBPORTCNTR_WORDSEND 1U
381#define QIBPORTCNTR_PSXMITDATA 2U
382#define QIBPORTCNTR_PSXMITPKTS 3U
383#define QIBPORTCNTR_PSXMITWAIT 4U
384#define QIBPORTCNTR_SENDSTALL 5U
385/* receive-related counters */
386#define QIBPORTCNTR_PKTRCV 6U
387#define QIBPORTCNTR_PSRCVDATA 7U
388#define QIBPORTCNTR_PSRCVPKTS 8U
389#define QIBPORTCNTR_RCVEBP 9U
390#define QIBPORTCNTR_RCVOVFL 10U
391#define QIBPORTCNTR_WORDRCV 11U
392/* IB link related error counters */
393#define QIBPORTCNTR_RXLOCALPHYERR 12U
394#define QIBPORTCNTR_RXVLERR 13U
395#define QIBPORTCNTR_ERRICRC 14U
396#define QIBPORTCNTR_ERRVCRC 15U
397#define QIBPORTCNTR_ERRLPCRC 16U
398#define QIBPORTCNTR_BADFORMAT 17U
399#define QIBPORTCNTR_ERR_RLEN 18U
400#define QIBPORTCNTR_IBSYMBOLERR 19U
401#define QIBPORTCNTR_INVALIDRLEN 20U
402#define QIBPORTCNTR_UNSUPVL 21U
403#define QIBPORTCNTR_EXCESSBUFOVFL 22U
404#define QIBPORTCNTR_ERRLINK 23U
405#define QIBPORTCNTR_IBLINKDOWN 24U
406#define QIBPORTCNTR_IBLINKERRRECOV 25U
407#define QIBPORTCNTR_LLI 26U
408/* other error counters */
409#define QIBPORTCNTR_RXDROPPKT 27U
410#define QIBPORTCNTR_VL15PKTDROP 28U
411#define QIBPORTCNTR_ERRPKEY 29U
412#define QIBPORTCNTR_KHDROVFL 30U
413/* sampling counters (these are actually control registers) */
414#define QIBPORTCNTR_PSINTERVAL 31U
415#define QIBPORTCNTR_PSSTART 32U
416#define QIBPORTCNTR_PSSTAT 33U
417
418/* how often we check for packet activity for "power on hours (in seconds) */
419#define ACTIVITY_TIMER 5
420
421/* Below is an opaque struct. Each chip (device) can maintain
422 * private data needed for its operation, but not germane to the
423 * rest of the driver. For convenience, we define another that
424 * is chip-specific, per-port
425 */
426struct qib_chip_specific;
427struct qib_chipport_specific;
428
429enum qib_sdma_states {
430 qib_sdma_state_s00_hw_down,
431 qib_sdma_state_s10_hw_start_up_wait,
432 qib_sdma_state_s20_idle,
433 qib_sdma_state_s30_sw_clean_up_wait,
434 qib_sdma_state_s40_hw_clean_up_wait,
435 qib_sdma_state_s50_hw_halt_wait,
436 qib_sdma_state_s99_running,
437};
438
439enum qib_sdma_events {
440 qib_sdma_event_e00_go_hw_down,
441 qib_sdma_event_e10_go_hw_start,
442 qib_sdma_event_e20_hw_started,
443 qib_sdma_event_e30_go_running,
444 qib_sdma_event_e40_sw_cleaned,
445 qib_sdma_event_e50_hw_cleaned,
446 qib_sdma_event_e60_hw_halted,
447 qib_sdma_event_e70_go_idle,
448 qib_sdma_event_e7220_err_halted,
449 qib_sdma_event_e7322_err_halted,
450 qib_sdma_event_e90_timer_tick,
451};
452
453extern char *qib_sdma_state_names[];
454extern char *qib_sdma_event_names[];
455
456struct sdma_set_state_action {
457 unsigned op_enable:1;
458 unsigned op_intenable:1;
459 unsigned op_halt:1;
460 unsigned op_drain:1;
461 unsigned go_s99_running_tofalse:1;
462 unsigned go_s99_running_totrue:1;
463};
464
465struct qib_sdma_state {
466 struct kref kref;
467 struct completion comp;
468 enum qib_sdma_states current_state;
469 struct sdma_set_state_action *set_state_action;
470 unsigned current_op;
471 unsigned go_s99_running;
472 unsigned first_sendbuf;
473 unsigned last_sendbuf; /* really last +1 */
474 /* debugging/devel */
475 enum qib_sdma_states previous_state;
476 unsigned previous_op;
477 enum qib_sdma_events last_event;
478};
479
480struct xmit_wait {
481 struct timer_list timer;
482 u64 counter;
483 u8 flags;
484 struct cache {
485 u64 psxmitdata;
486 u64 psrcvdata;
487 u64 psxmitpkts;
488 u64 psrcvpkts;
489 u64 psxmitwait;
490 } counter_cache;
491};
492
493/*
494 * The structure below encapsulates data relevant to a physical IB Port.
495 * Current chips support only one such port, but the separation
496 * clarifies things a bit. Note that to conform to IB conventions,
497 * port-numbers are one-based. The first or only port is port1.
498 */
499struct qib_pportdata {
500 struct qib_ibport ibport_data;
501
502 struct qib_devdata *dd;
503 struct qib_chippport_specific *cpspec; /* chip-specific per-port */
504 struct kobject pport_kobj;
505 struct kobject sl2vl_kobj;
506 struct kobject diagc_kobj;
507
508 /* GUID for this interface, in network order */
509 __be64 guid;
510
511 /* QIB_POLL, etc. link-state specific flags, per port */
512 u32 lflags;
513 /* qib_lflags driver is waiting for */
514 u32 state_wanted;
515 spinlock_t lflags_lock;
516 /* number of (port-specific) interrupts for this port -- saturates... */
517 u32 int_counter;
518
519 /* ref count for each pkey */
520 atomic_t pkeyrefs[4];
521
522 /*
523 * this address is mapped readonly into user processes so they can
524 * get status cheaply, whenever they want. One qword of status per port
525 */
526 u64 *statusp;
527
528 /* SendDMA related entries */
529 spinlock_t sdma_lock;
530 struct qib_sdma_state sdma_state;
531 unsigned long sdma_buf_jiffies;
532 struct qib_sdma_desc *sdma_descq;
533 u64 sdma_descq_added;
534 u64 sdma_descq_removed;
535 u16 sdma_descq_cnt;
536 u16 sdma_descq_tail;
537 u16 sdma_descq_head;
538 u16 sdma_next_intr;
539 u16 sdma_reset_wait;
540 u8 sdma_generation;
541 struct tasklet_struct sdma_sw_clean_up_task;
542 struct list_head sdma_activelist;
543
544 dma_addr_t sdma_descq_phys;
545 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */
546 dma_addr_t sdma_head_phys;
547
548 wait_queue_head_t state_wait; /* for state_wanted */
549
550 /* HoL blocking for SMP replies */
551 unsigned hol_state;
552 struct timer_list hol_timer;
553
554 /*
555 * Shadow copies of registers; size indicates read access size.
556 * Most of them are readonly, but some are write-only register,
557 * where we manipulate the bits in the shadow copy, and then write
558 * the shadow copy to qlogic_ib.
559 *
560 * We deliberately make most of these 32 bits, since they have
561 * restricted range. For any that we read, we won't to generate 32
562 * bit accesses, since Opteron will generate 2 separate 32 bit HT
563 * transactions for a 64 bit read, and we want to avoid unnecessary
564 * bus transactions.
565 */
566
567 /* This is the 64 bit group */
568 /* last ibcstatus. opaque outside chip-specific code */
569 u64 lastibcstat;
570
571 /* these are the "32 bit" regs */
572
573 /*
574 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
575 * all expect bit fields to be "unsigned long"
576 */
577 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */
578 unsigned long p_sendctrl; /* shadow per-port sendctrl */
579
580 u32 ibmtu; /* The MTU programmed for this unit */
581 /*
582 * Current max size IB packet (in bytes) including IB headers, that
583 * we can send. Changes when ibmtu changes.
584 */
585 u32 ibmaxlen;
586 /*
587 * ibmaxlen at init time, limited by chip and by receive buffer
588 * size. Not changed after init.
589 */
590 u32 init_ibmaxlen;
591 /* LID programmed for this instance */
592 u16 lid;
593 /* list of pkeys programmed; 0 if not set */
594 u16 pkeys[4];
595 /* LID mask control */
596 u8 lmc;
597 u8 link_width_supported;
598 u8 link_speed_supported;
599 u8 link_width_enabled;
600 u8 link_speed_enabled;
601 u8 link_width_active;
602 u8 link_speed_active;
603 u8 vls_supported;
604 u8 vls_operational;
605 /* Rx Polarity inversion (compensate for ~tx on partner) */
606 u8 rx_pol_inv;
607
608 u8 hw_pidx; /* physical port index */
609 u8 port; /* IB port number and index into dd->pports - 1 */
610
611 u8 delay_mult;
612
613 /* used to override LED behavior */
614 u8 led_override; /* Substituted for normal value, if non-zero */
615 u16 led_override_timeoff; /* delta to next timer event */
616 u8 led_override_vals[2]; /* Alternates per blink-frame */
617 u8 led_override_phase; /* Just counts, LSB picks from vals[] */
618 atomic_t led_override_timer_active;
619 /* Used to flash LEDs in override mode */
620 struct timer_list led_override_timer;
621 struct xmit_wait cong_stats;
622 struct timer_list symerr_clear_timer;
623};
624
625/* Observers. Not to be taken lightly, possibly not to ship. */
626/*
627 * If a diag read or write is to (bottom <= offset <= top),
628 * the "hoook" is called, allowing, e.g. shadows to be
629 * updated in sync with the driver. struct diag_observer
630 * is the "visible" part.
631 */
632struct diag_observer;
633
634typedef int (*diag_hook) (struct qib_devdata *dd,
635 const struct diag_observer *op,
636 u32 offs, u64 *data, u64 mask, int only_32);
637
638struct diag_observer {
639 diag_hook hook;
640 u32 bottom;
641 u32 top;
642};
643
644extern int qib_register_observer(struct qib_devdata *dd,
645 const struct diag_observer *op);
646
647/* Only declared here, not defined. Private to diags */
648struct diag_observer_list_elt;
649
650/* device data struct now contains only "general per-device" info.
651 * fields related to a physical IB port are in a qib_pportdata struct,
652 * described above) while fields only used by a particualr chip-type are in
653 * a qib_chipdata struct, whose contents are opaque to this file.
654 */
655struct qib_devdata {
656 struct qib_ibdev verbs_dev; /* must be first */
657 struct list_head list;
658 /* pointers to related structs for this device */
659 /* pci access data structure */
660 struct pci_dev *pcidev;
661 struct cdev *user_cdev;
662 struct cdev *diag_cdev;
663 struct device *user_device;
664 struct device *diag_device;
665
666 /* mem-mapped pointer to base of chip regs */
667 u64 __iomem *kregbase;
668 /* end of mem-mapped chip space excluding sendbuf and user regs */
669 u64 __iomem *kregend;
670 /* physical address of chip for io_remap, etc. */
671 resource_size_t physaddr;
672 /* qib_cfgctxts pointers */
673 struct qib_ctxtdata **rcd; /* Receive Context Data */
674
675 /* qib_pportdata, points to array of (physical) port-specific
676 * data structs, indexed by pidx (0..n-1)
677 */
678 struct qib_pportdata *pport;
679 struct qib_chip_specific *cspec; /* chip-specific */
680
681 /* kvirt address of 1st 2k pio buffer */
682 void __iomem *pio2kbase;
683 /* kvirt address of 1st 4k pio buffer */
684 void __iomem *pio4kbase;
685 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */
686 void __iomem *piobase;
687 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */
688 u64 __iomem *userbase;
689 /*
690 * points to area where PIOavail registers will be DMA'ed.
691 * Has to be on a page of it's own, because the page will be
692 * mapped into user program space. This copy is *ONLY* ever
693 * written by DMA, not by the driver! Need a copy per device
694 * when we get to multiple devices
695 */
696 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */
697 /* physical address where updates occur */
698 dma_addr_t pioavailregs_phys;
699
700 /* device-specific implementations of functions needed by
701 * common code. Contrary to previous consensus, we can't
702 * really just point to a device-specific table, because we
703 * may need to "bend", e.g. *_f_put_tid
704 */
705 /* fallback to alternate interrupt type if possible */
706 int (*f_intr_fallback)(struct qib_devdata *);
707 /* hard reset chip */
708 int (*f_reset)(struct qib_devdata *);
709 void (*f_quiet_serdes)(struct qib_pportdata *);
710 int (*f_bringup_serdes)(struct qib_pportdata *);
711 int (*f_early_init)(struct qib_devdata *);
712 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
713 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
714 u32, unsigned long);
715 void (*f_cleanup)(struct qib_devdata *);
716 void (*f_setextled)(struct qib_pportdata *, u32);
717 /* fill out chip-specific fields */
718 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
719 /* free irq */
720 void (*f_free_irq)(struct qib_devdata *);
721 struct qib_message_header *(*f_get_msgheader)
722 (struct qib_devdata *, __le32 *);
723 void (*f_config_ctxts)(struct qib_devdata *);
724 int (*f_get_ib_cfg)(struct qib_pportdata *, int);
725 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
726 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
727 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
728 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
729 u32 (*f_iblink_state)(u64);
730 u8 (*f_ibphys_portstate)(u64);
731 void (*f_xgxs_reset)(struct qib_pportdata *);
732 /* per chip actions needed for IB Link up/down changes */
733 int (*f_ib_updown)(struct qib_pportdata *, int, u64);
734 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
735 /* Read/modify/write of GPIO pins (potentially chip-specific */
736 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
737 u32 mask);
738 /* Enable writes to config EEPROM (if supported) */
739 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
740 /*
741 * modify rcvctrl shadow[s] and write to appropriate chip-regs.
742 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations.
743 * (ctxt == -1) means "all contexts", only meaningful for
744 * clearing. Could remove if chip_spec shutdown properly done.
745 */
746 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
747 int ctxt);
748 /* Read/modify/write sendctrl appropriately for op and port. */
749 void (*f_sendctrl)(struct qib_pportdata *, u32 op);
750 void (*f_set_intr_state)(struct qib_devdata *, u32);
751 void (*f_set_armlaunch)(struct qib_devdata *, u32);
752 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
753 int (*f_late_initreg)(struct qib_devdata *);
754 int (*f_init_sdma_regs)(struct qib_pportdata *);
755 u16 (*f_sdma_gethead)(struct qib_pportdata *);
756 int (*f_sdma_busy)(struct qib_pportdata *);
757 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
758 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
759 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
760 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
761 void (*f_sdma_hw_start_up)(struct qib_pportdata *);
762 void (*f_sdma_init_early)(struct qib_pportdata *);
763 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
764 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32);
765 u32 (*f_hdrqempty)(struct qib_ctxtdata *);
766 u64 (*f_portcntr)(struct qib_pportdata *, u32);
767 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
768 u64 **);
769 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
770 char **, u64 **);
771 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
772 void (*f_initvl15_bufs)(struct qib_devdata *);
773 void (*f_init_ctxt)(struct qib_ctxtdata *);
774 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
775 struct qib_ctxtdata *);
776 void (*f_writescratch)(struct qib_devdata *, u32);
777 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
778
779 char *boardname; /* human readable board info */
780
781 /* template for writing TIDs */
782 u64 tidtemplate;
783 /* value to write to free TIDs */
784 u64 tidinvalid;
785
786 /* number of registers used for pioavail */
787 u32 pioavregs;
788 /* device (not port) flags, basically device capabilities */
789 u32 flags;
790 /* last buffer for user use */
791 u32 lastctxt_piobuf;
792
793 /* saturating counter of (non-port-specific) device interrupts */
794 u32 int_counter;
795
796 /* pio bufs allocated per ctxt */
797 u32 pbufsctxt;
798 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */
799 u32 ctxts_extrabuf;
800 /*
801 * number of ctxts configured as max; zero is set to number chip
802 * supports, less gives more pio bufs/ctxt, etc.
803 */
804 u32 cfgctxts;
805
806 /*
807 * hint that we should update pioavailshadow before
808 * looking for a PIO buffer
809 */
810 u32 upd_pio_shadow;
811
812 /* internal debugging stats */
813 u32 maxpkts_call;
814 u32 avgpkts_call;
815 u64 nopiobufs;
816
817 /* PCI Vendor ID (here for NodeInfo) */
818 u16 vendorid;
819 /* PCI Device ID (here for NodeInfo) */
820 u16 deviceid;
821 /* for write combining settings */
822 unsigned long wc_cookie;
823 unsigned long wc_base;
824 unsigned long wc_len;
825
826 /* shadow copy of struct page *'s for exp tid pages */
827 struct page **pageshadow;
828 /* shadow copy of dma handles for exp tid pages */
829 dma_addr_t *physshadow;
830 u64 __iomem *egrtidbase;
831 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */
832 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
833 spinlock_t uctxt_lock; /* rcd and user context changes */
834 /*
835 * per unit status, see also portdata statusp
836 * mapped readonly into user processes so they can get unit and
837 * IB link status cheaply
838 */
839 u64 *devstatusp;
840 char *freezemsg; /* freeze msg if hw error put chip in freeze */
841 u32 freezelen; /* max length of freezemsg */
842 /* timer used to prevent stats overflow, error throttling, etc. */
843 struct timer_list stats_timer;
844
845 /* timer to verify interrupts work, and fallback if possible */
846 struct timer_list intrchk_timer;
847 unsigned long ureg_align; /* user register alignment */
848
849 /*
850 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and
851 * pio_writing.
852 */
853 spinlock_t pioavail_lock;
854
855 /*
856 * Shadow copies of registers; size indicates read access size.
857 * Most of them are readonly, but some are write-only register,
858 * where we manipulate the bits in the shadow copy, and then write
859 * the shadow copy to qlogic_ib.
860 *
861 * We deliberately make most of these 32 bits, since they have
862 * restricted range. For any that we read, we won't to generate 32
863 * bit accesses, since Opteron will generate 2 separate 32 bit HT
864 * transactions for a 64 bit read, and we want to avoid unnecessary
865 * bus transactions.
866 */
867
868 /* This is the 64 bit group */
869
870 unsigned long pioavailshadow[6];
871 /* bitmap of send buffers available for the kernel to use with PIO. */
872 unsigned long pioavailkernel[6];
873 /* bitmap of send buffers which need to be disarmed. */
874 unsigned long pio_need_disarm[3];
875 /* bitmap of send buffers which are being written to. */
876 unsigned long pio_writing[3];
877 /* kr_revision shadow */
878 u64 revision;
879 /* Base GUID for device (from eeprom, network order) */
880 __be64 base_guid;
881
882 /*
883 * kr_sendpiobufbase value (chip offset of pio buffers), and the
884 * base of the 2KB buffer s(user processes only use 2K)
885 */
886 u64 piobufbase;
887 u32 pio2k_bufbase;
888
889 /* these are the "32 bit" regs */
890
891 /* number of GUIDs in the flash for this interface */
892 u32 nguid;
893 /*
894 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
895 * all expect bit fields to be "unsigned long"
896 */
897 unsigned long rcvctrl; /* shadow per device rcvctrl */
898 unsigned long sendctrl; /* shadow per device sendctrl */
899
900 /* value we put in kr_rcvhdrcnt */
901 u32 rcvhdrcnt;
902 /* value we put in kr_rcvhdrsize */
903 u32 rcvhdrsize;
904 /* value we put in kr_rcvhdrentsize */
905 u32 rcvhdrentsize;
906 /* kr_ctxtcnt value */
907 u32 ctxtcnt;
908 /* kr_pagealign value */
909 u32 palign;
910 /* number of "2KB" PIO buffers */
911 u32 piobcnt2k;
912 /* size in bytes of "2KB" PIO buffers */
913 u32 piosize2k;
914 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */
915 u32 piosize2kmax_dwords;
916 /* number of "4KB" PIO buffers */
917 u32 piobcnt4k;
918 /* size in bytes of "4KB" PIO buffers */
919 u32 piosize4k;
920 /* kr_rcvegrbase value */
921 u32 rcvegrbase;
922 /* kr_rcvtidbase value */
923 u32 rcvtidbase;
924 /* kr_rcvtidcnt value */
925 u32 rcvtidcnt;
926 /* kr_userregbase */
927 u32 uregbase;
928 /* shadow the control register contents */
929 u32 control;
930
931 /* chip address space used by 4k pio buffers */
932 u32 align4k;
933 /* size of each rcvegrbuffer */
934 u32 rcvegrbufsize;
935 /* localbus width (1, 2,4,8,16,32) from config space */
936 u32 lbus_width;
937 /* localbus speed in MHz */
938 u32 lbus_speed;
939 int unit; /* unit # of this chip */
940
941 /* start of CHIP_SPEC move to chipspec, but need code changes */
942 /* low and high portions of MSI capability/vector */
943 u32 msi_lo;
944 /* saved after PCIe init for restore after reset */
945 u32 msi_hi;
946 /* MSI data (vector) saved for restore */
947 u16 msi_data;
948 /* so we can rewrite it after a chip reset */
949 u32 pcibar0;
950 /* so we can rewrite it after a chip reset */
951 u32 pcibar1;
952 u64 rhdrhead_intr_off;
953
954 /*
955 * ASCII serial number, from flash, large enough for original
956 * all digit strings, and longer QLogic serial number format
957 */
958 u8 serial[16];
959 /* human readable board version */
960 u8 boardversion[96];
961 u8 lbus_info[32]; /* human readable localbus info */
962 /* chip major rev, from qib_revision */
963 u8 majrev;
964 /* chip minor rev, from qib_revision */
965 u8 minrev;
966
967 /* Misc small ints */
968 /* Number of physical ports available */
969 u8 num_pports;
970 /* Lowest context number which can be used by user processes */
971 u8 first_user_ctxt;
972 u8 n_krcv_queues;
973 u8 qpn_mask;
974 u8 skip_kctxt_mask;
975
976 u16 rhf_offset; /* offset of RHF within receive header entry */
977
978 /*
979 * GPIO pins for twsi-connected devices, and device code for eeprom
980 */
981 u8 gpio_sda_num;
982 u8 gpio_scl_num;
983 u8 twsi_eeprom_dev;
984 u8 board_atten;
985
986 /* Support (including locks) for EEPROM logging of errors and time */
987 /* control access to actual counters, timer */
988 spinlock_t eep_st_lock;
989 /* control high-level access to EEPROM */
990 struct mutex eep_lock;
991 uint64_t traffic_wds;
992 /* active time is kept in seconds, but logged in hours */
993 atomic_t active_time;
994 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
995 uint8_t eep_st_errs[QIB_EEP_LOG_CNT];
996 uint8_t eep_st_new_errs[QIB_EEP_LOG_CNT];
997 uint16_t eep_hrs;
998 /*
999 * masks for which bits of errs, hwerrs that cause
1000 * each of the counters to increment.
1001 */
1002 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1003 struct qib_diag_client *diag_client;
1004 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */
1005 struct diag_observer_list_elt *diag_observer_list;
1006
1007 u8 psxmitwait_supported;
1008 /* cycle length of PS* counters in HW (in picoseconds) */
1009 u16 psxmitwait_check_rate;
1010};
1011
1012/* hol_state values */
1013#define QIB_HOL_UP 0
1014#define QIB_HOL_INIT 1
1015
1016#define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1017#define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1018#define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)
1019#define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
1020#define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)
1021
1022/* operation types for f_txchk_change() */
1023#define TXCHK_CHG_TYPE_DIS1 3
1024#define TXCHK_CHG_TYPE_ENAB1 2
1025#define TXCHK_CHG_TYPE_KERN 1
1026#define TXCHK_CHG_TYPE_USER 0
1027
1028#define QIB_CHASE_TIME msecs_to_jiffies(145)
1029#define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1030
1031/* Private data for file operations */
1032struct qib_filedata {
1033 struct qib_ctxtdata *rcd;
1034 unsigned subctxt;
1035 unsigned tidcursor;
1036 struct qib_user_sdma_queue *pq;
1037 int rec_cpu_num; /* for cpu affinity; -1 if none */
1038};
1039
1040extern struct list_head qib_dev_list;
1041extern spinlock_t qib_devs_lock;
1042extern struct qib_devdata *qib_lookup(int unit);
1043extern u32 qib_cpulist_count;
1044extern unsigned long *qib_cpulist;
1045
1046extern unsigned qib_wc_pat;
1047int qib_init(struct qib_devdata *, int);
1048int init_chip_wc_pat(struct qib_devdata *dd, u32);
1049int qib_enable_wc(struct qib_devdata *dd);
1050void qib_disable_wc(struct qib_devdata *dd);
1051int qib_count_units(int *npresentp, int *nupp);
1052int qib_count_active_units(void);
1053
1054int qib_cdev_init(int minor, const char *name,
1055 const struct file_operations *fops,
1056 struct cdev **cdevp, struct device **devp);
1057void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1058int qib_dev_init(void);
1059void qib_dev_cleanup(void);
1060
1061int qib_diag_add(struct qib_devdata *);
1062void qib_diag_remove(struct qib_devdata *);
1063void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1064void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */
1065
1066int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1067void qib_bad_intrstatus(struct qib_devdata *);
1068void qib_handle_urcv(struct qib_devdata *, u64);
1069
1070/* clean up any per-chip chip-specific stuff */
1071void qib_chip_cleanup(struct qib_devdata *);
1072/* clean up any chip type-specific stuff */
1073void qib_chip_done(void);
1074
1075/* check to see if we have to force ordering for write combining */
1076int qib_unordered_wc(void);
1077void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1078
1079void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1080int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1081void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1082void qib_cancel_sends(struct qib_pportdata *);
1083
1084int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1085int qib_setup_eagerbufs(struct qib_ctxtdata *);
1086void qib_set_ctxtcnt(struct qib_devdata *);
1087int qib_create_ctxts(struct qib_devdata *dd);
1088struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32);
1089void qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1090void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1091
1092u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1093int qib_reset_device(int);
1094int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1095int qib_set_linkstate(struct qib_pportdata *, u8);
1096int qib_set_mtu(struct qib_pportdata *, u16);
1097int qib_set_lid(struct qib_pportdata *, u32, u8);
1098void qib_hol_down(struct qib_pportdata *);
1099void qib_hol_init(struct qib_pportdata *);
1100void qib_hol_up(struct qib_pportdata *);
1101void qib_hol_event(unsigned long);
1102void qib_disable_after_error(struct qib_devdata *);
1103int qib_set_uevent_bits(struct qib_pportdata *, const int);
1104
1105/* for use in system calls, where we want to know device type, etc. */
1106#define ctxt_fp(fp) \
1107 (((struct qib_filedata *)(fp)->private_data)->rcd)
1108#define subctxt_fp(fp) \
1109 (((struct qib_filedata *)(fp)->private_data)->subctxt)
1110#define tidcursor_fp(fp) \
1111 (((struct qib_filedata *)(fp)->private_data)->tidcursor)
1112#define user_sdma_queue_fp(fp) \
1113 (((struct qib_filedata *)(fp)->private_data)->pq)
1114
1115static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1116{
1117 return ppd->dd;
1118}
1119
1120static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1121{
1122 return container_of(dev, struct qib_devdata, verbs_dev);
1123}
1124
1125static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1126{
1127 return dd_from_dev(to_idev(ibdev));
1128}
1129
1130static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1131{
1132 return container_of(ibp, struct qib_pportdata, ibport_data);
1133}
1134
1135static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port)
1136{
1137 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1138 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1139
1140 WARN_ON(pidx >= dd->num_pports);
1141 return &dd->pport[pidx].ibport_data;
1142}
1143
1144/*
1145 * values for dd->flags (_device_ related flags) and
1146 */
1147#define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */
1148#define QIB_INITTED 0x2 /* chip and driver up and initted */
1149#define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */
1150#define QIB_PRESENT 0x8 /* chip accesses can be done */
1151#define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */
1152#define QIB_HAS_THRESH_UPDATE 0x40
1153#define QIB_HAS_SDMA_TIMEOUT 0x80
1154#define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */
1155#define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */
1156#define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */
1157#define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */
1158#define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */
1159#define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */
1160#define QIB_BADINTR 0x8000 /* severe interrupt problems */
1161#define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */
1162#define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */
1163
1164/*
1165 * values for ppd->lflags (_ib_port_ related flags)
1166 */
1167#define QIBL_LINKV 0x1 /* IB link state valid */
1168#define QIBL_LINKDOWN 0x8 /* IB link is down */
1169#define QIBL_LINKINIT 0x10 /* IB link level is up */
1170#define QIBL_LINKARMED 0x20 /* IB link is ARMED */
1171#define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */
1172/* leave a gap for more IB-link state */
1173#define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */
1174#define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */
1175#define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced,
1176 * Do not try to bring up */
1177#define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */
1178
1179/* IB dword length mask in PBC (lower 11 bits); same for all chips */
1180#define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)
1181
1182
1183/* ctxt_flag bit offsets */
1184 /* waiting for a packet to arrive */
1185#define QIB_CTXT_WAITING_RCV 2
1186 /* master has not finished initializing */
1187#define QIB_CTXT_MASTER_UNINIT 4
1188 /* waiting for an urgent packet to arrive */
1189#define QIB_CTXT_WAITING_URG 5
1190
1191/* free up any allocated data at closes */
1192void qib_free_data(struct qib_ctxtdata *dd);
1193void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1194 u32, struct qib_ctxtdata *);
1195struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1196 const struct pci_device_id *);
1197struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1198 const struct pci_device_id *);
1199struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1200 const struct pci_device_id *);
1201void qib_free_devdata(struct qib_devdata *);
1202struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1203
1204#define QIB_TWSI_NO_DEV 0xFF
1205/* Below qib_twsi_ functions must be called with eep_lock held */
1206int qib_twsi_reset(struct qib_devdata *dd);
1207int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1208 int len);
1209int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1210 const void *buffer, int len);
1211void qib_get_eeprom_info(struct qib_devdata *);
1212int qib_update_eeprom_log(struct qib_devdata *dd);
1213void qib_inc_eeprom_err(struct qib_devdata *dd, u32 eidx, u32 incr);
1214void qib_dump_lookup_output_queue(struct qib_devdata *);
1215void qib_force_pio_avail_update(struct qib_devdata *);
1216void qib_clear_symerror_on_linkup(unsigned long opaque);
1217
1218/*
1219 * Set LED override, only the two LSBs have "public" meaning, but
1220 * any non-zero value substitutes them for the Link and LinkTrain
1221 * LED states.
1222 */
1223#define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
1224#define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */
1225void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1226
1227/* send dma routines */
1228int qib_setup_sdma(struct qib_pportdata *);
1229void qib_teardown_sdma(struct qib_pportdata *);
1230void __qib_sdma_intr(struct qib_pportdata *);
1231void qib_sdma_intr(struct qib_pportdata *);
1232int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *,
1233 u32, struct qib_verbs_txreq *);
1234/* ppd->sdma_lock should be locked before calling this. */
1235int qib_sdma_make_progress(struct qib_pportdata *dd);
1236
1237/* must be called under qib_sdma_lock */
1238static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1239{
1240 return ppd->sdma_descq_cnt -
1241 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1242}
1243
1244static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1245{
1246 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1247}
1248int qib_sdma_running(struct qib_pportdata *);
1249
1250void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1251void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1252
1253/*
1254 * number of words used for protocol header if not set by qib_userinit();
1255 */
1256#define QIB_DFLT_RCVHDRSIZE 9
1257
1258/*
1259 * We need to be able to handle an IB header of at least 24 dwords.
1260 * We need the rcvhdrq large enough to handle largest IB header, but
1261 * still have room for a 2KB MTU standard IB packet.
1262 * Additionally, some processor/memory controller combinations
1263 * benefit quite strongly from having the DMA'ed data be cacheline
1264 * aligned and a cacheline multiple, so we set the size to 32 dwords
1265 * (2 64-byte primary cachelines for pretty much all processors of
1266 * interest). The alignment hurts nothing, other than using somewhat
1267 * more memory.
1268 */
1269#define QIB_RCVHDR_ENTSIZE 32
1270
1271int qib_get_user_pages(unsigned long, size_t, struct page **);
1272void qib_release_user_pages(struct page **, size_t);
1273int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1274int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1275u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1276void qib_sendbuf_done(struct qib_devdata *, unsigned);
1277
1278static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1279{
1280 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1281}
1282
1283static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1284{
1285 /*
1286 * volatile because it's a DMA target from the chip, routine is
1287 * inlined, and don't want register caching or reordering.
1288 */
1289 return (u32) le64_to_cpu(
1290 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */
1291}
1292
1293static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd)
1294{
1295 const struct qib_devdata *dd = rcd->dd;
1296 u32 hdrqtail;
1297
1298 if (dd->flags & QIB_NODMA_RTAIL) {
1299 __le32 *rhf_addr;
1300 u32 seq;
1301
1302 rhf_addr = (__le32 *) rcd->rcvhdrq +
1303 rcd->head + dd->rhf_offset;
1304 seq = qib_hdrget_seq(rhf_addr);
1305 hdrqtail = rcd->head;
1306 if (seq == rcd->seq_cnt)
1307 hdrqtail++;
1308 } else
1309 hdrqtail = qib_get_rcvhdrtail(rcd);
1310
1311 return hdrqtail;
1312}
1313
1314/*
1315 * sysfs interface.
1316 */
1317
1318extern const char ib_qib_version[];
1319
1320int qib_device_create(struct qib_devdata *);
1321void qib_device_remove(struct qib_devdata *);
1322
1323int qib_create_port_files(struct ib_device *ibdev, u8 port_num,
1324 struct kobject *kobj);
1325int qib_verbs_register_sysfs(struct qib_devdata *);
1326void qib_verbs_unregister_sysfs(struct qib_devdata *);
1327/* Hook for sysfs read of QSFP */
1328extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1329
1330int __init qib_init_qibfs(void);
1331int __exit qib_exit_qibfs(void);
1332
1333int qibfs_add(struct qib_devdata *);
1334int qibfs_remove(struct qib_devdata *);
1335
1336int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1337int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1338 const struct pci_device_id *);
1339void qib_pcie_ddcleanup(struct qib_devdata *);
1340int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct msix_entry *);
1341int qib_reinit_intr(struct qib_devdata *);
1342void qib_enable_intx(struct pci_dev *);
1343void qib_nomsi(struct qib_devdata *);
1344void qib_nomsix(struct qib_devdata *);
1345void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1346void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1347
1348/*
1349 * dma_addr wrappers - all 0's invalid for hw
1350 */
1351dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
1352 size_t, int);
1353const char *qib_get_unit_name(int unit);
1354
1355/*
1356 * Flush write combining store buffers (if present) and perform a write
1357 * barrier.
1358 */
1359#if defined(CONFIG_X86_64)
1360#define qib_flush_wc() asm volatile("sfence" : : : "memory")
1361#else
1362#define qib_flush_wc() wmb() /* no reorder around wc flush */
1363#endif
1364
1365/* global module parameter variables */
1366extern unsigned qib_ibmtu;
1367extern ushort qib_cfgctxts;
1368extern ushort qib_num_cfg_vls;
1369extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */
1370extern unsigned qib_n_krcv_queues;
1371extern unsigned qib_sdma_fetch_arb;
1372extern unsigned qib_compat_ddr_negotiate;
1373extern int qib_special_trigger;
1374
1375extern struct mutex qib_mutex;
1376
1377/* Number of seconds before our card status check... */
1378#define STATUS_TIMEOUT 60
1379
1380#define QIB_DRV_NAME "ib_qib"
1381#define QIB_USER_MINOR_BASE 0
1382#define QIB_TRACE_MINOR 127
1383#define QIB_DIAGPKT_MINOR 128
1384#define QIB_DIAG_MINOR_BASE 129
1385#define QIB_NMINORS 255
1386
1387#define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1388#define PCI_VENDOR_ID_QLOGIC 0x1077
1389#define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1390#define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1391#define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1392
1393/*
1394 * qib_early_err is used (only!) to print early errors before devdata is
1395 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1396 * cleanup when devdata may have been freed, etc. qib_dev_porterr is
1397 * the same as qib_dev_err, but is used when the message really needs
1398 * the IB port# to be definitive as to what's happening..
1399 * All of these go to the trace log, and the trace log entry is done
1400 * first to avoid possible serial port delays from printk.
1401 */
1402#define qib_early_err(dev, fmt, ...) \
1403 do { \
1404 dev_info(dev, KERN_ERR QIB_DRV_NAME ": " fmt, ##__VA_ARGS__); \
1405 } while (0)
1406
1407#define qib_dev_err(dd, fmt, ...) \
1408 do { \
1409 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1410 qib_get_unit_name((dd)->unit), ##__VA_ARGS__); \
1411 } while (0)
1412
1413#define qib_dev_porterr(dd, port, fmt, ...) \
1414 do { \
1415 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1416 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \
1417 ##__VA_ARGS__); \
1418 } while (0)
1419
1420#define qib_devinfo(pcidev, fmt, ...) \
1421 do { \
1422 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__); \
1423 } while (0)
1424
1425/*
1426 * this is used for formatting hw error messages...
1427 */
1428struct qib_hwerror_msgs {
1429 u64 mask;
1430 const char *msg;
1431};
1432
1433#define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1434
1435/* in qib_intr.c... */
1436void qib_format_hwerrors(u64 hwerrs,
1437 const struct qib_hwerror_msgs *hwerrmsgs,
1438 size_t nhwerrmsgs, char *msg, size_t lmsg);
1439#endif /* _QIB_KERNEL_H */
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