diff options
Diffstat (limited to 'drivers/infiniband/hw/mthca/mthca_qp.c')
-rw-r--r-- | drivers/infiniband/hw/mthca/mthca_qp.c | 362 |
1 files changed, 105 insertions, 257 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c index f7126b14d5ae..0164b84d4ec6 100644 --- a/drivers/infiniband/hw/mthca/mthca_qp.c +++ b/drivers/infiniband/hw/mthca/mthca_qp.c | |||
@@ -1,6 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2004 Topspin Communications. All rights reserved. | 2 | * Copyright (c) 2004 Topspin Communications. All rights reserved. |
3 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | 3 | * Copyright (c) 2005 Cisco Systems. All rights reserved. |
4 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. | ||
5 | * Copyright (c) 2004 Voltaire, Inc. All rights reserved. | ||
4 | * | 6 | * |
5 | * This software is available to you under a choice of one of two | 7 | * This software is available to you under a choice of one of two |
6 | * licenses. You may choose to be licensed under the terms of the GNU | 8 | * licenses. You may choose to be licensed under the terms of the GNU |
@@ -35,13 +37,14 @@ | |||
35 | 37 | ||
36 | #include <linux/init.h> | 38 | #include <linux/init.h> |
37 | 39 | ||
38 | #include <ib_verbs.h> | 40 | #include <rdma/ib_verbs.h> |
39 | #include <ib_cache.h> | 41 | #include <rdma/ib_cache.h> |
40 | #include <ib_pack.h> | 42 | #include <rdma/ib_pack.h> |
41 | 43 | ||
42 | #include "mthca_dev.h" | 44 | #include "mthca_dev.h" |
43 | #include "mthca_cmd.h" | 45 | #include "mthca_cmd.h" |
44 | #include "mthca_memfree.h" | 46 | #include "mthca_memfree.h" |
47 | #include "mthca_wqe.h" | ||
45 | 48 | ||
46 | enum { | 49 | enum { |
47 | MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE, | 50 | MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE, |
@@ -95,62 +98,62 @@ enum { | |||
95 | }; | 98 | }; |
96 | 99 | ||
97 | struct mthca_qp_path { | 100 | struct mthca_qp_path { |
98 | u32 port_pkey; | 101 | __be32 port_pkey; |
99 | u8 rnr_retry; | 102 | u8 rnr_retry; |
100 | u8 g_mylmc; | 103 | u8 g_mylmc; |
101 | u16 rlid; | 104 | __be16 rlid; |
102 | u8 ackto; | 105 | u8 ackto; |
103 | u8 mgid_index; | 106 | u8 mgid_index; |
104 | u8 static_rate; | 107 | u8 static_rate; |
105 | u8 hop_limit; | 108 | u8 hop_limit; |
106 | u32 sl_tclass_flowlabel; | 109 | __be32 sl_tclass_flowlabel; |
107 | u8 rgid[16]; | 110 | u8 rgid[16]; |
108 | } __attribute__((packed)); | 111 | } __attribute__((packed)); |
109 | 112 | ||
110 | struct mthca_qp_context { | 113 | struct mthca_qp_context { |
111 | u32 flags; | 114 | __be32 flags; |
112 | u32 tavor_sched_queue; /* Reserved on Arbel */ | 115 | __be32 tavor_sched_queue; /* Reserved on Arbel */ |
113 | u8 mtu_msgmax; | 116 | u8 mtu_msgmax; |
114 | u8 rq_size_stride; /* Reserved on Tavor */ | 117 | u8 rq_size_stride; /* Reserved on Tavor */ |
115 | u8 sq_size_stride; /* Reserved on Tavor */ | 118 | u8 sq_size_stride; /* Reserved on Tavor */ |
116 | u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */ | 119 | u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */ |
117 | u32 usr_page; | 120 | __be32 usr_page; |
118 | u32 local_qpn; | 121 | __be32 local_qpn; |
119 | u32 remote_qpn; | 122 | __be32 remote_qpn; |
120 | u32 reserved1[2]; | 123 | u32 reserved1[2]; |
121 | struct mthca_qp_path pri_path; | 124 | struct mthca_qp_path pri_path; |
122 | struct mthca_qp_path alt_path; | 125 | struct mthca_qp_path alt_path; |
123 | u32 rdd; | 126 | __be32 rdd; |
124 | u32 pd; | 127 | __be32 pd; |
125 | u32 wqe_base; | 128 | __be32 wqe_base; |
126 | u32 wqe_lkey; | 129 | __be32 wqe_lkey; |
127 | u32 params1; | 130 | __be32 params1; |
128 | u32 reserved2; | 131 | __be32 reserved2; |
129 | u32 next_send_psn; | 132 | __be32 next_send_psn; |
130 | u32 cqn_snd; | 133 | __be32 cqn_snd; |
131 | u32 snd_wqe_base_l; /* Next send WQE on Tavor */ | 134 | __be32 snd_wqe_base_l; /* Next send WQE on Tavor */ |
132 | u32 snd_db_index; /* (debugging only entries) */ | 135 | __be32 snd_db_index; /* (debugging only entries) */ |
133 | u32 last_acked_psn; | 136 | __be32 last_acked_psn; |
134 | u32 ssn; | 137 | __be32 ssn; |
135 | u32 params2; | 138 | __be32 params2; |
136 | u32 rnr_nextrecvpsn; | 139 | __be32 rnr_nextrecvpsn; |
137 | u32 ra_buff_indx; | 140 | __be32 ra_buff_indx; |
138 | u32 cqn_rcv; | 141 | __be32 cqn_rcv; |
139 | u32 rcv_wqe_base_l; /* Next recv WQE on Tavor */ | 142 | __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */ |
140 | u32 rcv_db_index; /* (debugging only entries) */ | 143 | __be32 rcv_db_index; /* (debugging only entries) */ |
141 | u32 qkey; | 144 | __be32 qkey; |
142 | u32 srqn; | 145 | __be32 srqn; |
143 | u32 rmsn; | 146 | __be32 rmsn; |
144 | u16 rq_wqe_counter; /* reserved on Tavor */ | 147 | __be16 rq_wqe_counter; /* reserved on Tavor */ |
145 | u16 sq_wqe_counter; /* reserved on Tavor */ | 148 | __be16 sq_wqe_counter; /* reserved on Tavor */ |
146 | u32 reserved3[18]; | 149 | u32 reserved3[18]; |
147 | } __attribute__((packed)); | 150 | } __attribute__((packed)); |
148 | 151 | ||
149 | struct mthca_qp_param { | 152 | struct mthca_qp_param { |
150 | u32 opt_param_mask; | 153 | __be32 opt_param_mask; |
151 | u32 reserved1; | 154 | u32 reserved1; |
152 | struct mthca_qp_context context; | 155 | struct mthca_qp_context context; |
153 | u32 reserved2[62]; | 156 | u32 reserved2[62]; |
154 | } __attribute__((packed)); | 157 | } __attribute__((packed)); |
155 | 158 | ||
156 | enum { | 159 | enum { |
@@ -173,80 +176,6 @@ enum { | |||
173 | MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16 | 176 | MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16 |
174 | }; | 177 | }; |
175 | 178 | ||
176 | enum { | ||
177 | MTHCA_NEXT_DBD = 1 << 7, | ||
178 | MTHCA_NEXT_FENCE = 1 << 6, | ||
179 | MTHCA_NEXT_CQ_UPDATE = 1 << 3, | ||
180 | MTHCA_NEXT_EVENT_GEN = 1 << 2, | ||
181 | MTHCA_NEXT_SOLICIT = 1 << 1, | ||
182 | |||
183 | MTHCA_MLX_VL15 = 1 << 17, | ||
184 | MTHCA_MLX_SLR = 1 << 16 | ||
185 | }; | ||
186 | |||
187 | enum { | ||
188 | MTHCA_INVAL_LKEY = 0x100 | ||
189 | }; | ||
190 | |||
191 | struct mthca_next_seg { | ||
192 | u32 nda_op; /* [31:6] next WQE [4:0] next opcode */ | ||
193 | u32 ee_nds; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */ | ||
194 | u32 flags; /* [3] CQ [2] Event [1] Solicit */ | ||
195 | u32 imm; /* immediate data */ | ||
196 | }; | ||
197 | |||
198 | struct mthca_tavor_ud_seg { | ||
199 | u32 reserved1; | ||
200 | u32 lkey; | ||
201 | u64 av_addr; | ||
202 | u32 reserved2[4]; | ||
203 | u32 dqpn; | ||
204 | u32 qkey; | ||
205 | u32 reserved3[2]; | ||
206 | }; | ||
207 | |||
208 | struct mthca_arbel_ud_seg { | ||
209 | u32 av[8]; | ||
210 | u32 dqpn; | ||
211 | u32 qkey; | ||
212 | u32 reserved[2]; | ||
213 | }; | ||
214 | |||
215 | struct mthca_bind_seg { | ||
216 | u32 flags; /* [31] Atomic [30] rem write [29] rem read */ | ||
217 | u32 reserved; | ||
218 | u32 new_rkey; | ||
219 | u32 lkey; | ||
220 | u64 addr; | ||
221 | u64 length; | ||
222 | }; | ||
223 | |||
224 | struct mthca_raddr_seg { | ||
225 | u64 raddr; | ||
226 | u32 rkey; | ||
227 | u32 reserved; | ||
228 | }; | ||
229 | |||
230 | struct mthca_atomic_seg { | ||
231 | u64 swap_add; | ||
232 | u64 compare; | ||
233 | }; | ||
234 | |||
235 | struct mthca_data_seg { | ||
236 | u32 byte_count; | ||
237 | u32 lkey; | ||
238 | u64 addr; | ||
239 | }; | ||
240 | |||
241 | struct mthca_mlx_seg { | ||
242 | u32 nda_op; | ||
243 | u32 nds; | ||
244 | u32 flags; /* [17] VL15 [16] SLR [14:12] static rate | ||
245 | [11:8] SL [3] C [2] E */ | ||
246 | u16 rlid; | ||
247 | u16 vcrc; | ||
248 | }; | ||
249 | |||
250 | static const u8 mthca_opcode[] = { | 179 | static const u8 mthca_opcode[] = { |
251 | [IB_WR_SEND] = MTHCA_OPCODE_SEND, | 180 | [IB_WR_SEND] = MTHCA_OPCODE_SEND, |
252 | [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM, | 181 | [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM, |
@@ -573,12 +502,11 @@ static void init_port(struct mthca_dev *dev, int port) | |||
573 | 502 | ||
574 | memset(¶m, 0, sizeof param); | 503 | memset(¶m, 0, sizeof param); |
575 | 504 | ||
576 | param.enable_1x = 1; | 505 | param.port_width = dev->limits.port_width_cap; |
577 | param.enable_4x = 1; | 506 | param.vl_cap = dev->limits.vl_cap; |
578 | param.vl_cap = dev->limits.vl_cap; | 507 | param.mtu_cap = dev->limits.mtu_cap; |
579 | param.mtu_cap = dev->limits.mtu_cap; | 508 | param.gid_cap = dev->limits.gid_table_len; |
580 | param.gid_cap = dev->limits.gid_table_len; | 509 | param.pkey_cap = dev->limits.pkey_table_len; |
581 | param.pkey_cap = dev->limits.pkey_table_len; | ||
582 | 510 | ||
583 | err = mthca_INIT_IB(dev, ¶m, port, &status); | 511 | err = mthca_INIT_IB(dev, ¶m, port, &status); |
584 | if (err) | 512 | if (err) |
@@ -684,10 +612,13 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask) | |||
684 | qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31; | 612 | qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31; |
685 | 613 | ||
686 | if (mthca_is_memfree(dev)) { | 614 | if (mthca_is_memfree(dev)) { |
687 | qp_context->rq_size_stride = | 615 | if (qp->rq.max) |
688 | ((ffs(qp->rq.max) - 1) << 3) | (qp->rq.wqe_shift - 4); | 616 | qp_context->rq_size_stride = long_log2(qp->rq.max) << 3; |
689 | qp_context->sq_size_stride = | 617 | qp_context->rq_size_stride |= qp->rq.wqe_shift - 4; |
690 | ((ffs(qp->sq.max) - 1) << 3) | (qp->sq.wqe_shift - 4); | 618 | |
619 | if (qp->sq.max) | ||
620 | qp_context->sq_size_stride = long_log2(qp->sq.max) << 3; | ||
621 | qp_context->sq_size_stride |= qp->sq.wqe_shift - 4; | ||
691 | } | 622 | } |
692 | 623 | ||
693 | /* leave arbel_sched_queue as 0 */ | 624 | /* leave arbel_sched_queue as 0 */ |
@@ -856,6 +787,9 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask) | |||
856 | 787 | ||
857 | qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC); | 788 | qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC); |
858 | 789 | ||
790 | if (ibqp->srq) | ||
791 | qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC); | ||
792 | |||
859 | if (attr_mask & IB_QP_MIN_RNR_TIMER) { | 793 | if (attr_mask & IB_QP_MIN_RNR_TIMER) { |
860 | qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); | 794 | qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); |
861 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT); | 795 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT); |
@@ -878,6 +812,10 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask) | |||
878 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY); | 812 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY); |
879 | } | 813 | } |
880 | 814 | ||
815 | if (ibqp->srq) | ||
816 | qp_context->srqn = cpu_to_be32(1 << 24 | | ||
817 | to_msrq(ibqp->srq)->srqn); | ||
818 | |||
881 | err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans, | 819 | err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans, |
882 | qp->qpn, 0, mailbox, 0, &status); | 820 | qp->qpn, 0, mailbox, 0, &status); |
883 | if (status) { | 821 | if (status) { |
@@ -925,10 +863,6 @@ static int mthca_alloc_wqe_buf(struct mthca_dev *dev, | |||
925 | struct mthca_qp *qp) | 863 | struct mthca_qp *qp) |
926 | { | 864 | { |
927 | int size; | 865 | int size; |
928 | int i; | ||
929 | int npages, shift; | ||
930 | dma_addr_t t; | ||
931 | u64 *dma_list = NULL; | ||
932 | int err = -ENOMEM; | 866 | int err = -ENOMEM; |
933 | 867 | ||
934 | size = sizeof (struct mthca_next_seg) + | 868 | size = sizeof (struct mthca_next_seg) + |
@@ -978,116 +912,24 @@ static int mthca_alloc_wqe_buf(struct mthca_dev *dev, | |||
978 | if (!qp->wrid) | 912 | if (!qp->wrid) |
979 | goto err_out; | 913 | goto err_out; |
980 | 914 | ||
981 | if (size <= MTHCA_MAX_DIRECT_QP_SIZE) { | 915 | err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE, |
982 | qp->is_direct = 1; | 916 | &qp->queue, &qp->is_direct, pd, 0, &qp->mr); |
983 | npages = 1; | ||
984 | shift = get_order(size) + PAGE_SHIFT; | ||
985 | |||
986 | if (0) | ||
987 | mthca_dbg(dev, "Creating direct QP of size %d (shift %d)\n", | ||
988 | size, shift); | ||
989 | |||
990 | qp->queue.direct.buf = dma_alloc_coherent(&dev->pdev->dev, size, | ||
991 | &t, GFP_KERNEL); | ||
992 | if (!qp->queue.direct.buf) | ||
993 | goto err_out; | ||
994 | |||
995 | pci_unmap_addr_set(&qp->queue.direct, mapping, t); | ||
996 | |||
997 | memset(qp->queue.direct.buf, 0, size); | ||
998 | |||
999 | while (t & ((1 << shift) - 1)) { | ||
1000 | --shift; | ||
1001 | npages *= 2; | ||
1002 | } | ||
1003 | |||
1004 | dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); | ||
1005 | if (!dma_list) | ||
1006 | goto err_out_free; | ||
1007 | |||
1008 | for (i = 0; i < npages; ++i) | ||
1009 | dma_list[i] = t + i * (1 << shift); | ||
1010 | } else { | ||
1011 | qp->is_direct = 0; | ||
1012 | npages = size / PAGE_SIZE; | ||
1013 | shift = PAGE_SHIFT; | ||
1014 | |||
1015 | if (0) | ||
1016 | mthca_dbg(dev, "Creating indirect QP with %d pages\n", npages); | ||
1017 | |||
1018 | dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); | ||
1019 | if (!dma_list) | ||
1020 | goto err_out; | ||
1021 | |||
1022 | qp->queue.page_list = kmalloc(npages * | ||
1023 | sizeof *qp->queue.page_list, | ||
1024 | GFP_KERNEL); | ||
1025 | if (!qp->queue.page_list) | ||
1026 | goto err_out; | ||
1027 | |||
1028 | for (i = 0; i < npages; ++i) { | ||
1029 | qp->queue.page_list[i].buf = | ||
1030 | dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE, | ||
1031 | &t, GFP_KERNEL); | ||
1032 | if (!qp->queue.page_list[i].buf) | ||
1033 | goto err_out_free; | ||
1034 | |||
1035 | memset(qp->queue.page_list[i].buf, 0, PAGE_SIZE); | ||
1036 | |||
1037 | pci_unmap_addr_set(&qp->queue.page_list[i], mapping, t); | ||
1038 | dma_list[i] = t; | ||
1039 | } | ||
1040 | } | ||
1041 | |||
1042 | err = mthca_mr_alloc_phys(dev, pd->pd_num, dma_list, shift, | ||
1043 | npages, 0, size, | ||
1044 | MTHCA_MPT_FLAG_LOCAL_READ, | ||
1045 | &qp->mr); | ||
1046 | if (err) | 917 | if (err) |
1047 | goto err_out_free; | 918 | goto err_out; |
1048 | 919 | ||
1049 | kfree(dma_list); | ||
1050 | return 0; | 920 | return 0; |
1051 | 921 | ||
1052 | err_out_free: | 922 | err_out: |
1053 | if (qp->is_direct) { | ||
1054 | dma_free_coherent(&dev->pdev->dev, size, qp->queue.direct.buf, | ||
1055 | pci_unmap_addr(&qp->queue.direct, mapping)); | ||
1056 | } else | ||
1057 | for (i = 0; i < npages; ++i) { | ||
1058 | if (qp->queue.page_list[i].buf) | ||
1059 | dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, | ||
1060 | qp->queue.page_list[i].buf, | ||
1061 | pci_unmap_addr(&qp->queue.page_list[i], | ||
1062 | mapping)); | ||
1063 | |||
1064 | } | ||
1065 | |||
1066 | err_out: | ||
1067 | kfree(qp->wrid); | 923 | kfree(qp->wrid); |
1068 | kfree(dma_list); | ||
1069 | return err; | 924 | return err; |
1070 | } | 925 | } |
1071 | 926 | ||
1072 | static void mthca_free_wqe_buf(struct mthca_dev *dev, | 927 | static void mthca_free_wqe_buf(struct mthca_dev *dev, |
1073 | struct mthca_qp *qp) | 928 | struct mthca_qp *qp) |
1074 | { | 929 | { |
1075 | int i; | 930 | mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset + |
1076 | int size = PAGE_ALIGN(qp->send_wqe_offset + | 931 | (qp->sq.max << qp->sq.wqe_shift)), |
1077 | (qp->sq.max << qp->sq.wqe_shift)); | 932 | &qp->queue, qp->is_direct, &qp->mr); |
1078 | |||
1079 | if (qp->is_direct) { | ||
1080 | dma_free_coherent(&dev->pdev->dev, size, qp->queue.direct.buf, | ||
1081 | pci_unmap_addr(&qp->queue.direct, mapping)); | ||
1082 | } else { | ||
1083 | for (i = 0; i < size / PAGE_SIZE; ++i) { | ||
1084 | dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, | ||
1085 | qp->queue.page_list[i].buf, | ||
1086 | pci_unmap_addr(&qp->queue.page_list[i], | ||
1087 | mapping)); | ||
1088 | } | ||
1089 | } | ||
1090 | |||
1091 | kfree(qp->wrid); | 933 | kfree(qp->wrid); |
1092 | } | 934 | } |
1093 | 935 | ||
@@ -1428,11 +1270,12 @@ void mthca_free_qp(struct mthca_dev *dev, | |||
1428 | * unref the mem-free tables and free the QPN in our table. | 1270 | * unref the mem-free tables and free the QPN in our table. |
1429 | */ | 1271 | */ |
1430 | if (!qp->ibqp.uobject) { | 1272 | if (!qp->ibqp.uobject) { |
1431 | mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn); | 1273 | mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn, |
1274 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); | ||
1432 | if (qp->ibqp.send_cq != qp->ibqp.recv_cq) | 1275 | if (qp->ibqp.send_cq != qp->ibqp.recv_cq) |
1433 | mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn); | 1276 | mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn, |
1277 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); | ||
1434 | 1278 | ||
1435 | mthca_free_mr(dev, &qp->mr); | ||
1436 | mthca_free_memfree(dev, qp); | 1279 | mthca_free_memfree(dev, qp); |
1437 | mthca_free_wqe_buf(dev, qp); | 1280 | mthca_free_wqe_buf(dev, qp); |
1438 | } | 1281 | } |
@@ -1457,6 +1300,7 @@ static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp, | |||
1457 | { | 1300 | { |
1458 | int header_size; | 1301 | int header_size; |
1459 | int err; | 1302 | int err; |
1303 | u16 pkey; | ||
1460 | 1304 | ||
1461 | ib_ud_header_init(256, /* assume a MAD */ | 1305 | ib_ud_header_init(256, /* assume a MAD */ |
1462 | sqp->ud_header.grh_present, | 1306 | sqp->ud_header.grh_present, |
@@ -1467,8 +1311,8 @@ static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp, | |||
1467 | return err; | 1311 | return err; |
1468 | mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1); | 1312 | mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1); |
1469 | mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) | | 1313 | mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) | |
1470 | (sqp->ud_header.lrh.destination_lid == 0xffff ? | 1314 | (sqp->ud_header.lrh.destination_lid == |
1471 | MTHCA_MLX_SLR : 0) | | 1315 | IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) | |
1472 | (sqp->ud_header.lrh.service_level << 8)); | 1316 | (sqp->ud_header.lrh.service_level << 8)); |
1473 | mlx->rlid = sqp->ud_header.lrh.destination_lid; | 1317 | mlx->rlid = sqp->ud_header.lrh.destination_lid; |
1474 | mlx->vcrc = 0; | 1318 | mlx->vcrc = 0; |
@@ -1488,18 +1332,16 @@ static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp, | |||
1488 | } | 1332 | } |
1489 | 1333 | ||
1490 | sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; | 1334 | sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; |
1491 | if (sqp->ud_header.lrh.destination_lid == 0xffff) | 1335 | if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) |
1492 | sqp->ud_header.lrh.source_lid = 0xffff; | 1336 | sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; |
1493 | sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); | 1337 | sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); |
1494 | if (!sqp->qp.ibqp.qp_num) | 1338 | if (!sqp->qp.ibqp.qp_num) |
1495 | ib_get_cached_pkey(&dev->ib_dev, sqp->port, | 1339 | ib_get_cached_pkey(&dev->ib_dev, sqp->port, |
1496 | sqp->pkey_index, | 1340 | sqp->pkey_index, &pkey); |
1497 | &sqp->ud_header.bth.pkey); | ||
1498 | else | 1341 | else |
1499 | ib_get_cached_pkey(&dev->ib_dev, sqp->port, | 1342 | ib_get_cached_pkey(&dev->ib_dev, sqp->port, |
1500 | wr->wr.ud.pkey_index, | 1343 | wr->wr.ud.pkey_index, &pkey); |
1501 | &sqp->ud_header.bth.pkey); | 1344 | sqp->ud_header.bth.pkey = cpu_to_be16(pkey); |
1502 | cpu_to_be16s(&sqp->ud_header.bth.pkey); | ||
1503 | sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); | 1345 | sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); |
1504 | sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); | 1346 | sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); |
1505 | sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? | 1347 | sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? |
@@ -1742,7 +1584,7 @@ int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
1742 | 1584 | ||
1743 | out: | 1585 | out: |
1744 | if (likely(nreq)) { | 1586 | if (likely(nreq)) { |
1745 | u32 doorbell[2]; | 1587 | __be32 doorbell[2]; |
1746 | 1588 | ||
1747 | doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) + | 1589 | doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) + |
1748 | qp->send_wqe_offset) | f0 | op0); | 1590 | qp->send_wqe_offset) | f0 | op0); |
@@ -1843,7 +1685,7 @@ int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, | |||
1843 | 1685 | ||
1844 | out: | 1686 | out: |
1845 | if (likely(nreq)) { | 1687 | if (likely(nreq)) { |
1846 | u32 doorbell[2]; | 1688 | __be32 doorbell[2]; |
1847 | 1689 | ||
1848 | doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0); | 1690 | doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0); |
1849 | doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq); | 1691 | doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq); |
@@ -2064,7 +1906,7 @@ int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, | |||
2064 | 1906 | ||
2065 | out: | 1907 | out: |
2066 | if (likely(nreq)) { | 1908 | if (likely(nreq)) { |
2067 | u32 doorbell[2]; | 1909 | __be32 doorbell[2]; |
2068 | 1910 | ||
2069 | doorbell[0] = cpu_to_be32((nreq << 24) | | 1911 | doorbell[0] = cpu_to_be32((nreq << 24) | |
2070 | ((qp->sq.head & 0xffff) << 8) | | 1912 | ((qp->sq.head & 0xffff) << 8) | |
@@ -2174,19 +2016,25 @@ out: | |||
2174 | } | 2016 | } |
2175 | 2017 | ||
2176 | int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send, | 2018 | int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send, |
2177 | int index, int *dbd, u32 *new_wqe) | 2019 | int index, int *dbd, __be32 *new_wqe) |
2178 | { | 2020 | { |
2179 | struct mthca_next_seg *next; | 2021 | struct mthca_next_seg *next; |
2180 | 2022 | ||
2023 | /* | ||
2024 | * For SRQs, all WQEs generate a CQE, so we're always at the | ||
2025 | * end of the doorbell chain. | ||
2026 | */ | ||
2027 | if (qp->ibqp.srq) { | ||
2028 | *new_wqe = 0; | ||
2029 | return 0; | ||
2030 | } | ||
2031 | |||
2181 | if (is_send) | 2032 | if (is_send) |
2182 | next = get_send_wqe(qp, index); | 2033 | next = get_send_wqe(qp, index); |
2183 | else | 2034 | else |
2184 | next = get_recv_wqe(qp, index); | 2035 | next = get_recv_wqe(qp, index); |
2185 | 2036 | ||
2186 | if (mthca_is_memfree(dev)) | 2037 | *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD)); |
2187 | *dbd = 1; | ||
2188 | else | ||
2189 | *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD)); | ||
2190 | if (next->ee_nds & cpu_to_be32(0x3f)) | 2038 | if (next->ee_nds & cpu_to_be32(0x3f)) |
2191 | *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) | | 2039 | *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) | |
2192 | (next->ee_nds & cpu_to_be32(0x3f)); | 2040 | (next->ee_nds & cpu_to_be32(0x3f)); |