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Diffstat (limited to 'drivers/infiniband/hw/mthca/mthca_cq.c')
-rw-r--r--drivers/infiniband/hw/mthca/mthca_cq.c256
1 files changed, 81 insertions, 175 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_cq.c b/drivers/infiniband/hw/mthca/mthca_cq.c
index 5687c3014522..8600b6c3e0c2 100644
--- a/drivers/infiniband/hw/mthca/mthca_cq.c
+++ b/drivers/infiniband/hw/mthca/mthca_cq.c
@@ -2,6 +2,8 @@
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved. 4 * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
5 * 7 *
6 * This software is available to you under a choice of one of two 8 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU 9 * licenses. You may choose to be licensed under the terms of the GNU
@@ -37,7 +39,7 @@
37#include <linux/init.h> 39#include <linux/init.h>
38#include <linux/hardirq.h> 40#include <linux/hardirq.h>
39 41
40#include <ib_pack.h> 42#include <rdma/ib_pack.h>
41 43
42#include "mthca_dev.h" 44#include "mthca_dev.h"
43#include "mthca_cmd.h" 45#include "mthca_cmd.h"
@@ -55,21 +57,21 @@ enum {
55 * Must be packed because start is 64 bits but only aligned to 32 bits. 57 * Must be packed because start is 64 bits but only aligned to 32 bits.
56 */ 58 */
57struct mthca_cq_context { 59struct mthca_cq_context {
58 u32 flags; 60 __be32 flags;
59 u64 start; 61 __be64 start;
60 u32 logsize_usrpage; 62 __be32 logsize_usrpage;
61 u32 error_eqn; /* Tavor only */ 63 __be32 error_eqn; /* Tavor only */
62 u32 comp_eqn; 64 __be32 comp_eqn;
63 u32 pd; 65 __be32 pd;
64 u32 lkey; 66 __be32 lkey;
65 u32 last_notified_index; 67 __be32 last_notified_index;
66 u32 solicit_producer_index; 68 __be32 solicit_producer_index;
67 u32 consumer_index; 69 __be32 consumer_index;
68 u32 producer_index; 70 __be32 producer_index;
69 u32 cqn; 71 __be32 cqn;
70 u32 ci_db; /* Arbel only */ 72 __be32 ci_db; /* Arbel only */
71 u32 state_db; /* Arbel only */ 73 __be32 state_db; /* Arbel only */
72 u32 reserved; 74 u32 reserved;
73} __attribute__((packed)); 75} __attribute__((packed));
74 76
75#define MTHCA_CQ_STATUS_OK ( 0 << 28) 77#define MTHCA_CQ_STATUS_OK ( 0 << 28)
@@ -108,31 +110,31 @@ enum {
108}; 110};
109 111
110struct mthca_cqe { 112struct mthca_cqe {
111 u32 my_qpn; 113 __be32 my_qpn;
112 u32 my_ee; 114 __be32 my_ee;
113 u32 rqpn; 115 __be32 rqpn;
114 u16 sl_g_mlpath; 116 __be16 sl_g_mlpath;
115 u16 rlid; 117 __be16 rlid;
116 u32 imm_etype_pkey_eec; 118 __be32 imm_etype_pkey_eec;
117 u32 byte_cnt; 119 __be32 byte_cnt;
118 u32 wqe; 120 __be32 wqe;
119 u8 opcode; 121 u8 opcode;
120 u8 is_send; 122 u8 is_send;
121 u8 reserved; 123 u8 reserved;
122 u8 owner; 124 u8 owner;
123}; 125};
124 126
125struct mthca_err_cqe { 127struct mthca_err_cqe {
126 u32 my_qpn; 128 __be32 my_qpn;
127 u32 reserved1[3]; 129 u32 reserved1[3];
128 u8 syndrome; 130 u8 syndrome;
129 u8 reserved2; 131 u8 reserved2;
130 u16 db_cnt; 132 __be16 db_cnt;
131 u32 reserved3; 133 u32 reserved3;
132 u32 wqe; 134 __be32 wqe;
133 u8 opcode; 135 u8 opcode;
134 u8 reserved4[2]; 136 u8 reserved4[2];
135 u8 owner; 137 u8 owner;
136}; 138};
137 139
138#define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7) 140#define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
@@ -191,7 +193,7 @@ static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
191static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, 193static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
192 int incr) 194 int incr)
193{ 195{
194 u32 doorbell[2]; 196 __be32 doorbell[2];
195 197
196 if (mthca_is_memfree(dev)) { 198 if (mthca_is_memfree(dev)) {
197 *cq->set_ci_db = cpu_to_be32(cq->cons_index); 199 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
@@ -222,7 +224,8 @@ void mthca_cq_event(struct mthca_dev *dev, u32 cqn)
222 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 224 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
223} 225}
224 226
225void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn) 227void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
228 struct mthca_srq *srq)
226{ 229{
227 struct mthca_cq *cq; 230 struct mthca_cq *cq;
228 struct mthca_cqe *cqe; 231 struct mthca_cqe *cqe;
@@ -263,8 +266,11 @@ void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn)
263 */ 266 */
264 while (prod_index > cq->cons_index) { 267 while (prod_index > cq->cons_index) {
265 cqe = get_cqe(cq, (prod_index - 1) & cq->ibcq.cqe); 268 cqe = get_cqe(cq, (prod_index - 1) & cq->ibcq.cqe);
266 if (cqe->my_qpn == cpu_to_be32(qpn)) 269 if (cqe->my_qpn == cpu_to_be32(qpn)) {
270 if (srq)
271 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
267 ++nfreed; 272 ++nfreed;
273 }
268 else if (nfreed) 274 else if (nfreed)
269 memcpy(get_cqe(cq, (prod_index - 1 + nfreed) & 275 memcpy(get_cqe(cq, (prod_index - 1 + nfreed) &
270 cq->ibcq.cqe), 276 cq->ibcq.cqe),
@@ -291,7 +297,7 @@ static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
291{ 297{
292 int err; 298 int err;
293 int dbd; 299 int dbd;
294 u32 new_wqe; 300 __be32 new_wqe;
295 301
296 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) { 302 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
297 mthca_dbg(dev, "local QP operation err " 303 mthca_dbg(dev, "local QP operation err "
@@ -365,6 +371,13 @@ static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
365 break; 371 break;
366 } 372 }
367 373
374 /*
375 * Mem-free HCAs always generate one CQE per WQE, even in the
376 * error case, so we don't have to check the doorbell count, etc.
377 */
378 if (mthca_is_memfree(dev))
379 return 0;
380
368 err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe); 381 err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
369 if (err) 382 if (err)
370 return err; 383 return err;
@@ -373,12 +386,8 @@ static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
373 * If we're at the end of the WQE chain, or we've used up our 386 * If we're at the end of the WQE chain, or we've used up our
374 * doorbell count, free the CQE. Otherwise just update it for 387 * doorbell count, free the CQE. Otherwise just update it for
375 * the next poll operation. 388 * the next poll operation.
376 *
377 * This does not apply to mem-free HCAs: they don't use the
378 * doorbell count field, and so we should always free the CQE.
379 */ 389 */
380 if (mthca_is_memfree(dev) || 390 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
381 !(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
382 return 0; 391 return 0;
383 392
384 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd); 393 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
@@ -450,23 +459,27 @@ static inline int mthca_poll_one(struct mthca_dev *dev,
450 >> wq->wqe_shift); 459 >> wq->wqe_shift);
451 entry->wr_id = (*cur_qp)->wrid[wqe_index + 460 entry->wr_id = (*cur_qp)->wrid[wqe_index +
452 (*cur_qp)->rq.max]; 461 (*cur_qp)->rq.max];
462 } else if ((*cur_qp)->ibqp.srq) {
463 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
464 u32 wqe = be32_to_cpu(cqe->wqe);
465 wq = NULL;
466 wqe_index = wqe >> srq->wqe_shift;
467 entry->wr_id = srq->wrid[wqe_index];
468 mthca_free_srq_wqe(srq, wqe);
453 } else { 469 } else {
454 wq = &(*cur_qp)->rq; 470 wq = &(*cur_qp)->rq;
455 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift; 471 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
456 entry->wr_id = (*cur_qp)->wrid[wqe_index]; 472 entry->wr_id = (*cur_qp)->wrid[wqe_index];
457 } 473 }
458 474
459 if (wq->last_comp < wqe_index) 475 if (wq) {
460 wq->tail += wqe_index - wq->last_comp; 476 if (wq->last_comp < wqe_index)
461 else 477 wq->tail += wqe_index - wq->last_comp;
462 wq->tail += wqe_index + wq->max - wq->last_comp; 478 else
463 479 wq->tail += wqe_index + wq->max - wq->last_comp;
464 wq->last_comp = wqe_index;
465 480
466 if (0) 481 wq->last_comp = wqe_index;
467 mthca_dbg(dev, "%s completion for QP %06x, index %d (nr %d)\n", 482 }
468 is_send ? "Send" : "Receive",
469 (*cur_qp)->qpn, wqe_index, wq->max);
470 483
471 if (is_error) { 484 if (is_error) {
472 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send, 485 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
@@ -584,13 +597,13 @@ int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
584 597
585int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify) 598int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
586{ 599{
587 u32 doorbell[2]; 600 __be32 doorbell[2];
588 601
589 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ? 602 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
590 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL : 603 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
591 MTHCA_TAVOR_CQ_DB_REQ_NOT) | 604 MTHCA_TAVOR_CQ_DB_REQ_NOT) |
592 to_mcq(cq)->cqn); 605 to_mcq(cq)->cqn);
593 doorbell[1] = 0xffffffff; 606 doorbell[1] = (__force __be32) 0xffffffff;
594 607
595 mthca_write64(doorbell, 608 mthca_write64(doorbell,
596 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL, 609 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
@@ -602,9 +615,9 @@ int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
602int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify) 615int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
603{ 616{
604 struct mthca_cq *cq = to_mcq(ibcq); 617 struct mthca_cq *cq = to_mcq(ibcq);
605 u32 doorbell[2]; 618 __be32 doorbell[2];
606 u32 sn; 619 u32 sn;
607 u32 ci; 620 __be32 ci;
608 621
609 sn = cq->arm_sn & 3; 622 sn = cq->arm_sn & 3;
610 ci = cpu_to_be32(cq->cons_index); 623 ci = cpu_to_be32(cq->cons_index);
@@ -637,113 +650,8 @@ int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
637 650
638static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq) 651static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
639{ 652{
640 int i; 653 mthca_buf_free(dev, (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
641 int size; 654 &cq->queue, cq->is_direct, &cq->mr);
642
643 if (cq->is_direct)
644 dma_free_coherent(&dev->pdev->dev,
645 (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
646 cq->queue.direct.buf,
647 pci_unmap_addr(&cq->queue.direct,
648 mapping));
649 else {
650 size = (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE;
651 for (i = 0; i < (size + PAGE_SIZE - 1) / PAGE_SIZE; ++i)
652 if (cq->queue.page_list[i].buf)
653 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
654 cq->queue.page_list[i].buf,
655 pci_unmap_addr(&cq->queue.page_list[i],
656 mapping));
657
658 kfree(cq->queue.page_list);
659 }
660}
661
662static int mthca_alloc_cq_buf(struct mthca_dev *dev, int size,
663 struct mthca_cq *cq)
664{
665 int err = -ENOMEM;
666 int npages, shift;
667 u64 *dma_list = NULL;
668 dma_addr_t t;
669 int i;
670
671 if (size <= MTHCA_MAX_DIRECT_CQ_SIZE) {
672 cq->is_direct = 1;
673 npages = 1;
674 shift = get_order(size) + PAGE_SHIFT;
675
676 cq->queue.direct.buf = dma_alloc_coherent(&dev->pdev->dev,
677 size, &t, GFP_KERNEL);
678 if (!cq->queue.direct.buf)
679 return -ENOMEM;
680
681 pci_unmap_addr_set(&cq->queue.direct, mapping, t);
682
683 memset(cq->queue.direct.buf, 0, size);
684
685 while (t & ((1 << shift) - 1)) {
686 --shift;
687 npages *= 2;
688 }
689
690 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
691 if (!dma_list)
692 goto err_free;
693
694 for (i = 0; i < npages; ++i)
695 dma_list[i] = t + i * (1 << shift);
696 } else {
697 cq->is_direct = 0;
698 npages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
699 shift = PAGE_SHIFT;
700
701 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
702 if (!dma_list)
703 return -ENOMEM;
704
705 cq->queue.page_list = kmalloc(npages * sizeof *cq->queue.page_list,
706 GFP_KERNEL);
707 if (!cq->queue.page_list)
708 goto err_out;
709
710 for (i = 0; i < npages; ++i)
711 cq->queue.page_list[i].buf = NULL;
712
713 for (i = 0; i < npages; ++i) {
714 cq->queue.page_list[i].buf =
715 dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE,
716 &t, GFP_KERNEL);
717 if (!cq->queue.page_list[i].buf)
718 goto err_free;
719
720 dma_list[i] = t;
721 pci_unmap_addr_set(&cq->queue.page_list[i], mapping, t);
722
723 memset(cq->queue.page_list[i].buf, 0, PAGE_SIZE);
724 }
725 }
726
727 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
728 dma_list, shift, npages,
729 0, size,
730 MTHCA_MPT_FLAG_LOCAL_WRITE |
731 MTHCA_MPT_FLAG_LOCAL_READ,
732 &cq->mr);
733 if (err)
734 goto err_free;
735
736 kfree(dma_list);
737
738 return 0;
739
740err_free:
741 mthca_free_cq_buf(dev, cq);
742
743err_out:
744 kfree(dma_list);
745
746 return err;
747} 655}
748 656
749int mthca_init_cq(struct mthca_dev *dev, int nent, 657int mthca_init_cq(struct mthca_dev *dev, int nent,
@@ -795,7 +703,9 @@ int mthca_init_cq(struct mthca_dev *dev, int nent,
795 cq_context = mailbox->buf; 703 cq_context = mailbox->buf;
796 704
797 if (cq->is_kernel) { 705 if (cq->is_kernel) {
798 err = mthca_alloc_cq_buf(dev, size, cq); 706 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_CQ_SIZE,
707 &cq->queue, &cq->is_direct,
708 &dev->driver_pd, 1, &cq->mr);
799 if (err) 709 if (err)
800 goto err_out_mailbox; 710 goto err_out_mailbox;
801 711
@@ -811,7 +721,6 @@ int mthca_init_cq(struct mthca_dev *dev, int nent,
811 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK | 721 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
812 MTHCA_CQ_STATE_DISARMED | 722 MTHCA_CQ_STATE_DISARMED |
813 MTHCA_CQ_FLAG_TR); 723 MTHCA_CQ_FLAG_TR);
814 cq_context->start = cpu_to_be64(0);
815 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24); 724 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
816 if (ctx) 725 if (ctx)
817 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index); 726 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
@@ -857,10 +766,8 @@ int mthca_init_cq(struct mthca_dev *dev, int nent,
857 return 0; 766 return 0;
858 767
859err_out_free_mr: 768err_out_free_mr:
860 if (cq->is_kernel) { 769 if (cq->is_kernel)
861 mthca_free_mr(dev, &cq->mr);
862 mthca_free_cq_buf(dev, cq); 770 mthca_free_cq_buf(dev, cq);
863 }
864 771
865err_out_mailbox: 772err_out_mailbox:
866 mthca_free_mailbox(dev, mailbox); 773 mthca_free_mailbox(dev, mailbox);
@@ -904,7 +811,7 @@ void mthca_free_cq(struct mthca_dev *dev,
904 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status); 811 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
905 812
906 if (0) { 813 if (0) {
907 u32 *ctx = mailbox->buf; 814 __be32 *ctx = mailbox->buf;
908 int j; 815 int j;
909 816
910 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n", 817 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
@@ -928,7 +835,6 @@ void mthca_free_cq(struct mthca_dev *dev,
928 wait_event(cq->wait, !atomic_read(&cq->refcount)); 835 wait_event(cq->wait, !atomic_read(&cq->refcount));
929 836
930 if (cq->is_kernel) { 837 if (cq->is_kernel) {
931 mthca_free_mr(dev, &cq->mr);
932 mthca_free_cq_buf(dev, cq); 838 mthca_free_cq_buf(dev, cq);
933 if (mthca_is_memfree(dev)) { 839 if (mthca_is_memfree(dev)) {
934 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index); 840 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);