diff options
Diffstat (limited to 'drivers/infiniband/hw/ipath/ipath_iba6120.c')
-rw-r--r-- | drivers/infiniband/hw/ipath/ipath_iba6120.c | 1254 |
1 files changed, 1254 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6120.c b/drivers/infiniband/hw/ipath/ipath_iba6120.c new file mode 100644 index 000000000000..f4233baaa338 --- /dev/null +++ b/drivers/infiniband/hw/ipath/ipath_iba6120.c | |||
@@ -0,0 +1,1254 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2006 QLogic, Inc. All rights reserved. | ||
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the | ||
9 | * OpenIB.org BSD license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or | ||
12 | * without modification, are permitted provided that the following | ||
13 | * conditions are met: | ||
14 | * | ||
15 | * - Redistributions of source code must retain the above | ||
16 | * copyright notice, this list of conditions and the following | ||
17 | * disclaimer. | ||
18 | * | ||
19 | * - Redistributions in binary form must reproduce the above | ||
20 | * copyright notice, this list of conditions and the following | ||
21 | * disclaimer in the documentation and/or other materials | ||
22 | * provided with the distribution. | ||
23 | * | ||
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | ||
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | ||
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
31 | * SOFTWARE. | ||
32 | */ | ||
33 | /* | ||
34 | * This file contains all of the code that is specific to the | ||
35 | * InfiniPath PCIe chip. | ||
36 | */ | ||
37 | |||
38 | #include <linux/interrupt.h> | ||
39 | #include <linux/pci.h> | ||
40 | #include <linux/delay.h> | ||
41 | |||
42 | |||
43 | #include "ipath_kernel.h" | ||
44 | #include "ipath_registers.h" | ||
45 | |||
46 | /* | ||
47 | * This file contains all the chip-specific register information and | ||
48 | * access functions for the QLogic InfiniPath PCI-Express chip. | ||
49 | * | ||
50 | * This lists the InfiniPath registers, in the actual chip layout. | ||
51 | * This structure should never be directly accessed. | ||
52 | */ | ||
53 | struct _infinipath_do_not_use_kernel_regs { | ||
54 | unsigned long long Revision; | ||
55 | unsigned long long Control; | ||
56 | unsigned long long PageAlign; | ||
57 | unsigned long long PortCnt; | ||
58 | unsigned long long DebugPortSelect; | ||
59 | unsigned long long Reserved0; | ||
60 | unsigned long long SendRegBase; | ||
61 | unsigned long long UserRegBase; | ||
62 | unsigned long long CounterRegBase; | ||
63 | unsigned long long Scratch; | ||
64 | unsigned long long Reserved1; | ||
65 | unsigned long long Reserved2; | ||
66 | unsigned long long IntBlocked; | ||
67 | unsigned long long IntMask; | ||
68 | unsigned long long IntStatus; | ||
69 | unsigned long long IntClear; | ||
70 | unsigned long long ErrorMask; | ||
71 | unsigned long long ErrorStatus; | ||
72 | unsigned long long ErrorClear; | ||
73 | unsigned long long HwErrMask; | ||
74 | unsigned long long HwErrStatus; | ||
75 | unsigned long long HwErrClear; | ||
76 | unsigned long long HwDiagCtrl; | ||
77 | unsigned long long MDIO; | ||
78 | unsigned long long IBCStatus; | ||
79 | unsigned long long IBCCtrl; | ||
80 | unsigned long long ExtStatus; | ||
81 | unsigned long long ExtCtrl; | ||
82 | unsigned long long GPIOOut; | ||
83 | unsigned long long GPIOMask; | ||
84 | unsigned long long GPIOStatus; | ||
85 | unsigned long long GPIOClear; | ||
86 | unsigned long long RcvCtrl; | ||
87 | unsigned long long RcvBTHQP; | ||
88 | unsigned long long RcvHdrSize; | ||
89 | unsigned long long RcvHdrCnt; | ||
90 | unsigned long long RcvHdrEntSize; | ||
91 | unsigned long long RcvTIDBase; | ||
92 | unsigned long long RcvTIDCnt; | ||
93 | unsigned long long RcvEgrBase; | ||
94 | unsigned long long RcvEgrCnt; | ||
95 | unsigned long long RcvBufBase; | ||
96 | unsigned long long RcvBufSize; | ||
97 | unsigned long long RxIntMemBase; | ||
98 | unsigned long long RxIntMemSize; | ||
99 | unsigned long long RcvPartitionKey; | ||
100 | unsigned long long Reserved3; | ||
101 | unsigned long long RcvPktLEDCnt; | ||
102 | unsigned long long Reserved4[8]; | ||
103 | unsigned long long SendCtrl; | ||
104 | unsigned long long SendPIOBufBase; | ||
105 | unsigned long long SendPIOSize; | ||
106 | unsigned long long SendPIOBufCnt; | ||
107 | unsigned long long SendPIOAvailAddr; | ||
108 | unsigned long long TxIntMemBase; | ||
109 | unsigned long long TxIntMemSize; | ||
110 | unsigned long long Reserved5; | ||
111 | unsigned long long PCIeRBufTestReg0; | ||
112 | unsigned long long PCIeRBufTestReg1; | ||
113 | unsigned long long Reserved51[6]; | ||
114 | unsigned long long SendBufferError; | ||
115 | unsigned long long SendBufferErrorCONT1; | ||
116 | unsigned long long Reserved6SBE[6]; | ||
117 | unsigned long long RcvHdrAddr0; | ||
118 | unsigned long long RcvHdrAddr1; | ||
119 | unsigned long long RcvHdrAddr2; | ||
120 | unsigned long long RcvHdrAddr3; | ||
121 | unsigned long long RcvHdrAddr4; | ||
122 | unsigned long long Reserved7RHA[11]; | ||
123 | unsigned long long RcvHdrTailAddr0; | ||
124 | unsigned long long RcvHdrTailAddr1; | ||
125 | unsigned long long RcvHdrTailAddr2; | ||
126 | unsigned long long RcvHdrTailAddr3; | ||
127 | unsigned long long RcvHdrTailAddr4; | ||
128 | unsigned long long Reserved8RHTA[11]; | ||
129 | unsigned long long Reserved9SW[8]; | ||
130 | unsigned long long SerdesConfig0; | ||
131 | unsigned long long SerdesConfig1; | ||
132 | unsigned long long SerdesStatus; | ||
133 | unsigned long long XGXSConfig; | ||
134 | unsigned long long IBPLLCfg; | ||
135 | unsigned long long Reserved10SW2[3]; | ||
136 | unsigned long long PCIEQ0SerdesConfig0; | ||
137 | unsigned long long PCIEQ0SerdesConfig1; | ||
138 | unsigned long long PCIEQ0SerdesStatus; | ||
139 | unsigned long long Reserved11; | ||
140 | unsigned long long PCIEQ1SerdesConfig0; | ||
141 | unsigned long long PCIEQ1SerdesConfig1; | ||
142 | unsigned long long PCIEQ1SerdesStatus; | ||
143 | unsigned long long Reserved12; | ||
144 | }; | ||
145 | |||
146 | #define IPATH_KREG_OFFSET(field) (offsetof(struct \ | ||
147 | _infinipath_do_not_use_kernel_regs, field) / sizeof(u64)) | ||
148 | #define IPATH_CREG_OFFSET(field) (offsetof( \ | ||
149 | struct infinipath_counters, field) / sizeof(u64)) | ||
150 | |||
151 | static const struct ipath_kregs ipath_pe_kregs = { | ||
152 | .kr_control = IPATH_KREG_OFFSET(Control), | ||
153 | .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase), | ||
154 | .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect), | ||
155 | .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear), | ||
156 | .kr_errormask = IPATH_KREG_OFFSET(ErrorMask), | ||
157 | .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus), | ||
158 | .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl), | ||
159 | .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus), | ||
160 | .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear), | ||
161 | .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask), | ||
162 | .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut), | ||
163 | .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus), | ||
164 | .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl), | ||
165 | .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear), | ||
166 | .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask), | ||
167 | .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus), | ||
168 | .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl), | ||
169 | .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus), | ||
170 | .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked), | ||
171 | .kr_intclear = IPATH_KREG_OFFSET(IntClear), | ||
172 | .kr_intmask = IPATH_KREG_OFFSET(IntMask), | ||
173 | .kr_intstatus = IPATH_KREG_OFFSET(IntStatus), | ||
174 | .kr_mdio = IPATH_KREG_OFFSET(MDIO), | ||
175 | .kr_pagealign = IPATH_KREG_OFFSET(PageAlign), | ||
176 | .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey), | ||
177 | .kr_portcnt = IPATH_KREG_OFFSET(PortCnt), | ||
178 | .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP), | ||
179 | .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase), | ||
180 | .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize), | ||
181 | .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl), | ||
182 | .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase), | ||
183 | .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt), | ||
184 | .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt), | ||
185 | .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize), | ||
186 | .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize), | ||
187 | .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase), | ||
188 | .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize), | ||
189 | .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase), | ||
190 | .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt), | ||
191 | .kr_revision = IPATH_KREG_OFFSET(Revision), | ||
192 | .kr_scratch = IPATH_KREG_OFFSET(Scratch), | ||
193 | .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError), | ||
194 | .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl), | ||
195 | .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr), | ||
196 | .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase), | ||
197 | .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt), | ||
198 | .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize), | ||
199 | .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase), | ||
200 | .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase), | ||
201 | .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize), | ||
202 | .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase), | ||
203 | .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0), | ||
204 | .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1), | ||
205 | .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus), | ||
206 | .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig), | ||
207 | .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg), | ||
208 | |||
209 | /* | ||
210 | * These should not be used directly via ipath_read_kreg64(), | ||
211 | * use them with ipath_read_kreg64_port() | ||
212 | */ | ||
213 | .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0), | ||
214 | .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0), | ||
215 | |||
216 | /* The rcvpktled register controls one of the debug port signals, so | ||
217 | * a packet activity LED can be connected to it. */ | ||
218 | .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt), | ||
219 | .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0), | ||
220 | .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1), | ||
221 | .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0), | ||
222 | .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1), | ||
223 | .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus), | ||
224 | .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0), | ||
225 | .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1), | ||
226 | .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus) | ||
227 | }; | ||
228 | |||
229 | static const struct ipath_cregs ipath_pe_cregs = { | ||
230 | .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt), | ||
231 | .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt), | ||
232 | .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt), | ||
233 | .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt), | ||
234 | .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt), | ||
235 | .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt), | ||
236 | .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt), | ||
237 | .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt), | ||
238 | .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt), | ||
239 | .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt), | ||
240 | .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt), | ||
241 | .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt), | ||
242 | .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt), | ||
243 | .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt), | ||
244 | .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt), | ||
245 | .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt), | ||
246 | .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt), | ||
247 | .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt), | ||
248 | .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt), | ||
249 | .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt), | ||
250 | .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt), | ||
251 | .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt), | ||
252 | .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt), | ||
253 | .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt), | ||
254 | .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt), | ||
255 | .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt), | ||
256 | .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt), | ||
257 | .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt), | ||
258 | .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt), | ||
259 | .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt), | ||
260 | .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt), | ||
261 | .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt), | ||
262 | .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt) | ||
263 | }; | ||
264 | |||
265 | /* kr_intstatus, kr_intclear, kr_intmask bits */ | ||
266 | #define INFINIPATH_I_RCVURG_MASK 0x1F | ||
267 | #define INFINIPATH_I_RCVAVAIL_MASK 0x1F | ||
268 | |||
269 | /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */ | ||
270 | #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL | ||
271 | #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0 | ||
272 | #define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL | ||
273 | #define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL | ||
274 | #define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL | ||
275 | #define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL | ||
276 | #define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL | ||
277 | #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL | ||
278 | #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL | ||
279 | #define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL | ||
280 | #define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL | ||
281 | #define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL | ||
282 | |||
283 | /* kr_extstatus bits */ | ||
284 | #define INFINIPATH_EXTS_FREQSEL 0x2 | ||
285 | #define INFINIPATH_EXTS_SERDESSEL 0x4 | ||
286 | #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000 | ||
287 | #define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000 | ||
288 | |||
289 | #define _IPATH_GPIO_SDA_NUM 1 | ||
290 | #define _IPATH_GPIO_SCL_NUM 0 | ||
291 | |||
292 | #define IPATH_GPIO_SDA (1ULL << \ | ||
293 | (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT)) | ||
294 | #define IPATH_GPIO_SCL (1ULL << \ | ||
295 | (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT)) | ||
296 | |||
297 | /** | ||
298 | * ipath_pe_handle_hwerrors - display hardware errors. | ||
299 | * @dd: the infinipath device | ||
300 | * @msg: the output buffer | ||
301 | * @msgl: the size of the output buffer | ||
302 | * | ||
303 | * Use same msg buffer as regular errors to avoid excessive stack | ||
304 | * use. Most hardware errors are catastrophic, but for right now, | ||
305 | * we'll print them and continue. We reuse the same message buffer as | ||
306 | * ipath_handle_errors() to avoid excessive stack usage. | ||
307 | */ | ||
308 | static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg, | ||
309 | size_t msgl) | ||
310 | { | ||
311 | ipath_err_t hwerrs; | ||
312 | u32 bits, ctrl; | ||
313 | int isfatal = 0; | ||
314 | char bitsmsg[64]; | ||
315 | |||
316 | hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus); | ||
317 | if (!hwerrs) { | ||
318 | /* | ||
319 | * better than printing cofusing messages | ||
320 | * This seems to be related to clearing the crc error, or | ||
321 | * the pll error during init. | ||
322 | */ | ||
323 | ipath_cdbg(VERBOSE, "Called but no hardware errors set\n"); | ||
324 | return; | ||
325 | } else if (hwerrs == ~0ULL) { | ||
326 | ipath_dev_err(dd, "Read of hardware error status failed " | ||
327 | "(all bits set); ignoring\n"); | ||
328 | return; | ||
329 | } | ||
330 | ipath_stats.sps_hwerrs++; | ||
331 | |||
332 | /* Always clear the error status register, except MEMBISTFAIL, | ||
333 | * regardless of whether we continue or stop using the chip. | ||
334 | * We want that set so we know it failed, even across driver reload. | ||
335 | * We'll still ignore it in the hwerrmask. We do this partly for | ||
336 | * diagnostics, but also for support */ | ||
337 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | ||
338 | hwerrs&~INFINIPATH_HWE_MEMBISTFAILED); | ||
339 | |||
340 | hwerrs &= dd->ipath_hwerrmask; | ||
341 | |||
342 | /* | ||
343 | * make sure we get this much out, unless told to be quiet, | ||
344 | * or it's occurred within the last 5 seconds | ||
345 | */ | ||
346 | if ((hwerrs & ~dd->ipath_lasthwerror) || | ||
347 | (ipath_debug & __IPATH_VERBDBG)) | ||
348 | dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx " | ||
349 | "(cleared)\n", (unsigned long long) hwerrs); | ||
350 | dd->ipath_lasthwerror |= hwerrs; | ||
351 | |||
352 | if (hwerrs & ~infinipath_hwe_bitsextant) | ||
353 | ipath_dev_err(dd, "hwerror interrupt with unknown errors " | ||
354 | "%llx set\n", (unsigned long long) | ||
355 | (hwerrs & ~infinipath_hwe_bitsextant)); | ||
356 | |||
357 | ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control); | ||
358 | if (ctrl & INFINIPATH_C_FREEZEMODE) { | ||
359 | if (hwerrs) { | ||
360 | /* | ||
361 | * if any set that we aren't ignoring only make the | ||
362 | * complaint once, in case it's stuck or recurring, | ||
363 | * and we get here multiple times | ||
364 | */ | ||
365 | if (dd->ipath_flags & IPATH_INITTED) { | ||
366 | ipath_dev_err(dd, "Fatal Error (freeze " | ||
367 | "mode), no longer usable\n"); | ||
368 | isfatal = 1; | ||
369 | } | ||
370 | /* | ||
371 | * Mark as having had an error for driver, and also | ||
372 | * for /sys and status word mapped to user programs. | ||
373 | * This marks unit as not usable, until reset | ||
374 | */ | ||
375 | *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; | ||
376 | *dd->ipath_statusp |= IPATH_STATUS_HWERROR; | ||
377 | dd->ipath_flags &= ~IPATH_INITTED; | ||
378 | } else { | ||
379 | ipath_dbg("Clearing freezemode on ignored hardware " | ||
380 | "error\n"); | ||
381 | ctrl &= ~INFINIPATH_C_FREEZEMODE; | ||
382 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | ||
383 | ctrl); | ||
384 | } | ||
385 | } | ||
386 | |||
387 | *msg = '\0'; | ||
388 | |||
389 | if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) { | ||
390 | strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]", | ||
391 | msgl); | ||
392 | /* ignore from now on, so disable until driver reloaded */ | ||
393 | *dd->ipath_statusp |= IPATH_STATUS_HWERROR; | ||
394 | dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED; | ||
395 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, | ||
396 | dd->ipath_hwerrmask); | ||
397 | } | ||
398 | if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK | ||
399 | << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) { | ||
400 | bits = (u32) ((hwerrs >> | ||
401 | INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) & | ||
402 | INFINIPATH_HWE_RXEMEMPARITYERR_MASK); | ||
403 | snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ", | ||
404 | bits); | ||
405 | strlcat(msg, bitsmsg, msgl); | ||
406 | } | ||
407 | if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK | ||
408 | << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) { | ||
409 | bits = (u32) ((hwerrs >> | ||
410 | INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) & | ||
411 | INFINIPATH_HWE_TXEMEMPARITYERR_MASK); | ||
412 | snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ", | ||
413 | bits); | ||
414 | strlcat(msg, bitsmsg, msgl); | ||
415 | } | ||
416 | if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK | ||
417 | << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) { | ||
418 | bits = (u32) ((hwerrs >> | ||
419 | INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) & | ||
420 | INFINIPATH_HWE_PCIEMEMPARITYERR_MASK); | ||
421 | snprintf(bitsmsg, sizeof bitsmsg, | ||
422 | "[PCIe Mem Parity Errs %x] ", bits); | ||
423 | strlcat(msg, bitsmsg, msgl); | ||
424 | } | ||
425 | if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR) | ||
426 | strlcat(msg, "[IB2IPATH Parity]", msgl); | ||
427 | if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR) | ||
428 | strlcat(msg, "[IPATH2IB Parity]", msgl); | ||
429 | |||
430 | #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \ | ||
431 | INFINIPATH_HWE_COREPLL_RFSLIP ) | ||
432 | |||
433 | if (hwerrs & _IPATH_PLL_FAIL) { | ||
434 | snprintf(bitsmsg, sizeof bitsmsg, | ||
435 | "[PLL failed (%llx), InfiniPath hardware unusable]", | ||
436 | (unsigned long long) hwerrs & _IPATH_PLL_FAIL); | ||
437 | strlcat(msg, bitsmsg, msgl); | ||
438 | /* ignore from now on, so disable until driver reloaded */ | ||
439 | dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL); | ||
440 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, | ||
441 | dd->ipath_hwerrmask); | ||
442 | } | ||
443 | |||
444 | if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) { | ||
445 | /* | ||
446 | * If it occurs, it is left masked since the eternal | ||
447 | * interface is unused | ||
448 | */ | ||
449 | dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED; | ||
450 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, | ||
451 | dd->ipath_hwerrmask); | ||
452 | } | ||
453 | |||
454 | if (hwerrs & INFINIPATH_HWE_PCIEPOISONEDTLP) | ||
455 | strlcat(msg, "[PCIe Poisoned TLP]", msgl); | ||
456 | if (hwerrs & INFINIPATH_HWE_PCIECPLTIMEOUT) | ||
457 | strlcat(msg, "[PCIe completion timeout]", msgl); | ||
458 | |||
459 | /* | ||
460 | * In practice, it's unlikely wthat we'll see PCIe PLL, or bus | ||
461 | * parity or memory parity error failures, because most likely we | ||
462 | * won't be able to talk to the core of the chip. Nonetheless, we | ||
463 | * might see them, if they are in parts of the PCIe core that aren't | ||
464 | * essential. | ||
465 | */ | ||
466 | if (hwerrs & INFINIPATH_HWE_PCIE1PLLFAILED) | ||
467 | strlcat(msg, "[PCIePLL1]", msgl); | ||
468 | if (hwerrs & INFINIPATH_HWE_PCIE0PLLFAILED) | ||
469 | strlcat(msg, "[PCIePLL0]", msgl); | ||
470 | if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXTLH) | ||
471 | strlcat(msg, "[PCIe XTLH core parity]", msgl); | ||
472 | if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXADM) | ||
473 | strlcat(msg, "[PCIe ADM TX core parity]", msgl); | ||
474 | if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYRADM) | ||
475 | strlcat(msg, "[PCIe ADM RX core parity]", msgl); | ||
476 | |||
477 | if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR) | ||
478 | strlcat(msg, "[Rx Dsync]", msgl); | ||
479 | if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) | ||
480 | strlcat(msg, "[SerDes PLL]", msgl); | ||
481 | |||
482 | ipath_dev_err(dd, "%s hardware error\n", msg); | ||
483 | if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) { | ||
484 | /* | ||
485 | * for /sys status file ; if no trailing } is copied, we'll | ||
486 | * know it was truncated. | ||
487 | */ | ||
488 | snprintf(dd->ipath_freezemsg, dd->ipath_freezelen, | ||
489 | "{%s}", msg); | ||
490 | } | ||
491 | } | ||
492 | |||
493 | /** | ||
494 | * ipath_pe_boardname - fill in the board name | ||
495 | * @dd: the infinipath device | ||
496 | * @name: the output buffer | ||
497 | * @namelen: the size of the output buffer | ||
498 | * | ||
499 | * info is based on the board revision register | ||
500 | */ | ||
501 | static int ipath_pe_boardname(struct ipath_devdata *dd, char *name, | ||
502 | size_t namelen) | ||
503 | { | ||
504 | char *n = NULL; | ||
505 | u8 boardrev = dd->ipath_boardrev; | ||
506 | int ret; | ||
507 | |||
508 | switch (boardrev) { | ||
509 | case 0: | ||
510 | n = "InfiniPath_Emulation"; | ||
511 | break; | ||
512 | case 1: | ||
513 | n = "InfiniPath_QLE7140-Bringup"; | ||
514 | break; | ||
515 | case 2: | ||
516 | n = "InfiniPath_QLE7140"; | ||
517 | break; | ||
518 | case 3: | ||
519 | n = "InfiniPath_QMI7140"; | ||
520 | break; | ||
521 | case 4: | ||
522 | n = "InfiniPath_QEM7140"; | ||
523 | break; | ||
524 | case 5: | ||
525 | n = "InfiniPath_QMH7140"; | ||
526 | break; | ||
527 | default: | ||
528 | ipath_dev_err(dd, | ||
529 | "Don't yet know about board with ID %u\n", | ||
530 | boardrev); | ||
531 | snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u", | ||
532 | boardrev); | ||
533 | break; | ||
534 | } | ||
535 | if (n) | ||
536 | snprintf(name, namelen, "%s", n); | ||
537 | |||
538 | if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) { | ||
539 | ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n", | ||
540 | dd->ipath_majrev, dd->ipath_minrev); | ||
541 | ret = 1; | ||
542 | } else | ||
543 | ret = 0; | ||
544 | |||
545 | return ret; | ||
546 | } | ||
547 | |||
548 | /** | ||
549 | * ipath_pe_init_hwerrors - enable hardware errors | ||
550 | * @dd: the infinipath device | ||
551 | * | ||
552 | * now that we have finished initializing everything that might reasonably | ||
553 | * cause a hardware error, and cleared those errors bits as they occur, | ||
554 | * we can enable hardware errors in the mask (potentially enabling | ||
555 | * freeze mode), and enable hardware errors as errors (along with | ||
556 | * everything else) in errormask | ||
557 | */ | ||
558 | static void ipath_pe_init_hwerrors(struct ipath_devdata *dd) | ||
559 | { | ||
560 | ipath_err_t val; | ||
561 | u64 extsval; | ||
562 | |||
563 | extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus); | ||
564 | |||
565 | if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST)) | ||
566 | ipath_dev_err(dd, "MemBIST did not complete!\n"); | ||
567 | |||
568 | val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */ | ||
569 | |||
570 | if (!dd->ipath_boardrev) // no PLL for Emulator | ||
571 | val &= ~INFINIPATH_HWE_SERDESPLLFAILED; | ||
572 | |||
573 | /* workaround bug 9460 in internal interface bus parity checking */ | ||
574 | val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM; | ||
575 | |||
576 | dd->ipath_hwerrmask = val; | ||
577 | } | ||
578 | |||
579 | /** | ||
580 | * ipath_pe_bringup_serdes - bring up the serdes | ||
581 | * @dd: the infinipath device | ||
582 | */ | ||
583 | static int ipath_pe_bringup_serdes(struct ipath_devdata *dd) | ||
584 | { | ||
585 | u64 val, tmp, config1; | ||
586 | int ret = 0, change = 0; | ||
587 | |||
588 | ipath_dbg("Trying to bringup serdes\n"); | ||
589 | |||
590 | if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) & | ||
591 | INFINIPATH_HWE_SERDESPLLFAILED) { | ||
592 | ipath_dbg("At start, serdes PLL failed bit set " | ||
593 | "in hwerrstatus, clearing and continuing\n"); | ||
594 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | ||
595 | INFINIPATH_HWE_SERDESPLLFAILED); | ||
596 | } | ||
597 | |||
598 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); | ||
599 | config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1); | ||
600 | |||
601 | ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, " | ||
602 | "xgxsconfig %llx\n", (unsigned long long) val, | ||
603 | (unsigned long long) config1, (unsigned long long) | ||
604 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); | ||
605 | |||
606 | /* | ||
607 | * Force reset on, also set rxdetect enable. Must do before reading | ||
608 | * serdesstatus at least for simulation, or some of the bits in | ||
609 | * serdes status will come back as undefined and cause simulation | ||
610 | * failures | ||
611 | */ | ||
612 | val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN | ||
613 | | INFINIPATH_SERDC0_L1PWR_DN; | ||
614 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); | ||
615 | /* be sure chip saw it */ | ||
616 | tmp = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | ||
617 | udelay(5); /* need pll reset set at least for a bit */ | ||
618 | /* | ||
619 | * after PLL is reset, set the per-lane Resets and TxIdle and | ||
620 | * clear the PLL reset and rxdetect (to get falling edge). | ||
621 | * Leave L1PWR bits set (permanently) | ||
622 | */ | ||
623 | val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL | ||
624 | | INFINIPATH_SERDC0_L1PWR_DN); | ||
625 | val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE; | ||
626 | ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets " | ||
627 | "and txidle (%llx)\n", (unsigned long long) val); | ||
628 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); | ||
629 | /* be sure chip saw it */ | ||
630 | tmp = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | ||
631 | /* need PLL reset clear for at least 11 usec before lane | ||
632 | * resets cleared; give it a few more to be sure */ | ||
633 | udelay(15); | ||
634 | val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE); | ||
635 | |||
636 | ipath_cdbg(VERBOSE, "Clearing lane resets and txidle " | ||
637 | "(writing %llx)\n", (unsigned long long) val); | ||
638 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); | ||
639 | /* be sure chip saw it */ | ||
640 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | ||
641 | |||
642 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); | ||
643 | if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) & | ||
644 | INFINIPATH_XGXS_MDIOADDR_MASK) != 3) { | ||
645 | val &= | ||
646 | ~(INFINIPATH_XGXS_MDIOADDR_MASK << | ||
647 | INFINIPATH_XGXS_MDIOADDR_SHIFT); | ||
648 | /* MDIO address 3 */ | ||
649 | val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT; | ||
650 | change = 1; | ||
651 | } | ||
652 | if (val & INFINIPATH_XGXS_RESET) { | ||
653 | val &= ~INFINIPATH_XGXS_RESET; | ||
654 | change = 1; | ||
655 | } | ||
656 | if (change) | ||
657 | ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val); | ||
658 | |||
659 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); | ||
660 | |||
661 | /* clear current and de-emphasis bits */ | ||
662 | config1 &= ~0x0ffffffff00ULL; | ||
663 | /* set current to 20ma */ | ||
664 | config1 |= 0x00000000000ULL; | ||
665 | /* set de-emphasis to -5.68dB */ | ||
666 | config1 |= 0x0cccc000000ULL; | ||
667 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1); | ||
668 | |||
669 | ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx " | ||
670 | "config1=%llx, sstatus=%llx xgxs=%llx\n", | ||
671 | (unsigned long long) val, (unsigned long long) config1, | ||
672 | (unsigned long long) | ||
673 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus), | ||
674 | (unsigned long long) | ||
675 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); | ||
676 | |||
677 | if (!ipath_waitfor_mdio_cmdready(dd)) { | ||
678 | ipath_write_kreg( | ||
679 | dd, dd->ipath_kregs->kr_mdio, | ||
680 | ipath_mdio_req(IPATH_MDIO_CMD_READ, 31, | ||
681 | IPATH_MDIO_CTRL_XGXS_REG_8, 0)); | ||
682 | if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio, | ||
683 | IPATH_MDIO_DATAVALID, &val)) | ||
684 | ipath_dbg("Never got MDIO data for XGXS " | ||
685 | "status read\n"); | ||
686 | else | ||
687 | ipath_cdbg(VERBOSE, "MDIO Read reg8, " | ||
688 | "'bank' 31 %x\n", (u32) val); | ||
689 | } else | ||
690 | ipath_dbg("Never got MDIO cmdready for XGXS status read\n"); | ||
691 | |||
692 | return ret; | ||
693 | } | ||
694 | |||
695 | /** | ||
696 | * ipath_pe_quiet_serdes - set serdes to txidle | ||
697 | * @dd: the infinipath device | ||
698 | * Called when driver is being unloaded | ||
699 | */ | ||
700 | static void ipath_pe_quiet_serdes(struct ipath_devdata *dd) | ||
701 | { | ||
702 | u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); | ||
703 | |||
704 | val |= INFINIPATH_SERDC0_TXIDLE; | ||
705 | ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n", | ||
706 | (unsigned long long) val); | ||
707 | ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); | ||
708 | } | ||
709 | |||
710 | /* this is not yet needed on this chip, so just return 0. */ | ||
711 | static int ipath_pe_intconfig(struct ipath_devdata *dd) | ||
712 | { | ||
713 | return 0; | ||
714 | } | ||
715 | |||
716 | /** | ||
717 | * ipath_setup_pe_setextled - set the state of the two external LEDs | ||
718 | * @dd: the infinipath device | ||
719 | * @lst: the L state | ||
720 | * @ltst: the LT state | ||
721 | |||
722 | * These LEDs indicate the physical and logical state of IB link. | ||
723 | * For this chip (at least with recommended board pinouts), LED1 | ||
724 | * is Yellow (logical state) and LED2 is Green (physical state), | ||
725 | * | ||
726 | * Note: We try to match the Mellanox HCA LED behavior as best | ||
727 | * we can. Green indicates physical link state is OK (something is | ||
728 | * plugged in, and we can train). | ||
729 | * Amber indicates the link is logically up (ACTIVE). | ||
730 | * Mellanox further blinks the amber LED to indicate data packet | ||
731 | * activity, but we have no hardware support for that, so it would | ||
732 | * require waking up every 10-20 msecs and checking the counters | ||
733 | * on the chip, and then turning the LED off if appropriate. That's | ||
734 | * visible overhead, so not something we will do. | ||
735 | * | ||
736 | */ | ||
737 | static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst, | ||
738 | u64 ltst) | ||
739 | { | ||
740 | u64 extctl; | ||
741 | |||
742 | /* the diags use the LED to indicate diag info, so we leave | ||
743 | * the external LED alone when the diags are running */ | ||
744 | if (ipath_diag_inuse) | ||
745 | return; | ||
746 | |||
747 | extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON | | ||
748 | INFINIPATH_EXTC_LED2PRIPORT_ON); | ||
749 | |||
750 | if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP) | ||
751 | extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON; | ||
752 | if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE) | ||
753 | extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON; | ||
754 | dd->ipath_extctrl = extctl; | ||
755 | ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl); | ||
756 | } | ||
757 | |||
758 | /** | ||
759 | * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff | ||
760 | * @dd: the infinipath device | ||
761 | * | ||
762 | * This is called during driver unload. | ||
763 | * We do the pci_disable_msi here, not in generic code, because it | ||
764 | * isn't used for the HT chips. If we do end up needing pci_enable_msi | ||
765 | * at some point in the future for HT, we'll move the call back | ||
766 | * into the main init_one code. | ||
767 | */ | ||
768 | static void ipath_setup_pe_cleanup(struct ipath_devdata *dd) | ||
769 | { | ||
770 | dd->ipath_msi_lo = 0; /* just in case unload fails */ | ||
771 | pci_disable_msi(dd->pcidev); | ||
772 | } | ||
773 | |||
774 | /** | ||
775 | * ipath_setup_pe_config - setup PCIe config related stuff | ||
776 | * @dd: the infinipath device | ||
777 | * @pdev: the PCI device | ||
778 | * | ||
779 | * The pci_enable_msi() call will fail on systems with MSI quirks | ||
780 | * such as those with AMD8131, even if the device of interest is not | ||
781 | * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed | ||
782 | * late in 2.6.16). | ||
783 | * All that can be done is to edit the kernel source to remove the quirk | ||
784 | * check until that is fixed. | ||
785 | * We do not need to call enable_msi() for our HyperTransport chip, | ||
786 | * even though it uses MSI, and we want to avoid the quirk warning, so | ||
787 | * So we call enable_msi only for PCIe. If we do end up needing | ||
788 | * pci_enable_msi at some point in the future for HT, we'll move the | ||
789 | * call back into the main init_one code. | ||
790 | * We save the msi lo and hi values, so we can restore them after | ||
791 | * chip reset (the kernel PCI infrastructure doesn't yet handle that | ||
792 | * correctly). | ||
793 | */ | ||
794 | static int ipath_setup_pe_config(struct ipath_devdata *dd, | ||
795 | struct pci_dev *pdev) | ||
796 | { | ||
797 | int pos, ret; | ||
798 | |||
799 | dd->ipath_msi_lo = 0; /* used as a flag during reset processing */ | ||
800 | ret = pci_enable_msi(dd->pcidev); | ||
801 | if (ret) | ||
802 | ipath_dev_err(dd, "pci_enable_msi failed: %d, " | ||
803 | "interrupts may not work\n", ret); | ||
804 | /* continue even if it fails, we may still be OK... */ | ||
805 | |||
806 | if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) { | ||
807 | u16 control; | ||
808 | pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, | ||
809 | &dd->ipath_msi_lo); | ||
810 | pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, | ||
811 | &dd->ipath_msi_hi); | ||
812 | pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, | ||
813 | &control); | ||
814 | /* now save the data (vector) info */ | ||
815 | pci_read_config_word(dd->pcidev, | ||
816 | pos + ((control & PCI_MSI_FLAGS_64BIT) | ||
817 | ? 12 : 8), | ||
818 | &dd->ipath_msi_data); | ||
819 | ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset " | ||
820 | "0x%x, control=0x%x\n", dd->ipath_msi_data, | ||
821 | pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), | ||
822 | control); | ||
823 | /* we save the cachelinesize also, although it doesn't | ||
824 | * really matter */ | ||
825 | pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, | ||
826 | &dd->ipath_pci_cacheline); | ||
827 | } else | ||
828 | ipath_dev_err(dd, "Can't find MSI capability, " | ||
829 | "can't save MSI settings for reset\n"); | ||
830 | if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) { | ||
831 | u16 linkstat; | ||
832 | pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA, | ||
833 | &linkstat); | ||
834 | linkstat >>= 4; | ||
835 | linkstat &= 0x1f; | ||
836 | if (linkstat != 8) | ||
837 | ipath_dev_err(dd, "PCIe width %u, " | ||
838 | "performance reduced\n", linkstat); | ||
839 | } | ||
840 | else | ||
841 | ipath_dev_err(dd, "Can't find PCI Express " | ||
842 | "capability!\n"); | ||
843 | return 0; | ||
844 | } | ||
845 | |||
846 | static void ipath_init_pe_variables(void) | ||
847 | { | ||
848 | /* | ||
849 | * bits for selecting i2c direction and values, | ||
850 | * used for I2C serial flash | ||
851 | */ | ||
852 | ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM; | ||
853 | ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM; | ||
854 | ipath_gpio_sda = IPATH_GPIO_SDA; | ||
855 | ipath_gpio_scl = IPATH_GPIO_SCL; | ||
856 | |||
857 | /* variables for sanity checking interrupt and errors */ | ||
858 | infinipath_hwe_bitsextant = | ||
859 | (INFINIPATH_HWE_RXEMEMPARITYERR_MASK << | ||
860 | INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) | | ||
861 | (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK << | ||
862 | INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) | | ||
863 | INFINIPATH_HWE_PCIE1PLLFAILED | | ||
864 | INFINIPATH_HWE_PCIE0PLLFAILED | | ||
865 | INFINIPATH_HWE_PCIEPOISONEDTLP | | ||
866 | INFINIPATH_HWE_PCIECPLTIMEOUT | | ||
867 | INFINIPATH_HWE_PCIEBUSPARITYXTLH | | ||
868 | INFINIPATH_HWE_PCIEBUSPARITYXADM | | ||
869 | INFINIPATH_HWE_PCIEBUSPARITYRADM | | ||
870 | INFINIPATH_HWE_MEMBISTFAILED | | ||
871 | INFINIPATH_HWE_COREPLL_FBSLIP | | ||
872 | INFINIPATH_HWE_COREPLL_RFSLIP | | ||
873 | INFINIPATH_HWE_SERDESPLLFAILED | | ||
874 | INFINIPATH_HWE_IBCBUSTOSPCPARITYERR | | ||
875 | INFINIPATH_HWE_IBCBUSFRSPCPARITYERR; | ||
876 | infinipath_i_bitsextant = | ||
877 | (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) | | ||
878 | (INFINIPATH_I_RCVAVAIL_MASK << | ||
879 | INFINIPATH_I_RCVAVAIL_SHIFT) | | ||
880 | INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT | | ||
881 | INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO; | ||
882 | infinipath_e_bitsextant = | ||
883 | INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC | | ||
884 | INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN | | ||
885 | INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN | | ||
886 | INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR | | ||
887 | INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP | | ||
888 | INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION | | ||
889 | INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL | | ||
890 | INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN | | ||
891 | INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK | | ||
892 | INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN | | ||
893 | INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN | | ||
894 | INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT | | ||
895 | INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | | ||
896 | INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED | | ||
897 | INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET | | ||
898 | INFINIPATH_E_HARDWARE; | ||
899 | |||
900 | infinipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK; | ||
901 | infinipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK; | ||
902 | } | ||
903 | |||
904 | /* setup the MSI stuff again after a reset. I'd like to just call | ||
905 | * pci_enable_msi() and request_irq() again, but when I do that, | ||
906 | * the MSI enable bit doesn't get set in the command word, and | ||
907 | * we switch to to a different interrupt vector, which is confusing, | ||
908 | * so I instead just do it all inline. Perhaps somehow can tie this | ||
909 | * into the PCIe hotplug support at some point | ||
910 | * Note, because I'm doing it all here, I don't call pci_disable_msi() | ||
911 | * or free_irq() at the start of ipath_setup_pe_reset(). | ||
912 | */ | ||
913 | static int ipath_reinit_msi(struct ipath_devdata *dd) | ||
914 | { | ||
915 | int pos; | ||
916 | u16 control; | ||
917 | int ret; | ||
918 | |||
919 | if (!dd->ipath_msi_lo) { | ||
920 | dev_info(&dd->pcidev->dev, "Can't restore MSI config, " | ||
921 | "initial setup failed?\n"); | ||
922 | ret = 0; | ||
923 | goto bail; | ||
924 | } | ||
925 | |||
926 | if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) { | ||
927 | ipath_dev_err(dd, "Can't find MSI capability, " | ||
928 | "can't restore MSI settings\n"); | ||
929 | ret = 0; | ||
930 | goto bail; | ||
931 | } | ||
932 | ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n", | ||
933 | dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO); | ||
934 | pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, | ||
935 | dd->ipath_msi_lo); | ||
936 | ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n", | ||
937 | dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI); | ||
938 | pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, | ||
939 | dd->ipath_msi_hi); | ||
940 | pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); | ||
941 | if (!(control & PCI_MSI_FLAGS_ENABLE)) { | ||
942 | ipath_cdbg(VERBOSE, "MSI control at off %x was %x, " | ||
943 | "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS, | ||
944 | control, control | PCI_MSI_FLAGS_ENABLE); | ||
945 | control |= PCI_MSI_FLAGS_ENABLE; | ||
946 | pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, | ||
947 | control); | ||
948 | } | ||
949 | /* now rewrite the data (vector) info */ | ||
950 | pci_write_config_word(dd->pcidev, pos + | ||
951 | ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), | ||
952 | dd->ipath_msi_data); | ||
953 | /* we restore the cachelinesize also, although it doesn't really | ||
954 | * matter */ | ||
955 | pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, | ||
956 | dd->ipath_pci_cacheline); | ||
957 | /* and now set the pci master bit again */ | ||
958 | pci_set_master(dd->pcidev); | ||
959 | ret = 1; | ||
960 | |||
961 | bail: | ||
962 | return ret; | ||
963 | } | ||
964 | |||
965 | /* This routine sleeps, so it can only be called from user context, not | ||
966 | * from interrupt context. If we need interrupt context, we can split | ||
967 | * it into two routines. | ||
968 | */ | ||
969 | static int ipath_setup_pe_reset(struct ipath_devdata *dd) | ||
970 | { | ||
971 | u64 val; | ||
972 | int i; | ||
973 | int ret; | ||
974 | |||
975 | /* Use ERROR so it shows up in logs, etc. */ | ||
976 | ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit); | ||
977 | /* keep chip from being accessed in a few places */ | ||
978 | dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT); | ||
979 | val = dd->ipath_control | INFINIPATH_C_RESET; | ||
980 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val); | ||
981 | mb(); | ||
982 | |||
983 | for (i = 1; i <= 5; i++) { | ||
984 | int r; | ||
985 | /* allow MBIST, etc. to complete; longer on each retry. | ||
986 | * We sometimes get machine checks from bus timeout if no | ||
987 | * response, so for now, make it *really* long. | ||
988 | */ | ||
989 | msleep(1000 + (1 + i) * 2000); | ||
990 | if ((r = | ||
991 | pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, | ||
992 | dd->ipath_pcibar0))) | ||
993 | ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n", | ||
994 | r); | ||
995 | if ((r = | ||
996 | pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, | ||
997 | dd->ipath_pcibar1))) | ||
998 | ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n", | ||
999 | r); | ||
1000 | /* now re-enable memory access */ | ||
1001 | if ((r = pci_enable_device(dd->pcidev))) | ||
1002 | ipath_dev_err(dd, "pci_enable_device failed after " | ||
1003 | "reset: %d\n", r); | ||
1004 | /* whether it worked or not, mark as present, again */ | ||
1005 | dd->ipath_flags |= IPATH_PRESENT; | ||
1006 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision); | ||
1007 | if (val == dd->ipath_revision) { | ||
1008 | ipath_cdbg(VERBOSE, "Got matching revision " | ||
1009 | "register %llx on try %d\n", | ||
1010 | (unsigned long long) val, i); | ||
1011 | ret = ipath_reinit_msi(dd); | ||
1012 | goto bail; | ||
1013 | } | ||
1014 | /* Probably getting -1 back */ | ||
1015 | ipath_dbg("Didn't get expected revision register, " | ||
1016 | "got %llx, try %d\n", (unsigned long long) val, | ||
1017 | i + 1); | ||
1018 | } | ||
1019 | ret = 0; /* failed */ | ||
1020 | |||
1021 | bail: | ||
1022 | return ret; | ||
1023 | } | ||
1024 | |||
1025 | /** | ||
1026 | * ipath_pe_put_tid - write a TID in chip | ||
1027 | * @dd: the infinipath device | ||
1028 | * @tidptr: pointer to the expected TID (in chip) to udpate | ||
1029 | * @tidtype: 0 for eager, 1 for expected | ||
1030 | * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing | ||
1031 | * | ||
1032 | * This exists as a separate routine to allow for special locking etc. | ||
1033 | * It's used for both the full cleanup on exit, as well as the normal | ||
1034 | * setup and teardown. | ||
1035 | */ | ||
1036 | static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr, | ||
1037 | u32 type, unsigned long pa) | ||
1038 | { | ||
1039 | u32 __iomem *tidp32 = (u32 __iomem *)tidptr; | ||
1040 | unsigned long flags = 0; /* keep gcc quiet */ | ||
1041 | |||
1042 | if (pa != dd->ipath_tidinvalid) { | ||
1043 | if (pa & ((1U << 11) - 1)) { | ||
1044 | dev_info(&dd->pcidev->dev, "BUG: physaddr %lx " | ||
1045 | "not 4KB aligned!\n", pa); | ||
1046 | return; | ||
1047 | } | ||
1048 | pa >>= 11; | ||
1049 | /* paranoia check */ | ||
1050 | if (pa & (7<<29)) | ||
1051 | ipath_dev_err(dd, | ||
1052 | "BUG: Physical page address 0x%lx " | ||
1053 | "has bits set in 31-29\n", pa); | ||
1054 | |||
1055 | if (type == 0) | ||
1056 | pa |= dd->ipath_tidtemplate; | ||
1057 | else /* for now, always full 4KB page */ | ||
1058 | pa |= 2 << 29; | ||
1059 | } | ||
1060 | |||
1061 | /* workaround chip bug 9437 by writing each TID twice | ||
1062 | * and holding a spinlock around the writes, so they don't | ||
1063 | * intermix with other TID (eager or expected) writes | ||
1064 | * Unfortunately, this call can be done from interrupt level | ||
1065 | * for the port 0 eager TIDs, so we have to use irqsave | ||
1066 | */ | ||
1067 | spin_lock_irqsave(&dd->ipath_tid_lock, flags); | ||
1068 | ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf); | ||
1069 | if (dd->ipath_kregbase) | ||
1070 | writel(pa, tidp32); | ||
1071 | ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef); | ||
1072 | mmiowb(); | ||
1073 | spin_unlock_irqrestore(&dd->ipath_tid_lock, flags); | ||
1074 | } | ||
1075 | |||
1076 | /** | ||
1077 | * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager | ||
1078 | * @dd: the infinipath device | ||
1079 | * @port: the port | ||
1080 | * | ||
1081 | * clear all TID entries for a port, expected and eager. | ||
1082 | * Used from ipath_close(). On this chip, TIDs are only 32 bits, | ||
1083 | * not 64, but they are still on 64 bit boundaries, so tidbase | ||
1084 | * is declared as u64 * for the pointer math, even though we write 32 bits | ||
1085 | */ | ||
1086 | static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port) | ||
1087 | { | ||
1088 | u64 __iomem *tidbase; | ||
1089 | unsigned long tidinv; | ||
1090 | int i; | ||
1091 | |||
1092 | if (!dd->ipath_kregbase) | ||
1093 | return; | ||
1094 | |||
1095 | ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port); | ||
1096 | |||
1097 | tidinv = dd->ipath_tidinvalid; | ||
1098 | tidbase = (u64 __iomem *) | ||
1099 | ((char __iomem *)(dd->ipath_kregbase) + | ||
1100 | dd->ipath_rcvtidbase + | ||
1101 | port * dd->ipath_rcvtidcnt * sizeof(*tidbase)); | ||
1102 | |||
1103 | for (i = 0; i < dd->ipath_rcvtidcnt; i++) | ||
1104 | ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv); | ||
1105 | |||
1106 | tidbase = (u64 __iomem *) | ||
1107 | ((char __iomem *)(dd->ipath_kregbase) + | ||
1108 | dd->ipath_rcvegrbase + | ||
1109 | port * dd->ipath_rcvegrcnt * sizeof(*tidbase)); | ||
1110 | |||
1111 | for (i = 0; i < dd->ipath_rcvegrcnt; i++) | ||
1112 | ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv); | ||
1113 | } | ||
1114 | |||
1115 | /** | ||
1116 | * ipath_pe_tidtemplate - setup constants for TID updates | ||
1117 | * @dd: the infinipath device | ||
1118 | * | ||
1119 | * We setup stuff that we use a lot, to avoid calculating each time | ||
1120 | */ | ||
1121 | static void ipath_pe_tidtemplate(struct ipath_devdata *dd) | ||
1122 | { | ||
1123 | u32 egrsize = dd->ipath_rcvegrbufsize; | ||
1124 | |||
1125 | /* For now, we always allocate 4KB buffers (at init) so we can | ||
1126 | * receive max size packets. We may want a module parameter to | ||
1127 | * specify 2KB or 4KB and/or make be per port instead of per device | ||
1128 | * for those who want to reduce memory footprint. Note that the | ||
1129 | * ipath_rcvhdrentsize size must be large enough to hold the largest | ||
1130 | * IB header (currently 96 bytes) that we expect to handle (plus of | ||
1131 | * course the 2 dwords of RHF). | ||
1132 | */ | ||
1133 | if (egrsize == 2048) | ||
1134 | dd->ipath_tidtemplate = 1U << 29; | ||
1135 | else if (egrsize == 4096) | ||
1136 | dd->ipath_tidtemplate = 2U << 29; | ||
1137 | else { | ||
1138 | egrsize = 4096; | ||
1139 | dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize " | ||
1140 | "%u, using %u\n", dd->ipath_rcvegrbufsize, | ||
1141 | egrsize); | ||
1142 | dd->ipath_tidtemplate = 2U << 29; | ||
1143 | } | ||
1144 | dd->ipath_tidinvalid = 0; | ||
1145 | } | ||
1146 | |||
1147 | static int ipath_pe_early_init(struct ipath_devdata *dd) | ||
1148 | { | ||
1149 | dd->ipath_flags |= IPATH_4BYTE_TID; | ||
1150 | |||
1151 | /* | ||
1152 | * For openfabrics, we need to be able to handle an IB header of | ||
1153 | * 24 dwords. HT chip has arbitrary sized receive buffers, so we | ||
1154 | * made them the same size as the PIO buffers. This chip does not | ||
1155 | * handle arbitrary size buffers, so we need the header large enough | ||
1156 | * to handle largest IB header, but still have room for a 2KB MTU | ||
1157 | * standard IB packet. | ||
1158 | */ | ||
1159 | dd->ipath_rcvhdrentsize = 24; | ||
1160 | dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE; | ||
1161 | |||
1162 | /* | ||
1163 | * To truly support a 4KB MTU (for usermode), we need to | ||
1164 | * bump this to a larger value. For now, we use them for | ||
1165 | * the kernel only. | ||
1166 | */ | ||
1167 | dd->ipath_rcvegrbufsize = 2048; | ||
1168 | /* | ||
1169 | * the min() check here is currently a nop, but it may not always | ||
1170 | * be, depending on just how we do ipath_rcvegrbufsize | ||
1171 | */ | ||
1172 | dd->ipath_ibmaxlen = min(dd->ipath_piosize2k, | ||
1173 | dd->ipath_rcvegrbufsize + | ||
1174 | (dd->ipath_rcvhdrentsize << 2)); | ||
1175 | dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen; | ||
1176 | |||
1177 | /* | ||
1178 | * We can request a receive interrupt for 1 or | ||
1179 | * more packets from current offset. For now, we set this | ||
1180 | * up for a single packet. | ||
1181 | */ | ||
1182 | dd->ipath_rhdrhead_intr_off = 1ULL<<32; | ||
1183 | |||
1184 | ipath_get_eeprom_info(dd); | ||
1185 | |||
1186 | return 0; | ||
1187 | } | ||
1188 | |||
1189 | int __attribute__((weak)) ipath_unordered_wc(void) | ||
1190 | { | ||
1191 | return 0; | ||
1192 | } | ||
1193 | |||
1194 | /** | ||
1195 | * ipath_init_pe_get_base_info - set chip-specific flags for user code | ||
1196 | * @dd: the infinipath device | ||
1197 | * @kbase: ipath_base_info pointer | ||
1198 | * | ||
1199 | * We set the PCIE flag because the lower bandwidth on PCIe vs | ||
1200 | * HyperTransport can affect some user packet algorithims. | ||
1201 | */ | ||
1202 | static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase) | ||
1203 | { | ||
1204 | struct ipath_base_info *kinfo = kbase; | ||
1205 | |||
1206 | if (ipath_unordered_wc()) { | ||
1207 | kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER; | ||
1208 | ipath_cdbg(PROC, "Intel processor, forcing WC order\n"); | ||
1209 | } | ||
1210 | else | ||
1211 | ipath_cdbg(PROC, "Not Intel processor, WC ordered\n"); | ||
1212 | |||
1213 | kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE; | ||
1214 | |||
1215 | return 0; | ||
1216 | } | ||
1217 | |||
1218 | /** | ||
1219 | * ipath_init_iba6120_funcs - set up the chip-specific function pointers | ||
1220 | * @dd: the infinipath device | ||
1221 | * | ||
1222 | * This is global, and is called directly at init to set up the | ||
1223 | * chip-specific function pointers for later use. | ||
1224 | */ | ||
1225 | void ipath_init_iba6120_funcs(struct ipath_devdata *dd) | ||
1226 | { | ||
1227 | dd->ipath_f_intrsetup = ipath_pe_intconfig; | ||
1228 | dd->ipath_f_bus = ipath_setup_pe_config; | ||
1229 | dd->ipath_f_reset = ipath_setup_pe_reset; | ||
1230 | dd->ipath_f_get_boardname = ipath_pe_boardname; | ||
1231 | dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors; | ||
1232 | dd->ipath_f_early_init = ipath_pe_early_init; | ||
1233 | dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors; | ||
1234 | dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes; | ||
1235 | dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes; | ||
1236 | dd->ipath_f_clear_tids = ipath_pe_clear_tids; | ||
1237 | dd->ipath_f_put_tid = ipath_pe_put_tid; | ||
1238 | dd->ipath_f_cleanup = ipath_setup_pe_cleanup; | ||
1239 | dd->ipath_f_setextled = ipath_setup_pe_setextled; | ||
1240 | dd->ipath_f_get_base_info = ipath_pe_get_base_info; | ||
1241 | |||
1242 | /* initialize chip-specific variables */ | ||
1243 | dd->ipath_f_tidtemplate = ipath_pe_tidtemplate; | ||
1244 | |||
1245 | /* | ||
1246 | * setup the register offsets, since they are different for each | ||
1247 | * chip | ||
1248 | */ | ||
1249 | dd->ipath_kregs = &ipath_pe_kregs; | ||
1250 | dd->ipath_cregs = &ipath_pe_cregs; | ||
1251 | |||
1252 | ipath_init_pe_variables(); | ||
1253 | } | ||
1254 | |||