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Diffstat (limited to 'drivers/infiniband/hw/ipath/ipath_iba6120.c')
-rw-r--r--drivers/infiniband/hw/ipath/ipath_iba6120.c1264
1 files changed, 1264 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6120.c b/drivers/infiniband/hw/ipath/ipath_iba6120.c
new file mode 100644
index 000000000000..d86516d23df6
--- /dev/null
+++ b/drivers/infiniband/hw/ipath/ipath_iba6120.c
@@ -0,0 +1,1264 @@
1/*
2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the
35 * InfiniPath PCIe chip.
36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41
42
43#include "ipath_kernel.h"
44#include "ipath_registers.h"
45
46/*
47 * This file contains all the chip-specific register information and
48 * access functions for the QLogic InfiniPath PCI-Express chip.
49 *
50 * This lists the InfiniPath registers, in the actual chip layout.
51 * This structure should never be directly accessed.
52 */
53struct _infinipath_do_not_use_kernel_regs {
54 unsigned long long Revision;
55 unsigned long long Control;
56 unsigned long long PageAlign;
57 unsigned long long PortCnt;
58 unsigned long long DebugPortSelect;
59 unsigned long long Reserved0;
60 unsigned long long SendRegBase;
61 unsigned long long UserRegBase;
62 unsigned long long CounterRegBase;
63 unsigned long long Scratch;
64 unsigned long long Reserved1;
65 unsigned long long Reserved2;
66 unsigned long long IntBlocked;
67 unsigned long long IntMask;
68 unsigned long long IntStatus;
69 unsigned long long IntClear;
70 unsigned long long ErrorMask;
71 unsigned long long ErrorStatus;
72 unsigned long long ErrorClear;
73 unsigned long long HwErrMask;
74 unsigned long long HwErrStatus;
75 unsigned long long HwErrClear;
76 unsigned long long HwDiagCtrl;
77 unsigned long long MDIO;
78 unsigned long long IBCStatus;
79 unsigned long long IBCCtrl;
80 unsigned long long ExtStatus;
81 unsigned long long ExtCtrl;
82 unsigned long long GPIOOut;
83 unsigned long long GPIOMask;
84 unsigned long long GPIOStatus;
85 unsigned long long GPIOClear;
86 unsigned long long RcvCtrl;
87 unsigned long long RcvBTHQP;
88 unsigned long long RcvHdrSize;
89 unsigned long long RcvHdrCnt;
90 unsigned long long RcvHdrEntSize;
91 unsigned long long RcvTIDBase;
92 unsigned long long RcvTIDCnt;
93 unsigned long long RcvEgrBase;
94 unsigned long long RcvEgrCnt;
95 unsigned long long RcvBufBase;
96 unsigned long long RcvBufSize;
97 unsigned long long RxIntMemBase;
98 unsigned long long RxIntMemSize;
99 unsigned long long RcvPartitionKey;
100 unsigned long long Reserved3;
101 unsigned long long RcvPktLEDCnt;
102 unsigned long long Reserved4[8];
103 unsigned long long SendCtrl;
104 unsigned long long SendPIOBufBase;
105 unsigned long long SendPIOSize;
106 unsigned long long SendPIOBufCnt;
107 unsigned long long SendPIOAvailAddr;
108 unsigned long long TxIntMemBase;
109 unsigned long long TxIntMemSize;
110 unsigned long long Reserved5;
111 unsigned long long PCIeRBufTestReg0;
112 unsigned long long PCIeRBufTestReg1;
113 unsigned long long Reserved51[6];
114 unsigned long long SendBufferError;
115 unsigned long long SendBufferErrorCONT1;
116 unsigned long long Reserved6SBE[6];
117 unsigned long long RcvHdrAddr0;
118 unsigned long long RcvHdrAddr1;
119 unsigned long long RcvHdrAddr2;
120 unsigned long long RcvHdrAddr3;
121 unsigned long long RcvHdrAddr4;
122 unsigned long long Reserved7RHA[11];
123 unsigned long long RcvHdrTailAddr0;
124 unsigned long long RcvHdrTailAddr1;
125 unsigned long long RcvHdrTailAddr2;
126 unsigned long long RcvHdrTailAddr3;
127 unsigned long long RcvHdrTailAddr4;
128 unsigned long long Reserved8RHTA[11];
129 unsigned long long Reserved9SW[8];
130 unsigned long long SerdesConfig0;
131 unsigned long long SerdesConfig1;
132 unsigned long long SerdesStatus;
133 unsigned long long XGXSConfig;
134 unsigned long long IBPLLCfg;
135 unsigned long long Reserved10SW2[3];
136 unsigned long long PCIEQ0SerdesConfig0;
137 unsigned long long PCIEQ0SerdesConfig1;
138 unsigned long long PCIEQ0SerdesStatus;
139 unsigned long long Reserved11;
140 unsigned long long PCIEQ1SerdesConfig0;
141 unsigned long long PCIEQ1SerdesConfig1;
142 unsigned long long PCIEQ1SerdesStatus;
143 unsigned long long Reserved12;
144};
145
146#define IPATH_KREG_OFFSET(field) (offsetof(struct \
147 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
148#define IPATH_CREG_OFFSET(field) (offsetof( \
149 struct infinipath_counters, field) / sizeof(u64))
150
151static const struct ipath_kregs ipath_pe_kregs = {
152 .kr_control = IPATH_KREG_OFFSET(Control),
153 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
154 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
155 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
156 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
157 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
158 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
159 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
160 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
161 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
162 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
163 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
164 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
165 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
166 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
167 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
168 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
169 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
170 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
171 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
172 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
173 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
174 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
175 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
176 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
177 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
178 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
179 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
180 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
181 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
182 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
183 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
184 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
185 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
186 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
187 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
188 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
189 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
190 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
191 .kr_revision = IPATH_KREG_OFFSET(Revision),
192 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
193 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
194 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
195 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
196 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
197 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
198 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
199 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
200 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
201 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
202 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
203 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
204 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
205 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
206 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
207 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
208
209 /*
210 * These should not be used directly via ipath_read_kreg64(),
211 * use them with ipath_read_kreg64_port()
212 */
213 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
214 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
215
216 /* The rcvpktled register controls one of the debug port signals, so
217 * a packet activity LED can be connected to it. */
218 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
219 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
220 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
221 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
222 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
223 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
224 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
225 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
226 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
227};
228
229static const struct ipath_cregs ipath_pe_cregs = {
230 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
231 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
232 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
233 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
234 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
235 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
236 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
237 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
238 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
239 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
240 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
241 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
242 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
243 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
244 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
245 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
246 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
247 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
248 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
249 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
250 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
251 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
252 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
253 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
254 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
255 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
256 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
257 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
258 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
259 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
260 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
261 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
262 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
263};
264
265/* kr_intstatus, kr_intclear, kr_intmask bits */
266#define INFINIPATH_I_RCVURG_MASK 0x1F
267#define INFINIPATH_I_RCVAVAIL_MASK 0x1F
268
269/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
270#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
271#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
272#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
273#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
274#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
275#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
276#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
277#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
278#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
279#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
280#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
281#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
282
283/* kr_extstatus bits */
284#define INFINIPATH_EXTS_FREQSEL 0x2
285#define INFINIPATH_EXTS_SERDESSEL 0x4
286#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
287#define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
288
289#define _IPATH_GPIO_SDA_NUM 1
290#define _IPATH_GPIO_SCL_NUM 0
291
292#define IPATH_GPIO_SDA (1ULL << \
293 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
294#define IPATH_GPIO_SCL (1ULL << \
295 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
296
297/**
298 * ipath_pe_handle_hwerrors - display hardware errors.
299 * @dd: the infinipath device
300 * @msg: the output buffer
301 * @msgl: the size of the output buffer
302 *
303 * Use same msg buffer as regular errors to avoid excessive stack
304 * use. Most hardware errors are catastrophic, but for right now,
305 * we'll print them and continue. We reuse the same message buffer as
306 * ipath_handle_errors() to avoid excessive stack usage.
307 */
308static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
309 size_t msgl)
310{
311 ipath_err_t hwerrs;
312 u32 bits, ctrl;
313 int isfatal = 0;
314 char bitsmsg[64];
315
316 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
317 if (!hwerrs) {
318 /*
319 * better than printing cofusing messages
320 * This seems to be related to clearing the crc error, or
321 * the pll error during init.
322 */
323 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
324 return;
325 } else if (hwerrs == ~0ULL) {
326 ipath_dev_err(dd, "Read of hardware error status failed "
327 "(all bits set); ignoring\n");
328 return;
329 }
330 ipath_stats.sps_hwerrs++;
331
332 /* Always clear the error status register, except MEMBISTFAIL,
333 * regardless of whether we continue or stop using the chip.
334 * We want that set so we know it failed, even across driver reload.
335 * We'll still ignore it in the hwerrmask. We do this partly for
336 * diagnostics, but also for support */
337 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
338 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
339
340 hwerrs &= dd->ipath_hwerrmask;
341
342 /*
343 * make sure we get this much out, unless told to be quiet,
344 * or it's occurred within the last 5 seconds
345 */
346 if ((hwerrs & ~dd->ipath_lasthwerror) ||
347 (ipath_debug & __IPATH_VERBDBG))
348 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
349 "(cleared)\n", (unsigned long long) hwerrs);
350 dd->ipath_lasthwerror |= hwerrs;
351
352 if (hwerrs & ~infinipath_hwe_bitsextant)
353 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
354 "%llx set\n", (unsigned long long)
355 (hwerrs & ~infinipath_hwe_bitsextant));
356
357 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
358 if (ctrl & INFINIPATH_C_FREEZEMODE) {
359 if (hwerrs) {
360 /*
361 * if any set that we aren't ignoring only make the
362 * complaint once, in case it's stuck or recurring,
363 * and we get here multiple times
364 */
365 if (dd->ipath_flags & IPATH_INITTED) {
366 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
367 "mode), no longer usable, SN %.16s\n",
368 dd->ipath_serial);
369 isfatal = 1;
370 }
371 /*
372 * Mark as having had an error for driver, and also
373 * for /sys and status word mapped to user programs.
374 * This marks unit as not usable, until reset
375 */
376 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
377 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
378 dd->ipath_flags &= ~IPATH_INITTED;
379 } else {
380 ipath_dbg("Clearing freezemode on ignored hardware "
381 "error\n");
382 ctrl &= ~INFINIPATH_C_FREEZEMODE;
383 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
384 ctrl);
385 }
386 }
387
388 *msg = '\0';
389
390 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
391 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
392 msgl);
393 /* ignore from now on, so disable until driver reloaded */
394 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
395 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
396 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
397 dd->ipath_hwerrmask);
398 }
399 if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK
400 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) {
401 bits = (u32) ((hwerrs >>
402 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) &
403 INFINIPATH_HWE_RXEMEMPARITYERR_MASK);
404 snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ",
405 bits);
406 strlcat(msg, bitsmsg, msgl);
407 }
408 if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
409 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
410 bits = (u32) ((hwerrs >>
411 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
412 INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
413 snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
414 bits);
415 strlcat(msg, bitsmsg, msgl);
416 }
417 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
418 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
419 bits = (u32) ((hwerrs >>
420 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
421 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
422 snprintf(bitsmsg, sizeof bitsmsg,
423 "[PCIe Mem Parity Errs %x] ", bits);
424 strlcat(msg, bitsmsg, msgl);
425 }
426 if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
427 strlcat(msg, "[IB2IPATH Parity]", msgl);
428 if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
429 strlcat(msg, "[IPATH2IB Parity]", msgl);
430
431#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
432 INFINIPATH_HWE_COREPLL_RFSLIP )
433
434 if (hwerrs & _IPATH_PLL_FAIL) {
435 snprintf(bitsmsg, sizeof bitsmsg,
436 "[PLL failed (%llx), InfiniPath hardware unusable]",
437 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
438 strlcat(msg, bitsmsg, msgl);
439 /* ignore from now on, so disable until driver reloaded */
440 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
441 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
442 dd->ipath_hwerrmask);
443 }
444
445 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
446 /*
447 * If it occurs, it is left masked since the eternal
448 * interface is unused
449 */
450 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
451 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
452 dd->ipath_hwerrmask);
453 }
454
455 if (hwerrs & INFINIPATH_HWE_PCIEPOISONEDTLP)
456 strlcat(msg, "[PCIe Poisoned TLP]", msgl);
457 if (hwerrs & INFINIPATH_HWE_PCIECPLTIMEOUT)
458 strlcat(msg, "[PCIe completion timeout]", msgl);
459
460 /*
461 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
462 * parity or memory parity error failures, because most likely we
463 * won't be able to talk to the core of the chip. Nonetheless, we
464 * might see them, if they are in parts of the PCIe core that aren't
465 * essential.
466 */
467 if (hwerrs & INFINIPATH_HWE_PCIE1PLLFAILED)
468 strlcat(msg, "[PCIePLL1]", msgl);
469 if (hwerrs & INFINIPATH_HWE_PCIE0PLLFAILED)
470 strlcat(msg, "[PCIePLL0]", msgl);
471 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXTLH)
472 strlcat(msg, "[PCIe XTLH core parity]", msgl);
473 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXADM)
474 strlcat(msg, "[PCIe ADM TX core parity]", msgl);
475 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYRADM)
476 strlcat(msg, "[PCIe ADM RX core parity]", msgl);
477
478 if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
479 strlcat(msg, "[Rx Dsync]", msgl);
480 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
481 strlcat(msg, "[SerDes PLL]", msgl);
482
483 ipath_dev_err(dd, "%s hardware error\n", msg);
484 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
485 /*
486 * for /sys status file ; if no trailing } is copied, we'll
487 * know it was truncated.
488 */
489 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
490 "{%s}", msg);
491 }
492}
493
494/**
495 * ipath_pe_boardname - fill in the board name
496 * @dd: the infinipath device
497 * @name: the output buffer
498 * @namelen: the size of the output buffer
499 *
500 * info is based on the board revision register
501 */
502static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
503 size_t namelen)
504{
505 char *n = NULL;
506 u8 boardrev = dd->ipath_boardrev;
507 int ret;
508
509 switch (boardrev) {
510 case 0:
511 n = "InfiniPath_Emulation";
512 break;
513 case 1:
514 n = "InfiniPath_QLE7140-Bringup";
515 break;
516 case 2:
517 n = "InfiniPath_QLE7140";
518 break;
519 case 3:
520 n = "InfiniPath_QMI7140";
521 break;
522 case 4:
523 n = "InfiniPath_QEM7140";
524 break;
525 case 5:
526 n = "InfiniPath_QMH7140";
527 break;
528 default:
529 ipath_dev_err(dd,
530 "Don't yet know about board with ID %u\n",
531 boardrev);
532 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
533 boardrev);
534 break;
535 }
536 if (n)
537 snprintf(name, namelen, "%s", n);
538
539 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
540 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
541 dd->ipath_majrev, dd->ipath_minrev);
542 ret = 1;
543 } else
544 ret = 0;
545
546 return ret;
547}
548
549/**
550 * ipath_pe_init_hwerrors - enable hardware errors
551 * @dd: the infinipath device
552 *
553 * now that we have finished initializing everything that might reasonably
554 * cause a hardware error, and cleared those errors bits as they occur,
555 * we can enable hardware errors in the mask (potentially enabling
556 * freeze mode), and enable hardware errors as errors (along with
557 * everything else) in errormask
558 */
559static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
560{
561 ipath_err_t val;
562 u64 extsval;
563
564 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
565
566 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
567 ipath_dev_err(dd, "MemBIST did not complete!\n");
568
569 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
570
571 if (!dd->ipath_boardrev) // no PLL for Emulator
572 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
573
574 /* workaround bug 9460 in internal interface bus parity checking */
575 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
576
577 dd->ipath_hwerrmask = val;
578}
579
580/**
581 * ipath_pe_bringup_serdes - bring up the serdes
582 * @dd: the infinipath device
583 */
584static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
585{
586 u64 val, tmp, config1;
587 int ret = 0, change = 0;
588
589 ipath_dbg("Trying to bringup serdes\n");
590
591 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
592 INFINIPATH_HWE_SERDESPLLFAILED) {
593 ipath_dbg("At start, serdes PLL failed bit set "
594 "in hwerrstatus, clearing and continuing\n");
595 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
596 INFINIPATH_HWE_SERDESPLLFAILED);
597 }
598
599 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
600 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
601
602 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
603 "xgxsconfig %llx\n", (unsigned long long) val,
604 (unsigned long long) config1, (unsigned long long)
605 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
606
607 /*
608 * Force reset on, also set rxdetect enable. Must do before reading
609 * serdesstatus at least for simulation, or some of the bits in
610 * serdes status will come back as undefined and cause simulation
611 * failures
612 */
613 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
614 | INFINIPATH_SERDC0_L1PWR_DN;
615 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
616 /* be sure chip saw it */
617 tmp = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
618 udelay(5); /* need pll reset set at least for a bit */
619 /*
620 * after PLL is reset, set the per-lane Resets and TxIdle and
621 * clear the PLL reset and rxdetect (to get falling edge).
622 * Leave L1PWR bits set (permanently)
623 */
624 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
625 | INFINIPATH_SERDC0_L1PWR_DN);
626 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
627 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
628 "and txidle (%llx)\n", (unsigned long long) val);
629 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
630 /* be sure chip saw it */
631 tmp = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
632 /* need PLL reset clear for at least 11 usec before lane
633 * resets cleared; give it a few more to be sure */
634 udelay(15);
635 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
636
637 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
638 "(writing %llx)\n", (unsigned long long) val);
639 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
640 /* be sure chip saw it */
641 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
642
643 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
644 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
645 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
646 val &=
647 ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
648 INFINIPATH_XGXS_MDIOADDR_SHIFT);
649 /* MDIO address 3 */
650 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
651 change = 1;
652 }
653 if (val & INFINIPATH_XGXS_RESET) {
654 val &= ~INFINIPATH_XGXS_RESET;
655 change = 1;
656 }
657 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
658 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
659 /* need to compensate for Tx inversion in partner */
660 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
661 INFINIPATH_XGXS_RX_POL_SHIFT);
662 val |= dd->ipath_rx_pol_inv <<
663 INFINIPATH_XGXS_RX_POL_SHIFT;
664 change = 1;
665 }
666 if (change)
667 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
668
669 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
670
671 /* clear current and de-emphasis bits */
672 config1 &= ~0x0ffffffff00ULL;
673 /* set current to 20ma */
674 config1 |= 0x00000000000ULL;
675 /* set de-emphasis to -5.68dB */
676 config1 |= 0x0cccc000000ULL;
677 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
678
679 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
680 "config1=%llx, sstatus=%llx xgxs=%llx\n",
681 (unsigned long long) val, (unsigned long long) config1,
682 (unsigned long long)
683 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
684 (unsigned long long)
685 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
686
687 if (!ipath_waitfor_mdio_cmdready(dd)) {
688 ipath_write_kreg(
689 dd, dd->ipath_kregs->kr_mdio,
690 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
691 IPATH_MDIO_CTRL_XGXS_REG_8, 0));
692 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
693 IPATH_MDIO_DATAVALID, &val))
694 ipath_dbg("Never got MDIO data for XGXS "
695 "status read\n");
696 else
697 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
698 "'bank' 31 %x\n", (u32) val);
699 } else
700 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
701
702 return ret;
703}
704
705/**
706 * ipath_pe_quiet_serdes - set serdes to txidle
707 * @dd: the infinipath device
708 * Called when driver is being unloaded
709 */
710static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
711{
712 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
713
714 val |= INFINIPATH_SERDC0_TXIDLE;
715 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
716 (unsigned long long) val);
717 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
718}
719
720/* this is not yet needed on this chip, so just return 0. */
721static int ipath_pe_intconfig(struct ipath_devdata *dd)
722{
723 return 0;
724}
725
726/**
727 * ipath_setup_pe_setextled - set the state of the two external LEDs
728 * @dd: the infinipath device
729 * @lst: the L state
730 * @ltst: the LT state
731
732 * These LEDs indicate the physical and logical state of IB link.
733 * For this chip (at least with recommended board pinouts), LED1
734 * is Yellow (logical state) and LED2 is Green (physical state),
735 *
736 * Note: We try to match the Mellanox HCA LED behavior as best
737 * we can. Green indicates physical link state is OK (something is
738 * plugged in, and we can train).
739 * Amber indicates the link is logically up (ACTIVE).
740 * Mellanox further blinks the amber LED to indicate data packet
741 * activity, but we have no hardware support for that, so it would
742 * require waking up every 10-20 msecs and checking the counters
743 * on the chip, and then turning the LED off if appropriate. That's
744 * visible overhead, so not something we will do.
745 *
746 */
747static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
748 u64 ltst)
749{
750 u64 extctl;
751
752 /* the diags use the LED to indicate diag info, so we leave
753 * the external LED alone when the diags are running */
754 if (ipath_diag_inuse)
755 return;
756
757 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
758 INFINIPATH_EXTC_LED2PRIPORT_ON);
759
760 if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
761 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
762 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
763 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
764 dd->ipath_extctrl = extctl;
765 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
766}
767
768/**
769 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
770 * @dd: the infinipath device
771 *
772 * This is called during driver unload.
773 * We do the pci_disable_msi here, not in generic code, because it
774 * isn't used for the HT chips. If we do end up needing pci_enable_msi
775 * at some point in the future for HT, we'll move the call back
776 * into the main init_one code.
777 */
778static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
779{
780 dd->ipath_msi_lo = 0; /* just in case unload fails */
781 pci_disable_msi(dd->pcidev);
782}
783
784/**
785 * ipath_setup_pe_config - setup PCIe config related stuff
786 * @dd: the infinipath device
787 * @pdev: the PCI device
788 *
789 * The pci_enable_msi() call will fail on systems with MSI quirks
790 * such as those with AMD8131, even if the device of interest is not
791 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
792 * late in 2.6.16).
793 * All that can be done is to edit the kernel source to remove the quirk
794 * check until that is fixed.
795 * We do not need to call enable_msi() for our HyperTransport chip,
796 * even though it uses MSI, and we want to avoid the quirk warning, so
797 * So we call enable_msi only for PCIe. If we do end up needing
798 * pci_enable_msi at some point in the future for HT, we'll move the
799 * call back into the main init_one code.
800 * We save the msi lo and hi values, so we can restore them after
801 * chip reset (the kernel PCI infrastructure doesn't yet handle that
802 * correctly).
803 */
804static int ipath_setup_pe_config(struct ipath_devdata *dd,
805 struct pci_dev *pdev)
806{
807 int pos, ret;
808
809 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
810 ret = pci_enable_msi(dd->pcidev);
811 if (ret)
812 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
813 "interrupts may not work\n", ret);
814 /* continue even if it fails, we may still be OK... */
815
816 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
817 u16 control;
818 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
819 &dd->ipath_msi_lo);
820 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
821 &dd->ipath_msi_hi);
822 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
823 &control);
824 /* now save the data (vector) info */
825 pci_read_config_word(dd->pcidev,
826 pos + ((control & PCI_MSI_FLAGS_64BIT)
827 ? 12 : 8),
828 &dd->ipath_msi_data);
829 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
830 "0x%x, control=0x%x\n", dd->ipath_msi_data,
831 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
832 control);
833 /* we save the cachelinesize also, although it doesn't
834 * really matter */
835 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
836 &dd->ipath_pci_cacheline);
837 } else
838 ipath_dev_err(dd, "Can't find MSI capability, "
839 "can't save MSI settings for reset\n");
840 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
841 u16 linkstat;
842 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
843 &linkstat);
844 linkstat >>= 4;
845 linkstat &= 0x1f;
846 if (linkstat != 8)
847 ipath_dev_err(dd, "PCIe width %u, "
848 "performance reduced\n", linkstat);
849 }
850 else
851 ipath_dev_err(dd, "Can't find PCI Express "
852 "capability!\n");
853 return 0;
854}
855
856static void ipath_init_pe_variables(void)
857{
858 /*
859 * bits for selecting i2c direction and values,
860 * used for I2C serial flash
861 */
862 ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
863 ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
864 ipath_gpio_sda = IPATH_GPIO_SDA;
865 ipath_gpio_scl = IPATH_GPIO_SCL;
866
867 /* variables for sanity checking interrupt and errors */
868 infinipath_hwe_bitsextant =
869 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
870 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
871 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
872 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
873 INFINIPATH_HWE_PCIE1PLLFAILED |
874 INFINIPATH_HWE_PCIE0PLLFAILED |
875 INFINIPATH_HWE_PCIEPOISONEDTLP |
876 INFINIPATH_HWE_PCIECPLTIMEOUT |
877 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
878 INFINIPATH_HWE_PCIEBUSPARITYXADM |
879 INFINIPATH_HWE_PCIEBUSPARITYRADM |
880 INFINIPATH_HWE_MEMBISTFAILED |
881 INFINIPATH_HWE_COREPLL_FBSLIP |
882 INFINIPATH_HWE_COREPLL_RFSLIP |
883 INFINIPATH_HWE_SERDESPLLFAILED |
884 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
885 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
886 infinipath_i_bitsextant =
887 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
888 (INFINIPATH_I_RCVAVAIL_MASK <<
889 INFINIPATH_I_RCVAVAIL_SHIFT) |
890 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
891 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
892 infinipath_e_bitsextant =
893 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
894 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
895 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
896 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
897 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
898 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
899 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
900 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
901 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
902 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
903 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
904 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
905 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
906 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
907 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
908 INFINIPATH_E_HARDWARE;
909
910 infinipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
911 infinipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
912}
913
914/* setup the MSI stuff again after a reset. I'd like to just call
915 * pci_enable_msi() and request_irq() again, but when I do that,
916 * the MSI enable bit doesn't get set in the command word, and
917 * we switch to to a different interrupt vector, which is confusing,
918 * so I instead just do it all inline. Perhaps somehow can tie this
919 * into the PCIe hotplug support at some point
920 * Note, because I'm doing it all here, I don't call pci_disable_msi()
921 * or free_irq() at the start of ipath_setup_pe_reset().
922 */
923static int ipath_reinit_msi(struct ipath_devdata *dd)
924{
925 int pos;
926 u16 control;
927 int ret;
928
929 if (!dd->ipath_msi_lo) {
930 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
931 "initial setup failed?\n");
932 ret = 0;
933 goto bail;
934 }
935
936 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
937 ipath_dev_err(dd, "Can't find MSI capability, "
938 "can't restore MSI settings\n");
939 ret = 0;
940 goto bail;
941 }
942 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
943 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
944 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
945 dd->ipath_msi_lo);
946 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
947 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
948 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
949 dd->ipath_msi_hi);
950 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
951 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
952 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
953 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
954 control, control | PCI_MSI_FLAGS_ENABLE);
955 control |= PCI_MSI_FLAGS_ENABLE;
956 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
957 control);
958 }
959 /* now rewrite the data (vector) info */
960 pci_write_config_word(dd->pcidev, pos +
961 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
962 dd->ipath_msi_data);
963 /* we restore the cachelinesize also, although it doesn't really
964 * matter */
965 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
966 dd->ipath_pci_cacheline);
967 /* and now set the pci master bit again */
968 pci_set_master(dd->pcidev);
969 ret = 1;
970
971bail:
972 return ret;
973}
974
975/* This routine sleeps, so it can only be called from user context, not
976 * from interrupt context. If we need interrupt context, we can split
977 * it into two routines.
978*/
979static int ipath_setup_pe_reset(struct ipath_devdata *dd)
980{
981 u64 val;
982 int i;
983 int ret;
984
985 /* Use ERROR so it shows up in logs, etc. */
986 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
987 /* keep chip from being accessed in a few places */
988 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
989 val = dd->ipath_control | INFINIPATH_C_RESET;
990 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
991 mb();
992
993 for (i = 1; i <= 5; i++) {
994 int r;
995 /* allow MBIST, etc. to complete; longer on each retry.
996 * We sometimes get machine checks from bus timeout if no
997 * response, so for now, make it *really* long.
998 */
999 msleep(1000 + (1 + i) * 2000);
1000 if ((r =
1001 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1002 dd->ipath_pcibar0)))
1003 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1004 r);
1005 if ((r =
1006 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1007 dd->ipath_pcibar1)))
1008 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1009 r);
1010 /* now re-enable memory access */
1011 if ((r = pci_enable_device(dd->pcidev)))
1012 ipath_dev_err(dd, "pci_enable_device failed after "
1013 "reset: %d\n", r);
1014 /* whether it worked or not, mark as present, again */
1015 dd->ipath_flags |= IPATH_PRESENT;
1016 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1017 if (val == dd->ipath_revision) {
1018 ipath_cdbg(VERBOSE, "Got matching revision "
1019 "register %llx on try %d\n",
1020 (unsigned long long) val, i);
1021 ret = ipath_reinit_msi(dd);
1022 goto bail;
1023 }
1024 /* Probably getting -1 back */
1025 ipath_dbg("Didn't get expected revision register, "
1026 "got %llx, try %d\n", (unsigned long long) val,
1027 i + 1);
1028 }
1029 ret = 0; /* failed */
1030
1031bail:
1032 return ret;
1033}
1034
1035/**
1036 * ipath_pe_put_tid - write a TID in chip
1037 * @dd: the infinipath device
1038 * @tidptr: pointer to the expected TID (in chip) to udpate
1039 * @tidtype: 0 for eager, 1 for expected
1040 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1041 *
1042 * This exists as a separate routine to allow for special locking etc.
1043 * It's used for both the full cleanup on exit, as well as the normal
1044 * setup and teardown.
1045 */
1046static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1047 u32 type, unsigned long pa)
1048{
1049 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1050 unsigned long flags = 0; /* keep gcc quiet */
1051
1052 if (pa != dd->ipath_tidinvalid) {
1053 if (pa & ((1U << 11) - 1)) {
1054 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1055 "not 4KB aligned!\n", pa);
1056 return;
1057 }
1058 pa >>= 11;
1059 /* paranoia check */
1060 if (pa & (7<<29))
1061 ipath_dev_err(dd,
1062 "BUG: Physical page address 0x%lx "
1063 "has bits set in 31-29\n", pa);
1064
1065 if (type == 0)
1066 pa |= dd->ipath_tidtemplate;
1067 else /* for now, always full 4KB page */
1068 pa |= 2 << 29;
1069 }
1070
1071 /* workaround chip bug 9437 by writing each TID twice
1072 * and holding a spinlock around the writes, so they don't
1073 * intermix with other TID (eager or expected) writes
1074 * Unfortunately, this call can be done from interrupt level
1075 * for the port 0 eager TIDs, so we have to use irqsave
1076 */
1077 spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1078 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1079 if (dd->ipath_kregbase)
1080 writel(pa, tidp32);
1081 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1082 mmiowb();
1083 spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1084}
1085
1086/**
1087 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1088 * @dd: the infinipath device
1089 * @port: the port
1090 *
1091 * clear all TID entries for a port, expected and eager.
1092 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
1093 * not 64, but they are still on 64 bit boundaries, so tidbase
1094 * is declared as u64 * for the pointer math, even though we write 32 bits
1095 */
1096static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1097{
1098 u64 __iomem *tidbase;
1099 unsigned long tidinv;
1100 int i;
1101
1102 if (!dd->ipath_kregbase)
1103 return;
1104
1105 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1106
1107 tidinv = dd->ipath_tidinvalid;
1108 tidbase = (u64 __iomem *)
1109 ((char __iomem *)(dd->ipath_kregbase) +
1110 dd->ipath_rcvtidbase +
1111 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1112
1113 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1114 ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv);
1115
1116 tidbase = (u64 __iomem *)
1117 ((char __iomem *)(dd->ipath_kregbase) +
1118 dd->ipath_rcvegrbase +
1119 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1120
1121 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1122 ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv);
1123}
1124
1125/**
1126 * ipath_pe_tidtemplate - setup constants for TID updates
1127 * @dd: the infinipath device
1128 *
1129 * We setup stuff that we use a lot, to avoid calculating each time
1130 */
1131static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1132{
1133 u32 egrsize = dd->ipath_rcvegrbufsize;
1134
1135 /* For now, we always allocate 4KB buffers (at init) so we can
1136 * receive max size packets. We may want a module parameter to
1137 * specify 2KB or 4KB and/or make be per port instead of per device
1138 * for those who want to reduce memory footprint. Note that the
1139 * ipath_rcvhdrentsize size must be large enough to hold the largest
1140 * IB header (currently 96 bytes) that we expect to handle (plus of
1141 * course the 2 dwords of RHF).
1142 */
1143 if (egrsize == 2048)
1144 dd->ipath_tidtemplate = 1U << 29;
1145 else if (egrsize == 4096)
1146 dd->ipath_tidtemplate = 2U << 29;
1147 else {
1148 egrsize = 4096;
1149 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1150 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1151 egrsize);
1152 dd->ipath_tidtemplate = 2U << 29;
1153 }
1154 dd->ipath_tidinvalid = 0;
1155}
1156
1157static int ipath_pe_early_init(struct ipath_devdata *dd)
1158{
1159 dd->ipath_flags |= IPATH_4BYTE_TID;
1160
1161 /*
1162 * For openfabrics, we need to be able to handle an IB header of
1163 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1164 * made them the same size as the PIO buffers. This chip does not
1165 * handle arbitrary size buffers, so we need the header large enough
1166 * to handle largest IB header, but still have room for a 2KB MTU
1167 * standard IB packet.
1168 */
1169 dd->ipath_rcvhdrentsize = 24;
1170 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1171
1172 /*
1173 * To truly support a 4KB MTU (for usermode), we need to
1174 * bump this to a larger value. For now, we use them for
1175 * the kernel only.
1176 */
1177 dd->ipath_rcvegrbufsize = 2048;
1178 /*
1179 * the min() check here is currently a nop, but it may not always
1180 * be, depending on just how we do ipath_rcvegrbufsize
1181 */
1182 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1183 dd->ipath_rcvegrbufsize +
1184 (dd->ipath_rcvhdrentsize << 2));
1185 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1186
1187 /*
1188 * We can request a receive interrupt for 1 or
1189 * more packets from current offset. For now, we set this
1190 * up for a single packet.
1191 */
1192 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1193
1194 ipath_get_eeprom_info(dd);
1195
1196 return 0;
1197}
1198
1199int __attribute__((weak)) ipath_unordered_wc(void)
1200{
1201 return 0;
1202}
1203
1204/**
1205 * ipath_init_pe_get_base_info - set chip-specific flags for user code
1206 * @dd: the infinipath device
1207 * @kbase: ipath_base_info pointer
1208 *
1209 * We set the PCIE flag because the lower bandwidth on PCIe vs
1210 * HyperTransport can affect some user packet algorithims.
1211 */
1212static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1213{
1214 struct ipath_base_info *kinfo = kbase;
1215
1216 if (ipath_unordered_wc()) {
1217 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1218 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1219 }
1220 else
1221 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1222
1223 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
1224
1225 return 0;
1226}
1227
1228/**
1229 * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1230 * @dd: the infinipath device
1231 *
1232 * This is global, and is called directly at init to set up the
1233 * chip-specific function pointers for later use.
1234 */
1235void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1236{
1237 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1238 dd->ipath_f_bus = ipath_setup_pe_config;
1239 dd->ipath_f_reset = ipath_setup_pe_reset;
1240 dd->ipath_f_get_boardname = ipath_pe_boardname;
1241 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1242 dd->ipath_f_early_init = ipath_pe_early_init;
1243 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1244 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1245 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1246 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1247 dd->ipath_f_put_tid = ipath_pe_put_tid;
1248 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1249 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1250 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1251
1252 /* initialize chip-specific variables */
1253 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1254
1255 /*
1256 * setup the register offsets, since they are different for each
1257 * chip
1258 */
1259 dd->ipath_kregs = &ipath_pe_kregs;
1260 dd->ipath_cregs = &ipath_pe_cregs;
1261
1262 ipath_init_pe_variables();
1263}
1264
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 10:23:55 -0500