diff options
Diffstat (limited to 'drivers/iio/accel/bmc150-accel.c')
-rw-r--r-- | drivers/iio/accel/bmc150-accel.c | 408 |
1 files changed, 392 insertions, 16 deletions
diff --git a/drivers/iio/accel/bmc150-accel.c b/drivers/iio/accel/bmc150-accel.c index f1b80c4c0b35..4026122a7592 100644 --- a/drivers/iio/accel/bmc150-accel.c +++ b/drivers/iio/accel/bmc150-accel.c | |||
@@ -70,7 +70,9 @@ | |||
70 | #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) | 70 | #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) |
71 | 71 | ||
72 | #define BMC150_ACCEL_REG_INT_MAP_1 0x1A | 72 | #define BMC150_ACCEL_REG_INT_MAP_1 0x1A |
73 | #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) | 73 | #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) |
74 | #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) | ||
75 | #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) | ||
74 | 76 | ||
75 | #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 | 77 | #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 |
76 | #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 | 78 | #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 |
@@ -83,7 +85,9 @@ | |||
83 | #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) | 85 | #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) |
84 | 86 | ||
85 | #define BMC150_ACCEL_REG_INT_EN_1 0x17 | 87 | #define BMC150_ACCEL_REG_INT_EN_1 0x17 |
86 | #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) | 88 | #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) |
89 | #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) | ||
90 | #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) | ||
87 | 91 | ||
88 | #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 | 92 | #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 |
89 | #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) | 93 | #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) |
@@ -122,6 +126,12 @@ | |||
122 | #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) | 126 | #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) |
123 | #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 | 127 | #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 |
124 | 128 | ||
129 | #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E | ||
130 | #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 | ||
131 | #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E | ||
132 | #define BMC150_ACCEL_REG_FIFO_DATA 0x3F | ||
133 | #define BMC150_ACCEL_FIFO_LENGTH 32 | ||
134 | |||
125 | enum bmc150_accel_axis { | 135 | enum bmc150_accel_axis { |
126 | AXIS_X, | 136 | AXIS_X, |
127 | AXIS_Y, | 137 | AXIS_Y, |
@@ -179,13 +189,14 @@ struct bmc150_accel_data { | |||
179 | atomic_t active_intr; | 189 | atomic_t active_intr; |
180 | struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; | 190 | struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; |
181 | struct mutex mutex; | 191 | struct mutex mutex; |
192 | u8 fifo_mode, watermark; | ||
182 | s16 buffer[8]; | 193 | s16 buffer[8]; |
183 | u8 bw_bits; | 194 | u8 bw_bits; |
184 | u32 slope_dur; | 195 | u32 slope_dur; |
185 | u32 slope_thres; | 196 | u32 slope_thres; |
186 | u32 range; | 197 | u32 range; |
187 | int ev_enable_state; | 198 | int ev_enable_state; |
188 | int64_t timestamp; | 199 | int64_t timestamp, old_timestamp; |
189 | const struct bmc150_accel_chip_info *chip_info; | 200 | const struct bmc150_accel_chip_info *chip_info; |
190 | }; | 201 | }; |
191 | 202 | ||
@@ -470,6 +481,12 @@ static const struct bmc150_accel_interrupt_info { | |||
470 | BMC150_ACCEL_INT_EN_BIT_SLP_Y | | 481 | BMC150_ACCEL_INT_EN_BIT_SLP_Y | |
471 | BMC150_ACCEL_INT_EN_BIT_SLP_Z | 482 | BMC150_ACCEL_INT_EN_BIT_SLP_Z |
472 | }, | 483 | }, |
484 | { /* fifo watermark interrupt */ | ||
485 | .map_reg = BMC150_ACCEL_REG_INT_MAP_1, | ||
486 | .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM, | ||
487 | .en_reg = BMC150_ACCEL_REG_INT_EN_1, | ||
488 | .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, | ||
489 | }, | ||
473 | }; | 490 | }; |
474 | 491 | ||
475 | static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, | 492 | static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, |
@@ -823,6 +840,214 @@ static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, | |||
823 | return -EINVAL; | 840 | return -EINVAL; |
824 | } | 841 | } |
825 | 842 | ||
843 | static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, | ||
844 | struct device_attribute *attr, | ||
845 | char *buf) | ||
846 | { | ||
847 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | ||
848 | struct bmc150_accel_data *data = iio_priv(indio_dev); | ||
849 | int wm; | ||
850 | |||
851 | mutex_lock(&data->mutex); | ||
852 | wm = data->watermark; | ||
853 | mutex_unlock(&data->mutex); | ||
854 | |||
855 | return sprintf(buf, "%d\n", wm); | ||
856 | } | ||
857 | |||
858 | static ssize_t bmc150_accel_get_fifo_state(struct device *dev, | ||
859 | struct device_attribute *attr, | ||
860 | char *buf) | ||
861 | { | ||
862 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | ||
863 | struct bmc150_accel_data *data = iio_priv(indio_dev); | ||
864 | bool state; | ||
865 | |||
866 | mutex_lock(&data->mutex); | ||
867 | state = data->fifo_mode; | ||
868 | mutex_unlock(&data->mutex); | ||
869 | |||
870 | return sprintf(buf, "%d\n", state); | ||
871 | } | ||
872 | |||
873 | static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); | ||
874 | static IIO_CONST_ATTR(hwfifo_watermark_max, | ||
875 | __stringify(BMC150_ACCEL_FIFO_LENGTH)); | ||
876 | static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, | ||
877 | bmc150_accel_get_fifo_state, NULL, 0); | ||
878 | static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, | ||
879 | bmc150_accel_get_fifo_watermark, NULL, 0); | ||
880 | |||
881 | static const struct attribute *bmc150_accel_fifo_attributes[] = { | ||
882 | &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, | ||
883 | &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, | ||
884 | &iio_dev_attr_hwfifo_watermark.dev_attr.attr, | ||
885 | &iio_dev_attr_hwfifo_enabled.dev_attr.attr, | ||
886 | NULL, | ||
887 | }; | ||
888 | |||
889 | static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) | ||
890 | { | ||
891 | struct bmc150_accel_data *data = iio_priv(indio_dev); | ||
892 | |||
893 | if (val > BMC150_ACCEL_FIFO_LENGTH) | ||
894 | val = BMC150_ACCEL_FIFO_LENGTH; | ||
895 | |||
896 | mutex_lock(&data->mutex); | ||
897 | data->watermark = val; | ||
898 | mutex_unlock(&data->mutex); | ||
899 | |||
900 | return 0; | ||
901 | } | ||
902 | |||
903 | /* | ||
904 | * We must read at least one full frame in one burst, otherwise the rest of the | ||
905 | * frame data is discarded. | ||
906 | */ | ||
907 | static int bmc150_accel_fifo_transfer(const struct i2c_client *client, | ||
908 | char *buffer, int samples) | ||
909 | { | ||
910 | int sample_length = 3 * 2; | ||
911 | u8 reg_fifo_data = BMC150_ACCEL_REG_FIFO_DATA; | ||
912 | int ret = -EIO; | ||
913 | |||
914 | if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { | ||
915 | struct i2c_msg msg[2] = { | ||
916 | { | ||
917 | .addr = client->addr, | ||
918 | .flags = 0, | ||
919 | .buf = ®_fifo_data, | ||
920 | .len = sizeof(reg_fifo_data), | ||
921 | }, | ||
922 | { | ||
923 | .addr = client->addr, | ||
924 | .flags = I2C_M_RD, | ||
925 | .buf = (u8 *)buffer, | ||
926 | .len = samples * sample_length, | ||
927 | } | ||
928 | }; | ||
929 | |||
930 | ret = i2c_transfer(client->adapter, msg, 2); | ||
931 | if (ret != 2) | ||
932 | ret = -EIO; | ||
933 | else | ||
934 | ret = 0; | ||
935 | } else { | ||
936 | int i, step = I2C_SMBUS_BLOCK_MAX / sample_length; | ||
937 | |||
938 | for (i = 0; i < samples * sample_length; i += step) { | ||
939 | ret = i2c_smbus_read_i2c_block_data(client, | ||
940 | reg_fifo_data, step, | ||
941 | &buffer[i]); | ||
942 | if (ret != step) { | ||
943 | ret = -EIO; | ||
944 | break; | ||
945 | } | ||
946 | |||
947 | ret = 0; | ||
948 | } | ||
949 | } | ||
950 | |||
951 | if (ret) | ||
952 | dev_err(&client->dev, "Error transferring data from fifo\n"); | ||
953 | |||
954 | return ret; | ||
955 | } | ||
956 | |||
957 | static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, | ||
958 | unsigned samples, bool irq) | ||
959 | { | ||
960 | struct bmc150_accel_data *data = iio_priv(indio_dev); | ||
961 | int ret, i; | ||
962 | u8 count; | ||
963 | u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; | ||
964 | int64_t tstamp; | ||
965 | uint64_t sample_period; | ||
966 | ret = i2c_smbus_read_byte_data(data->client, | ||
967 | BMC150_ACCEL_REG_FIFO_STATUS); | ||
968 | if (ret < 0) { | ||
969 | dev_err(&data->client->dev, "Error reading reg_fifo_status\n"); | ||
970 | return ret; | ||
971 | } | ||
972 | |||
973 | count = ret & 0x7F; | ||
974 | |||
975 | if (!count) | ||
976 | return 0; | ||
977 | |||
978 | /* | ||
979 | * If we getting called from IRQ handler we know the stored timestamp is | ||
980 | * fairly accurate for the last stored sample. Otherwise, if we are | ||
981 | * called as a result of a read operation from userspace and hence | ||
982 | * before the watermark interrupt was triggered, take a timestamp | ||
983 | * now. We can fall anywhere in between two samples so the error in this | ||
984 | * case is at most one sample period. | ||
985 | */ | ||
986 | if (!irq) { | ||
987 | data->old_timestamp = data->timestamp; | ||
988 | data->timestamp = iio_get_time_ns(); | ||
989 | } | ||
990 | |||
991 | /* | ||
992 | * Approximate timestamps for each of the sample based on the sampling | ||
993 | * frequency, timestamp for last sample and number of samples. | ||
994 | * | ||
995 | * Note that we can't use the current bandwidth settings to compute the | ||
996 | * sample period because the sample rate varies with the device | ||
997 | * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That | ||
998 | * small variation adds when we store a large number of samples and | ||
999 | * creates significant jitter between the last and first samples in | ||
1000 | * different batches (e.g. 32ms vs 21ms). | ||
1001 | * | ||
1002 | * To avoid this issue we compute the actual sample period ourselves | ||
1003 | * based on the timestamp delta between the last two flush operations. | ||
1004 | */ | ||
1005 | sample_period = (data->timestamp - data->old_timestamp); | ||
1006 | do_div(sample_period, count); | ||
1007 | tstamp = data->timestamp - (count - 1) * sample_period; | ||
1008 | |||
1009 | if (samples && count > samples) | ||
1010 | count = samples; | ||
1011 | |||
1012 | ret = bmc150_accel_fifo_transfer(data->client, (u8 *)buffer, count); | ||
1013 | if (ret) | ||
1014 | return ret; | ||
1015 | |||
1016 | /* | ||
1017 | * Ideally we want the IIO core to handle the demux when running in fifo | ||
1018 | * mode but not when running in triggered buffer mode. Unfortunately | ||
1019 | * this does not seem to be possible, so stick with driver demux for | ||
1020 | * now. | ||
1021 | */ | ||
1022 | for (i = 0; i < count; i++) { | ||
1023 | u16 sample[8]; | ||
1024 | int j, bit; | ||
1025 | |||
1026 | j = 0; | ||
1027 | for_each_set_bit(bit, indio_dev->active_scan_mask, | ||
1028 | indio_dev->masklength) | ||
1029 | memcpy(&sample[j++], &buffer[i * 3 + bit], 2); | ||
1030 | |||
1031 | iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp); | ||
1032 | |||
1033 | tstamp += sample_period; | ||
1034 | } | ||
1035 | |||
1036 | return count; | ||
1037 | } | ||
1038 | |||
1039 | static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) | ||
1040 | { | ||
1041 | struct bmc150_accel_data *data = iio_priv(indio_dev); | ||
1042 | int ret; | ||
1043 | |||
1044 | mutex_lock(&data->mutex); | ||
1045 | ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); | ||
1046 | mutex_unlock(&data->mutex); | ||
1047 | |||
1048 | return ret; | ||
1049 | } | ||
1050 | |||
826 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( | 1051 | static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( |
827 | "7.810000 15.630000 31.250000 62.500000 125 250 500 1000"); | 1052 | "7.810000 15.630000 31.250000 62.500000 125 250 500 1000"); |
828 | 1053 | ||
@@ -962,6 +1187,20 @@ static const struct iio_info bmc150_accel_info = { | |||
962 | .driver_module = THIS_MODULE, | 1187 | .driver_module = THIS_MODULE, |
963 | }; | 1188 | }; |
964 | 1189 | ||
1190 | static const struct iio_info bmc150_accel_info_fifo = { | ||
1191 | .attrs = &bmc150_accel_attrs_group, | ||
1192 | .read_raw = bmc150_accel_read_raw, | ||
1193 | .write_raw = bmc150_accel_write_raw, | ||
1194 | .read_event_value = bmc150_accel_read_event, | ||
1195 | .write_event_value = bmc150_accel_write_event, | ||
1196 | .write_event_config = bmc150_accel_write_event_config, | ||
1197 | .read_event_config = bmc150_accel_read_event_config, | ||
1198 | .validate_trigger = bmc150_accel_validate_trigger, | ||
1199 | .hwfifo_set_watermark = bmc150_accel_set_watermark, | ||
1200 | .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, | ||
1201 | .driver_module = THIS_MODULE, | ||
1202 | }; | ||
1203 | |||
965 | static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) | 1204 | static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) |
966 | { | 1205 | { |
967 | struct iio_poll_func *pf = p; | 1206 | struct iio_poll_func *pf = p; |
@@ -1057,18 +1296,17 @@ static const struct iio_trigger_ops bmc150_accel_trigger_ops = { | |||
1057 | .owner = THIS_MODULE, | 1296 | .owner = THIS_MODULE, |
1058 | }; | 1297 | }; |
1059 | 1298 | ||
1060 | static irqreturn_t bmc150_accel_event_handler(int irq, void *private) | 1299 | static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) |
1061 | { | 1300 | { |
1062 | struct iio_dev *indio_dev = private; | ||
1063 | struct bmc150_accel_data *data = iio_priv(indio_dev); | 1301 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
1064 | int ret; | ||
1065 | int dir; | 1302 | int dir; |
1303 | int ret; | ||
1066 | 1304 | ||
1067 | ret = i2c_smbus_read_byte_data(data->client, | 1305 | ret = i2c_smbus_read_byte_data(data->client, |
1068 | BMC150_ACCEL_REG_INT_STATUS_2); | 1306 | BMC150_ACCEL_REG_INT_STATUS_2); |
1069 | if (ret < 0) { | 1307 | if (ret < 0) { |
1070 | dev_err(&data->client->dev, "Error reading reg_int_status_2\n"); | 1308 | dev_err(&data->client->dev, "Error reading reg_int_status_2\n"); |
1071 | goto ack_intr_status; | 1309 | return ret; |
1072 | } | 1310 | } |
1073 | 1311 | ||
1074 | if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) | 1312 | if (ret & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) |
@@ -1097,35 +1335,73 @@ static irqreturn_t bmc150_accel_event_handler(int irq, void *private) | |||
1097 | IIO_EV_TYPE_ROC, | 1335 | IIO_EV_TYPE_ROC, |
1098 | dir), | 1336 | dir), |
1099 | data->timestamp); | 1337 | data->timestamp); |
1100 | ack_intr_status: | 1338 | return ret; |
1101 | if (!data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY].enabled) | 1339 | } |
1340 | |||
1341 | static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) | ||
1342 | { | ||
1343 | struct iio_dev *indio_dev = private; | ||
1344 | struct bmc150_accel_data *data = iio_priv(indio_dev); | ||
1345 | bool ack = false; | ||
1346 | int ret; | ||
1347 | |||
1348 | mutex_lock(&data->mutex); | ||
1349 | |||
1350 | if (data->fifo_mode) { | ||
1351 | ret = __bmc150_accel_fifo_flush(indio_dev, | ||
1352 | BMC150_ACCEL_FIFO_LENGTH, true); | ||
1353 | if (ret > 0) | ||
1354 | ack = true; | ||
1355 | } | ||
1356 | |||
1357 | if (data->ev_enable_state) { | ||
1358 | ret = bmc150_accel_handle_roc_event(indio_dev); | ||
1359 | if (ret > 0) | ||
1360 | ack = true; | ||
1361 | } | ||
1362 | |||
1363 | if (ack) { | ||
1102 | ret = i2c_smbus_write_byte_data(data->client, | 1364 | ret = i2c_smbus_write_byte_data(data->client, |
1103 | BMC150_ACCEL_REG_INT_RST_LATCH, | 1365 | BMC150_ACCEL_REG_INT_RST_LATCH, |
1104 | BMC150_ACCEL_INT_MODE_LATCH_INT | | 1366 | BMC150_ACCEL_INT_MODE_LATCH_INT | |
1105 | BMC150_ACCEL_INT_MODE_LATCH_RESET); | 1367 | BMC150_ACCEL_INT_MODE_LATCH_RESET); |
1368 | if (ret) | ||
1369 | dev_err(&data->client->dev, "Error writing reg_int_rst_latch\n"); | ||
1370 | ret = IRQ_HANDLED; | ||
1371 | } else { | ||
1372 | ret = IRQ_NONE; | ||
1373 | } | ||
1106 | 1374 | ||
1107 | return IRQ_HANDLED; | 1375 | mutex_unlock(&data->mutex); |
1376 | |||
1377 | return ret; | ||
1108 | } | 1378 | } |
1109 | 1379 | ||
1110 | static irqreturn_t bmc150_accel_data_rdy_trig_poll(int irq, void *private) | 1380 | static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) |
1111 | { | 1381 | { |
1112 | struct iio_dev *indio_dev = private; | 1382 | struct iio_dev *indio_dev = private; |
1113 | struct bmc150_accel_data *data = iio_priv(indio_dev); | 1383 | struct bmc150_accel_data *data = iio_priv(indio_dev); |
1384 | bool ack = false; | ||
1114 | int i; | 1385 | int i; |
1115 | 1386 | ||
1387 | data->old_timestamp = data->timestamp; | ||
1116 | data->timestamp = iio_get_time_ns(); | 1388 | data->timestamp = iio_get_time_ns(); |
1117 | 1389 | ||
1118 | for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { | 1390 | for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { |
1119 | if (data->triggers[i].enabled) { | 1391 | if (data->triggers[i].enabled) { |
1120 | iio_trigger_poll(data->triggers[i].indio_trig); | 1392 | iio_trigger_poll(data->triggers[i].indio_trig); |
1393 | ack = true; | ||
1121 | break; | 1394 | break; |
1122 | } | 1395 | } |
1123 | } | 1396 | } |
1124 | 1397 | ||
1125 | if (data->ev_enable_state) | 1398 | if (data->ev_enable_state || data->fifo_mode) |
1126 | return IRQ_WAKE_THREAD; | 1399 | return IRQ_WAKE_THREAD; |
1127 | else | 1400 | |
1401 | if (ack) | ||
1128 | return IRQ_HANDLED; | 1402 | return IRQ_HANDLED; |
1403 | |||
1404 | return IRQ_NONE; | ||
1129 | } | 1405 | } |
1130 | 1406 | ||
1131 | static const char *bmc150_accel_match_acpi_device(struct device *dev, int *data) | 1407 | static const char *bmc150_accel_match_acpi_device(struct device *dev, int *data) |
@@ -1232,6 +1508,94 @@ static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, | |||
1232 | return ret; | 1508 | return ret; |
1233 | } | 1509 | } |
1234 | 1510 | ||
1511 | #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 | ||
1512 | #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 | ||
1513 | #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 | ||
1514 | |||
1515 | static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) | ||
1516 | { | ||
1517 | u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; | ||
1518 | int ret; | ||
1519 | |||
1520 | ret = i2c_smbus_write_byte_data(data->client, reg, data->fifo_mode); | ||
1521 | if (ret < 0) { | ||
1522 | dev_err(&data->client->dev, "Error writing reg_fifo_config1\n"); | ||
1523 | return ret; | ||
1524 | } | ||
1525 | |||
1526 | if (!data->fifo_mode) | ||
1527 | return 0; | ||
1528 | |||
1529 | ret = i2c_smbus_write_byte_data(data->client, | ||
1530 | BMC150_ACCEL_REG_FIFO_CONFIG0, | ||
1531 | data->watermark); | ||
1532 | if (ret < 0) | ||
1533 | dev_err(&data->client->dev, "Error writing reg_fifo_config0\n"); | ||
1534 | |||
1535 | return ret; | ||
1536 | } | ||
1537 | |||
1538 | static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) | ||
1539 | { | ||
1540 | struct bmc150_accel_data *data = iio_priv(indio_dev); | ||
1541 | int ret = 0; | ||
1542 | |||
1543 | if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) | ||
1544 | return iio_triggered_buffer_postenable(indio_dev); | ||
1545 | |||
1546 | mutex_lock(&data->mutex); | ||
1547 | |||
1548 | if (!data->watermark) | ||
1549 | goto out; | ||
1550 | |||
1551 | ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, | ||
1552 | true); | ||
1553 | if (ret) | ||
1554 | goto out; | ||
1555 | |||
1556 | data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; | ||
1557 | |||
1558 | ret = bmc150_accel_fifo_set_mode(data); | ||
1559 | if (ret) { | ||
1560 | data->fifo_mode = 0; | ||
1561 | bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, | ||
1562 | false); | ||
1563 | } | ||
1564 | |||
1565 | out: | ||
1566 | mutex_unlock(&data->mutex); | ||
1567 | |||
1568 | return ret; | ||
1569 | } | ||
1570 | |||
1571 | static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) | ||
1572 | { | ||
1573 | struct bmc150_accel_data *data = iio_priv(indio_dev); | ||
1574 | |||
1575 | if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) | ||
1576 | return iio_triggered_buffer_predisable(indio_dev); | ||
1577 | |||
1578 | mutex_lock(&data->mutex); | ||
1579 | |||
1580 | if (!data->fifo_mode) | ||
1581 | goto out; | ||
1582 | |||
1583 | bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); | ||
1584 | __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); | ||
1585 | data->fifo_mode = 0; | ||
1586 | bmc150_accel_fifo_set_mode(data); | ||
1587 | |||
1588 | out: | ||
1589 | mutex_unlock(&data->mutex); | ||
1590 | |||
1591 | return 0; | ||
1592 | } | ||
1593 | |||
1594 | static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { | ||
1595 | .postenable = bmc150_accel_buffer_postenable, | ||
1596 | .predisable = bmc150_accel_buffer_predisable, | ||
1597 | }; | ||
1598 | |||
1235 | static int bmc150_accel_probe(struct i2c_client *client, | 1599 | static int bmc150_accel_probe(struct i2c_client *client, |
1236 | const struct i2c_device_id *id) | 1600 | const struct i2c_device_id *id) |
1237 | { | 1601 | { |
@@ -1278,8 +1642,8 @@ static int bmc150_accel_probe(struct i2c_client *client, | |||
1278 | if (client->irq >= 0) { | 1642 | if (client->irq >= 0) { |
1279 | ret = devm_request_threaded_irq( | 1643 | ret = devm_request_threaded_irq( |
1280 | &client->dev, client->irq, | 1644 | &client->dev, client->irq, |
1281 | bmc150_accel_data_rdy_trig_poll, | 1645 | bmc150_accel_irq_handler, |
1282 | bmc150_accel_event_handler, | 1646 | bmc150_accel_irq_thread_handler, |
1283 | IRQF_TRIGGER_RISING, | 1647 | IRQF_TRIGGER_RISING, |
1284 | BMC150_ACCEL_IRQ_NAME, | 1648 | BMC150_ACCEL_IRQ_NAME, |
1285 | indio_dev); | 1649 | indio_dev); |
@@ -1309,12 +1673,20 @@ static int bmc150_accel_probe(struct i2c_client *client, | |||
1309 | ret = iio_triggered_buffer_setup(indio_dev, | 1673 | ret = iio_triggered_buffer_setup(indio_dev, |
1310 | &iio_pollfunc_store_time, | 1674 | &iio_pollfunc_store_time, |
1311 | bmc150_accel_trigger_handler, | 1675 | bmc150_accel_trigger_handler, |
1312 | NULL); | 1676 | &bmc150_accel_buffer_ops); |
1313 | if (ret < 0) { | 1677 | if (ret < 0) { |
1314 | dev_err(&client->dev, | 1678 | dev_err(&client->dev, |
1315 | "Failed: iio triggered buffer setup\n"); | 1679 | "Failed: iio triggered buffer setup\n"); |
1316 | goto err_trigger_unregister; | 1680 | goto err_trigger_unregister; |
1317 | } | 1681 | } |
1682 | |||
1683 | if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) || | ||
1684 | i2c_check_functionality(client->adapter, | ||
1685 | I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { | ||
1686 | indio_dev->modes |= INDIO_BUFFER_SOFTWARE; | ||
1687 | indio_dev->info = &bmc150_accel_info_fifo; | ||
1688 | indio_dev->buffer->attrs = bmc150_accel_fifo_attributes; | ||
1689 | } | ||
1318 | } | 1690 | } |
1319 | 1691 | ||
1320 | ret = iio_device_register(indio_dev); | 1692 | ret = iio_device_register(indio_dev); |
@@ -1386,6 +1758,7 @@ static int bmc150_accel_resume(struct device *dev) | |||
1386 | mutex_lock(&data->mutex); | 1758 | mutex_lock(&data->mutex); |
1387 | if (atomic_read(&data->active_intr)) | 1759 | if (atomic_read(&data->active_intr)) |
1388 | bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); | 1760 | bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); |
1761 | bmc150_accel_fifo_set_mode(data); | ||
1389 | mutex_unlock(&data->mutex); | 1762 | mutex_unlock(&data->mutex); |
1390 | 1763 | ||
1391 | return 0; | 1764 | return 0; |
@@ -1419,6 +1792,9 @@ static int bmc150_accel_runtime_resume(struct device *dev) | |||
1419 | ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); | 1792 | ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); |
1420 | if (ret < 0) | 1793 | if (ret < 0) |
1421 | return ret; | 1794 | return ret; |
1795 | ret = bmc150_accel_fifo_set_mode(data); | ||
1796 | if (ret < 0) | ||
1797 | return ret; | ||
1422 | 1798 | ||
1423 | sleep_val = bmc150_accel_get_startup_times(data); | 1799 | sleep_val = bmc150_accel_get_startup_times(data); |
1424 | if (sleep_val < 20) | 1800 | if (sleep_val < 20) |