diff options
Diffstat (limited to 'drivers/ieee1394')
-rw-r--r-- | drivers/ieee1394/csr.c | 12 | ||||
-rw-r--r-- | drivers/ieee1394/csr.h | 10 | ||||
-rw-r--r-- | drivers/ieee1394/csr1212.c | 45 | ||||
-rw-r--r-- | drivers/ieee1394/csr1212.h | 9 | ||||
-rw-r--r-- | drivers/ieee1394/dv1394-private.h | 44 | ||||
-rw-r--r-- | drivers/ieee1394/dv1394.c | 12 | ||||
-rw-r--r-- | drivers/ieee1394/eth1394.c | 28 | ||||
-rw-r--r-- | drivers/ieee1394/eth1394.h | 16 | ||||
-rw-r--r-- | drivers/ieee1394/highlevel.c | 9 | ||||
-rw-r--r-- | drivers/ieee1394/highlevel.h | 7 | ||||
-rw-r--r-- | drivers/ieee1394/hosts.c | 6 | ||||
-rw-r--r-- | drivers/ieee1394/hosts.h | 2 | ||||
-rw-r--r-- | drivers/ieee1394/ieee1394.h | 3 | ||||
-rw-r--r-- | drivers/ieee1394/nodemgr.c | 20 | ||||
-rw-r--r-- | drivers/ieee1394/nodemgr.h | 3 | ||||
-rw-r--r-- | drivers/ieee1394/ohci1394.c | 26 | ||||
-rw-r--r-- | drivers/ieee1394/pcilynx.c | 2 | ||||
-rw-r--r-- | drivers/ieee1394/pcilynx.h | 2 | ||||
-rw-r--r-- | drivers/ieee1394/raw1394.c | 2 | ||||
-rw-r--r-- | drivers/ieee1394/sbp2.c | 4 |
20 files changed, 121 insertions, 141 deletions
diff --git a/drivers/ieee1394/csr.c b/drivers/ieee1394/csr.c index c90be4070e40..31400c8ae051 100644 --- a/drivers/ieee1394/csr.c +++ b/drivers/ieee1394/csr.c | |||
@@ -68,22 +68,22 @@ static struct hpsb_highlevel csr_highlevel = { | |||
68 | .host_reset = host_reset, | 68 | .host_reset = host_reset, |
69 | }; | 69 | }; |
70 | 70 | ||
71 | static struct hpsb_address_ops map_ops = { | 71 | const static struct hpsb_address_ops map_ops = { |
72 | .read = read_maps, | 72 | .read = read_maps, |
73 | }; | 73 | }; |
74 | 74 | ||
75 | static struct hpsb_address_ops fcp_ops = { | 75 | const static struct hpsb_address_ops fcp_ops = { |
76 | .write = write_fcp, | 76 | .write = write_fcp, |
77 | }; | 77 | }; |
78 | 78 | ||
79 | static struct hpsb_address_ops reg_ops = { | 79 | const static struct hpsb_address_ops reg_ops = { |
80 | .read = read_regs, | 80 | .read = read_regs, |
81 | .write = write_regs, | 81 | .write = write_regs, |
82 | .lock = lock_regs, | 82 | .lock = lock_regs, |
83 | .lock64 = lock64_regs, | 83 | .lock64 = lock64_regs, |
84 | }; | 84 | }; |
85 | 85 | ||
86 | static struct hpsb_address_ops config_rom_ops = { | 86 | const static struct hpsb_address_ops config_rom_ops = { |
87 | .read = read_config_rom, | 87 | .read = read_config_rom, |
88 | }; | 88 | }; |
89 | 89 | ||
@@ -217,7 +217,7 @@ static void add_host(struct hpsb_host *host) | |||
217 | 217 | ||
218 | host->csr.generation = 2; | 218 | host->csr.generation = 2; |
219 | 219 | ||
220 | bus_info[1] = __constant_cpu_to_be32(0x31333934); | 220 | bus_info[1] = IEEE1394_BUSID_MAGIC; |
221 | bus_info[2] = cpu_to_be32((hpsb_disable_irm ? 0 : 1 << CSR_IRMC_SHIFT) | | 221 | bus_info[2] = cpu_to_be32((hpsb_disable_irm ? 0 : 1 << CSR_IRMC_SHIFT) | |
222 | (1 << CSR_CMC_SHIFT) | | 222 | (1 << CSR_CMC_SHIFT) | |
223 | (1 << CSR_ISC_SHIFT) | | 223 | (1 << CSR_ISC_SHIFT) | |
@@ -250,7 +250,7 @@ static void remove_host(struct hpsb_host *host) | |||
250 | { | 250 | { |
251 | quadlet_t bus_info[CSR_BUS_INFO_SIZE]; | 251 | quadlet_t bus_info[CSR_BUS_INFO_SIZE]; |
252 | 252 | ||
253 | bus_info[1] = __constant_cpu_to_be32(0x31333934); | 253 | bus_info[1] = IEEE1394_BUSID_MAGIC; |
254 | bus_info[2] = cpu_to_be32((0 << CSR_IRMC_SHIFT) | | 254 | bus_info[2] = cpu_to_be32((0 << CSR_IRMC_SHIFT) | |
255 | (0 << CSR_CMC_SHIFT) | | 255 | (0 << CSR_CMC_SHIFT) | |
256 | (0 << CSR_ISC_SHIFT) | | 256 | (0 << CSR_ISC_SHIFT) | |
diff --git a/drivers/ieee1394/csr.h b/drivers/ieee1394/csr.h index f11546550d84..90fb3f2192c3 100644 --- a/drivers/ieee1394/csr.h +++ b/drivers/ieee1394/csr.h | |||
@@ -50,11 +50,11 @@ | |||
50 | #define CSR_MAX_ROM_SHIFT 8 | 50 | #define CSR_MAX_ROM_SHIFT 8 |
51 | #define CSR_GENERATION_SHIFT 4 | 51 | #define CSR_GENERATION_SHIFT 4 |
52 | 52 | ||
53 | #define CSR_SET_BUS_INFO_GENERATION(csr, gen) \ | 53 | static inline void csr_set_bus_info_generation(struct csr1212_csr *csr, u8 gen) |
54 | ((csr)->bus_info_data[2] = \ | 54 | { |
55 | cpu_to_be32((be32_to_cpu((csr)->bus_info_data[2]) & \ | 55 | csr->bus_info_data[2] &= ~cpu_to_be32(0xf << CSR_GENERATION_SHIFT); |
56 | ~(0xf << CSR_GENERATION_SHIFT)) | \ | 56 | csr->bus_info_data[2] |= cpu_to_be32((u32)gen << CSR_GENERATION_SHIFT); |
57 | (gen) << CSR_GENERATION_SHIFT)) | 57 | } |
58 | 58 | ||
59 | struct csr_control { | 59 | struct csr_control { |
60 | spinlock_t lock; | 60 | spinlock_t lock; |
diff --git a/drivers/ieee1394/csr1212.c b/drivers/ieee1394/csr1212.c index 5e38a68b8af2..a6dfeb0b3372 100644 --- a/drivers/ieee1394/csr1212.c +++ b/drivers/ieee1394/csr1212.c | |||
@@ -1077,15 +1077,10 @@ static int csr1212_parse_bus_info_block(struct csr1212_csr *csr) | |||
1077 | int i; | 1077 | int i; |
1078 | int ret; | 1078 | int ret; |
1079 | 1079 | ||
1080 | /* IEEE 1212 says that the entire bus info block should be readable in | ||
1081 | * a single transaction regardless of the max_rom value. | ||
1082 | * Unfortunately, many IEEE 1394 devices do not abide by that, so the | ||
1083 | * bus info block will be read 1 quadlet at a time. The rest of the | ||
1084 | * ConfigROM will be read according to the max_rom field. */ | ||
1085 | for (i = 0; i < csr->bus_info_len; i += sizeof(u32)) { | 1080 | for (i = 0; i < csr->bus_info_len; i += sizeof(u32)) { |
1086 | ret = csr->ops->bus_read(csr, CSR1212_CONFIG_ROM_SPACE_BASE + i, | 1081 | ret = csr->ops->bus_read(csr, CSR1212_CONFIG_ROM_SPACE_BASE + i, |
1087 | sizeof(u32), &csr->cache_head->data[bytes_to_quads(i)], | 1082 | &csr->cache_head->data[bytes_to_quads(i)], |
1088 | csr->private); | 1083 | csr->private); |
1089 | if (ret != CSR1212_SUCCESS) | 1084 | if (ret != CSR1212_SUCCESS) |
1090 | return ret; | 1085 | return ret; |
1091 | 1086 | ||
@@ -1104,8 +1099,8 @@ static int csr1212_parse_bus_info_block(struct csr1212_csr *csr) | |||
1104 | * a time. */ | 1099 | * a time. */ |
1105 | for (i = csr->bus_info_len; i <= csr->crc_len; i += sizeof(u32)) { | 1100 | for (i = csr->bus_info_len; i <= csr->crc_len; i += sizeof(u32)) { |
1106 | ret = csr->ops->bus_read(csr, CSR1212_CONFIG_ROM_SPACE_BASE + i, | 1101 | ret = csr->ops->bus_read(csr, CSR1212_CONFIG_ROM_SPACE_BASE + i, |
1107 | sizeof(u32), &csr->cache_head->data[bytes_to_quads(i)], | 1102 | &csr->cache_head->data[bytes_to_quads(i)], |
1108 | csr->private); | 1103 | csr->private); |
1109 | if (ret != CSR1212_SUCCESS) | 1104 | if (ret != CSR1212_SUCCESS) |
1110 | return ret; | 1105 | return ret; |
1111 | } | 1106 | } |
@@ -1289,7 +1284,7 @@ csr1212_read_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv) | |||
1289 | 1284 | ||
1290 | if (csr->ops->bus_read(csr, | 1285 | if (csr->ops->bus_read(csr, |
1291 | CSR1212_REGISTER_SPACE_BASE + kv->offset, | 1286 | CSR1212_REGISTER_SPACE_BASE + kv->offset, |
1292 | sizeof(u32), &q, csr->private)) | 1287 | &q, csr->private)) |
1293 | return -EIO; | 1288 | return -EIO; |
1294 | 1289 | ||
1295 | kv->value.leaf.len = be32_to_cpu(q) >> 16; | 1290 | kv->value.leaf.len = be32_to_cpu(q) >> 16; |
@@ -1372,17 +1367,8 @@ csr1212_read_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv) | |||
1372 | addr = (CSR1212_CSR_ARCH_REG_SPACE_BASE + cache->offset + | 1367 | addr = (CSR1212_CSR_ARCH_REG_SPACE_BASE + cache->offset + |
1373 | cr->offset_end) & ~(csr->max_rom - 1); | 1368 | cr->offset_end) & ~(csr->max_rom - 1); |
1374 | 1369 | ||
1375 | if (csr->ops->bus_read(csr, addr, csr->max_rom, cache_ptr, | 1370 | if (csr->ops->bus_read(csr, addr, cache_ptr, csr->private)) |
1376 | csr->private)) { | 1371 | return -EIO; |
1377 | if (csr->max_rom == 4) | ||
1378 | /* We've got problems! */ | ||
1379 | return -EIO; | ||
1380 | |||
1381 | /* Apperently the max_rom value was a lie, set it to | ||
1382 | * do quadlet reads and try again. */ | ||
1383 | csr->max_rom = 4; | ||
1384 | continue; | ||
1385 | } | ||
1386 | 1372 | ||
1387 | cr->offset_end += csr->max_rom - (cr->offset_end & | 1373 | cr->offset_end += csr->max_rom - (cr->offset_end & |
1388 | (csr->max_rom - 1)); | 1374 | (csr->max_rom - 1)); |
@@ -1433,7 +1419,6 @@ csr1212_get_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv) | |||
1433 | 1419 | ||
1434 | int csr1212_parse_csr(struct csr1212_csr *csr) | 1420 | int csr1212_parse_csr(struct csr1212_csr *csr) |
1435 | { | 1421 | { |
1436 | static const int mr_map[] = { 4, 64, 1024, 0 }; | ||
1437 | struct csr1212_dentry *dentry; | 1422 | struct csr1212_dentry *dentry; |
1438 | int ret; | 1423 | int ret; |
1439 | 1424 | ||
@@ -1443,15 +1428,13 @@ int csr1212_parse_csr(struct csr1212_csr *csr) | |||
1443 | if (ret != CSR1212_SUCCESS) | 1428 | if (ret != CSR1212_SUCCESS) |
1444 | return ret; | 1429 | return ret; |
1445 | 1430 | ||
1446 | if (!csr->ops->get_max_rom) { | 1431 | /* |
1447 | csr->max_rom = mr_map[0]; /* default value */ | 1432 | * There has been a buggy firmware with bus_info_block.max_rom > 0 |
1448 | } else { | 1433 | * spotted which actually only supported quadlet read requests to the |
1449 | int i = csr->ops->get_max_rom(csr->bus_info_data, | 1434 | * config ROM. Therefore read everything quadlet by quadlet regardless |
1450 | csr->private); | 1435 | * of what the bus info block says. |
1451 | if (i & ~0x3) | 1436 | */ |
1452 | return -EINVAL; | 1437 | csr->max_rom = 4; |
1453 | csr->max_rom = mr_map[i]; | ||
1454 | } | ||
1455 | 1438 | ||
1456 | csr->cache_head->layout_head = csr->root_kv; | 1439 | csr->cache_head->layout_head = csr->root_kv; |
1457 | csr->cache_head->layout_tail = csr->root_kv; | 1440 | csr->cache_head->layout_tail = csr->root_kv; |
diff --git a/drivers/ieee1394/csr1212.h b/drivers/ieee1394/csr1212.h index 043039fc63ec..a892d922dbc9 100644 --- a/drivers/ieee1394/csr1212.h +++ b/drivers/ieee1394/csr1212.h | |||
@@ -181,7 +181,7 @@ struct csr1212_csr_rom_cache { | |||
181 | struct csr1212_csr { | 181 | struct csr1212_csr { |
182 | size_t bus_info_len; /* bus info block length in bytes */ | 182 | size_t bus_info_len; /* bus info block length in bytes */ |
183 | size_t crc_len; /* crc length in bytes */ | 183 | size_t crc_len; /* crc length in bytes */ |
184 | u32 *bus_info_data; /* bus info data incl bus name and EUI */ | 184 | __be32 *bus_info_data; /* bus info data incl bus name and EUI */ |
185 | 185 | ||
186 | void *private; /* private, bus specific data */ | 186 | void *private; /* private, bus specific data */ |
187 | struct csr1212_bus_ops *ops; | 187 | struct csr1212_bus_ops *ops; |
@@ -200,7 +200,7 @@ struct csr1212_bus_ops { | |||
200 | * entries located in the Units Space. Must return 0 on success | 200 | * entries located in the Units Space. Must return 0 on success |
201 | * anything else indicates an error. */ | 201 | * anything else indicates an error. */ |
202 | int (*bus_read) (struct csr1212_csr *csr, u64 addr, | 202 | int (*bus_read) (struct csr1212_csr *csr, u64 addr, |
203 | u16 length, void *buffer, void *private); | 203 | void *buffer, void *private); |
204 | 204 | ||
205 | /* This function is used by csr1212 to allocate a region in units space | 205 | /* This function is used by csr1212 to allocate a region in units space |
206 | * in the event that Config ROM entries don't all fit in the predefined | 206 | * in the event that Config ROM entries don't all fit in the predefined |
@@ -211,11 +211,6 @@ struct csr1212_bus_ops { | |||
211 | /* This function is used by csr1212 to release a region in units space | 211 | /* This function is used by csr1212 to release a region in units space |
212 | * that is no longer needed. */ | 212 | * that is no longer needed. */ |
213 | void (*release_addr) (u64 addr, void *private); | 213 | void (*release_addr) (u64 addr, void *private); |
214 | |||
215 | /* This function is used by csr1212 to determine the max read request | ||
216 | * supported by a remote node when reading the ConfigROM space. Must | ||
217 | * return 0, 1, or 2 per IEEE 1212. */ | ||
218 | int (*get_max_rom) (u32 *bus_info, void *private); | ||
219 | }; | 214 | }; |
220 | 215 | ||
221 | 216 | ||
diff --git a/drivers/ieee1394/dv1394-private.h b/drivers/ieee1394/dv1394-private.h index 7d1d2845b420..18b92cbf4a9f 100644 --- a/drivers/ieee1394/dv1394-private.h +++ b/drivers/ieee1394/dv1394-private.h | |||
@@ -77,11 +77,11 @@ static inline void fill_cip_header(struct CIP_header *cip, | |||
77 | See the Texas Instruments OHCI 1394 chipset documentation. | 77 | See the Texas Instruments OHCI 1394 chipset documentation. |
78 | */ | 78 | */ |
79 | 79 | ||
80 | struct output_more_immediate { u32 q[8]; }; | 80 | struct output_more_immediate { __le32 q[8]; }; |
81 | struct output_more { u32 q[4]; }; | 81 | struct output_more { __le32 q[4]; }; |
82 | struct output_last { u32 q[4]; }; | 82 | struct output_last { __le32 q[4]; }; |
83 | struct input_more { u32 q[4]; }; | 83 | struct input_more { __le32 q[4]; }; |
84 | struct input_last { u32 q[4]; }; | 84 | struct input_last { __le32 q[4]; }; |
85 | 85 | ||
86 | /* outputs */ | 86 | /* outputs */ |
87 | 87 | ||
@@ -92,9 +92,9 @@ static inline void fill_output_more_immediate(struct output_more_immediate *omi, | |||
92 | unsigned int payload_size) | 92 | unsigned int payload_size) |
93 | { | 93 | { |
94 | omi->q[0] = cpu_to_le32(0x02000000 | 8); /* OUTPUT_MORE_IMMEDIATE; 8 is the size of the IT header */ | 94 | omi->q[0] = cpu_to_le32(0x02000000 | 8); /* OUTPUT_MORE_IMMEDIATE; 8 is the size of the IT header */ |
95 | omi->q[1] = 0; | 95 | omi->q[1] = cpu_to_le32(0); |
96 | omi->q[2] = 0; | 96 | omi->q[2] = cpu_to_le32(0); |
97 | omi->q[3] = 0; | 97 | omi->q[3] = cpu_to_le32(0); |
98 | 98 | ||
99 | /* IT packet header */ | 99 | /* IT packet header */ |
100 | omi->q[4] = cpu_to_le32( (0x0 << 16) /* IEEE1394_SPEED_100 */ | 100 | omi->q[4] = cpu_to_le32( (0x0 << 16) /* IEEE1394_SPEED_100 */ |
@@ -106,8 +106,8 @@ static inline void fill_output_more_immediate(struct output_more_immediate *omi, | |||
106 | /* reserved field; mimic behavior of my Sony DSR-40 */ | 106 | /* reserved field; mimic behavior of my Sony DSR-40 */ |
107 | omi->q[5] = cpu_to_le32((payload_size << 16) | (0x7F << 8) | 0xA0); | 107 | omi->q[5] = cpu_to_le32((payload_size << 16) | (0x7F << 8) | 0xA0); |
108 | 108 | ||
109 | omi->q[6] = 0; | 109 | omi->q[6] = cpu_to_le32(0); |
110 | omi->q[7] = 0; | 110 | omi->q[7] = cpu_to_le32(0); |
111 | } | 111 | } |
112 | 112 | ||
113 | static inline void fill_output_more(struct output_more *om, | 113 | static inline void fill_output_more(struct output_more *om, |
@@ -116,8 +116,8 @@ static inline void fill_output_more(struct output_more *om, | |||
116 | { | 116 | { |
117 | om->q[0] = cpu_to_le32(data_size); | 117 | om->q[0] = cpu_to_le32(data_size); |
118 | om->q[1] = cpu_to_le32(data_phys_addr); | 118 | om->q[1] = cpu_to_le32(data_phys_addr); |
119 | om->q[2] = 0; | 119 | om->q[2] = cpu_to_le32(0); |
120 | om->q[3] = 0; | 120 | om->q[3] = cpu_to_le32(0); |
121 | } | 121 | } |
122 | 122 | ||
123 | static inline void fill_output_last(struct output_last *ol, | 123 | static inline void fill_output_last(struct output_last *ol, |
@@ -140,8 +140,8 @@ static inline void fill_output_last(struct output_last *ol, | |||
140 | 140 | ||
141 | ol->q[0] = cpu_to_le32(temp); | 141 | ol->q[0] = cpu_to_le32(temp); |
142 | ol->q[1] = cpu_to_le32(data_phys_addr); | 142 | ol->q[1] = cpu_to_le32(data_phys_addr); |
143 | ol->q[2] = 0; | 143 | ol->q[2] = cpu_to_le32(0); |
144 | ol->q[3] = 0; | 144 | ol->q[3] = cpu_to_le32(0); |
145 | } | 145 | } |
146 | 146 | ||
147 | /* inputs */ | 147 | /* inputs */ |
@@ -161,8 +161,8 @@ static inline void fill_input_more(struct input_more *im, | |||
161 | 161 | ||
162 | im->q[0] = cpu_to_le32(temp); | 162 | im->q[0] = cpu_to_le32(temp); |
163 | im->q[1] = cpu_to_le32(data_phys_addr); | 163 | im->q[1] = cpu_to_le32(data_phys_addr); |
164 | im->q[2] = 0; /* branchAddress and Z not use in packet-per-buffer mode */ | 164 | im->q[2] = cpu_to_le32(0); /* branchAddress and Z not use in packet-per-buffer mode */ |
165 | im->q[3] = 0; /* xferStatus & resCount, resCount must be initialize to data_size */ | 165 | im->q[3] = cpu_to_le32(0); /* xferStatus & resCount, resCount must be initialize to data_size */ |
166 | } | 166 | } |
167 | 167 | ||
168 | static inline void fill_input_last(struct input_last *il, | 168 | static inline void fill_input_last(struct input_last *il, |
@@ -331,7 +331,7 @@ struct frame { | |||
331 | 331 | ||
332 | /* points to status/timestamp field of first DMA packet */ | 332 | /* points to status/timestamp field of first DMA packet */ |
333 | /* (we'll check it later to monitor timestamp accuracy) */ | 333 | /* (we'll check it later to monitor timestamp accuracy) */ |
334 | u32 *frame_begin_timestamp; | 334 | __le32 *frame_begin_timestamp; |
335 | 335 | ||
336 | /* the timestamp we assigned to the first packet in the frame */ | 336 | /* the timestamp we assigned to the first packet in the frame */ |
337 | u32 assigned_timestamp; | 337 | u32 assigned_timestamp; |
@@ -348,15 +348,15 @@ struct frame { | |||
348 | that can cause interrupts. We'll check these from the | 348 | that can cause interrupts. We'll check these from the |
349 | interrupt handler. | 349 | interrupt handler. |
350 | */ | 350 | */ |
351 | u32 *mid_frame_timestamp; | 351 | __le32 *mid_frame_timestamp; |
352 | u32 *frame_end_timestamp; | 352 | __le32 *frame_end_timestamp; |
353 | 353 | ||
354 | /* branch address field of final packet. This is effectively | 354 | /* branch address field of final packet. This is effectively |
355 | the "tail" in the chain of DMA descriptor blocks. | 355 | the "tail" in the chain of DMA descriptor blocks. |
356 | We will fill it with the address of the first DMA descriptor | 356 | We will fill it with the address of the first DMA descriptor |
357 | block in the subsequent frame, once it is ready. | 357 | block in the subsequent frame, once it is ready. |
358 | */ | 358 | */ |
359 | u32 *frame_end_branch; | 359 | __le32 *frame_end_branch; |
360 | 360 | ||
361 | /* the number of descriptors in the first descriptor block | 361 | /* the number of descriptors in the first descriptor block |
362 | of the frame. Needed to start DMA */ | 362 | of the frame. Needed to start DMA */ |
@@ -365,10 +365,10 @@ struct frame { | |||
365 | 365 | ||
366 | 366 | ||
367 | struct packet { | 367 | struct packet { |
368 | u16 timestamp; | 368 | __le16 timestamp; |
369 | u16 invalid; | 369 | u16 invalid; |
370 | u16 iso_header; | 370 | u16 iso_header; |
371 | u16 data_length; | 371 | __le16 data_length; |
372 | u32 cip_h1; | 372 | u32 cip_h1; |
373 | u32 cip_h2; | 373 | u32 cip_h2; |
374 | unsigned char data[480]; | 374 | unsigned char data[480]; |
diff --git a/drivers/ieee1394/dv1394.c b/drivers/ieee1394/dv1394.c index c19f23267157..a329e6bd5d2d 100644 --- a/drivers/ieee1394/dv1394.c +++ b/drivers/ieee1394/dv1394.c | |||
@@ -265,7 +265,7 @@ static void frame_prepare(struct video_card *video, unsigned int this_frame) | |||
265 | /* these flags denote packets that need special attention */ | 265 | /* these flags denote packets that need special attention */ |
266 | int empty_packet, first_packet, last_packet, mid_packet; | 266 | int empty_packet, first_packet, last_packet, mid_packet; |
267 | 267 | ||
268 | u32 *branch_address, *last_branch_address = NULL; | 268 | __le32 *branch_address, *last_branch_address = NULL; |
269 | unsigned long data_p; | 269 | unsigned long data_p; |
270 | int first_packet_empty = 0; | 270 | int first_packet_empty = 0; |
271 | u32 cycleTimer, ct_sec, ct_cyc, ct_off; | 271 | u32 cycleTimer, ct_sec, ct_cyc, ct_off; |
@@ -848,7 +848,7 @@ static void receive_packets(struct video_card *video) | |||
848 | dma_addr_t block_dma = 0; | 848 | dma_addr_t block_dma = 0; |
849 | struct packet *data = NULL; | 849 | struct packet *data = NULL; |
850 | dma_addr_t data_dma = 0; | 850 | dma_addr_t data_dma = 0; |
851 | u32 *last_branch_address = NULL; | 851 | __le32 *last_branch_address = NULL; |
852 | unsigned long irq_flags; | 852 | unsigned long irq_flags; |
853 | int want_interrupt = 0; | 853 | int want_interrupt = 0; |
854 | struct frame *f = NULL; | 854 | struct frame *f = NULL; |
@@ -2110,17 +2110,17 @@ static void ir_tasklet_func(unsigned long data) | |||
2110 | f = video->frames[next_i / MAX_PACKETS]; | 2110 | f = video->frames[next_i / MAX_PACKETS]; |
2111 | next = &(f->descriptor_pool[next_i % MAX_PACKETS]); | 2111 | next = &(f->descriptor_pool[next_i % MAX_PACKETS]); |
2112 | next_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma; | 2112 | next_dma = ((unsigned long) block - (unsigned long) f->descriptor_pool) + f->descriptor_pool_dma; |
2113 | next->u.in.il.q[0] |= 3 << 20; /* enable interrupt */ | 2113 | next->u.in.il.q[0] |= cpu_to_le32(3 << 20); /* enable interrupt */ |
2114 | next->u.in.il.q[2] = 0; /* disable branch */ | 2114 | next->u.in.il.q[2] = cpu_to_le32(0); /* disable branch */ |
2115 | 2115 | ||
2116 | /* link previous to next */ | 2116 | /* link previous to next */ |
2117 | prev_i = (next_i == 0) ? (MAX_PACKETS * video->n_frames - 1) : (next_i - 1); | 2117 | prev_i = (next_i == 0) ? (MAX_PACKETS * video->n_frames - 1) : (next_i - 1); |
2118 | f = video->frames[prev_i / MAX_PACKETS]; | 2118 | f = video->frames[prev_i / MAX_PACKETS]; |
2119 | prev = &(f->descriptor_pool[prev_i % MAX_PACKETS]); | 2119 | prev = &(f->descriptor_pool[prev_i % MAX_PACKETS]); |
2120 | if (prev_i % (MAX_PACKETS/2)) { | 2120 | if (prev_i % (MAX_PACKETS/2)) { |
2121 | prev->u.in.il.q[0] &= ~(3 << 20); /* no interrupt */ | 2121 | prev->u.in.il.q[0] &= ~cpu_to_le32(3 << 20); /* no interrupt */ |
2122 | } else { | 2122 | } else { |
2123 | prev->u.in.il.q[0] |= 3 << 20; /* enable interrupt */ | 2123 | prev->u.in.il.q[0] |= cpu_to_le32(3 << 20); /* enable interrupt */ |
2124 | } | 2124 | } |
2125 | prev->u.in.il.q[2] = cpu_to_le32(next_dma | 1); /* set Z=1 */ | 2125 | prev->u.in.il.q[2] = cpu_to_le32(next_dma | 1); /* set Z=1 */ |
2126 | wmb(); | 2126 | wmb(); |
diff --git a/drivers/ieee1394/eth1394.c b/drivers/ieee1394/eth1394.c index 930d47f053cf..1a919df809f8 100644 --- a/drivers/ieee1394/eth1394.c +++ b/drivers/ieee1394/eth1394.c | |||
@@ -92,7 +92,7 @@ struct partial_datagram { | |||
92 | struct list_head list; | 92 | struct list_head list; |
93 | u16 dgl; | 93 | u16 dgl; |
94 | u16 dg_size; | 94 | u16 dg_size; |
95 | u16 ether_type; | 95 | __be16 ether_type; |
96 | struct sk_buff *skb; | 96 | struct sk_buff *skb; |
97 | char *pbuf; | 97 | char *pbuf; |
98 | struct list_head frag_info; | 98 | struct list_head frag_info; |
@@ -181,7 +181,7 @@ static void ether1394_remove_host(struct hpsb_host *host); | |||
181 | static void ether1394_host_reset(struct hpsb_host *host); | 181 | static void ether1394_host_reset(struct hpsb_host *host); |
182 | 182 | ||
183 | /* Function for incoming 1394 packets */ | 183 | /* Function for incoming 1394 packets */ |
184 | static struct hpsb_address_ops addr_ops = { | 184 | const static struct hpsb_address_ops addr_ops = { |
185 | .write = ether1394_write, | 185 | .write = ether1394_write, |
186 | }; | 186 | }; |
187 | 187 | ||
@@ -764,7 +764,7 @@ static int ether1394_header_parse(const struct sk_buff *skb, | |||
764 | static int ether1394_header_cache(const struct neighbour *neigh, | 764 | static int ether1394_header_cache(const struct neighbour *neigh, |
765 | struct hh_cache *hh) | 765 | struct hh_cache *hh) |
766 | { | 766 | { |
767 | unsigned short type = hh->hh_type; | 767 | __be16 type = hh->hh_type; |
768 | struct net_device *dev = neigh->dev; | 768 | struct net_device *dev = neigh->dev; |
769 | struct eth1394hdr *eth = | 769 | struct eth1394hdr *eth = |
770 | (struct eth1394hdr *)((u8 *)hh->hh_data + 16 - ETH1394_HLEN); | 770 | (struct eth1394hdr *)((u8 *)hh->hh_data + 16 - ETH1394_HLEN); |
@@ -792,7 +792,7 @@ static void ether1394_header_cache_update(struct hh_cache *hh, | |||
792 | ******************************************/ | 792 | ******************************************/ |
793 | 793 | ||
794 | /* Copied from net/ethernet/eth.c */ | 794 | /* Copied from net/ethernet/eth.c */ |
795 | static u16 ether1394_type_trans(struct sk_buff *skb, struct net_device *dev) | 795 | static __be16 ether1394_type_trans(struct sk_buff *skb, struct net_device *dev) |
796 | { | 796 | { |
797 | struct eth1394hdr *eth; | 797 | struct eth1394hdr *eth; |
798 | unsigned char *rawp; | 798 | unsigned char *rawp; |
@@ -826,17 +826,17 @@ static u16 ether1394_type_trans(struct sk_buff *skb, struct net_device *dev) | |||
826 | 826 | ||
827 | /* Parse an encapsulated IP1394 header into an ethernet frame packet. | 827 | /* Parse an encapsulated IP1394 header into an ethernet frame packet. |
828 | * We also perform ARP translation here, if need be. */ | 828 | * We also perform ARP translation here, if need be. */ |
829 | static u16 ether1394_parse_encap(struct sk_buff *skb, struct net_device *dev, | 829 | static __be16 ether1394_parse_encap(struct sk_buff *skb, struct net_device *dev, |
830 | nodeid_t srcid, nodeid_t destid, | 830 | nodeid_t srcid, nodeid_t destid, |
831 | u16 ether_type) | 831 | __be16 ether_type) |
832 | { | 832 | { |
833 | struct eth1394_priv *priv = netdev_priv(dev); | 833 | struct eth1394_priv *priv = netdev_priv(dev); |
834 | u64 dest_hw; | 834 | __be64 dest_hw; |
835 | unsigned short ret = 0; | 835 | __be16 ret = 0; |
836 | 836 | ||
837 | /* Setup our hw addresses. We use these to build the ethernet header. */ | 837 | /* Setup our hw addresses. We use these to build the ethernet header. */ |
838 | if (destid == (LOCAL_BUS | ALL_NODES)) | 838 | if (destid == (LOCAL_BUS | ALL_NODES)) |
839 | dest_hw = ~0ULL; /* broadcast */ | 839 | dest_hw = ~cpu_to_be64(0); /* broadcast */ |
840 | else | 840 | else |
841 | dest_hw = cpu_to_be64((u64)priv->host->csr.guid_hi << 32 | | 841 | dest_hw = cpu_to_be64((u64)priv->host->csr.guid_hi << 32 | |
842 | priv->host->csr.guid_lo); | 842 | priv->host->csr.guid_lo); |
@@ -870,7 +870,7 @@ static u16 ether1394_parse_encap(struct sk_buff *skb, struct net_device *dev, | |||
870 | node = eth1394_find_node_guid(&priv->ip_node_list, | 870 | node = eth1394_find_node_guid(&priv->ip_node_list, |
871 | be64_to_cpu(guid)); | 871 | be64_to_cpu(guid)); |
872 | if (!node) | 872 | if (!node) |
873 | return 0; | 873 | return cpu_to_be16(0); |
874 | 874 | ||
875 | node_info = | 875 | node_info = |
876 | (struct eth1394_node_info *)node->ud->device.driver_data; | 876 | (struct eth1394_node_info *)node->ud->device.driver_data; |
@@ -1060,7 +1060,7 @@ static int ether1394_data_handler(struct net_device *dev, int srcid, int destid, | |||
1060 | unsigned long flags; | 1060 | unsigned long flags; |
1061 | struct eth1394_priv *priv = netdev_priv(dev); | 1061 | struct eth1394_priv *priv = netdev_priv(dev); |
1062 | union eth1394_hdr *hdr = (union eth1394_hdr *)buf; | 1062 | union eth1394_hdr *hdr = (union eth1394_hdr *)buf; |
1063 | u16 ether_type = 0; /* initialized to clear warning */ | 1063 | __be16 ether_type = cpu_to_be16(0); /* initialized to clear warning */ |
1064 | int hdr_len; | 1064 | int hdr_len; |
1065 | struct unit_directory *ud = priv->ud_list[NODEID_TO_NODE(srcid)]; | 1065 | struct unit_directory *ud = priv->ud_list[NODEID_TO_NODE(srcid)]; |
1066 | struct eth1394_node_info *node_info; | 1066 | struct eth1394_node_info *node_info; |
@@ -1254,7 +1254,7 @@ static int ether1394_write(struct hpsb_host *host, int srcid, int destid, | |||
1254 | 1254 | ||
1255 | static void ether1394_iso(struct hpsb_iso *iso) | 1255 | static void ether1394_iso(struct hpsb_iso *iso) |
1256 | { | 1256 | { |
1257 | quadlet_t *data; | 1257 | __be32 *data; |
1258 | char *buf; | 1258 | char *buf; |
1259 | struct eth1394_host_info *hi; | 1259 | struct eth1394_host_info *hi; |
1260 | struct net_device *dev; | 1260 | struct net_device *dev; |
@@ -1278,7 +1278,7 @@ static void ether1394_iso(struct hpsb_iso *iso) | |||
1278 | for (i = 0; i < nready; i++) { | 1278 | for (i = 0; i < nready; i++) { |
1279 | struct hpsb_iso_packet_info *info = | 1279 | struct hpsb_iso_packet_info *info = |
1280 | &iso->infos[(iso->first_packet + i) % iso->buf_packets]; | 1280 | &iso->infos[(iso->first_packet + i) % iso->buf_packets]; |
1281 | data = (quadlet_t *)(iso->data_buf.kvirt + info->offset); | 1281 | data = (__be32 *)(iso->data_buf.kvirt + info->offset); |
1282 | 1282 | ||
1283 | /* skip over GASP header */ | 1283 | /* skip over GASP header */ |
1284 | buf = (char *)data + 8; | 1284 | buf = (char *)data + 8; |
@@ -1610,7 +1610,7 @@ static int ether1394_tx(struct sk_buff *skb, struct net_device *dev) | |||
1610 | if (max_payload < dg_size + hdr_type_len[ETH1394_HDR_LF_UF]) | 1610 | if (max_payload < dg_size + hdr_type_len[ETH1394_HDR_LF_UF]) |
1611 | priv->bc_dgl++; | 1611 | priv->bc_dgl++; |
1612 | } else { | 1612 | } else { |
1613 | __be64 guid = get_unaligned((u64 *)hdr_buf.h_dest); | 1613 | __be64 guid = get_unaligned((__be64 *)hdr_buf.h_dest); |
1614 | 1614 | ||
1615 | node = eth1394_find_node_guid(&priv->ip_node_list, | 1615 | node = eth1394_find_node_guid(&priv->ip_node_list, |
1616 | be64_to_cpu(guid)); | 1616 | be64_to_cpu(guid)); |
diff --git a/drivers/ieee1394/eth1394.h b/drivers/ieee1394/eth1394.h index c5bd29ab6056..d53bac47b86f 100644 --- a/drivers/ieee1394/eth1394.h +++ b/drivers/ieee1394/eth1394.h | |||
@@ -81,7 +81,7 @@ struct eth1394_priv { | |||
81 | 81 | ||
82 | struct eth1394hdr { | 82 | struct eth1394hdr { |
83 | unsigned char h_dest[ETH1394_ALEN]; /* destination eth1394 addr */ | 83 | unsigned char h_dest[ETH1394_ALEN]; /* destination eth1394 addr */ |
84 | unsigned short h_proto; /* packet type ID field */ | 84 | __be16 h_proto; /* packet type ID field */ |
85 | } __attribute__((packed)); | 85 | } __attribute__((packed)); |
86 | 86 | ||
87 | static inline struct eth1394hdr *eth1394_hdr(const struct sk_buff *skb) | 87 | static inline struct eth1394hdr *eth1394_hdr(const struct sk_buff *skb) |
@@ -98,13 +98,13 @@ typedef enum {ETH1394_GASP, ETH1394_WRREQ} eth1394_tx_type; | |||
98 | struct eth1394_uf_hdr { | 98 | struct eth1394_uf_hdr { |
99 | u16 lf:2; | 99 | u16 lf:2; |
100 | u16 res:14; | 100 | u16 res:14; |
101 | u16 ether_type; /* Ethernet packet type */ | 101 | __be16 ether_type; /* Ethernet packet type */ |
102 | } __attribute__((packed)); | 102 | } __attribute__((packed)); |
103 | #elif defined __LITTLE_ENDIAN_BITFIELD | 103 | #elif defined __LITTLE_ENDIAN_BITFIELD |
104 | struct eth1394_uf_hdr { | 104 | struct eth1394_uf_hdr { |
105 | u16 res:14; | 105 | u16 res:14; |
106 | u16 lf:2; | 106 | u16 lf:2; |
107 | u16 ether_type; | 107 | __be16 ether_type; |
108 | } __attribute__((packed)); | 108 | } __attribute__((packed)); |
109 | #else | 109 | #else |
110 | #error Unknown bit field type | 110 | #error Unknown bit field type |
@@ -116,7 +116,7 @@ struct eth1394_ff_hdr { | |||
116 | u16 lf:2; | 116 | u16 lf:2; |
117 | u16 res1:2; | 117 | u16 res1:2; |
118 | u16 dg_size:12; /* Datagram size */ | 118 | u16 dg_size:12; /* Datagram size */ |
119 | u16 ether_type; /* Ethernet packet type */ | 119 | __be16 ether_type; /* Ethernet packet type */ |
120 | u16 dgl; /* Datagram label */ | 120 | u16 dgl; /* Datagram label */ |
121 | u16 res2; | 121 | u16 res2; |
122 | } __attribute__((packed)); | 122 | } __attribute__((packed)); |
@@ -125,7 +125,7 @@ struct eth1394_ff_hdr { | |||
125 | u16 dg_size:12; | 125 | u16 dg_size:12; |
126 | u16 res1:2; | 126 | u16 res1:2; |
127 | u16 lf:2; | 127 | u16 lf:2; |
128 | u16 ether_type; | 128 | __be16 ether_type; |
129 | u16 dgl; | 129 | u16 dgl; |
130 | u16 res2; | 130 | u16 res2; |
131 | } __attribute__((packed)); | 131 | } __attribute__((packed)); |
@@ -206,11 +206,11 @@ struct eth1394_arp { | |||
206 | u16 opcode; /* ARP Opcode */ | 206 | u16 opcode; /* ARP Opcode */ |
207 | /* Above is exactly the same format as struct arphdr */ | 207 | /* Above is exactly the same format as struct arphdr */ |
208 | 208 | ||
209 | u64 s_uniq_id; /* Sender's 64bit EUI */ | 209 | __be64 s_uniq_id; /* Sender's 64bit EUI */ |
210 | u8 max_rec; /* Sender's max packet size */ | 210 | u8 max_rec; /* Sender's max packet size */ |
211 | u8 sspd; /* Sender's max speed */ | 211 | u8 sspd; /* Sender's max speed */ |
212 | u16 fifo_hi; /* hi 16bits of sender's FIFO addr */ | 212 | __be16 fifo_hi; /* hi 16bits of sender's FIFO addr */ |
213 | u32 fifo_lo; /* lo 32bits of sender's FIFO addr */ | 213 | __be32 fifo_lo; /* lo 32bits of sender's FIFO addr */ |
214 | u32 sip; /* Sender's IP Address */ | 214 | u32 sip; /* Sender's IP Address */ |
215 | u32 tip; /* IP Address of requested hw addr */ | 215 | u32 tip; /* IP Address of requested hw addr */ |
216 | }; | 216 | }; |
diff --git a/drivers/ieee1394/highlevel.c b/drivers/ieee1394/highlevel.c index 272543a42a43..600e391c8fe7 100644 --- a/drivers/ieee1394/highlevel.c +++ b/drivers/ieee1394/highlevel.c | |||
@@ -320,7 +320,7 @@ void hpsb_unregister_highlevel(struct hpsb_highlevel *hl) | |||
320 | */ | 320 | */ |
321 | u64 hpsb_allocate_and_register_addrspace(struct hpsb_highlevel *hl, | 321 | u64 hpsb_allocate_and_register_addrspace(struct hpsb_highlevel *hl, |
322 | struct hpsb_host *host, | 322 | struct hpsb_host *host, |
323 | struct hpsb_address_ops *ops, | 323 | const struct hpsb_address_ops *ops, |
324 | u64 size, u64 alignment, | 324 | u64 size, u64 alignment, |
325 | u64 start, u64 end) | 325 | u64 start, u64 end) |
326 | { | 326 | { |
@@ -407,7 +407,8 @@ u64 hpsb_allocate_and_register_addrspace(struct hpsb_highlevel *hl, | |||
407 | * are automatically deallocated together with the hpsb_highlevel @hl. | 407 | * are automatically deallocated together with the hpsb_highlevel @hl. |
408 | */ | 408 | */ |
409 | int hpsb_register_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, | 409 | int hpsb_register_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, |
410 | struct hpsb_address_ops *ops, u64 start, u64 end) | 410 | const struct hpsb_address_ops *ops, |
411 | u64 start, u64 end) | ||
411 | { | 412 | { |
412 | struct hpsb_address_serve *as; | 413 | struct hpsb_address_serve *as; |
413 | struct list_head *lh; | 414 | struct list_head *lh; |
@@ -420,7 +421,7 @@ int hpsb_register_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, | |||
420 | return 0; | 421 | return 0; |
421 | } | 422 | } |
422 | 423 | ||
423 | as = kmalloc(sizeof(*as), GFP_ATOMIC); | 424 | as = kmalloc(sizeof(*as), GFP_KERNEL); |
424 | if (!as) | 425 | if (!as) |
425 | return 0; | 426 | return 0; |
426 | 427 | ||
@@ -477,7 +478,7 @@ int hpsb_unregister_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, | |||
477 | return retval; | 478 | return retval; |
478 | } | 479 | } |
479 | 480 | ||
480 | static struct hpsb_address_ops dummy_ops; | 481 | const static struct hpsb_address_ops dummy_ops; |
481 | 482 | ||
482 | /* dummy address spaces as lower and upper bounds of the host's a.s. list */ | 483 | /* dummy address spaces as lower and upper bounds of the host's a.s. list */ |
483 | static void init_hpsb_highlevel(struct hpsb_host *host) | 484 | static void init_hpsb_highlevel(struct hpsb_host *host) |
diff --git a/drivers/ieee1394/highlevel.h b/drivers/ieee1394/highlevel.h index bc5d0854c17e..9dba89fc60ad 100644 --- a/drivers/ieee1394/highlevel.h +++ b/drivers/ieee1394/highlevel.h | |||
@@ -15,7 +15,7 @@ struct hpsb_host; | |||
15 | struct hpsb_address_serve { | 15 | struct hpsb_address_serve { |
16 | struct list_head host_list; /* per host list */ | 16 | struct list_head host_list; /* per host list */ |
17 | struct list_head hl_list; /* hpsb_highlevel list */ | 17 | struct list_head hl_list; /* hpsb_highlevel list */ |
18 | struct hpsb_address_ops *op; | 18 | const struct hpsb_address_ops *op; |
19 | struct hpsb_host *host; | 19 | struct hpsb_host *host; |
20 | u64 start; /* first address handled, quadlet aligned */ | 20 | u64 start; /* first address handled, quadlet aligned */ |
21 | u64 end; /* first address behind, quadlet aligned */ | 21 | u64 end; /* first address behind, quadlet aligned */ |
@@ -119,11 +119,12 @@ void hpsb_unregister_highlevel(struct hpsb_highlevel *hl); | |||
119 | 119 | ||
120 | u64 hpsb_allocate_and_register_addrspace(struct hpsb_highlevel *hl, | 120 | u64 hpsb_allocate_and_register_addrspace(struct hpsb_highlevel *hl, |
121 | struct hpsb_host *host, | 121 | struct hpsb_host *host, |
122 | struct hpsb_address_ops *ops, | 122 | const struct hpsb_address_ops *ops, |
123 | u64 size, u64 alignment, | 123 | u64 size, u64 alignment, |
124 | u64 start, u64 end); | 124 | u64 start, u64 end); |
125 | int hpsb_register_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, | 125 | int hpsb_register_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, |
126 | struct hpsb_address_ops *ops, u64 start, u64 end); | 126 | const struct hpsb_address_ops *ops, |
127 | u64 start, u64 end); | ||
127 | int hpsb_unregister_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, | 128 | int hpsb_unregister_addrspace(struct hpsb_highlevel *hl, struct hpsb_host *host, |
128 | u64 start); | 129 | u64 start); |
129 | 130 | ||
diff --git a/drivers/ieee1394/hosts.c b/drivers/ieee1394/hosts.c index 237d0c9d69c6..e947d8ffac85 100644 --- a/drivers/ieee1394/hosts.c +++ b/drivers/ieee1394/hosts.c | |||
@@ -34,18 +34,18 @@ static void delayed_reset_bus(struct work_struct *work) | |||
34 | { | 34 | { |
35 | struct hpsb_host *host = | 35 | struct hpsb_host *host = |
36 | container_of(work, struct hpsb_host, delayed_reset.work); | 36 | container_of(work, struct hpsb_host, delayed_reset.work); |
37 | int generation = host->csr.generation + 1; | 37 | u8 generation = host->csr.generation + 1; |
38 | 38 | ||
39 | /* The generation field rolls over to 2 rather than 0 per IEEE | 39 | /* The generation field rolls over to 2 rather than 0 per IEEE |
40 | * 1394a-2000. */ | 40 | * 1394a-2000. */ |
41 | if (generation > 0xf || generation < 2) | 41 | if (generation > 0xf || generation < 2) |
42 | generation = 2; | 42 | generation = 2; |
43 | 43 | ||
44 | CSR_SET_BUS_INFO_GENERATION(host->csr.rom, generation); | 44 | csr_set_bus_info_generation(host->csr.rom, generation); |
45 | if (csr1212_generate_csr_image(host->csr.rom) != CSR1212_SUCCESS) { | 45 | if (csr1212_generate_csr_image(host->csr.rom) != CSR1212_SUCCESS) { |
46 | /* CSR image creation failed. | 46 | /* CSR image creation failed. |
47 | * Reset generation field and do not issue a bus reset. */ | 47 | * Reset generation field and do not issue a bus reset. */ |
48 | CSR_SET_BUS_INFO_GENERATION(host->csr.rom, | 48 | csr_set_bus_info_generation(host->csr.rom, |
49 | host->csr.generation); | 49 | host->csr.generation); |
50 | return; | 50 | return; |
51 | } | 51 | } |
diff --git a/drivers/ieee1394/hosts.h b/drivers/ieee1394/hosts.h index dd229950acca..49c359022c54 100644 --- a/drivers/ieee1394/hosts.h +++ b/drivers/ieee1394/hosts.h | |||
@@ -154,7 +154,7 @@ struct hpsb_host_driver { | |||
154 | * to set the hardware ConfigROM if the hardware supports handling | 154 | * to set the hardware ConfigROM if the hardware supports handling |
155 | * reads to the ConfigROM on its own. */ | 155 | * reads to the ConfigROM on its own. */ |
156 | void (*set_hw_config_rom)(struct hpsb_host *host, | 156 | void (*set_hw_config_rom)(struct hpsb_host *host, |
157 | quadlet_t *config_rom); | 157 | __be32 *config_rom); |
158 | 158 | ||
159 | /* This function shall implement packet transmission based on | 159 | /* This function shall implement packet transmission based on |
160 | * packet->type. It shall CRC both parts of the packet (unless | 160 | * packet->type. It shall CRC both parts of the packet (unless |
diff --git a/drivers/ieee1394/ieee1394.h b/drivers/ieee1394/ieee1394.h index 40492074c013..e0ae0d3d747f 100644 --- a/drivers/ieee1394/ieee1394.h +++ b/drivers/ieee1394/ieee1394.h | |||
@@ -121,6 +121,9 @@ extern const char *hpsb_speedto_str[]; | |||
121 | 121 | ||
122 | #include <asm/byteorder.h> | 122 | #include <asm/byteorder.h> |
123 | 123 | ||
124 | /* '1' '3' '9' '4' in ASCII */ | ||
125 | #define IEEE1394_BUSID_MAGIC cpu_to_be32(0x31333934) | ||
126 | |||
124 | #ifdef __BIG_ENDIAN_BITFIELD | 127 | #ifdef __BIG_ENDIAN_BITFIELD |
125 | 128 | ||
126 | struct selfid { | 129 | struct selfid { |
diff --git a/drivers/ieee1394/nodemgr.c b/drivers/ieee1394/nodemgr.c index 79ef5fd928ae..906c5a98d814 100644 --- a/drivers/ieee1394/nodemgr.c +++ b/drivers/ieee1394/nodemgr.c | |||
@@ -67,7 +67,7 @@ static int nodemgr_check_speed(struct nodemgr_csr_info *ci, u64 addr, | |||
67 | for (i = IEEE1394_SPEED_100; i <= old_speed; i++) { | 67 | for (i = IEEE1394_SPEED_100; i <= old_speed; i++) { |
68 | *speed = i; | 68 | *speed = i; |
69 | error = hpsb_read(ci->host, ci->nodeid, ci->generation, addr, | 69 | error = hpsb_read(ci->host, ci->nodeid, ci->generation, addr, |
70 | &q, sizeof(quadlet_t)); | 70 | &q, 4); |
71 | if (error) | 71 | if (error) |
72 | break; | 72 | break; |
73 | *buffer = q; | 73 | *buffer = q; |
@@ -85,7 +85,7 @@ static int nodemgr_check_speed(struct nodemgr_csr_info *ci, u64 addr, | |||
85 | return error; | 85 | return error; |
86 | } | 86 | } |
87 | 87 | ||
88 | static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length, | 88 | static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, |
89 | void *buffer, void *__ci) | 89 | void *buffer, void *__ci) |
90 | { | 90 | { |
91 | struct nodemgr_csr_info *ci = (struct nodemgr_csr_info*)__ci; | 91 | struct nodemgr_csr_info *ci = (struct nodemgr_csr_info*)__ci; |
@@ -93,7 +93,7 @@ static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length, | |||
93 | 93 | ||
94 | for (i = 1; ; i++) { | 94 | for (i = 1; ; i++) { |
95 | error = hpsb_read(ci->host, ci->nodeid, ci->generation, addr, | 95 | error = hpsb_read(ci->host, ci->nodeid, ci->generation, addr, |
96 | buffer, length); | 96 | buffer, 4); |
97 | if (!error) { | 97 | if (!error) { |
98 | ci->speed_unverified = 0; | 98 | ci->speed_unverified = 0; |
99 | break; | 99 | break; |
@@ -104,7 +104,7 @@ static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length, | |||
104 | 104 | ||
105 | /* The ieee1394_core guessed the node's speed capability from | 105 | /* The ieee1394_core guessed the node's speed capability from |
106 | * the self ID. Check whether a lower speed works. */ | 106 | * the self ID. Check whether a lower speed works. */ |
107 | if (ci->speed_unverified && length == sizeof(quadlet_t)) { | 107 | if (ci->speed_unverified) { |
108 | error = nodemgr_check_speed(ci, addr, buffer); | 108 | error = nodemgr_check_speed(ci, addr, buffer); |
109 | if (!error) | 109 | if (!error) |
110 | break; | 110 | break; |
@@ -115,20 +115,8 @@ static int nodemgr_bus_read(struct csr1212_csr *csr, u64 addr, u16 length, | |||
115 | return error; | 115 | return error; |
116 | } | 116 | } |
117 | 117 | ||
118 | #define OUI_FREECOM_TECHNOLOGIES_GMBH 0x0001db | ||
119 | |||
120 | static int nodemgr_get_max_rom(quadlet_t *bus_info_data, void *__ci) | ||
121 | { | ||
122 | /* Freecom FireWire Hard Drive firmware bug */ | ||
123 | if (be32_to_cpu(bus_info_data[3]) >> 8 == OUI_FREECOM_TECHNOLOGIES_GMBH) | ||
124 | return 0; | ||
125 | |||
126 | return (be32_to_cpu(bus_info_data[2]) >> 8) & 0x3; | ||
127 | } | ||
128 | |||
129 | static struct csr1212_bus_ops nodemgr_csr_ops = { | 118 | static struct csr1212_bus_ops nodemgr_csr_ops = { |
130 | .bus_read = nodemgr_bus_read, | 119 | .bus_read = nodemgr_bus_read, |
131 | .get_max_rom = nodemgr_get_max_rom | ||
132 | }; | 120 | }; |
133 | 121 | ||
134 | 122 | ||
diff --git a/drivers/ieee1394/nodemgr.h b/drivers/ieee1394/nodemgr.h index 4f287a3561ba..15ea09733e84 100644 --- a/drivers/ieee1394/nodemgr.h +++ b/drivers/ieee1394/nodemgr.h | |||
@@ -31,9 +31,6 @@ struct csr1212_keyval; | |||
31 | struct hpsb_host; | 31 | struct hpsb_host; |
32 | struct ieee1394_device_id; | 32 | struct ieee1394_device_id; |
33 | 33 | ||
34 | /* '1' '3' '9' '4' in ASCII */ | ||
35 | #define IEEE1394_BUSID_MAGIC __constant_cpu_to_be32(0x31333934) | ||
36 | |||
37 | /* This is the start of a Node entry structure. It should be a stable API | 34 | /* This is the start of a Node entry structure. It should be a stable API |
38 | * for which to gather info from the Node Manager about devices attached | 35 | * for which to gather info from the Node Manager about devices attached |
39 | * to the bus. */ | 36 | * to the bus. */ |
diff --git a/drivers/ieee1394/ohci1394.c b/drivers/ieee1394/ohci1394.c index e509e13cb7a7..65c1429e4129 100644 --- a/drivers/ieee1394/ohci1394.c +++ b/drivers/ieee1394/ohci1394.c | |||
@@ -2973,7 +2973,7 @@ alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d, | |||
2973 | return 0; | 2973 | return 0; |
2974 | } | 2974 | } |
2975 | 2975 | ||
2976 | static void ohci_set_hw_config_rom(struct hpsb_host *host, quadlet_t *config_rom) | 2976 | static void ohci_set_hw_config_rom(struct hpsb_host *host, __be32 *config_rom) |
2977 | { | 2977 | { |
2978 | struct ti_ohci *ohci = host->hostdata; | 2978 | struct ti_ohci *ohci = host->hostdata; |
2979 | 2979 | ||
@@ -3199,15 +3199,16 @@ static int __devinit ohci1394_pci_probe(struct pci_dev *dev, | |||
3199 | /* Now enable LPS, which we need in order to start accessing | 3199 | /* Now enable LPS, which we need in order to start accessing |
3200 | * most of the registers. In fact, on some cards (ALI M5251), | 3200 | * most of the registers. In fact, on some cards (ALI M5251), |
3201 | * accessing registers in the SClk domain without LPS enabled | 3201 | * accessing registers in the SClk domain without LPS enabled |
3202 | * will lock up the machine. Wait 50msec to make sure we have | 3202 | * will lock up the machine. */ |
3203 | * full link enabled. */ | ||
3204 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); | 3203 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); |
3205 | 3204 | ||
3206 | /* Disable and clear interrupts */ | 3205 | /* Disable and clear interrupts */ |
3207 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); | 3206 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); |
3208 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); | 3207 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); |
3209 | 3208 | ||
3210 | mdelay(50); | 3209 | /* Flush MMIO writes and wait to make sure we have full link enabled. */ |
3210 | reg_read(ohci, OHCI1394_Version); | ||
3211 | msleep(50); | ||
3211 | 3212 | ||
3212 | /* Determine the number of available IR and IT contexts. */ | 3213 | /* Determine the number of available IR and IT contexts. */ |
3213 | ohci->nb_iso_rcv_ctx = | 3214 | ohci->nb_iso_rcv_ctx = |
@@ -3233,8 +3234,9 @@ static int __devinit ohci1394_pci_probe(struct pci_dev *dev, | |||
3233 | * we need to get to that "no event", so enough should be initialized | 3234 | * we need to get to that "no event", so enough should be initialized |
3234 | * by that point. | 3235 | * by that point. |
3235 | */ | 3236 | */ |
3236 | if (request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED, | 3237 | err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED, |
3237 | OHCI1394_DRIVER_NAME, ohci)) { | 3238 | OHCI1394_DRIVER_NAME, ohci); |
3239 | if (err) { | ||
3238 | PRINT_G(KERN_ERR, "Failed to allocate interrupt %d", dev->irq); | 3240 | PRINT_G(KERN_ERR, "Failed to allocate interrupt %d", dev->irq); |
3239 | goto err; | 3241 | goto err; |
3240 | } | 3242 | } |
@@ -3381,6 +3383,7 @@ static int ohci1394_pci_suspend(struct pci_dev *dev, pm_message_t state) | |||
3381 | ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT); | 3383 | ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT); |
3382 | ohci_soft_reset(ohci); | 3384 | ohci_soft_reset(ohci); |
3383 | 3385 | ||
3386 | free_irq(dev->irq, ohci); | ||
3384 | err = pci_save_state(dev); | 3387 | err = pci_save_state(dev); |
3385 | if (err) { | 3388 | if (err) { |
3386 | PRINT(KERN_ERR, "pci_save_state failed with %d", err); | 3389 | PRINT(KERN_ERR, "pci_save_state failed with %d", err); |
@@ -3420,7 +3423,16 @@ static int ohci1394_pci_resume(struct pci_dev *dev) | |||
3420 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); | 3423 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); |
3421 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); | 3424 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); |
3422 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); | 3425 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); |
3423 | mdelay(50); | 3426 | reg_read(ohci, OHCI1394_Version); |
3427 | msleep(50); | ||
3428 | |||
3429 | err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED, | ||
3430 | OHCI1394_DRIVER_NAME, ohci); | ||
3431 | if (err) { | ||
3432 | PRINT_G(KERN_ERR, "Failed to allocate interrupt %d", dev->irq); | ||
3433 | return err; | ||
3434 | } | ||
3435 | |||
3424 | ohci_initialize(ohci); | 3436 | ohci_initialize(ohci); |
3425 | 3437 | ||
3426 | hpsb_resume_host(ohci->host); | 3438 | hpsb_resume_host(ohci->host); |
diff --git a/drivers/ieee1394/pcilynx.c b/drivers/ieee1394/pcilynx.c index 7aee1ac97c80..dc15cadb06ef 100644 --- a/drivers/ieee1394/pcilynx.c +++ b/drivers/ieee1394/pcilynx.c | |||
@@ -1463,7 +1463,7 @@ static int __devinit add_card(struct pci_dev *dev, | |||
1463 | 1463 | ||
1464 | /* info_length, crc_length and 1394 magic number to check, if it is really a bus info block */ | 1464 | /* info_length, crc_length and 1394 magic number to check, if it is really a bus info block */ |
1465 | if (((be32_to_cpu(lynx->bus_info_block[0]) & 0xffff0000) == 0x04040000) && | 1465 | if (((be32_to_cpu(lynx->bus_info_block[0]) & 0xffff0000) == 0x04040000) && |
1466 | (lynx->bus_info_block[1] == __constant_cpu_to_be32(0x31333934))) | 1466 | (lynx->bus_info_block[1] == IEEE1394_BUSID_MAGIC)) |
1467 | { | 1467 | { |
1468 | PRINT(KERN_DEBUG, lynx->id, "read a valid bus info block from"); | 1468 | PRINT(KERN_DEBUG, lynx->id, "read a valid bus info block from"); |
1469 | } else { | 1469 | } else { |
diff --git a/drivers/ieee1394/pcilynx.h b/drivers/ieee1394/pcilynx.h index ec27321f6724..693a169acea3 100644 --- a/drivers/ieee1394/pcilynx.h +++ b/drivers/ieee1394/pcilynx.h | |||
@@ -52,7 +52,7 @@ struct ti_lynx { | |||
52 | void __iomem *local_rom; | 52 | void __iomem *local_rom; |
53 | void __iomem *local_ram; | 53 | void __iomem *local_ram; |
54 | void __iomem *aux_port; | 54 | void __iomem *aux_port; |
55 | quadlet_t bus_info_block[5]; | 55 | __be32 bus_info_block[5]; |
56 | 56 | ||
57 | /* | 57 | /* |
58 | * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for | 58 | * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for |
diff --git a/drivers/ieee1394/raw1394.c b/drivers/ieee1394/raw1394.c index bf7e761c12b1..bad66c65b0d6 100644 --- a/drivers/ieee1394/raw1394.c +++ b/drivers/ieee1394/raw1394.c | |||
@@ -90,7 +90,7 @@ static int arm_lock(struct hpsb_host *host, int nodeid, quadlet_t * store, | |||
90 | static int arm_lock64(struct hpsb_host *host, int nodeid, octlet_t * store, | 90 | static int arm_lock64(struct hpsb_host *host, int nodeid, octlet_t * store, |
91 | u64 addr, octlet_t data, octlet_t arg, int ext_tcode, | 91 | u64 addr, octlet_t data, octlet_t arg, int ext_tcode, |
92 | u16 flags); | 92 | u16 flags); |
93 | static struct hpsb_address_ops arm_ops = { | 93 | const static struct hpsb_address_ops arm_ops = { |
94 | .read = arm_read, | 94 | .read = arm_read, |
95 | .write = arm_write, | 95 | .write = arm_write, |
96 | .lock = arm_lock, | 96 | .lock = arm_lock, |
diff --git a/drivers/ieee1394/sbp2.c b/drivers/ieee1394/sbp2.c index a373c18cf7b8..ab1034ccb7fb 100644 --- a/drivers/ieee1394/sbp2.c +++ b/drivers/ieee1394/sbp2.c | |||
@@ -265,7 +265,7 @@ static struct hpsb_highlevel sbp2_highlevel = { | |||
265 | .host_reset = sbp2_host_reset, | 265 | .host_reset = sbp2_host_reset, |
266 | }; | 266 | }; |
267 | 267 | ||
268 | static struct hpsb_address_ops sbp2_ops = { | 268 | const static struct hpsb_address_ops sbp2_ops = { |
269 | .write = sbp2_handle_status_write | 269 | .write = sbp2_handle_status_write |
270 | }; | 270 | }; |
271 | 271 | ||
@@ -275,7 +275,7 @@ static int sbp2_handle_physdma_write(struct hpsb_host *, int, int, quadlet_t *, | |||
275 | static int sbp2_handle_physdma_read(struct hpsb_host *, int, quadlet_t *, u64, | 275 | static int sbp2_handle_physdma_read(struct hpsb_host *, int, quadlet_t *, u64, |
276 | size_t, u16); | 276 | size_t, u16); |
277 | 277 | ||
278 | static struct hpsb_address_ops sbp2_physdma_ops = { | 278 | const static struct hpsb_address_ops sbp2_physdma_ops = { |
279 | .read = sbp2_handle_physdma_read, | 279 | .read = sbp2_handle_physdma_read, |
280 | .write = sbp2_handle_physdma_write, | 280 | .write = sbp2_handle_physdma_write, |
281 | }; | 281 | }; |