aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/ieee1394/ohci1394.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/ieee1394/ohci1394.c')
-rw-r--r--drivers/ieee1394/ohci1394.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/ieee1394/ohci1394.c b/drivers/ieee1394/ohci1394.c
index d077fe6d0ce5..498539ecd673 100644
--- a/drivers/ieee1394/ohci1394.c
+++ b/drivers/ieee1394/ohci1394.c
@@ -3199,15 +3199,16 @@ static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
3199 /* Now enable LPS, which we need in order to start accessing 3199 /* Now enable LPS, which we need in order to start accessing
3200 * most of the registers. In fact, on some cards (ALI M5251), 3200 * most of the registers. In fact, on some cards (ALI M5251),
3201 * accessing registers in the SClk domain without LPS enabled 3201 * accessing registers in the SClk domain without LPS enabled
3202 * will lock up the machine. Wait 50msec to make sure we have 3202 * will lock up the machine. */
3203 * full link enabled. */
3204 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); 3203 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3205 3204
3206 /* Disable and clear interrupts */ 3205 /* Disable and clear interrupts */
3207 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); 3206 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3208 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); 3207 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3209 3208
3210 mdelay(50); 3209 /* Flush MMIO writes and wait to make sure we have full link enabled. */
3210 reg_read(ohci, OHCI1394_Version);
3211 msleep(50);
3211 3212
3212 /* Determine the number of available IR and IT contexts. */ 3213 /* Determine the number of available IR and IT contexts. */
3213 ohci->nb_iso_rcv_ctx = 3214 ohci->nb_iso_rcv_ctx =
@@ -3422,7 +3423,8 @@ static int ohci1394_pci_resume(struct pci_dev *dev)
3422 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); 3423 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
3423 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); 3424 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
3424 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); 3425 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
3425 mdelay(50); 3426 reg_read(ohci, OHCI1394_Version);
3427 msleep(50);
3426 3428
3427 err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED, 3429 err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
3428 OHCI1394_DRIVER_NAME, ohci); 3430 OHCI1394_DRIVER_NAME, ohci);