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1/* -*- c-basic-offset: 8 -*-
2 *
3 * amdtp.c - Audio and Music Data Transmission Protocol Driver
4 * Copyright (C) 2001 Kristian Høgsberg
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/* OVERVIEW
22 * --------
23 *
24 * The AMDTP driver is designed to expose the IEEE1394 bus as a
25 * regular OSS soundcard, i.e. you can link /dev/dsp to /dev/amdtp and
26 * then your favourite MP3 player, game or whatever sound program will
27 * output to an IEEE1394 isochronous channel. The signal destination
28 * could be a set of IEEE1394 loudspeakers (if and when such things
29 * become available) or an amplifier with IEEE1394 input (like the
30 * Sony STR-LSA1). The driver only handles the actual streaming, some
31 * connection management is also required for this to actually work.
32 * That is outside the scope of this driver, and furthermore it is not
33 * really standardized yet.
34 *
35 * The Audio and Music Data Tranmission Protocol is available at
36 *
37 * http://www.1394ta.org/Download/Technology/Specifications/2001/AM20Final-jf2.pdf
38 *
39 *
40 * TODO
41 * ----
42 *
43 * - We should be able to change input sample format between LE/BE, as
44 * we already shift the bytes around when we construct the iso
45 * packets.
46 *
47 * - Fix DMA stop after bus reset!
48 *
49 * - Clean up iso context handling in ohci1394.
50 *
51 *
52 * MAYBE TODO
53 * ----------
54 *
55 * - Receive data for local playback or recording. Playback requires
56 * soft syncing with the sound card.
57 *
58 * - Signal processing, i.e. receive packets, do some processing, and
59 * transmit them again using the same packet structure and timestamps
60 * offset by processing time.
61 *
62 * - Maybe make an ALSA interface, that is, create a file_ops
63 * implementation that recognizes ALSA ioctls and uses defaults for
64 * things that can't be controlled through ALSA (iso channel).
65 *
66 * Changes:
67 *
68 * - Audit copy_from_user in amdtp_write.
69 * Daniele Bellucci <bellucda@tiscali.it>
70 *
71 */
72
73#include <linux/module.h>
74#include <linux/list.h>
75#include <linux/sched.h>
76#include <linux/types.h>
77#include <linux/fs.h>
78#include <linux/ioctl.h>
79#include <linux/wait.h>
80#include <linux/pci.h>
81#include <linux/interrupt.h>
82#include <linux/poll.h>
83#include <linux/ioctl32.h>
84#include <linux/compat.h>
85#include <linux/cdev.h>
86#include <asm/uaccess.h>
87#include <asm/atomic.h>
88
89#include "hosts.h"
90#include "highlevel.h"
91#include "ieee1394.h"
92#include "ieee1394_core.h"
93#include "ohci1394.h"
94
95#include "amdtp.h"
96#include "cmp.h"
97
98#define FMT_AMDTP 0x10
99#define FDF_AM824 0x00
100#define FDF_SFC_32KHZ 0x00
101#define FDF_SFC_44K1HZ 0x01
102#define FDF_SFC_48KHZ 0x02
103#define FDF_SFC_88K2HZ 0x03
104#define FDF_SFC_96KHZ 0x04
105#define FDF_SFC_176K4HZ 0x05
106#define FDF_SFC_192KHZ 0x06
107
108struct descriptor_block {
109 struct output_more_immediate {
110 u32 control;
111 u32 pad0;
112 u32 skip;
113 u32 pad1;
114 u32 header[4];
115 } header_desc;
116
117 struct output_last {
118 u32 control;
119 u32 data_address;
120 u32 branch;
121 u32 status;
122 } payload_desc;
123};
124
125struct packet {
126 struct descriptor_block *db;
127 dma_addr_t db_bus;
128 struct iso_packet *payload;
129 dma_addr_t payload_bus;
130};
131
132#include <asm/byteorder.h>
133
134#if defined __BIG_ENDIAN_BITFIELD
135
136struct iso_packet {
137 /* First quadlet */
138 unsigned int dbs : 8;
139 unsigned int eoh0 : 2;
140 unsigned int sid : 6;
141
142 unsigned int dbc : 8;
143 unsigned int fn : 2;
144 unsigned int qpc : 3;
145 unsigned int sph : 1;
146 unsigned int reserved : 2;
147
148 /* Second quadlet */
149 unsigned int fdf : 8;
150 unsigned int eoh1 : 2;
151 unsigned int fmt : 6;
152
153 unsigned int syt : 16;
154
155 quadlet_t data[0];
156};
157
158#elif defined __LITTLE_ENDIAN_BITFIELD
159
160struct iso_packet {
161 /* First quadlet */
162 unsigned int sid : 6;
163 unsigned int eoh0 : 2;
164 unsigned int dbs : 8;
165
166 unsigned int reserved : 2;
167 unsigned int sph : 1;
168 unsigned int qpc : 3;
169 unsigned int fn : 2;
170 unsigned int dbc : 8;
171
172 /* Second quadlet */
173 unsigned int fmt : 6;
174 unsigned int eoh1 : 2;
175 unsigned int fdf : 8;
176
177 unsigned int syt : 16;
178
179 quadlet_t data[0];
180};
181
182#else
183
184#error Unknown bitfield type
185
186#endif
187
188struct fraction {
189 int integer;
190 int numerator;
191 int denominator;
192};
193
194#define PACKET_LIST_SIZE 256
195#define MAX_PACKET_LISTS 4
196
197struct packet_list {
198 struct list_head link;
199 int last_cycle_count;
200 struct packet packets[PACKET_LIST_SIZE];
201};
202
203#define BUFFER_SIZE 128
204
205/* This implements a circular buffer for incoming samples. */
206
207struct buffer {
208 size_t head, tail, length, size;
209 unsigned char data[0];
210};
211
212struct stream {
213 int iso_channel;
214 int format;
215 int rate;
216 int dimension;
217 int fdf;
218 int mode;
219 int sample_format;
220 struct cmp_pcr *opcr;
221
222 /* Input samples are copied here. */
223 struct buffer *input;
224
225 /* ISO Packer state */
226 unsigned char dbc;
227 struct packet_list *current_packet_list;
228 int current_packet;
229 struct fraction ready_samples, samples_per_cycle;
230
231 /* We use these to generate control bits when we are packing
232 * iec958 data.
233 */
234 int iec958_frame_count;
235 int iec958_rate_code;
236
237 /* The cycle_count and cycle_offset fields are used for the
238 * synchronization timestamps (syt) in the cip header. They
239 * are incremented by at least a cycle every time we put a
240 * time stamp in a packet. As we don't time stamp all
241 * packages, cycle_count isn't updated in every cycle, and
242 * sometimes it's incremented by 2. Thus, we have
243 * cycle_count2, which is simply incremented by one with each
244 * packet, so we can compare it to the transmission time
245 * written back in the dma programs.
246 */
247 atomic_t cycle_count, cycle_count2;
248 struct fraction cycle_offset, ticks_per_syt_offset;
249 int syt_interval;
250 int stale_count;
251
252 /* Theses fields control the sample output to the DMA engine.
253 * The dma_packet_lists list holds packet lists currently
254 * queued for dma; the head of the list is currently being
255 * processed. The last program in a packet list generates an
256 * interrupt, which removes the head from dma_packet_lists and
257 * puts it back on the free list.
258 */
259 struct list_head dma_packet_lists;
260 struct list_head free_packet_lists;
261 wait_queue_head_t packet_list_wait;
262 spinlock_t packet_list_lock;
263 struct ohci1394_iso_tasklet iso_tasklet;
264 struct pci_pool *descriptor_pool, *packet_pool;
265
266 /* Streams at a host controller are chained through this field. */
267 struct list_head link;
268 struct amdtp_host *host;
269};
270
271struct amdtp_host {
272 struct hpsb_host *host;
273 struct ti_ohci *ohci;
274 struct list_head stream_list;
275 spinlock_t stream_list_lock;
276};
277
278static struct hpsb_highlevel amdtp_highlevel;
279
280
281/* FIXME: This doesn't belong here... */
282
283#define OHCI1394_CONTEXT_CYCLE_MATCH 0x80000000
284#define OHCI1394_CONTEXT_RUN 0x00008000
285#define OHCI1394_CONTEXT_WAKE 0x00001000
286#define OHCI1394_CONTEXT_DEAD 0x00000800
287#define OHCI1394_CONTEXT_ACTIVE 0x00000400
288
289static void ohci1394_start_it_ctx(struct ti_ohci *ohci, int ctx,
290 dma_addr_t first_cmd, int z, int cycle_match)
291{
292 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << ctx);
293 reg_write(ohci, OHCI1394_IsoXmitCommandPtr + ctx * 16, first_cmd | z);
294 reg_write(ohci, OHCI1394_IsoXmitContextControlClear + ctx * 16, ~0);
295 wmb();
296 reg_write(ohci, OHCI1394_IsoXmitContextControlSet + ctx * 16,
297 OHCI1394_CONTEXT_CYCLE_MATCH | (cycle_match << 16) |
298 OHCI1394_CONTEXT_RUN);
299}
300
301static void ohci1394_wake_it_ctx(struct ti_ohci *ohci, int ctx)
302{
303 reg_write(ohci, OHCI1394_IsoXmitContextControlSet + ctx * 16,
304 OHCI1394_CONTEXT_WAKE);
305}
306
307static void ohci1394_stop_it_ctx(struct ti_ohci *ohci, int ctx, int synchronous)
308{
309 u32 control;
310 int wait;
311
312 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << ctx);
313 reg_write(ohci, OHCI1394_IsoXmitContextControlClear + ctx * 16,
314 OHCI1394_CONTEXT_RUN);
315 wmb();
316
317 if (synchronous) {
318 for (wait = 0; wait < 5; wait++) {
319 control = reg_read(ohci, OHCI1394_IsoXmitContextControlSet + ctx * 16);
320 if ((control & OHCI1394_CONTEXT_ACTIVE) == 0)
321 break;
322
323 set_current_state(TASK_INTERRUPTIBLE);
324 schedule_timeout(1);
325 }
326 }
327}
328
329/* Note: we can test if free_packet_lists is empty without aquiring
330 * the packet_list_lock. The interrupt handler only adds to the free
331 * list, there is no race condition between testing the list non-empty
332 * and acquiring the lock.
333 */
334
335static struct packet_list *stream_get_free_packet_list(struct stream *s)
336{
337 struct packet_list *pl;
338 unsigned long flags;
339
340 if (list_empty(&s->free_packet_lists))
341 return NULL;
342
343 spin_lock_irqsave(&s->packet_list_lock, flags);
344 pl = list_entry(s->free_packet_lists.next, struct packet_list, link);
345 list_del(&pl->link);
346 spin_unlock_irqrestore(&s->packet_list_lock, flags);
347
348 return pl;
349}
350
351static void stream_start_dma(struct stream *s, struct packet_list *pl)
352{
353 u32 syt_cycle, cycle_count, start_cycle;
354
355 cycle_count = reg_read(s->host->ohci,
356 OHCI1394_IsochronousCycleTimer) >> 12;
357 syt_cycle = (pl->last_cycle_count - PACKET_LIST_SIZE + 1) & 0x0f;
358
359 /* We program the DMA controller to start transmission at
360 * least 17 cycles from now - this happens when the lower four
361 * bits of cycle_count is 0x0f and syt_cycle is 0, in this
362 * case the start cycle is cycle_count - 15 + 32. */
363 start_cycle = (cycle_count & ~0x0f) + 32 + syt_cycle;
364 if ((start_cycle & 0x1fff) >= 8000)
365 start_cycle = start_cycle - 8000 + 0x2000;
366
367 ohci1394_start_it_ctx(s->host->ohci, s->iso_tasklet.context,
368 pl->packets[0].db_bus, 3,
369 start_cycle & 0x7fff);
370}
371
372static void stream_put_dma_packet_list(struct stream *s,
373 struct packet_list *pl)
374{
375 unsigned long flags;
376 struct packet_list *prev;
377
378 /* Remember the cycle_count used for timestamping the last packet. */
379 pl->last_cycle_count = atomic_read(&s->cycle_count2) - 1;
380 pl->packets[PACKET_LIST_SIZE - 1].db->payload_desc.branch = 0;
381
382 spin_lock_irqsave(&s->packet_list_lock, flags);
383 list_add_tail(&pl->link, &s->dma_packet_lists);
384 spin_unlock_irqrestore(&s->packet_list_lock, flags);
385
386 prev = list_entry(pl->link.prev, struct packet_list, link);
387 if (pl->link.prev != &s->dma_packet_lists) {
388 struct packet *last = &prev->packets[PACKET_LIST_SIZE - 1];
389 last->db->payload_desc.branch = pl->packets[0].db_bus | 3;
390 last->db->header_desc.skip = pl->packets[0].db_bus | 3;
391 ohci1394_wake_it_ctx(s->host->ohci, s->iso_tasklet.context);
392 }
393 else
394 stream_start_dma(s, pl);
395}
396
397static void stream_shift_packet_lists(unsigned long l)
398{
399 struct stream *s = (struct stream *) l;
400 struct packet_list *pl;
401 struct packet *last;
402 int diff;
403
404 if (list_empty(&s->dma_packet_lists)) {
405 HPSB_ERR("empty dma_packet_lists in %s", __FUNCTION__);
406 return;
407 }
408
409 /* Now that we know the list is non-empty, we can get the head
410 * of the list without locking, because the process context
411 * only adds to the tail.
412 */
413 pl = list_entry(s->dma_packet_lists.next, struct packet_list, link);
414 last = &pl->packets[PACKET_LIST_SIZE - 1];
415
416 /* This is weird... if we stop dma processing in the middle of
417 * a packet list, the dma context immediately generates an
418 * interrupt if we enable it again later. This only happens
419 * when amdtp_release is interrupted while waiting for dma to
420 * complete, though. Anyway, we detect this by seeing that
421 * the status of the dma descriptor that we expected an
422 * interrupt from is still 0.
423 */
424 if (last->db->payload_desc.status == 0) {
425 HPSB_INFO("weird interrupt...");
426 return;
427 }
428
429 /* If the last descriptor block does not specify a branch
430 * address, we have a sample underflow.
431 */
432 if (last->db->payload_desc.branch == 0)
433 HPSB_INFO("FIXME: sample underflow...");
434
435 /* Here we check when (which cycle) the last packet was sent
436 * and compare it to what the iso packer was using at the
437 * time. If there is a mismatch, we adjust the cycle count in
438 * the iso packer. However, there are still up to
439 * MAX_PACKET_LISTS packet lists queued with bad time stamps,
440 * so we disable time stamp monitoring for the next
441 * MAX_PACKET_LISTS packet lists.
442 */
443 diff = (last->db->payload_desc.status - pl->last_cycle_count) & 0xf;
444 if (diff > 0 && s->stale_count == 0) {
445 atomic_add(diff, &s->cycle_count);
446 atomic_add(diff, &s->cycle_count2);
447 s->stale_count = MAX_PACKET_LISTS;
448 }
449
450 if (s->stale_count > 0)
451 s->stale_count--;
452
453 /* Finally, we move the packet list that was just processed
454 * back to the free list, and notify any waiters.
455 */
456 spin_lock(&s->packet_list_lock);
457 list_del(&pl->link);
458 list_add_tail(&pl->link, &s->free_packet_lists);
459 spin_unlock(&s->packet_list_lock);
460
461 wake_up_interruptible(&s->packet_list_wait);
462}
463
464static struct packet *stream_current_packet(struct stream *s)
465{
466 if (s->current_packet_list == NULL &&
467 (s->current_packet_list = stream_get_free_packet_list(s)) == NULL)
468 return NULL;
469
470 return &s->current_packet_list->packets[s->current_packet];
471}
472
473static void stream_queue_packet(struct stream *s)
474{
475 s->current_packet++;
476 if (s->current_packet == PACKET_LIST_SIZE) {
477 stream_put_dma_packet_list(s, s->current_packet_list);
478 s->current_packet_list = NULL;
479 s->current_packet = 0;
480 }
481}
482
483/* Integer fractional math. When we transmit a 44k1Hz signal we must
484 * send 5 41/80 samples per isochronous cycle, as these occur 8000
485 * times a second. Of course, we must send an integral number of
486 * samples in a packet, so we use the integer math to alternate
487 * between sending 5 and 6 samples per packet.
488 */
489
490static void fraction_init(struct fraction *f, int numerator, int denominator)
491{
492 f->integer = numerator / denominator;
493 f->numerator = numerator % denominator;
494 f->denominator = denominator;
495}
496
497static __inline__ void fraction_add(struct fraction *dst,
498 struct fraction *src1,
499 struct fraction *src2)
500{
501 /* assert: src1->denominator == src2->denominator */
502
503 int sum, denom;
504
505 /* We use these two local variables to allow gcc to optimize
506 * the division and the modulo into only one division. */
507
508 sum = src1->numerator + src2->numerator;
509 denom = src1->denominator;
510 dst->integer = src1->integer + src2->integer + sum / denom;
511 dst->numerator = sum % denom;
512 dst->denominator = denom;
513}
514
515static __inline__ void fraction_sub_int(struct fraction *dst,
516 struct fraction *src, int integer)
517{
518 dst->integer = src->integer - integer;
519 dst->numerator = src->numerator;
520 dst->denominator = src->denominator;
521}
522
523static __inline__ int fraction_floor(struct fraction *frac)
524{
525 return frac->integer;
526}
527
528static __inline__ int fraction_ceil(struct fraction *frac)
529{
530 return frac->integer + (frac->numerator > 0 ? 1 : 0);
531}
532
533static void packet_initialize(struct packet *p, struct packet *next)
534{
535 /* Here we initialize the dma descriptor block for
536 * transferring one iso packet. We use two descriptors per
537 * packet: an OUTPUT_MORE_IMMMEDIATE descriptor for the
538 * IEEE1394 iso packet header and an OUTPUT_LAST descriptor
539 * for the payload.
540 */
541
542 p->db->header_desc.control =
543 DMA_CTL_OUTPUT_MORE | DMA_CTL_IMMEDIATE | 8;
544
545 if (next) {
546 p->db->payload_desc.control =
547 DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH;
548 p->db->payload_desc.branch = next->db_bus | 3;
549 p->db->header_desc.skip = next->db_bus | 3;
550 }
551 else {
552 p->db->payload_desc.control =
553 DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH |
554 DMA_CTL_UPDATE | DMA_CTL_IRQ;
555 p->db->payload_desc.branch = 0;
556 p->db->header_desc.skip = 0;
557 }
558 p->db->payload_desc.data_address = p->payload_bus;
559 p->db->payload_desc.status = 0;
560}
561
562static struct packet_list *packet_list_alloc(struct stream *s)
563{
564 int i;
565 struct packet_list *pl;
566 struct packet *next;
567
568 pl = kmalloc(sizeof *pl, SLAB_KERNEL);
569 if (pl == NULL)
570 return NULL;
571
572 for (i = 0; i < PACKET_LIST_SIZE; i++) {
573 struct packet *p = &pl->packets[i];
574 p->db = pci_pool_alloc(s->descriptor_pool, SLAB_KERNEL,
575 &p->db_bus);
576 p->payload = pci_pool_alloc(s->packet_pool, SLAB_KERNEL,
577 &p->payload_bus);
578 }
579
580 for (i = 0; i < PACKET_LIST_SIZE; i++) {
581 if (i < PACKET_LIST_SIZE - 1)
582 next = &pl->packets[i + 1];
583 else
584 next = NULL;
585 packet_initialize(&pl->packets[i], next);
586 }
587
588 return pl;
589}
590
591static void packet_list_free(struct packet_list *pl, struct stream *s)
592{
593 int i;
594
595 for (i = 0; i < PACKET_LIST_SIZE; i++) {
596 struct packet *p = &pl->packets[i];
597 pci_pool_free(s->descriptor_pool, p->db, p->db_bus);
598 pci_pool_free(s->packet_pool, p->payload, p->payload_bus);
599 }
600 kfree(pl);
601}
602
603static struct buffer *buffer_alloc(int size)
604{
605 struct buffer *b;
606
607 b = kmalloc(sizeof *b + size, SLAB_KERNEL);
608 if (b == NULL)
609 return NULL;
610 b->head = 0;
611 b->tail = 0;
612 b->length = 0;
613 b->size = size;
614
615 return b;
616}
617
618static unsigned char *buffer_get_bytes(struct buffer *buffer, int size)
619{
620 unsigned char *p;
621
622 if (buffer->head + size > buffer->size)
623 BUG();
624
625 p = &buffer->data[buffer->head];
626 buffer->head += size;
627 if (buffer->head == buffer->size)
628 buffer->head = 0;
629 buffer->length -= size;
630
631 return p;
632}
633
634static unsigned char *buffer_put_bytes(struct buffer *buffer,
635 size_t max, size_t *actual)
636{
637 size_t length;
638 unsigned char *p;
639
640 p = &buffer->data[buffer->tail];
641 length = min(buffer->size - buffer->length, max);
642 if (buffer->tail + length < buffer->size) {
643 *actual = length;
644 buffer->tail += length;
645 }
646 else {
647 *actual = buffer->size - buffer->tail;
648 buffer->tail = 0;
649 }
650
651 buffer->length += *actual;
652 return p;
653}
654
655static u32 get_iec958_header_bits(struct stream *s, int sub_frame, u32 sample)
656{
657 int csi, parity, shift;
658 int block_start;
659 u32 bits;
660
661 switch (s->iec958_frame_count) {
662 case 1:
663 csi = s->format == AMDTP_FORMAT_IEC958_AC3;
664 break;
665 case 2:
666 case 9:
667 csi = 1;
668 break;
669 case 24 ... 27:
670 csi = (s->iec958_rate_code >> (27 - s->iec958_frame_count)) & 0x01;
671 break;
672 default:
673 csi = 0;
674 break;
675 }
676
677 block_start = (s->iec958_frame_count == 0 && sub_frame == 0);
678
679 /* The parity bit is the xor of the sample bits and the
680 * channel status info bit. */
681 for (shift = 16, parity = sample ^ csi; shift > 0; shift >>= 1)
682 parity ^= (parity >> shift);
683
684 bits = (block_start << 5) | /* Block start bit */
685 ((sub_frame == 0) << 4) | /* Subframe bit */
686 ((parity & 1) << 3) | /* Parity bit */
687 (csi << 2); /* Channel status info bit */
688
689 return bits;
690}
691
692static u32 get_header_bits(struct stream *s, int sub_frame, u32 sample)
693{
694 switch (s->format) {
695 case AMDTP_FORMAT_IEC958_PCM:
696 case AMDTP_FORMAT_IEC958_AC3:
697 return get_iec958_header_bits(s, sub_frame, sample);
698
699 case AMDTP_FORMAT_RAW:
700 return 0x40;
701
702 default:
703 return 0;
704 }
705}
706
707static void fill_payload_le16(struct stream *s, quadlet_t *data, int nevents)
708{
709 quadlet_t *event, sample, bits;
710 unsigned char *p;
711 int i, j;
712
713 for (i = 0, event = data; i < nevents; i++) {
714
715 for (j = 0; j < s->dimension; j++) {
716 p = buffer_get_bytes(s->input, 2);
717 sample = (p[1] << 16) | (p[0] << 8);
718 bits = get_header_bits(s, j, sample);
719 event[j] = cpu_to_be32((bits << 24) | sample);
720 }
721
722 event += s->dimension;
723 if (++s->iec958_frame_count == 192)
724 s->iec958_frame_count = 0;
725 }
726}
727
728static void fill_packet(struct stream *s, struct packet *packet, int nevents)
729{
730 int syt_index, syt, size;
731 u32 control;
732
733 size = (nevents * s->dimension + 2) * sizeof(quadlet_t);
734
735 /* Update DMA descriptors */
736 packet->db->payload_desc.status = 0;
737 control = packet->db->payload_desc.control & 0xffff0000;
738 packet->db->payload_desc.control = control | size;
739
740 /* Fill IEEE1394 headers */
741 packet->db->header_desc.header[0] =
742 (IEEE1394_SPEED_100 << 16) | (0x01 << 14) |
743 (s->iso_channel << 8) | (TCODE_ISO_DATA << 4);
744 packet->db->header_desc.header[1] = size << 16;
745
746 /* Calculate synchronization timestamp (syt). First we
747 * determine syt_index, that is, the index in the packet of
748 * the sample for which the timestamp is valid. */
749 syt_index = (s->syt_interval - s->dbc) & (s->syt_interval - 1);
750 if (syt_index < nevents) {
751 syt = ((atomic_read(&s->cycle_count) << 12) |
752 s->cycle_offset.integer) & 0xffff;
753 fraction_add(&s->cycle_offset,
754 &s->cycle_offset, &s->ticks_per_syt_offset);
755
756 /* This next addition should be modulo 8000 (0x1f40),
757 * but we only use the lower 4 bits of cycle_count, so
758 * we don't need the modulo. */
759 atomic_add(s->cycle_offset.integer / 3072, &s->cycle_count);
760 s->cycle_offset.integer %= 3072;
761 }
762 else
763 syt = 0xffff;
764
765 atomic_inc(&s->cycle_count2);
766
767 /* Fill cip header */
768 packet->payload->eoh0 = 0;
769 packet->payload->sid = s->host->host->node_id & 0x3f;
770 packet->payload->dbs = s->dimension;
771 packet->payload->fn = 0;
772 packet->payload->qpc = 0;
773 packet->payload->sph = 0;
774 packet->payload->reserved = 0;
775 packet->payload->dbc = s->dbc;
776 packet->payload->eoh1 = 2;
777 packet->payload->fmt = FMT_AMDTP;
778 packet->payload->fdf = s->fdf;
779 packet->payload->syt = cpu_to_be16(syt);
780
781 switch (s->sample_format) {
782 case AMDTP_INPUT_LE16:
783 fill_payload_le16(s, packet->payload->data, nevents);
784 break;
785 }
786
787 s->dbc += nevents;
788}
789
790static void stream_flush(struct stream *s)
791{
792 struct packet *p;
793 int nevents;
794 struct fraction next;
795
796 /* The AMDTP specifies two transmission modes: blocking and
797 * non-blocking. In blocking mode you always transfer
798 * syt_interval or zero samples, whereas in non-blocking mode
799 * you send as many samples as you have available at transfer
800 * time.
801 *
802 * The fraction samples_per_cycle specifies the number of
803 * samples that become available per cycle. We add this to
804 * the fraction ready_samples, which specifies the number of
805 * leftover samples from the previous transmission. The sum,
806 * stored in the fraction next, specifies the number of
807 * samples available for transmission, and from this we
808 * determine the number of samples to actually transmit.
809 */
810
811 while (1) {
812 fraction_add(&next, &s->ready_samples, &s->samples_per_cycle);
813 if (s->mode == AMDTP_MODE_BLOCKING) {
814 if (fraction_floor(&next) >= s->syt_interval)
815 nevents = s->syt_interval;
816 else
817 nevents = 0;
818 }
819 else
820 nevents = fraction_floor(&next);
821
822 p = stream_current_packet(s);
823 if (s->input->length < nevents * s->dimension * 2 || p == NULL)
824 break;
825
826 fill_packet(s, p, nevents);
827 stream_queue_packet(s);
828
829 /* Now that we have successfully queued the packet for
830 * transmission, we update the fraction ready_samples. */
831 fraction_sub_int(&s->ready_samples, &next, nevents);
832 }
833}
834
835static int stream_alloc_packet_lists(struct stream *s)
836{
837 int max_nevents, max_packet_size, i;
838
839 if (s->mode == AMDTP_MODE_BLOCKING)
840 max_nevents = s->syt_interval;
841 else
842 max_nevents = fraction_ceil(&s->samples_per_cycle);
843
844 max_packet_size = max_nevents * s->dimension * 4 + 8;
845 s->packet_pool = pci_pool_create("packet pool", s->host->ohci->dev,
846 max_packet_size, 0, 0);
847
848 if (s->packet_pool == NULL)
849 return -1;
850
851 INIT_LIST_HEAD(&s->free_packet_lists);
852 INIT_LIST_HEAD(&s->dma_packet_lists);
853 for (i = 0; i < MAX_PACKET_LISTS; i++) {
854 struct packet_list *pl = packet_list_alloc(s);
855 if (pl == NULL)
856 break;
857 list_add_tail(&pl->link, &s->free_packet_lists);
858 }
859
860 return i < MAX_PACKET_LISTS ? -1 : 0;
861}
862
863static void stream_free_packet_lists(struct stream *s)
864{
865 struct packet_list *packet_l, *packet_l_next;
866
867 if (s->current_packet_list != NULL)
868 packet_list_free(s->current_packet_list, s);
869 list_for_each_entry_safe(packet_l, packet_l_next, &s->dma_packet_lists, link)
870 packet_list_free(packet_l, s);
871 list_for_each_entry_safe(packet_l, packet_l_next, &s->free_packet_lists, link)
872 packet_list_free(packet_l, s);
873 if (s->packet_pool != NULL)
874 pci_pool_destroy(s->packet_pool);
875
876 s->current_packet_list = NULL;
877 INIT_LIST_HEAD(&s->free_packet_lists);
878 INIT_LIST_HEAD(&s->dma_packet_lists);
879 s->packet_pool = NULL;
880}
881
882static void plug_update(struct cmp_pcr *plug, void *data)
883{
884 struct stream *s = data;
885
886 HPSB_INFO("plug update: p2p_count=%d, channel=%d",
887 plug->p2p_count, plug->channel);
888 s->iso_channel = plug->channel;
889 if (plug->p2p_count > 0) {
890 struct packet_list *pl;
891
892 pl = list_entry(s->dma_packet_lists.next, struct packet_list, link);
893 stream_start_dma(s, pl);
894 }
895 else {
896 ohci1394_stop_it_ctx(s->host->ohci, s->iso_tasklet.context, 0);
897 }
898}
899
900static int stream_configure(struct stream *s, int cmd, struct amdtp_ioctl *cfg)
901{
902 const int transfer_delay = 9000;
903
904 if (cfg->format <= AMDTP_FORMAT_IEC958_AC3)
905 s->format = cfg->format;
906 else
907 return -EINVAL;
908
909 switch (cfg->rate) {
910 case 32000:
911 s->syt_interval = 8;
912 s->fdf = FDF_SFC_32KHZ;
913 s->iec958_rate_code = 0x0c;
914 break;
915 case 44100:
916 s->syt_interval = 8;
917 s->fdf = FDF_SFC_44K1HZ;
918 s->iec958_rate_code = 0x00;
919 break;
920 case 48000:
921 s->syt_interval = 8;
922 s->fdf = FDF_SFC_48KHZ;
923 s->iec958_rate_code = 0x04;
924 break;
925 case 88200:
926 s->syt_interval = 16;
927 s->fdf = FDF_SFC_88K2HZ;
928 s->iec958_rate_code = 0x00;
929 break;
930 case 96000:
931 s->syt_interval = 16;
932 s->fdf = FDF_SFC_96KHZ;
933 s->iec958_rate_code = 0x00;
934 break;
935 case 176400:
936 s->syt_interval = 32;
937 s->fdf = FDF_SFC_176K4HZ;
938 s->iec958_rate_code = 0x00;
939 break;
940 case 192000:
941 s->syt_interval = 32;
942 s->fdf = FDF_SFC_192KHZ;
943 s->iec958_rate_code = 0x00;
944 break;
945
946 default:
947 return -EINVAL;
948 }
949
950 s->rate = cfg->rate;
951 fraction_init(&s->samples_per_cycle, s->rate, 8000);
952 fraction_init(&s->ready_samples, 0, 8000);
953
954 /* The ticks_per_syt_offset is initialized to the number of
955 * ticks between syt_interval events. The number of ticks per
956 * second is 24.576e6, so the number of ticks between
957 * syt_interval events is 24.576e6 * syt_interval / rate.
958 */
959 fraction_init(&s->ticks_per_syt_offset,
960 24576000 * s->syt_interval, s->rate);
961 fraction_init(&s->cycle_offset, (transfer_delay % 3072) * s->rate, s->rate);
962 atomic_set(&s->cycle_count, transfer_delay / 3072);
963 atomic_set(&s->cycle_count2, 0);
964
965 s->mode = cfg->mode;
966 s->sample_format = AMDTP_INPUT_LE16;
967
968 /* When using the AM824 raw subformat we can stream signals of
969 * any dimension. The IEC958 subformat, however, only
970 * supports 2 channels.
971 */
972 if (s->format == AMDTP_FORMAT_RAW || cfg->dimension == 2)
973 s->dimension = cfg->dimension;
974 else
975 return -EINVAL;
976
977 if (s->opcr != NULL) {
978 cmp_unregister_opcr(s->host->host, s->opcr);
979 s->opcr = NULL;
980 }
981
982 switch(cmd) {
983 case AMDTP_IOC_PLUG:
984 s->opcr = cmp_register_opcr(s->host->host, cfg->u.plug,
985 /*payload*/ 12, plug_update, s);
986 if (s->opcr == NULL)
987 return -EINVAL;
988 s->iso_channel = s->opcr->channel;
989 break;
990
991 case AMDTP_IOC_CHANNEL:
992 if (cfg->u.channel >= 0 && cfg->u.channel < 64)
993 s->iso_channel = cfg->u.channel;
994 else
995 return -EINVAL;
996 break;
997 }
998
999 /* The ioctl settings were all valid, so we realloc the packet
1000 * lists to make sure the packet size is big enough.
1001 */
1002 if (s->packet_pool != NULL)
1003 stream_free_packet_lists(s);
1004
1005 if (stream_alloc_packet_lists(s) < 0) {
1006 stream_free_packet_lists(s);
1007 return -ENOMEM;
1008 }
1009
1010 return 0;
1011}
1012
1013static struct stream *stream_alloc(struct amdtp_host *host)
1014{
1015 struct stream *s;
1016 unsigned long flags;
1017
1018 s = kmalloc(sizeof(struct stream), SLAB_KERNEL);
1019 if (s == NULL)
1020 return NULL;
1021
1022 memset(s, 0, sizeof(struct stream));
1023 s->host = host;
1024
1025 s->input = buffer_alloc(BUFFER_SIZE);
1026 if (s->input == NULL) {
1027 kfree(s);
1028 return NULL;
1029 }
1030
1031 s->descriptor_pool = pci_pool_create("descriptor pool", host->ohci->dev,
1032 sizeof(struct descriptor_block),
1033 16, 0);
1034
1035 if (s->descriptor_pool == NULL) {
1036 kfree(s->input);
1037 kfree(s);
1038 return NULL;
1039 }
1040
1041 INIT_LIST_HEAD(&s->free_packet_lists);
1042 INIT_LIST_HEAD(&s->dma_packet_lists);
1043
1044 init_waitqueue_head(&s->packet_list_wait);
1045 spin_lock_init(&s->packet_list_lock);
1046
1047 ohci1394_init_iso_tasklet(&s->iso_tasklet, OHCI_ISO_TRANSMIT,
1048 stream_shift_packet_lists,
1049 (unsigned long) s);
1050
1051 if (ohci1394_register_iso_tasklet(host->ohci, &s->iso_tasklet) < 0) {
1052 pci_pool_destroy(s->descriptor_pool);
1053 kfree(s->input);
1054 kfree(s);
1055 return NULL;
1056 }
1057
1058 spin_lock_irqsave(&host->stream_list_lock, flags);
1059 list_add_tail(&s->link, &host->stream_list);
1060 spin_unlock_irqrestore(&host->stream_list_lock, flags);
1061
1062 return s;
1063}
1064
1065static void stream_free(struct stream *s)
1066{
1067 unsigned long flags;
1068
1069 /* Stop the DMA. We wait for the dma packet list to become
1070 * empty and let the dma controller run out of programs. This
1071 * seems to be more reliable than stopping it directly, since
1072 * that sometimes generates an it transmit interrupt if we
1073 * later re-enable the context.
1074 */
1075 wait_event_interruptible(s->packet_list_wait,
1076 list_empty(&s->dma_packet_lists));
1077
1078 ohci1394_stop_it_ctx(s->host->ohci, s->iso_tasklet.context, 1);
1079 ohci1394_unregister_iso_tasklet(s->host->ohci, &s->iso_tasklet);
1080
1081 if (s->opcr != NULL)
1082 cmp_unregister_opcr(s->host->host, s->opcr);
1083
1084 spin_lock_irqsave(&s->host->stream_list_lock, flags);
1085 list_del(&s->link);
1086 spin_unlock_irqrestore(&s->host->stream_list_lock, flags);
1087
1088 kfree(s->input);
1089
1090 stream_free_packet_lists(s);
1091 pci_pool_destroy(s->descriptor_pool);
1092
1093 kfree(s);
1094}
1095
1096/* File operations */
1097
1098static ssize_t amdtp_write(struct file *file, const char __user *buffer, size_t count,
1099 loff_t *offset_is_ignored)
1100{
1101 struct stream *s = file->private_data;
1102 unsigned char *p;
1103 int i;
1104 size_t length;
1105
1106 if (s->packet_pool == NULL)
1107 return -EBADFD;
1108
1109 /* Fill the circular buffer from the input buffer and call the
1110 * iso packer when the buffer is full. The iso packer may
1111 * leave bytes in the buffer for two reasons: either the
1112 * remaining bytes wasn't enough to build a new packet, or
1113 * there were no free packet lists. In the first case we
1114 * re-fill the buffer and call the iso packer again or return
1115 * if we used all the data from userspace. In the second
1116 * case, the wait_event_interruptible will block until the irq
1117 * handler frees a packet list.
1118 */
1119
1120 for (i = 0; i < count; i += length) {
1121 p = buffer_put_bytes(s->input, count - i, &length);
1122 if (copy_from_user(p, buffer + i, length))
1123 return -EFAULT;
1124 if (s->input->length < s->input->size)
1125 continue;
1126
1127 stream_flush(s);
1128
1129 if (s->current_packet_list != NULL)
1130 continue;
1131
1132 if (file->f_flags & O_NONBLOCK)
1133 return i + length > 0 ? i + length : -EAGAIN;
1134
1135 if (wait_event_interruptible(s->packet_list_wait,
1136 !list_empty(&s->free_packet_lists)))
1137 return -EINTR;
1138 }
1139
1140 return count;
1141}
1142
1143static long amdtp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1144{
1145 struct stream *s = file->private_data;
1146 struct amdtp_ioctl cfg;
1147 int err;
1148 lock_kernel();
1149 switch(cmd)
1150 {
1151 case AMDTP_IOC_PLUG:
1152 case AMDTP_IOC_CHANNEL:
1153 if (copy_from_user(&cfg, (struct amdtp_ioctl __user *) arg, sizeof cfg))
1154 err = -EFAULT;
1155 else
1156 err = stream_configure(s, cmd, &cfg);
1157 break;
1158
1159 default:
1160 err = -EINVAL;
1161 break;
1162 }
1163 unlock_kernel();
1164 return err;
1165}
1166
1167static unsigned int amdtp_poll(struct file *file, poll_table *pt)
1168{
1169 struct stream *s = file->private_data;
1170
1171 poll_wait(file, &s->packet_list_wait, pt);
1172
1173 if (!list_empty(&s->free_packet_lists))
1174 return POLLOUT | POLLWRNORM;
1175 else
1176 return 0;
1177}
1178
1179static int amdtp_open(struct inode *inode, struct file *file)
1180{
1181 struct amdtp_host *host;
1182 int i = ieee1394_file_to_instance(file);
1183
1184 host = hpsb_get_hostinfo_bykey(&amdtp_highlevel, i);
1185 if (host == NULL)
1186 return -ENODEV;
1187
1188 file->private_data = stream_alloc(host);
1189 if (file->private_data == NULL)
1190 return -ENOMEM;
1191
1192 return 0;
1193}
1194
1195static int amdtp_release(struct inode *inode, struct file *file)
1196{
1197 struct stream *s = file->private_data;
1198
1199 stream_free(s);
1200
1201 return 0;
1202}
1203
1204static struct cdev amdtp_cdev;
1205static struct file_operations amdtp_fops =
1206{
1207 .owner = THIS_MODULE,
1208 .write = amdtp_write,
1209 .poll = amdtp_poll,
1210 .unlocked_ioctl = amdtp_ioctl,
1211 .compat_ioctl = amdtp_ioctl, /* All amdtp ioctls are compatible */
1212 .open = amdtp_open,
1213 .release = amdtp_release
1214};
1215
1216/* IEEE1394 Subsystem functions */
1217
1218static void amdtp_add_host(struct hpsb_host *host)
1219{
1220 struct amdtp_host *ah;
1221 int minor;
1222
1223 if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME) != 0)
1224 return;
1225
1226 ah = hpsb_create_hostinfo(&amdtp_highlevel, host, sizeof(*ah));
1227 if (!ah) {
1228 HPSB_ERR("amdtp: Unable able to alloc hostinfo");
1229 return;
1230 }
1231
1232 ah->host = host;
1233 ah->ohci = host->hostdata;
1234
1235 hpsb_set_hostinfo_key(&amdtp_highlevel, host, ah->host->id);
1236
1237 minor = IEEE1394_MINOR_BLOCK_AMDTP * 16 + ah->host->id;
1238
1239 INIT_LIST_HEAD(&ah->stream_list);
1240 spin_lock_init(&ah->stream_list_lock);
1241
1242 devfs_mk_cdev(MKDEV(IEEE1394_MAJOR, minor),
1243 S_IFCHR|S_IRUSR|S_IWUSR, "amdtp/%d", ah->host->id);
1244}
1245
1246static void amdtp_remove_host(struct hpsb_host *host)
1247{
1248 struct amdtp_host *ah = hpsb_get_hostinfo(&amdtp_highlevel, host);
1249
1250 if (ah)
1251 devfs_remove("amdtp/%d", ah->host->id);
1252
1253 return;
1254}
1255
1256static struct hpsb_highlevel amdtp_highlevel = {
1257 .name = "amdtp",
1258 .add_host = amdtp_add_host,
1259 .remove_host = amdtp_remove_host,
1260};
1261
1262/* Module interface */
1263
1264MODULE_AUTHOR("Kristian Hogsberg <hogsberg@users.sf.net>");
1265MODULE_DESCRIPTION("Driver for Audio & Music Data Transmission Protocol "
1266 "on OHCI boards.");
1267MODULE_SUPPORTED_DEVICE("amdtp");
1268MODULE_LICENSE("GPL");
1269
1270static int __init amdtp_init_module (void)
1271{
1272 cdev_init(&amdtp_cdev, &amdtp_fops);
1273 amdtp_cdev.owner = THIS_MODULE;
1274 kobject_set_name(&amdtp_cdev.kobj, "amdtp");
1275 if (cdev_add(&amdtp_cdev, IEEE1394_AMDTP_DEV, 16)) {
1276 HPSB_ERR("amdtp: unable to add char device");
1277 return -EIO;
1278 }
1279
1280 devfs_mk_dir("amdtp");
1281
1282 hpsb_register_highlevel(&amdtp_highlevel);
1283
1284 HPSB_INFO("Loaded AMDTP driver");
1285
1286 return 0;
1287}
1288
1289static void __exit amdtp_exit_module (void)
1290{
1291 hpsb_unregister_highlevel(&amdtp_highlevel);
1292 devfs_remove("amdtp");
1293 cdev_del(&amdtp_cdev);
1294
1295 HPSB_INFO("Unloaded AMDTP driver");
1296}
1297
1298module_init(amdtp_init_module);
1299module_exit(amdtp_exit_module);
1300MODULE_ALIAS_CHARDEV(IEEE1394_MAJOR, IEEE1394_MINOR_BLOCK_AMDTP * 16);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 00:10:16 -0500