aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/idle/intel_idle.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/idle/intel_idle.c')
-rw-r--r--drivers/idle/intel_idle.c108
1 files changed, 54 insertions, 54 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 9b7ee7e427df..9cceacb92f9d 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -128,28 +128,28 @@ static struct cpuidle_state nehalem_cstates[] = {
128 { 128 {
129 .name = "C1-NHM", 129 .name = "C1-NHM",
130 .desc = "MWAIT 0x00", 130 .desc = "MWAIT 0x00",
131 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 131 .flags = MWAIT2flg(0x00),
132 .exit_latency = 3, 132 .exit_latency = 3,
133 .target_residency = 6, 133 .target_residency = 6,
134 .enter = &intel_idle }, 134 .enter = &intel_idle },
135 { 135 {
136 .name = "C1E-NHM", 136 .name = "C1E-NHM",
137 .desc = "MWAIT 0x01", 137 .desc = "MWAIT 0x01",
138 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 138 .flags = MWAIT2flg(0x01),
139 .exit_latency = 10, 139 .exit_latency = 10,
140 .target_residency = 20, 140 .target_residency = 20,
141 .enter = &intel_idle }, 141 .enter = &intel_idle },
142 { 142 {
143 .name = "C3-NHM", 143 .name = "C3-NHM",
144 .desc = "MWAIT 0x10", 144 .desc = "MWAIT 0x10",
145 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 145 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
146 .exit_latency = 20, 146 .exit_latency = 20,
147 .target_residency = 80, 147 .target_residency = 80,
148 .enter = &intel_idle }, 148 .enter = &intel_idle },
149 { 149 {
150 .name = "C6-NHM", 150 .name = "C6-NHM",
151 .desc = "MWAIT 0x20", 151 .desc = "MWAIT 0x20",
152 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 152 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
153 .exit_latency = 200, 153 .exit_latency = 200,
154 .target_residency = 800, 154 .target_residency = 800,
155 .enter = &intel_idle }, 155 .enter = &intel_idle },
@@ -161,35 +161,35 @@ static struct cpuidle_state snb_cstates[] = {
161 { 161 {
162 .name = "C1-SNB", 162 .name = "C1-SNB",
163 .desc = "MWAIT 0x00", 163 .desc = "MWAIT 0x00",
164 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 164 .flags = MWAIT2flg(0x00),
165 .exit_latency = 2, 165 .exit_latency = 2,
166 .target_residency = 2, 166 .target_residency = 2,
167 .enter = &intel_idle }, 167 .enter = &intel_idle },
168 { 168 {
169 .name = "C1E-SNB", 169 .name = "C1E-SNB",
170 .desc = "MWAIT 0x01", 170 .desc = "MWAIT 0x01",
171 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 171 .flags = MWAIT2flg(0x01),
172 .exit_latency = 10, 172 .exit_latency = 10,
173 .target_residency = 20, 173 .target_residency = 20,
174 .enter = &intel_idle }, 174 .enter = &intel_idle },
175 { 175 {
176 .name = "C3-SNB", 176 .name = "C3-SNB",
177 .desc = "MWAIT 0x10", 177 .desc = "MWAIT 0x10",
178 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 178 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
179 .exit_latency = 80, 179 .exit_latency = 80,
180 .target_residency = 211, 180 .target_residency = 211,
181 .enter = &intel_idle }, 181 .enter = &intel_idle },
182 { 182 {
183 .name = "C6-SNB", 183 .name = "C6-SNB",
184 .desc = "MWAIT 0x20", 184 .desc = "MWAIT 0x20",
185 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 185 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
186 .exit_latency = 104, 186 .exit_latency = 104,
187 .target_residency = 345, 187 .target_residency = 345,
188 .enter = &intel_idle }, 188 .enter = &intel_idle },
189 { 189 {
190 .name = "C7-SNB", 190 .name = "C7-SNB",
191 .desc = "MWAIT 0x30", 191 .desc = "MWAIT 0x30",
192 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 192 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
193 .exit_latency = 109, 193 .exit_latency = 109,
194 .target_residency = 345, 194 .target_residency = 345,
195 .enter = &intel_idle }, 195 .enter = &intel_idle },
@@ -201,42 +201,42 @@ static struct cpuidle_state byt_cstates[] = {
201 { 201 {
202 .name = "C1-BYT", 202 .name = "C1-BYT",
203 .desc = "MWAIT 0x00", 203 .desc = "MWAIT 0x00",
204 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 204 .flags = MWAIT2flg(0x00),
205 .exit_latency = 1, 205 .exit_latency = 1,
206 .target_residency = 1, 206 .target_residency = 1,
207 .enter = &intel_idle }, 207 .enter = &intel_idle },
208 { 208 {
209 .name = "C1E-BYT", 209 .name = "C1E-BYT",
210 .desc = "MWAIT 0x01", 210 .desc = "MWAIT 0x01",
211 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 211 .flags = MWAIT2flg(0x01),
212 .exit_latency = 15, 212 .exit_latency = 15,
213 .target_residency = 30, 213 .target_residency = 30,
214 .enter = &intel_idle }, 214 .enter = &intel_idle },
215 { 215 {
216 .name = "C6N-BYT", 216 .name = "C6N-BYT",
217 .desc = "MWAIT 0x58", 217 .desc = "MWAIT 0x58",
218 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 218 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
219 .exit_latency = 40, 219 .exit_latency = 40,
220 .target_residency = 275, 220 .target_residency = 275,
221 .enter = &intel_idle }, 221 .enter = &intel_idle },
222 { 222 {
223 .name = "C6S-BYT", 223 .name = "C6S-BYT",
224 .desc = "MWAIT 0x52", 224 .desc = "MWAIT 0x52",
225 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 225 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
226 .exit_latency = 140, 226 .exit_latency = 140,
227 .target_residency = 560, 227 .target_residency = 560,
228 .enter = &intel_idle }, 228 .enter = &intel_idle },
229 { 229 {
230 .name = "C7-BYT", 230 .name = "C7-BYT",
231 .desc = "MWAIT 0x60", 231 .desc = "MWAIT 0x60",
232 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 232 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
233 .exit_latency = 1200, 233 .exit_latency = 1200,
234 .target_residency = 1500, 234 .target_residency = 1500,
235 .enter = &intel_idle }, 235 .enter = &intel_idle },
236 { 236 {
237 .name = "C7S-BYT", 237 .name = "C7S-BYT",
238 .desc = "MWAIT 0x64", 238 .desc = "MWAIT 0x64",
239 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 239 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
240 .exit_latency = 10000, 240 .exit_latency = 10000,
241 .target_residency = 20000, 241 .target_residency = 20000,
242 .enter = &intel_idle }, 242 .enter = &intel_idle },
@@ -248,35 +248,35 @@ static struct cpuidle_state ivb_cstates[] = {
248 { 248 {
249 .name = "C1-IVB", 249 .name = "C1-IVB",
250 .desc = "MWAIT 0x00", 250 .desc = "MWAIT 0x00",
251 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 251 .flags = MWAIT2flg(0x00),
252 .exit_latency = 1, 252 .exit_latency = 1,
253 .target_residency = 1, 253 .target_residency = 1,
254 .enter = &intel_idle }, 254 .enter = &intel_idle },
255 { 255 {
256 .name = "C1E-IVB", 256 .name = "C1E-IVB",
257 .desc = "MWAIT 0x01", 257 .desc = "MWAIT 0x01",
258 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 258 .flags = MWAIT2flg(0x01),
259 .exit_latency = 10, 259 .exit_latency = 10,
260 .target_residency = 20, 260 .target_residency = 20,
261 .enter = &intel_idle }, 261 .enter = &intel_idle },
262 { 262 {
263 .name = "C3-IVB", 263 .name = "C3-IVB",
264 .desc = "MWAIT 0x10", 264 .desc = "MWAIT 0x10",
265 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 265 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
266 .exit_latency = 59, 266 .exit_latency = 59,
267 .target_residency = 156, 267 .target_residency = 156,
268 .enter = &intel_idle }, 268 .enter = &intel_idle },
269 { 269 {
270 .name = "C6-IVB", 270 .name = "C6-IVB",
271 .desc = "MWAIT 0x20", 271 .desc = "MWAIT 0x20",
272 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 272 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
273 .exit_latency = 80, 273 .exit_latency = 80,
274 .target_residency = 300, 274 .target_residency = 300,
275 .enter = &intel_idle }, 275 .enter = &intel_idle },
276 { 276 {
277 .name = "C7-IVB", 277 .name = "C7-IVB",
278 .desc = "MWAIT 0x30", 278 .desc = "MWAIT 0x30",
279 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 279 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
280 .exit_latency = 87, 280 .exit_latency = 87,
281 .target_residency = 300, 281 .target_residency = 300,
282 .enter = &intel_idle }, 282 .enter = &intel_idle },
@@ -288,28 +288,28 @@ static struct cpuidle_state ivt_cstates[] = {
288 { 288 {
289 .name = "C1-IVT", 289 .name = "C1-IVT",
290 .desc = "MWAIT 0x00", 290 .desc = "MWAIT 0x00",
291 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 291 .flags = MWAIT2flg(0x00),
292 .exit_latency = 1, 292 .exit_latency = 1,
293 .target_residency = 1, 293 .target_residency = 1,
294 .enter = &intel_idle }, 294 .enter = &intel_idle },
295 { 295 {
296 .name = "C1E-IVT", 296 .name = "C1E-IVT",
297 .desc = "MWAIT 0x01", 297 .desc = "MWAIT 0x01",
298 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 298 .flags = MWAIT2flg(0x01),
299 .exit_latency = 10, 299 .exit_latency = 10,
300 .target_residency = 80, 300 .target_residency = 80,
301 .enter = &intel_idle }, 301 .enter = &intel_idle },
302 { 302 {
303 .name = "C3-IVT", 303 .name = "C3-IVT",
304 .desc = "MWAIT 0x10", 304 .desc = "MWAIT 0x10",
305 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 305 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
306 .exit_latency = 59, 306 .exit_latency = 59,
307 .target_residency = 156, 307 .target_residency = 156,
308 .enter = &intel_idle }, 308 .enter = &intel_idle },
309 { 309 {
310 .name = "C6-IVT", 310 .name = "C6-IVT",
311 .desc = "MWAIT 0x20", 311 .desc = "MWAIT 0x20",
312 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 312 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
313 .exit_latency = 82, 313 .exit_latency = 82,
314 .target_residency = 300, 314 .target_residency = 300,
315 .enter = &intel_idle }, 315 .enter = &intel_idle },
@@ -321,28 +321,28 @@ static struct cpuidle_state ivt_cstates_4s[] = {
321 { 321 {
322 .name = "C1-IVT-4S", 322 .name = "C1-IVT-4S",
323 .desc = "MWAIT 0x00", 323 .desc = "MWAIT 0x00",
324 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 324 .flags = MWAIT2flg(0x00),
325 .exit_latency = 1, 325 .exit_latency = 1,
326 .target_residency = 1, 326 .target_residency = 1,
327 .enter = &intel_idle }, 327 .enter = &intel_idle },
328 { 328 {
329 .name = "C1E-IVT-4S", 329 .name = "C1E-IVT-4S",
330 .desc = "MWAIT 0x01", 330 .desc = "MWAIT 0x01",
331 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 331 .flags = MWAIT2flg(0x01),
332 .exit_latency = 10, 332 .exit_latency = 10,
333 .target_residency = 250, 333 .target_residency = 250,
334 .enter = &intel_idle }, 334 .enter = &intel_idle },
335 { 335 {
336 .name = "C3-IVT-4S", 336 .name = "C3-IVT-4S",
337 .desc = "MWAIT 0x10", 337 .desc = "MWAIT 0x10",
338 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 338 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
339 .exit_latency = 59, 339 .exit_latency = 59,
340 .target_residency = 300, 340 .target_residency = 300,
341 .enter = &intel_idle }, 341 .enter = &intel_idle },
342 { 342 {
343 .name = "C6-IVT-4S", 343 .name = "C6-IVT-4S",
344 .desc = "MWAIT 0x20", 344 .desc = "MWAIT 0x20",
345 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 345 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
346 .exit_latency = 84, 346 .exit_latency = 84,
347 .target_residency = 400, 347 .target_residency = 400,
348 .enter = &intel_idle }, 348 .enter = &intel_idle },
@@ -354,28 +354,28 @@ static struct cpuidle_state ivt_cstates_8s[] = {
354 { 354 {
355 .name = "C1-IVT-8S", 355 .name = "C1-IVT-8S",
356 .desc = "MWAIT 0x00", 356 .desc = "MWAIT 0x00",
357 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 357 .flags = MWAIT2flg(0x00),
358 .exit_latency = 1, 358 .exit_latency = 1,
359 .target_residency = 1, 359 .target_residency = 1,
360 .enter = &intel_idle }, 360 .enter = &intel_idle },
361 { 361 {
362 .name = "C1E-IVT-8S", 362 .name = "C1E-IVT-8S",
363 .desc = "MWAIT 0x01", 363 .desc = "MWAIT 0x01",
364 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 364 .flags = MWAIT2flg(0x01),
365 .exit_latency = 10, 365 .exit_latency = 10,
366 .target_residency = 500, 366 .target_residency = 500,
367 .enter = &intel_idle }, 367 .enter = &intel_idle },
368 { 368 {
369 .name = "C3-IVT-8S", 369 .name = "C3-IVT-8S",
370 .desc = "MWAIT 0x10", 370 .desc = "MWAIT 0x10",
371 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 371 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
372 .exit_latency = 59, 372 .exit_latency = 59,
373 .target_residency = 600, 373 .target_residency = 600,
374 .enter = &intel_idle }, 374 .enter = &intel_idle },
375 { 375 {
376 .name = "C6-IVT-8S", 376 .name = "C6-IVT-8S",
377 .desc = "MWAIT 0x20", 377 .desc = "MWAIT 0x20",
378 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 378 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
379 .exit_latency = 88, 379 .exit_latency = 88,
380 .target_residency = 700, 380 .target_residency = 700,
381 .enter = &intel_idle }, 381 .enter = &intel_idle },
@@ -387,56 +387,56 @@ static struct cpuidle_state hsw_cstates[] = {
387 { 387 {
388 .name = "C1-HSW", 388 .name = "C1-HSW",
389 .desc = "MWAIT 0x00", 389 .desc = "MWAIT 0x00",
390 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 390 .flags = MWAIT2flg(0x00),
391 .exit_latency = 2, 391 .exit_latency = 2,
392 .target_residency = 2, 392 .target_residency = 2,
393 .enter = &intel_idle }, 393 .enter = &intel_idle },
394 { 394 {
395 .name = "C1E-HSW", 395 .name = "C1E-HSW",
396 .desc = "MWAIT 0x01", 396 .desc = "MWAIT 0x01",
397 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 397 .flags = MWAIT2flg(0x01),
398 .exit_latency = 10, 398 .exit_latency = 10,
399 .target_residency = 20, 399 .target_residency = 20,
400 .enter = &intel_idle }, 400 .enter = &intel_idle },
401 { 401 {
402 .name = "C3-HSW", 402 .name = "C3-HSW",
403 .desc = "MWAIT 0x10", 403 .desc = "MWAIT 0x10",
404 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 404 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
405 .exit_latency = 33, 405 .exit_latency = 33,
406 .target_residency = 100, 406 .target_residency = 100,
407 .enter = &intel_idle }, 407 .enter = &intel_idle },
408 { 408 {
409 .name = "C6-HSW", 409 .name = "C6-HSW",
410 .desc = "MWAIT 0x20", 410 .desc = "MWAIT 0x20",
411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
412 .exit_latency = 133, 412 .exit_latency = 133,
413 .target_residency = 400, 413 .target_residency = 400,
414 .enter = &intel_idle }, 414 .enter = &intel_idle },
415 { 415 {
416 .name = "C7s-HSW", 416 .name = "C7s-HSW",
417 .desc = "MWAIT 0x32", 417 .desc = "MWAIT 0x32",
418 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 418 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
419 .exit_latency = 166, 419 .exit_latency = 166,
420 .target_residency = 500, 420 .target_residency = 500,
421 .enter = &intel_idle }, 421 .enter = &intel_idle },
422 { 422 {
423 .name = "C8-HSW", 423 .name = "C8-HSW",
424 .desc = "MWAIT 0x40", 424 .desc = "MWAIT 0x40",
425 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 425 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
426 .exit_latency = 300, 426 .exit_latency = 300,
427 .target_residency = 900, 427 .target_residency = 900,
428 .enter = &intel_idle }, 428 .enter = &intel_idle },
429 { 429 {
430 .name = "C9-HSW", 430 .name = "C9-HSW",
431 .desc = "MWAIT 0x50", 431 .desc = "MWAIT 0x50",
432 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 432 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
433 .exit_latency = 600, 433 .exit_latency = 600,
434 .target_residency = 1800, 434 .target_residency = 1800,
435 .enter = &intel_idle }, 435 .enter = &intel_idle },
436 { 436 {
437 .name = "C10-HSW", 437 .name = "C10-HSW",
438 .desc = "MWAIT 0x60", 438 .desc = "MWAIT 0x60",
439 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 439 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
440 .exit_latency = 2600, 440 .exit_latency = 2600,
441 .target_residency = 7700, 441 .target_residency = 7700,
442 .enter = &intel_idle }, 442 .enter = &intel_idle },
@@ -447,56 +447,56 @@ static struct cpuidle_state bdw_cstates[] = {
447 { 447 {
448 .name = "C1-BDW", 448 .name = "C1-BDW",
449 .desc = "MWAIT 0x00", 449 .desc = "MWAIT 0x00",
450 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 450 .flags = MWAIT2flg(0x00),
451 .exit_latency = 2, 451 .exit_latency = 2,
452 .target_residency = 2, 452 .target_residency = 2,
453 .enter = &intel_idle }, 453 .enter = &intel_idle },
454 { 454 {
455 .name = "C1E-BDW", 455 .name = "C1E-BDW",
456 .desc = "MWAIT 0x01", 456 .desc = "MWAIT 0x01",
457 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 457 .flags = MWAIT2flg(0x01),
458 .exit_latency = 10, 458 .exit_latency = 10,
459 .target_residency = 20, 459 .target_residency = 20,
460 .enter = &intel_idle }, 460 .enter = &intel_idle },
461 { 461 {
462 .name = "C3-BDW", 462 .name = "C3-BDW",
463 .desc = "MWAIT 0x10", 463 .desc = "MWAIT 0x10",
464 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 464 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
465 .exit_latency = 40, 465 .exit_latency = 40,
466 .target_residency = 100, 466 .target_residency = 100,
467 .enter = &intel_idle }, 467 .enter = &intel_idle },
468 { 468 {
469 .name = "C6-BDW", 469 .name = "C6-BDW",
470 .desc = "MWAIT 0x20", 470 .desc = "MWAIT 0x20",
471 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 471 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
472 .exit_latency = 133, 472 .exit_latency = 133,
473 .target_residency = 400, 473 .target_residency = 400,
474 .enter = &intel_idle }, 474 .enter = &intel_idle },
475 { 475 {
476 .name = "C7s-BDW", 476 .name = "C7s-BDW",
477 .desc = "MWAIT 0x32", 477 .desc = "MWAIT 0x32",
478 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 478 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
479 .exit_latency = 166, 479 .exit_latency = 166,
480 .target_residency = 500, 480 .target_residency = 500,
481 .enter = &intel_idle }, 481 .enter = &intel_idle },
482 { 482 {
483 .name = "C8-BDW", 483 .name = "C8-BDW",
484 .desc = "MWAIT 0x40", 484 .desc = "MWAIT 0x40",
485 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 485 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
486 .exit_latency = 300, 486 .exit_latency = 300,
487 .target_residency = 900, 487 .target_residency = 900,
488 .enter = &intel_idle }, 488 .enter = &intel_idle },
489 { 489 {
490 .name = "C9-BDW", 490 .name = "C9-BDW",
491 .desc = "MWAIT 0x50", 491 .desc = "MWAIT 0x50",
492 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 492 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
493 .exit_latency = 600, 493 .exit_latency = 600,
494 .target_residency = 1800, 494 .target_residency = 1800,
495 .enter = &intel_idle }, 495 .enter = &intel_idle },
496 { 496 {
497 .name = "C10-BDW", 497 .name = "C10-BDW",
498 .desc = "MWAIT 0x60", 498 .desc = "MWAIT 0x60",
499 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 499 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
500 .exit_latency = 2600, 500 .exit_latency = 2600,
501 .target_residency = 7700, 501 .target_residency = 7700,
502 .enter = &intel_idle }, 502 .enter = &intel_idle },
@@ -508,28 +508,28 @@ static struct cpuidle_state atom_cstates[] = {
508 { 508 {
509 .name = "C1E-ATM", 509 .name = "C1E-ATM",
510 .desc = "MWAIT 0x00", 510 .desc = "MWAIT 0x00",
511 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 511 .flags = MWAIT2flg(0x00),
512 .exit_latency = 10, 512 .exit_latency = 10,
513 .target_residency = 20, 513 .target_residency = 20,
514 .enter = &intel_idle }, 514 .enter = &intel_idle },
515 { 515 {
516 .name = "C2-ATM", 516 .name = "C2-ATM",
517 .desc = "MWAIT 0x10", 517 .desc = "MWAIT 0x10",
518 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID, 518 .flags = MWAIT2flg(0x10),
519 .exit_latency = 20, 519 .exit_latency = 20,
520 .target_residency = 80, 520 .target_residency = 80,
521 .enter = &intel_idle }, 521 .enter = &intel_idle },
522 { 522 {
523 .name = "C4-ATM", 523 .name = "C4-ATM",
524 .desc = "MWAIT 0x30", 524 .desc = "MWAIT 0x30",
525 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 525 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
526 .exit_latency = 100, 526 .exit_latency = 100,
527 .target_residency = 400, 527 .target_residency = 400,
528 .enter = &intel_idle }, 528 .enter = &intel_idle },
529 { 529 {
530 .name = "C6-ATM", 530 .name = "C6-ATM",
531 .desc = "MWAIT 0x52", 531 .desc = "MWAIT 0x52",
532 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 532 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
533 .exit_latency = 140, 533 .exit_latency = 140,
534 .target_residency = 560, 534 .target_residency = 560,
535 .enter = &intel_idle }, 535 .enter = &intel_idle },
@@ -540,14 +540,14 @@ static struct cpuidle_state avn_cstates[] = {
540 { 540 {
541 .name = "C1-AVN", 541 .name = "C1-AVN",
542 .desc = "MWAIT 0x00", 542 .desc = "MWAIT 0x00",
543 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 543 .flags = MWAIT2flg(0x00),
544 .exit_latency = 2, 544 .exit_latency = 2,
545 .target_residency = 2, 545 .target_residency = 2,
546 .enter = &intel_idle }, 546 .enter = &intel_idle },
547 { 547 {
548 .name = "C6-AVN", 548 .name = "C6-AVN",
549 .desc = "MWAIT 0x51", 549 .desc = "MWAIT 0x51",
550 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 550 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
551 .exit_latency = 15, 551 .exit_latency = 15,
552 .target_residency = 45, 552 .target_residency = 45,
553 .enter = &intel_idle }, 553 .enter = &intel_idle },
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 15:51:45 -0500