diff options
Diffstat (limited to 'drivers/ide')
-rw-r--r-- | drivers/ide/alim15x3.c | 12 | ||||
-rw-r--r-- | drivers/ide/cmd64x.c | 17 | ||||
-rw-r--r-- | drivers/ide/cy82c693.c | 27 | ||||
-rw-r--r-- | drivers/ide/pdc202xx_old.c | 15 | ||||
-rw-r--r-- | drivers/ide/sis5513.c | 9 | ||||
-rw-r--r-- | drivers/ide/sl82c105.c | 24 |
6 files changed, 2 insertions, 102 deletions
diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c index e59b6dee9ae2..0abc43f3101e 100644 --- a/drivers/ide/alim15x3.c +++ b/drivers/ide/alim15x3.c | |||
@@ -40,16 +40,6 @@ | |||
40 | #define DRV_NAME "alim15x3" | 40 | #define DRV_NAME "alim15x3" |
41 | 41 | ||
42 | /* | 42 | /* |
43 | * Allow UDMA on M1543C-E chipset for WDC disks that ignore CRC checking | ||
44 | * (this is DANGEROUS and could result in data corruption). | ||
45 | */ | ||
46 | static int wdc_udma; | ||
47 | |||
48 | module_param(wdc_udma, bool, 0); | ||
49 | MODULE_PARM_DESC(wdc_udma, | ||
50 | "allow UDMA on M1543C-E chipset for WDC disks (DANGEROUS)"); | ||
51 | |||
52 | /* | ||
53 | * ALi devices are not plug in. Otherwise these static values would | 43 | * ALi devices are not plug in. Otherwise these static values would |
54 | * need to go. They ought to go away anyway | 44 | * need to go. They ought to go away anyway |
55 | */ | 45 | */ |
@@ -132,7 +122,7 @@ static u8 ali_udma_filter(ide_drive_t *drive) | |||
132 | if (m5229_revision > 0x20 && m5229_revision < 0xC2) { | 122 | if (m5229_revision > 0x20 && m5229_revision < 0xC2) { |
133 | if (drive->media != ide_disk) | 123 | if (drive->media != ide_disk) |
134 | return 0; | 124 | return 0; |
135 | if (wdc_udma == 0 && chip_is_1543c_e && | 125 | if (chip_is_1543c_e && |
136 | strstr((char *)&drive->id[ATA_ID_PROD], "WDC ")) | 126 | strstr((char *)&drive->id[ATA_ID_PROD], "WDC ")) |
137 | return 0; | 127 | return 0; |
138 | } | 128 | } |
diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c index ca0c46f6580a..f2500c8826bb 100644 --- a/drivers/ide/cmd64x.c +++ b/drivers/ide/cmd64x.c | |||
@@ -20,14 +20,6 @@ | |||
20 | 20 | ||
21 | #define DRV_NAME "cmd64x" | 21 | #define DRV_NAME "cmd64x" |
22 | 22 | ||
23 | #define CMD_DEBUG 0 | ||
24 | |||
25 | #if CMD_DEBUG | ||
26 | #define cmdprintk(x...) printk(x) | ||
27 | #else | ||
28 | #define cmdprintk(x...) | ||
29 | #endif | ||
30 | |||
31 | /* | 23 | /* |
32 | * CMD64x specific registers definition. | 24 | * CMD64x specific registers definition. |
33 | */ | 25 | */ |
@@ -76,9 +68,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_ | |||
76 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; | 68 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; |
77 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; | 69 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; |
78 | 70 | ||
79 | cmdprintk("program_cycle_times parameters: total=%d, active=%d\n", | ||
80 | cycle_time, active_time); | ||
81 | |||
82 | cycle_count = quantize_timing( cycle_time, clock_time); | 71 | cycle_count = quantize_timing( cycle_time, clock_time); |
83 | active_count = quantize_timing(active_time, clock_time); | 72 | active_count = quantize_timing(active_time, clock_time); |
84 | recovery_count = cycle_count - active_count; | 73 | recovery_count = cycle_count - active_count; |
@@ -94,9 +83,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_ | |||
94 | if (active_count > 16) /* shouldn't actually happen... */ | 83 | if (active_count > 16) /* shouldn't actually happen... */ |
95 | active_count = 16; | 84 | active_count = 16; |
96 | 85 | ||
97 | cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n", | ||
98 | cycle_count, active_count, recovery_count); | ||
99 | |||
100 | /* | 86 | /* |
101 | * Convert values to internal chipset representation | 87 | * Convert values to internal chipset representation |
102 | */ | 88 | */ |
@@ -106,7 +92,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_ | |||
106 | /* Program the active/recovery counts into the DRWTIM register */ | 92 | /* Program the active/recovery counts into the DRWTIM register */ |
107 | drwtim = (active_count << 4) | recovery_count; | 93 | drwtim = (active_count << 4) | recovery_count; |
108 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); | 94 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); |
109 | cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]); | ||
110 | } | 95 | } |
111 | 96 | ||
112 | /* | 97 | /* |
@@ -150,7 +135,6 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) | |||
150 | 135 | ||
151 | if (setup_count > 5) /* shouldn't actually happen... */ | 136 | if (setup_count > 5) /* shouldn't actually happen... */ |
152 | setup_count = 5; | 137 | setup_count = 5; |
153 | cmdprintk("Final address setup count: %d\n", setup_count); | ||
154 | 138 | ||
155 | /* | 139 | /* |
156 | * Program the address setup clocks into the ARTTIM registers. | 140 | * Program the address setup clocks into the ARTTIM registers. |
@@ -162,7 +146,6 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) | |||
162 | arttim &= ~0xc0; | 146 | arttim &= ~0xc0; |
163 | arttim |= setup_values[setup_count]; | 147 | arttim |= setup_values[setup_count]; |
164 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); | 148 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); |
165 | cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]); | ||
166 | } | 149 | } |
167 | 150 | ||
168 | /* | 151 | /* |
diff --git a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c index 74fc5401f407..d6e2cbbc53a0 100644 --- a/drivers/ide/cy82c693.c +++ b/drivers/ide/cy82c693.c | |||
@@ -51,11 +51,6 @@ | |||
51 | #define DRV_NAME "cy82c693" | 51 | #define DRV_NAME "cy82c693" |
52 | 52 | ||
53 | /* | 53 | /* |
54 | * The following are used to debug the driver. | ||
55 | */ | ||
56 | #define CY82C693_DEBUG_INFO 0 | ||
57 | |||
58 | /* | ||
59 | * NOTE: the value for busmaster timeout is tricky and I got it by | 54 | * NOTE: the value for busmaster timeout is tricky and I got it by |
60 | * trial and error! By using a to low value will cause DMA timeouts | 55 | * trial and error! By using a to low value will cause DMA timeouts |
61 | * and drop IDE performance, and by using a to high value will cause | 56 | * and drop IDE performance, and by using a to high value will cause |
@@ -176,11 +171,6 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) | |||
176 | outb(index, CY82_INDEX_PORT); | 171 | outb(index, CY82_INDEX_PORT); |
177 | outb(data, CY82_DATA_PORT); | 172 | outb(data, CY82_DATA_PORT); |
178 | 173 | ||
179 | #if CY82C693_DEBUG_INFO | ||
180 | printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", | ||
181 | drive->name, hwif->channel, drive->dn & 1, mode & 3, single); | ||
182 | #endif /* CY82C693_DEBUG_INFO */ | ||
183 | |||
184 | /* | 174 | /* |
185 | * note: below we set the value for Bus Master IDE TimeOut Register | 175 | * note: below we set the value for Bus Master IDE TimeOut Register |
186 | * I'm not absolutly sure what this does, but it solved my problem | 176 | * I'm not absolutly sure what this does, but it solved my problem |
@@ -194,11 +184,6 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode) | |||
194 | data = BUSMASTER_TIMEOUT; | 184 | data = BUSMASTER_TIMEOUT; |
195 | outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); | 185 | outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); |
196 | outb(data, CY82_DATA_PORT); | 186 | outb(data, CY82_DATA_PORT); |
197 | |||
198 | #if CY82C693_DEBUG_INFO | ||
199 | printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n", | ||
200 | drive->name, data); | ||
201 | #endif /* CY82C693_DEBUG_INFO */ | ||
202 | } | 187 | } |
203 | 188 | ||
204 | static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) | 189 | static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) |
@@ -239,8 +224,6 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) | |||
239 | pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r); | 224 | pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r); |
240 | pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w); | 225 | pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w); |
241 | pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8); | 226 | pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8); |
242 | |||
243 | addrCtrl &= 0xF; | ||
244 | } else { | 227 | } else { |
245 | /* | 228 | /* |
246 | * set slave drive | 229 | * set slave drive |
@@ -257,17 +240,7 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio) | |||
257 | pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r); | 240 | pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r); |
258 | pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w); | 241 | pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w); |
259 | pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8); | 242 | pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8); |
260 | |||
261 | addrCtrl >>= 4; | ||
262 | addrCtrl &= 0xF; | ||
263 | } | 243 | } |
264 | |||
265 | #if CY82C693_DEBUG_INFO | ||
266 | printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to " | ||
267 | "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", | ||
268 | drive->name, hwif->channel, drive->dn & 1, | ||
269 | addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8); | ||
270 | #endif /* CY82C693_DEBUG_INFO */ | ||
271 | } | 244 | } |
272 | 245 | ||
273 | static void __devinit init_iops_cy82c693(ide_hwif_t *hwif) | 246 | static void __devinit init_iops_cy82c693(ide_hwif_t *hwif) |
diff --git a/drivers/ide/pdc202xx_old.c b/drivers/ide/pdc202xx_old.c index cb812f3700e8..35161dd840a0 100644 --- a/drivers/ide/pdc202xx_old.c +++ b/drivers/ide/pdc202xx_old.c | |||
@@ -21,8 +21,6 @@ | |||
21 | 21 | ||
22 | #define DRV_NAME "pdc202xx_old" | 22 | #define DRV_NAME "pdc202xx_old" |
23 | 23 | ||
24 | #define PDC202XX_DEBUG_DRIVE_INFO 0 | ||
25 | |||
26 | static void pdc_old_disable_66MHz_clock(ide_hwif_t *); | 24 | static void pdc_old_disable_66MHz_clock(ide_hwif_t *); |
27 | 25 | ||
28 | static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) | 26 | static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) |
@@ -34,11 +32,6 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) | |||
34 | u8 AP = 0, BP = 0, CP = 0; | 32 | u8 AP = 0, BP = 0, CP = 0; |
35 | u8 TA = 0, TB = 0, TC = 0; | 33 | u8 TA = 0, TB = 0, TC = 0; |
36 | 34 | ||
37 | #if PDC202XX_DEBUG_DRIVE_INFO | ||
38 | u32 drive_conf = 0; | ||
39 | pci_read_config_dword(dev, drive_pci, &drive_conf); | ||
40 | #endif | ||
41 | |||
42 | /* | 35 | /* |
43 | * TODO: do this once per channel | 36 | * TODO: do this once per channel |
44 | */ | 37 | */ |
@@ -89,14 +82,6 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) | |||
89 | pci_write_config_byte(dev, drive_pci + 1, BP | TB); | 82 | pci_write_config_byte(dev, drive_pci + 1, BP | TB); |
90 | pci_write_config_byte(dev, drive_pci + 2, CP | TC); | 83 | pci_write_config_byte(dev, drive_pci + 2, CP | TC); |
91 | } | 84 | } |
92 | |||
93 | #if PDC202XX_DEBUG_DRIVE_INFO | ||
94 | printk(KERN_DEBUG "%s: %s drive%d 0x%08x ", | ||
95 | drive->name, ide_xfer_verbose(speed), | ||
96 | drive->dn, drive_conf); | ||
97 | pci_read_config_dword(dev, drive_pci, &drive_conf); | ||
98 | printk("0x%08x\n", drive_conf); | ||
99 | #endif | ||
100 | } | 85 | } |
101 | 86 | ||
102 | static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio) | 87 | static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
diff --git a/drivers/ide/sis5513.c b/drivers/ide/sis5513.c index 3b88eba04c9c..468706082fb5 100644 --- a/drivers/ide/sis5513.c +++ b/drivers/ide/sis5513.c | |||
@@ -632,12 +632,3 @@ module_exit(sis5513_ide_exit); | |||
632 | MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik"); | 632 | MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik"); |
633 | MODULE_DESCRIPTION("PCI driver module for SIS IDE"); | 633 | MODULE_DESCRIPTION("PCI driver module for SIS IDE"); |
634 | MODULE_LICENSE("GPL"); | 634 | MODULE_LICENSE("GPL"); |
635 | |||
636 | /* | ||
637 | * TODO: | ||
638 | * - CLEANUP | ||
639 | * - More checks in the config registers (force values instead of | ||
640 | * relying on the BIOS setting them correctly). | ||
641 | * - Further optimisations ? | ||
642 | * . for example ATA66+ regs 0x48 & 0x4A | ||
643 | */ | ||
diff --git a/drivers/ide/sl82c105.c b/drivers/ide/sl82c105.c index d698da470d6f..3c2bbf0057ea 100644 --- a/drivers/ide/sl82c105.c +++ b/drivers/ide/sl82c105.c | |||
@@ -24,13 +24,6 @@ | |||
24 | 24 | ||
25 | #define DRV_NAME "sl82c105" | 25 | #define DRV_NAME "sl82c105" |
26 | 26 | ||
27 | #undef DEBUG | ||
28 | |||
29 | #ifdef DEBUG | ||
30 | #define DBG(arg) printk arg | ||
31 | #else | ||
32 | #define DBG(fmt,...) | ||
33 | #endif | ||
34 | /* | 27 | /* |
35 | * SL82C105 PCI config register 0x40 bits. | 28 | * SL82C105 PCI config register 0x40 bits. |
36 | */ | 29 | */ |
@@ -104,9 +97,6 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) | |||
104 | unsigned long timings = (unsigned long)ide_get_drivedata(drive); | 97 | unsigned long timings = (unsigned long)ide_get_drivedata(drive); |
105 | u16 drv_ctrl; | 98 | u16 drv_ctrl; |
106 | 99 | ||
107 | DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", | ||
108 | drive->name, ide_xfer_verbose(speed))); | ||
109 | |||
110 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; | 100 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; |
111 | 101 | ||
112 | /* | 102 | /* |
@@ -196,8 +186,6 @@ static void sl82c105_dma_start(ide_drive_t *drive) | |||
196 | struct pci_dev *dev = to_pci_dev(hwif->dev); | 186 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
197 | int reg = 0x44 + drive->dn * 4; | 187 | int reg = 0x44 + drive->dn * 4; |
198 | 188 | ||
199 | DBG(("%s(drive:%s)\n", __func__, drive->name)); | ||
200 | |||
201 | pci_write_config_word(dev, reg, | 189 | pci_write_config_word(dev, reg, |
202 | (unsigned long)ide_get_drivedata(drive) >> 16); | 190 | (unsigned long)ide_get_drivedata(drive) >> 16); |
203 | 191 | ||
@@ -209,8 +197,6 @@ static void sl82c105_dma_clear(ide_drive_t *drive) | |||
209 | { | 197 | { |
210 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); | 198 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
211 | 199 | ||
212 | DBG(("sl82c105_dma_clear(drive:%s)\n", drive->name)); | ||
213 | |||
214 | sl82c105_reset_host(dev); | 200 | sl82c105_reset_host(dev); |
215 | } | 201 | } |
216 | 202 | ||
@@ -218,11 +204,7 @@ static int sl82c105_dma_end(ide_drive_t *drive) | |||
218 | { | 204 | { |
219 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); | 205 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
220 | int reg = 0x44 + drive->dn * 4; | 206 | int reg = 0x44 + drive->dn * 4; |
221 | int ret; | 207 | int ret = ide_dma_end(drive); |
222 | |||
223 | DBG(("%s(drive:%s)\n", __func__, drive->name)); | ||
224 | |||
225 | ret = ide_dma_end(drive); | ||
226 | 208 | ||
227 | pci_write_config_word(dev, reg, | 209 | pci_write_config_word(dev, reg, |
228 | (unsigned long)ide_get_drivedata(drive)); | 210 | (unsigned long)ide_get_drivedata(drive)); |
@@ -239,8 +221,6 @@ static void sl82c105_resetproc(ide_drive_t *drive) | |||
239 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); | 221 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
240 | u32 val; | 222 | u32 val; |
241 | 223 | ||
242 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); | ||
243 | |||
244 | pci_read_config_dword(dev, 0x40, &val); | 224 | pci_read_config_dword(dev, 0x40, &val); |
245 | val |= (CTRL_P1F16 | CTRL_P0F16); | 225 | val |= (CTRL_P1F16 | CTRL_P0F16); |
246 | pci_write_config_dword(dev, 0x40, val); | 226 | pci_write_config_dword(dev, 0x40, val); |
@@ -291,8 +271,6 @@ static int init_chipset_sl82c105(struct pci_dev *dev) | |||
291 | { | 271 | { |
292 | u32 val; | 272 | u32 val; |
293 | 273 | ||
294 | DBG(("init_chipset_sl82c105()\n")); | ||
295 | |||
296 | pci_read_config_dword(dev, 0x40, &val); | 274 | pci_read_config_dword(dev, 0x40, &val); |
297 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | 275 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; |
298 | pci_write_config_dword(dev, 0x40, val); | 276 | pci_write_config_dword(dev, 0x40, val); |