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-rw-r--r--drivers/ide/Kconfig34
-rw-r--r--drivers/ide/Makefile2
-rw-r--r--drivers/ide/arm/bast-ide.c12
-rw-r--r--drivers/ide/arm/icside.c23
-rw-r--r--drivers/ide/arm/palm_bk3710.c13
-rw-r--r--drivers/ide/arm/rapide.c9
-rw-r--r--drivers/ide/cris/Makefile3
-rw-r--r--drivers/ide/cris/ide-cris.c1086
-rw-r--r--drivers/ide/h8300/ide-h8300.c114
-rw-r--r--drivers/ide/ide-acpi.c18
-rw-r--r--drivers/ide/ide-cd.c46
-rw-r--r--drivers/ide/ide-cd_verbose.c2
-rw-r--r--drivers/ide/ide-dma.c11
-rw-r--r--drivers/ide/ide-floppy.c37
-rw-r--r--drivers/ide/ide-io.c83
-rw-r--r--drivers/ide/ide-iops.c390
-rw-r--r--drivers/ide/ide-lib.c2
-rw-r--r--drivers/ide/ide-pnp.c5
-rw-r--r--drivers/ide/ide-probe.c75
-rw-r--r--drivers/ide/ide-proc.c15
-rw-r--r--drivers/ide/ide-tape.c1210
-rw-r--r--drivers/ide/ide-taskfile.c76
-rw-r--r--drivers/ide/ide.c364
-rw-r--r--drivers/ide/legacy/ali14xx.c6
-rw-r--r--drivers/ide/legacy/buddha.c14
-rw-r--r--drivers/ide/legacy/dtc2278.c5
-rw-r--r--drivers/ide/legacy/falconide.c32
-rw-r--r--drivers/ide/legacy/gayle.c18
-rw-r--r--drivers/ide/legacy/ht6560b.c11
-rw-r--r--drivers/ide/legacy/ide-4drives.c2
-rw-r--r--drivers/ide/legacy/ide-cs.c12
-rw-r--r--drivers/ide/legacy/ide_platform.c14
-rw-r--r--drivers/ide/legacy/macide.c4
-rw-r--r--drivers/ide/legacy/q40ide.c71
-rw-r--r--drivers/ide/legacy/qd65xx.c33
-rw-r--r--drivers/ide/legacy/umc8672.c4
-rw-r--r--drivers/ide/mips/au1xxx-ide.c32
-rw-r--r--drivers/ide/mips/swarm.c7
-rw-r--r--drivers/ide/pci/aec62xx.c2
-rw-r--r--drivers/ide/pci/alim15x3.c242
-rw-r--r--drivers/ide/pci/amd74xx.c2
-rw-r--r--drivers/ide/pci/cmd640.c89
-rw-r--r--drivers/ide/pci/cmd64x.c6
-rw-r--r--drivers/ide/pci/cy82c693.c4
-rw-r--r--drivers/ide/pci/delkin_cb.c9
-rw-r--r--drivers/ide/pci/hpt366.c2
-rw-r--r--drivers/ide/pci/ns87415.c56
-rw-r--r--drivers/ide/pci/opti621.c7
-rw-r--r--drivers/ide/pci/pdc202xx_new.c8
-rw-r--r--drivers/ide/pci/piix.c1
-rw-r--r--drivers/ide/pci/scc_pata.c207
-rw-r--r--drivers/ide/pci/sgiioc4.c28
-rw-r--r--drivers/ide/pci/siimage.c564
-rw-r--r--drivers/ide/pci/trm290.c2
-rw-r--r--drivers/ide/pci/via82cxxx.c2
-rw-r--r--drivers/ide/ppc/mpc8xx.c28
-rw-r--r--drivers/ide/ppc/pmac.c8
57 files changed, 1625 insertions, 3537 deletions
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 3f9e10001e19..f702f9152ce6 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -862,40 +862,6 @@ config BLK_DEV_IDE_BAST
862 Say Y here if you want to support the onboard IDE channels on the 862 Say Y here if you want to support the onboard IDE channels on the
863 Simtec BAST or the Thorcom VR1000 863 Simtec BAST or the Thorcom VR1000
864 864
865config ETRAX_IDE
866 tristate "ETRAX IDE support"
867 depends on CRIS && BROKEN
868 select BLK_DEV_IDEDMA
869 help
870 Enables the ETRAX IDE driver.
871
872 You can't use parallel ports or SCSI ports at the same time.
873
874config ETRAX_IDE_DELAY
875 int "Delay for drives to regain consciousness"
876 depends on ETRAX_IDE && ETRAX_ARCH_V10
877 default 15
878 help
879 Number of seconds to wait for IDE drives to spin up after an IDE
880 reset.
881
882choice
883 prompt "IDE reset pin"
884 depends on ETRAX_IDE && ETRAX_ARCH_V10
885 default ETRAX_IDE_PB7_RESET
886
887config ETRAX_IDE_PB7_RESET
888 bool "Port_PB_Bit_7"
889 help
890 IDE reset on pin 7 on port B
891
892config ETRAX_IDE_G27_RESET
893 bool "Port_G_Bit_27"
894 help
895 IDE reset on pin 27 on port G
896
897endchoice
898
899config IDE_H8300 865config IDE_H8300
900 tristate "H8300 IDE support" 866 tristate "H8300 IDE support"
901 depends on H8300 867 depends on H8300
diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile
index 571544c37bb2..f94b679b611e 100644
--- a/drivers/ide/Makefile
+++ b/drivers/ide/Makefile
@@ -35,7 +35,7 @@ ifeq ($(CONFIG_BLK_DEV_CMD640), y)
35 obj-y += cmd640-core.o 35 obj-y += cmd640-core.o
36endif 36endif
37 37
38obj-$(CONFIG_BLK_DEV_IDE) += cris/ ppc/ 38obj-$(CONFIG_BLK_DEV_IDE) += ppc/
39obj-$(CONFIG_IDE_H8300) += h8300/ 39obj-$(CONFIG_IDE_H8300) += h8300/
40obj-$(CONFIG_IDE_GENERIC) += ide-generic.o 40obj-$(CONFIG_IDE_GENERIC) += ide-generic.o
41obj-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o 41obj-$(CONFIG_BLK_DEV_IDEPNP) += ide-pnp.o
diff --git a/drivers/ide/arm/bast-ide.c b/drivers/ide/arm/bast-ide.c
index d158f579bde2..713cef20622e 100644
--- a/drivers/ide/arm/bast-ide.c
+++ b/drivers/ide/arm/bast-ide.c
@@ -35,12 +35,12 @@ static int __init bastide_register(unsigned int base, unsigned int aux, int irq)
35 base += BAST_IDE_CS; 35 base += BAST_IDE_CS;
36 aux += BAST_IDE_CS; 36 aux += BAST_IDE_CS;
37 37
38 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 38 for (i = 0; i <= 7; i++) {
39 hw.io_ports[i] = (unsigned long)base; 39 hw.io_ports_array[i] = (unsigned long)base;
40 base += 0x20; 40 base += 0x20;
41 } 41 }
42 42
43 hw.io_ports[IDE_CONTROL_OFFSET] = aux + (6 * 0x20); 43 hw.io_ports.ctl_addr = aux + (6 * 0x20);
44 hw.irq = irq; 44 hw.irq = irq;
45 45
46 hwif = ide_find_port(); 46 hwif = ide_find_port();
@@ -49,11 +49,7 @@ static int __init bastide_register(unsigned int base, unsigned int aux, int irq)
49 49
50 i = hwif->index; 50 i = hwif->index;
51 51
52 if (hwif->present) 52 ide_init_port_data(hwif, i);
53 ide_unregister(i);
54 else
55 ide_init_port_data(hwif, i);
56
57 ide_init_port_hw(hwif, &hw); 53 ide_init_port_hw(hwif, &hw);
58 hwif->port_ops = NULL; 54 hwif->port_ops = NULL;
59 55
diff --git a/drivers/ide/arm/icside.c b/drivers/ide/arm/icside.c
index 7d642f44e35b..061456914ca3 100644
--- a/drivers/ide/arm/icside.c
+++ b/drivers/ide/arm/icside.c
@@ -419,18 +419,21 @@ icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *e
419 419
420 hwif = ide_find_port(); 420 hwif = ide_find_port();
421 if (hwif) { 421 if (hwif) {
422 int i;
423
424 /* 422 /*
425 * Ensure we're using MMIO 423 * Ensure we're using MMIO
426 */ 424 */
427 default_hwif_mmiops(hwif); 425 default_hwif_mmiops(hwif);
428 426
429 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 427 hwif->io_ports.data_addr = port;
430 hwif->io_ports[i] = port; 428 hwif->io_ports.error_addr = port + (1 << info->stepping);
431 port += 1 << info->stepping; 429 hwif->io_ports.nsect_addr = port + (2 << info->stepping);
432 } 430 hwif->io_ports.lbal_addr = port + (3 << info->stepping);
433 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset; 431 hwif->io_ports.lbam_addr = port + (4 << info->stepping);
432 hwif->io_ports.lbah_addr = port + (5 << info->stepping);
433 hwif->io_ports.device_addr = port + (6 << info->stepping);
434 hwif->io_ports.status_addr = port + (7 << info->stepping);
435 hwif->io_ports.ctl_addr =
436 (unsigned long)base + info->ctrloffset;
434 hwif->irq = ec->irq; 437 hwif->irq = ec->irq;
435 hwif->chipset = ide_acorn; 438 hwif->chipset = ide_acorn;
436 hwif->gendev.parent = &ec->dev; 439 hwif->gendev.parent = &ec->dev;
@@ -480,8 +483,7 @@ static const struct ide_port_info icside_v6_port_info __initdata = {
480 .init_dma = icside_dma_off_init, 483 .init_dma = icside_dma_off_init,
481 .port_ops = &icside_v6_no_dma_port_ops, 484 .port_ops = &icside_v6_no_dma_port_ops,
482 .dma_ops = &icside_v6_dma_ops, 485 .dma_ops = &icside_v6_dma_ops,
483 .host_flags = IDE_HFLAG_SERIALIZE | 486 .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
484 IDE_HFLAG_NO_AUTOTUNE,
485 .mwdma_mask = ATA_MWDMA2, 487 .mwdma_mask = ATA_MWDMA2,
486 .swdma_mask = ATA_SWDMA2, 488 .swdma_mask = ATA_SWDMA2,
487}; 489};
@@ -547,14 +549,13 @@ icside_register_v6(struct icside_state *state, struct expansion_card *ec)
547 hwif->config_data = (unsigned long)ioc_base; 549 hwif->config_data = (unsigned long)ioc_base;
548 hwif->select_data = sel; 550 hwif->select_data = sel;
549 551
550 mate->maskproc = icside_maskproc;
551 mate->hwif_data = state; 552 mate->hwif_data = state;
552 mate->config_data = (unsigned long)ioc_base; 553 mate->config_data = (unsigned long)ioc_base;
553 mate->select_data = sel | 1; 554 mate->select_data = sel | 1;
554 555
555 if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) { 556 if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
556 d.init_dma = icside_dma_init; 557 d.init_dma = icside_dma_init;
557 d.port_ops = &icside_v6_dma_port_ops; 558 d.port_ops = &icside_v6_port_ops;
558 d.dma_ops = NULL; 559 d.dma_ops = NULL;
559 } 560 }
560 561
diff --git a/drivers/ide/arm/palm_bk3710.c b/drivers/ide/arm/palm_bk3710.c
index 8fa34e26443a..96378ebfb31f 100644
--- a/drivers/ide/arm/palm_bk3710.c
+++ b/drivers/ide/arm/palm_bk3710.c
@@ -321,7 +321,7 @@ static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif,
321 const struct ide_port_info *d) 321 const struct ide_port_info *d)
322{ 322{
323 unsigned long base = 323 unsigned long base =
324 hwif->io_ports[IDE_DATA_OFFSET] - IDE_PALM_ATA_PRI_REG_OFFSET; 324 hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
325 325
326 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); 326 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
327 327
@@ -342,6 +342,7 @@ static const struct ide_port_ops palm_bk3710_ports_ops = {
342static const struct ide_port_info __devinitdata palm_bk3710_port_info = { 342static const struct ide_port_info __devinitdata palm_bk3710_port_info = {
343 .init_dma = palm_bk3710_init_dma, 343 .init_dma = palm_bk3710_init_dma,
344 .port_ops = &palm_bk3710_ports_ops, 344 .port_ops = &palm_bk3710_ports_ops,
345 .host_flags = IDE_HFLAG_MMIO,
345 .pio_mask = ATA_PIO4, 346 .pio_mask = ATA_PIO4,
346 .udma_mask = ATA_UDMA4, /* (input clk 99MHz) */ 347 .udma_mask = ATA_UDMA4, /* (input clk 99MHz) */
347 .mwdma_mask = ATA_MWDMA2, 348 .mwdma_mask = ATA_MWDMA2,
@@ -386,8 +387,8 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev)
386 387
387 pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET; 388 pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET;
388 for (i = 0; i < IDE_NR_PORTS - 2; i++) 389 for (i = 0; i < IDE_NR_PORTS - 2; i++)
389 hw.io_ports[i] = pribase + i; 390 hw.io_ports_array[i] = pribase + i;
390 hw.io_ports[IDE_CONTROL_OFFSET] = mem->start + 391 hw.io_ports.ctl_addr = mem->start +
391 IDE_PALM_ATA_PRI_CTL_OFFSET; 392 IDE_PALM_ATA_PRI_CTL_OFFSET;
392 hw.irq = irq->start; 393 hw.irq = irq->start;
393 hw.chipset = ide_palm3710; 394 hw.chipset = ide_palm3710;
@@ -398,11 +399,7 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev)
398 399
399 i = hwif->index; 400 i = hwif->index;
400 401
401 if (hwif->present) 402 ide_init_port_data(hwif, i);
402 ide_unregister(i);
403 else
404 ide_init_port_data(hwif, i);
405
406 ide_init_port_hw(hwif, &hw); 403 ide_init_port_hw(hwif, &hw);
407 404
408 hwif->mmio = 1; 405 hwif->mmio = 1;
diff --git a/drivers/ide/arm/rapide.c b/drivers/ide/arm/rapide.c
index c0581bd98d0d..1747b2358775 100644
--- a/drivers/ide/arm/rapide.c
+++ b/drivers/ide/arm/rapide.c
@@ -17,11 +17,11 @@ static void rapide_setup_ports(hw_regs_t *hw, void __iomem *base,
17 unsigned long port = (unsigned long)base; 17 unsigned long port = (unsigned long)base;
18 int i; 18 int i;
19 19
20 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { 20 for (i = 0; i <= 7; i++) {
21 hw->io_ports[i] = port; 21 hw->io_ports_array[i] = port;
22 port += sz; 22 port += sz;
23 } 23 }
24 hw->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)ctrl; 24 hw->io_ports.ctl_addr = (unsigned long)ctrl;
25 hw->irq = irq; 25 hw->irq = irq;
26} 26}
27 27
@@ -53,6 +53,7 @@ rapide_probe(struct expansion_card *ec, const struct ecard_id *id)
53 53
54 ide_init_port_hw(hwif, &hw); 54 ide_init_port_hw(hwif, &hw);
55 55
56 hwif->host_flags = IDE_HFLAG_MMIO;
56 default_hwif_mmiops(hwif); 57 default_hwif_mmiops(hwif);
57 58
58 idx[0] = hwif->index; 59 idx[0] = hwif->index;
@@ -75,7 +76,7 @@ static void __devexit rapide_remove(struct expansion_card *ec)
75 76
76 ecard_set_drvdata(ec, NULL); 77 ecard_set_drvdata(ec, NULL);
77 78
78 ide_unregister(hwif->index); 79 ide_unregister(hwif);
79 80
80 ecard_release_resources(ec); 81 ecard_release_resources(ec);
81} 82}
diff --git a/drivers/ide/cris/Makefile b/drivers/ide/cris/Makefile
deleted file mode 100644
index 20b95960531f..000000000000
--- a/drivers/ide/cris/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
1EXTRA_CFLAGS += -Idrivers/ide
2
3obj-$(CONFIG_IDE_ETRAX) += ide-cris.o
diff --git a/drivers/ide/cris/ide-cris.c b/drivers/ide/cris/ide-cris.c
deleted file mode 100644
index a62ca75c7e28..000000000000
--- a/drivers/ide/cris/ide-cris.c
+++ /dev/null
@@ -1,1086 +0,0 @@
1/*
2 * Etrax specific IDE functions, like init and PIO-mode setting etc.
3 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
4 * Copyright (c) 2000-2005 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (initial version)
7 * Mikael Starvik (crisv32 port)
8 */
9
10/* Regarding DMA:
11 *
12 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
13 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
14 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
15 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
16 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
17 */
18
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/timer.h>
22#include <linux/mm.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/blkdev.h>
26#include <linux/hdreg.h>
27#include <linux/ide.h>
28#include <linux/init.h>
29
30#include <asm/io.h>
31#include <asm/dma.h>
32
33/* number of DMA descriptors */
34#define MAX_DMA_DESCRS 64
35
36/* number of times to retry busy-flags when reading/writing IDE-registers
37 * this can't be too high because a hung harddisk might cause the watchdog
38 * to trigger (sometimes INB and OUTB are called with irq's disabled)
39 */
40
41#define IDE_REGISTER_TIMEOUT 300
42
43#define LOWDB(x)
44#define D(x)
45
46enum /* Transfer types */
47{
48 TYPE_PIO,
49 TYPE_DMA,
50 TYPE_UDMA
51};
52
53/* CRISv32 specifics */
54#ifdef CONFIG_ETRAX_ARCH_V32
55#include <asm/arch/hwregs/ata_defs.h>
56#include <asm/arch/hwregs/dma_defs.h>
57#include <asm/arch/hwregs/dma.h>
58#include <asm/arch/pinmux.h>
59
60#define ATA_UDMA2_CYC 2
61#define ATA_UDMA2_DVS 3
62#define ATA_UDMA1_CYC 2
63#define ATA_UDMA1_DVS 4
64#define ATA_UDMA0_CYC 4
65#define ATA_UDMA0_DVS 6
66#define ATA_DMA2_STROBE 7
67#define ATA_DMA2_HOLD 1
68#define ATA_DMA1_STROBE 8
69#define ATA_DMA1_HOLD 3
70#define ATA_DMA0_STROBE 25
71#define ATA_DMA0_HOLD 19
72#define ATA_PIO4_SETUP 3
73#define ATA_PIO4_STROBE 7
74#define ATA_PIO4_HOLD 1
75#define ATA_PIO3_SETUP 3
76#define ATA_PIO3_STROBE 9
77#define ATA_PIO3_HOLD 3
78#define ATA_PIO2_SETUP 3
79#define ATA_PIO2_STROBE 13
80#define ATA_PIO2_HOLD 5
81#define ATA_PIO1_SETUP 5
82#define ATA_PIO1_STROBE 23
83#define ATA_PIO1_HOLD 9
84#define ATA_PIO0_SETUP 9
85#define ATA_PIO0_STROBE 39
86#define ATA_PIO0_HOLD 9
87
88int
89cris_ide_ack_intr(ide_hwif_t* hwif)
90{
91 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
92 int, hwif->io_ports[0]);
93 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
94 return 1;
95}
96
97static inline int
98cris_ide_busy(void)
99{
100 reg_ata_rs_stat_data stat_data;
101 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
102 return stat_data.busy;
103}
104
105static inline int
106cris_ide_ready(void)
107{
108 return !cris_ide_busy();
109}
110
111static inline int
112cris_ide_data_available(unsigned short* data)
113{
114 reg_ata_rs_stat_data stat_data;
115 stat_data = REG_RD(ata, regi_ata, rs_stat_data);
116 *data = stat_data.data;
117 return stat_data.dav;
118}
119
120static void
121cris_ide_write_command(unsigned long command)
122{
123 REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
124}
125
126static void
127cris_ide_set_speed(int type, int setup, int strobe, int hold)
128{
129 reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
130 reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
131
132 if (type == TYPE_PIO) {
133 ctrl0.pio_setup = setup;
134 ctrl0.pio_strb = strobe;
135 ctrl0.pio_hold = hold;
136 } else if (type == TYPE_DMA) {
137 ctrl0.dma_strb = strobe;
138 ctrl0.dma_hold = hold;
139 } else if (type == TYPE_UDMA) {
140 ctrl1.udma_tcyc = setup;
141 ctrl1.udma_tdvs = strobe;
142 }
143 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
144 REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
145}
146
147static unsigned long
148cris_ide_base_address(int bus)
149{
150 reg_ata_rw_ctrl2 ctrl2 = {0};
151 ctrl2.sel = bus;
152 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
153}
154
155static unsigned long
156cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
157{
158 reg_ata_rw_ctrl2 ctrl2 = {0};
159 ctrl2.addr = addr;
160 ctrl2.cs1 = cs1;
161 ctrl2.cs0 = cs0;
162 return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
163}
164
165static __init void
166cris_ide_reset(unsigned val)
167{
168 reg_ata_rw_ctrl0 ctrl0 = {0};
169 ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
170 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
171}
172
173static __init void
174cris_ide_init(void)
175{
176 reg_ata_rw_ctrl0 ctrl0 = {0};
177 reg_ata_rw_intr_mask intr_mask = {0};
178
179 ctrl0.en = regk_ata_yes;
180 REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
181
182 intr_mask.bus0 = regk_ata_yes;
183 intr_mask.bus1 = regk_ata_yes;
184 intr_mask.bus2 = regk_ata_yes;
185 intr_mask.bus3 = regk_ata_yes;
186
187 REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
188
189 crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
190 crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
191
192 crisv32_pinmux_alloc_fixed(pinmux_ata);
193 crisv32_pinmux_alloc_fixed(pinmux_ata0);
194 crisv32_pinmux_alloc_fixed(pinmux_ata1);
195 crisv32_pinmux_alloc_fixed(pinmux_ata2);
196 crisv32_pinmux_alloc_fixed(pinmux_ata3);
197
198 DMA_RESET(regi_dma2);
199 DMA_ENABLE(regi_dma2);
200 DMA_RESET(regi_dma3);
201 DMA_ENABLE(regi_dma3);
202
203 DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
204 DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
205}
206
207static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
208
209#define cris_dma_descr_type dma_descr_data
210#define cris_pio_read regk_ata_rd
211#define cris_ultra_mask 0x7
212#define MAX_DESCR_SIZE 0xffffffffUL
213
214static unsigned long
215cris_ide_get_reg(unsigned long reg)
216{
217 return (reg & 0x0e000000) >> 25;
218}
219
220static void
221cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
222{
223 d->buf = (char*)virt_to_phys(buf);
224 d->after = d->buf + len;
225 d->eol = last;
226}
227
228static void
229cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
230{
231 ide_hwif_t *hwif = drive->hwif;
232
233 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
234 hwif->io_ports[IDE_DATA_OFFSET]);
235 reg_ata_rw_trf_cnt trf_cnt = {0};
236
237 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
238 mycontext.saved_data_buf = d->buf;
239 /* start the dma channel */
240 DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
241
242 /* initiate a multi word dma read using PIO handshaking */
243 trf_cnt.cnt = len >> 1;
244 /* Due to a "feature" the transfer count has to be one extra word for UDMA. */
245 if (type == TYPE_UDMA)
246 trf_cnt.cnt++;
247 REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
248
249 ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
250 ctrl2.trf_mode = regk_ata_dma;
251 ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
252 type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
253 ctrl2.multi = regk_ata_yes;
254 ctrl2.dma_size = regk_ata_word;
255 REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
256}
257
258static void
259cris_ide_wait_dma(int dir)
260{
261 reg_dma_rw_stat status;
262 do
263 {
264 status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
265 } while(status.list_state != regk_dma_data_at_eol);
266}
267
268static int cris_dma_test_irq(ide_drive_t *drive)
269{
270 ide_hwif_t *hwif = drive->hwif;
271 int intr = REG_RD_INT(ata, regi_ata, r_intr);
272
273 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
274 hwif->io_ports[IDE_DATA_OFFSET]);
275
276 return intr & (1 << ctrl2.sel) ? 1 : 0;
277}
278
279static void cris_ide_initialize_dma(int dir)
280{
281}
282
283#else
284/* CRISv10 specifics */
285#include <asm/arch/svinto.h>
286#include <asm/arch/io_interface_mux.h>
287
288/* PIO timing (in R_ATA_CONFIG)
289 *
290 * _____________________________
291 * ADDRESS : ________/
292 *
293 * _______________
294 * DIOR : ____________/ \__________
295 *
296 * _______________
297 * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
298 *
299 *
300 * DIOR is unbuffered while address and data is buffered.
301 * This creates two problems:
302 * 1. The DIOR pulse is to early (because it is unbuffered)
303 * 2. The rise time of DIOR is long
304 *
305 * There are at least three different plausible solutions
306 * 1. Use a pad capable of larger currents in Etrax
307 * 2. Use an external buffer
308 * 3. Make the strobe pulse longer
309 *
310 * Some of the strobe timings below are modified to compensate
311 * for this. This implies a slight performance decrease.
312 *
313 * THIS SHOULD NEVER BE CHANGED!
314 *
315 * TODO: Is this true for the latest LX boards still ?
316 */
317
318#define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */
319#define ATA_UDMA2_DVS 0
320#define ATA_UDMA1_CYC 0
321#define ATA_UDMA1_DVS 0
322#define ATA_UDMA0_CYC 0
323#define ATA_UDMA0_DVS 0
324#define ATA_DMA2_STROBE 4
325#define ATA_DMA2_HOLD 0
326#define ATA_DMA1_STROBE 4
327#define ATA_DMA1_HOLD 1
328#define ATA_DMA0_STROBE 12
329#define ATA_DMA0_HOLD 9
330#define ATA_PIO4_SETUP 1
331#define ATA_PIO4_STROBE 5
332#define ATA_PIO4_HOLD 0
333#define ATA_PIO3_SETUP 1
334#define ATA_PIO3_STROBE 5
335#define ATA_PIO3_HOLD 1
336#define ATA_PIO2_SETUP 1
337#define ATA_PIO2_STROBE 6
338#define ATA_PIO2_HOLD 2
339#define ATA_PIO1_SETUP 2
340#define ATA_PIO1_STROBE 11
341#define ATA_PIO1_HOLD 4
342#define ATA_PIO0_SETUP 4
343#define ATA_PIO0_STROBE 19
344#define ATA_PIO0_HOLD 4
345
346int
347cris_ide_ack_intr(ide_hwif_t* hwif)
348{
349 return 1;
350}
351
352static inline int
353cris_ide_busy(void)
354{
355 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
356}
357
358static inline int
359cris_ide_ready(void)
360{
361 return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
362}
363
364static inline int
365cris_ide_data_available(unsigned short* data)
366{
367 unsigned long status = *R_ATA_STATUS_DATA;
368 *data = (unsigned short)status;
369 return status & IO_MASK(R_ATA_STATUS_DATA, dav);
370}
371
372static void
373cris_ide_write_command(unsigned long command)
374{
375 *R_ATA_CTRL_DATA = command;
376}
377
378static void
379cris_ide_set_speed(int type, int setup, int strobe, int hold)
380{
381 static int pio_setup = ATA_PIO4_SETUP;
382 static int pio_strobe = ATA_PIO4_STROBE;
383 static int pio_hold = ATA_PIO4_HOLD;
384 static int dma_strobe = ATA_DMA2_STROBE;
385 static int dma_hold = ATA_DMA2_HOLD;
386
387 if (type == TYPE_PIO) {
388 pio_setup = setup;
389 pio_strobe = strobe;
390 pio_hold = hold;
391 } else if (type == TYPE_DMA) {
392 dma_strobe = strobe;
393 dma_hold = hold;
394 }
395 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
396 IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
397 IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) |
398 IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) |
399 IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
400 IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) );
401}
402
403static unsigned long
404cris_ide_base_address(int bus)
405{
406 return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
407}
408
409static unsigned long
410cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
411{
412 return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
413 IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
414 IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
415}
416
417static __init void
418cris_ide_reset(unsigned val)
419{
420#ifdef CONFIG_ETRAX_IDE_G27_RESET
421 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
422#endif
423#ifdef CONFIG_ETRAX_IDE_PB7_RESET
424 port_pb_dir_shadow = port_pb_dir_shadow |
425 IO_STATE(R_PORT_PB_DIR, dir7, output);
426 *R_PORT_PB_DIR = port_pb_dir_shadow;
427 REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
428#endif
429}
430
431static __init void
432cris_ide_init(void)
433{
434 volatile unsigned int dummy;
435
436 *R_ATA_CTRL_DATA = 0;
437 *R_ATA_TRANSFER_CNT = 0;
438 *R_ATA_CONFIG = 0;
439
440 if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
441 printk(KERN_CRIT "ide: Failed to get IO interface\n");
442 return;
443 } else if (cris_request_dma(ATA_TX_DMA_NBR,
444 "ETRAX100LX IDE TX",
445 DMA_VERBOSE_ON_ERROR,
446 dma_ata)) {
447 cris_free_io_interface(if_ata);
448 printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
449 return;
450 } else if (cris_request_dma(ATA_RX_DMA_NBR,
451 "ETRAX100LX IDE RX",
452 DMA_VERBOSE_ON_ERROR,
453 dma_ata)) {
454 cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
455 cris_free_io_interface(if_ata);
456 printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
457 return;
458 }
459
460 /* make a dummy read to set the ata controller in a proper state */
461 dummy = *R_ATA_STATUS_DATA;
462
463 *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
464 *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
465 IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
466
467 while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
468
469 *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
470 IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
471 IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
472 IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
473
474 /* reset the dma channels we will use */
475
476 RESET_DMA(ATA_TX_DMA_NBR);
477 RESET_DMA(ATA_RX_DMA_NBR);
478 WAIT_DMA(ATA_TX_DMA_NBR);
479 WAIT_DMA(ATA_RX_DMA_NBR);
480}
481
482#define cris_dma_descr_type etrax_dma_descr
483#define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
484#define cris_ultra_mask 0x0
485#define MAX_DESCR_SIZE 0x10000UL
486
487static unsigned long
488cris_ide_get_reg(unsigned long reg)
489{
490 return (reg & 0x0e000000) >> 25;
491}
492
493static void
494cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
495{
496 d->buf = virt_to_phys(buf);
497 d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
498 if (last)
499 d->ctrl |= d_eol;
500}
501
502static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
503{
504 unsigned long cmd;
505
506 if (dir) {
507 /* need to do this before RX DMA due to a chip bug
508 * it is enough to just flush the part of the cache that
509 * corresponds to the buffers we start, but since HD transfers
510 * usually are more than 8 kB, it is easier to optimize for the
511 * normal case and just flush the entire cache. its the only
512 * way to be sure! (OB movie quote)
513 */
514 flush_etrax_cache();
515 *R_DMA_CH3_FIRST = virt_to_phys(d);
516 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
517
518 } else {
519 *R_DMA_CH2_FIRST = virt_to_phys(d);
520 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
521 }
522
523 /* initiate a multi word dma read using DMA handshaking */
524
525 *R_ATA_TRANSFER_CNT =
526 IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
527
528 cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
529 cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
530 IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
531 *R_ATA_CTRL_DATA =
532 cmd |
533 IO_FIELD(R_ATA_CTRL_DATA, data,
534 drive->hwif->io_ports[IDE_DATA_OFFSET]) |
535 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
536 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
537 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
538}
539
540static void
541cris_ide_wait_dma(int dir)
542{
543 if (dir)
544 WAIT_DMA(ATA_RX_DMA_NBR);
545 else
546 WAIT_DMA(ATA_TX_DMA_NBR);
547}
548
549static int cris_dma_test_irq(ide_drive_t *drive)
550{
551 int intr = *R_IRQ_MASK0_RD;
552 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel,
553 drive->hwif->io_ports[IDE_DATA_OFFSET]);
554
555 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
556}
557
558
559static void cris_ide_initialize_dma(int dir)
560{
561 if (dir)
562 {
563 RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
564 WAIT_DMA(ATA_RX_DMA_NBR);
565 }
566 else
567 {
568 RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
569 WAIT_DMA(ATA_TX_DMA_NBR);
570 }
571}
572
573#endif
574
575void
576cris_ide_outw(unsigned short data, unsigned long reg) {
577 int timeleft;
578
579 LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
580
581 /* note the lack of handling any timeouts. we stop waiting, but we don't
582 * really notify anybody.
583 */
584
585 timeleft = IDE_REGISTER_TIMEOUT;
586 /* wait for busy flag */
587 do {
588 timeleft--;
589 } while(timeleft && cris_ide_busy());
590
591 /*
592 * Fall through at a timeout, so the ongoing command will be
593 * aborted by the write below, which is expected to be a dummy
594 * command to the command register. This happens when a faulty
595 * drive times out on a command. See comment on timeout in
596 * INB.
597 */
598 if(!timeleft)
599 printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
600
601 cris_ide_write_command(reg|data); /* write data to the drive's register */
602
603 timeleft = IDE_REGISTER_TIMEOUT;
604 /* wait for transmitter ready */
605 do {
606 timeleft--;
607 } while(timeleft && !cris_ide_ready());
608}
609
610void
611cris_ide_outb(unsigned char data, unsigned long reg)
612{
613 cris_ide_outw(data, reg);
614}
615
616void
617cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
618{
619 cris_ide_outw(addr, port);
620}
621
622unsigned short
623cris_ide_inw(unsigned long reg) {
624 int timeleft;
625 unsigned short val;
626
627 timeleft = IDE_REGISTER_TIMEOUT;
628 /* wait for busy flag */
629 do {
630 timeleft--;
631 } while(timeleft && cris_ide_busy());
632
633 if(!timeleft) {
634 /*
635 * If we're asked to read the status register, like for
636 * example when a command does not complete for an
637 * extended time, but the ATA interface is stuck in a
638 * busy state at the *ETRAX* ATA interface level (as has
639 * happened repeatedly with at least one bad disk), then
640 * the best thing to do is to pretend that we read
641 * "busy" in the status register, so the IDE driver will
642 * time-out, abort the ongoing command and perform a
643 * reset sequence. Note that the subsequent OUT_BYTE
644 * call will also timeout on busy, but as long as the
645 * write is still performed, everything will be fine.
646 */
647 if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET)
648 return BUSY_STAT;
649 else
650 /* For other rare cases we assume 0 is good enough. */
651 return 0;
652 }
653
654 cris_ide_write_command(reg | cris_pio_read);
655
656 timeleft = IDE_REGISTER_TIMEOUT;
657 /* wait for available */
658 do {
659 timeleft--;
660 } while(timeleft && !cris_ide_data_available(&val));
661
662 if(!timeleft)
663 return 0;
664
665 LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
666
667 return val;
668}
669
670unsigned char
671cris_ide_inb(unsigned long reg)
672{
673 return (unsigned char)cris_ide_inw(reg);
674}
675
676static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int);
677static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int);
678static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
679static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
680
681static void cris_dma_host_set(ide_drive_t *drive, int on)
682{
683}
684
685static void cris_set_pio_mode(ide_drive_t *drive, const u8 pio)
686{
687 int setup, strobe, hold;
688
689 switch(pio)
690 {
691 case 0:
692 setup = ATA_PIO0_SETUP;
693 strobe = ATA_PIO0_STROBE;
694 hold = ATA_PIO0_HOLD;
695 break;
696 case 1:
697 setup = ATA_PIO1_SETUP;
698 strobe = ATA_PIO1_STROBE;
699 hold = ATA_PIO1_HOLD;
700 break;
701 case 2:
702 setup = ATA_PIO2_SETUP;
703 strobe = ATA_PIO2_STROBE;
704 hold = ATA_PIO2_HOLD;
705 break;
706 case 3:
707 setup = ATA_PIO3_SETUP;
708 strobe = ATA_PIO3_STROBE;
709 hold = ATA_PIO3_HOLD;
710 break;
711 case 4:
712 setup = ATA_PIO4_SETUP;
713 strobe = ATA_PIO4_STROBE;
714 hold = ATA_PIO4_HOLD;
715 break;
716 default:
717 return;
718 }
719
720 cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
721}
722
723static void cris_set_dma_mode(ide_drive_t *drive, const u8 speed)
724{
725 int cyc = 0, dvs = 0, strobe = 0, hold = 0;
726
727 switch(speed)
728 {
729 case XFER_UDMA_0:
730 cyc = ATA_UDMA0_CYC;
731 dvs = ATA_UDMA0_DVS;
732 break;
733 case XFER_UDMA_1:
734 cyc = ATA_UDMA1_CYC;
735 dvs = ATA_UDMA1_DVS;
736 break;
737 case XFER_UDMA_2:
738 cyc = ATA_UDMA2_CYC;
739 dvs = ATA_UDMA2_DVS;
740 break;
741 case XFER_MW_DMA_0:
742 strobe = ATA_DMA0_STROBE;
743 hold = ATA_DMA0_HOLD;
744 break;
745 case XFER_MW_DMA_1:
746 strobe = ATA_DMA1_STROBE;
747 hold = ATA_DMA1_HOLD;
748 break;
749 case XFER_MW_DMA_2:
750 strobe = ATA_DMA2_STROBE;
751 hold = ATA_DMA2_HOLD;
752 break;
753 }
754
755 if (speed >= XFER_UDMA_0)
756 cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
757 else
758 cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
759}
760
761static void __init cris_setup_ports(hw_regs_t *hw, unsigned long base)
762{
763 int i;
764
765 memset(hw, 0, sizeof(*hw));
766
767 for (i = 0; i <= 7; i++)
768 hw->io_ports[i] = base + cris_ide_reg_addr(i, 0, 1);
769
770 /*
771 * the IDE control register is at ATA address 6,
772 * with CS1 active instead of CS0
773 */
774 hw->io_ports[IDE_CONTROL_OFFSET] = base + cris_ide_reg_addr(6, 1, 0);
775
776 hw->irq = ide_default_irq(0);
777 hw->ack_intr = cris_ide_ack_intr;
778}
779
780static const struct ide_port_ops cris_port_ops = {
781 .set_pio_mode = cris_set_pio_mode,
782 .set_dma_mode = cris_set_dma_mode,
783};
784
785static const struct ide_dma_ops cris_dma_ops;
786
787static const struct ide_port_info cris_port_info __initdata = {
788 .chipset = ide_etrax100,
789 .port_ops = &cris_port_ops,
790 .dma_ops = &cris_dma_ops,
791 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
792 IDE_HFLAG_NO_DMA, /* no SFF-style DMA */
793 .pio_mask = ATA_PIO4,
794 .udma_mask = cris_ultra_mask,
795 .mwdma_mask = ATA_MWDMA2,
796};
797
798static int __init init_e100_ide(void)
799{
800 hw_regs_t hw;
801 int h;
802 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
803
804 printk("ide: ETRAX FS built-in ATA DMA controller\n");
805
806 for (h = 0; h < 4; h++) {
807 ide_hwif_t *hwif = NULL;
808
809 cris_setup_ports(&hw, cris_ide_base_address(h));
810
811 hwif = ide_find_port();
812 if (hwif == NULL)
813 continue;
814 ide_init_port_data(hwif, hwif->index);
815 ide_init_port_hw(hwif, &hw);
816
817 hwif->ata_input_data = &cris_ide_input_data;
818 hwif->ata_output_data = &cris_ide_output_data;
819 hwif->atapi_input_bytes = &cris_atapi_input_bytes;
820 hwif->atapi_output_bytes = &cris_atapi_output_bytes;
821 hwif->OUTB = &cris_ide_outb;
822 hwif->OUTW = &cris_ide_outw;
823 hwif->OUTBSYNC = &cris_ide_outbsync;
824 hwif->INB = &cris_ide_inb;
825 hwif->INW = &cris_ide_inw;
826 hwif->cbl = ATA_CBL_PATA40;
827
828 idx[h] = hwif->index;
829 }
830
831 /* Reset pulse */
832 cris_ide_reset(0);
833 udelay(25);
834 cris_ide_reset(1);
835
836 cris_ide_init();
837
838 cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
839 cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
840 cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
841
842 ide_device_add(idx, &cris_port_info);
843
844 return 0;
845}
846
847static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
848
849/*
850 * The following routines are mainly used by the ATAPI drivers.
851 *
852 * These routines will round up any request for an odd number of bytes,
853 * so if an odd bytecount is specified, be sure that there's at least one
854 * extra byte allocated for the buffer.
855 */
856static void
857cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
858{
859 D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
860 buffer, bytecount));
861
862 if(bytecount & 1) {
863 printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
864 bytecount++; /* to round off */
865 }
866
867 /* setup DMA and start transfer */
868
869 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
870 cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
871
872 /* wait for completion */
873 LED_DISK_READ(1);
874 cris_ide_wait_dma(1);
875 LED_DISK_READ(0);
876}
877
878static void
879cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
880{
881 D(printk("atapi_output_bytes, buffer 0x%x, count %d\n",
882 buffer, bytecount));
883
884 if(bytecount & 1) {
885 printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
886 bytecount++;
887 }
888
889 cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
890 cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
891
892 /* wait for completion */
893
894 LED_DISK_WRITE(1);
895 LED_DISK_READ(1);
896 cris_ide_wait_dma(0);
897 LED_DISK_WRITE(0);
898}
899
900/*
901 * This is used for most PIO data transfers *from* the IDE interface
902 */
903static void
904cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
905{
906 cris_atapi_input_bytes(drive, buffer, wcount << 2);
907}
908
909/*
910 * This is used for most PIO data transfers *to* the IDE interface
911 */
912static void
913cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
914{
915 cris_atapi_output_bytes(drive, buffer, wcount << 2);
916}
917
918/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
919static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
920static unsigned int ata_tot_size;
921
922/*
923 * cris_ide_build_dmatable() prepares a dma request.
924 * Returns 0 if all went okay, returns 1 otherwise.
925 */
926static int cris_ide_build_dmatable (ide_drive_t *drive)
927{
928 ide_hwif_t *hwif = drive->hwif;
929 struct scatterlist* sg;
930 struct request *rq = drive->hwif->hwgroup->rq;
931 unsigned long size, addr;
932 unsigned int count = 0;
933 int i = 0;
934
935 sg = hwif->sg_table;
936
937 ata_tot_size = 0;
938
939 ide_map_sg(drive, rq);
940 i = hwif->sg_nents;
941
942 while(i) {
943 /*
944 * Determine addr and size of next buffer area. We assume that
945 * individual virtual buffers are always composed linearly in
946 * physical memory. For example, we assume that any 8kB buffer
947 * is always composed of two adjacent physical 4kB pages rather
948 * than two possibly non-adjacent physical 4kB pages.
949 */
950 /* group sequential buffers into one large buffer */
951 addr = sg_phys(sg);
952 size = sg_dma_len(sg);
953 while (--i) {
954 sg = sg_next(sg);
955 if ((addr + size) != sg_phys(sg))
956 break;
957 size += sg_dma_len(sg);
958 }
959
960 /* did we run out of descriptors? */
961
962 if(count >= MAX_DMA_DESCRS) {
963 printk("%s: too few DMA descriptors\n", drive->name);
964 return 1;
965 }
966
967 /* however, this case is more difficult - rw_trf_cnt cannot be more
968 than 65536 words per transfer, so in that case we need to either
969 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
970 the descriptors, or
971 2) simply do the request here, and get dma_intr to only ide_end_request on
972 those blocks that were actually set-up for transfer.
973 */
974
975 if(ata_tot_size + size > 131072) {
976 printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
977 return 1;
978 }
979
980 /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
981 don't handle size > 131072 only one split is necessary */
982
983 if(size > MAX_DESCR_SIZE) {
984 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
985 count++;
986 ata_tot_size += MAX_DESCR_SIZE;
987 size -= MAX_DESCR_SIZE;
988 addr += MAX_DESCR_SIZE;
989 }
990
991 cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
992 count++;
993 ata_tot_size += size;
994 }
995
996 if (count) {
997 /* return and say all is ok */
998 return 0;
999 }
1000
1001 printk("%s: empty DMA table?\n", drive->name);
1002 return 1; /* let the PIO routines handle this weirdness */
1003}
1004
1005/*
1006 * cris_dma_intr() is the handler for disk read/write DMA interrupts
1007 */
1008static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
1009{
1010 LED_DISK_READ(0);
1011 LED_DISK_WRITE(0);
1012
1013 return ide_dma_intr(drive);
1014}
1015
1016/*
1017 * Functions below initiates/aborts DMA read/write operations on a drive.
1018 *
1019 * The caller is assumed to have selected the drive and programmed the drive's
1020 * sector address using CHS or LBA. All that remains is to prepare for DMA
1021 * and then issue the actual read/write DMA/PIO command to the drive.
1022 *
1023 * For ATAPI devices, we just prepare for DMA and return. The caller should
1024 * then issue the packet command to the drive and call us again with
1025 * cris_dma_start afterwards.
1026 *
1027 * Returns 0 if all went well.
1028 * Returns 1 if DMA read/write could not be started, in which case
1029 * the caller should revert to PIO for the current request.
1030 */
1031
1032static int cris_dma_end(ide_drive_t *drive)
1033{
1034 drive->waiting_for_dma = 0;
1035 return 0;
1036}
1037
1038static int cris_dma_setup(ide_drive_t *drive)
1039{
1040 struct request *rq = drive->hwif->hwgroup->rq;
1041
1042 cris_ide_initialize_dma(!rq_data_dir(rq));
1043 if (cris_ide_build_dmatable (drive)) {
1044 ide_map_sg(drive, rq);
1045 return 1;
1046 }
1047
1048 drive->waiting_for_dma = 1;
1049 return 0;
1050}
1051
1052static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
1053{
1054 ide_execute_command(drive, command, &cris_dma_intr, WAIT_CMD, NULL);
1055}
1056
1057static void cris_dma_start(ide_drive_t *drive)
1058{
1059 struct request *rq = drive->hwif->hwgroup->rq;
1060 int writing = rq_data_dir(rq);
1061 int type = TYPE_DMA;
1062
1063 if (drive->current_speed >= XFER_UDMA_0)
1064 type = TYPE_UDMA;
1065
1066 cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
1067
1068 if (writing) {
1069 LED_DISK_WRITE(1);
1070 } else {
1071 LED_DISK_READ(1);
1072 }
1073}
1074
1075static const struct ide_dma_ops cris_dma_ops = {
1076 .dma_host_set = cris_dma_host_set,
1077 .dma_setup = cris_dma_setup,
1078 .dma_exec_cmd = cris_dma_exec_cmd,
1079 .dma_start = cris_dma_start,
1080 .dma_end = cris_dma_end,
1081 .dma_test_irq = cris_dma_test_irq,
1082};
1083
1084module_init(init_e100_ide);
1085
1086MODULE_LICENSE("GPL");
diff --git a/drivers/ide/h8300/ide-h8300.c b/drivers/ide/h8300/ide-h8300.c
index 0708b29cdb17..ecf53bb0d2aa 100644
--- a/drivers/ide/h8300/ide-h8300.c
+++ b/drivers/ide/h8300/ide-h8300.c
@@ -42,6 +42,91 @@ static u16 mm_inw(unsigned long a)
42 return r; 42 return r;
43} 43}
44 44
45static void h8300_tf_load(ide_drive_t *drive, ide_task_t *task)
46{
47 ide_hwif_t *hwif = drive->hwif;
48 struct ide_io_ports *io_ports = &hwif->io_ports;
49 struct ide_taskfile *tf = &task->tf;
50 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
51
52 if (task->tf_flags & IDE_TFLAG_FLAGGED)
53 HIHI = 0xFF;
54
55 ide_set_irq(drive, 1);
56
57 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
58 mm_outw((tf->hob_data << 8) | tf->data, io_ports->data_addr);
59
60 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
61 outb(tf->hob_feature, io_ports->feature_addr);
62 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
63 outb(tf->hob_nsect, io_ports->nsect_addr);
64 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
65 outb(tf->hob_lbal, io_ports->lbal_addr);
66 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
67 outb(tf->hob_lbam, io_ports->lbam_addr);
68 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
69 outb(tf->hob_lbah, io_ports->lbah_addr);
70
71 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
72 outb(tf->feature, io_ports->feature_addr);
73 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
74 outb(tf->nsect, io_ports->nsect_addr);
75 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
76 outb(tf->lbal, io_ports->lbal_addr);
77 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
78 outb(tf->lbam, io_ports->lbam_addr);
79 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
80 outb(tf->lbah, io_ports->lbah_addr);
81
82 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
83 outb((tf->device & HIHI) | drive->select.all,
84 io_ports->device_addr);
85}
86
87static void h8300_tf_read(ide_drive_t *drive, ide_task_t *task)
88{
89 ide_hwif_t *hwif = drive->hwif;
90 struct ide_io_ports *io_ports = &hwif->io_ports;
91 struct ide_taskfile *tf = &task->tf;
92
93 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
94 u16 data = mm_inw(io_ports->data_addr);
95
96 tf->data = data & 0xff;
97 tf->hob_data = (data >> 8) & 0xff;
98 }
99
100 /* be sure we're looking at the low order bits */
101 outb(drive->ctl & ~0x80, io_ports->ctl_addr);
102
103 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
104 tf->nsect = inb(io_ports->nsect_addr);
105 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
106 tf->lbal = inb(io_ports->lbal_addr);
107 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
108 tf->lbam = inb(io_ports->lbam_addr);
109 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
110 tf->lbah = inb(io_ports->lbah_addr);
111 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
112 tf->device = inb(io_ports->device_addr);
113
114 if (task->tf_flags & IDE_TFLAG_LBA48) {
115 outb(drive->ctl | 0x80, io_ports->ctl_addr);
116
117 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
118 tf->hob_feature = inb(io_ports->feature_addr);
119 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
120 tf->hob_nsect = inb(io_ports->nsect_addr);
121 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
122 tf->hob_lbal = inb(io_ports->lbal_addr);
123 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
124 tf->hob_lbam = inb(io_ports->lbam_addr);
125 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
126 tf->hob_lbah = inb(io_ports->lbah_addr);
127 }
128}
129
45static void mm_outsw(unsigned long addr, void *buf, u32 len) 130static void mm_outsw(unsigned long addr, void *buf, u32 len)
46{ 131{
47 unsigned short *bp = (unsigned short *)buf; 132 unsigned short *bp = (unsigned short *)buf;
@@ -56,6 +141,18 @@ static void mm_insw(unsigned long addr, void *buf, u32 len)
56 *bp = bswap(*(volatile u16 *)addr); 141 *bp = bswap(*(volatile u16 *)addr);
57} 142}
58 143
144static void h8300_input_data(ide_drive_t *drive, struct request *rq,
145 void *buf, unsigned int len)
146{
147 mm_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
148}
149
150static void h8300_output_data(ide_drive_t *drive, struct request *rq,
151 void *buf, unsigned int len)
152{
153 mm_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
154}
155
59#define H8300_IDE_GAP (2) 156#define H8300_IDE_GAP (2)
60 157
61static inline void hw_setup(hw_regs_t *hw) 158static inline void hw_setup(hw_regs_t *hw)
@@ -63,9 +160,9 @@ static inline void hw_setup(hw_regs_t *hw)
63 int i; 160 int i;
64 161
65 memset(hw, 0, sizeof(hw_regs_t)); 162 memset(hw, 0, sizeof(hw_regs_t));
66 for (i = 0; i <= IDE_STATUS_OFFSET; i++) 163 for (i = 0; i <= 7; i++)
67 hw->io_ports[i] = CONFIG_H8300_IDE_BASE + H8300_IDE_GAP*i; 164 hw->io_ports_array[i] = CONFIG_H8300_IDE_BASE + H8300_IDE_GAP*i;
68 hw->io_ports[IDE_CONTROL_OFFSET] = CONFIG_H8300_IDE_ALT; 165 hw->io_ports.ctl_addr = CONFIG_H8300_IDE_ALT;
69 hw->irq = EXT_IRQ0 + CONFIG_H8300_IDE_IRQ; 166 hw->irq = EXT_IRQ0 + CONFIG_H8300_IDE_IRQ;
70 hw->chipset = ide_generic; 167 hw->chipset = ide_generic;
71} 168}
@@ -74,12 +171,11 @@ static inline void hwif_setup(ide_hwif_t *hwif)
74{ 171{
75 default_hwif_iops(hwif); 172 default_hwif_iops(hwif);
76 173
77 hwif->OUTW = mm_outw; 174 hwif->tf_load = h8300_tf_load;
78 hwif->OUTSW = mm_outsw; 175 hwif->tf_read = h8300_tf_read;
79 hwif->INW = mm_inw; 176
80 hwif->INSW = mm_insw; 177 hwif->input_data = h8300_input_data;
81 hwif->OUTSL = NULL; 178 hwif->output_data = h8300_output_data;
82 hwif->INSL = NULL;
83} 179}
84 180
85static int __init h8300_ide_init(void) 181static int __init h8300_ide_init(void)
diff --git a/drivers/ide/ide-acpi.c b/drivers/ide/ide-acpi.c
index e4ad26e4fce7..9d3601fa5680 100644
--- a/drivers/ide/ide-acpi.c
+++ b/drivers/ide/ide-acpi.c
@@ -60,9 +60,17 @@ struct ide_acpi_hwif_link {
60#define DEBPRINT(fmt, args...) do {} while (0) 60#define DEBPRINT(fmt, args...) do {} while (0)
61#endif /* DEBUGGING */ 61#endif /* DEBUGGING */
62 62
63extern int ide_noacpi; 63int ide_noacpi;
64extern int ide_noacpitfs; 64module_param_named(noacpi, ide_noacpi, bool, 0);
65extern int ide_noacpionboot; 65MODULE_PARM_DESC(noacpi, "disable IDE ACPI support");
66
67int ide_acpigtf;
68module_param_named(acpigtf, ide_acpigtf, bool, 0);
69MODULE_PARM_DESC(acpigtf, "enable IDE ACPI _GTF support");
70
71int ide_acpionboot;
72module_param_named(acpionboot, ide_acpionboot, bool, 0);
73MODULE_PARM_DESC(acpionboot, "call IDE ACPI methods on boot");
66 74
67static bool ide_noacpi_psx; 75static bool ide_noacpi_psx;
68static int no_acpi_psx(const struct dmi_system_id *id) 76static int no_acpi_psx(const struct dmi_system_id *id)
@@ -376,7 +384,7 @@ static int taskfile_load_raw(ide_drive_t *drive,
376 memcpy(&args.tf_array[7], &gtf->tfa, 7); 384 memcpy(&args.tf_array[7], &gtf->tfa, 7);
377 args.tf_flags = IDE_TFLAG_TF | IDE_TFLAG_DEVICE; 385 args.tf_flags = IDE_TFLAG_TF | IDE_TFLAG_DEVICE;
378 386
379 if (ide_noacpitfs) { 387 if (!ide_acpigtf) {
380 DEBPRINT("_GTF execution disabled\n"); 388 DEBPRINT("_GTF execution disabled\n");
381 return err; 389 return err;
382 } 390 }
@@ -721,7 +729,7 @@ void ide_acpi_port_init_devices(ide_hwif_t *hwif)
721 drive->name, err); 729 drive->name, err);
722 } 730 }
723 731
724 if (ide_noacpionboot) { 732 if (!ide_acpionboot) {
725 DEBPRINT("ACPI methods disabled on boot\n"); 733 DEBPRINT("ACPI methods disabled on boot\n");
726 return; 734 return;
727 } 735 }
diff --git a/drivers/ide/ide-cd.c b/drivers/ide/ide-cd.c
index ad984322da94..68e7f19dc036 100644
--- a/drivers/ide/ide-cd.c
+++ b/drivers/ide/ide-cd.c
@@ -142,7 +142,6 @@ static void cdrom_analyze_sense_data(ide_drive_t *drive,
142{ 142{
143 unsigned long sector; 143 unsigned long sector;
144 unsigned long bio_sectors; 144 unsigned long bio_sectors;
145 unsigned long valid;
146 struct cdrom_info *info = drive->driver_data; 145 struct cdrom_info *info = drive->driver_data;
147 146
148 if (!cdrom_log_sense(drive, failed_command, sense)) 147 if (!cdrom_log_sense(drive, failed_command, sense))
@@ -173,17 +172,13 @@ static void cdrom_analyze_sense_data(ide_drive_t *drive,
173 (sense->information[2] << 8) | 172 (sense->information[2] << 8) |
174 (sense->information[3]); 173 (sense->information[3]);
175 174
176 bio_sectors = bio_sectors(failed_command->bio);
177 if (bio_sectors < 4)
178 bio_sectors = 4;
179 if (drive->queue->hardsect_size == 2048) 175 if (drive->queue->hardsect_size == 2048)
180 /* device sector size is 2K */ 176 /* device sector size is 2K */
181 sector <<= 2; 177 sector <<= 2;
178
179 bio_sectors = max(bio_sectors(failed_command->bio), 4U);
182 sector &= ~(bio_sectors - 1); 180 sector &= ~(bio_sectors - 1);
183 valid = (sector - failed_command->sector) << 9;
184 181
185 if (valid < 0)
186 valid = 0;
187 if (sector < get_capacity(info->disk) && 182 if (sector < get_capacity(info->disk) &&
188 drive->probed_capacity - sector < 4 * 75) 183 drive->probed_capacity - sector < 4 * 75)
189 set_capacity(info->disk, sector); 184 set_capacity(info->disk, sector);
@@ -555,14 +550,7 @@ static ide_startstop_t cdrom_start_packet_command(ide_drive_t *drive,
555 ATAPI_WAIT_PC, cdrom_timer_expiry); 550 ATAPI_WAIT_PC, cdrom_timer_expiry);
556 return ide_started; 551 return ide_started;
557 } else { 552 } else {
558 unsigned long flags; 553 ide_execute_pkt_cmd(drive);
559
560 /* packet command */
561 spin_lock_irqsave(&ide_lock, flags);
562 hwif->OUTBSYNC(drive, WIN_PACKETCMD,
563 hwif->io_ports[IDE_COMMAND_OFFSET]);
564 ndelay(400);
565 spin_unlock_irqrestore(&ide_lock, flags);
566 554
567 return (*handler) (drive); 555 return (*handler) (drive);
568 } 556 }
@@ -613,7 +601,7 @@ static ide_startstop_t cdrom_transfer_packet_command(ide_drive_t *drive,
613 cmd_len = ATAPI_MIN_CDB_BYTES; 601 cmd_len = ATAPI_MIN_CDB_BYTES;
614 602
615 /* send the command to the device */ 603 /* send the command to the device */
616 HWIF(drive)->atapi_output_bytes(drive, rq->cmd, cmd_len); 604 hwif->output_data(drive, NULL, rq->cmd, cmd_len);
617 605
618 /* start the DMA if need be */ 606 /* start the DMA if need be */
619 if (info->dma) 607 if (info->dma)
@@ -629,7 +617,7 @@ static void ide_cd_pad_transfer(ide_drive_t *drive, xfer_func_t *xf, int len)
629{ 617{
630 while (len > 0) { 618 while (len > 0) {
631 int dum = 0; 619 int dum = 0;
632 xf(drive, &dum, sizeof(dum)); 620 xf(drive, NULL, &dum, sizeof(dum));
633 len -= sizeof(dum); 621 len -= sizeof(dum);
634 } 622 }
635} 623}
@@ -639,7 +627,7 @@ static void ide_cd_drain_data(ide_drive_t *drive, int nsects)
639 while (nsects > 0) { 627 while (nsects > 0) {
640 static char dum[SECTOR_SIZE]; 628 static char dum[SECTOR_SIZE];
641 629
642 drive->hwif->atapi_input_bytes(drive, dum, sizeof(dum)); 630 drive->hwif->input_data(drive, NULL, dum, sizeof(dum));
643 nsects--; 631 nsects--;
644 } 632 }
645} 633}
@@ -666,7 +654,7 @@ static int ide_cd_check_ireason(ide_drive_t *drive, struct request *rq,
666 printk(KERN_ERR "%s: %s: wrong transfer direction!\n", 654 printk(KERN_ERR "%s: %s: wrong transfer direction!\n",
667 drive->name, __func__); 655 drive->name, __func__);
668 656
669 xf = rw ? hwif->atapi_output_bytes : hwif->atapi_input_bytes; 657 xf = rw ? hwif->output_data : hwif->input_data;
670 ide_cd_pad_transfer(drive, xf, len); 658 ide_cd_pad_transfer(drive, xf, len);
671 } else if (rw == 0 && ireason == 1) { 659 } else if (rw == 0 && ireason == 1) {
672 /* 660 /*
@@ -794,7 +782,7 @@ static ide_startstop_t cdrom_start_seek_continuation(ide_drive_t *drive)
794 782
795 sector_div(frame, queue_hardsect_size(drive->queue) >> SECTOR_BITS); 783 sector_div(frame, queue_hardsect_size(drive->queue) >> SECTOR_BITS);
796 784
797 memset(rq->cmd, 0, sizeof(rq->cmd)); 785 memset(rq->cmd, 0, BLK_MAX_CDB);
798 rq->cmd[0] = GPCMD_SEEK; 786 rq->cmd[0] = GPCMD_SEEK;
799 put_unaligned(cpu_to_be32(frame), (unsigned int *) &rq->cmd[2]); 787 put_unaligned(cpu_to_be32(frame), (unsigned int *) &rq->cmd[2]);
800 788
@@ -952,9 +940,9 @@ static ide_startstop_t cdrom_newpc_intr(ide_drive_t *drive)
952 } 940 }
953 941
954 /* ok we fall to pio :/ */ 942 /* ok we fall to pio :/ */
955 ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]) & 0x3; 943 ireason = hwif->INB(hwif->io_ports.nsect_addr) & 0x3;
956 lowcyl = hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]); 944 lowcyl = hwif->INB(hwif->io_ports.lbam_addr);
957 highcyl = hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]); 945 highcyl = hwif->INB(hwif->io_ports.lbah_addr);
958 946
959 len = lowcyl + (256 * highcyl); 947 len = lowcyl + (256 * highcyl);
960 948
@@ -1019,10 +1007,10 @@ static ide_startstop_t cdrom_newpc_intr(ide_drive_t *drive)
1019 1007
1020 if (ireason == 0) { 1008 if (ireason == 0) {
1021 write = 1; 1009 write = 1;
1022 xferfunc = HWIF(drive)->atapi_output_bytes; 1010 xferfunc = hwif->output_data;
1023 } else { 1011 } else {
1024 write = 0; 1012 write = 0;
1025 xferfunc = HWIF(drive)->atapi_input_bytes; 1013 xferfunc = hwif->input_data;
1026 } 1014 }
1027 1015
1028 /* transfer data */ 1016 /* transfer data */
@@ -1061,7 +1049,7 @@ static ide_startstop_t cdrom_newpc_intr(ide_drive_t *drive)
1061 if (blen > thislen) 1049 if (blen > thislen)
1062 blen = thislen; 1050 blen = thislen;
1063 1051
1064 xferfunc(drive, ptr, blen); 1052 xferfunc(drive, NULL, ptr, blen);
1065 1053
1066 thislen -= blen; 1054 thislen -= blen;
1067 len -= blen; 1055 len -= blen;
@@ -1706,7 +1694,7 @@ static int ide_cdrom_prep_fs(struct request_queue *q, struct request *rq)
1706 long block = (long)rq->hard_sector / (hard_sect >> 9); 1694 long block = (long)rq->hard_sector / (hard_sect >> 9);
1707 unsigned long blocks = rq->hard_nr_sectors / (hard_sect >> 9); 1695 unsigned long blocks = rq->hard_nr_sectors / (hard_sect >> 9);
1708 1696
1709 memset(rq->cmd, 0, sizeof(rq->cmd)); 1697 memset(rq->cmd, 0, BLK_MAX_CDB);
1710 1698
1711 if (rq_data_dir(rq) == READ) 1699 if (rq_data_dir(rq) == READ)
1712 rq->cmd[0] = GPCMD_READ_10; 1700 rq->cmd[0] = GPCMD_READ_10;
@@ -1909,9 +1897,7 @@ static int ide_cdrom_setup(ide_drive_t *drive)
1909 /* set correct block size */ 1897 /* set correct block size */
1910 blk_queue_hardsect_size(drive->queue, CD_FRAMESIZE); 1898 blk_queue_hardsect_size(drive->queue, CD_FRAMESIZE);
1911 1899
1912 if (drive->autotune == IDE_TUNE_DEFAULT || 1900 drive->dsc_overlap = (drive->next != drive);
1913 drive->autotune == IDE_TUNE_AUTO)
1914 drive->dsc_overlap = (drive->next != drive);
1915 1901
1916 if (ide_cdrom_register(drive, nslots)) { 1902 if (ide_cdrom_register(drive, nslots)) {
1917 printk(KERN_ERR "%s: %s failed to register device with the" 1903 printk(KERN_ERR "%s: %s failed to register device with the"
diff --git a/drivers/ide/ide-cd_verbose.c b/drivers/ide/ide-cd_verbose.c
index 6ed7ca071331..6490a2dea96b 100644
--- a/drivers/ide/ide-cd_verbose.c
+++ b/drivers/ide/ide-cd_verbose.c
@@ -326,7 +326,7 @@ void ide_cd_log_error(const char *name, struct request *failed_command,
326 326
327 printk(KERN_ERR " The failed \"%s\" packet command " 327 printk(KERN_ERR " The failed \"%s\" packet command "
328 "was: \n \"", s); 328 "was: \n \"", s);
329 for (i = 0; i < sizeof(failed_command->cmd); i++) 329 for (i = 0; i < BLK_MAX_CDB; i++)
330 printk(KERN_CONT "%02x ", failed_command->cmd[i]); 330 printk(KERN_CONT "%02x ", failed_command->cmd[i]);
331 printk(KERN_CONT "\"\n"); 331 printk(KERN_CONT "\"\n");
332 } 332 }
diff --git a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c
index c352cf27b6e7..653b1ade13d3 100644
--- a/drivers/ide/ide-dma.c
+++ b/drivers/ide/ide-dma.c
@@ -464,9 +464,10 @@ int ide_dma_setup(ide_drive_t *drive)
464 464
465 /* PRD table */ 465 /* PRD table */
466 if (hwif->mmio) 466 if (hwif->mmio)
467 writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable); 467 writel(hwif->dmatable_dma,
468 (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
468 else 469 else
469 outl(hwif->dmatable_dma, hwif->dma_prdtable); 470 outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
470 471
471 /* specify r/w */ 472 /* specify r/w */
472 hwif->OUTB(reading, hwif->dma_command); 473 hwif->OUTB(reading, hwif->dma_command);
@@ -858,14 +859,8 @@ void ide_setup_dma(ide_hwif_t *hwif, unsigned long base)
858 859
859 if (!hwif->dma_command) 860 if (!hwif->dma_command)
860 hwif->dma_command = hwif->dma_base + 0; 861 hwif->dma_command = hwif->dma_base + 0;
861 if (!hwif->dma_vendor1)
862 hwif->dma_vendor1 = hwif->dma_base + 1;
863 if (!hwif->dma_status) 862 if (!hwif->dma_status)
864 hwif->dma_status = hwif->dma_base + 2; 863 hwif->dma_status = hwif->dma_base + 2;
865 if (!hwif->dma_vendor3)
866 hwif->dma_vendor3 = hwif->dma_base + 3;
867 if (!hwif->dma_prdtable)
868 hwif->dma_prdtable = hwif->dma_base + 4;
869 864
870 hwif->dma_ops = &sff_dma_ops; 865 hwif->dma_ops = &sff_dma_ops;
871} 866}
diff --git a/drivers/ide/ide-floppy.c b/drivers/ide/ide-floppy.c
index 6e891bccd052..f05fbc2bd7a8 100644
--- a/drivers/ide/ide-floppy.c
+++ b/drivers/ide/ide-floppy.c
@@ -231,6 +231,7 @@ static int idefloppy_end_request(ide_drive_t *drive, int uptodate, int nsecs)
231static void ide_floppy_io_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc, 231static void ide_floppy_io_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
232 unsigned int bcount, int direction) 232 unsigned int bcount, int direction)
233{ 233{
234 ide_hwif_t *hwif = drive->hwif;
234 struct request *rq = pc->rq; 235 struct request *rq = pc->rq;
235 struct req_iterator iter; 236 struct req_iterator iter;
236 struct bio_vec *bvec; 237 struct bio_vec *bvec;
@@ -246,9 +247,9 @@ static void ide_floppy_io_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
246 247
247 data = bvec_kmap_irq(bvec, &flags); 248 data = bvec_kmap_irq(bvec, &flags);
248 if (direction) 249 if (direction)
249 drive->hwif->atapi_output_bytes(drive, data, count); 250 hwif->output_data(drive, NULL, data, count);
250 else 251 else
251 drive->hwif->atapi_input_bytes(drive, data, count); 252 hwif->input_data(drive, NULL, data, count);
252 bvec_kunmap_irq(data, &flags); 253 bvec_kunmap_irq(data, &flags);
253 254
254 bcount -= count; 255 bcount -= count;
@@ -261,10 +262,7 @@ static void ide_floppy_io_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
261 if (bcount) { 262 if (bcount) {
262 printk(KERN_ERR "%s: leftover data in %s, bcount == %d\n", 263 printk(KERN_ERR "%s: leftover data in %s, bcount == %d\n",
263 drive->name, __func__, bcount); 264 drive->name, __func__, bcount);
264 if (direction) 265 ide_pad_transfer(drive, direction, bcount);
265 ide_atapi_write_zeros(drive, bcount);
266 else
267 ide_atapi_discard_data(drive, bcount);
268 } 266 }
269} 267}
270 268
@@ -465,10 +463,10 @@ static ide_startstop_t idefloppy_pc_intr(ide_drive_t *drive)
465 } 463 }
466 464
467 /* Get the number of bytes to transfer */ 465 /* Get the number of bytes to transfer */
468 bcount = (hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]) << 8) | 466 bcount = (hwif->INB(hwif->io_ports.lbah_addr) << 8) |
469 hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]); 467 hwif->INB(hwif->io_ports.lbam_addr);
470 /* on this interrupt */ 468 /* on this interrupt */
471 ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 469 ireason = hwif->INB(hwif->io_ports.nsect_addr);
472 470
473 if (ireason & CD) { 471 if (ireason & CD) {
474 printk(KERN_ERR "ide-floppy: CoD != 0 in %s\n", __func__); 472 printk(KERN_ERR "ide-floppy: CoD != 0 in %s\n", __func__);
@@ -490,7 +488,7 @@ static ide_startstop_t idefloppy_pc_intr(ide_drive_t *drive)
490 printk(KERN_ERR "ide-floppy: The floppy wants " 488 printk(KERN_ERR "ide-floppy: The floppy wants "
491 "to send us more data than expected " 489 "to send us more data than expected "
492 "- discarding data\n"); 490 "- discarding data\n");
493 ide_atapi_discard_data(drive, bcount); 491 ide_pad_transfer(drive, 0, bcount);
494 492
495 ide_set_handler(drive, 493 ide_set_handler(drive,
496 &idefloppy_pc_intr, 494 &idefloppy_pc_intr,
@@ -503,12 +501,12 @@ static ide_startstop_t idefloppy_pc_intr(ide_drive_t *drive)
503 } 501 }
504 } 502 }
505 if (pc->flags & PC_FLAG_WRITING) 503 if (pc->flags & PC_FLAG_WRITING)
506 xferfunc = hwif->atapi_output_bytes; 504 xferfunc = hwif->output_data;
507 else 505 else
508 xferfunc = hwif->atapi_input_bytes; 506 xferfunc = hwif->input_data;
509 507
510 if (pc->buf) 508 if (pc->buf)
511 xferfunc(drive, pc->cur_pos, bcount); 509 xferfunc(drive, NULL, pc->cur_pos, bcount);
512 else 510 else
513 ide_floppy_io_buffers(drive, pc, bcount, 511 ide_floppy_io_buffers(drive, pc, bcount,
514 !!(pc->flags & PC_FLAG_WRITING)); 512 !!(pc->flags & PC_FLAG_WRITING));
@@ -539,7 +537,7 @@ static ide_startstop_t idefloppy_transfer_pc(ide_drive_t *drive)
539 "initiated yet DRQ isn't asserted\n"); 537 "initiated yet DRQ isn't asserted\n");
540 return startstop; 538 return startstop;
541 } 539 }
542 ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 540 ireason = hwif->INB(hwif->io_ports.nsect_addr);
543 if ((ireason & CD) == 0 || (ireason & IO)) { 541 if ((ireason & CD) == 0 || (ireason & IO)) {
544 printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) while " 542 printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) while "
545 "issuing a packet command\n"); 543 "issuing a packet command\n");
@@ -548,8 +546,10 @@ static ide_startstop_t idefloppy_transfer_pc(ide_drive_t *drive)
548 546
549 /* Set the interrupt routine */ 547 /* Set the interrupt routine */
550 ide_set_handler(drive, &idefloppy_pc_intr, IDEFLOPPY_WAIT_CMD, NULL); 548 ide_set_handler(drive, &idefloppy_pc_intr, IDEFLOPPY_WAIT_CMD, NULL);
549
551 /* Send the actual packet */ 550 /* Send the actual packet */
552 HWIF(drive)->atapi_output_bytes(drive, floppy->pc->c, 12); 551 hwif->output_data(drive, NULL, floppy->pc->c, 12);
552
553 return ide_started; 553 return ide_started;
554} 554}
555 555
@@ -569,7 +569,8 @@ static int idefloppy_transfer_pc2(ide_drive_t *drive)
569 idefloppy_floppy_t *floppy = drive->driver_data; 569 idefloppy_floppy_t *floppy = drive->driver_data;
570 570
571 /* Send the actual packet */ 571 /* Send the actual packet */
572 HWIF(drive)->atapi_output_bytes(drive, floppy->pc->c, 12); 572 drive->hwif->output_data(drive, NULL, floppy->pc->c, 12);
573
573 /* Timeout for the packet command */ 574 /* Timeout for the packet command */
574 return IDEFLOPPY_WAIT_CMD; 575 return IDEFLOPPY_WAIT_CMD;
575} 576}
@@ -586,7 +587,7 @@ static ide_startstop_t idefloppy_transfer_pc1(ide_drive_t *drive)
586 "initiated yet DRQ isn't asserted\n"); 587 "initiated yet DRQ isn't asserted\n");
587 return startstop; 588 return startstop;
588 } 589 }
589 ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 590 ireason = hwif->INB(hwif->io_ports.nsect_addr);
590 if ((ireason & CD) == 0 || (ireason & IO)) { 591 if ((ireason & CD) == 0 || (ireason & IO)) {
591 printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) " 592 printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) "
592 "while issuing a packet command\n"); 593 "while issuing a packet command\n");
@@ -692,7 +693,7 @@ static ide_startstop_t idefloppy_issue_pc(ide_drive_t *drive,
692 return ide_started; 693 return ide_started;
693 } else { 694 } else {
694 /* Issue the packet command */ 695 /* Issue the packet command */
695 hwif->OUTB(WIN_PACKETCMD, hwif->io_ports[IDE_COMMAND_OFFSET]); 696 ide_execute_pkt_cmd(drive);
696 return (*pkt_xfer_routine) (drive); 697 return (*pkt_xfer_routine) (drive);
697 } 698 }
698} 699}
diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c
index 0fe89a599275..696525342e9a 100644
--- a/drivers/ide/ide-io.c
+++ b/drivers/ide/ide-io.c
@@ -295,54 +295,6 @@ static void ide_complete_pm_request (ide_drive_t *drive, struct request *rq)
295 spin_unlock_irqrestore(&ide_lock, flags); 295 spin_unlock_irqrestore(&ide_lock, flags);
296} 296}
297 297
298void ide_tf_read(ide_drive_t *drive, ide_task_t *task)
299{
300 ide_hwif_t *hwif = drive->hwif;
301 struct ide_taskfile *tf = &task->tf;
302
303 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
304 u16 data = hwif->INW(hwif->io_ports[IDE_DATA_OFFSET]);
305
306 tf->data = data & 0xff;
307 tf->hob_data = (data >> 8) & 0xff;
308 }
309
310 /* be sure we're looking at the low order bits */
311 hwif->OUTB(drive->ctl & ~0x80, hwif->io_ports[IDE_CONTROL_OFFSET]);
312
313 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
314 tf->nsect = hwif->INB(hwif->io_ports[IDE_NSECTOR_OFFSET]);
315 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
316 tf->lbal = hwif->INB(hwif->io_ports[IDE_SECTOR_OFFSET]);
317 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
318 tf->lbam = hwif->INB(hwif->io_ports[IDE_LCYL_OFFSET]);
319 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
320 tf->lbah = hwif->INB(hwif->io_ports[IDE_HCYL_OFFSET]);
321 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
322 tf->device = hwif->INB(hwif->io_ports[IDE_SELECT_OFFSET]);
323
324 if (task->tf_flags & IDE_TFLAG_LBA48) {
325 hwif->OUTB(drive->ctl | 0x80,
326 hwif->io_ports[IDE_CONTROL_OFFSET]);
327
328 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
329 tf->hob_feature =
330 hwif->INB(hwif->io_ports[IDE_FEATURE_OFFSET]);
331 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
332 tf->hob_nsect =
333 hwif->INB(hwif->io_ports[IDE_NSECTOR_OFFSET]);
334 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
335 tf->hob_lbal =
336 hwif->INB(hwif->io_ports[IDE_SECTOR_OFFSET]);
337 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
338 tf->hob_lbam =
339 hwif->INB(hwif->io_ports[IDE_LCYL_OFFSET]);
340 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
341 tf->hob_lbah =
342 hwif->INB(hwif->io_ports[IDE_HCYL_OFFSET]);
343 }
344}
345
346/** 298/**
347 * ide_end_drive_cmd - end an explicit drive command 299 * ide_end_drive_cmd - end an explicit drive command
348 * @drive: command 300 * @drive: command
@@ -378,7 +330,7 @@ void ide_end_drive_cmd (ide_drive_t *drive, u8 stat, u8 err)
378 tf->error = err; 330 tf->error = err;
379 tf->status = stat; 331 tf->status = stat;
380 332
381 ide_tf_read(drive, task); 333 drive->hwif->tf_read(drive, task);
382 334
383 if (task->tf_flags & IDE_TFLAG_DYN) 335 if (task->tf_flags & IDE_TFLAG_DYN)
384 kfree(task); 336 kfree(task);
@@ -427,7 +379,7 @@ static void try_to_flush_leftover_data (ide_drive_t *drive)
427 u32 wcount = (i > 16) ? 16 : i; 379 u32 wcount = (i > 16) ? 16 : i;
428 380
429 i -= wcount; 381 i -= wcount;
430 HWIF(drive)->ata_input_data(drive, buffer, wcount); 382 drive->hwif->input_data(drive, NULL, buffer, wcount * 4);
431 } 383 }
432} 384}
433 385
@@ -454,7 +406,7 @@ static ide_startstop_t ide_ata_error(ide_drive_t *drive, struct request *rq, u8
454 if (err == ABRT_ERR) { 406 if (err == ABRT_ERR) {
455 if (drive->select.b.lba && 407 if (drive->select.b.lba &&
456 /* some newer drives don't support WIN_SPECIFY */ 408 /* some newer drives don't support WIN_SPECIFY */
457 hwif->INB(hwif->io_ports[IDE_COMMAND_OFFSET]) == 409 hwif->INB(hwif->io_ports.command_addr) ==
458 WIN_SPECIFY) 410 WIN_SPECIFY)
459 return ide_stopped; 411 return ide_stopped;
460 } else if ((err & BAD_CRC) == BAD_CRC) { 412 } else if ((err & BAD_CRC) == BAD_CRC) {
@@ -507,8 +459,8 @@ static ide_startstop_t ide_atapi_error(ide_drive_t *drive, struct request *rq, u
507 459
508 if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT)) 460 if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT))
509 /* force an abort */ 461 /* force an abort */
510 hwif->OUTB(WIN_IDLEIMMEDIATE, 462 hwif->OUTBSYNC(drive, WIN_IDLEIMMEDIATE,
511 hwif->io_ports[IDE_COMMAND_OFFSET]); 463 hwif->io_ports.command_addr);
512 464
513 if (rq->errors >= ERROR_MAX) { 465 if (rq->errors >= ERROR_MAX) {
514 ide_kill_rq(drive, rq); 466 ide_kill_rq(drive, rq);
@@ -1421,7 +1373,7 @@ static void unexpected_intr (int irq, ide_hwgroup_t *hwgroup)
1421 */ 1373 */
1422 do { 1374 do {
1423 if (hwif->irq == irq) { 1375 if (hwif->irq == irq) {
1424 stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 1376 stat = hwif->INB(hwif->io_ports.status_addr);
1425 if (!OK_STAT(stat, READY_STAT, BAD_STAT)) { 1377 if (!OK_STAT(stat, READY_STAT, BAD_STAT)) {
1426 /* Try to not flood the console with msgs */ 1378 /* Try to not flood the console with msgs */
1427 static unsigned long last_msgtime, count; 1379 static unsigned long last_msgtime, count;
@@ -1511,7 +1463,7 @@ irqreturn_t ide_intr (int irq, void *dev_id)
1511 * Whack the status register, just in case 1463 * Whack the status register, just in case
1512 * we have a leftover pending IRQ. 1464 * we have a leftover pending IRQ.
1513 */ 1465 */
1514 (void) hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 1466 (void) hwif->INB(hwif->io_ports.status_addr);
1515#endif /* CONFIG_BLK_DEV_IDEPCI */ 1467#endif /* CONFIG_BLK_DEV_IDEPCI */
1516 } 1468 }
1517 spin_unlock_irqrestore(&ide_lock, flags); 1469 spin_unlock_irqrestore(&ide_lock, flags);
@@ -1598,8 +1550,7 @@ irqreturn_t ide_intr (int irq, void *dev_id)
1598 1550
1599void ide_init_drive_cmd (struct request *rq) 1551void ide_init_drive_cmd (struct request *rq)
1600{ 1552{
1601 memset(rq, 0, sizeof(*rq)); 1553 blk_rq_init(NULL, rq);
1602 rq->ref_count = 1;
1603} 1554}
1604 1555
1605EXPORT_SYMBOL(ide_init_drive_cmd); 1556EXPORT_SYMBOL(ide_init_drive_cmd);
@@ -1685,7 +1636,23 @@ void ide_pktcmd_tf_load(ide_drive_t *drive, u32 tf_flags, u16 bcount, u8 dma)
1685 task.tf.lbam = bcount & 0xff; 1636 task.tf.lbam = bcount & 0xff;
1686 task.tf.lbah = (bcount >> 8) & 0xff; 1637 task.tf.lbah = (bcount >> 8) & 0xff;
1687 1638
1688 ide_tf_load(drive, &task); 1639 ide_tf_dump(drive->name, &task.tf);
1640 drive->hwif->tf_load(drive, &task);
1689} 1641}
1690 1642
1691EXPORT_SYMBOL_GPL(ide_pktcmd_tf_load); 1643EXPORT_SYMBOL_GPL(ide_pktcmd_tf_load);
1644
1645void ide_pad_transfer(ide_drive_t *drive, int write, int len)
1646{
1647 ide_hwif_t *hwif = drive->hwif;
1648 u8 buf[4] = { 0 };
1649
1650 while (len > 0) {
1651 if (write)
1652 hwif->output_data(drive, NULL, buf, min(4, len));
1653 else
1654 hwif->input_data(drive, NULL, buf, min(4, len));
1655 len -= 4;
1656 }
1657}
1658EXPORT_SYMBOL_GPL(ide_pad_transfer);
diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c
index 9c646bd63549..57d9a9a79a6f 100644
--- a/drivers/ide/ide-iops.c
+++ b/drivers/ide/ide-iops.c
@@ -37,21 +37,6 @@ static u8 ide_inb (unsigned long port)
37 return (u8) inb(port); 37 return (u8) inb(port);
38} 38}
39 39
40static u16 ide_inw (unsigned long port)
41{
42 return (u16) inw(port);
43}
44
45static void ide_insw (unsigned long port, void *addr, u32 count)
46{
47 insw(port, addr, count);
48}
49
50static void ide_insl (unsigned long port, void *addr, u32 count)
51{
52 insl(port, addr, count);
53}
54
55static void ide_outb (u8 val, unsigned long port) 40static void ide_outb (u8 val, unsigned long port)
56{ 41{
57 outb(val, port); 42 outb(val, port);
@@ -62,32 +47,11 @@ static void ide_outbsync (ide_drive_t *drive, u8 addr, unsigned long port)
62 outb(addr, port); 47 outb(addr, port);
63} 48}
64 49
65static void ide_outw (u16 val, unsigned long port)
66{
67 outw(val, port);
68}
69
70static void ide_outsw (unsigned long port, void *addr, u32 count)
71{
72 outsw(port, addr, count);
73}
74
75static void ide_outsl (unsigned long port, void *addr, u32 count)
76{
77 outsl(port, addr, count);
78}
79
80void default_hwif_iops (ide_hwif_t *hwif) 50void default_hwif_iops (ide_hwif_t *hwif)
81{ 51{
82 hwif->OUTB = ide_outb; 52 hwif->OUTB = ide_outb;
83 hwif->OUTBSYNC = ide_outbsync; 53 hwif->OUTBSYNC = ide_outbsync;
84 hwif->OUTW = ide_outw;
85 hwif->OUTSW = ide_outsw;
86 hwif->OUTSL = ide_outsl;
87 hwif->INB = ide_inb; 54 hwif->INB = ide_inb;
88 hwif->INW = ide_inw;
89 hwif->INSW = ide_insw;
90 hwif->INSL = ide_insl;
91} 55}
92 56
93/* 57/*
@@ -99,21 +63,6 @@ static u8 ide_mm_inb (unsigned long port)
99 return (u8) readb((void __iomem *) port); 63 return (u8) readb((void __iomem *) port);
100} 64}
101 65
102static u16 ide_mm_inw (unsigned long port)
103{
104 return (u16) readw((void __iomem *) port);
105}
106
107static void ide_mm_insw (unsigned long port, void *addr, u32 count)
108{
109 __ide_mm_insw((void __iomem *) port, addr, count);
110}
111
112static void ide_mm_insl (unsigned long port, void *addr, u32 count)
113{
114 __ide_mm_insl((void __iomem *) port, addr, count);
115}
116
117static void ide_mm_outb (u8 value, unsigned long port) 66static void ide_mm_outb (u8 value, unsigned long port)
118{ 67{
119 writeb(value, (void __iomem *) port); 68 writeb(value, (void __iomem *) port);
@@ -124,34 +73,13 @@ static void ide_mm_outbsync (ide_drive_t *drive, u8 value, unsigned long port)
124 writeb(value, (void __iomem *) port); 73 writeb(value, (void __iomem *) port);
125} 74}
126 75
127static void ide_mm_outw (u16 value, unsigned long port)
128{
129 writew(value, (void __iomem *) port);
130}
131
132static void ide_mm_outsw (unsigned long port, void *addr, u32 count)
133{
134 __ide_mm_outsw((void __iomem *) port, addr, count);
135}
136
137static void ide_mm_outsl (unsigned long port, void *addr, u32 count)
138{
139 __ide_mm_outsl((void __iomem *) port, addr, count);
140}
141
142void default_hwif_mmiops (ide_hwif_t *hwif) 76void default_hwif_mmiops (ide_hwif_t *hwif)
143{ 77{
144 hwif->OUTB = ide_mm_outb; 78 hwif->OUTB = ide_mm_outb;
145 /* Most systems will need to override OUTBSYNC, alas however 79 /* Most systems will need to override OUTBSYNC, alas however
146 this one is controller specific! */ 80 this one is controller specific! */
147 hwif->OUTBSYNC = ide_mm_outbsync; 81 hwif->OUTBSYNC = ide_mm_outbsync;
148 hwif->OUTW = ide_mm_outw;
149 hwif->OUTSW = ide_mm_outsw;
150 hwif->OUTSL = ide_mm_outsl;
151 hwif->INB = ide_mm_inb; 82 hwif->INB = ide_mm_inb;
152 hwif->INW = ide_mm_inw;
153 hwif->INSW = ide_mm_insw;
154 hwif->INSL = ide_mm_insl;
155} 83}
156 84
157EXPORT_SYMBOL(default_hwif_mmiops); 85EXPORT_SYMBOL(default_hwif_mmiops);
@@ -164,7 +92,7 @@ void SELECT_DRIVE (ide_drive_t *drive)
164 if (port_ops && port_ops->selectproc) 92 if (port_ops && port_ops->selectproc)
165 port_ops->selectproc(drive); 93 port_ops->selectproc(drive);
166 94
167 hwif->OUTB(drive->select.all, hwif->io_ports[IDE_SELECT_OFFSET]); 95 hwif->OUTB(drive->select.all, hwif->io_ports.device_addr);
168} 96}
169 97
170void SELECT_MASK (ide_drive_t *drive, int mask) 98void SELECT_MASK (ide_drive_t *drive, int mask)
@@ -175,6 +103,123 @@ void SELECT_MASK (ide_drive_t *drive, int mask)
175 port_ops->maskproc(drive, mask); 103 port_ops->maskproc(drive, mask);
176} 104}
177 105
106static void ide_tf_load(ide_drive_t *drive, ide_task_t *task)
107{
108 ide_hwif_t *hwif = drive->hwif;
109 struct ide_io_ports *io_ports = &hwif->io_ports;
110 struct ide_taskfile *tf = &task->tf;
111 void (*tf_outb)(u8 addr, unsigned long port);
112 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
113 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
114
115 if (mmio)
116 tf_outb = ide_mm_outb;
117 else
118 tf_outb = ide_outb;
119
120 if (task->tf_flags & IDE_TFLAG_FLAGGED)
121 HIHI = 0xFF;
122
123 ide_set_irq(drive, 1);
124
125 if ((task->tf_flags & IDE_TFLAG_NO_SELECT_MASK) == 0)
126 SELECT_MASK(drive, 0);
127
128 if (task->tf_flags & IDE_TFLAG_OUT_DATA) {
129 u16 data = (tf->hob_data << 8) | tf->data;
130
131 if (mmio)
132 writew(data, (void __iomem *)io_ports->data_addr);
133 else
134 outw(data, io_ports->data_addr);
135 }
136
137 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
138 tf_outb(tf->hob_feature, io_ports->feature_addr);
139 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
140 tf_outb(tf->hob_nsect, io_ports->nsect_addr);
141 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
142 tf_outb(tf->hob_lbal, io_ports->lbal_addr);
143 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
144 tf_outb(tf->hob_lbam, io_ports->lbam_addr);
145 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
146 tf_outb(tf->hob_lbah, io_ports->lbah_addr);
147
148 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
149 tf_outb(tf->feature, io_ports->feature_addr);
150 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
151 tf_outb(tf->nsect, io_ports->nsect_addr);
152 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
153 tf_outb(tf->lbal, io_ports->lbal_addr);
154 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
155 tf_outb(tf->lbam, io_ports->lbam_addr);
156 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
157 tf_outb(tf->lbah, io_ports->lbah_addr);
158
159 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
160 tf_outb((tf->device & HIHI) | drive->select.all,
161 io_ports->device_addr);
162}
163
164static void ide_tf_read(ide_drive_t *drive, ide_task_t *task)
165{
166 ide_hwif_t *hwif = drive->hwif;
167 struct ide_io_ports *io_ports = &hwif->io_ports;
168 struct ide_taskfile *tf = &task->tf;
169 void (*tf_outb)(u8 addr, unsigned long port);
170 u8 (*tf_inb)(unsigned long port);
171 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
172
173 if (mmio) {
174 tf_outb = ide_mm_outb;
175 tf_inb = ide_mm_inb;
176 } else {
177 tf_outb = ide_outb;
178 tf_inb = ide_inb;
179 }
180
181 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
182 u16 data;
183
184 if (mmio)
185 data = readw((void __iomem *)io_ports->data_addr);
186 else
187 data = inw(io_ports->data_addr);
188
189 tf->data = data & 0xff;
190 tf->hob_data = (data >> 8) & 0xff;
191 }
192
193 /* be sure we're looking at the low order bits */
194 tf_outb(drive->ctl & ~0x80, io_ports->ctl_addr);
195
196 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
197 tf->nsect = tf_inb(io_ports->nsect_addr);
198 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
199 tf->lbal = tf_inb(io_ports->lbal_addr);
200 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
201 tf->lbam = tf_inb(io_ports->lbam_addr);
202 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
203 tf->lbah = tf_inb(io_ports->lbah_addr);
204 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
205 tf->device = tf_inb(io_ports->device_addr);
206
207 if (task->tf_flags & IDE_TFLAG_LBA48) {
208 tf_outb(drive->ctl | 0x80, io_ports->ctl_addr);
209
210 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
211 tf->hob_feature = tf_inb(io_ports->feature_addr);
212 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
213 tf->hob_nsect = tf_inb(io_ports->nsect_addr);
214 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
215 tf->hob_lbal = tf_inb(io_ports->lbal_addr);
216 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
217 tf->hob_lbam = tf_inb(io_ports->lbam_addr);
218 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
219 tf->hob_lbah = tf_inb(io_ports->lbah_addr);
220 }
221}
222
178/* 223/*
179 * Some localbus EIDE interfaces require a special access sequence 224 * Some localbus EIDE interfaces require a special access sequence
180 * when using 32-bit I/O instructions to transfer data. We call this 225 * when using 32-bit I/O instructions to transfer data. We call this
@@ -182,115 +227,112 @@ void SELECT_MASK (ide_drive_t *drive, int mask)
182 * of the sector count register location, with interrupts disabled 227 * of the sector count register location, with interrupts disabled
183 * to ensure that the reads all happen together. 228 * to ensure that the reads all happen together.
184 */ 229 */
185static void ata_vlb_sync(ide_drive_t *drive, unsigned long port) 230static void ata_vlb_sync(unsigned long port)
186{ 231{
187 (void) HWIF(drive)->INB(port); 232 (void)inb(port);
188 (void) HWIF(drive)->INB(port); 233 (void)inb(port);
189 (void) HWIF(drive)->INB(port); 234 (void)inb(port);
190} 235}
191 236
192/* 237/*
193 * This is used for most PIO data transfers *from* the IDE interface 238 * This is used for most PIO data transfers *from* the IDE interface
239 *
240 * These routines will round up any request for an odd number of bytes,
241 * so if an odd len is specified, be sure that there's at least one
242 * extra byte allocated for the buffer.
194 */ 243 */
195static void ata_input_data(ide_drive_t *drive, void *buffer, u32 wcount) 244static void ata_input_data(ide_drive_t *drive, struct request *rq,
245 void *buf, unsigned int len)
196{ 246{
197 ide_hwif_t *hwif = HWIF(drive); 247 ide_hwif_t *hwif = drive->hwif;
198 u8 io_32bit = drive->io_32bit; 248 struct ide_io_ports *io_ports = &hwif->io_ports;
249 unsigned long data_addr = io_ports->data_addr;
250 u8 io_32bit = drive->io_32bit;
251 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
252
253 len++;
199 254
200 if (io_32bit) { 255 if (io_32bit) {
201 if (io_32bit & 2) { 256 unsigned long uninitialized_var(flags);
202 unsigned long flags;
203 257
258 if ((io_32bit & 2) && !mmio) {
204 local_irq_save(flags); 259 local_irq_save(flags);
205 ata_vlb_sync(drive, hwif->io_ports[IDE_NSECTOR_OFFSET]); 260 ata_vlb_sync(io_ports->nsect_addr);
206 hwif->INSL(hwif->io_ports[IDE_DATA_OFFSET], buffer, 261 }
207 wcount); 262
263 if (mmio)
264 __ide_mm_insl((void __iomem *)data_addr, buf, len / 4);
265 else
266 insl(data_addr, buf, len / 4);
267
268 if ((io_32bit & 2) && !mmio)
208 local_irq_restore(flags); 269 local_irq_restore(flags);
209 } else 270
210 hwif->INSL(hwif->io_ports[IDE_DATA_OFFSET], buffer, 271 if ((len & 3) >= 2) {
211 wcount); 272 if (mmio)
212 } else 273 __ide_mm_insw((void __iomem *)data_addr,
213 hwif->INSW(hwif->io_ports[IDE_DATA_OFFSET], buffer, 274 (u8 *)buf + (len & ~3), 1);
214 wcount << 1); 275 else
276 insw(data_addr, (u8 *)buf + (len & ~3), 1);
277 }
278 } else {
279 if (mmio)
280 __ide_mm_insw((void __iomem *)data_addr, buf, len / 2);
281 else
282 insw(data_addr, buf, len / 2);
283 }
215} 284}
216 285
217/* 286/*
218 * This is used for most PIO data transfers *to* the IDE interface 287 * This is used for most PIO data transfers *to* the IDE interface
219 */ 288 */
220static void ata_output_data(ide_drive_t *drive, void *buffer, u32 wcount) 289static void ata_output_data(ide_drive_t *drive, struct request *rq,
290 void *buf, unsigned int len)
221{ 291{
222 ide_hwif_t *hwif = HWIF(drive); 292 ide_hwif_t *hwif = drive->hwif;
223 u8 io_32bit = drive->io_32bit; 293 struct ide_io_ports *io_ports = &hwif->io_ports;
294 unsigned long data_addr = io_ports->data_addr;
295 u8 io_32bit = drive->io_32bit;
296 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
224 297
225 if (io_32bit) { 298 if (io_32bit) {
226 if (io_32bit & 2) { 299 unsigned long uninitialized_var(flags);
227 unsigned long flags;
228 300
301 if ((io_32bit & 2) && !mmio) {
229 local_irq_save(flags); 302 local_irq_save(flags);
230 ata_vlb_sync(drive, hwif->io_ports[IDE_NSECTOR_OFFSET]); 303 ata_vlb_sync(io_ports->nsect_addr);
231 hwif->OUTSL(hwif->io_ports[IDE_DATA_OFFSET], buffer, 304 }
232 wcount);
233 local_irq_restore(flags);
234 } else
235 hwif->OUTSL(hwif->io_ports[IDE_DATA_OFFSET], buffer,
236 wcount);
237 } else
238 hwif->OUTSW(hwif->io_ports[IDE_DATA_OFFSET], buffer,
239 wcount << 1);
240}
241
242/*
243 * The following routines are mainly used by the ATAPI drivers.
244 *
245 * These routines will round up any request for an odd number of bytes,
246 * so if an odd bytecount is specified, be sure that there's at least one
247 * extra byte allocated for the buffer.
248 */
249
250static void atapi_input_bytes(ide_drive_t *drive, void *buffer, u32 bytecount)
251{
252 ide_hwif_t *hwif = HWIF(drive);
253 305
254 ++bytecount; 306 if (mmio)
255#if defined(CONFIG_ATARI) || defined(CONFIG_Q40) 307 __ide_mm_outsl((void __iomem *)data_addr, buf, len / 4);
256 if (MACH_IS_ATARI || MACH_IS_Q40) { 308 else
257 /* Atari has a byte-swapped IDE interface */ 309 outsl(data_addr, buf, len / 4);
258 insw_swapw(hwif->io_ports[IDE_DATA_OFFSET], buffer,
259 bytecount / 2);
260 return;
261 }
262#endif /* CONFIG_ATARI || CONFIG_Q40 */
263 hwif->ata_input_data(drive, buffer, bytecount / 4);
264 if ((bytecount & 0x03) >= 2)
265 hwif->INSW(hwif->io_ports[IDE_DATA_OFFSET],
266 (u8 *)buffer + (bytecount & ~0x03), 1);
267}
268 310
269static void atapi_output_bytes(ide_drive_t *drive, void *buffer, u32 bytecount) 311 if ((io_32bit & 2) && !mmio)
270{ 312 local_irq_restore(flags);
271 ide_hwif_t *hwif = HWIF(drive);
272 313
273 ++bytecount; 314 if ((len & 3) >= 2) {
274#if defined(CONFIG_ATARI) || defined(CONFIG_Q40) 315 if (mmio)
275 if (MACH_IS_ATARI || MACH_IS_Q40) { 316 __ide_mm_outsw((void __iomem *)data_addr,
276 /* Atari has a byte-swapped IDE interface */ 317 (u8 *)buf + (len & ~3), 1);
277 outsw_swapw(hwif->io_ports[IDE_DATA_OFFSET], buffer, 318 else
278 bytecount / 2); 319 outsw(data_addr, (u8 *)buf + (len & ~3), 1);
279 return; 320 }
321 } else {
322 if (mmio)
323 __ide_mm_outsw((void __iomem *)data_addr, buf, len / 2);
324 else
325 outsw(data_addr, buf, len / 2);
280 } 326 }
281#endif /* CONFIG_ATARI || CONFIG_Q40 */
282 hwif->ata_output_data(drive, buffer, bytecount / 4);
283 if ((bytecount & 0x03) >= 2)
284 hwif->OUTSW(hwif->io_ports[IDE_DATA_OFFSET],
285 (u8 *)buffer + (bytecount & ~0x03), 1);
286} 327}
287 328
288void default_hwif_transport(ide_hwif_t *hwif) 329void default_hwif_transport(ide_hwif_t *hwif)
289{ 330{
290 hwif->ata_input_data = ata_input_data; 331 hwif->tf_load = ide_tf_load;
291 hwif->ata_output_data = ata_output_data; 332 hwif->tf_read = ide_tf_read;
292 hwif->atapi_input_bytes = atapi_input_bytes; 333
293 hwif->atapi_output_bytes = atapi_output_bytes; 334 hwif->input_data = ata_input_data;
335 hwif->output_data = ata_output_data;
294} 336}
295 337
296void ide_fix_driveid (struct hd_driveid *id) 338void ide_fix_driveid (struct hd_driveid *id)
@@ -445,7 +487,7 @@ int drive_is_ready (ide_drive_t *drive)
445 * an interrupt with another pci card/device. We make no assumptions 487 * an interrupt with another pci card/device. We make no assumptions
446 * about possible isa-pnp and pci-pnp issues yet. 488 * about possible isa-pnp and pci-pnp issues yet.
447 */ 489 */
448 if (hwif->io_ports[IDE_CONTROL_OFFSET]) 490 if (hwif->io_ports.ctl_addr)
449 stat = ide_read_altstatus(drive); 491 stat = ide_read_altstatus(drive);
450 else 492 else
451 /* Note: this may clear a pending IRQ!! */ 493 /* Note: this may clear a pending IRQ!! */
@@ -583,6 +625,8 @@ static const struct drive_list_entry ivb_list[] = {
583 { "TSSTcorp CDDVDW SH-S202J" , "SB01" }, 625 { "TSSTcorp CDDVDW SH-S202J" , "SB01" },
584 { "TSSTcorp CDDVDW SH-S202N" , "SB00" }, 626 { "TSSTcorp CDDVDW SH-S202N" , "SB00" },
585 { "TSSTcorp CDDVDW SH-S202N" , "SB01" }, 627 { "TSSTcorp CDDVDW SH-S202N" , "SB01" },
628 { "TSSTcorp CDDVDW SH-S202H" , "SB00" },
629 { "TSSTcorp CDDVDW SH-S202H" , "SB01" },
586 { NULL , NULL } 630 { NULL , NULL }
587}; 631};
588 632
@@ -647,7 +691,7 @@ int ide_driveid_update(ide_drive_t *drive)
647 SELECT_MASK(drive, 1); 691 SELECT_MASK(drive, 1);
648 ide_set_irq(drive, 1); 692 ide_set_irq(drive, 1);
649 msleep(50); 693 msleep(50);
650 hwif->OUTB(WIN_IDENTIFY, hwif->io_ports[IDE_COMMAND_OFFSET]); 694 hwif->OUTBSYNC(drive, WIN_IDENTIFY, hwif->io_ports.command_addr);
651 timeout = jiffies + WAIT_WORSTCASE; 695 timeout = jiffies + WAIT_WORSTCASE;
652 do { 696 do {
653 if (time_after(jiffies, timeout)) { 697 if (time_after(jiffies, timeout)) {
@@ -674,7 +718,7 @@ int ide_driveid_update(ide_drive_t *drive)
674 local_irq_restore(flags); 718 local_irq_restore(flags);
675 return 0; 719 return 0;
676 } 720 }
677 hwif->ata_input_data(drive, id, SECTOR_WORDS); 721 hwif->input_data(drive, NULL, id, SECTOR_SIZE);
678 (void)ide_read_status(drive); /* clear drive IRQ */ 722 (void)ide_read_status(drive); /* clear drive IRQ */
679 local_irq_enable(); 723 local_irq_enable();
680 local_irq_restore(flags); 724 local_irq_restore(flags);
@@ -696,6 +740,7 @@ int ide_driveid_update(ide_drive_t *drive)
696int ide_config_drive_speed(ide_drive_t *drive, u8 speed) 740int ide_config_drive_speed(ide_drive_t *drive, u8 speed)
697{ 741{
698 ide_hwif_t *hwif = drive->hwif; 742 ide_hwif_t *hwif = drive->hwif;
743 struct ide_io_ports *io_ports = &hwif->io_ports;
699 int error = 0; 744 int error = 0;
700 u8 stat; 745 u8 stat;
701 746
@@ -734,10 +779,9 @@ int ide_config_drive_speed(ide_drive_t *drive, u8 speed)
734 SELECT_MASK(drive, 0); 779 SELECT_MASK(drive, 0);
735 udelay(1); 780 udelay(1);
736 ide_set_irq(drive, 0); 781 ide_set_irq(drive, 0);
737 hwif->OUTB(speed, hwif->io_ports[IDE_NSECTOR_OFFSET]); 782 hwif->OUTB(speed, io_ports->nsect_addr);
738 hwif->OUTB(SETFEATURES_XFER, hwif->io_ports[IDE_FEATURE_OFFSET]); 783 hwif->OUTB(SETFEATURES_XFER, io_ports->feature_addr);
739 hwif->OUTBSYNC(drive, WIN_SETFEATURES, 784 hwif->OUTBSYNC(drive, WIN_SETFEATURES, io_ports->command_addr);
740 hwif->io_ports[IDE_COMMAND_OFFSET]);
741 if (drive->quirk_list == 2) 785 if (drive->quirk_list == 2)
742 ide_set_irq(drive, 1); 786 ide_set_irq(drive, 1);
743 787
@@ -845,7 +889,7 @@ void ide_execute_command(ide_drive_t *drive, u8 cmd, ide_handler_t *handler,
845 889
846 spin_lock_irqsave(&ide_lock, flags); 890 spin_lock_irqsave(&ide_lock, flags);
847 __ide_set_handler(drive, handler, timeout, expiry); 891 __ide_set_handler(drive, handler, timeout, expiry);
848 hwif->OUTBSYNC(drive, cmd, hwif->io_ports[IDE_COMMAND_OFFSET]); 892 hwif->OUTBSYNC(drive, cmd, hwif->io_ports.command_addr);
849 /* 893 /*
850 * Drive takes 400nS to respond, we must avoid the IRQ being 894 * Drive takes 400nS to respond, we must avoid the IRQ being
851 * serviced before that. 895 * serviced before that.
@@ -855,9 +899,19 @@ void ide_execute_command(ide_drive_t *drive, u8 cmd, ide_handler_t *handler,
855 ndelay(400); 899 ndelay(400);
856 spin_unlock_irqrestore(&ide_lock, flags); 900 spin_unlock_irqrestore(&ide_lock, flags);
857} 901}
858
859EXPORT_SYMBOL(ide_execute_command); 902EXPORT_SYMBOL(ide_execute_command);
860 903
904void ide_execute_pkt_cmd(ide_drive_t *drive)
905{
906 ide_hwif_t *hwif = drive->hwif;
907 unsigned long flags;
908
909 spin_lock_irqsave(&ide_lock, flags);
910 hwif->OUTBSYNC(drive, WIN_PACKETCMD, hwif->io_ports.command_addr);
911 ndelay(400);
912 spin_unlock_irqrestore(&ide_lock, flags);
913}
914EXPORT_SYMBOL_GPL(ide_execute_pkt_cmd);
861 915
862/* needed below */ 916/* needed below */
863static ide_startstop_t do_reset1 (ide_drive_t *, int); 917static ide_startstop_t do_reset1 (ide_drive_t *, int);
@@ -1029,6 +1083,7 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
1029 unsigned long flags; 1083 unsigned long flags;
1030 ide_hwif_t *hwif; 1084 ide_hwif_t *hwif;
1031 ide_hwgroup_t *hwgroup; 1085 ide_hwgroup_t *hwgroup;
1086 struct ide_io_ports *io_ports;
1032 const struct ide_port_ops *port_ops; 1087 const struct ide_port_ops *port_ops;
1033 u8 ctl; 1088 u8 ctl;
1034 1089
@@ -1036,6 +1091,8 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
1036 hwif = HWIF(drive); 1091 hwif = HWIF(drive);
1037 hwgroup = HWGROUP(drive); 1092 hwgroup = HWGROUP(drive);
1038 1093
1094 io_ports = &hwif->io_ports;
1095
1039 /* We must not reset with running handlers */ 1096 /* We must not reset with running handlers */
1040 BUG_ON(hwgroup->handler != NULL); 1097 BUG_ON(hwgroup->handler != NULL);
1041 1098
@@ -1045,8 +1102,7 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
1045 pre_reset(drive); 1102 pre_reset(drive);
1046 SELECT_DRIVE(drive); 1103 SELECT_DRIVE(drive);
1047 udelay (20); 1104 udelay (20);
1048 hwif->OUTBSYNC(drive, WIN_SRST, 1105 hwif->OUTBSYNC(drive, WIN_SRST, io_ports->command_addr);
1049 hwif->io_ports[IDE_COMMAND_OFFSET]);
1050 ndelay(400); 1106 ndelay(400);
1051 hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE; 1107 hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE;
1052 hwgroup->polling = 1; 1108 hwgroup->polling = 1;
@@ -1062,7 +1118,7 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
1062 for (unit = 0; unit < MAX_DRIVES; ++unit) 1118 for (unit = 0; unit < MAX_DRIVES; ++unit)
1063 pre_reset(&hwif->drives[unit]); 1119 pre_reset(&hwif->drives[unit]);
1064 1120
1065 if (hwif->io_ports[IDE_CONTROL_OFFSET] == 0) { 1121 if (io_ports->ctl_addr == 0) {
1066 spin_unlock_irqrestore(&ide_lock, flags); 1122 spin_unlock_irqrestore(&ide_lock, flags);
1067 return ide_stopped; 1123 return ide_stopped;
1068 } 1124 }
@@ -1077,14 +1133,14 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
1077 * recover from reset very quickly, saving us the first 50ms wait time. 1133 * recover from reset very quickly, saving us the first 50ms wait time.
1078 */ 1134 */
1079 /* set SRST and nIEN */ 1135 /* set SRST and nIEN */
1080 hwif->OUTBSYNC(drive, drive->ctl|6, hwif->io_ports[IDE_CONTROL_OFFSET]); 1136 hwif->OUTBSYNC(drive, drive->ctl|6, io_ports->ctl_addr);
1081 /* more than enough time */ 1137 /* more than enough time */
1082 udelay(10); 1138 udelay(10);
1083 if (drive->quirk_list == 2) 1139 if (drive->quirk_list == 2)
1084 ctl = drive->ctl; /* clear SRST and nIEN */ 1140 ctl = drive->ctl; /* clear SRST and nIEN */
1085 else 1141 else
1086 ctl = drive->ctl | 2; /* clear SRST, leave nIEN */ 1142 ctl = drive->ctl | 2; /* clear SRST, leave nIEN */
1087 hwif->OUTBSYNC(drive, ctl, hwif->io_ports[IDE_CONTROL_OFFSET]); 1143 hwif->OUTBSYNC(drive, ctl, io_ports->ctl_addr);
1088 /* more than enough time */ 1144 /* more than enough time */
1089 udelay(10); 1145 udelay(10);
1090 hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE; 1146 hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE;
@@ -1129,7 +1185,7 @@ int ide_wait_not_busy(ide_hwif_t *hwif, unsigned long timeout)
1129 * about locking issues (2.5 work ?). 1185 * about locking issues (2.5 work ?).
1130 */ 1186 */
1131 mdelay(1); 1187 mdelay(1);
1132 stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 1188 stat = hwif->INB(hwif->io_ports.status_addr);
1133 if ((stat & BUSY_STAT) == 0) 1189 if ((stat & BUSY_STAT) == 0)
1134 return 0; 1190 return 0;
1135 /* 1191 /*
diff --git a/drivers/ide/ide-lib.c b/drivers/ide/ide-lib.c
index 6f04ea3e93a8..47af80df6872 100644
--- a/drivers/ide/ide-lib.c
+++ b/drivers/ide/ide-lib.c
@@ -487,7 +487,7 @@ static void ide_dump_sector(ide_drive_t *drive)
487 else 487 else
488 task.tf_flags = IDE_TFLAG_IN_LBA | IDE_TFLAG_IN_DEVICE; 488 task.tf_flags = IDE_TFLAG_IN_LBA | IDE_TFLAG_IN_DEVICE;
489 489
490 ide_tf_read(drive, &task); 490 drive->hwif->tf_read(drive, &task);
491 491
492 if (lba48 || (tf->device & ATA_LBA)) 492 if (lba48 || (tf->device & ATA_LBA))
493 printk(", LBAsect=%llu", 493 printk(", LBAsect=%llu",
diff --git a/drivers/ide/ide-pnp.c b/drivers/ide/ide-pnp.c
index 10c20e9a5785..6a8953f68e9f 100644
--- a/drivers/ide/ide-pnp.c
+++ b/drivers/ide/ide-pnp.c
@@ -82,10 +82,7 @@ static void idepnp_remove(struct pnp_dev *dev)
82{ 82{
83 ide_hwif_t *hwif = pnp_get_drvdata(dev); 83 ide_hwif_t *hwif = pnp_get_drvdata(dev);
84 84
85 if (hwif) 85 ide_unregister(hwif);
86 ide_unregister(hwif->index);
87 else
88 printk(KERN_ERR "idepnp: Unable to remove device, please report.\n");
89 86
90 release_region(pnp_port_start(dev, 1), 1); 87 release_region(pnp_port_start(dev, 1), 1);
91 release_region(pnp_port_start(dev, 0), 8); 88 release_region(pnp_port_start(dev, 0), 8);
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
index a4b65b321f51..099a0fe1745b 100644
--- a/drivers/ide/ide-probe.c
+++ b/drivers/ide/ide-probe.c
@@ -124,7 +124,7 @@ static inline void do_identify (ide_drive_t *drive, u8 cmd)
124 124
125 id = drive->id; 125 id = drive->id;
126 /* read 512 bytes of id info */ 126 /* read 512 bytes of id info */
127 hwif->ata_input_data(drive, id, SECTOR_WORDS); 127 hwif->input_data(drive, NULL, id, SECTOR_SIZE);
128 128
129 drive->id_read = 1; 129 drive->id_read = 1;
130 local_irq_enable(); 130 local_irq_enable();
@@ -264,6 +264,7 @@ err_misc:
264static int actual_try_to_identify (ide_drive_t *drive, u8 cmd) 264static int actual_try_to_identify (ide_drive_t *drive, u8 cmd)
265{ 265{
266 ide_hwif_t *hwif = HWIF(drive); 266 ide_hwif_t *hwif = HWIF(drive);
267 struct ide_io_ports *io_ports = &hwif->io_ports;
267 int use_altstatus = 0, rc; 268 int use_altstatus = 0, rc;
268 unsigned long timeout; 269 unsigned long timeout;
269 u8 s = 0, a = 0; 270 u8 s = 0, a = 0;
@@ -271,7 +272,7 @@ static int actual_try_to_identify (ide_drive_t *drive, u8 cmd)
271 /* take a deep breath */ 272 /* take a deep breath */
272 msleep(50); 273 msleep(50);
273 274
274 if (hwif->io_ports[IDE_CONTROL_OFFSET]) { 275 if (io_ports->ctl_addr) {
275 a = ide_read_altstatus(drive); 276 a = ide_read_altstatus(drive);
276 s = ide_read_status(drive); 277 s = ide_read_status(drive);
277 if ((a ^ s) & ~INDEX_STAT) 278 if ((a ^ s) & ~INDEX_STAT)
@@ -289,10 +290,10 @@ static int actual_try_to_identify (ide_drive_t *drive, u8 cmd)
289 */ 290 */
290 if ((cmd == WIN_PIDENTIFY)) 291 if ((cmd == WIN_PIDENTIFY))
291 /* disable dma & overlap */ 292 /* disable dma & overlap */
292 hwif->OUTB(0, hwif->io_ports[IDE_FEATURE_OFFSET]); 293 hwif->OUTB(0, io_ports->feature_addr);
293 294
294 /* ask drive for ID */ 295 /* ask drive for ID */
295 hwif->OUTB(cmd, hwif->io_ports[IDE_COMMAND_OFFSET]); 296 hwif->OUTBSYNC(drive, cmd, io_ports->command_addr);
296 297
297 timeout = ((cmd == WIN_IDENTIFY) ? WAIT_WORSTCASE : WAIT_PIDENTIFY) / 2; 298 timeout = ((cmd == WIN_IDENTIFY) ? WAIT_WORSTCASE : WAIT_PIDENTIFY) / 2;
298 timeout += jiffies; 299 timeout += jiffies;
@@ -353,7 +354,7 @@ static int try_to_identify (ide_drive_t *drive, u8 cmd)
353 * interrupts during the identify-phase that 354 * interrupts during the identify-phase that
354 * the irq handler isn't expecting. 355 * the irq handler isn't expecting.
355 */ 356 */
356 if (hwif->io_ports[IDE_CONTROL_OFFSET]) { 357 if (hwif->io_ports.ctl_addr) {
357 if (!hwif->irq) { 358 if (!hwif->irq) {
358 autoprobe = 1; 359 autoprobe = 1;
359 cookie = probe_irq_on(); 360 cookie = probe_irq_on();
@@ -393,7 +394,7 @@ static int ide_busy_sleep(ide_hwif_t *hwif)
393 394
394 do { 395 do {
395 msleep(50); 396 msleep(50);
396 stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 397 stat = hwif->INB(hwif->io_ports.status_addr);
397 if ((stat & BUSY_STAT) == 0) 398 if ((stat & BUSY_STAT) == 0)
398 return 0; 399 return 0;
399 } while (time_before(jiffies, timeout)); 400 } while (time_before(jiffies, timeout));
@@ -425,6 +426,7 @@ static int ide_busy_sleep(ide_hwif_t *hwif)
425static int do_probe (ide_drive_t *drive, u8 cmd) 426static int do_probe (ide_drive_t *drive, u8 cmd)
426{ 427{
427 ide_hwif_t *hwif = HWIF(drive); 428 ide_hwif_t *hwif = HWIF(drive);
429 struct ide_io_ports *io_ports = &hwif->io_ports;
428 int rc; 430 int rc;
429 u8 stat; 431 u8 stat;
430 432
@@ -445,7 +447,7 @@ static int do_probe (ide_drive_t *drive, u8 cmd)
445 msleep(50); 447 msleep(50);
446 SELECT_DRIVE(drive); 448 SELECT_DRIVE(drive);
447 msleep(50); 449 msleep(50);
448 if (hwif->INB(hwif->io_ports[IDE_SELECT_OFFSET]) != drive->select.all && 450 if (hwif->INB(io_ports->device_addr) != drive->select.all &&
449 !drive->present) { 451 !drive->present) {
450 if (drive->select.b.unit != 0) { 452 if (drive->select.b.unit != 0) {
451 /* exit with drive0 selected */ 453 /* exit with drive0 selected */
@@ -472,17 +474,13 @@ static int do_probe (ide_drive_t *drive, u8 cmd)
472 if (stat == (BUSY_STAT | READY_STAT)) 474 if (stat == (BUSY_STAT | READY_STAT))
473 return 4; 475 return 4;
474 476
475 if ((rc == 1 && cmd == WIN_PIDENTIFY) && 477 if (rc == 1 && cmd == WIN_PIDENTIFY) {
476 ((drive->autotune == IDE_TUNE_DEFAULT) ||
477 (drive->autotune == IDE_TUNE_AUTO))) {
478 printk(KERN_ERR "%s: no response (status = 0x%02x), " 478 printk(KERN_ERR "%s: no response (status = 0x%02x), "
479 "resetting drive\n", drive->name, stat); 479 "resetting drive\n", drive->name, stat);
480 msleep(50); 480 msleep(50);
481 hwif->OUTB(drive->select.all, 481 hwif->OUTB(drive->select.all, io_ports->device_addr);
482 hwif->io_ports[IDE_SELECT_OFFSET]);
483 msleep(50); 482 msleep(50);
484 hwif->OUTB(WIN_SRST, 483 hwif->OUTBSYNC(drive, WIN_SRST, io_ports->command_addr);
485 hwif->io_ports[IDE_COMMAND_OFFSET]);
486 (void)ide_busy_sleep(hwif); 484 (void)ide_busy_sleep(hwif);
487 rc = try_to_identify(drive, cmd); 485 rc = try_to_identify(drive, cmd);
488 } 486 }
@@ -518,7 +516,7 @@ static void enable_nest (ide_drive_t *drive)
518 printk("%s: enabling %s -- ", hwif->name, drive->id->model); 516 printk("%s: enabling %s -- ", hwif->name, drive->id->model);
519 SELECT_DRIVE(drive); 517 SELECT_DRIVE(drive);
520 msleep(50); 518 msleep(50);
521 hwif->OUTB(EXABYTE_ENABLE_NEST, hwif->io_ports[IDE_COMMAND_OFFSET]); 519 hwif->OUTBSYNC(drive, EXABYTE_ENABLE_NEST, hwif->io_ports.command_addr);
522 520
523 if (ide_busy_sleep(hwif)) { 521 if (ide_busy_sleep(hwif)) {
524 printk(KERN_CONT "failed (timeout)\n"); 522 printk(KERN_CONT "failed (timeout)\n");
@@ -800,14 +798,9 @@ static int ide_probe_port(ide_hwif_t *hwif)
800 if (drive->present) 798 if (drive->present)
801 rc = 0; 799 rc = 0;
802 } 800 }
803 if (hwif->io_ports[IDE_CONTROL_OFFSET] && hwif->reset) { 801
804 printk(KERN_WARNING "%s: reset\n", hwif->name);
805 hwif->OUTB(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
806 udelay(10);
807 hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
808 (void)ide_busy_sleep(hwif);
809 }
810 local_irq_restore(flags); 802 local_irq_restore(flags);
803
811 /* 804 /*
812 * Use cached IRQ number. It might be (and is...) changed by probe 805 * Use cached IRQ number. It might be (and is...) changed by probe
813 * code above 806 * code above
@@ -834,12 +827,7 @@ static void ide_port_tune_devices(ide_hwif_t *hwif)
834 ide_drive_t *drive = &hwif->drives[unit]; 827 ide_drive_t *drive = &hwif->drives[unit];
835 828
836 if (drive->present) { 829 if (drive->present) {
837 if (drive->autotune == IDE_TUNE_AUTO) 830 ide_set_max_pio(drive);
838 ide_set_max_pio(drive);
839
840 if (drive->autotune != IDE_TUNE_DEFAULT &&
841 drive->autotune != IDE_TUNE_AUTO)
842 continue;
843 831
844 drive->nice1 = 1; 832 drive->nice1 = 1;
845 833
@@ -994,6 +982,7 @@ static void ide_port_setup_devices(ide_hwif_t *hwif)
994 */ 982 */
995static int init_irq (ide_hwif_t *hwif) 983static int init_irq (ide_hwif_t *hwif)
996{ 984{
985 struct ide_io_ports *io_ports = &hwif->io_ports;
997 unsigned int index; 986 unsigned int index;
998 ide_hwgroup_t *hwgroup; 987 ide_hwgroup_t *hwgroup;
999 ide_hwif_t *match = NULL; 988 ide_hwif_t *match = NULL;
@@ -1077,9 +1066,9 @@ static int init_irq (ide_hwif_t *hwif)
1077 if (IDE_CHIPSET_IS_PCI(hwif->chipset)) 1066 if (IDE_CHIPSET_IS_PCI(hwif->chipset))
1078 sa = IRQF_SHARED; 1067 sa = IRQF_SHARED;
1079 1068
1080 if (hwif->io_ports[IDE_CONTROL_OFFSET]) 1069 if (io_ports->ctl_addr)
1081 /* clear nIEN */ 1070 /* clear nIEN */
1082 hwif->OUTB(0x08, hwif->io_ports[IDE_CONTROL_OFFSET]); 1071 hwif->OUTB(0x08, io_ports->ctl_addr);
1083 1072
1084 if (request_irq(hwif->irq,&ide_intr,sa,hwif->name,hwgroup)) 1073 if (request_irq(hwif->irq,&ide_intr,sa,hwif->name,hwgroup))
1085 goto out_unlink; 1074 goto out_unlink;
@@ -1095,12 +1084,11 @@ static int init_irq (ide_hwif_t *hwif)
1095 1084
1096#if !defined(__mc68000__) 1085#if !defined(__mc68000__)
1097 printk("%s at 0x%03lx-0x%03lx,0x%03lx on irq %d", hwif->name, 1086 printk("%s at 0x%03lx-0x%03lx,0x%03lx on irq %d", hwif->name,
1098 hwif->io_ports[IDE_DATA_OFFSET], 1087 io_ports->data_addr, io_ports->status_addr,
1099 hwif->io_ports[IDE_DATA_OFFSET]+7, 1088 io_ports->ctl_addr, hwif->irq);
1100 hwif->io_ports[IDE_CONTROL_OFFSET], hwif->irq);
1101#else 1089#else
1102 printk("%s at 0x%08lx on irq %d", hwif->name, 1090 printk("%s at 0x%08lx on irq %d", hwif->name,
1103 hwif->io_ports[IDE_DATA_OFFSET], hwif->irq); 1091 io_ports->data_addr, hwif->irq);
1104#endif /* __mc68000__ */ 1092#endif /* __mc68000__ */
1105 if (match) 1093 if (match)
1106 printk(" (%sed with %s)", 1094 printk(" (%sed with %s)",
@@ -1242,8 +1230,8 @@ static int hwif_init(ide_hwif_t *hwif)
1242 int old_irq; 1230 int old_irq;
1243 1231
1244 if (!hwif->irq) { 1232 if (!hwif->irq) {
1245 if (!(hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]))) 1233 hwif->irq = ide_default_irq(hwif->io_ports.data_addr);
1246 { 1234 if (!hwif->irq) {
1247 printk("%s: DISABLED, NO IRQ\n", hwif->name); 1235 printk("%s: DISABLED, NO IRQ\n", hwif->name);
1248 return 0; 1236 return 0;
1249 } 1237 }
@@ -1272,7 +1260,8 @@ static int hwif_init(ide_hwif_t *hwif)
1272 * It failed to initialise. Find the default IRQ for 1260 * It failed to initialise. Find the default IRQ for
1273 * this port and try that. 1261 * this port and try that.
1274 */ 1262 */
1275 if (!(hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]))) { 1263 hwif->irq = ide_default_irq(hwif->io_ports.data_addr);
1264 if (!hwif->irq) {
1276 printk("%s: Disabled unable to get IRQ %d.\n", 1265 printk("%s: Disabled unable to get IRQ %d.\n",
1277 hwif->name, old_irq); 1266 hwif->name, old_irq);
1278 goto out; 1267 goto out;
@@ -1336,8 +1325,6 @@ static void ide_port_init_devices(ide_hwif_t *hwif)
1336 drive->unmask = 1; 1325 drive->unmask = 1;
1337 if (hwif->host_flags & IDE_HFLAG_NO_UNMASK_IRQS) 1326 if (hwif->host_flags & IDE_HFLAG_NO_UNMASK_IRQS)
1338 drive->no_unmask = 1; 1327 drive->no_unmask = 1;
1339 if ((hwif->host_flags & IDE_HFLAG_NO_AUTOTUNE) == 0)
1340 drive->autotune = 1;
1341 } 1328 }
1342 1329
1343 if (port_ops && port_ops->port_init_devs) 1330 if (port_ops && port_ops->port_init_devs)
@@ -1518,13 +1505,20 @@ int ide_device_add_all(u8 *idx, const struct ide_port_info *d)
1518 int i, rc = 0; 1505 int i, rc = 0;
1519 1506
1520 for (i = 0; i < MAX_HWIFS; i++) { 1507 for (i = 0; i < MAX_HWIFS; i++) {
1521 if (d == NULL || idx[i] == 0xff) { 1508 if (idx[i] == 0xff) {
1522 mate = NULL; 1509 mate = NULL;
1523 continue; 1510 continue;
1524 } 1511 }
1525 1512
1526 hwif = &ide_hwifs[idx[i]]; 1513 hwif = &ide_hwifs[idx[i]];
1527 1514
1515 ide_port_apply_params(hwif);
1516
1517 if (d == NULL) {
1518 mate = NULL;
1519 continue;
1520 }
1521
1528 if (d->chipset != ide_etrax100 && (i & 1) && mate) { 1522 if (d->chipset != ide_etrax100 && (i & 1) && mate) {
1529 hwif->mate = mate; 1523 hwif->mate = mate;
1530 mate->mate = hwif; 1524 mate->mate = hwif;
@@ -1621,6 +1615,7 @@ EXPORT_SYMBOL_GPL(ide_device_add);
1621 1615
1622void ide_port_scan(ide_hwif_t *hwif) 1616void ide_port_scan(ide_hwif_t *hwif)
1623{ 1617{
1618 ide_port_apply_params(hwif);
1624 ide_port_cable_detect(hwif); 1619 ide_port_cable_detect(hwif);
1625 ide_port_init_devices(hwif); 1620 ide_port_init_devices(hwif);
1626 1621
diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c
index d9d98ac85b29..8d6ad812a014 100644
--- a/drivers/ide/ide-proc.c
+++ b/drivers/ide/ide-proc.c
@@ -786,14 +786,6 @@ void ide_proc_register_port(ide_hwif_t *hwif)
786 } 786 }
787} 787}
788 788
789#ifdef CONFIG_BLK_DEV_IDEPCI
790void ide_pci_create_host_proc(const char *name, get_info_t *get_info)
791{
792 create_proc_info_entry(name, 0, proc_ide_root, get_info);
793}
794EXPORT_SYMBOL_GPL(ide_pci_create_host_proc);
795#endif
796
797void ide_proc_unregister_port(ide_hwif_t *hwif) 789void ide_proc_unregister_port(ide_hwif_t *hwif)
798{ 790{
799 if (hwif->proc) { 791 if (hwif->proc) {
@@ -830,6 +822,7 @@ static int ide_drivers_open(struct inode *inode, struct file *file)
830} 822}
831 823
832static const struct file_operations ide_drivers_operations = { 824static const struct file_operations ide_drivers_operations = {
825 .owner = THIS_MODULE,
833 .open = ide_drivers_open, 826 .open = ide_drivers_open,
834 .read = seq_read, 827 .read = seq_read,
835 .llseek = seq_lseek, 828 .llseek = seq_lseek,
@@ -838,16 +831,12 @@ static const struct file_operations ide_drivers_operations = {
838 831
839void proc_ide_create(void) 832void proc_ide_create(void)
840{ 833{
841 struct proc_dir_entry *entry;
842
843 proc_ide_root = proc_mkdir("ide", NULL); 834 proc_ide_root = proc_mkdir("ide", NULL);
844 835
845 if (!proc_ide_root) 836 if (!proc_ide_root)
846 return; 837 return;
847 838
848 entry = create_proc_entry("drivers", 0, proc_ide_root); 839 proc_create("drivers", 0, proc_ide_root, &ide_drivers_operations);
849 if (entry)
850 entry->proc_fops = &ide_drivers_operations;
851} 840}
852 841
853void proc_ide_destroy(void) 842void proc_ide_destroy(void)
diff --git a/drivers/ide/ide-tape.c b/drivers/ide/ide-tape.c
index d3d8b8d5157c..1e1f26331a24 100644
--- a/drivers/ide/ide-tape.c
+++ b/drivers/ide/ide-tape.c
@@ -72,26 +72,6 @@ enum {
72#endif 72#endif
73 73
74/**************************** Tunable parameters *****************************/ 74/**************************** Tunable parameters *****************************/
75
76
77/*
78 * Pipelined mode parameters.
79 *
80 * We try to use the minimum number of stages which is enough to keep the tape
81 * constantly streaming. To accomplish that, we implement a feedback loop around
82 * the maximum number of stages:
83 *
84 * We start from MIN maximum stages (we will not even use MIN stages if we don't
85 * need them), increment it by RATE*(MAX-MIN) whenever we sense that the
86 * pipeline is empty, until we reach the optimum value or until we reach MAX.
87 *
88 * Setting the following parameter to 0 is illegal: the pipelined mode cannot be
89 * disabled (idetape_calculate_speeds() divides by tape->max_stages.)
90 */
91#define IDETAPE_MIN_PIPELINE_STAGES 1
92#define IDETAPE_MAX_PIPELINE_STAGES 400
93#define IDETAPE_INCREASE_STAGES_RATE 20
94
95/* 75/*
96 * After each failed packet command we issue a request sense command and retry 76 * After each failed packet command we issue a request sense command and retry
97 * the packet command IDETAPE_MAX_PC_RETRIES times. 77 * the packet command IDETAPE_MAX_PC_RETRIES times.
@@ -224,28 +204,17 @@ enum {
224 /* 0 When the tape position is unknown */ 204 /* 0 When the tape position is unknown */
225 IDETAPE_FLAG_ADDRESS_VALID = (1 << 1), 205 IDETAPE_FLAG_ADDRESS_VALID = (1 << 1),
226 /* Device already opened */ 206 /* Device already opened */
227 IDETAPE_FLAG_BUSY = (1 << 2), 207 IDETAPE_FLAG_BUSY = (1 << 2),
228 /* Error detected in a pipeline stage */
229 IDETAPE_FLAG_PIPELINE_ERR = (1 << 3),
230 /* Attempt to auto-detect the current user block size */ 208 /* Attempt to auto-detect the current user block size */
231 IDETAPE_FLAG_DETECT_BS = (1 << 4), 209 IDETAPE_FLAG_DETECT_BS = (1 << 3),
232 /* Currently on a filemark */ 210 /* Currently on a filemark */
233 IDETAPE_FLAG_FILEMARK = (1 << 5), 211 IDETAPE_FLAG_FILEMARK = (1 << 4),
234 /* DRQ interrupt device */ 212 /* DRQ interrupt device */
235 IDETAPE_FLAG_DRQ_INTERRUPT = (1 << 6), 213 IDETAPE_FLAG_DRQ_INTERRUPT = (1 << 5),
236 /* pipeline active */
237 IDETAPE_FLAG_PIPELINE_ACTIVE = (1 << 7),
238 /* 0 = no tape is loaded, so we don't rewind after ejecting */ 214 /* 0 = no tape is loaded, so we don't rewind after ejecting */
239 IDETAPE_FLAG_MEDIUM_PRESENT = (1 << 8), 215 IDETAPE_FLAG_MEDIUM_PRESENT = (1 << 6),
240}; 216};
241 217
242/* A pipeline stage. */
243typedef struct idetape_stage_s {
244 struct request rq; /* The corresponding request */
245 struct idetape_bh *bh; /* The data buffers */
246 struct idetape_stage_s *next; /* Pointer to the next stage */
247} idetape_stage_t;
248
249/* 218/*
250 * Most of our global data which we need to save even as we leave the driver due 219 * Most of our global data which we need to save even as we leave the driver due
251 * to an interrupt or a timer event is stored in the struct defined below. 220 * to an interrupt or a timer event is stored in the struct defined below.
@@ -289,9 +258,7 @@ typedef struct ide_tape_obj {
289 * While polling for DSC we use postponed_rq to postpone the current 258 * While polling for DSC we use postponed_rq to postpone the current
290 * request so that ide.c will be able to service pending requests on the 259 * request so that ide.c will be able to service pending requests on the
291 * other device. Note that at most we will have only one DSC (usually 260 * other device. Note that at most we will have only one DSC (usually
292 * data transfer) request in the device request queue. Additional 261 * data transfer) request in the device request queue.
293 * requests can be queued in our internal pipeline, but they will be
294 * visible to ide.c only one at a time.
295 */ 262 */
296 struct request *postponed_rq; 263 struct request *postponed_rq;
297 /* The time in which we started polling for DSC */ 264 /* The time in which we started polling for DSC */
@@ -331,43 +298,20 @@ typedef struct ide_tape_obj {
331 * At most, there is only one ide-tape originated data transfer request 298 * At most, there is only one ide-tape originated data transfer request
332 * in the device request queue. This allows ide.c to easily service 299 * in the device request queue. This allows ide.c to easily service
333 * requests from the other device when we postpone our active request. 300 * requests from the other device when we postpone our active request.
334 * In the pipelined operation mode, we use our internal pipeline
335 * structure to hold more data requests. The data buffer size is chosen
336 * based on the tape's recommendation.
337 */ 301 */
338 /* ptr to the request which is waiting in the device request queue */ 302
339 struct request *active_data_rq;
340 /* Data buffer size chosen based on the tape's recommendation */ 303 /* Data buffer size chosen based on the tape's recommendation */
341 int stage_size; 304 int buffer_size;
342 idetape_stage_t *merge_stage; 305 /* merge buffer */
343 int merge_stage_size; 306 struct idetape_bh *merge_bh;
307 /* size of the merge buffer */
308 int merge_bh_size;
309 /* pointer to current buffer head within the merge buffer */
344 struct idetape_bh *bh; 310 struct idetape_bh *bh;
345 char *b_data; 311 char *b_data;
346 int b_count; 312 int b_count;
347 313
348 /* 314 int pages_per_buffer;
349 * Pipeline parameters.
350 *
351 * To accomplish non-pipelined mode, we simply set the following
352 * variables to zero (or NULL, where appropriate).
353 */
354 /* Number of currently used stages */
355 int nr_stages;
356 /* Number of pending stages */
357 int nr_pending_stages;
358 /* We will not allocate more than this number of stages */
359 int max_stages, min_pipeline, max_pipeline;
360 /* The first stage which will be removed from the pipeline */
361 idetape_stage_t *first_stage;
362 /* The currently active stage */
363 idetape_stage_t *active_stage;
364 /* Will be serviced after the currently active request */
365 idetape_stage_t *next_stage;
366 /* New requests will be added to the pipeline here */
367 idetape_stage_t *last_stage;
368 /* Optional free stage which we can use */
369 idetape_stage_t *cache_stage;
370 int pages_per_stage;
371 /* Wasted space in each stage */ 315 /* Wasted space in each stage */
372 int excess_bh_size; 316 int excess_bh_size;
373 317
@@ -388,45 +332,6 @@ typedef struct ide_tape_obj {
388 /* the tape is write protected (hardware or opened as read-only) */ 332 /* the tape is write protected (hardware or opened as read-only) */
389 char write_prot; 333 char write_prot;
390 334
391 /*
392 * Limit the number of times a request can be postponed, to avoid an
393 * infinite postpone deadlock.
394 */
395 int postpone_cnt;
396
397 /*
398 * Measures number of frames:
399 *
400 * 1. written/read to/from the driver pipeline (pipeline_head).
401 * 2. written/read to/from the tape buffers (idetape_bh).
402 * 3. written/read by the tape to/from the media (tape_head).
403 */
404 int pipeline_head;
405 int buffer_head;
406 int tape_head;
407 int last_tape_head;
408
409 /* Speed control at the tape buffers input/output */
410 unsigned long insert_time;
411 int insert_size;
412 int insert_speed;
413 int max_insert_speed;
414 int measure_insert_time;
415
416 /* Speed regulation negative feedback loop */
417 int speed_control;
418 int pipeline_head_speed;
419 int controlled_pipeline_head_speed;
420 int uncontrolled_pipeline_head_speed;
421 int controlled_last_pipeline_head;
422 unsigned long uncontrolled_pipeline_head_time;
423 unsigned long controlled_pipeline_head_time;
424 int controlled_previous_pipeline_head;
425 int uncontrolled_previous_pipeline_head;
426 unsigned long controlled_previous_head_time;
427 unsigned long uncontrolled_previous_head_time;
428 int restart_speed_control_req;
429
430 u32 debug_mask; 335 u32 debug_mask;
431} idetape_tape_t; 336} idetape_tape_t;
432 337
@@ -490,13 +395,13 @@ static void idetape_input_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
490 if (bh == NULL) { 395 if (bh == NULL) {
491 printk(KERN_ERR "ide-tape: bh == NULL in " 396 printk(KERN_ERR "ide-tape: bh == NULL in "
492 "idetape_input_buffers\n"); 397 "idetape_input_buffers\n");
493 ide_atapi_discard_data(drive, bcount); 398 ide_pad_transfer(drive, 0, bcount);
494 return; 399 return;
495 } 400 }
496 count = min( 401 count = min(
497 (unsigned int)(bh->b_size - atomic_read(&bh->b_count)), 402 (unsigned int)(bh->b_size - atomic_read(&bh->b_count)),
498 bcount); 403 bcount);
499 HWIF(drive)->atapi_input_bytes(drive, bh->b_data + 404 drive->hwif->input_data(drive, NULL, bh->b_data +
500 atomic_read(&bh->b_count), count); 405 atomic_read(&bh->b_count), count);
501 bcount -= count; 406 bcount -= count;
502 atomic_add(count, &bh->b_count); 407 atomic_add(count, &bh->b_count);
@@ -522,7 +427,7 @@ static void idetape_output_buffers(ide_drive_t *drive, struct ide_atapi_pc *pc,
522 return; 427 return;
523 } 428 }
524 count = min((unsigned int)pc->b_count, (unsigned int)bcount); 429 count = min((unsigned int)pc->b_count, (unsigned int)bcount);
525 HWIF(drive)->atapi_output_bytes(drive, pc->b_data, count); 430 drive->hwif->output_data(drive, NULL, pc->b_data, count);
526 bcount -= count; 431 bcount -= count;
527 pc->b_data += count; 432 pc->b_data += count;
528 pc->b_count -= count; 433 pc->b_count -= count;
@@ -674,128 +579,36 @@ static void idetape_analyze_error(ide_drive_t *drive, u8 *sense)
674 } 579 }
675} 580}
676 581
677static void idetape_activate_next_stage(ide_drive_t *drive) 582/* Free data buffers completely. */
583static void ide_tape_kfree_buffer(idetape_tape_t *tape)
678{ 584{
679 idetape_tape_t *tape = drive->driver_data; 585 struct idetape_bh *prev_bh, *bh = tape->merge_bh;
680 idetape_stage_t *stage = tape->next_stage;
681 struct request *rq = &stage->rq;
682 586
683 debug_log(DBG_PROCS, "Enter %s\n", __func__); 587 while (bh) {
588 u32 size = bh->b_size;
684 589
685 if (stage == NULL) { 590 while (size) {
686 printk(KERN_ERR "ide-tape: bug: Trying to activate a non" 591 unsigned int order = fls(size >> PAGE_SHIFT)-1;
687 " existing stage\n");
688 return;
689 }
690 592
691 rq->rq_disk = tape->disk; 593 if (bh->b_data)
692 rq->buffer = NULL; 594 free_pages((unsigned long)bh->b_data, order);
693 rq->special = (void *)stage->bh; 595
694 tape->active_data_rq = rq; 596 size &= (order-1);
695 tape->active_stage = stage; 597 bh->b_data += (1 << order) * PAGE_SIZE;
696 tape->next_stage = stage->next;
697}
698
699/* Free a stage along with its related buffers completely. */
700static void __idetape_kfree_stage(idetape_stage_t *stage)
701{
702 struct idetape_bh *prev_bh, *bh = stage->bh;
703 int size;
704
705 while (bh != NULL) {
706 if (bh->b_data != NULL) {
707 size = (int) bh->b_size;
708 while (size > 0) {
709 free_page((unsigned long) bh->b_data);
710 size -= PAGE_SIZE;
711 bh->b_data += PAGE_SIZE;
712 }
713 } 598 }
714 prev_bh = bh; 599 prev_bh = bh;
715 bh = bh->b_reqnext; 600 bh = bh->b_reqnext;
716 kfree(prev_bh); 601 kfree(prev_bh);
717 } 602 }
718 kfree(stage); 603 kfree(tape->merge_bh);
719}
720
721static void idetape_kfree_stage(idetape_tape_t *tape, idetape_stage_t *stage)
722{
723 __idetape_kfree_stage(stage);
724}
725
726/*
727 * Remove tape->first_stage from the pipeline. The caller should avoid race
728 * conditions.
729 */
730static void idetape_remove_stage_head(ide_drive_t *drive)
731{
732 idetape_tape_t *tape = drive->driver_data;
733 idetape_stage_t *stage;
734
735 debug_log(DBG_PROCS, "Enter %s\n", __func__);
736
737 if (tape->first_stage == NULL) {
738 printk(KERN_ERR "ide-tape: bug: tape->first_stage is NULL\n");
739 return;
740 }
741 if (tape->active_stage == tape->first_stage) {
742 printk(KERN_ERR "ide-tape: bug: Trying to free our active "
743 "pipeline stage\n");
744 return;
745 }
746 stage = tape->first_stage;
747 tape->first_stage = stage->next;
748 idetape_kfree_stage(tape, stage);
749 tape->nr_stages--;
750 if (tape->first_stage == NULL) {
751 tape->last_stage = NULL;
752 if (tape->next_stage != NULL)
753 printk(KERN_ERR "ide-tape: bug: tape->next_stage !="
754 " NULL\n");
755 if (tape->nr_stages)
756 printk(KERN_ERR "ide-tape: bug: nr_stages should be 0 "
757 "now\n");
758 }
759} 604}
760 605
761/*
762 * This will free all the pipeline stages starting from new_last_stage->next
763 * to the end of the list, and point tape->last_stage to new_last_stage.
764 */
765static void idetape_abort_pipeline(ide_drive_t *drive,
766 idetape_stage_t *new_last_stage)
767{
768 idetape_tape_t *tape = drive->driver_data;
769 idetape_stage_t *stage = new_last_stage->next;
770 idetape_stage_t *nstage;
771
772 debug_log(DBG_PROCS, "%s: Enter %s\n", tape->name, __func__);
773
774 while (stage) {
775 nstage = stage->next;
776 idetape_kfree_stage(tape, stage);
777 --tape->nr_stages;
778 --tape->nr_pending_stages;
779 stage = nstage;
780 }
781 if (new_last_stage)
782 new_last_stage->next = NULL;
783 tape->last_stage = new_last_stage;
784 tape->next_stage = NULL;
785}
786
787/*
788 * Finish servicing a request and insert a pending pipeline request into the
789 * main device queue.
790 */
791static int idetape_end_request(ide_drive_t *drive, int uptodate, int nr_sects) 606static int idetape_end_request(ide_drive_t *drive, int uptodate, int nr_sects)
792{ 607{
793 struct request *rq = HWGROUP(drive)->rq; 608 struct request *rq = HWGROUP(drive)->rq;
794 idetape_tape_t *tape = drive->driver_data; 609 idetape_tape_t *tape = drive->driver_data;
795 unsigned long flags; 610 unsigned long flags;
796 int error; 611 int error;
797 int remove_stage = 0;
798 idetape_stage_t *active_stage;
799 612
800 debug_log(DBG_PROCS, "Enter %s\n", __func__); 613 debug_log(DBG_PROCS, "Enter %s\n", __func__);
801 614
@@ -815,58 +628,8 @@ static int idetape_end_request(ide_drive_t *drive, int uptodate, int nr_sects)
815 628
816 spin_lock_irqsave(&tape->lock, flags); 629 spin_lock_irqsave(&tape->lock, flags);
817 630
818 /* The request was a pipelined data transfer request */
819 if (tape->active_data_rq == rq) {
820 active_stage = tape->active_stage;
821 tape->active_stage = NULL;
822 tape->active_data_rq = NULL;
823 tape->nr_pending_stages--;
824 if (rq->cmd[0] & REQ_IDETAPE_WRITE) {
825 remove_stage = 1;
826 if (error) {
827 set_bit(IDETAPE_FLAG_PIPELINE_ERR,
828 &tape->flags);
829 if (error == IDETAPE_ERROR_EOD)
830 idetape_abort_pipeline(drive,
831 active_stage);
832 }
833 } else if (rq->cmd[0] & REQ_IDETAPE_READ) {
834 if (error == IDETAPE_ERROR_EOD) {
835 set_bit(IDETAPE_FLAG_PIPELINE_ERR,
836 &tape->flags);
837 idetape_abort_pipeline(drive, active_stage);
838 }
839 }
840 if (tape->next_stage != NULL) {
841 idetape_activate_next_stage(drive);
842
843 /* Insert the next request into the request queue. */
844 (void)ide_do_drive_cmd(drive, tape->active_data_rq,
845 ide_end);
846 } else if (!error) {
847 /*
848 * This is a part of the feedback loop which tries to
849 * find the optimum number of stages. We are starting
850 * from a minimum maximum number of stages, and if we
851 * sense that the pipeline is empty, we try to increase
852 * it, until we reach the user compile time memory
853 * limit.
854 */
855 int i = (tape->max_pipeline - tape->min_pipeline) / 10;
856
857 tape->max_stages += max(i, 1);
858 tape->max_stages = max(tape->max_stages,
859 tape->min_pipeline);
860 tape->max_stages = min(tape->max_stages,
861 tape->max_pipeline);
862 }
863 }
864 ide_end_drive_cmd(drive, 0, 0); 631 ide_end_drive_cmd(drive, 0, 0);
865 632
866 if (remove_stage)
867 idetape_remove_stage_head(drive);
868 if (tape->active_data_rq == NULL)
869 clear_bit(IDETAPE_FLAG_PIPELINE_ACTIVE, &tape->flags);
870 spin_unlock_irqrestore(&tape->lock, flags); 633 spin_unlock_irqrestore(&tape->lock, flags);
871 return 0; 634 return 0;
872} 635}
@@ -899,7 +662,7 @@ static void idetape_create_request_sense_cmd(struct ide_atapi_pc *pc)
899 662
900static void idetape_init_rq(struct request *rq, u8 cmd) 663static void idetape_init_rq(struct request *rq, u8 cmd)
901{ 664{
902 memset(rq, 0, sizeof(*rq)); 665 blk_rq_init(NULL, rq);
903 rq->cmd_type = REQ_TYPE_SPECIAL; 666 rq->cmd_type = REQ_TYPE_SPECIAL;
904 rq->cmd[0] = cmd; 667 rq->cmd[0] = cmd;
905} 668}
@@ -1083,10 +846,10 @@ static ide_startstop_t idetape_pc_intr(ide_drive_t *drive)
1083 return ide_do_reset(drive); 846 return ide_do_reset(drive);
1084 } 847 }
1085 /* Get the number of bytes to transfer on this interrupt. */ 848 /* Get the number of bytes to transfer on this interrupt. */
1086 bcount = (hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]) << 8) | 849 bcount = (hwif->INB(hwif->io_ports.lbah_addr) << 8) |
1087 hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]); 850 hwif->INB(hwif->io_ports.lbam_addr);
1088 851
1089 ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 852 ireason = hwif->INB(hwif->io_ports.nsect_addr);
1090 853
1091 if (ireason & CD) { 854 if (ireason & CD) {
1092 printk(KERN_ERR "ide-tape: CoD != 0 in %s\n", __func__); 855 printk(KERN_ERR "ide-tape: CoD != 0 in %s\n", __func__);
@@ -1108,7 +871,7 @@ static ide_startstop_t idetape_pc_intr(ide_drive_t *drive)
1108 printk(KERN_ERR "ide-tape: The tape wants to " 871 printk(KERN_ERR "ide-tape: The tape wants to "
1109 "send us more data than expected " 872 "send us more data than expected "
1110 "- discarding data\n"); 873 "- discarding data\n");
1111 ide_atapi_discard_data(drive, bcount); 874 ide_pad_transfer(drive, 0, bcount);
1112 ide_set_handler(drive, &idetape_pc_intr, 875 ide_set_handler(drive, &idetape_pc_intr,
1113 IDETAPE_WAIT_CMD, NULL); 876 IDETAPE_WAIT_CMD, NULL);
1114 return ide_started; 877 return ide_started;
@@ -1117,16 +880,16 @@ static ide_startstop_t idetape_pc_intr(ide_drive_t *drive)
1117 "data than expected - allowing transfer\n"); 880 "data than expected - allowing transfer\n");
1118 } 881 }
1119 iobuf = &idetape_input_buffers; 882 iobuf = &idetape_input_buffers;
1120 xferfunc = hwif->atapi_input_bytes; 883 xferfunc = hwif->input_data;
1121 } else { 884 } else {
1122 iobuf = &idetape_output_buffers; 885 iobuf = &idetape_output_buffers;
1123 xferfunc = hwif->atapi_output_bytes; 886 xferfunc = hwif->output_data;
1124 } 887 }
1125 888
1126 if (pc->bh) 889 if (pc->bh)
1127 iobuf(drive, pc, bcount); 890 iobuf(drive, pc, bcount);
1128 else 891 else
1129 xferfunc(drive, pc->cur_pos, bcount); 892 xferfunc(drive, NULL, pc->cur_pos, bcount);
1130 893
1131 /* Update the current position */ 894 /* Update the current position */
1132 pc->xferred += bcount; 895 pc->xferred += bcount;
@@ -1190,12 +953,12 @@ static ide_startstop_t idetape_transfer_pc(ide_drive_t *drive)
1190 "yet DRQ isn't asserted\n"); 953 "yet DRQ isn't asserted\n");
1191 return startstop; 954 return startstop;
1192 } 955 }
1193 ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 956 ireason = hwif->INB(hwif->io_ports.nsect_addr);
1194 while (retries-- && ((ireason & CD) == 0 || (ireason & IO))) { 957 while (retries-- && ((ireason & CD) == 0 || (ireason & IO))) {
1195 printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while issuing " 958 printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while issuing "
1196 "a packet command, retrying\n"); 959 "a packet command, retrying\n");
1197 udelay(100); 960 udelay(100);
1198 ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]); 961 ireason = hwif->INB(hwif->io_ports.nsect_addr);
1199 if (retries == 0) { 962 if (retries == 0) {
1200 printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while " 963 printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while "
1201 "issuing a packet command, ignoring\n"); 964 "issuing a packet command, ignoring\n");
@@ -1216,7 +979,8 @@ static ide_startstop_t idetape_transfer_pc(ide_drive_t *drive)
1216 hwif->dma_ops->dma_start(drive); 979 hwif->dma_ops->dma_start(drive);
1217#endif 980#endif
1218 /* Send the actual packet */ 981 /* Send the actual packet */
1219 HWIF(drive)->atapi_output_bytes(drive, pc->c, 12); 982 hwif->output_data(drive, NULL, pc->c, 12);
983
1220 return ide_started; 984 return ide_started;
1221} 985}
1222 986
@@ -1292,7 +1056,7 @@ static ide_startstop_t idetape_issue_pc(ide_drive_t *drive,
1292 IDETAPE_WAIT_CMD, NULL); 1056 IDETAPE_WAIT_CMD, NULL);
1293 return ide_started; 1057 return ide_started;
1294 } else { 1058 } else {
1295 hwif->OUTB(WIN_PACKETCMD, hwif->io_ports[IDE_COMMAND_OFFSET]); 1059 ide_execute_pkt_cmd(drive);
1296 return idetape_transfer_pc(drive); 1060 return idetape_transfer_pc(drive);
1297 } 1061 }
1298} 1062}
@@ -1335,69 +1099,6 @@ static void idetape_create_mode_sense_cmd(struct ide_atapi_pc *pc, u8 page_code)
1335 pc->idetape_callback = &idetape_pc_callback; 1099 pc->idetape_callback = &idetape_pc_callback;
1336} 1100}
1337 1101
1338static void idetape_calculate_speeds(ide_drive_t *drive)
1339{
1340 idetape_tape_t *tape = drive->driver_data;
1341
1342 if (time_after(jiffies,
1343 tape->controlled_pipeline_head_time + 120 * HZ)) {
1344 tape->controlled_previous_pipeline_head =
1345 tape->controlled_last_pipeline_head;
1346 tape->controlled_previous_head_time =
1347 tape->controlled_pipeline_head_time;
1348 tape->controlled_last_pipeline_head = tape->pipeline_head;
1349 tape->controlled_pipeline_head_time = jiffies;
1350 }
1351 if (time_after(jiffies, tape->controlled_pipeline_head_time + 60 * HZ))
1352 tape->controlled_pipeline_head_speed = (tape->pipeline_head -
1353 tape->controlled_last_pipeline_head) * 32 * HZ /
1354 (jiffies - tape->controlled_pipeline_head_time);
1355 else if (time_after(jiffies, tape->controlled_previous_head_time))
1356 tape->controlled_pipeline_head_speed = (tape->pipeline_head -
1357 tape->controlled_previous_pipeline_head) * 32 *
1358 HZ / (jiffies - tape->controlled_previous_head_time);
1359
1360 if (tape->nr_pending_stages < tape->max_stages/*- 1 */) {
1361 /* -1 for read mode error recovery */
1362 if (time_after(jiffies, tape->uncontrolled_previous_head_time +
1363 10 * HZ)) {
1364 tape->uncontrolled_pipeline_head_time = jiffies;
1365 tape->uncontrolled_pipeline_head_speed =
1366 (tape->pipeline_head -
1367 tape->uncontrolled_previous_pipeline_head) *
1368 32 * HZ / (jiffies -
1369 tape->uncontrolled_previous_head_time);
1370 }
1371 } else {
1372 tape->uncontrolled_previous_head_time = jiffies;
1373 tape->uncontrolled_previous_pipeline_head = tape->pipeline_head;
1374 if (time_after(jiffies, tape->uncontrolled_pipeline_head_time +
1375 30 * HZ))
1376 tape->uncontrolled_pipeline_head_time = jiffies;
1377
1378 }
1379 tape->pipeline_head_speed = max(tape->uncontrolled_pipeline_head_speed,
1380 tape->controlled_pipeline_head_speed);
1381
1382 if (tape->speed_control == 1) {
1383 if (tape->nr_pending_stages >= tape->max_stages / 2)
1384 tape->max_insert_speed = tape->pipeline_head_speed +
1385 (1100 - tape->pipeline_head_speed) * 2 *
1386 (tape->nr_pending_stages - tape->max_stages / 2)
1387 / tape->max_stages;
1388 else
1389 tape->max_insert_speed = 500 +
1390 (tape->pipeline_head_speed - 500) * 2 *
1391 tape->nr_pending_stages / tape->max_stages;
1392
1393 if (tape->nr_pending_stages >= tape->max_stages * 99 / 100)
1394 tape->max_insert_speed = 5000;
1395 } else
1396 tape->max_insert_speed = tape->speed_control;
1397
1398 tape->max_insert_speed = max(tape->max_insert_speed, 500);
1399}
1400
1401static ide_startstop_t idetape_media_access_finished(ide_drive_t *drive) 1102static ide_startstop_t idetape_media_access_finished(ide_drive_t *drive)
1402{ 1103{
1403 idetape_tape_t *tape = drive->driver_data; 1104 idetape_tape_t *tape = drive->driver_data;
@@ -1432,17 +1133,7 @@ static ide_startstop_t idetape_rw_callback(ide_drive_t *drive)
1432 int blocks = tape->pc->xferred / tape->blk_size; 1133 int blocks = tape->pc->xferred / tape->blk_size;
1433 1134
1434 tape->avg_size += blocks * tape->blk_size; 1135 tape->avg_size += blocks * tape->blk_size;
1435 tape->insert_size += blocks * tape->blk_size; 1136
1436 if (tape->insert_size > 1024 * 1024)
1437 tape->measure_insert_time = 1;
1438 if (tape->measure_insert_time) {
1439 tape->measure_insert_time = 0;
1440 tape->insert_time = jiffies;
1441 tape->insert_size = 0;
1442 }
1443 if (time_after(jiffies, tape->insert_time))
1444 tape->insert_speed = tape->insert_size / 1024 * HZ /
1445 (jiffies - tape->insert_time);
1446 if (time_after_eq(jiffies, tape->avg_time + HZ)) { 1137 if (time_after_eq(jiffies, tape->avg_time + HZ)) {
1447 tape->avg_speed = tape->avg_size * HZ / 1138 tape->avg_speed = tape->avg_size * HZ /
1448 (jiffies - tape->avg_time) / 1024; 1139 (jiffies - tape->avg_time) / 1024;
@@ -1475,7 +1166,7 @@ static void idetape_create_read_cmd(idetape_tape_t *tape,
1475 pc->buf = NULL; 1166 pc->buf = NULL;
1476 pc->buf_size = length * tape->blk_size; 1167 pc->buf_size = length * tape->blk_size;
1477 pc->req_xfer = pc->buf_size; 1168 pc->req_xfer = pc->buf_size;
1478 if (pc->req_xfer == tape->stage_size) 1169 if (pc->req_xfer == tape->buffer_size)
1479 pc->flags |= PC_FLAG_DMA_RECOMMENDED; 1170 pc->flags |= PC_FLAG_DMA_RECOMMENDED;
1480} 1171}
1481 1172
@@ -1495,7 +1186,7 @@ static void idetape_create_write_cmd(idetape_tape_t *tape,
1495 pc->buf = NULL; 1186 pc->buf = NULL;
1496 pc->buf_size = length * tape->blk_size; 1187 pc->buf_size = length * tape->blk_size;
1497 pc->req_xfer = pc->buf_size; 1188 pc->req_xfer = pc->buf_size;
1498 if (pc->req_xfer == tape->stage_size) 1189 if (pc->req_xfer == tape->buffer_size)
1499 pc->flags |= PC_FLAG_DMA_RECOMMENDED; 1190 pc->flags |= PC_FLAG_DMA_RECOMMENDED;
1500} 1191}
1501 1192
@@ -1547,10 +1238,6 @@ static ide_startstop_t idetape_do_request(ide_drive_t *drive,
1547 drive->post_reset = 0; 1238 drive->post_reset = 0;
1548 } 1239 }
1549 1240
1550 if (time_after(jiffies, tape->insert_time))
1551 tape->insert_speed = tape->insert_size / 1024 * HZ /
1552 (jiffies - tape->insert_time);
1553 idetape_calculate_speeds(drive);
1554 if (!test_and_clear_bit(IDETAPE_FLAG_IGNORE_DSC, &tape->flags) && 1241 if (!test_and_clear_bit(IDETAPE_FLAG_IGNORE_DSC, &tape->flags) &&
1555 (stat & SEEK_STAT) == 0) { 1242 (stat & SEEK_STAT) == 0) {
1556 if (postponed_rq == NULL) { 1243 if (postponed_rq == NULL) {
@@ -1574,16 +1261,12 @@ static ide_startstop_t idetape_do_request(ide_drive_t *drive,
1574 return ide_stopped; 1261 return ide_stopped;
1575 } 1262 }
1576 if (rq->cmd[0] & REQ_IDETAPE_READ) { 1263 if (rq->cmd[0] & REQ_IDETAPE_READ) {
1577 tape->buffer_head++;
1578 tape->postpone_cnt = 0;
1579 pc = idetape_next_pc_storage(drive); 1264 pc = idetape_next_pc_storage(drive);
1580 idetape_create_read_cmd(tape, pc, rq->current_nr_sectors, 1265 idetape_create_read_cmd(tape, pc, rq->current_nr_sectors,
1581 (struct idetape_bh *)rq->special); 1266 (struct idetape_bh *)rq->special);
1582 goto out; 1267 goto out;
1583 } 1268 }
1584 if (rq->cmd[0] & REQ_IDETAPE_WRITE) { 1269 if (rq->cmd[0] & REQ_IDETAPE_WRITE) {
1585 tape->buffer_head++;
1586 tape->postpone_cnt = 0;
1587 pc = idetape_next_pc_storage(drive); 1270 pc = idetape_next_pc_storage(drive);
1588 idetape_create_write_cmd(tape, pc, rq->current_nr_sectors, 1271 idetape_create_write_cmd(tape, pc, rq->current_nr_sectors,
1589 (struct idetape_bh *)rq->special); 1272 (struct idetape_bh *)rq->special);
@@ -1604,103 +1287,91 @@ out:
1604 return idetape_issue_pc(drive, pc); 1287 return idetape_issue_pc(drive, pc);
1605} 1288}
1606 1289
1607/* Pipeline related functions */
1608
1609/* 1290/*
1610 * The function below uses __get_free_page to allocate a pipeline stage, along 1291 * The function below uses __get_free_pages to allocate a data buffer of size
1611 * with all the necessary small buffers which together make a buffer of size 1292 * tape->buffer_size (or a bit more). We attempt to combine sequential pages as
1612 * tape->stage_size (or a bit more). We attempt to combine sequential pages as
1613 * much as possible. 1293 * much as possible.
1614 * 1294 *
1615 * It returns a pointer to the new allocated stage, or NULL if we can't (or 1295 * It returns a pointer to the newly allocated buffer, or NULL in case of
1616 * don't want to) allocate a stage. 1296 * failure.
1617 *
1618 * Pipeline stages are optional and are used to increase performance. If we
1619 * can't allocate them, we'll manage without them.
1620 */ 1297 */
1621static idetape_stage_t *__idetape_kmalloc_stage(idetape_tape_t *tape, int full, 1298static struct idetape_bh *ide_tape_kmalloc_buffer(idetape_tape_t *tape,
1622 int clear) 1299 int full, int clear)
1623{ 1300{
1624 idetape_stage_t *stage; 1301 struct idetape_bh *prev_bh, *bh, *merge_bh;
1625 struct idetape_bh *prev_bh, *bh; 1302 int pages = tape->pages_per_buffer;
1626 int pages = tape->pages_per_stage; 1303 unsigned int order, b_allocd;
1627 char *b_data = NULL; 1304 char *b_data = NULL;
1628 1305
1629 stage = kmalloc(sizeof(idetape_stage_t), GFP_KERNEL); 1306 merge_bh = kmalloc(sizeof(struct idetape_bh), GFP_KERNEL);
1630 if (!stage) 1307 bh = merge_bh;
1631 return NULL;
1632 stage->next = NULL;
1633
1634 stage->bh = kmalloc(sizeof(struct idetape_bh), GFP_KERNEL);
1635 bh = stage->bh;
1636 if (bh == NULL) 1308 if (bh == NULL)
1637 goto abort; 1309 goto abort;
1638 bh->b_reqnext = NULL; 1310
1639 bh->b_data = (char *) __get_free_page(GFP_KERNEL); 1311 order = fls(pages) - 1;
1312 bh->b_data = (char *) __get_free_pages(GFP_KERNEL, order);
1640 if (!bh->b_data) 1313 if (!bh->b_data)
1641 goto abort; 1314 goto abort;
1315 b_allocd = (1 << order) * PAGE_SIZE;
1316 pages &= (order-1);
1317
1642 if (clear) 1318 if (clear)
1643 memset(bh->b_data, 0, PAGE_SIZE); 1319 memset(bh->b_data, 0, b_allocd);
1644 bh->b_size = PAGE_SIZE; 1320 bh->b_reqnext = NULL;
1321 bh->b_size = b_allocd;
1645 atomic_set(&bh->b_count, full ? bh->b_size : 0); 1322 atomic_set(&bh->b_count, full ? bh->b_size : 0);
1646 1323
1647 while (--pages) { 1324 while (pages) {
1648 b_data = (char *) __get_free_page(GFP_KERNEL); 1325 order = fls(pages) - 1;
1326 b_data = (char *) __get_free_pages(GFP_KERNEL, order);
1649 if (!b_data) 1327 if (!b_data)
1650 goto abort; 1328 goto abort;
1329 b_allocd = (1 << order) * PAGE_SIZE;
1330
1651 if (clear) 1331 if (clear)
1652 memset(b_data, 0, PAGE_SIZE); 1332 memset(b_data, 0, b_allocd);
1653 if (bh->b_data == b_data + PAGE_SIZE) { 1333
1654 bh->b_size += PAGE_SIZE; 1334 /* newly allocated page frames below buffer header or ...*/
1655 bh->b_data -= PAGE_SIZE; 1335 if (bh->b_data == b_data + b_allocd) {
1336 bh->b_size += b_allocd;
1337 bh->b_data -= b_allocd;
1656 if (full) 1338 if (full)
1657 atomic_add(PAGE_SIZE, &bh->b_count); 1339 atomic_add(b_allocd, &bh->b_count);
1658 continue; 1340 continue;
1659 } 1341 }
1342 /* they are above the header */
1660 if (b_data == bh->b_data + bh->b_size) { 1343 if (b_data == bh->b_data + bh->b_size) {
1661 bh->b_size += PAGE_SIZE; 1344 bh->b_size += b_allocd;
1662 if (full) 1345 if (full)
1663 atomic_add(PAGE_SIZE, &bh->b_count); 1346 atomic_add(b_allocd, &bh->b_count);
1664 continue; 1347 continue;
1665 } 1348 }
1666 prev_bh = bh; 1349 prev_bh = bh;
1667 bh = kmalloc(sizeof(struct idetape_bh), GFP_KERNEL); 1350 bh = kmalloc(sizeof(struct idetape_bh), GFP_KERNEL);
1668 if (!bh) { 1351 if (!bh) {
1669 free_page((unsigned long) b_data); 1352 free_pages((unsigned long) b_data, order);
1670 goto abort; 1353 goto abort;
1671 } 1354 }
1672 bh->b_reqnext = NULL; 1355 bh->b_reqnext = NULL;
1673 bh->b_data = b_data; 1356 bh->b_data = b_data;
1674 bh->b_size = PAGE_SIZE; 1357 bh->b_size = b_allocd;
1675 atomic_set(&bh->b_count, full ? bh->b_size : 0); 1358 atomic_set(&bh->b_count, full ? bh->b_size : 0);
1676 prev_bh->b_reqnext = bh; 1359 prev_bh->b_reqnext = bh;
1360
1361 pages &= (order-1);
1677 } 1362 }
1363
1678 bh->b_size -= tape->excess_bh_size; 1364 bh->b_size -= tape->excess_bh_size;
1679 if (full) 1365 if (full)
1680 atomic_sub(tape->excess_bh_size, &bh->b_count); 1366 atomic_sub(tape->excess_bh_size, &bh->b_count);
1681 return stage; 1367 return merge_bh;
1682abort: 1368abort:
1683 __idetape_kfree_stage(stage); 1369 ide_tape_kfree_buffer(tape);
1684 return NULL; 1370 return NULL;
1685} 1371}
1686 1372
1687static idetape_stage_t *idetape_kmalloc_stage(idetape_tape_t *tape)
1688{
1689 idetape_stage_t *cache_stage = tape->cache_stage;
1690
1691 debug_log(DBG_PROCS, "Enter %s\n", __func__);
1692
1693 if (tape->nr_stages >= tape->max_stages)
1694 return NULL;
1695 if (cache_stage != NULL) {
1696 tape->cache_stage = NULL;
1697 return cache_stage;
1698 }
1699 return __idetape_kmalloc_stage(tape, 0, 0);
1700}
1701
1702static int idetape_copy_stage_from_user(idetape_tape_t *tape, 1373static int idetape_copy_stage_from_user(idetape_tape_t *tape,
1703 idetape_stage_t *stage, const char __user *buf, int n) 1374 const char __user *buf, int n)
1704{ 1375{
1705 struct idetape_bh *bh = tape->bh; 1376 struct idetape_bh *bh = tape->bh;
1706 int count; 1377 int count;
@@ -1732,7 +1403,7 @@ static int idetape_copy_stage_from_user(idetape_tape_t *tape,
1732} 1403}
1733 1404
1734static int idetape_copy_stage_to_user(idetape_tape_t *tape, char __user *buf, 1405static int idetape_copy_stage_to_user(idetape_tape_t *tape, char __user *buf,
1735 idetape_stage_t *stage, int n) 1406 int n)
1736{ 1407{
1737 struct idetape_bh *bh = tape->bh; 1408 struct idetape_bh *bh = tape->bh;
1738 int count; 1409 int count;
@@ -1763,11 +1434,11 @@ static int idetape_copy_stage_to_user(idetape_tape_t *tape, char __user *buf,
1763 return ret; 1434 return ret;
1764} 1435}
1765 1436
1766static void idetape_init_merge_stage(idetape_tape_t *tape) 1437static void idetape_init_merge_buffer(idetape_tape_t *tape)
1767{ 1438{
1768 struct idetape_bh *bh = tape->merge_stage->bh; 1439 struct idetape_bh *bh = tape->merge_bh;
1440 tape->bh = tape->merge_bh;
1769 1441
1770 tape->bh = bh;
1771 if (tape->chrdev_dir == IDETAPE_DIR_WRITE) 1442 if (tape->chrdev_dir == IDETAPE_DIR_WRITE)
1772 atomic_set(&bh->b_count, 0); 1443 atomic_set(&bh->b_count, 0);
1773 else { 1444 else {
@@ -1776,61 +1447,6 @@ static void idetape_init_merge_stage(idetape_tape_t *tape)
1776 } 1447 }
1777} 1448}
1778 1449
1779static void idetape_switch_buffers(idetape_tape_t *tape, idetape_stage_t *stage)
1780{
1781 struct idetape_bh *tmp;
1782
1783 tmp = stage->bh;
1784 stage->bh = tape->merge_stage->bh;
1785 tape->merge_stage->bh = tmp;
1786 idetape_init_merge_stage(tape);
1787}
1788
1789/* Add a new stage at the end of the pipeline. */
1790static void idetape_add_stage_tail(ide_drive_t *drive, idetape_stage_t *stage)
1791{
1792 idetape_tape_t *tape = drive->driver_data;
1793 unsigned long flags;
1794
1795 debug_log(DBG_PROCS, "Enter %s\n", __func__);
1796
1797 spin_lock_irqsave(&tape->lock, flags);
1798 stage->next = NULL;
1799 if (tape->last_stage != NULL)
1800 tape->last_stage->next = stage;
1801 else
1802 tape->first_stage = stage;
1803 tape->next_stage = stage;
1804 tape->last_stage = stage;
1805 if (tape->next_stage == NULL)
1806 tape->next_stage = tape->last_stage;
1807 tape->nr_stages++;
1808 tape->nr_pending_stages++;
1809 spin_unlock_irqrestore(&tape->lock, flags);
1810}
1811
1812/* Install a completion in a pending request and sleep until it is serviced. The
1813 * caller should ensure that the request will not be serviced before we install
1814 * the completion (usually by disabling interrupts).
1815 */
1816static void idetape_wait_for_request(ide_drive_t *drive, struct request *rq)
1817{
1818 DECLARE_COMPLETION_ONSTACK(wait);
1819 idetape_tape_t *tape = drive->driver_data;
1820
1821 if (rq == NULL || !blk_special_request(rq)) {
1822 printk(KERN_ERR "ide-tape: bug: Trying to sleep on non-valid"
1823 " request\n");
1824 return;
1825 }
1826 rq->end_io_data = &wait;
1827 rq->end_io = blk_end_sync_rq;
1828 spin_unlock_irq(&tape->lock);
1829 wait_for_completion(&wait);
1830 /* The stage and its struct request have been deallocated */
1831 spin_lock_irq(&tape->lock);
1832}
1833
1834static ide_startstop_t idetape_read_position_callback(ide_drive_t *drive) 1450static ide_startstop_t idetape_read_position_callback(ide_drive_t *drive)
1835{ 1451{
1836 idetape_tape_t *tape = drive->driver_data; 1452 idetape_tape_t *tape = drive->driver_data;
@@ -1899,7 +1515,7 @@ static void idetape_create_test_unit_ready_cmd(struct ide_atapi_pc *pc)
1899 * to the request list without waiting for it to be serviced! In that case, we 1515 * to the request list without waiting for it to be serviced! In that case, we
1900 * usually use idetape_queue_pc_head(). 1516 * usually use idetape_queue_pc_head().
1901 */ 1517 */
1902static int __idetape_queue_pc_tail(ide_drive_t *drive, struct ide_atapi_pc *pc) 1518static int idetape_queue_pc_tail(ide_drive_t *drive, struct ide_atapi_pc *pc)
1903{ 1519{
1904 struct ide_tape_obj *tape = drive->driver_data; 1520 struct ide_tape_obj *tape = drive->driver_data;
1905 struct request rq; 1521 struct request rq;
@@ -1931,7 +1547,7 @@ static int idetape_wait_ready(ide_drive_t *drive, unsigned long timeout)
1931 timeout += jiffies; 1547 timeout += jiffies;
1932 while (time_before(jiffies, timeout)) { 1548 while (time_before(jiffies, timeout)) {
1933 idetape_create_test_unit_ready_cmd(&pc); 1549 idetape_create_test_unit_ready_cmd(&pc);
1934 if (!__idetape_queue_pc_tail(drive, &pc)) 1550 if (!idetape_queue_pc_tail(drive, &pc))
1935 return 0; 1551 return 0;
1936 if ((tape->sense_key == 2 && tape->asc == 4 && tape->ascq == 2) 1552 if ((tape->sense_key == 2 && tape->asc == 4 && tape->ascq == 2)
1937 || (tape->asc == 0x3A)) { 1553 || (tape->asc == 0x3A)) {
@@ -1940,7 +1556,7 @@ static int idetape_wait_ready(ide_drive_t *drive, unsigned long timeout)
1940 return -ENOMEDIUM; 1556 return -ENOMEDIUM;
1941 idetape_create_load_unload_cmd(drive, &pc, 1557 idetape_create_load_unload_cmd(drive, &pc,
1942 IDETAPE_LU_LOAD_MASK); 1558 IDETAPE_LU_LOAD_MASK);
1943 __idetape_queue_pc_tail(drive, &pc); 1559 idetape_queue_pc_tail(drive, &pc);
1944 load_attempted = 1; 1560 load_attempted = 1;
1945 /* not about to be ready */ 1561 /* not about to be ready */
1946 } else if (!(tape->sense_key == 2 && tape->asc == 4 && 1562 } else if (!(tape->sense_key == 2 && tape->asc == 4 &&
@@ -1951,11 +1567,6 @@ static int idetape_wait_ready(ide_drive_t *drive, unsigned long timeout)
1951 return -EIO; 1567 return -EIO;
1952} 1568}
1953 1569
1954static int idetape_queue_pc_tail(ide_drive_t *drive, struct ide_atapi_pc *pc)
1955{
1956 return __idetape_queue_pc_tail(drive, pc);
1957}
1958
1959static int idetape_flush_tape_buffers(ide_drive_t *drive) 1570static int idetape_flush_tape_buffers(ide_drive_t *drive)
1960{ 1571{
1961 struct ide_atapi_pc pc; 1572 struct ide_atapi_pc pc;
@@ -2021,50 +1632,21 @@ static int idetape_create_prevent_cmd(ide_drive_t *drive,
2021 return 1; 1632 return 1;
2022} 1633}
2023 1634
2024static int __idetape_discard_read_pipeline(ide_drive_t *drive) 1635static void __ide_tape_discard_merge_buffer(ide_drive_t *drive)
2025{ 1636{
2026 idetape_tape_t *tape = drive->driver_data; 1637 idetape_tape_t *tape = drive->driver_data;
2027 unsigned long flags;
2028 int cnt;
2029 1638
2030 if (tape->chrdev_dir != IDETAPE_DIR_READ) 1639 if (tape->chrdev_dir != IDETAPE_DIR_READ)
2031 return 0; 1640 return;
2032 1641
2033 /* Remove merge stage. */ 1642 clear_bit(IDETAPE_FLAG_FILEMARK, &tape->flags);
2034 cnt = tape->merge_stage_size / tape->blk_size; 1643 tape->merge_bh_size = 0;
2035 if (test_and_clear_bit(IDETAPE_FLAG_FILEMARK, &tape->flags)) 1644 if (tape->merge_bh != NULL) {
2036 ++cnt; /* Filemarks count as 1 sector */ 1645 ide_tape_kfree_buffer(tape);
2037 tape->merge_stage_size = 0; 1646 tape->merge_bh = NULL;
2038 if (tape->merge_stage != NULL) {
2039 __idetape_kfree_stage(tape->merge_stage);
2040 tape->merge_stage = NULL;
2041 } 1647 }
2042 1648
2043 /* Clear pipeline flags. */
2044 clear_bit(IDETAPE_FLAG_PIPELINE_ERR, &tape->flags);
2045 tape->chrdev_dir = IDETAPE_DIR_NONE; 1649 tape->chrdev_dir = IDETAPE_DIR_NONE;
2046
2047 /* Remove pipeline stages. */
2048 if (tape->first_stage == NULL)
2049 return 0;
2050
2051 spin_lock_irqsave(&tape->lock, flags);
2052 tape->next_stage = NULL;
2053 if (test_bit(IDETAPE_FLAG_PIPELINE_ACTIVE, &tape->flags))
2054 idetape_wait_for_request(drive, tape->active_data_rq);
2055 spin_unlock_irqrestore(&tape->lock, flags);
2056
2057 while (tape->first_stage != NULL) {
2058 struct request *rq_ptr = &tape->first_stage->rq;
2059
2060 cnt += rq_ptr->nr_sectors - rq_ptr->current_nr_sectors;
2061 if (rq_ptr->errors == IDETAPE_ERROR_FILEMARK)
2062 ++cnt;
2063 idetape_remove_stage_head(drive);
2064 }
2065 tape->nr_pending_stages = 0;
2066 tape->max_stages = tape->min_pipeline;
2067 return cnt;
2068} 1650}
2069 1651
2070/* 1652/*
@@ -2081,7 +1663,7 @@ static int idetape_position_tape(ide_drive_t *drive, unsigned int block,
2081 struct ide_atapi_pc pc; 1663 struct ide_atapi_pc pc;
2082 1664
2083 if (tape->chrdev_dir == IDETAPE_DIR_READ) 1665 if (tape->chrdev_dir == IDETAPE_DIR_READ)
2084 __idetape_discard_read_pipeline(drive); 1666 __ide_tape_discard_merge_buffer(drive);
2085 idetape_wait_ready(drive, 60 * 5 * HZ); 1667 idetape_wait_ready(drive, 60 * 5 * HZ);
2086 idetape_create_locate_cmd(drive, &pc, block, partition, skip); 1668 idetape_create_locate_cmd(drive, &pc, block, partition, skip);
2087 retval = idetape_queue_pc_tail(drive, &pc); 1669 retval = idetape_queue_pc_tail(drive, &pc);
@@ -2092,20 +1674,19 @@ static int idetape_position_tape(ide_drive_t *drive, unsigned int block,
2092 return (idetape_queue_pc_tail(drive, &pc)); 1674 return (idetape_queue_pc_tail(drive, &pc));
2093} 1675}
2094 1676
2095static void idetape_discard_read_pipeline(ide_drive_t *drive, 1677static void ide_tape_discard_merge_buffer(ide_drive_t *drive,
2096 int restore_position) 1678 int restore_position)
2097{ 1679{
2098 idetape_tape_t *tape = drive->driver_data; 1680 idetape_tape_t *tape = drive->driver_data;
2099 int cnt;
2100 int seek, position; 1681 int seek, position;
2101 1682
2102 cnt = __idetape_discard_read_pipeline(drive); 1683 __ide_tape_discard_merge_buffer(drive);
2103 if (restore_position) { 1684 if (restore_position) {
2104 position = idetape_read_position(drive); 1685 position = idetape_read_position(drive);
2105 seek = position > cnt ? position - cnt : 0; 1686 seek = position > 0 ? position : 0;
2106 if (idetape_position_tape(drive, seek, 0, 0)) { 1687 if (idetape_position_tape(drive, seek, 0, 0)) {
2107 printk(KERN_INFO "ide-tape: %s: position_tape failed in" 1688 printk(KERN_INFO "ide-tape: %s: position_tape failed in"
2108 " discard_pipeline()\n", tape->name); 1689 " %s\n", tape->name, __func__);
2109 return; 1690 return;
2110 } 1691 }
2111 } 1692 }
@@ -2123,12 +1704,6 @@ static int idetape_queue_rw_tail(ide_drive_t *drive, int cmd, int blocks,
2123 1704
2124 debug_log(DBG_SENSE, "%s: cmd=%d\n", __func__, cmd); 1705 debug_log(DBG_SENSE, "%s: cmd=%d\n", __func__, cmd);
2125 1706
2126 if (test_bit(IDETAPE_FLAG_PIPELINE_ACTIVE, &tape->flags)) {
2127 printk(KERN_ERR "ide-tape: bug: the pipeline is active in %s\n",
2128 __func__);
2129 return (0);
2130 }
2131
2132 idetape_init_rq(&rq, cmd); 1707 idetape_init_rq(&rq, cmd);
2133 rq.rq_disk = tape->disk; 1708 rq.rq_disk = tape->disk;
2134 rq.special = (void *)bh; 1709 rq.special = (void *)bh;
@@ -2140,26 +1715,13 @@ static int idetape_queue_rw_tail(ide_drive_t *drive, int cmd, int blocks,
2140 if ((cmd & (REQ_IDETAPE_READ | REQ_IDETAPE_WRITE)) == 0) 1715 if ((cmd & (REQ_IDETAPE_READ | REQ_IDETAPE_WRITE)) == 0)
2141 return 0; 1716 return 0;
2142 1717
2143 if (tape->merge_stage) 1718 if (tape->merge_bh)
2144 idetape_init_merge_stage(tape); 1719 idetape_init_merge_buffer(tape);
2145 if (rq.errors == IDETAPE_ERROR_GENERAL) 1720 if (rq.errors == IDETAPE_ERROR_GENERAL)
2146 return -EIO; 1721 return -EIO;
2147 return (tape->blk_size * (blocks-rq.current_nr_sectors)); 1722 return (tape->blk_size * (blocks-rq.current_nr_sectors));
2148} 1723}
2149 1724
2150/* start servicing the pipeline stages, starting from tape->next_stage. */
2151static void idetape_plug_pipeline(ide_drive_t *drive)
2152{
2153 idetape_tape_t *tape = drive->driver_data;
2154
2155 if (tape->next_stage == NULL)
2156 return;
2157 if (!test_and_set_bit(IDETAPE_FLAG_PIPELINE_ACTIVE, &tape->flags)) {
2158 idetape_activate_next_stage(drive);
2159 (void) ide_do_drive_cmd(drive, tape->active_data_rq, ide_end);
2160 }
2161}
2162
2163static void idetape_create_inquiry_cmd(struct ide_atapi_pc *pc) 1725static void idetape_create_inquiry_cmd(struct ide_atapi_pc *pc)
2164{ 1726{
2165 idetape_init_pc(pc); 1727 idetape_init_pc(pc);
@@ -2197,137 +1759,39 @@ static void idetape_create_space_cmd(struct ide_atapi_pc *pc, int count, u8 cmd)
2197 pc->idetape_callback = &idetape_pc_callback; 1759 pc->idetape_callback = &idetape_pc_callback;
2198} 1760}
2199 1761
2200static void idetape_wait_first_stage(ide_drive_t *drive) 1762/* Queue up a character device originated write request. */
2201{
2202 idetape_tape_t *tape = drive->driver_data;
2203 unsigned long flags;
2204
2205 if (tape->first_stage == NULL)
2206 return;
2207 spin_lock_irqsave(&tape->lock, flags);
2208 if (tape->active_stage == tape->first_stage)
2209 idetape_wait_for_request(drive, tape->active_data_rq);
2210 spin_unlock_irqrestore(&tape->lock, flags);
2211}
2212
2213/*
2214 * Try to add a character device originated write request to our pipeline. In
2215 * case we don't succeed, we revert to non-pipelined operation mode for this
2216 * request. In order to accomplish that, we
2217 *
2218 * 1. Try to allocate a new pipeline stage.
2219 * 2. If we can't, wait for more and more requests to be serviced and try again
2220 * each time.
2221 * 3. If we still can't allocate a stage, fallback to non-pipelined operation
2222 * mode for this request.
2223 */
2224static int idetape_add_chrdev_write_request(ide_drive_t *drive, int blocks) 1763static int idetape_add_chrdev_write_request(ide_drive_t *drive, int blocks)
2225{ 1764{
2226 idetape_tape_t *tape = drive->driver_data; 1765 idetape_tape_t *tape = drive->driver_data;
2227 idetape_stage_t *new_stage;
2228 unsigned long flags;
2229 struct request *rq;
2230 1766
2231 debug_log(DBG_CHRDEV, "Enter %s\n", __func__); 1767 debug_log(DBG_CHRDEV, "Enter %s\n", __func__);
2232 1768
2233 /* Attempt to allocate a new stage. Beware possible race conditions. */ 1769 return idetape_queue_rw_tail(drive, REQ_IDETAPE_WRITE,
2234 while ((new_stage = idetape_kmalloc_stage(tape)) == NULL) { 1770 blocks, tape->merge_bh);
2235 spin_lock_irqsave(&tape->lock, flags);
2236 if (test_bit(IDETAPE_FLAG_PIPELINE_ACTIVE, &tape->flags)) {
2237 idetape_wait_for_request(drive, tape->active_data_rq);
2238 spin_unlock_irqrestore(&tape->lock, flags);
2239 } else {
2240 spin_unlock_irqrestore(&tape->lock, flags);
2241 idetape_plug_pipeline(drive);
2242 if (test_bit(IDETAPE_FLAG_PIPELINE_ACTIVE,
2243 &tape->flags))
2244 continue;
2245 /*
2246 * The machine is short on memory. Fallback to non-
2247 * pipelined operation mode for this request.
2248 */
2249 return idetape_queue_rw_tail(drive, REQ_IDETAPE_WRITE,
2250 blocks, tape->merge_stage->bh);
2251 }
2252 }
2253 rq = &new_stage->rq;
2254 idetape_init_rq(rq, REQ_IDETAPE_WRITE);
2255 /* Doesn't actually matter - We always assume sequential access */
2256 rq->sector = tape->first_frame;
2257 rq->current_nr_sectors = blocks;
2258 rq->nr_sectors = blocks;
2259
2260 idetape_switch_buffers(tape, new_stage);
2261 idetape_add_stage_tail(drive, new_stage);
2262 tape->pipeline_head++;
2263 idetape_calculate_speeds(drive);
2264
2265 /*
2266 * Estimate whether the tape has stopped writing by checking if our
2267 * write pipeline is currently empty. If we are not writing anymore,
2268 * wait for the pipeline to be almost completely full (90%) before
2269 * starting to service requests, so that we will be able to keep up with
2270 * the higher speeds of the tape.
2271 */
2272 if (!test_bit(IDETAPE_FLAG_PIPELINE_ACTIVE, &tape->flags)) {
2273 if (tape->nr_stages >= tape->max_stages * 9 / 10 ||
2274 tape->nr_stages >= tape->max_stages -
2275 tape->uncontrolled_pipeline_head_speed * 3 * 1024 /
2276 tape->blk_size) {
2277 tape->measure_insert_time = 1;
2278 tape->insert_time = jiffies;
2279 tape->insert_size = 0;
2280 tape->insert_speed = 0;
2281 idetape_plug_pipeline(drive);
2282 }
2283 }
2284 if (test_and_clear_bit(IDETAPE_FLAG_PIPELINE_ERR, &tape->flags))
2285 /* Return a deferred error */
2286 return -EIO;
2287 return blocks;
2288} 1771}
2289 1772
2290/* 1773static void ide_tape_flush_merge_buffer(ide_drive_t *drive)
2291 * Wait until all pending pipeline requests are serviced. Typically called on
2292 * device close.
2293 */
2294static void idetape_wait_for_pipeline(ide_drive_t *drive)
2295{
2296 idetape_tape_t *tape = drive->driver_data;
2297 unsigned long flags;
2298
2299 while (tape->next_stage || test_bit(IDETAPE_FLAG_PIPELINE_ACTIVE,
2300 &tape->flags)) {
2301 idetape_plug_pipeline(drive);
2302 spin_lock_irqsave(&tape->lock, flags);
2303 if (test_bit(IDETAPE_FLAG_PIPELINE_ACTIVE, &tape->flags))
2304 idetape_wait_for_request(drive, tape->active_data_rq);
2305 spin_unlock_irqrestore(&tape->lock, flags);
2306 }
2307}
2308
2309static void idetape_empty_write_pipeline(ide_drive_t *drive)
2310{ 1774{
2311 idetape_tape_t *tape = drive->driver_data; 1775 idetape_tape_t *tape = drive->driver_data;
2312 int blocks, min; 1776 int blocks, min;
2313 struct idetape_bh *bh; 1777 struct idetape_bh *bh;
2314 1778
2315 if (tape->chrdev_dir != IDETAPE_DIR_WRITE) { 1779 if (tape->chrdev_dir != IDETAPE_DIR_WRITE) {
2316 printk(KERN_ERR "ide-tape: bug: Trying to empty write pipeline," 1780 printk(KERN_ERR "ide-tape: bug: Trying to empty merge buffer"
2317 " but we are not writing.\n"); 1781 " but we are not writing.\n");
2318 return; 1782 return;
2319 } 1783 }
2320 if (tape->merge_stage_size > tape->stage_size) { 1784 if (tape->merge_bh_size > tape->buffer_size) {
2321 printk(KERN_ERR "ide-tape: bug: merge_buffer too big\n"); 1785 printk(KERN_ERR "ide-tape: bug: merge_buffer too big\n");
2322 tape->merge_stage_size = tape->stage_size; 1786 tape->merge_bh_size = tape->buffer_size;
2323 } 1787 }
2324 if (tape->merge_stage_size) { 1788 if (tape->merge_bh_size) {
2325 blocks = tape->merge_stage_size / tape->blk_size; 1789 blocks = tape->merge_bh_size / tape->blk_size;
2326 if (tape->merge_stage_size % tape->blk_size) { 1790 if (tape->merge_bh_size % tape->blk_size) {
2327 unsigned int i; 1791 unsigned int i;
2328 1792
2329 blocks++; 1793 blocks++;
2330 i = tape->blk_size - tape->merge_stage_size % 1794 i = tape->blk_size - tape->merge_bh_size %
2331 tape->blk_size; 1795 tape->blk_size;
2332 bh = tape->bh->b_reqnext; 1796 bh = tape->bh->b_reqnext;
2333 while (bh) { 1797 while (bh) {
@@ -2351,74 +1815,33 @@ static void idetape_empty_write_pipeline(ide_drive_t *drive)
2351 } 1815 }
2352 } 1816 }
2353 (void) idetape_add_chrdev_write_request(drive, blocks); 1817 (void) idetape_add_chrdev_write_request(drive, blocks);
2354 tape->merge_stage_size = 0; 1818 tape->merge_bh_size = 0;
2355 } 1819 }
2356 idetape_wait_for_pipeline(drive); 1820 if (tape->merge_bh != NULL) {
2357 if (tape->merge_stage != NULL) { 1821 ide_tape_kfree_buffer(tape);
2358 __idetape_kfree_stage(tape->merge_stage); 1822 tape->merge_bh = NULL;
2359 tape->merge_stage = NULL;
2360 } 1823 }
2361 clear_bit(IDETAPE_FLAG_PIPELINE_ERR, &tape->flags);
2362 tape->chrdev_dir = IDETAPE_DIR_NONE; 1824 tape->chrdev_dir = IDETAPE_DIR_NONE;
2363
2364 /*
2365 * On the next backup, perform the feedback loop again. (I don't want to
2366 * keep sense information between backups, as some systems are
2367 * constantly on, and the system load can be totally different on the
2368 * next backup).
2369 */
2370 tape->max_stages = tape->min_pipeline;
2371 if (tape->first_stage != NULL ||
2372 tape->next_stage != NULL ||
2373 tape->last_stage != NULL ||
2374 tape->nr_stages != 0) {
2375 printk(KERN_ERR "ide-tape: ide-tape pipeline bug, "
2376 "first_stage %p, next_stage %p, "
2377 "last_stage %p, nr_stages %d\n",
2378 tape->first_stage, tape->next_stage,
2379 tape->last_stage, tape->nr_stages);
2380 }
2381} 1825}
2382 1826
2383static void idetape_restart_speed_control(ide_drive_t *drive) 1827static int idetape_init_read(ide_drive_t *drive)
2384{ 1828{
2385 idetape_tape_t *tape = drive->driver_data; 1829 idetape_tape_t *tape = drive->driver_data;
2386
2387 tape->restart_speed_control_req = 0;
2388 tape->pipeline_head = 0;
2389 tape->controlled_last_pipeline_head = 0;
2390 tape->controlled_previous_pipeline_head = 0;
2391 tape->uncontrolled_previous_pipeline_head = 0;
2392 tape->controlled_pipeline_head_speed = 5000;
2393 tape->pipeline_head_speed = 5000;
2394 tape->uncontrolled_pipeline_head_speed = 0;
2395 tape->controlled_pipeline_head_time =
2396 tape->uncontrolled_pipeline_head_time = jiffies;
2397 tape->controlled_previous_head_time =
2398 tape->uncontrolled_previous_head_time = jiffies;
2399}
2400
2401static int idetape_init_read(ide_drive_t *drive, int max_stages)
2402{
2403 idetape_tape_t *tape = drive->driver_data;
2404 idetape_stage_t *new_stage;
2405 struct request rq;
2406 int bytes_read; 1830 int bytes_read;
2407 u16 blocks = *(u16 *)&tape->caps[12];
2408 1831
2409 /* Initialize read operation */ 1832 /* Initialize read operation */
2410 if (tape->chrdev_dir != IDETAPE_DIR_READ) { 1833 if (tape->chrdev_dir != IDETAPE_DIR_READ) {
2411 if (tape->chrdev_dir == IDETAPE_DIR_WRITE) { 1834 if (tape->chrdev_dir == IDETAPE_DIR_WRITE) {
2412 idetape_empty_write_pipeline(drive); 1835 ide_tape_flush_merge_buffer(drive);
2413 idetape_flush_tape_buffers(drive); 1836 idetape_flush_tape_buffers(drive);
2414 } 1837 }
2415 if (tape->merge_stage || tape->merge_stage_size) { 1838 if (tape->merge_bh || tape->merge_bh_size) {
2416 printk(KERN_ERR "ide-tape: merge_stage_size should be" 1839 printk(KERN_ERR "ide-tape: merge_bh_size should be"
2417 " 0 now\n"); 1840 " 0 now\n");
2418 tape->merge_stage_size = 0; 1841 tape->merge_bh_size = 0;
2419 } 1842 }
2420 tape->merge_stage = __idetape_kmalloc_stage(tape, 0, 0); 1843 tape->merge_bh = ide_tape_kmalloc_buffer(tape, 0, 0);
2421 if (!tape->merge_stage) 1844 if (!tape->merge_bh)
2422 return -ENOMEM; 1845 return -ENOMEM;
2423 tape->chrdev_dir = IDETAPE_DIR_READ; 1846 tape->chrdev_dir = IDETAPE_DIR_READ;
2424 1847
@@ -2431,54 +1854,23 @@ static int idetape_init_read(ide_drive_t *drive, int max_stages)
2431 if (drive->dsc_overlap) { 1854 if (drive->dsc_overlap) {
2432 bytes_read = idetape_queue_rw_tail(drive, 1855 bytes_read = idetape_queue_rw_tail(drive,
2433 REQ_IDETAPE_READ, 0, 1856 REQ_IDETAPE_READ, 0,
2434 tape->merge_stage->bh); 1857 tape->merge_bh);
2435 if (bytes_read < 0) { 1858 if (bytes_read < 0) {
2436 __idetape_kfree_stage(tape->merge_stage); 1859 ide_tape_kfree_buffer(tape);
2437 tape->merge_stage = NULL; 1860 tape->merge_bh = NULL;
2438 tape->chrdev_dir = IDETAPE_DIR_NONE; 1861 tape->chrdev_dir = IDETAPE_DIR_NONE;
2439 return bytes_read; 1862 return bytes_read;
2440 } 1863 }
2441 } 1864 }
2442 } 1865 }
2443 if (tape->restart_speed_control_req) 1866
2444 idetape_restart_speed_control(drive);
2445 idetape_init_rq(&rq, REQ_IDETAPE_READ);
2446 rq.sector = tape->first_frame;
2447 rq.nr_sectors = blocks;
2448 rq.current_nr_sectors = blocks;
2449 if (!test_bit(IDETAPE_FLAG_PIPELINE_ERR, &tape->flags) &&
2450 tape->nr_stages < max_stages) {
2451 new_stage = idetape_kmalloc_stage(tape);
2452 while (new_stage != NULL) {
2453 new_stage->rq = rq;
2454 idetape_add_stage_tail(drive, new_stage);
2455 if (tape->nr_stages >= max_stages)
2456 break;
2457 new_stage = idetape_kmalloc_stage(tape);
2458 }
2459 }
2460 if (!test_bit(IDETAPE_FLAG_PIPELINE_ACTIVE, &tape->flags)) {
2461 if (tape->nr_pending_stages >= 3 * max_stages / 4) {
2462 tape->measure_insert_time = 1;
2463 tape->insert_time = jiffies;
2464 tape->insert_size = 0;
2465 tape->insert_speed = 0;
2466 idetape_plug_pipeline(drive);
2467 }
2468 }
2469 return 0; 1867 return 0;
2470} 1868}
2471 1869
2472/* 1870/* called from idetape_chrdev_read() to service a chrdev read request. */
2473 * Called from idetape_chrdev_read() to service a character device read request
2474 * and add read-ahead requests to our pipeline.
2475 */
2476static int idetape_add_chrdev_read_request(ide_drive_t *drive, int blocks) 1871static int idetape_add_chrdev_read_request(ide_drive_t *drive, int blocks)
2477{ 1872{
2478 idetape_tape_t *tape = drive->driver_data; 1873 idetape_tape_t *tape = drive->driver_data;
2479 unsigned long flags;
2480 struct request *rq_ptr;
2481 int bytes_read;
2482 1874
2483 debug_log(DBG_PROCS, "Enter %s, %d blocks\n", __func__, blocks); 1875 debug_log(DBG_PROCS, "Enter %s, %d blocks\n", __func__, blocks);
2484 1876
@@ -2486,39 +1878,10 @@ static int idetape_add_chrdev_read_request(ide_drive_t *drive, int blocks)
2486 if (test_bit(IDETAPE_FLAG_FILEMARK, &tape->flags)) 1878 if (test_bit(IDETAPE_FLAG_FILEMARK, &tape->flags))
2487 return 0; 1879 return 0;
2488 1880
2489 /* Wait for the next block to reach the head of the pipeline. */ 1881 idetape_init_read(drive);
2490 idetape_init_read(drive, tape->max_stages);
2491 if (tape->first_stage == NULL) {
2492 if (test_bit(IDETAPE_FLAG_PIPELINE_ERR, &tape->flags))
2493 return 0;
2494 return idetape_queue_rw_tail(drive, REQ_IDETAPE_READ, blocks,
2495 tape->merge_stage->bh);
2496 }
2497 idetape_wait_first_stage(drive);
2498 rq_ptr = &tape->first_stage->rq;
2499 bytes_read = tape->blk_size * (rq_ptr->nr_sectors -
2500 rq_ptr->current_nr_sectors);
2501 rq_ptr->nr_sectors = 0;
2502 rq_ptr->current_nr_sectors = 0;
2503 1882
2504 if (rq_ptr->errors == IDETAPE_ERROR_EOD) 1883 return idetape_queue_rw_tail(drive, REQ_IDETAPE_READ, blocks,
2505 return 0; 1884 tape->merge_bh);
2506 else {
2507 idetape_switch_buffers(tape, tape->first_stage);
2508 if (rq_ptr->errors == IDETAPE_ERROR_FILEMARK)
2509 set_bit(IDETAPE_FLAG_FILEMARK, &tape->flags);
2510 spin_lock_irqsave(&tape->lock, flags);
2511 idetape_remove_stage_head(drive);
2512 spin_unlock_irqrestore(&tape->lock, flags);
2513 tape->pipeline_head++;
2514 idetape_calculate_speeds(drive);
2515 }
2516 if (bytes_read > blocks * tape->blk_size) {
2517 printk(KERN_ERR "ide-tape: bug: trying to return more bytes"
2518 " than requested\n");
2519 bytes_read = blocks * tape->blk_size;
2520 }
2521 return (bytes_read);
2522} 1885}
2523 1886
2524static void idetape_pad_zeros(ide_drive_t *drive, int bcount) 1887static void idetape_pad_zeros(ide_drive_t *drive, int bcount)
@@ -2530,8 +1893,8 @@ static void idetape_pad_zeros(ide_drive_t *drive, int bcount)
2530 while (bcount) { 1893 while (bcount) {
2531 unsigned int count; 1894 unsigned int count;
2532 1895
2533 bh = tape->merge_stage->bh; 1896 bh = tape->merge_bh;
2534 count = min(tape->stage_size, bcount); 1897 count = min(tape->buffer_size, bcount);
2535 bcount -= count; 1898 bcount -= count;
2536 blocks = count / tape->blk_size; 1899 blocks = count / tape->blk_size;
2537 while (count) { 1900 while (count) {
@@ -2542,29 +1905,8 @@ static void idetape_pad_zeros(ide_drive_t *drive, int bcount)
2542 bh = bh->b_reqnext; 1905 bh = bh->b_reqnext;
2543 } 1906 }
2544 idetape_queue_rw_tail(drive, REQ_IDETAPE_WRITE, blocks, 1907 idetape_queue_rw_tail(drive, REQ_IDETAPE_WRITE, blocks,
2545 tape->merge_stage->bh); 1908 tape->merge_bh);
2546 }
2547}
2548
2549static int idetape_pipeline_size(ide_drive_t *drive)
2550{
2551 idetape_tape_t *tape = drive->driver_data;
2552 idetape_stage_t *stage;
2553 struct request *rq;
2554 int size = 0;
2555
2556 idetape_wait_for_pipeline(drive);
2557 stage = tape->first_stage;
2558 while (stage != NULL) {
2559 rq = &stage->rq;
2560 size += tape->blk_size * (rq->nr_sectors -
2561 rq->current_nr_sectors);
2562 if (rq->errors == IDETAPE_ERROR_FILEMARK)
2563 size += tape->blk_size;
2564 stage = stage->next;
2565 } 1909 }
2566 size += tape->merge_stage_size;
2567 return size;
2568} 1910}
2569 1911
2570/* 1912/*
@@ -2612,11 +1954,10 @@ static int idetape_blkdev_ioctl(ide_drive_t *drive, unsigned int cmd,
2612 if (copy_from_user(&config, argp, sizeof(config))) 1954 if (copy_from_user(&config, argp, sizeof(config)))
2613 return -EFAULT; 1955 return -EFAULT;
2614 tape->best_dsc_rw_freq = config.dsc_rw_frequency; 1956 tape->best_dsc_rw_freq = config.dsc_rw_frequency;
2615 tape->max_stages = config.nr_stages;
2616 break; 1957 break;
2617 case 0x0350: 1958 case 0x0350:
2618 config.dsc_rw_frequency = (int) tape->best_dsc_rw_freq; 1959 config.dsc_rw_frequency = (int) tape->best_dsc_rw_freq;
2619 config.nr_stages = tape->max_stages; 1960 config.nr_stages = 1;
2620 if (copy_to_user(argp, &config, sizeof(config))) 1961 if (copy_to_user(argp, &config, sizeof(config)))
2621 return -EFAULT; 1962 return -EFAULT;
2622 break; 1963 break;
@@ -2626,19 +1967,11 @@ static int idetape_blkdev_ioctl(ide_drive_t *drive, unsigned int cmd,
2626 return 0; 1967 return 0;
2627} 1968}
2628 1969
2629/*
2630 * The function below is now a bit more complicated than just passing the
2631 * command to the tape since we may have crossed some filemarks during our
2632 * pipelined read-ahead mode. As a minor side effect, the pipeline enables us to
2633 * support MTFSFM when the filemark is in our internal pipeline even if the tape
2634 * doesn't support spacing over filemarks in the reverse direction.
2635 */
2636static int idetape_space_over_filemarks(ide_drive_t *drive, short mt_op, 1970static int idetape_space_over_filemarks(ide_drive_t *drive, short mt_op,
2637 int mt_count) 1971 int mt_count)
2638{ 1972{
2639 idetape_tape_t *tape = drive->driver_data; 1973 idetape_tape_t *tape = drive->driver_data;
2640 struct ide_atapi_pc pc; 1974 struct ide_atapi_pc pc;
2641 unsigned long flags;
2642 int retval, count = 0; 1975 int retval, count = 0;
2643 int sprev = !!(tape->caps[4] & 0x20); 1976 int sprev = !!(tape->caps[4] & 0x20);
2644 1977
@@ -2651,48 +1984,12 @@ static int idetape_space_over_filemarks(ide_drive_t *drive, short mt_op,
2651 } 1984 }
2652 1985
2653 if (tape->chrdev_dir == IDETAPE_DIR_READ) { 1986 if (tape->chrdev_dir == IDETAPE_DIR_READ) {
2654 /* its a read-ahead buffer, scan it for crossed filemarks. */ 1987 tape->merge_bh_size = 0;
2655 tape->merge_stage_size = 0;
2656 if (test_and_clear_bit(IDETAPE_FLAG_FILEMARK, &tape->flags)) 1988 if (test_and_clear_bit(IDETAPE_FLAG_FILEMARK, &tape->flags))
2657 ++count; 1989 ++count;
2658 while (tape->first_stage != NULL) { 1990 ide_tape_discard_merge_buffer(drive, 0);
2659 if (count == mt_count) {
2660 if (mt_op == MTFSFM)
2661 set_bit(IDETAPE_FLAG_FILEMARK,
2662 &tape->flags);
2663 return 0;
2664 }
2665 spin_lock_irqsave(&tape->lock, flags);
2666 if (tape->first_stage == tape->active_stage) {
2667 /*
2668 * We have reached the active stage in the read
2669 * pipeline. There is no point in allowing the
2670 * drive to continue reading any farther, so we
2671 * stop the pipeline.
2672 *
2673 * This section should be moved to a separate
2674 * subroutine because similar operations are
2675 * done in __idetape_discard_read_pipeline(),
2676 * for example.
2677 */
2678 tape->next_stage = NULL;
2679 spin_unlock_irqrestore(&tape->lock, flags);
2680 idetape_wait_first_stage(drive);
2681 tape->next_stage = tape->first_stage->next;
2682 } else
2683 spin_unlock_irqrestore(&tape->lock, flags);
2684 if (tape->first_stage->rq.errors ==
2685 IDETAPE_ERROR_FILEMARK)
2686 ++count;
2687 idetape_remove_stage_head(drive);
2688 }
2689 idetape_discard_read_pipeline(drive, 0);
2690 } 1991 }
2691 1992
2692 /*
2693 * The filemark was not found in our internal pipeline; now we can issue
2694 * the space command.
2695 */
2696 switch (mt_op) { 1993 switch (mt_op) {
2697 case MTFSF: 1994 case MTFSF:
2698 case MTBSF: 1995 case MTBSF:
@@ -2748,27 +2045,25 @@ static ssize_t idetape_chrdev_read(struct file *file, char __user *buf,
2748 (count % tape->blk_size) == 0) 2045 (count % tape->blk_size) == 0)
2749 tape->user_bs_factor = count / tape->blk_size; 2046 tape->user_bs_factor = count / tape->blk_size;
2750 } 2047 }
2751 rc = idetape_init_read(drive, tape->max_stages); 2048 rc = idetape_init_read(drive);
2752 if (rc < 0) 2049 if (rc < 0)
2753 return rc; 2050 return rc;
2754 if (count == 0) 2051 if (count == 0)
2755 return (0); 2052 return (0);
2756 if (tape->merge_stage_size) { 2053 if (tape->merge_bh_size) {
2757 actually_read = min((unsigned int)(tape->merge_stage_size), 2054 actually_read = min((unsigned int)(tape->merge_bh_size),
2758 (unsigned int)count); 2055 (unsigned int)count);
2759 if (idetape_copy_stage_to_user(tape, buf, tape->merge_stage, 2056 if (idetape_copy_stage_to_user(tape, buf, actually_read))
2760 actually_read))
2761 ret = -EFAULT; 2057 ret = -EFAULT;
2762 buf += actually_read; 2058 buf += actually_read;
2763 tape->merge_stage_size -= actually_read; 2059 tape->merge_bh_size -= actually_read;
2764 count -= actually_read; 2060 count -= actually_read;
2765 } 2061 }
2766 while (count >= tape->stage_size) { 2062 while (count >= tape->buffer_size) {
2767 bytes_read = idetape_add_chrdev_read_request(drive, ctl); 2063 bytes_read = idetape_add_chrdev_read_request(drive, ctl);
2768 if (bytes_read <= 0) 2064 if (bytes_read <= 0)
2769 goto finish; 2065 goto finish;
2770 if (idetape_copy_stage_to_user(tape, buf, tape->merge_stage, 2066 if (idetape_copy_stage_to_user(tape, buf, bytes_read))
2771 bytes_read))
2772 ret = -EFAULT; 2067 ret = -EFAULT;
2773 buf += bytes_read; 2068 buf += bytes_read;
2774 count -= bytes_read; 2069 count -= bytes_read;
@@ -2779,11 +2074,10 @@ static ssize_t idetape_chrdev_read(struct file *file, char __user *buf,
2779 if (bytes_read <= 0) 2074 if (bytes_read <= 0)
2780 goto finish; 2075 goto finish;
2781 temp = min((unsigned long)count, (unsigned long)bytes_read); 2076 temp = min((unsigned long)count, (unsigned long)bytes_read);
2782 if (idetape_copy_stage_to_user(tape, buf, tape->merge_stage, 2077 if (idetape_copy_stage_to_user(tape, buf, temp))
2783 temp))
2784 ret = -EFAULT; 2078 ret = -EFAULT;
2785 actually_read += temp; 2079 actually_read += temp;
2786 tape->merge_stage_size = bytes_read-temp; 2080 tape->merge_bh_size = bytes_read-temp;
2787 } 2081 }
2788finish: 2082finish:
2789 if (!actually_read && test_bit(IDETAPE_FLAG_FILEMARK, &tape->flags)) { 2083 if (!actually_read && test_bit(IDETAPE_FLAG_FILEMARK, &tape->flags)) {
@@ -2814,17 +2108,17 @@ static ssize_t idetape_chrdev_write(struct file *file, const char __user *buf,
2814 /* Initialize write operation */ 2108 /* Initialize write operation */
2815 if (tape->chrdev_dir != IDETAPE_DIR_WRITE) { 2109 if (tape->chrdev_dir != IDETAPE_DIR_WRITE) {
2816 if (tape->chrdev_dir == IDETAPE_DIR_READ) 2110 if (tape->chrdev_dir == IDETAPE_DIR_READ)
2817 idetape_discard_read_pipeline(drive, 1); 2111 ide_tape_discard_merge_buffer(drive, 1);
2818 if (tape->merge_stage || tape->merge_stage_size) { 2112 if (tape->merge_bh || tape->merge_bh_size) {
2819 printk(KERN_ERR "ide-tape: merge_stage_size " 2113 printk(KERN_ERR "ide-tape: merge_bh_size "
2820 "should be 0 now\n"); 2114 "should be 0 now\n");
2821 tape->merge_stage_size = 0; 2115 tape->merge_bh_size = 0;
2822 } 2116 }
2823 tape->merge_stage = __idetape_kmalloc_stage(tape, 0, 0); 2117 tape->merge_bh = ide_tape_kmalloc_buffer(tape, 0, 0);
2824 if (!tape->merge_stage) 2118 if (!tape->merge_bh)
2825 return -ENOMEM; 2119 return -ENOMEM;
2826 tape->chrdev_dir = IDETAPE_DIR_WRITE; 2120 tape->chrdev_dir = IDETAPE_DIR_WRITE;
2827 idetape_init_merge_stage(tape); 2121 idetape_init_merge_buffer(tape);
2828 2122
2829 /* 2123 /*
2830 * Issue a write 0 command to ensure that DSC handshake is 2124 * Issue a write 0 command to ensure that DSC handshake is
@@ -2835,10 +2129,10 @@ static ssize_t idetape_chrdev_write(struct file *file, const char __user *buf,
2835 if (drive->dsc_overlap) { 2129 if (drive->dsc_overlap) {
2836 ssize_t retval = idetape_queue_rw_tail(drive, 2130 ssize_t retval = idetape_queue_rw_tail(drive,
2837 REQ_IDETAPE_WRITE, 0, 2131 REQ_IDETAPE_WRITE, 0,
2838 tape->merge_stage->bh); 2132 tape->merge_bh);
2839 if (retval < 0) { 2133 if (retval < 0) {
2840 __idetape_kfree_stage(tape->merge_stage); 2134 ide_tape_kfree_buffer(tape);
2841 tape->merge_stage = NULL; 2135 tape->merge_bh = NULL;
2842 tape->chrdev_dir = IDETAPE_DIR_NONE; 2136 tape->chrdev_dir = IDETAPE_DIR_NONE;
2843 return retval; 2137 return retval;
2844 } 2138 }
@@ -2846,49 +2140,44 @@ static ssize_t idetape_chrdev_write(struct file *file, const char __user *buf,
2846 } 2140 }
2847 if (count == 0) 2141 if (count == 0)
2848 return (0); 2142 return (0);
2849 if (tape->restart_speed_control_req) 2143 if (tape->merge_bh_size) {
2850 idetape_restart_speed_control(drive); 2144 if (tape->merge_bh_size >= tape->buffer_size) {
2851 if (tape->merge_stage_size) {
2852 if (tape->merge_stage_size >= tape->stage_size) {
2853 printk(KERN_ERR "ide-tape: bug: merge buf too big\n"); 2145 printk(KERN_ERR "ide-tape: bug: merge buf too big\n");
2854 tape->merge_stage_size = 0; 2146 tape->merge_bh_size = 0;
2855 } 2147 }
2856 actually_written = min((unsigned int) 2148 actually_written = min((unsigned int)
2857 (tape->stage_size - tape->merge_stage_size), 2149 (tape->buffer_size - tape->merge_bh_size),
2858 (unsigned int)count); 2150 (unsigned int)count);
2859 if (idetape_copy_stage_from_user(tape, tape->merge_stage, buf, 2151 if (idetape_copy_stage_from_user(tape, buf, actually_written))
2860 actually_written))
2861 ret = -EFAULT; 2152 ret = -EFAULT;
2862 buf += actually_written; 2153 buf += actually_written;
2863 tape->merge_stage_size += actually_written; 2154 tape->merge_bh_size += actually_written;
2864 count -= actually_written; 2155 count -= actually_written;
2865 2156
2866 if (tape->merge_stage_size == tape->stage_size) { 2157 if (tape->merge_bh_size == tape->buffer_size) {
2867 ssize_t retval; 2158 ssize_t retval;
2868 tape->merge_stage_size = 0; 2159 tape->merge_bh_size = 0;
2869 retval = idetape_add_chrdev_write_request(drive, ctl); 2160 retval = idetape_add_chrdev_write_request(drive, ctl);
2870 if (retval <= 0) 2161 if (retval <= 0)
2871 return (retval); 2162 return (retval);
2872 } 2163 }
2873 } 2164 }
2874 while (count >= tape->stage_size) { 2165 while (count >= tape->buffer_size) {
2875 ssize_t retval; 2166 ssize_t retval;
2876 if (idetape_copy_stage_from_user(tape, tape->merge_stage, buf, 2167 if (idetape_copy_stage_from_user(tape, buf, tape->buffer_size))
2877 tape->stage_size))
2878 ret = -EFAULT; 2168 ret = -EFAULT;
2879 buf += tape->stage_size; 2169 buf += tape->buffer_size;
2880 count -= tape->stage_size; 2170 count -= tape->buffer_size;
2881 retval = idetape_add_chrdev_write_request(drive, ctl); 2171 retval = idetape_add_chrdev_write_request(drive, ctl);
2882 actually_written += tape->stage_size; 2172 actually_written += tape->buffer_size;
2883 if (retval <= 0) 2173 if (retval <= 0)
2884 return (retval); 2174 return (retval);
2885 } 2175 }
2886 if (count) { 2176 if (count) {
2887 actually_written += count; 2177 actually_written += count;
2888 if (idetape_copy_stage_from_user(tape, tape->merge_stage, buf, 2178 if (idetape_copy_stage_from_user(tape, buf, count))
2889 count))
2890 ret = -EFAULT; 2179 ret = -EFAULT;
2891 tape->merge_stage_size += count; 2180 tape->merge_bh_size += count;
2892 } 2181 }
2893 return ret ? ret : actually_written; 2182 return ret ? ret : actually_written;
2894} 2183}
@@ -2912,8 +2201,7 @@ static int idetape_write_filemark(ide_drive_t *drive)
2912 * 2201 *
2913 * Note: MTBSF and MTBSFM are not supported when the tape doesn't support 2202 * Note: MTBSF and MTBSFM are not supported when the tape doesn't support
2914 * spacing over filemarks in the reverse direction. In this case, MTFSFM is also 2203 * spacing over filemarks in the reverse direction. In this case, MTFSFM is also
2915 * usually not supported (it is supported in the rare case in which we crossed 2204 * usually not supported.
2916 * the filemark during our read-ahead pipelined operation mode).
2917 * 2205 *
2918 * The following commands are currently not supported: 2206 * The following commands are currently not supported:
2919 * 2207 *
@@ -2929,7 +2217,6 @@ static int idetape_mtioctop(ide_drive_t *drive, short mt_op, int mt_count)
2929 debug_log(DBG_ERR, "Handling MTIOCTOP ioctl: mt_op=%d, mt_count=%d\n", 2217 debug_log(DBG_ERR, "Handling MTIOCTOP ioctl: mt_op=%d, mt_count=%d\n",
2930 mt_op, mt_count); 2218 mt_op, mt_count);
2931 2219
2932 /* Commands which need our pipelined read-ahead stages. */
2933 switch (mt_op) { 2220 switch (mt_op) {
2934 case MTFSF: 2221 case MTFSF:
2935 case MTFSFM: 2222 case MTFSFM:
@@ -2946,7 +2233,7 @@ static int idetape_mtioctop(ide_drive_t *drive, short mt_op, int mt_count)
2946 case MTWEOF: 2233 case MTWEOF:
2947 if (tape->write_prot) 2234 if (tape->write_prot)
2948 return -EACCES; 2235 return -EACCES;
2949 idetape_discard_read_pipeline(drive, 1); 2236 ide_tape_discard_merge_buffer(drive, 1);
2950 for (i = 0; i < mt_count; i++) { 2237 for (i = 0; i < mt_count; i++) {
2951 retval = idetape_write_filemark(drive); 2238 retval = idetape_write_filemark(drive);
2952 if (retval) 2239 if (retval)
@@ -2954,12 +2241,12 @@ static int idetape_mtioctop(ide_drive_t *drive, short mt_op, int mt_count)
2954 } 2241 }
2955 return 0; 2242 return 0;
2956 case MTREW: 2243 case MTREW:
2957 idetape_discard_read_pipeline(drive, 0); 2244 ide_tape_discard_merge_buffer(drive, 0);
2958 if (idetape_rewind_tape(drive)) 2245 if (idetape_rewind_tape(drive))
2959 return -EIO; 2246 return -EIO;
2960 return 0; 2247 return 0;
2961 case MTLOAD: 2248 case MTLOAD:
2962 idetape_discard_read_pipeline(drive, 0); 2249 ide_tape_discard_merge_buffer(drive, 0);
2963 idetape_create_load_unload_cmd(drive, &pc, 2250 idetape_create_load_unload_cmd(drive, &pc,
2964 IDETAPE_LU_LOAD_MASK); 2251 IDETAPE_LU_LOAD_MASK);
2965 return idetape_queue_pc_tail(drive, &pc); 2252 return idetape_queue_pc_tail(drive, &pc);
@@ -2974,7 +2261,7 @@ static int idetape_mtioctop(ide_drive_t *drive, short mt_op, int mt_count)
2974 if (!idetape_queue_pc_tail(drive, &pc)) 2261 if (!idetape_queue_pc_tail(drive, &pc))
2975 tape->door_locked = DOOR_UNLOCKED; 2262 tape->door_locked = DOOR_UNLOCKED;
2976 } 2263 }
2977 idetape_discard_read_pipeline(drive, 0); 2264 ide_tape_discard_merge_buffer(drive, 0);
2978 idetape_create_load_unload_cmd(drive, &pc, 2265 idetape_create_load_unload_cmd(drive, &pc,
2979 !IDETAPE_LU_LOAD_MASK); 2266 !IDETAPE_LU_LOAD_MASK);
2980 retval = idetape_queue_pc_tail(drive, &pc); 2267 retval = idetape_queue_pc_tail(drive, &pc);
@@ -2982,10 +2269,10 @@ static int idetape_mtioctop(ide_drive_t *drive, short mt_op, int mt_count)
2982 clear_bit(IDETAPE_FLAG_MEDIUM_PRESENT, &tape->flags); 2269 clear_bit(IDETAPE_FLAG_MEDIUM_PRESENT, &tape->flags);
2983 return retval; 2270 return retval;
2984 case MTNOP: 2271 case MTNOP:
2985 idetape_discard_read_pipeline(drive, 0); 2272 ide_tape_discard_merge_buffer(drive, 0);
2986 return idetape_flush_tape_buffers(drive); 2273 return idetape_flush_tape_buffers(drive);
2987 case MTRETEN: 2274 case MTRETEN:
2988 idetape_discard_read_pipeline(drive, 0); 2275 ide_tape_discard_merge_buffer(drive, 0);
2989 idetape_create_load_unload_cmd(drive, &pc, 2276 idetape_create_load_unload_cmd(drive, &pc,
2990 IDETAPE_LU_RETENSION_MASK | IDETAPE_LU_LOAD_MASK); 2277 IDETAPE_LU_RETENSION_MASK | IDETAPE_LU_LOAD_MASK);
2991 return idetape_queue_pc_tail(drive, &pc); 2278 return idetape_queue_pc_tail(drive, &pc);
@@ -3007,11 +2294,11 @@ static int idetape_mtioctop(ide_drive_t *drive, short mt_op, int mt_count)
3007 set_bit(IDETAPE_FLAG_DETECT_BS, &tape->flags); 2294 set_bit(IDETAPE_FLAG_DETECT_BS, &tape->flags);
3008 return 0; 2295 return 0;
3009 case MTSEEK: 2296 case MTSEEK:
3010 idetape_discard_read_pipeline(drive, 0); 2297 ide_tape_discard_merge_buffer(drive, 0);
3011 return idetape_position_tape(drive, 2298 return idetape_position_tape(drive,
3012 mt_count * tape->user_bs_factor, tape->partition, 0); 2299 mt_count * tape->user_bs_factor, tape->partition, 0);
3013 case MTSETPART: 2300 case MTSETPART:
3014 idetape_discard_read_pipeline(drive, 0); 2301 ide_tape_discard_merge_buffer(drive, 0);
3015 return idetape_position_tape(drive, 0, mt_count, 0); 2302 return idetape_position_tape(drive, 0, mt_count, 0);
3016 case MTFSR: 2303 case MTFSR:
3017 case MTBSR: 2304 case MTBSR:
@@ -3056,13 +2343,12 @@ static int idetape_chrdev_ioctl(struct inode *inode, struct file *file,
3056 2343
3057 debug_log(DBG_CHRDEV, "Enter %s, cmd=%u\n", __func__, cmd); 2344 debug_log(DBG_CHRDEV, "Enter %s, cmd=%u\n", __func__, cmd);
3058 2345
3059 tape->restart_speed_control_req = 1;
3060 if (tape->chrdev_dir == IDETAPE_DIR_WRITE) { 2346 if (tape->chrdev_dir == IDETAPE_DIR_WRITE) {
3061 idetape_empty_write_pipeline(drive); 2347 ide_tape_flush_merge_buffer(drive);
3062 idetape_flush_tape_buffers(drive); 2348 idetape_flush_tape_buffers(drive);
3063 } 2349 }
3064 if (cmd == MTIOCGET || cmd == MTIOCPOS) { 2350 if (cmd == MTIOCGET || cmd == MTIOCPOS) {
3065 block_offset = idetape_pipeline_size(drive) / 2351 block_offset = tape->merge_bh_size /
3066 (tape->blk_size * tape->user_bs_factor); 2352 (tape->blk_size * tape->user_bs_factor);
3067 position = idetape_read_position(drive); 2353 position = idetape_read_position(drive);
3068 if (position < 0) 2354 if (position < 0)
@@ -3094,7 +2380,7 @@ static int idetape_chrdev_ioctl(struct inode *inode, struct file *file,
3094 return 0; 2380 return 0;
3095 default: 2381 default:
3096 if (tape->chrdev_dir == IDETAPE_DIR_READ) 2382 if (tape->chrdev_dir == IDETAPE_DIR_READ)
3097 idetape_discard_read_pipeline(drive, 1); 2383 ide_tape_discard_merge_buffer(drive, 1);
3098 return idetape_blkdev_ioctl(drive, cmd, arg); 2384 return idetape_blkdev_ioctl(drive, cmd, arg);
3099 } 2385 }
3100} 2386}
@@ -3168,9 +2454,6 @@ static int idetape_chrdev_open(struct inode *inode, struct file *filp)
3168 if (!test_bit(IDETAPE_FLAG_ADDRESS_VALID, &tape->flags)) 2454 if (!test_bit(IDETAPE_FLAG_ADDRESS_VALID, &tape->flags))
3169 (void)idetape_rewind_tape(drive); 2455 (void)idetape_rewind_tape(drive);
3170 2456
3171 if (tape->chrdev_dir != IDETAPE_DIR_READ)
3172 clear_bit(IDETAPE_FLAG_PIPELINE_ERR, &tape->flags);
3173
3174 /* Read block size and write protect status from drive. */ 2457 /* Read block size and write protect status from drive. */
3175 ide_tape_get_bsize_from_bdesc(drive); 2458 ide_tape_get_bsize_from_bdesc(drive);
3176 2459
@@ -3199,8 +2482,6 @@ static int idetape_chrdev_open(struct inode *inode, struct file *filp)
3199 } 2482 }
3200 } 2483 }
3201 } 2484 }
3202 idetape_restart_speed_control(drive);
3203 tape->restart_speed_control_req = 0;
3204 return 0; 2485 return 0;
3205 2486
3206out_put_tape: 2487out_put_tape:
@@ -3212,13 +2493,13 @@ static void idetape_write_release(ide_drive_t *drive, unsigned int minor)
3212{ 2493{
3213 idetape_tape_t *tape = drive->driver_data; 2494 idetape_tape_t *tape = drive->driver_data;
3214 2495
3215 idetape_empty_write_pipeline(drive); 2496 ide_tape_flush_merge_buffer(drive);
3216 tape->merge_stage = __idetape_kmalloc_stage(tape, 1, 0); 2497 tape->merge_bh = ide_tape_kmalloc_buffer(tape, 1, 0);
3217 if (tape->merge_stage != NULL) { 2498 if (tape->merge_bh != NULL) {
3218 idetape_pad_zeros(drive, tape->blk_size * 2499 idetape_pad_zeros(drive, tape->blk_size *
3219 (tape->user_bs_factor - 1)); 2500 (tape->user_bs_factor - 1));
3220 __idetape_kfree_stage(tape->merge_stage); 2501 ide_tape_kfree_buffer(tape);
3221 tape->merge_stage = NULL; 2502 tape->merge_bh = NULL;
3222 } 2503 }
3223 idetape_write_filemark(drive); 2504 idetape_write_filemark(drive);
3224 idetape_flush_tape_buffers(drive); 2505 idetape_flush_tape_buffers(drive);
@@ -3241,14 +2522,9 @@ static int idetape_chrdev_release(struct inode *inode, struct file *filp)
3241 idetape_write_release(drive, minor); 2522 idetape_write_release(drive, minor);
3242 if (tape->chrdev_dir == IDETAPE_DIR_READ) { 2523 if (tape->chrdev_dir == IDETAPE_DIR_READ) {
3243 if (minor < 128) 2524 if (minor < 128)
3244 idetape_discard_read_pipeline(drive, 1); 2525 ide_tape_discard_merge_buffer(drive, 1);
3245 else
3246 idetape_wait_for_pipeline(drive);
3247 }
3248 if (tape->cache_stage != NULL) {
3249 __idetape_kfree_stage(tape->cache_stage);
3250 tape->cache_stage = NULL;
3251 } 2526 }
2527
3252 if (minor < 128 && test_bit(IDETAPE_FLAG_MEDIUM_PRESENT, &tape->flags)) 2528 if (minor < 128 && test_bit(IDETAPE_FLAG_MEDIUM_PRESENT, &tape->flags))
3253 (void) idetape_rewind_tape(drive); 2529 (void) idetape_rewind_tape(drive);
3254 if (tape->chrdev_dir == IDETAPE_DIR_NONE) { 2530 if (tape->chrdev_dir == IDETAPE_DIR_NONE) {
@@ -3385,33 +2661,15 @@ static void idetape_add_settings(ide_drive_t *drive)
3385 2661
3386 ide_add_setting(drive, "buffer", SETTING_READ, TYPE_SHORT, 0, 0xffff, 2662 ide_add_setting(drive, "buffer", SETTING_READ, TYPE_SHORT, 0, 0xffff,
3387 1, 2, (u16 *)&tape->caps[16], NULL); 2663 1, 2, (u16 *)&tape->caps[16], NULL);
3388 ide_add_setting(drive, "pipeline_min", SETTING_RW, TYPE_INT, 1, 0xffff,
3389 tape->stage_size / 1024, 1, &tape->min_pipeline, NULL);
3390 ide_add_setting(drive, "pipeline", SETTING_RW, TYPE_INT, 1, 0xffff,
3391 tape->stage_size / 1024, 1, &tape->max_stages, NULL);
3392 ide_add_setting(drive, "pipeline_max", SETTING_RW, TYPE_INT, 1, 0xffff,
3393 tape->stage_size / 1024, 1, &tape->max_pipeline, NULL);
3394 ide_add_setting(drive, "pipeline_used", SETTING_READ, TYPE_INT, 0,
3395 0xffff, tape->stage_size / 1024, 1, &tape->nr_stages,
3396 NULL);
3397 ide_add_setting(drive, "pipeline_pending", SETTING_READ, TYPE_INT, 0,
3398 0xffff, tape->stage_size / 1024, 1,
3399 &tape->nr_pending_stages, NULL);
3400 ide_add_setting(drive, "speed", SETTING_READ, TYPE_SHORT, 0, 0xffff, 2664 ide_add_setting(drive, "speed", SETTING_READ, TYPE_SHORT, 0, 0xffff,
3401 1, 1, (u16 *)&tape->caps[14], NULL); 2665 1, 1, (u16 *)&tape->caps[14], NULL);
3402 ide_add_setting(drive, "stage", SETTING_READ, TYPE_INT, 0, 0xffff, 1, 2666 ide_add_setting(drive, "buffer_size", SETTING_READ, TYPE_INT, 0, 0xffff,
3403 1024, &tape->stage_size, NULL); 2667 1, 1024, &tape->buffer_size, NULL);
3404 ide_add_setting(drive, "tdsc", SETTING_RW, TYPE_INT, IDETAPE_DSC_RW_MIN, 2668 ide_add_setting(drive, "tdsc", SETTING_RW, TYPE_INT, IDETAPE_DSC_RW_MIN,
3405 IDETAPE_DSC_RW_MAX, 1000, HZ, &tape->best_dsc_rw_freq, 2669 IDETAPE_DSC_RW_MAX, 1000, HZ, &tape->best_dsc_rw_freq,
3406 NULL); 2670 NULL);
3407 ide_add_setting(drive, "dsc_overlap", SETTING_RW, TYPE_BYTE, 0, 1, 1, 2671 ide_add_setting(drive, "dsc_overlap", SETTING_RW, TYPE_BYTE, 0, 1, 1,
3408 1, &drive->dsc_overlap, NULL); 2672 1, &drive->dsc_overlap, NULL);
3409 ide_add_setting(drive, "pipeline_head_speed_c", SETTING_READ, TYPE_INT,
3410 0, 0xffff, 1, 1, &tape->controlled_pipeline_head_speed,
3411 NULL);
3412 ide_add_setting(drive, "pipeline_head_speed_u", SETTING_READ, TYPE_INT,
3413 0, 0xffff, 1, 1,
3414 &tape->uncontrolled_pipeline_head_speed, NULL);
3415 ide_add_setting(drive, "avg_speed", SETTING_READ, TYPE_INT, 0, 0xffff, 2673 ide_add_setting(drive, "avg_speed", SETTING_READ, TYPE_INT, 0, 0xffff,
3416 1, 1, &tape->avg_speed, NULL); 2674 1, 1, &tape->avg_speed, NULL);
3417 ide_add_setting(drive, "debug_mask", SETTING_RW, TYPE_INT, 0, 0xffff, 1, 2675 ide_add_setting(drive, "debug_mask", SETTING_RW, TYPE_INT, 0, 0xffff, 1,
@@ -3434,11 +2692,10 @@ static inline void idetape_add_settings(ide_drive_t *drive) { ; }
3434 */ 2692 */
3435static void idetape_setup(ide_drive_t *drive, idetape_tape_t *tape, int minor) 2693static void idetape_setup(ide_drive_t *drive, idetape_tape_t *tape, int minor)
3436{ 2694{
3437 unsigned long t1, tmid, tn, t; 2695 unsigned long t;
3438 int speed; 2696 int speed;
3439 int stage_size; 2697 int buffer_size;
3440 u8 gcw[2]; 2698 u8 gcw[2];
3441 struct sysinfo si;
3442 u16 *ctl = (u16 *)&tape->caps[12]; 2699 u16 *ctl = (u16 *)&tape->caps[12];
3443 2700
3444 spin_lock_init(&tape->lock); 2701 spin_lock_init(&tape->lock);
@@ -3457,65 +2714,33 @@ static void idetape_setup(ide_drive_t *drive, idetape_tape_t *tape, int minor)
3457 tape->name[2] = '0' + minor; 2714 tape->name[2] = '0' + minor;
3458 tape->chrdev_dir = IDETAPE_DIR_NONE; 2715 tape->chrdev_dir = IDETAPE_DIR_NONE;
3459 tape->pc = tape->pc_stack; 2716 tape->pc = tape->pc_stack;
3460 tape->max_insert_speed = 10000;
3461 tape->speed_control = 1;
3462 *((unsigned short *) &gcw) = drive->id->config; 2717 *((unsigned short *) &gcw) = drive->id->config;
3463 2718
3464 /* Command packet DRQ type */ 2719 /* Command packet DRQ type */
3465 if (((gcw[0] & 0x60) >> 5) == 1) 2720 if (((gcw[0] & 0x60) >> 5) == 1)
3466 set_bit(IDETAPE_FLAG_DRQ_INTERRUPT, &tape->flags); 2721 set_bit(IDETAPE_FLAG_DRQ_INTERRUPT, &tape->flags);
3467 2722
3468 tape->min_pipeline = 10;
3469 tape->max_pipeline = 10;
3470 tape->max_stages = 10;
3471
3472 idetape_get_inquiry_results(drive); 2723 idetape_get_inquiry_results(drive);
3473 idetape_get_mode_sense_results(drive); 2724 idetape_get_mode_sense_results(drive);
3474 ide_tape_get_bsize_from_bdesc(drive); 2725 ide_tape_get_bsize_from_bdesc(drive);
3475 tape->user_bs_factor = 1; 2726 tape->user_bs_factor = 1;
3476 tape->stage_size = *ctl * tape->blk_size; 2727 tape->buffer_size = *ctl * tape->blk_size;
3477 while (tape->stage_size > 0xffff) { 2728 while (tape->buffer_size > 0xffff) {
3478 printk(KERN_NOTICE "ide-tape: decreasing stage size\n"); 2729 printk(KERN_NOTICE "ide-tape: decreasing stage size\n");
3479 *ctl /= 2; 2730 *ctl /= 2;
3480 tape->stage_size = *ctl * tape->blk_size; 2731 tape->buffer_size = *ctl * tape->blk_size;
3481 } 2732 }
3482 stage_size = tape->stage_size; 2733 buffer_size = tape->buffer_size;
3483 tape->pages_per_stage = stage_size / PAGE_SIZE; 2734 tape->pages_per_buffer = buffer_size / PAGE_SIZE;
3484 if (stage_size % PAGE_SIZE) { 2735 if (buffer_size % PAGE_SIZE) {
3485 tape->pages_per_stage++; 2736 tape->pages_per_buffer++;
3486 tape->excess_bh_size = PAGE_SIZE - stage_size % PAGE_SIZE; 2737 tape->excess_bh_size = PAGE_SIZE - buffer_size % PAGE_SIZE;
3487 } 2738 }
3488 2739
3489 /* Select the "best" DSC read/write polling freq and pipeline size. */ 2740 /* select the "best" DSC read/write polling freq */
3490 speed = max(*(u16 *)&tape->caps[14], *(u16 *)&tape->caps[8]); 2741 speed = max(*(u16 *)&tape->caps[14], *(u16 *)&tape->caps[8]);
3491 2742
3492 tape->max_stages = speed * 1000 * 10 / tape->stage_size; 2743 t = (IDETAPE_FIFO_THRESHOLD * tape->buffer_size * HZ) / (speed * 1000);
3493
3494 /* Limit memory use for pipeline to 10% of physical memory */
3495 si_meminfo(&si);
3496 if (tape->max_stages * tape->stage_size >
3497 si.totalram * si.mem_unit / 10)
3498 tape->max_stages =
3499 si.totalram * si.mem_unit / (10 * tape->stage_size);
3500
3501 tape->max_stages = min(tape->max_stages, IDETAPE_MAX_PIPELINE_STAGES);
3502 tape->min_pipeline = min(tape->max_stages, IDETAPE_MIN_PIPELINE_STAGES);
3503 tape->max_pipeline =
3504 min(tape->max_stages * 2, IDETAPE_MAX_PIPELINE_STAGES);
3505 if (tape->max_stages == 0) {
3506 tape->max_stages = 1;
3507 tape->min_pipeline = 1;
3508 tape->max_pipeline = 1;
3509 }
3510
3511 t1 = (tape->stage_size * HZ) / (speed * 1000);
3512 tmid = (*(u16 *)&tape->caps[16] * 32 * HZ) / (speed * 125);
3513 tn = (IDETAPE_FIFO_THRESHOLD * tape->stage_size * HZ) / (speed * 1000);
3514
3515 if (tape->max_stages)
3516 t = tn;
3517 else
3518 t = t1;
3519 2744
3520 /* 2745 /*
3521 * Ensure that the number we got makes sense; limit it within 2746 * Ensure that the number we got makes sense; limit it within
@@ -3525,11 +2750,10 @@ static void idetape_setup(ide_drive_t *drive, idetape_tape_t *tape, int minor)
3525 min_t(unsigned long, t, IDETAPE_DSC_RW_MAX), 2750 min_t(unsigned long, t, IDETAPE_DSC_RW_MAX),
3526 IDETAPE_DSC_RW_MIN); 2751 IDETAPE_DSC_RW_MIN);
3527 printk(KERN_INFO "ide-tape: %s <-> %s: %dKBps, %d*%dkB buffer, " 2752 printk(KERN_INFO "ide-tape: %s <-> %s: %dKBps, %d*%dkB buffer, "
3528 "%dkB pipeline, %lums tDSC%s\n", 2753 "%lums tDSC%s\n",
3529 drive->name, tape->name, *(u16 *)&tape->caps[14], 2754 drive->name, tape->name, *(u16 *)&tape->caps[14],
3530 (*(u16 *)&tape->caps[16] * 512) / tape->stage_size, 2755 (*(u16 *)&tape->caps[16] * 512) / tape->buffer_size,
3531 tape->stage_size / 1024, 2756 tape->buffer_size / 1024,
3532 tape->max_stages * tape->stage_size / 1024,
3533 tape->best_dsc_rw_freq * 1000 / HZ, 2757 tape->best_dsc_rw_freq * 1000 / HZ,
3534 drive->using_dma ? ", DMA":""); 2758 drive->using_dma ? ", DMA":"");
3535 2759
@@ -3553,7 +2777,7 @@ static void ide_tape_release(struct kref *kref)
3553 ide_drive_t *drive = tape->drive; 2777 ide_drive_t *drive = tape->drive;
3554 struct gendisk *g = tape->disk; 2778 struct gendisk *g = tape->disk;
3555 2779
3556 BUG_ON(tape->first_stage != NULL || tape->merge_stage_size); 2780 BUG_ON(tape->merge_bh_size);
3557 2781
3558 drive->dsc_overlap = 0; 2782 drive->dsc_overlap = 0;
3559 drive->driver_data = NULL; 2783 drive->driver_data = NULL;
diff --git a/drivers/ide/ide-taskfile.c b/drivers/ide/ide-taskfile.c
index a317ca9c46e5..0c908ca3ff79 100644
--- a/drivers/ide/ide-taskfile.c
+++ b/drivers/ide/ide-taskfile.c
@@ -33,60 +33,18 @@
33#include <asm/uaccess.h> 33#include <asm/uaccess.h>
34#include <asm/io.h> 34#include <asm/io.h>
35 35
36void ide_tf_load(ide_drive_t *drive, ide_task_t *task) 36void ide_tf_dump(const char *s, struct ide_taskfile *tf)
37{ 37{
38 ide_hwif_t *hwif = drive->hwif;
39 struct ide_taskfile *tf = &task->tf;
40 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
41
42 if (task->tf_flags & IDE_TFLAG_FLAGGED)
43 HIHI = 0xFF;
44
45#ifdef DEBUG 38#ifdef DEBUG
46 printk("%s: tf: feat 0x%02x nsect 0x%02x lbal 0x%02x " 39 printk("%s: tf: feat 0x%02x nsect 0x%02x lbal 0x%02x "
47 "lbam 0x%02x lbah 0x%02x dev 0x%02x cmd 0x%02x\n", 40 "lbam 0x%02x lbah 0x%02x dev 0x%02x cmd 0x%02x\n",
48 drive->name, tf->feature, tf->nsect, tf->lbal, 41 s, tf->feature, tf->nsect, tf->lbal,
49 tf->lbam, tf->lbah, tf->device, tf->command); 42 tf->lbam, tf->lbah, tf->device, tf->command);
50 printk("%s: hob: nsect 0x%02x lbal 0x%02x " 43 printk("%s: hob: nsect 0x%02x lbal 0x%02x "
51 "lbam 0x%02x lbah 0x%02x\n", 44 "lbam 0x%02x lbah 0x%02x\n",
52 drive->name, tf->hob_nsect, tf->hob_lbal, 45 s, tf->hob_nsect, tf->hob_lbal,
53 tf->hob_lbam, tf->hob_lbah); 46 tf->hob_lbam, tf->hob_lbah);
54#endif 47#endif
55
56 ide_set_irq(drive, 1);
57
58 if ((task->tf_flags & IDE_TFLAG_NO_SELECT_MASK) == 0)
59 SELECT_MASK(drive, 0);
60
61 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
62 hwif->OUTW((tf->hob_data << 8) | tf->data,
63 hwif->io_ports[IDE_DATA_OFFSET]);
64
65 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
66 hwif->OUTB(tf->hob_feature, hwif->io_ports[IDE_FEATURE_OFFSET]);
67 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
68 hwif->OUTB(tf->hob_nsect, hwif->io_ports[IDE_NSECTOR_OFFSET]);
69 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
70 hwif->OUTB(tf->hob_lbal, hwif->io_ports[IDE_SECTOR_OFFSET]);
71 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
72 hwif->OUTB(tf->hob_lbam, hwif->io_ports[IDE_LCYL_OFFSET]);
73 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
74 hwif->OUTB(tf->hob_lbah, hwif->io_ports[IDE_HCYL_OFFSET]);
75
76 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
77 hwif->OUTB(tf->feature, hwif->io_ports[IDE_FEATURE_OFFSET]);
78 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
79 hwif->OUTB(tf->nsect, hwif->io_ports[IDE_NSECTOR_OFFSET]);
80 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
81 hwif->OUTB(tf->lbal, hwif->io_ports[IDE_SECTOR_OFFSET]);
82 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
83 hwif->OUTB(tf->lbam, hwif->io_ports[IDE_LCYL_OFFSET]);
84 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
85 hwif->OUTB(tf->lbah, hwif->io_ports[IDE_HCYL_OFFSET]);
86
87 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
88 hwif->OUTB((tf->device & HIHI) | drive->select.all,
89 hwif->io_ports[IDE_SELECT_OFFSET]);
90} 48}
91 49
92int taskfile_lib_get_identify (ide_drive_t *drive, u8 *buf) 50int taskfile_lib_get_identify (ide_drive_t *drive, u8 *buf)
@@ -149,14 +107,15 @@ ide_startstop_t do_rw_taskfile (ide_drive_t *drive, ide_task_t *task)
149 if (task->tf_flags & IDE_TFLAG_FLAGGED) 107 if (task->tf_flags & IDE_TFLAG_FLAGGED)
150 task->tf_flags |= IDE_TFLAG_FLAGGED_SET_IN_FLAGS; 108 task->tf_flags |= IDE_TFLAG_FLAGGED_SET_IN_FLAGS;
151 109
152 if ((task->tf_flags & IDE_TFLAG_DMA_PIO_FALLBACK) == 0) 110 if ((task->tf_flags & IDE_TFLAG_DMA_PIO_FALLBACK) == 0) {
153 ide_tf_load(drive, task); 111 ide_tf_dump(drive->name, tf);
112 hwif->tf_load(drive, task);
113 }
154 114
155 switch (task->data_phase) { 115 switch (task->data_phase) {
156 case TASKFILE_MULTI_OUT: 116 case TASKFILE_MULTI_OUT:
157 case TASKFILE_OUT: 117 case TASKFILE_OUT:
158 hwif->OUTBSYNC(drive, tf->command, 118 hwif->OUTBSYNC(drive, tf->command, hwif->io_ports.command_addr);
159 hwif->io_ports[IDE_COMMAND_OFFSET]);
160 ndelay(400); /* FIXME */ 119 ndelay(400); /* FIXME */
161 return pre_task_out_intr(drive, task->rq); 120 return pre_task_out_intr(drive, task->rq);
162 case TASKFILE_MULTI_IN: 121 case TASKFILE_MULTI_IN:
@@ -284,7 +243,8 @@ static u8 wait_drive_not_busy(ide_drive_t *drive)
284 return stat; 243 return stat;
285} 244}
286 245
287static void ide_pio_sector(ide_drive_t *drive, unsigned int write) 246static void ide_pio_sector(ide_drive_t *drive, struct request *rq,
247 unsigned int write)
288{ 248{
289 ide_hwif_t *hwif = drive->hwif; 249 ide_hwif_t *hwif = drive->hwif;
290 struct scatterlist *sg = hwif->sg_table; 250 struct scatterlist *sg = hwif->sg_table;
@@ -324,9 +284,9 @@ static void ide_pio_sector(ide_drive_t *drive, unsigned int write)
324 284
325 /* do the actual data transfer */ 285 /* do the actual data transfer */
326 if (write) 286 if (write)
327 hwif->ata_output_data(drive, buf, SECTOR_WORDS); 287 hwif->output_data(drive, rq, buf, SECTOR_SIZE);
328 else 288 else
329 hwif->ata_input_data(drive, buf, SECTOR_WORDS); 289 hwif->input_data(drive, rq, buf, SECTOR_SIZE);
330 290
331 kunmap_atomic(buf, KM_BIO_SRC_IRQ); 291 kunmap_atomic(buf, KM_BIO_SRC_IRQ);
332#ifdef CONFIG_HIGHMEM 292#ifdef CONFIG_HIGHMEM
@@ -334,13 +294,14 @@ static void ide_pio_sector(ide_drive_t *drive, unsigned int write)
334#endif 294#endif
335} 295}
336 296
337static void ide_pio_multi(ide_drive_t *drive, unsigned int write) 297static void ide_pio_multi(ide_drive_t *drive, struct request *rq,
298 unsigned int write)
338{ 299{
339 unsigned int nsect; 300 unsigned int nsect;
340 301
341 nsect = min_t(unsigned int, drive->hwif->nleft, drive->mult_count); 302 nsect = min_t(unsigned int, drive->hwif->nleft, drive->mult_count);
342 while (nsect--) 303 while (nsect--)
343 ide_pio_sector(drive, write); 304 ide_pio_sector(drive, rq, write);
344} 305}
345 306
346static void ide_pio_datablock(ide_drive_t *drive, struct request *rq, 307static void ide_pio_datablock(ide_drive_t *drive, struct request *rq,
@@ -363,10 +324,10 @@ static void ide_pio_datablock(ide_drive_t *drive, struct request *rq,
363 switch (drive->hwif->data_phase) { 324 switch (drive->hwif->data_phase) {
364 case TASKFILE_MULTI_IN: 325 case TASKFILE_MULTI_IN:
365 case TASKFILE_MULTI_OUT: 326 case TASKFILE_MULTI_OUT:
366 ide_pio_multi(drive, write); 327 ide_pio_multi(drive, rq, write);
367 break; 328 break;
368 default: 329 default:
369 ide_pio_sector(drive, write); 330 ide_pio_sector(drive, rq, write);
370 break; 331 break;
371 } 332 }
372 333
@@ -533,8 +494,7 @@ int ide_raw_taskfile(ide_drive_t *drive, ide_task_t *task, u8 *buf, u16 nsect)
533{ 494{
534 struct request rq; 495 struct request rq;
535 496
536 memset(&rq, 0, sizeof(rq)); 497 blk_rq_init(NULL, &rq);
537 rq.ref_count = 1;
538 rq.cmd_type = REQ_TYPE_ATA_TASKFILE; 498 rq.cmd_type = REQ_TYPE_ATA_TASKFILE;
539 rq.buffer = buf; 499 rq.buffer = buf;
540 500
diff --git a/drivers/ide/ide.c b/drivers/ide/ide.c
index bced02f9f2c3..c758dcb13b14 100644
--- a/drivers/ide/ide.c
+++ b/drivers/ide/ide.c
@@ -94,12 +94,6 @@ DEFINE_MUTEX(ide_cfg_mtx);
94 94
95int noautodma = 0; 95int noautodma = 0;
96 96
97#ifdef CONFIG_BLK_DEV_IDEACPI
98int ide_noacpi = 0;
99int ide_noacpitfs = 1;
100int ide_noacpionboot = 1;
101#endif
102
103ide_hwif_t ide_hwifs[MAX_HWIFS]; /* master data repository */ 97ide_hwif_t ide_hwifs[MAX_HWIFS]; /* master data repository */
104 98
105static void ide_port_init_devices_data(ide_hwif_t *); 99static void ide_port_init_devices_data(ide_hwif_t *);
@@ -293,7 +287,7 @@ EXPORT_SYMBOL_GPL(ide_port_unregister_devices);
293 287
294/** 288/**
295 * ide_unregister - free an IDE interface 289 * ide_unregister - free an IDE interface
296 * @index: index of interface (will change soon to a pointer) 290 * @hwif: IDE interface
297 * 291 *
298 * Perform the final unregister of an IDE interface. At the moment 292 * Perform the final unregister of an IDE interface. At the moment
299 * we don't refcount interfaces so this will also get split up. 293 * we don't refcount interfaces so this will also get split up.
@@ -313,19 +307,16 @@ EXPORT_SYMBOL_GPL(ide_port_unregister_devices);
313 * This is raving bonkers. 307 * This is raving bonkers.
314 */ 308 */
315 309
316void ide_unregister(unsigned int index) 310void ide_unregister(ide_hwif_t *hwif)
317{ 311{
318 ide_hwif_t *hwif, *g; 312 ide_hwif_t *g;
319 ide_hwgroup_t *hwgroup; 313 ide_hwgroup_t *hwgroup;
320 int irq_count = 0; 314 int irq_count = 0;
321 315
322 BUG_ON(index >= MAX_HWIFS);
323
324 BUG_ON(in_interrupt()); 316 BUG_ON(in_interrupt());
325 BUG_ON(irqs_disabled()); 317 BUG_ON(irqs_disabled());
326 mutex_lock(&ide_cfg_mtx); 318 mutex_lock(&ide_cfg_mtx);
327 spin_lock_irq(&ide_lock); 319 spin_lock_irq(&ide_lock);
328 hwif = &ide_hwifs[index];
329 if (!hwif->present) 320 if (!hwif->present)
330 goto abort; 321 goto abort;
331 __ide_port_unregister_devices(hwif); 322 __ide_port_unregister_devices(hwif);
@@ -366,7 +357,7 @@ void ide_unregister(unsigned int index)
366 ide_release_dma_engine(hwif); 357 ide_release_dma_engine(hwif);
367 358
368 /* restore hwif data to pristine status */ 359 /* restore hwif data to pristine status */
369 ide_init_port_data(hwif, index); 360 ide_init_port_data(hwif, hwif->index);
370 361
371abort: 362abort:
372 spin_unlock_irq(&ide_lock); 363 spin_unlock_irq(&ide_lock);
@@ -377,7 +368,7 @@ EXPORT_SYMBOL(ide_unregister);
377 368
378void ide_init_port_hw(ide_hwif_t *hwif, hw_regs_t *hw) 369void ide_init_port_hw(ide_hwif_t *hwif, hw_regs_t *hw)
379{ 370{
380 memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports)); 371 memcpy(&hwif->io_ports, &hw->io_ports, sizeof(hwif->io_ports));
381 hwif->irq = hw->irq; 372 hwif->irq = hw->irq;
382 hwif->chipset = hw->chipset; 373 hwif->chipset = hw->chipset;
383 hwif->gendev.parent = hw->dev; 374 hwif->gendev.parent = hw->dev;
@@ -573,7 +564,7 @@ static int generic_ide_suspend(struct device *dev, pm_message_t mesg)
573 if (!(drive->dn % 2)) 564 if (!(drive->dn % 2))
574 ide_acpi_get_timing(hwif); 565 ide_acpi_get_timing(hwif);
575 566
576 memset(&rq, 0, sizeof(rq)); 567 blk_rq_init(NULL, &rq);
577 memset(&rqpm, 0, sizeof(rqpm)); 568 memset(&rqpm, 0, sizeof(rqpm));
578 memset(&args, 0, sizeof(args)); 569 memset(&args, 0, sizeof(args));
579 rq.cmd_type = REQ_TYPE_PM_SUSPEND; 570 rq.cmd_type = REQ_TYPE_PM_SUSPEND;
@@ -611,7 +602,7 @@ static int generic_ide_resume(struct device *dev)
611 602
612 ide_acpi_exec_tfs(drive); 603 ide_acpi_exec_tfs(drive);
613 604
614 memset(&rq, 0, sizeof(rq)); 605 blk_rq_init(NULL, &rq);
615 memset(&rqpm, 0, sizeof(rqpm)); 606 memset(&rqpm, 0, sizeof(rqpm));
616 memset(&args, 0, sizeof(args)); 607 memset(&args, 0, sizeof(args));
617 rq.cmd_type = REQ_TYPE_PM_RESUME; 608 rq.cmd_type = REQ_TYPE_PM_RESUME;
@@ -837,16 +828,6 @@ static int __init match_parm (char *s, const char *keywords[], int vals[], int m
837 return 0; /* zero = nothing matched */ 828 return 0; /* zero = nothing matched */
838} 829}
839 830
840extern int probe_ali14xx;
841extern int probe_umc8672;
842extern int probe_dtc2278;
843extern int probe_ht6560b;
844extern int probe_qd65xx;
845extern int cmd640_vlb;
846extern int probe_4drives;
847
848static int __initdata is_chipset_set;
849
850/* 831/*
851 * ide_setup() gets called VERY EARLY during initialization, 832 * ide_setup() gets called VERY EARLY during initialization,
852 * to handle kernel "command line" strings beginning with "hdx=" or "ide". 833 * to handle kernel "command line" strings beginning with "hdx=" or "ide".
@@ -855,14 +836,12 @@ static int __initdata is_chipset_set;
855 */ 836 */
856static int __init ide_setup(char *s) 837static int __init ide_setup(char *s)
857{ 838{
858 int i, vals[3];
859 ide_hwif_t *hwif; 839 ide_hwif_t *hwif;
860 ide_drive_t *drive; 840 ide_drive_t *drive;
861 unsigned int hw, unit; 841 unsigned int hw, unit;
842 int vals[3];
862 const char max_drive = 'a' + ((MAX_HWIFS * MAX_DRIVES) - 1); 843 const char max_drive = 'a' + ((MAX_HWIFS * MAX_DRIVES) - 1);
863 const char max_hwif = '0' + (MAX_HWIFS - 1);
864 844
865
866 if (strncmp(s,"hd",2) == 0 && s[2] == '=') /* hd= is for hd.c */ 845 if (strncmp(s,"hd",2) == 0 && s[2] == '=') /* hd= is for hd.c */
867 return 0; /* driver and not us */ 846 return 0; /* driver and not us */
868 847
@@ -878,7 +857,7 @@ static int __init ide_setup(char *s)
878 857
879 printk(" : Enabled support for IDE doublers\n"); 858 printk(" : Enabled support for IDE doublers\n");
880 ide_doubler = 1; 859 ide_doubler = 1;
881 return 1; 860 goto obsolete_option;
882 } 861 }
883#endif /* CONFIG_BLK_DEV_IDEDOUBLER */ 862#endif /* CONFIG_BLK_DEV_IDEDOUBLER */
884 863
@@ -892,17 +871,17 @@ static int __init ide_setup(char *s)
892 if (!strcmp(s, "ide=noacpi")) { 871 if (!strcmp(s, "ide=noacpi")) {
893 //printk(" : Disable IDE ACPI support.\n"); 872 //printk(" : Disable IDE ACPI support.\n");
894 ide_noacpi = 1; 873 ide_noacpi = 1;
895 return 1; 874 goto obsolete_option;
896 } 875 }
897 if (!strcmp(s, "ide=acpigtf")) { 876 if (!strcmp(s, "ide=acpigtf")) {
898 //printk(" : Enable IDE ACPI _GTF support.\n"); 877 //printk(" : Enable IDE ACPI _GTF support.\n");
899 ide_noacpitfs = 0; 878 ide_acpigtf = 1;
900 return 1; 879 goto obsolete_option;
901 } 880 }
902 if (!strcmp(s, "ide=acpionboot")) { 881 if (!strcmp(s, "ide=acpionboot")) {
903 //printk(" : Call IDE ACPI methods on boot.\n"); 882 //printk(" : Call IDE ACPI methods on boot.\n");
904 ide_noacpionboot = 0; 883 ide_acpionboot = 1;
905 return 1; 884 goto obsolete_option;
906 } 885 }
907#endif /* CONFIG_BLK_DEV_IDEACPI */ 886#endif /* CONFIG_BLK_DEV_IDEACPI */
908 887
@@ -912,7 +891,7 @@ static int __init ide_setup(char *s)
912 if (s[0] == 'h' && s[1] == 'd' && s[2] >= 'a' && s[2] <= max_drive) { 891 if (s[0] == 'h' && s[1] == 'd' && s[2] >= 'a' && s[2] <= max_drive) {
913 const char *hd_words[] = { 892 const char *hd_words[] = {
914 "none", "noprobe", "nowerr", "cdrom", "nodma", 893 "none", "noprobe", "nowerr", "cdrom", "nodma",
915 "autotune", "noautotune", "-8", "-9", "-10", 894 "-6", "-7", "-8", "-9", "-10",
916 "noflush", "remap", "remap63", "scsi", NULL }; 895 "noflush", "remap", "remap63", "scsi", NULL };
917 unit = s[2] - 'a'; 896 unit = s[2] - 'a';
918 hw = unit / MAX_DRIVES; 897 hw = unit / MAX_DRIVES;
@@ -927,28 +906,22 @@ static int __init ide_setup(char *s)
927 case -1: /* "none" */ 906 case -1: /* "none" */
928 case -2: /* "noprobe" */ 907 case -2: /* "noprobe" */
929 drive->noprobe = 1; 908 drive->noprobe = 1;
930 goto done; 909 goto obsolete_option;
931 case -3: /* "nowerr" */ 910 case -3: /* "nowerr" */
932 drive->bad_wstat = BAD_R_STAT; 911 drive->bad_wstat = BAD_R_STAT;
933 goto done; 912 goto obsolete_option;
934 case -4: /* "cdrom" */ 913 case -4: /* "cdrom" */
935 drive->present = 1; 914 drive->present = 1;
936 drive->media = ide_cdrom; 915 drive->media = ide_cdrom;
937 /* an ATAPI device ignores DRDY */ 916 /* an ATAPI device ignores DRDY */
938 drive->ready_stat = 0; 917 drive->ready_stat = 0;
939 goto done; 918 goto obsolete_option;
940 case -5: /* nodma */ 919 case -5: /* nodma */
941 drive->nodma = 1; 920 drive->nodma = 1;
942 goto done;
943 case -6: /* "autotune" */
944 drive->autotune = IDE_TUNE_AUTO;
945 goto obsolete_option;
946 case -7: /* "noautotune" */
947 drive->autotune = IDE_TUNE_NOAUTO;
948 goto obsolete_option; 921 goto obsolete_option;
949 case -11: /* noflush */ 922 case -11: /* noflush */
950 drive->noflush = 1; 923 drive->noflush = 1;
951 goto done; 924 goto obsolete_option;
952 case -12: /* "remap" */ 925 case -12: /* "remap" */
953 drive->remap_0_to_1 = 1; 926 drive->remap_0_to_1 = 1;
954 goto obsolete_option; 927 goto obsolete_option;
@@ -966,7 +939,7 @@ static int __init ide_setup(char *s)
966 drive->sect = drive->bios_sect = vals[2]; 939 drive->sect = drive->bios_sect = vals[2];
967 drive->present = 1; 940 drive->present = 1;
968 drive->forced_geom = 1; 941 drive->forced_geom = 1;
969 goto done; 942 goto obsolete_option;
970 default: 943 default:
971 goto bad_option; 944 goto bad_option;
972 } 945 }
@@ -984,126 +957,15 @@ static int __init ide_setup(char *s)
984 idebus_parameter = vals[0]; 957 idebus_parameter = vals[0];
985 } else 958 } else
986 printk(" -- BAD BUS SPEED! Expected value from 20 to 66"); 959 printk(" -- BAD BUS SPEED! Expected value from 20 to 66");
987 goto done; 960 goto obsolete_option;
988 } 961 }
989 /*
990 * Look for interface options: "idex="
991 */
992 if (s[3] >= '0' && s[3] <= max_hwif) {
993 /*
994 * Be VERY CAREFUL changing this: note hardcoded indexes below
995 * (-8, -9, -10) are reserved to ease the hardcoding.
996 */
997 static const char *ide_words[] = {
998 "minus1", "serialize", "minus3", "minus4",
999 "reset", "minus6", "ata66", "minus8", "minus9",
1000 "minus10", "four", "qd65xx", "ht6560b", "cmd640_vlb",
1001 "dtc2278", "umc8672", "ali14xx", NULL };
1002
1003 hw = s[3] - '0';
1004 hwif = &ide_hwifs[hw];
1005 i = match_parm(&s[4], ide_words, vals, 3);
1006
1007 /*
1008 * Cryptic check to ensure chipset not already set for hwif.
1009 * Note: we can't depend on hwif->chipset here.
1010 */
1011 if (i >= -18 && i <= -11) {
1012 /* chipset already specified */
1013 if (is_chipset_set)
1014 goto bad_option;
1015 /* these drivers are for "ide0=" only */
1016 if (hw != 0)
1017 goto bad_hwif;
1018 is_chipset_set = 1;
1019 printk("\n");
1020 }
1021
1022 switch (i) {
1023#ifdef CONFIG_BLK_DEV_ALI14XX
1024 case -17: /* "ali14xx" */
1025 probe_ali14xx = 1;
1026 goto obsolete_option;
1027#endif
1028#ifdef CONFIG_BLK_DEV_UMC8672
1029 case -16: /* "umc8672" */
1030 probe_umc8672 = 1;
1031 goto obsolete_option;
1032#endif
1033#ifdef CONFIG_BLK_DEV_DTC2278
1034 case -15: /* "dtc2278" */
1035 probe_dtc2278 = 1;
1036 goto obsolete_option;
1037#endif
1038#ifdef CONFIG_BLK_DEV_CMD640
1039 case -14: /* "cmd640_vlb" */
1040 cmd640_vlb = 1;
1041 goto obsolete_option;
1042#endif
1043#ifdef CONFIG_BLK_DEV_HT6560B
1044 case -13: /* "ht6560b" */
1045 probe_ht6560b = 1;
1046 goto obsolete_option;
1047#endif
1048#ifdef CONFIG_BLK_DEV_QD65XX
1049 case -12: /* "qd65xx" */
1050 probe_qd65xx = 1;
1051 goto obsolete_option;
1052#endif
1053#ifdef CONFIG_BLK_DEV_4DRIVES
1054 case -11: /* "four" drives on one set of ports */
1055 probe_4drives = 1;
1056 goto obsolete_option;
1057#endif
1058 case -10: /* minus10 */
1059 case -9: /* minus9 */
1060 case -8: /* minus8 */
1061 case -6:
1062 case -4:
1063 case -3:
1064 goto bad_option;
1065 case -7: /* ata66 */
1066#ifdef CONFIG_BLK_DEV_IDEPCI
1067 /*
1068 * Use ATA_CBL_PATA40_SHORT so drive side
1069 * cable detection is also overriden.
1070 */
1071 hwif->cbl = ATA_CBL_PATA40_SHORT;
1072 goto obsolete_option;
1073#else
1074 goto bad_hwif;
1075#endif
1076 case -5: /* "reset" */
1077 hwif->reset = 1;
1078 goto obsolete_option;
1079 case -2: /* "serialize" */
1080 hwif->mate = &ide_hwifs[hw^1];
1081 hwif->mate->mate = hwif;
1082 hwif->serialized = hwif->mate->serialized = 1;
1083 goto obsolete_option;
1084 962
1085 case -1:
1086 case 0:
1087 case 1:
1088 case 2:
1089 case 3:
1090 goto bad_option;
1091 default:
1092 printk(" -- SUPPORT NOT CONFIGURED IN THIS KERNEL\n");
1093 return 1;
1094 }
1095 }
1096bad_option: 963bad_option:
1097 printk(" -- BAD OPTION\n"); 964 printk(" -- BAD OPTION\n");
1098 return 1; 965 return 1;
1099obsolete_option: 966obsolete_option:
1100 printk(" -- OBSOLETE OPTION, WILL BE REMOVED SOON!\n"); 967 printk(" -- OBSOLETE OPTION, WILL BE REMOVED SOON!\n");
1101 return 1; 968 return 1;
1102bad_hwif:
1103 printk("-- NOT SUPPORTED ON ide%d", hw);
1104done:
1105 printk("\n");
1106 return 1;
1107} 969}
1108 970
1109EXPORT_SYMBOL(ide_lock); 971EXPORT_SYMBOL(ide_lock);
@@ -1239,6 +1101,185 @@ static void ide_port_class_release(struct device *portdev)
1239 put_device(&hwif->gendev); 1101 put_device(&hwif->gendev);
1240} 1102}
1241 1103
1104int ide_vlb_clk;
1105EXPORT_SYMBOL_GPL(ide_vlb_clk);
1106
1107module_param_named(vlb_clock, ide_vlb_clk, int, 0);
1108MODULE_PARM_DESC(vlb_clock, "VLB clock frequency (in MHz)");
1109
1110int ide_pci_clk;
1111EXPORT_SYMBOL_GPL(ide_pci_clk);
1112
1113module_param_named(pci_clock, ide_pci_clk, int, 0);
1114MODULE_PARM_DESC(pci_clock, "PCI bus clock frequency (in MHz)");
1115
1116static int ide_set_dev_param_mask(const char *s, struct kernel_param *kp)
1117{
1118 int a, b, i, j = 1;
1119 unsigned int *dev_param_mask = (unsigned int *)kp->arg;
1120
1121 if (sscanf(s, "%d.%d:%d", &a, &b, &j) != 3 &&
1122 sscanf(s, "%d.%d", &a, &b) != 2)
1123 return -EINVAL;
1124
1125 i = a * MAX_DRIVES + b;
1126
1127 if (i >= MAX_HWIFS * MAX_DRIVES || j < 0 || j > 1)
1128 return -EINVAL;
1129
1130 if (j)
1131 *dev_param_mask |= (1 << i);
1132 else
1133 *dev_param_mask &= (1 << i);
1134
1135 return 0;
1136}
1137
1138static unsigned int ide_nodma;
1139
1140module_param_call(nodma, ide_set_dev_param_mask, NULL, &ide_nodma, 0);
1141MODULE_PARM_DESC(nodma, "disallow DMA for a device");
1142
1143static unsigned int ide_noflush;
1144
1145module_param_call(noflush, ide_set_dev_param_mask, NULL, &ide_noflush, 0);
1146MODULE_PARM_DESC(noflush, "disable flush requests for a device");
1147
1148static unsigned int ide_noprobe;
1149
1150module_param_call(noprobe, ide_set_dev_param_mask, NULL, &ide_noprobe, 0);
1151MODULE_PARM_DESC(noprobe, "skip probing for a device");
1152
1153static unsigned int ide_nowerr;
1154
1155module_param_call(nowerr, ide_set_dev_param_mask, NULL, &ide_nowerr, 0);
1156MODULE_PARM_DESC(nowerr, "ignore the WRERR_STAT bit for a device");
1157
1158static unsigned int ide_cdroms;
1159
1160module_param_call(cdrom, ide_set_dev_param_mask, NULL, &ide_cdroms, 0);
1161MODULE_PARM_DESC(cdrom, "force device as a CD-ROM");
1162
1163struct chs_geom {
1164 unsigned int cyl;
1165 u8 head;
1166 u8 sect;
1167};
1168
1169static unsigned int ide_disks;
1170static struct chs_geom ide_disks_chs[MAX_HWIFS * MAX_DRIVES];
1171
1172static int ide_set_disk_chs(const char *str, struct kernel_param *kp)
1173{
1174 int a, b, c = 0, h = 0, s = 0, i, j = 1;
1175
1176 if (sscanf(str, "%d.%d:%d,%d,%d", &a, &b, &c, &h, &s) != 5 &&
1177 sscanf(str, "%d.%d:%d", &a, &b, &j) != 3)
1178 return -EINVAL;
1179
1180 i = a * MAX_DRIVES + b;
1181
1182 if (i >= MAX_HWIFS * MAX_DRIVES || j < 0 || j > 1)
1183 return -EINVAL;
1184
1185 if (c > INT_MAX || h > 255 || s > 255)
1186 return -EINVAL;
1187
1188 if (j)
1189 ide_disks |= (1 << i);
1190 else
1191 ide_disks &= (1 << i);
1192
1193 ide_disks_chs[i].cyl = c;
1194 ide_disks_chs[i].head = h;
1195 ide_disks_chs[i].sect = s;
1196
1197 return 0;
1198}
1199
1200module_param_call(chs, ide_set_disk_chs, NULL, NULL, 0);
1201MODULE_PARM_DESC(chs, "force device as a disk (using CHS)");
1202
1203static void ide_dev_apply_params(ide_drive_t *drive)
1204{
1205 int i = drive->hwif->index * MAX_DRIVES + drive->select.b.unit;
1206
1207 if (ide_nodma & (1 << i)) {
1208 printk(KERN_INFO "ide: disallowing DMA for %s\n", drive->name);
1209 drive->nodma = 1;
1210 }
1211 if (ide_noflush & (1 << i)) {
1212 printk(KERN_INFO "ide: disabling flush requests for %s\n",
1213 drive->name);
1214 drive->noflush = 1;
1215 }
1216 if (ide_noprobe & (1 << i)) {
1217 printk(KERN_INFO "ide: skipping probe for %s\n", drive->name);
1218 drive->noprobe = 1;
1219 }
1220 if (ide_nowerr & (1 << i)) {
1221 printk(KERN_INFO "ide: ignoring the WRERR_STAT bit for %s\n",
1222 drive->name);
1223 drive->bad_wstat = BAD_R_STAT;
1224 }
1225 if (ide_cdroms & (1 << i)) {
1226 printk(KERN_INFO "ide: forcing %s as a CD-ROM\n", drive->name);
1227 drive->present = 1;
1228 drive->media = ide_cdrom;
1229 /* an ATAPI device ignores DRDY */
1230 drive->ready_stat = 0;
1231 }
1232 if (ide_disks & (1 << i)) {
1233 drive->cyl = drive->bios_cyl = ide_disks_chs[i].cyl;
1234 drive->head = drive->bios_head = ide_disks_chs[i].head;
1235 drive->sect = drive->bios_sect = ide_disks_chs[i].sect;
1236 drive->forced_geom = 1;
1237 printk(KERN_INFO "ide: forcing %s as a disk (%d/%d/%d)\n",
1238 drive->name,
1239 drive->cyl, drive->head, drive->sect);
1240 drive->present = 1;
1241 drive->media = ide_disk;
1242 drive->ready_stat = READY_STAT;
1243 }
1244}
1245
1246static unsigned int ide_ignore_cable;
1247
1248static int ide_set_ignore_cable(const char *s, struct kernel_param *kp)
1249{
1250 int i, j = 1;
1251
1252 if (sscanf(s, "%d:%d", &i, &j) != 2 && sscanf(s, "%d", &i) != 1)
1253 return -EINVAL;
1254
1255 if (i >= MAX_HWIFS || j < 0 || j > 1)
1256 return -EINVAL;
1257
1258 if (j)
1259 ide_ignore_cable |= (1 << i);
1260 else
1261 ide_ignore_cable &= (1 << i);
1262
1263 return 0;
1264}
1265
1266module_param_call(ignore_cable, ide_set_ignore_cable, NULL, NULL, 0);
1267MODULE_PARM_DESC(ignore_cable, "ignore cable detection");
1268
1269void ide_port_apply_params(ide_hwif_t *hwif)
1270{
1271 int i;
1272
1273 if (ide_ignore_cable & (1 << hwif->index)) {
1274 printk(KERN_INFO "ide: ignoring cable detection for %s\n",
1275 hwif->name);
1276 hwif->cbl = ATA_CBL_PATA40_SHORT;
1277 }
1278
1279 for (i = 0; i < MAX_DRIVES; i++)
1280 ide_dev_apply_params(&hwif->drives[i]);
1281}
1282
1242/* 1283/*
1243 * This is gets invoked once during initialization, to set *everything* up 1284 * This is gets invoked once during initialization, to set *everything* up
1244 */ 1285 */
@@ -1305,11 +1346,6 @@ int __init init_module (void)
1305 1346
1306void __exit cleanup_module (void) 1347void __exit cleanup_module (void)
1307{ 1348{
1308 int index;
1309
1310 for (index = 0; index < MAX_HWIFS; ++index)
1311 ide_unregister(index);
1312
1313 proc_ide_destroy(); 1349 proc_ide_destroy();
1314 1350
1315 class_destroy(ide_port_class); 1351 class_destroy(ide_port_class);
diff --git a/drivers/ide/legacy/ali14xx.c b/drivers/ide/legacy/ali14xx.c
index 6efbf947c6db..90c65cf97448 100644
--- a/drivers/ide/legacy/ali14xx.c
+++ b/drivers/ide/legacy/ali14xx.c
@@ -116,7 +116,7 @@ static void ali14xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
116 int time1, time2; 116 int time1, time2;
117 u8 param1, param2, param3, param4; 117 u8 param1, param2, param3, param4;
118 unsigned long flags; 118 unsigned long flags;
119 int bus_speed = system_bus_clock(); 119 int bus_speed = ide_vlb_clk ? ide_vlb_clk : system_bus_clock();
120 120
121 /* calculate timing, according to PIO mode */ 121 /* calculate timing, according to PIO mode */
122 time1 = ide_pio_cycle_time(drive, pio); 122 time1 = ide_pio_cycle_time(drive, pio);
@@ -202,7 +202,7 @@ static const struct ide_port_info ali14xx_port_info = {
202 .name = DRV_NAME, 202 .name = DRV_NAME,
203 .chipset = ide_ali14xx, 203 .chipset = ide_ali14xx,
204 .port_ops = &ali14xx_port_ops, 204 .port_ops = &ali14xx_port_ops,
205 .host_flags = IDE_HFLAG_NO_DMA | IDE_HFLAG_NO_AUTOTUNE, 205 .host_flags = IDE_HFLAG_NO_DMA,
206 .pio_mask = ATA_PIO4, 206 .pio_mask = ATA_PIO4,
207}; 207};
208 208
@@ -220,7 +220,7 @@ static int __init ali14xx_probe(void)
220 return ide_legacy_device_add(&ali14xx_port_info, 0); 220 return ide_legacy_device_add(&ali14xx_port_info, 0);
221} 221}
222 222
223int probe_ali14xx; 223static int probe_ali14xx;
224 224
225module_param_named(probe, probe_ali14xx, bool, 0); 225module_param_named(probe, probe_ali14xx, bool, 0);
226MODULE_PARM_DESC(probe, "probe for ALI M14xx chipsets"); 226MODULE_PARM_DESC(probe, "probe for ALI M14xx chipsets");
diff --git a/drivers/ide/legacy/buddha.c b/drivers/ide/legacy/buddha.c
index f51433bce8e4..5c730e4dd735 100644
--- a/drivers/ide/legacy/buddha.c
+++ b/drivers/ide/legacy/buddha.c
@@ -102,7 +102,7 @@ static int buddha_ack_intr(ide_hwif_t *hwif)
102{ 102{
103 unsigned char ch; 103 unsigned char ch;
104 104
105 ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]); 105 ch = z_readb(hwif->io_ports.irq_addr);
106 if (!(ch & 0x80)) 106 if (!(ch & 0x80))
107 return 0; 107 return 0;
108 return 1; 108 return 1;
@@ -112,9 +112,9 @@ static int xsurf_ack_intr(ide_hwif_t *hwif)
112{ 112{
113 unsigned char ch; 113 unsigned char ch;
114 114
115 ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]); 115 ch = z_readb(hwif->io_ports.irq_addr);
116 /* X-Surf needs a 0 written to IRQ register to ensure ISA bit A11 stays at 0 */ 116 /* X-Surf needs a 0 written to IRQ register to ensure ISA bit A11 stays at 0 */
117 z_writeb(0, hwif->io_ports[IDE_IRQ_OFFSET]); 117 z_writeb(0, hwif->io_ports.irq_addr);
118 if (!(ch & 0x80)) 118 if (!(ch & 0x80))
119 return 0; 119 return 0;
120 return 1; 120 return 1;
@@ -128,13 +128,13 @@ static void __init buddha_setup_ports(hw_regs_t *hw, unsigned long base,
128 128
129 memset(hw, 0, sizeof(*hw)); 129 memset(hw, 0, sizeof(*hw));
130 130
131 hw->io_ports[IDE_DATA_OFFSET] = base; 131 hw->io_ports.data_addr = base;
132 132
133 for (i = 1; i < 8; i++) 133 for (i = 1; i < 8; i++)
134 hw->io_ports[i] = base + 2 + i * 4; 134 hw->io_ports_array[i] = base + 2 + i * 4;
135 135
136 hw->io_ports[IDE_CONTROL_OFFSET] = ctl; 136 hw->io_ports.ctl_addr = ctl;
137 hw->io_ports[IDE_IRQ_OFFSET] = irq_port; 137 hw->io_ports.irq_addr = irq_port;
138 138
139 hw->irq = IRQ_AMIGA_PORTS; 139 hw->irq = IRQ_AMIGA_PORTS;
140 hw->ack_intr = ack_intr; 140 hw->ack_intr = ack_intr;
diff --git a/drivers/ide/legacy/dtc2278.c b/drivers/ide/legacy/dtc2278.c
index f7c4ad1c57c0..af791a02a120 100644
--- a/drivers/ide/legacy/dtc2278.c
+++ b/drivers/ide/legacy/dtc2278.c
@@ -101,8 +101,7 @@ static const struct ide_port_info dtc2278_port_info __initdata = {
101 IDE_HFLAG_IO_32BIT | 101 IDE_HFLAG_IO_32BIT |
102 /* disallow ->io_32bit changes */ 102 /* disallow ->io_32bit changes */
103 IDE_HFLAG_NO_IO_32BIT | 103 IDE_HFLAG_NO_IO_32BIT |
104 IDE_HFLAG_NO_DMA | 104 IDE_HFLAG_NO_DMA,
105 IDE_HFLAG_NO_AUTOTUNE,
106 .pio_mask = ATA_PIO4, 105 .pio_mask = ATA_PIO4,
107}; 106};
108 107
@@ -131,7 +130,7 @@ static int __init dtc2278_probe(void)
131 return ide_legacy_device_add(&dtc2278_port_info, 0); 130 return ide_legacy_device_add(&dtc2278_port_info, 0);
132} 131}
133 132
134int probe_dtc2278 = 0; 133static int probe_dtc2278;
135 134
136module_param_named(probe, probe_dtc2278, bool, 0); 135module_param_named(probe, probe_dtc2278, bool, 0);
137MODULE_PARM_DESC(probe, "probe for DTC2278xx chipsets"); 136MODULE_PARM_DESC(probe, "probe for DTC2278xx chipsets");
diff --git a/drivers/ide/legacy/falconide.c b/drivers/ide/legacy/falconide.c
index 5c19c422c5cc..83555ca513b5 100644
--- a/drivers/ide/legacy/falconide.c
+++ b/drivers/ide/legacy/falconide.c
@@ -44,18 +44,40 @@
44int falconide_intr_lock; 44int falconide_intr_lock;
45EXPORT_SYMBOL(falconide_intr_lock); 45EXPORT_SYMBOL(falconide_intr_lock);
46 46
47static void falconide_input_data(ide_drive_t *drive, struct request *rq,
48 void *buf, unsigned int len)
49{
50 unsigned long data_addr = drive->hwif->io_ports.data_addr;
51
52 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
53 return insw(data_addr, buf, (len + 1) / 2);
54
55 insw_swapw(data_addr, buf, (len + 1) / 2);
56}
57
58static void falconide_output_data(ide_drive_t *drive, struct request *rq,
59 void *buf, unsigned int len)
60{
61 unsigned long data_addr = drive->hwif->io_ports.data_addr;
62
63 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
64 return outsw(data_adr, buf, (len + 1) / 2);
65
66 outsw_swapw(data_addr, buf, (len + 1) / 2);
67}
68
47static void __init falconide_setup_ports(hw_regs_t *hw) 69static void __init falconide_setup_ports(hw_regs_t *hw)
48{ 70{
49 int i; 71 int i;
50 72
51 memset(hw, 0, sizeof(*hw)); 73 memset(hw, 0, sizeof(*hw));
52 74
53 hw->io_ports[IDE_DATA_OFFSET] = ATA_HD_BASE; 75 hw->io_ports.data_addr = ATA_HD_BASE;
54 76
55 for (i = 1; i < 8; i++) 77 for (i = 1; i < 8; i++)
56 hw->io_ports[i] = ATA_HD_BASE + 1 + i * 4; 78 hw->io_ports_array[i] = ATA_HD_BASE + 1 + i * 4;
57 79
58 hw->io_ports[IDE_CONTROL_OFFSET] = ATA_HD_BASE + ATA_HD_CONTROL; 80 hw->io_ports.ctl_addr = ATA_HD_BASE + ATA_HD_CONTROL;
59 81
60 hw->irq = IRQ_MFP_IDE; 82 hw->irq = IRQ_MFP_IDE;
61 hw->ack_intr = NULL; 83 hw->ack_intr = NULL;
@@ -90,6 +112,10 @@ static int __init falconide_init(void)
90 ide_init_port_data(hwif, index); 112 ide_init_port_data(hwif, index);
91 ide_init_port_hw(hwif, &hw); 113 ide_init_port_hw(hwif, &hw);
92 114
115 /* Atari has a byte-swapped IDE interface */
116 hwif->input_data = falconide_input_data;
117 hwif->output_data = falconide_output_data;
118
93 ide_get_lock(NULL, NULL); 119 ide_get_lock(NULL, NULL);
94 ide_device_add(idx, NULL); 120 ide_device_add(idx, NULL);
95 ide_release_lock(); 121 ide_release_lock();
diff --git a/drivers/ide/legacy/gayle.c b/drivers/ide/legacy/gayle.c
index a0c9601bdaf0..a9c2593a898c 100644
--- a/drivers/ide/legacy/gayle.c
+++ b/drivers/ide/legacy/gayle.c
@@ -63,6 +63,8 @@
63#define GAYLE_HAS_CONTROL_REG (!ide_doubler) 63#define GAYLE_HAS_CONTROL_REG (!ide_doubler)
64#define GAYLE_IDEREG_SIZE (ide_doubler ? 0x1000 : 0x2000) 64#define GAYLE_IDEREG_SIZE (ide_doubler ? 0x1000 : 0x2000)
65int ide_doubler = 0; /* support IDE doublers? */ 65int ide_doubler = 0; /* support IDE doublers? */
66module_param_named(doubler, ide_doubler, bool, 0);
67MODULE_PARM_DESC(doubler, "enable support for IDE doublers");
66#endif /* CONFIG_BLK_DEV_IDEDOUBLER */ 68#endif /* CONFIG_BLK_DEV_IDEDOUBLER */
67 69
68 70
@@ -74,7 +76,7 @@ static int gayle_ack_intr_a4000(ide_hwif_t *hwif)
74{ 76{
75 unsigned char ch; 77 unsigned char ch;
76 78
77 ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]); 79 ch = z_readb(hwif->io_ports.irq_addr);
78 if (!(ch & GAYLE_IRQ_IDE)) 80 if (!(ch & GAYLE_IRQ_IDE))
79 return 0; 81 return 0;
80 return 1; 82 return 1;
@@ -84,11 +86,11 @@ static int gayle_ack_intr_a1200(ide_hwif_t *hwif)
84{ 86{
85 unsigned char ch; 87 unsigned char ch;
86 88
87 ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]); 89 ch = z_readb(hwif->io_ports.irq_addr);
88 if (!(ch & GAYLE_IRQ_IDE)) 90 if (!(ch & GAYLE_IRQ_IDE))
89 return 0; 91 return 0;
90 (void)z_readb(hwif->io_ports[IDE_STATUS_OFFSET]); 92 (void)z_readb(hwif->io_ports.status_addr);
91 z_writeb(0x7c, hwif->io_ports[IDE_IRQ_OFFSET]); 93 z_writeb(0x7c, hwif->io_ports.irq_addr);
92 return 1; 94 return 1;
93} 95}
94 96
@@ -100,13 +102,13 @@ static void __init gayle_setup_ports(hw_regs_t *hw, unsigned long base,
100 102
101 memset(hw, 0, sizeof(*hw)); 103 memset(hw, 0, sizeof(*hw));
102 104
103 hw->io_ports[IDE_DATA_OFFSET] = base; 105 hw->io_ports.data_addr = base;
104 106
105 for (i = 1; i < 8; i++) 107 for (i = 1; i < 8; i++)
106 hw->io_ports[i] = base + 2 + i * 4; 108 hw->io_ports_array[i] = base + 2 + i * 4;
107 109
108 hw->io_ports[IDE_CONTROL_OFFSET] = ctl; 110 hw->io_ports.ctl_addr = ctl;
109 hw->io_ports[IDE_IRQ_OFFSET] = irq_port; 111 hw->io_ports.irq_addr = irq_port;
110 112
111 hw->irq = IRQ_AMIGA_PORTS; 113 hw->irq = IRQ_AMIGA_PORTS;
112 hw->ack_intr = ack_intr; 114 hw->ack_intr = ack_intr;
diff --git a/drivers/ide/legacy/ht6560b.c b/drivers/ide/legacy/ht6560b.c
index 702d8deb5780..4fe516df9f74 100644
--- a/drivers/ide/legacy/ht6560b.c
+++ b/drivers/ide/legacy/ht6560b.c
@@ -157,8 +157,8 @@ static void ht6560b_selectproc (ide_drive_t *drive)
157 /* 157 /*
158 * Set timing for this drive: 158 * Set timing for this drive:
159 */ 159 */
160 outb(timing, hwif->io_ports[IDE_SELECT_OFFSET]); 160 outb(timing, hwif->io_ports.device_addr);
161 (void)inb(hwif->io_ports[IDE_STATUS_OFFSET]); 161 (void)inb(hwif->io_ports.status_addr);
162#ifdef DEBUG 162#ifdef DEBUG
163 printk("ht6560b: %s: select=%#x timing=%#x\n", 163 printk("ht6560b: %s: select=%#x timing=%#x\n",
164 drive->name, select, timing); 164 drive->name, select, timing);
@@ -212,8 +212,8 @@ static u8 ht_pio2timings(ide_drive_t *drive, const u8 pio)
212{ 212{
213 int active_time, recovery_time; 213 int active_time, recovery_time;
214 int active_cycles, recovery_cycles; 214 int active_cycles, recovery_cycles;
215 int bus_speed = system_bus_clock(); 215 int bus_speed = ide_vlb_clk ? ide_vlb_clk : system_bus_clock();
216 216
217 if (pio) { 217 if (pio) {
218 unsigned int cycle_time; 218 unsigned int cycle_time;
219 219
@@ -323,7 +323,7 @@ static void __init ht6560b_port_init_devs(ide_hwif_t *hwif)
323 hwif->drives[1].drive_data = t; 323 hwif->drives[1].drive_data = t;
324} 324}
325 325
326int probe_ht6560b = 0; 326static int probe_ht6560b;
327 327
328module_param_named(probe, probe_ht6560b, bool, 0); 328module_param_named(probe, probe_ht6560b, bool, 0);
329MODULE_PARM_DESC(probe, "probe for HT6560B chipset"); 329MODULE_PARM_DESC(probe, "probe for HT6560B chipset");
@@ -340,7 +340,6 @@ static const struct ide_port_info ht6560b_port_info __initdata = {
340 .port_ops = &ht6560b_port_ops, 340 .port_ops = &ht6560b_port_ops,
341 .host_flags = IDE_HFLAG_SERIALIZE | /* is this needed? */ 341 .host_flags = IDE_HFLAG_SERIALIZE | /* is this needed? */
342 IDE_HFLAG_NO_DMA | 342 IDE_HFLAG_NO_DMA |
343 IDE_HFLAG_NO_AUTOTUNE |
344 IDE_HFLAG_ABUSE_PREFETCH, 343 IDE_HFLAG_ABUSE_PREFETCH,
345 .pio_mask = ATA_PIO4, 344 .pio_mask = ATA_PIO4,
346}; 345};
diff --git a/drivers/ide/legacy/ide-4drives.c b/drivers/ide/legacy/ide-4drives.c
index 17f94d0cb539..ecae916a3385 100644
--- a/drivers/ide/legacy/ide-4drives.c
+++ b/drivers/ide/legacy/ide-4drives.c
@@ -6,7 +6,7 @@
6 6
7#define DRV_NAME "ide-4drives" 7#define DRV_NAME "ide-4drives"
8 8
9int probe_4drives; 9static int probe_4drives;
10 10
11module_param_named(probe, probe_4drives, bool, 0); 11module_param_named(probe, probe_4drives, bool, 0);
12MODULE_PARM_DESC(probe, "probe for generic IDE chipset with 4 drives/port"); 12MODULE_PARM_DESC(probe, "probe for generic IDE chipset with 4 drives/port");
diff --git a/drivers/ide/legacy/ide-cs.c b/drivers/ide/legacy/ide-cs.c
index 855e157b18d3..aa2ea3deac85 100644
--- a/drivers/ide/legacy/ide-cs.c
+++ b/drivers/ide/legacy/ide-cs.c
@@ -140,8 +140,8 @@ static void ide_detach(struct pcmcia_device *link)
140 140
141 ide_release(link); 141 ide_release(link);
142 142
143 release_region(hwif->io_ports[IDE_CONTROL_OFFSET], 1); 143 release_region(hwif->io_ports.ctl_addr, 1);
144 release_region(hwif->io_ports[IDE_DATA_OFFSET], 8); 144 release_region(hwif->io_ports.data_addr, 8);
145 145
146 kfree(info); 146 kfree(info);
147} /* ide_detach */ 147} /* ide_detach */
@@ -183,11 +183,7 @@ static ide_hwif_t *idecs_register(unsigned long io, unsigned long ctl,
183 183
184 i = hwif->index; 184 i = hwif->index;
185 185
186 if (hwif->present) 186 ide_init_port_data(hwif, i);
187 ide_unregister(i);
188 else
189 ide_init_port_data(hwif, i);
190
191 ide_init_port_hw(hwif, &hw); 187 ide_init_port_hw(hwif, &hw);
192 hwif->port_ops = &idecs_port_ops; 188 hwif->port_ops = &idecs_port_ops;
193 189
@@ -390,7 +386,7 @@ void ide_release(struct pcmcia_device *link)
390 if (info->ndev) { 386 if (info->ndev) {
391 /* FIXME: if this fails we need to queue the cleanup somehow 387 /* FIXME: if this fails we need to queue the cleanup somehow
392 -- need to investigate the required PCMCIA magic */ 388 -- need to investigate the required PCMCIA magic */
393 ide_unregister(hwif->index); 389 ide_unregister(hwif);
394 } 390 }
395 info->ndev = 0; 391 info->ndev = 0;
396 392
diff --git a/drivers/ide/legacy/ide_platform.c b/drivers/ide/legacy/ide_platform.c
index 822f48b05c70..d3bc3f24e05d 100644
--- a/drivers/ide/legacy/ide_platform.c
+++ b/drivers/ide/legacy/ide_platform.c
@@ -30,14 +30,14 @@ static void __devinit plat_ide_setup_ports(hw_regs_t *hw,
30 unsigned long port = (unsigned long)base; 30 unsigned long port = (unsigned long)base;
31 int i; 31 int i;
32 32
33 hw->io_ports[IDE_DATA_OFFSET] = port; 33 hw->io_ports.data_addr = port;
34 34
35 port += (1 << pdata->ioport_shift); 35 port += (1 << pdata->ioport_shift);
36 for (i = IDE_ERROR_OFFSET; i <= IDE_STATUS_OFFSET; 36 for (i = 1; i <= 7;
37 i++, port += (1 << pdata->ioport_shift)) 37 i++, port += (1 << pdata->ioport_shift))
38 hw->io_ports[i] = port; 38 hw->io_ports_array[i] = port;
39 39
40 hw->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)ctrl; 40 hw->io_ports.ctl_addr = (unsigned long)ctrl;
41 41
42 hw->irq = irq; 42 hw->irq = irq;
43 43
@@ -101,8 +101,10 @@ static int __devinit plat_ide_probe(struct platform_device *pdev)
101 101
102 ide_init_port_hw(hwif, &hw); 102 ide_init_port_hw(hwif, &hw);
103 103
104 if (mmio) 104 if (mmio) {
105 hwif->host_flags = IDE_HFLAG_MMIO;
105 default_hwif_mmiops(hwif); 106 default_hwif_mmiops(hwif);
107 }
106 108
107 idx[0] = hwif->index; 109 idx[0] = hwif->index;
108 110
@@ -120,7 +122,7 @@ static int __devexit plat_ide_remove(struct platform_device *pdev)
120{ 122{
121 ide_hwif_t *hwif = pdev->dev.driver_data; 123 ide_hwif_t *hwif = pdev->dev.driver_data;
122 124
123 ide_unregister(hwif->index); 125 ide_unregister(hwif);
124 126
125 return 0; 127 return 0;
126} 128}
diff --git a/drivers/ide/legacy/macide.c b/drivers/ide/legacy/macide.c
index 26546d0afc7f..1f527bbf8d96 100644
--- a/drivers/ide/legacy/macide.c
+++ b/drivers/ide/legacy/macide.c
@@ -72,9 +72,9 @@ static void __init macide_setup_ports(hw_regs_t *hw, unsigned long base,
72 memset(hw, 0, sizeof(*hw)); 72 memset(hw, 0, sizeof(*hw));
73 73
74 for (i = 0; i < 8; i++) 74 for (i = 0; i < 8; i++)
75 hw->io_ports[i] = base + i * 4; 75 hw->io_ports_array[i] = base + i * 4;
76 76
77 hw->io_ports[IDE_CONTROL_OFFSET] = base + IDE_CONTROL; 77 hw->io_ports.ctl_addr = base + IDE_CONTROL;
78 78
79 hw->irq = irq; 79 hw->irq = irq;
80 hw->ack_intr = ack_intr; 80 hw->ack_intr = ack_intr;
diff --git a/drivers/ide/legacy/q40ide.c b/drivers/ide/legacy/q40ide.c
index f23999dd3d46..6f535d00e638 100644
--- a/drivers/ide/legacy/q40ide.c
+++ b/drivers/ide/legacy/q40ide.c
@@ -36,23 +36,6 @@ static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
36 PCIDE_BASE6 */ 36 PCIDE_BASE6 */
37}; 37};
38 38
39
40 /*
41 * Offsets from one of the above bases
42 */
43
44/* used to do addr translation here but it is easier to do in setup ports */
45/*#define IDE_OFF_B(x) ((unsigned long)Q40_ISA_IO_B((IDE_##x##_OFFSET)))*/
46
47#define IDE_OFF_B(x) ((unsigned long)((IDE_##x##_OFFSET)))
48#define IDE_OFF_W(x) ((unsigned long)((IDE_##x##_OFFSET)))
49
50static const int pcide_offsets[IDE_NR_PORTS] = {
51 IDE_OFF_W(DATA), IDE_OFF_B(ERROR), IDE_OFF_B(NSECTOR), IDE_OFF_B(SECTOR),
52 IDE_OFF_B(LCYL), IDE_OFF_B(HCYL), 6 /*IDE_OFF_B(CURRENT)*/, IDE_OFF_B(STATUS),
53 518/*IDE_OFF(CMD)*/
54};
55
56static int q40ide_default_irq(unsigned long base) 39static int q40ide_default_irq(unsigned long base)
57{ 40{
58 switch (base) { 41 switch (base) {
@@ -68,29 +51,48 @@ static int q40ide_default_irq(unsigned long base)
68/* 51/*
69 * Addresses are pretranslated for Q40 ISA access. 52 * Addresses are pretranslated for Q40 ISA access.
70 */ 53 */
71void q40_ide_setup_ports ( hw_regs_t *hw, 54static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
72 unsigned long base, int *offsets,
73 unsigned long ctrl, unsigned long intr,
74 ide_ack_intr_t *ack_intr, 55 ide_ack_intr_t *ack_intr,
75 int irq) 56 int irq)
76{ 57{
77 int i;
78
79 memset(hw, 0, sizeof(hw_regs_t)); 58 memset(hw, 0, sizeof(hw_regs_t));
80 for (i = 0; i < IDE_NR_PORTS; i++) { 59 /* BIG FAT WARNING:
81 /* BIG FAT WARNING: 60 assumption: only DATA port is ever used in 16 bit mode */
82 assumption: only DATA port is ever used in 16 bit mode */ 61 hw->io_ports.data_addr = Q40_ISA_IO_W(base);
83 if ( i==0 ) 62 hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
84 hw->io_ports[i] = Q40_ISA_IO_W(base + offsets[i]); 63 hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
85 else 64 hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
86 hw->io_ports[i] = Q40_ISA_IO_B(base + offsets[i]); 65 hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
87 } 66 hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
67 hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
68 hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
69 hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
88 70
89 hw->irq = irq; 71 hw->irq = irq;
90 hw->ack_intr = ack_intr; 72 hw->ack_intr = ack_intr;
91} 73}
92 74
75static void q40ide_input_data(ide_drive_t *drive, struct request *rq,
76 void *buf, unsigned int len)
77{
78 unsigned long data_addr = drive->hwif->io_ports.data_addr;
79
80 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
81 return insw(data_addr, buf, (len + 1) / 2);
93 82
83 insw_swapw(data_addr, buf, (len + 1) / 2);
84}
85
86static void q40ide_output_data(ide_drive_t *drive, struct request *rq,
87 void *buf, unsigned int len)
88{
89 unsigned long data_addr = drive->hwif->io_ports.data_addr;
90
91 if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
92 return outsw(data_addr, buf, (len + 1) / 2);
93
94 outsw_swapw(data_addr, buf, (len + 1) / 2);
95}
94 96
95/* 97/*
96 * the static array is needed to have the name reported in /proc/ioports, 98 * the static array is needed to have the name reported in /proc/ioports,
@@ -131,9 +133,8 @@ static int __init q40ide_init(void)
131 release_region(pcide_bases[i], 8); 133 release_region(pcide_bases[i], 8);
132 continue; 134 continue;
133 } 135 }
134 q40_ide_setup_ports(&hw,(unsigned long) pcide_bases[i], (int *)pcide_offsets, 136 q40_ide_setup_ports(&hw, pcide_bases[i],
135 pcide_bases[i]+0x206, 137 NULL,
136 0, NULL,
137// m68kide_iops, 138// m68kide_iops,
138 q40ide_default_irq(pcide_bases[i])); 139 q40ide_default_irq(pcide_bases[i]));
139 140
@@ -142,6 +143,10 @@ static int __init q40ide_init(void)
142 ide_init_port_data(hwif, hwif->index); 143 ide_init_port_data(hwif, hwif->index);
143 ide_init_port_hw(hwif, &hw); 144 ide_init_port_hw(hwif, &hw);
144 145
146 /* Q40 has a byte-swapped IDE interface */
147 hwif->input_data = q40ide_input_data;
148 hwif->output_data = q40ide_output_data;
149
145 idx[i] = hwif->index; 150 idx[i] = hwif->index;
146 } 151 }
147 } 152 }
diff --git a/drivers/ide/legacy/qd65xx.c b/drivers/ide/legacy/qd65xx.c
index 15a99aae0cf9..6424af154325 100644
--- a/drivers/ide/legacy/qd65xx.c
+++ b/drivers/ide/legacy/qd65xx.c
@@ -11,11 +11,7 @@
11 * 11 *
12 * QDI QD6500/QD6580 EIDE controller fast support 12 * QDI QD6500/QD6580 EIDE controller fast support
13 * 13 *
14 * Please set local bus speed using kernel parameter idebus
15 * for example, "idebus=33" stands for 33Mhz VLbus
16 * To activate controller support, use "ide0=qd65xx" 14 * To activate controller support, use "ide0=qd65xx"
17 * To enable tuning, use "hda=autotune hdb=autotune"
18 * To enable 2nd channel tuning (qd6580 only), use "hdc=autotune hdd=autotune"
19 */ 15 */
20 16
21/* 17/*
@@ -114,17 +110,18 @@ static void qd65xx_select(ide_drive_t *drive)
114 110
115static u8 qd6500_compute_timing (ide_hwif_t *hwif, int active_time, int recovery_time) 111static u8 qd6500_compute_timing (ide_hwif_t *hwif, int active_time, int recovery_time)
116{ 112{
117 u8 active_cycle,recovery_cycle; 113 int clk = ide_vlb_clk ? ide_vlb_clk : system_bus_clock();
114 u8 act_cyc, rec_cyc;
118 115
119 if (system_bus_clock()<=33) { 116 if (clk <= 33) {
120 active_cycle = 9 - IDE_IN(active_time * system_bus_clock() / 1000 + 1, 2, 9); 117 act_cyc = 9 - IDE_IN(active_time * clk / 1000 + 1, 2, 9);
121 recovery_cycle = 15 - IDE_IN(recovery_time * system_bus_clock() / 1000 + 1, 0, 15); 118 rec_cyc = 15 - IDE_IN(recovery_time * clk / 1000 + 1, 0, 15);
122 } else { 119 } else {
123 active_cycle = 8 - IDE_IN(active_time * system_bus_clock() / 1000 + 1, 1, 8); 120 act_cyc = 8 - IDE_IN(active_time * clk / 1000 + 1, 1, 8);
124 recovery_cycle = 18 - IDE_IN(recovery_time * system_bus_clock() / 1000 + 1, 3, 18); 121 rec_cyc = 18 - IDE_IN(recovery_time * clk / 1000 + 1, 3, 18);
125 } 122 }
126 123
127 return((recovery_cycle<<4) | 0x08 | active_cycle); 124 return (rec_cyc << 4) | 0x08 | act_cyc;
128} 125}
129 126
130/* 127/*
@@ -135,10 +132,13 @@ static u8 qd6500_compute_timing (ide_hwif_t *hwif, int active_time, int recovery
135 132
136static u8 qd6580_compute_timing (int active_time, int recovery_time) 133static u8 qd6580_compute_timing (int active_time, int recovery_time)
137{ 134{
138 u8 active_cycle = 17 - IDE_IN(active_time * system_bus_clock() / 1000 + 1, 2, 17); 135 int clk = ide_vlb_clk ? ide_vlb_clk : system_bus_clock();
139 u8 recovery_cycle = 15 - IDE_IN(recovery_time * system_bus_clock() / 1000 + 1, 2, 15); 136 u8 act_cyc, rec_cyc;
140 137
141 return((recovery_cycle<<4) | active_cycle); 138 act_cyc = 17 - IDE_IN(active_time * clk / 1000 + 1, 2, 17);
139 rec_cyc = 15 - IDE_IN(recovery_time * clk / 1000 + 1, 2, 15);
140
141 return (rec_cyc << 4) | act_cyc;
142} 142}
143 143
144/* 144/*
@@ -322,8 +322,7 @@ static const struct ide_port_info qd65xx_port_info __initdata = {
322 .name = DRV_NAME, 322 .name = DRV_NAME,
323 .chipset = ide_qd65xx, 323 .chipset = ide_qd65xx,
324 .host_flags = IDE_HFLAG_IO_32BIT | 324 .host_flags = IDE_HFLAG_IO_32BIT |
325 IDE_HFLAG_NO_DMA | 325 IDE_HFLAG_NO_DMA,
326 IDE_HFLAG_NO_AUTOTUNE,
327 .pio_mask = ATA_PIO4, 326 .pio_mask = ATA_PIO4,
328}; 327};
329 328
@@ -399,7 +398,7 @@ static int __init qd_probe(int base)
399 return rc; 398 return rc;
400} 399}
401 400
402int probe_qd65xx = 0; 401static int probe_qd65xx;
403 402
404module_param_named(probe, probe_qd65xx, bool, 0); 403module_param_named(probe, probe_qd65xx, bool, 0);
405MODULE_PARM_DESC(probe, "probe for QD65xx chipsets"); 404MODULE_PARM_DESC(probe, "probe for QD65xx chipsets");
diff --git a/drivers/ide/legacy/umc8672.c b/drivers/ide/legacy/umc8672.c
index 17d515329fe0..b54a14a57755 100644
--- a/drivers/ide/legacy/umc8672.c
+++ b/drivers/ide/legacy/umc8672.c
@@ -130,7 +130,7 @@ static const struct ide_port_info umc8672_port_info __initdata = {
130 .name = DRV_NAME, 130 .name = DRV_NAME,
131 .chipset = ide_umc8672, 131 .chipset = ide_umc8672,
132 .port_ops = &umc8672_port_ops, 132 .port_ops = &umc8672_port_ops,
133 .host_flags = IDE_HFLAG_NO_DMA | IDE_HFLAG_NO_AUTOTUNE, 133 .host_flags = IDE_HFLAG_NO_DMA,
134 .pio_mask = ATA_PIO4, 134 .pio_mask = ATA_PIO4,
135}; 135};
136 136
@@ -158,7 +158,7 @@ static int __init umc8672_probe(void)
158 return ide_legacy_device_add(&umc8672_port_info, 0); 158 return ide_legacy_device_add(&umc8672_port_info, 0);
159} 159}
160 160
161int probe_umc8672; 161static int probe_umc8672;
162 162
163module_param_named(probe, probe_umc8672, bool, 0); 163module_param_named(probe, probe_umc8672, bool, 0);
164MODULE_PARM_DESC(probe, "probe for UMC8672 chipset"); 164MODULE_PARM_DESC(probe, "probe for UMC8672 chipset");
diff --git a/drivers/ide/mips/au1xxx-ide.c b/drivers/ide/mips/au1xxx-ide.c
index 3485a310c95b..1a6c27b32498 100644
--- a/drivers/ide/mips/au1xxx-ide.c
+++ b/drivers/ide/mips/au1xxx-ide.c
@@ -48,8 +48,6 @@
48 48
49static _auide_hwif auide_hwif; 49static _auide_hwif auide_hwif;
50 50
51static int auide_ddma_init(_auide_hwif *auide);
52
53#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA) 51#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
54 52
55void auide_insw(unsigned long port, void *addr, u32 count) 53void auide_insw(unsigned long port, void *addr, u32 count)
@@ -88,6 +86,17 @@ void auide_outsw(unsigned long port, void *addr, u32 count)
88 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp); 86 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
89} 87}
90 88
89static void au1xxx_input_data(ide_drive_t *drive, struct request *rq,
90 void *buf, unsigned int len)
91{
92 auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
93}
94
95static void au1xxx_output_data(ide_drive_t *drive, struct request *rq,
96 void *buf, unsigned int len)
97{
98 auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
99}
91#endif 100#endif
92 101
93static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio) 102static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
@@ -359,7 +368,7 @@ static void auide_ddma_rx_callback(int irq, void *param)
359static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags) 368static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
360{ 369{
361 dev->dev_id = dev_id; 370 dev->dev_id = dev_id;
362 dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR; 371 dev->dev_physaddr = (u32)IDE_PHYS_ADDR;
363 dev->dev_intlevel = 0; 372 dev->dev_intlevel = 0;
364 dev->dev_intpolarity = 0; 373 dev->dev_intpolarity = 0;
365 dev->dev_tsize = tsize; 374 dev->dev_tsize = tsize;
@@ -397,7 +406,7 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
397 dbdev_tab_t source_dev_tab, target_dev_tab; 406 dbdev_tab_t source_dev_tab, target_dev_tab;
398 u32 dev_id, tsize, devwidth, flags; 407 u32 dev_id, tsize, devwidth, flags;
399 408
400 dev_id = AU1XXX_ATA_DDMA_REQ; 409 dev_id = IDE_DDMA_REQ;
401 410
402 tsize = 8; /* 1 */ 411 tsize = 8; /* 1 */
403 devwidth = 32; /* 16 */ 412 devwidth = 32; /* 16 */
@@ -502,15 +511,14 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
502static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif) 511static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
503{ 512{
504 int i; 513 int i;
505 unsigned long *ata_regs = hw->io_ports; 514 unsigned long *ata_regs = hw->io_ports_array;
506 515
507 /* FIXME? */ 516 /* FIXME? */
508 for (i = 0; i < IDE_CONTROL_OFFSET; i++) { 517 for (i = 0; i < 8; i++)
509 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET); 518 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
510 }
511 519
512 /* set the Alternative Status register */ 520 /* set the Alternative Status register */
513 *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET); 521 *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
514} 522}
515 523
516static const struct ide_port_ops au1xxx_port_ops = { 524static const struct ide_port_ops au1xxx_port_ops = {
@@ -599,8 +607,8 @@ static int au_ide_probe(struct device *dev)
599 */ 607 */
600 608
601#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA 609#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
602 hwif->INSW = auide_insw; 610 hwif->input_data = au1xxx_input_data;
603 hwif->OUTSW = auide_outsw; 611 hwif->output_data = au1xxx_output_data;
604#endif 612#endif
605 hwif->select_data = 0; /* no chipset-specific code */ 613 hwif->select_data = 0; /* no chipset-specific code */
606 hwif->config_data = 0; /* no chipset-specific code */ 614 hwif->config_data = 0; /* no chipset-specific code */
@@ -627,7 +635,7 @@ static int au_ide_remove(struct device *dev)
627 ide_hwif_t *hwif = dev_get_drvdata(dev); 635 ide_hwif_t *hwif = dev_get_drvdata(dev);
628 _auide_hwif *ahwif = &auide_hwif; 636 _auide_hwif *ahwif = &auide_hwif;
629 637
630 ide_unregister(hwif->index); 638 ide_unregister(hwif);
631 639
632 iounmap((void *)ahwif->regbase); 640 iounmap((void *)ahwif->regbase);
633 641
diff --git a/drivers/ide/mips/swarm.c b/drivers/ide/mips/swarm.c
index 112fe566bb93..712d17bdd470 100644
--- a/drivers/ide/mips/swarm.c
+++ b/drivers/ide/mips/swarm.c
@@ -109,14 +109,15 @@ static int __devinit swarm_ide_probe(struct device *dev)
109 base = ioremap(offset, size); 109 base = ioremap(offset, size);
110 110
111 /* Setup MMIO ops. */ 111 /* Setup MMIO ops. */
112 hwif->host_flags = IDE_HFLAG_MMIO;
112 default_hwif_mmiops(hwif); 113 default_hwif_mmiops(hwif);
113 114
114 hwif->chipset = ide_generic; 115 hwif->chipset = ide_generic;
115 116
116 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) 117 for (i = 0; i <= 7; i++)
117 hwif->io_ports[i] = 118 hwif->io_ports_array[i] =
118 (unsigned long)(base + ((0x1f0 + i) << 5)); 119 (unsigned long)(base + ((0x1f0 + i) << 5));
119 hwif->io_ports[IDE_CONTROL_OFFSET] = 120 hwif->io_ports.ctl_addr =
120 (unsigned long)(base + (0x3f6 << 5)); 121 (unsigned long)(base + (0x3f6 << 5));
121 hwif->irq = K_INT_GB_IDE; 122 hwif->irq = K_INT_GB_IDE;
122 123
diff --git a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c
index ca16f37f9486..7f46c224b7c4 100644
--- a/drivers/ide/pci/aec62xx.c
+++ b/drivers/ide/pci/aec62xx.c
@@ -140,7 +140,7 @@ static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
140 140
141static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name) 141static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
142{ 142{
143 int bus_speed = system_bus_clock(); 143 int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock();
144 144
145 if (bus_speed <= 33) 145 if (bus_speed <= 33)
146 pci_set_drvdata(dev, (void *) aec6xxx_33_base); 146 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c
index b5a3bc33e167..b36a22b8c213 100644
--- a/drivers/ide/pci/alim15x3.c
+++ b/drivers/ide/pci/alim15x3.c
@@ -38,8 +38,6 @@
38 38
39#include <asm/io.h> 39#include <asm/io.h>
40 40
41#define DISPLAY_ALI_TIMINGS
42
43/* 41/*
44 * ALi devices are not plug in. Otherwise these static values would 42 * ALi devices are not plug in. Otherwise these static values would
45 * need to go. They ought to go away anyway 43 * need to go. They ought to go away anyway
@@ -49,236 +47,6 @@ static u8 m5229_revision;
49static u8 chip_is_1543c_e; 47static u8 chip_is_1543c_e;
50static struct pci_dev *isa_dev; 48static struct pci_dev *isa_dev;
51 49
52#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
53#include <linux/stat.h>
54#include <linux/proc_fs.h>
55
56static u8 ali_proc = 0;
57
58static struct pci_dev *bmide_dev;
59
60static char *fifo[4] = {
61 "FIFO Off",
62 "FIFO On ",
63 "DMA mode",
64 "PIO mode" };
65
66static char *udmaT[8] = {
67 "1.5T",
68 " 2T",
69 "2.5T",
70 " 3T",
71 "3.5T",
72 " 4T",
73 " 6T",
74 " 8T"
75};
76
77static char *channel_status[8] = {
78 "OK ",
79 "busy ",
80 "DRQ ",
81 "DRQ busy ",
82 "error ",
83 "error busy ",
84 "error DRQ ",
85 "error DRQ busy"
86};
87
88/**
89 * ali_get_info - generate proc file for ALi IDE
90 * @buffer: buffer to fill
91 * @addr: address of user start in buffer
92 * @offset: offset into 'file'
93 * @count: buffer count
94 *
95 * Walks the Ali devices and outputs summary data on the tuning and
96 * anything else that will help with debugging
97 */
98
99static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
100{
101 unsigned long bibma;
102 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
103 char *q, *p = buffer;
104
105 /* fetch rev. */
106 pci_read_config_byte(bmide_dev, 0x08, &rev);
107 if (rev >= 0xc1) /* M1543C or newer */
108 udmaT[7] = " ???";
109 else
110 fifo[3] = " ??? ";
111
112 /* first fetch bibma: */
113
114 bibma = pci_resource_start(bmide_dev, 4);
115
116 /*
117 * at that point bibma+0x2 et bibma+0xa are byte
118 * registers to investigate:
119 */
120 c0 = inb(bibma + 0x02);
121 c1 = inb(bibma + 0x0a);
122
123 p += sprintf(p,
124 "\n Ali M15x3 Chipset.\n");
125 p += sprintf(p,
126 " ------------------\n");
127 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
128 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
129
130 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
131 p += sprintf(p,
132 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
133 (reg53h & 0x02) ? "Yes" : "No ",
134 (reg53h & 0x01) ? "Yes" : "No " );
135 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
136 p += sprintf(p,
137 "FIFO Status: contains %d Words, runs%s%s\n\n",
138 (reg53h & 0x3f),
139 (reg53h & 0x40) ? " OVERWR" : "",
140 (reg53h & 0x80) ? " OVERRD." : "." );
141
142 p += sprintf(p,
143 "-------------------primary channel"
144 "-------------------secondary channel"
145 "---------\n\n");
146
147 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
148 p += sprintf(p,
149 "channel status: %s"
150 " %s\n",
151 (reg53h & 0x20) ? "On " : "Off",
152 (reg53h & 0x10) ? "On " : "Off" );
153
154 p += sprintf(p,
155 "both channels togth: %s"
156 " %s\n",
157 (c0&0x80) ? "No " : "Yes",
158 (c1&0x80) ? "No " : "Yes" );
159
160 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
161 p += sprintf(p,
162 "Channel state: %s %s\n",
163 channel_status[reg53h & 0x07],
164 channel_status[(reg53h & 0x70) >> 4] );
165
166 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
167 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
168 p += sprintf(p,
169 "Add. Setup Timing: %dT"
170 " %dT\n",
171 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
172 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
173
174 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
175 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
176 p += sprintf(p,
177 "Command Act. Count: %dT"
178 " %dT\n"
179 "Command Rec. Count: %dT"
180 " %dT\n\n",
181 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
182 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
183 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
184 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
185
186 p += sprintf(p,
187 "----------------drive0-----------drive1"
188 "------------drive0-----------drive1------\n\n");
189 p += sprintf(p,
190 "DMA enabled: %s %s"
191 " %s %s\n",
192 (c0&0x20) ? "Yes" : "No ",
193 (c0&0x40) ? "Yes" : "No ",
194 (c1&0x20) ? "Yes" : "No ",
195 (c1&0x40) ? "Yes" : "No " );
196
197 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
198 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
199 q = "FIFO threshold: %2d Words %2d Words"
200 " %2d Words %2d Words\n";
201 if (rev < 0xc1) {
202 if ((rev == 0x20) &&
203 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
204 p += sprintf(p, q, 8, 8, 8, 8);
205 } else {
206 p += sprintf(p, q,
207 (reg5xh & 0x03) + 12,
208 ((reg5xh & 0x30)>>4) + 12,
209 (reg5yh & 0x03) + 12,
210 ((reg5yh & 0x30)>>4) + 12 );
211 }
212 } else {
213 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
214 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
215 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
216 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
217 p += sprintf(p, q, t1, t2, t3, t4);
218 }
219
220#if 0
221 p += sprintf(p,
222 "FIFO threshold: %2d Words %2d Words"
223 " %2d Words %2d Words\n",
224 (reg5xh & 0x03) + 12,
225 ((reg5xh & 0x30)>>4) + 12,
226 (reg5yh & 0x03) + 12,
227 ((reg5yh & 0x30)>>4) + 12 );
228#endif
229
230 p += sprintf(p,
231 "FIFO mode: %s %s %s %s\n",
232 fifo[((reg5xh & 0x0c) >> 2)],
233 fifo[((reg5xh & 0xc0) >> 6)],
234 fifo[((reg5yh & 0x0c) >> 2)],
235 fifo[((reg5yh & 0xc0) >> 6)] );
236
237 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
238 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
239 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
240 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
241
242 p += sprintf(p,/*
243 "------------------drive0-----------drive1"
244 "------------drive0-----------drive1------\n")*/
245 "Dt RW act. Cnt %2dT %2dT"
246 " %2dT %2dT\n"
247 "Dt RW rec. Cnt %2dT %2dT"
248 " %2dT %2dT\n\n",
249 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
250 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
251 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
252 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
253 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
254 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
255 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
256 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
257
258 p += sprintf(p,
259 "-----------------------------------UDMA Timings"
260 "--------------------------------\n\n");
261
262 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
263 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
264 p += sprintf(p,
265 "UDMA: %s %s"
266 " %s %s\n"
267 "UDMA timings: %s %s"
268 " %s %s\n\n",
269 (reg5xh & 0x08) ? "OK" : "No",
270 (reg5xh & 0x80) ? "OK" : "No",
271 (reg5yh & 0x08) ? "OK" : "No",
272 (reg5yh & 0x80) ? "OK" : "No",
273 udmaT[(reg5xh & 0x07)],
274 udmaT[(reg5xh & 0x70) >> 4],
275 udmaT[reg5yh & 0x07],
276 udmaT[(reg5yh & 0x70) >> 4] );
277
278 return p-buffer; /* => must be less than 4k! */
279}
280#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
281
282/** 50/**
283 * ali_set_pio_mode - set host controller for PIO mode 51 * ali_set_pio_mode - set host controller for PIO mode
284 * @drive: drive 52 * @drive: drive
@@ -294,7 +62,7 @@ static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
294 int s_time, a_time, c_time; 62 int s_time, a_time, c_time;
295 u8 s_clc, a_clc, r_clc; 63 u8 s_clc, a_clc, r_clc;
296 unsigned long flags; 64 unsigned long flags;
297 int bus_speed = system_bus_clock(); 65 int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock();
298 int port = hwif->channel ? 0x5c : 0x58; 66 int port = hwif->channel ? 0x5c : 0x58;
299 int portFIFO = hwif->channel ? 0x55 : 0x54; 67 int portFIFO = hwif->channel ? 0x55 : 0x54;
300 u8 cd_dma_fifo = 0; 68 u8 cd_dma_fifo = 0;
@@ -465,14 +233,6 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c
465 233
466 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL); 234 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
467 235
468#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
469 if (!ali_proc) {
470 ali_proc = 1;
471 bmide_dev = dev;
472 ide_pci_create_host_proc("ali", ali_get_info);
473 }
474#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
475
476 local_irq_save(flags); 236 local_irq_save(flags);
477 237
478 if (m5229_revision < 0xC2) { 238 if (m5229_revision < 0xC2) {
diff --git a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c
index f7c883808b02..efcf54338be7 100644
--- a/drivers/ide/pci/amd74xx.c
+++ b/drivers/ide/pci/amd74xx.c
@@ -179,7 +179,7 @@ static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev,
179 * Determine the system bus clock. 179 * Determine the system bus clock.
180 */ 180 */
181 181
182 amd_clock = system_bus_clock() * 1000; 182 amd_clock = (ide_pci_clk ? ide_pci_clk : system_bus_clock()) * 1000;
183 183
184 switch (amd_clock) { 184 switch (amd_clock) {
185 case 33000: amd_clock = 33333; break; 185 case 33000: amd_clock = 33333; break;
diff --git a/drivers/ide/pci/cmd640.c b/drivers/ide/pci/cmd640.c
index 25c2f1bd175f..aaf38109eaec 100644
--- a/drivers/ide/pci/cmd640.c
+++ b/drivers/ide/pci/cmd640.c
@@ -111,10 +111,7 @@
111 111
112#define DRV_NAME "cmd640" 112#define DRV_NAME "cmd640"
113 113
114/* 114static int cmd640_vlb;
115 * This flag is set in ide.c by the parameter: ide0=cmd640_vlb
116 */
117int cmd640_vlb;
118 115
119/* 116/*
120 * CMD640 specific registers definition. 117 * CMD640 specific registers definition.
@@ -350,12 +347,12 @@ static int __init secondary_port_responding(void)
350 347
351 spin_lock_irqsave(&cmd640_lock, flags); 348 spin_lock_irqsave(&cmd640_lock, flags);
352 349
353 outb_p(0x0a, 0x170 + IDE_SELECT_OFFSET); /* select drive0 */ 350 outb_p(0x0a, 0x176); /* select drive0 */
354 udelay(100); 351 udelay(100);
355 if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x0a) { 352 if ((inb_p(0x176) & 0x1f) != 0x0a) {
356 outb_p(0x1a, 0x170 + IDE_SELECT_OFFSET); /* select drive1 */ 353 outb_p(0x1a, 0x176); /* select drive1 */
357 udelay(100); 354 udelay(100);
358 if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x1a) { 355 if ((inb_p(0x176) & 0x1f) != 0x1a) {
359 spin_unlock_irqrestore(&cmd640_lock, flags); 356 spin_unlock_irqrestore(&cmd640_lock, flags);
360 return 0; /* nothing responded */ 357 return 0; /* nothing responded */
361 } 358 }
@@ -383,6 +380,7 @@ static void cmd640_dump_regs(void)
383} 380}
384#endif 381#endif
385 382
383#ifndef CONFIG_BLK_DEV_CMD640_ENHANCED
386/* 384/*
387 * Check whether prefetch is on for a drive, 385 * Check whether prefetch is on for a drive,
388 * and initialize the unmask flags for safe operation. 386 * and initialize the unmask flags for safe operation.
@@ -403,9 +401,7 @@ static void __init check_prefetch(ide_drive_t *drive, unsigned int index)
403 drive->no_io_32bit = 0; 401 drive->no_io_32bit = 0;
404 } 402 }
405} 403}
406 404#else
407#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
408
409/* 405/*
410 * Sets prefetch mode for a drive. 406 * Sets prefetch mode for a drive.
411 */ 407 */
@@ -462,34 +458,6 @@ static inline u8 pack_nibbles(u8 upper, u8 lower)
462} 458}
463 459
464/* 460/*
465 * This routine retrieves the initial drive timings from the chipset.
466 */
467static void __init retrieve_drive_counts(unsigned int index)
468{
469 u8 b;
470
471 /*
472 * Get the internal setup timing, and convert to clock count
473 */
474 b = get_cmd640_reg(arttim_regs[index]) & ~0x3f;
475 switch (b) {
476 case 0x00: b = 4; break;
477 case 0x80: b = 3; break;
478 case 0x40: b = 2; break;
479 default: b = 5; break;
480 }
481 setup_counts[index] = b;
482
483 /*
484 * Get the active/recovery counts
485 */
486 b = get_cmd640_reg(drwtim_regs[index]);
487 active_counts[index] = (b >> 4) ? (b >> 4) : 0x10;
488 recovery_counts[index] = (b & 0x0f) ? (b & 0x0f) : 0x10;
489}
490
491
492/*
493 * This routine writes the prepared setup/active/recovery counts 461 * This routine writes the prepared setup/active/recovery counts
494 * for a drive into the cmd640 chipset registers to active them. 462 * for a drive into the cmd640 chipset registers to active them.
495 */ 463 */
@@ -555,7 +523,14 @@ static void cmd640_set_mode(ide_drive_t *drive, unsigned int index,
555{ 523{
556 int setup_time, active_time, recovery_time, clock_time; 524 int setup_time, active_time, recovery_time, clock_time;
557 u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count; 525 u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count;
558 int bus_speed = system_bus_clock(); 526 int bus_speed;
527
528 if (cmd640_vlb && ide_vlb_clk)
529 bus_speed = ide_vlb_clk;
530 else if (!cmd640_vlb && ide_pci_clk)
531 bus_speed = ide_pci_clk;
532 else
533 bus_speed = system_bus_clock();
559 534
560 if (pio_mode > 5) 535 if (pio_mode > 5)
561 pio_mode = 5; 536 pio_mode = 5;
@@ -679,7 +654,6 @@ static const struct ide_port_info cmd640_port_info __initdata = {
679 .chipset = ide_cmd640, 654 .chipset = ide_cmd640,
680 .host_flags = IDE_HFLAG_SERIALIZE | 655 .host_flags = IDE_HFLAG_SERIALIZE |
681 IDE_HFLAG_NO_DMA | 656 IDE_HFLAG_NO_DMA |
682 IDE_HFLAG_NO_AUTOTUNE |
683 IDE_HFLAG_ABUSE_PREFETCH | 657 IDE_HFLAG_ABUSE_PREFETCH |
684 IDE_HFLAG_ABUSE_FAST_DEVSEL, 658 IDE_HFLAG_ABUSE_FAST_DEVSEL,
685#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED 659#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
@@ -862,29 +836,16 @@ static int __init cmd640x_init(void)
862 } 836 }
863 837
864#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED 838#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
865 if (drive->autotune || ((index > 1) && second_port_toggled)) { 839 /*
866 /* 840 * Reset timing to the slowest speed and turn off prefetch.
867 * Reset timing to the slowest speed and turn off 841 * This way, the drive identify code has a better chance.
868 * prefetch. This way, the drive identify code has 842 */
869 * a better chance. 843 setup_counts [index] = 4; /* max possible */
870 */ 844 active_counts [index] = 16; /* max possible */
871 setup_counts [index] = 4; /* max possible */ 845 recovery_counts [index] = 16; /* max possible */
872 active_counts [index] = 16; /* max possible */ 846 program_drive_counts(drive, index);
873 recovery_counts [index] = 16; /* max possible */ 847 set_prefetch_mode(drive, index, 0);
874 program_drive_counts(drive, index); 848 printk("cmd640: drive%d timings/prefetch cleared\n", index);
875 set_prefetch_mode(drive, index, 0);
876 printk("cmd640: drive%d timings/prefetch cleared\n", index);
877 } else {
878 /*
879 * Record timings/prefetch without changing them.
880 * This preserves any prior BIOS setup.
881 */
882 retrieve_drive_counts (index);
883 check_prefetch(drive, index);
884 printk("cmd640: drive%d timings/prefetch(%s) preserved",
885 index, drive->no_io_32bit ? "off" : "on");
886 display_clocks(index);
887 }
888#else 849#else
889 /* 850 /*
890 * Set the drive unmask flags to match the prefetch setting 851 * Set the drive unmask flags to match the prefetch setting
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
index 006fb62656bc..08674711d089 100644
--- a/drivers/ide/pci/cmd64x.c
+++ b/drivers/ide/pci/cmd64x.c
@@ -68,8 +68,8 @@ static u8 quantize_timing(int timing, int quant)
68 */ 68 */
69static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) 69static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
70{ 70{
71 struct pci_dev *dev = to_pci_dev(drive->hwif->dev); 71 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
72 int clock_time = 1000 / system_bus_clock(); 72 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : system_bus_clock());
73 u8 cycle_count, active_count, recovery_count, drwtim; 73 u8 cycle_count, active_count, recovery_count, drwtim;
74 static const u8 recovery_values[] = 74 static const u8 recovery_values[] =
75 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; 75 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
@@ -128,7 +128,7 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
128 ide_pio_timings[pio].active_time); 128 ide_pio_timings[pio].active_time);
129 129
130 setup_count = quantize_timing(ide_pio_timings[pio].setup_time, 130 setup_count = quantize_timing(ide_pio_timings[pio].setup_time,
131 1000 / system_bus_clock()); 131 1000 / (ide_pci_clk ? ide_pci_clk : system_bus_clock()));
132 132
133 /* 133 /*
134 * The primary channel has individual address setup timing registers 134 * The primary channel has individual address setup timing registers
diff --git a/drivers/ide/pci/cy82c693.c b/drivers/ide/pci/cy82c693.c
index e30eae5a01b6..77cc22c2ad45 100644
--- a/drivers/ide/pci/cy82c693.c
+++ b/drivers/ide/pci/cy82c693.c
@@ -18,8 +18,6 @@
18 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA 18 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
19 * - this is my first linux driver, so there's probably a lot of room 19 * - this is my first linux driver, so there's probably a lot of room
20 * for optimizations and bug fixing, so feel free to do it. 20 * for optimizations and bug fixing, so feel free to do it.
21 * - use idebus=xx parameter to set PCI bus speed - needed to calc
22 * timings for PIO modes (default will be 40)
23 * - if using PIO mode it's a good idea to set the PIO mode and 21 * - if using PIO mode it's a good idea to set the PIO mode and
24 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda 22 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
25 * - I had some problems with my IBM DHEA with PIO modes < 2 23 * - I had some problems with my IBM DHEA with PIO modes < 2
@@ -136,7 +134,7 @@ static int calc_clk(int time, int bus_speed)
136static void compute_clocks(u8 pio, pio_clocks_t *p_pclk) 134static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
137{ 135{
138 int clk1, clk2; 136 int clk1, clk2;
139 int bus_speed = system_bus_clock(); /* get speed of PCI bus */ 137 int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock();
140 138
141 /* we don't check against CY82C693's min and max speed, 139 /* we don't check against CY82C693's min and max speed,
142 * so you can play with the idebus=xx parameter 140 * so you can play with the idebus=xx parameter
diff --git a/drivers/ide/pci/delkin_cb.c b/drivers/ide/pci/delkin_cb.c
index c7b7e0483287..b9e457996d0e 100644
--- a/drivers/ide/pci/delkin_cb.c
+++ b/drivers/ide/pci/delkin_cb.c
@@ -87,11 +87,7 @@ delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id)
87 87
88 i = hwif->index; 88 i = hwif->index;
89 89
90 if (hwif->present) 90 ide_init_port_data(hwif, i);
91 ide_unregister(i);
92 else
93 ide_init_port_data(hwif, i);
94
95 ide_init_port_hw(hwif, &hw); 91 ide_init_port_hw(hwif, &hw);
96 hwif->port_ops = &delkin_cb_port_ops; 92 hwif->port_ops = &delkin_cb_port_ops;
97 93
@@ -123,8 +119,7 @@ delkin_cb_remove (struct pci_dev *dev)
123{ 119{
124 ide_hwif_t *hwif = pci_get_drvdata(dev); 120 ide_hwif_t *hwif = pci_get_drvdata(dev);
125 121
126 if (hwif) 122 ide_unregister(hwif);
127 ide_unregister(hwif->index);
128 123
129 pci_release_regions(dev); 124 pci_release_regions(dev);
130 pci_disable_device(dev); 125 pci_disable_device(dev);
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index 8c02961d0188..c929dadaaaff 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -760,7 +760,7 @@ static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
760 } 760 }
761 } else 761 } else
762 outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 762 outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
763 hwif->io_ports[IDE_CONTROL_OFFSET]); 763 hwif->io_ports.ctl_addr);
764} 764}
765 765
766/* 766/*
diff --git a/drivers/ide/pci/ns87415.c b/drivers/ide/pci/ns87415.c
index e1b0c9a9ab9c..fec4955f449b 100644
--- a/drivers/ide/pci/ns87415.c
+++ b/drivers/ide/pci/ns87415.c
@@ -63,6 +63,48 @@ static u8 superio_ide_inb (unsigned long port)
63 return inb(port); 63 return inb(port);
64} 64}
65 65
66static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
67{
68 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
69 struct ide_taskfile *tf = &task->tf;
70
71 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
72 u16 data = inw(io_ports->data_addr);
73
74 tf->data = data & 0xff;
75 tf->hob_data = (data >> 8) & 0xff;
76 }
77
78 /* be sure we're looking at the low order bits */
79 outb(drive->ctl & ~0x80, io_ports->ctl_addr);
80
81 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
82 tf->nsect = inb(io_ports->nsect_addr);
83 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
84 tf->lbal = inb(io_ports->lbal_addr);
85 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
86 tf->lbam = inb(io_ports->lbam_addr);
87 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
88 tf->lbah = inb(io_ports->lbah_addr);
89 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
90 tf->device = superio_ide_inb(io_ports->device_addr);
91
92 if (task->tf_flags & IDE_TFLAG_LBA48) {
93 outb(drive->ctl | 0x80, io_ports->ctl_addr);
94
95 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
96 tf->hob_feature = inb(io_ports->feature_addr);
97 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
98 tf->hob_nsect = inb(io_ports->nsect_addr);
99 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
100 tf->hob_lbal = inb(io_ports->lbal_addr);
101 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
102 tf->hob_lbam = inb(io_ports->lbam_addr);
103 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
104 tf->hob_lbah = inb(io_ports->lbah_addr);
105 }
106}
107
66static void __devinit superio_ide_init_iops (struct hwif_s *hwif) 108static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
67{ 109{
68 struct pci_dev *pdev = to_pci_dev(hwif->dev); 110 struct pci_dev *pdev = to_pci_dev(hwif->dev);
@@ -72,14 +114,16 @@ static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
72 base = pci_resource_start(pdev, port * 2) & ~3; 114 base = pci_resource_start(pdev, port * 2) & ~3;
73 dmabase = pci_resource_start(pdev, 4) & ~3; 115 dmabase = pci_resource_start(pdev, 4) & ~3;
74 116
75 superio_ide_status[port] = base + IDE_STATUS_OFFSET; 117 superio_ide_status[port] = base + 7;
76 superio_ide_select[port] = base + IDE_SELECT_OFFSET; 118 superio_ide_select[port] = base + 6;
77 superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa); 119 superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
78 120
79 /* Clear error/interrupt, enable dma */ 121 /* Clear error/interrupt, enable dma */
80 tmp = superio_ide_inb(superio_ide_dma_status[port]); 122 tmp = superio_ide_inb(superio_ide_dma_status[port]);
81 outb(tmp | 0x66, superio_ide_dma_status[port]); 123 outb(tmp | 0x66, superio_ide_dma_status[port]);
82 124
125 hwif->tf_read = superio_tf_read;
126
83 /* We need to override inb to workaround a SuperIO errata */ 127 /* We need to override inb to workaround a SuperIO errata */
84 hwif->INB = superio_ide_inb; 128 hwif->INB = superio_ide_inb;
85} 129}
@@ -231,12 +275,12 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
231 * SELECT_DRIVE() properly during first ide_probe_port(). 275 * SELECT_DRIVE() properly during first ide_probe_port().
232 */ 276 */
233 timeout = 10000; 277 timeout = 10000;
234 outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]); 278 outb(12, hwif->io_ports.ctl_addr);
235 udelay(10); 279 udelay(10);
236 outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]); 280 outb(8, hwif->io_ports.ctl_addr);
237 do { 281 do {
238 udelay(50); 282 udelay(50);
239 stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); 283 stat = hwif->INB(hwif->io_ports.status_addr);
240 if (stat == 0xff) 284 if (stat == 0xff)
241 break; 285 break;
242 } while ((stat & BUSY_STAT) && --timeout); 286 } while ((stat & BUSY_STAT) && --timeout);
@@ -244,7 +288,7 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
244 } 288 }
245 289
246 if (!using_inta) 290 if (!using_inta)
247 hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]); 291 hwif->irq = ide_default_irq(hwif->io_ports.data_addr);
248 else if (!hwif->irq && hwif->mate && hwif->mate->irq) 292 else if (!hwif->irq && hwif->mate && hwif->mate->irq)
249 hwif->irq = hwif->mate->irq; /* share IRQ with mate */ 293 hwif->irq = hwif->mate->irq; /* share IRQ with mate */
250 294
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
index 9edacba20ffb..6e99080497bf 100644
--- a/drivers/ide/pci/opti621.c
+++ b/drivers/ide/pci/opti621.c
@@ -53,8 +53,7 @@
53 * If you then set the second drive to another PIO, the old value 53 * If you then set the second drive to another PIO, the old value
54 * (automatically selected) will be overrided by yours. 54 * (automatically selected) will be overrided by yours.
55 * There is a 25/33MHz switch in configuration 55 * There is a 25/33MHz switch in configuration
56 * register, but driver is written for use at any frequency which get 56 * register, but driver is written for use at any frequency.
57 * (use idebus=xx to select PCI bus speed).
58 * 57 *
59 * Version 0.1, Nov 8, 1996 58 * Version 0.1, Nov 8, 1996
60 * by Jaromir Koutek, for 2.1.8. 59 * by Jaromir Koutek, for 2.1.8.
@@ -210,7 +209,7 @@ static void compute_clocks(int pio, pio_clocks_t *clks)
210{ 209{
211 if (pio != PIO_NOT_EXIST) { 210 if (pio != PIO_NOT_EXIST) {
212 int adr_setup, data_pls; 211 int adr_setup, data_pls;
213 int bus_speed = system_bus_clock(); 212 int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock();
214 213
215 adr_setup = ide_pio_timings[pio].setup_time; 214 adr_setup = ide_pio_timings[pio].setup_time;
216 data_pls = ide_pio_timings[pio].active_time; 215 data_pls = ide_pio_timings[pio].active_time;
@@ -280,7 +279,7 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
280 279
281 spin_lock_irqsave(&opti621_lock, flags); 280 spin_lock_irqsave(&opti621_lock, flags);
282 281
283 reg_base = hwif->io_ports[IDE_DATA_OFFSET]; 282 reg_base = hwif->io_ports.data_addr;
284 283
285 /* allow Register-B */ 284 /* allow Register-B */
286 outb(0xc0, reg_base + CNTRL_REG); 285 outb(0xc0, reg_base + CNTRL_REG);
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index ec9bd7b352fc..070df8ab3b21 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -83,8 +83,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
83{ 83{
84 u8 value; 84 u8 value;
85 85
86 outb(index, hwif->dma_vendor1); 86 outb(index, hwif->dma_base + 1);
87 value = inb(hwif->dma_vendor3); 87 value = inb(hwif->dma_base + 3);
88 88
89 DBG("index[%02X] value[%02X]\n", index, value); 89 DBG("index[%02X] value[%02X]\n", index, value);
90 return value; 90 return value;
@@ -97,8 +97,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
97 */ 97 */
98static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value) 98static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
99{ 99{
100 outb(index, hwif->dma_vendor1); 100 outb(index, hwif->dma_base + 1);
101 outb(value, hwif->dma_vendor3); 101 outb(value, hwif->dma_base + 3);
102 DBG("index[%02X] value[%02X]\n", index, value); 102 DBG("index[%02X] value[%02X]\n", index, value);
103} 103}
104 104
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
index 21c5dd23f928..f04738d14a6f 100644
--- a/drivers/ide/pci/piix.c
+++ b/drivers/ide/pci/piix.c
@@ -250,6 +250,7 @@ static const struct ich_laptop ich_laptop[] = {
250 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 250 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
251 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 251 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
252 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */ 252 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
253 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
253 /* end marker */ 254 /* end marker */
254 { 0, } 255 { 0, }
255}; 256};
diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c
index 17cf86490d59..910fb00deb71 100644
--- a/drivers/ide/pci/scc_pata.c
+++ b/drivers/ide/pci/scc_pata.c
@@ -126,12 +126,6 @@ static u8 scc_ide_inb(unsigned long port)
126 return (u8)data; 126 return (u8)data;
127} 127}
128 128
129static u16 scc_ide_inw(unsigned long port)
130{
131 u32 data = in_be32((void*)port);
132 return (u16)data;
133}
134
135static void scc_ide_insw(unsigned long port, void *addr, u32 count) 129static void scc_ide_insw(unsigned long port, void *addr, u32 count)
136{ 130{
137 u16 *ptr = (u16 *)addr; 131 u16 *ptr = (u16 *)addr;
@@ -154,11 +148,6 @@ static void scc_ide_outb(u8 addr, unsigned long port)
154 out_be32((void*)port, addr); 148 out_be32((void*)port, addr);
155} 149}
156 150
157static void scc_ide_outw(u16 addr, unsigned long port)
158{
159 out_be32((void*)port, addr);
160}
161
162static void 151static void
163scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port) 152scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
164{ 153{
@@ -271,6 +260,20 @@ static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
271 out_be32((void __iomem *)udenvt_port, reg); 260 out_be32((void __iomem *)udenvt_port, reg);
272} 261}
273 262
263static void scc_dma_host_set(ide_drive_t *drive, int on)
264{
265 ide_hwif_t *hwif = drive->hwif;
266 u8 unit = (drive->select.b.unit & 0x01);
267 u8 dma_stat = scc_ide_inb(hwif->dma_status);
268
269 if (on)
270 dma_stat |= (1 << (5 + unit));
271 else
272 dma_stat &= ~(1 << (5 + unit));
273
274 scc_ide_outb(dma_stat, hwif->dma_status);
275}
276
274/** 277/**
275 * scc_ide_dma_setup - begin a DMA phase 278 * scc_ide_dma_setup - begin a DMA phase
276 * @drive: target device 279 * @drive: target device
@@ -301,7 +304,7 @@ static int scc_dma_setup(ide_drive_t *drive)
301 } 304 }
302 305
303 /* PRD table */ 306 /* PRD table */
304 out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma); 307 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
305 308
306 /* specify r/w */ 309 /* specify r/w */
307 out_be32((void __iomem *)hwif->dma_command, reading); 310 out_be32((void __iomem *)hwif->dma_command, reading);
@@ -315,13 +318,45 @@ static int scc_dma_setup(ide_drive_t *drive)
315 return 0; 318 return 0;
316} 319}
317 320
321static void scc_dma_start(ide_drive_t *drive)
322{
323 ide_hwif_t *hwif = drive->hwif;
324 u8 dma_cmd = scc_ide_inb(hwif->dma_command);
325
326 /* start DMA */
327 scc_ide_outb(dma_cmd | 1, hwif->dma_command);
328 hwif->dma = 1;
329 wmb();
330}
331
332static int __scc_dma_end(ide_drive_t *drive)
333{
334 ide_hwif_t *hwif = drive->hwif;
335 u8 dma_stat, dma_cmd;
336
337 drive->waiting_for_dma = 0;
338 /* get DMA command mode */
339 dma_cmd = scc_ide_inb(hwif->dma_command);
340 /* stop DMA */
341 scc_ide_outb(dma_cmd & ~1, hwif->dma_command);
342 /* get DMA status */
343 dma_stat = scc_ide_inb(hwif->dma_status);
344 /* clear the INTR & ERROR bits */
345 scc_ide_outb(dma_stat | 6, hwif->dma_status);
346 /* purge DMA mappings */
347 ide_destroy_dmatable(drive);
348 /* verify good DMA status */
349 hwif->dma = 0;
350 wmb();
351 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
352}
318 353
319/** 354/**
320 * scc_dma_end - Stop DMA 355 * scc_dma_end - Stop DMA
321 * @drive: IDE drive 356 * @drive: IDE drive
322 * 357 *
323 * Check and clear INT Status register. 358 * Check and clear INT Status register.
324 * Then call __ide_dma_end(). 359 * Then call __scc_dma_end().
325 */ 360 */
326 361
327static int scc_dma_end(ide_drive_t *drive) 362static int scc_dma_end(ide_drive_t *drive)
@@ -334,7 +369,7 @@ static int scc_dma_end(ide_drive_t *drive)
334 369
335 /* errata A308 workaround: Step5 (check data loss) */ 370 /* errata A308 workaround: Step5 (check data loss) */
336 /* We don't check non ide_disk because it is limited to UDMA4 */ 371 /* We don't check non ide_disk because it is limited to UDMA4 */
337 if (!(in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET]) 372 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
338 & ERR_STAT) && 373 & ERR_STAT) &&
339 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { 374 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
340 reg = in_be32((void __iomem *)intsts_port); 375 reg = in_be32((void __iomem *)intsts_port);
@@ -425,7 +460,7 @@ static int scc_dma_end(ide_drive_t *drive)
425 break; 460 break;
426 } 461 }
427 462
428 dma_stat = __ide_dma_end(drive); 463 dma_stat = __scc_dma_end(drive);
429 if (data_loss) 464 if (data_loss)
430 dma_stat |= 2; /* emulate DMA error (to retry command) */ 465 dma_stat |= 2; /* emulate DMA error (to retry command) */
431 return dma_stat; 466 return dma_stat;
@@ -438,7 +473,7 @@ static int scc_dma_test_irq(ide_drive_t *drive)
438 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); 473 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
439 474
440 /* SCC errata A252,A308 workaround: Step4 */ 475 /* SCC errata A252,A308 workaround: Step4 */
441 if ((in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET]) 476 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
442 & ERR_STAT) && 477 & ERR_STAT) &&
443 (int_stat & INTSTS_INTRQ)) 478 (int_stat & INTSTS_INTRQ))
444 return 1; 479 return 1;
@@ -534,8 +569,8 @@ static int scc_ide_setup_pci_device(struct pci_dev *dev,
534 } 569 }
535 570
536 memset(&hw, 0, sizeof(hw)); 571 memset(&hw, 0, sizeof(hw));
537 for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; i++) 572 for (i = 0; i <= 8; i++)
538 hw.io_ports[i] = ports->dma + 0x20 + i * 4; 573 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
539 hw.irq = dev->irq; 574 hw.irq = dev->irq;
540 hw.dev = &dev->dev; 575 hw.dev = &dev->dev;
541 hw.chipset = ide_pci; 576 hw.chipset = ide_pci;
@@ -618,6 +653,122 @@ static int __devinit init_setup_scc(struct pci_dev *dev,
618 return rc; 653 return rc;
619} 654}
620 655
656static void scc_tf_load(ide_drive_t *drive, ide_task_t *task)
657{
658 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
659 struct ide_taskfile *tf = &task->tf;
660 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
661
662 if (task->tf_flags & IDE_TFLAG_FLAGGED)
663 HIHI = 0xFF;
664
665 ide_set_irq(drive, 1);
666
667 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
668 out_be32((void *)io_ports->data_addr,
669 (tf->hob_data << 8) | tf->data);
670
671 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
672 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
673 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
674 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
675 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
676 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
677 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
678 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
679 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
680 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
681
682 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
683 scc_ide_outb(tf->feature, io_ports->feature_addr);
684 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
685 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
686 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
687 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
688 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
689 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
690 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
691 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
692
693 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
694 scc_ide_outb((tf->device & HIHI) | drive->select.all,
695 io_ports->device_addr);
696}
697
698static void scc_tf_read(ide_drive_t *drive, ide_task_t *task)
699{
700 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
701 struct ide_taskfile *tf = &task->tf;
702
703 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
704 u16 data = (u16)in_be32((void *)io_ports->data_addr);
705
706 tf->data = data & 0xff;
707 tf->hob_data = (data >> 8) & 0xff;
708 }
709
710 /* be sure we're looking at the low order bits */
711 scc_ide_outb(drive->ctl & ~0x80, io_ports->ctl_addr);
712
713 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
714 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
715 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
716 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
717 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
718 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
719 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
720 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
721 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
722 tf->device = scc_ide_inb(io_ports->device_addr);
723
724 if (task->tf_flags & IDE_TFLAG_LBA48) {
725 scc_ide_outb(drive->ctl | 0x80, io_ports->ctl_addr);
726
727 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
728 tf->hob_feature = scc_ide_inb(io_ports->feature_addr);
729 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
730 tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr);
731 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
732 tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr);
733 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
734 tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr);
735 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
736 tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr);
737 }
738}
739
740static void scc_input_data(ide_drive_t *drive, struct request *rq,
741 void *buf, unsigned int len)
742{
743 unsigned long data_addr = drive->hwif->io_ports.data_addr;
744
745 len++;
746
747 if (drive->io_32bit) {
748 scc_ide_insl(data_addr, buf, len / 4);
749
750 if ((len & 3) >= 2)
751 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
752 } else
753 scc_ide_insw(data_addr, buf, len / 2);
754}
755
756static void scc_output_data(ide_drive_t *drive, struct request *rq,
757 void *buf, unsigned int len)
758{
759 unsigned long data_addr = drive->hwif->io_ports.data_addr;
760
761 len++;
762
763 if (drive->io_32bit) {
764 scc_ide_outsl(data_addr, buf, len / 4);
765
766 if ((len & 3) >= 2)
767 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
768 } else
769 scc_ide_outsw(data_addr, buf, len / 2);
770}
771
621/** 772/**
622 * init_mmio_iops_scc - set up the iops for MMIO 773 * init_mmio_iops_scc - set up the iops for MMIO
623 * @hwif: interface to set up 774 * @hwif: interface to set up
@@ -632,15 +783,15 @@ static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
632 783
633 ide_set_hwifdata(hwif, ports); 784 ide_set_hwifdata(hwif, ports);
634 785
786 hwif->tf_load = scc_tf_load;
787 hwif->tf_read = scc_tf_read;
788
789 hwif->input_data = scc_input_data;
790 hwif->output_data = scc_output_data;
791
635 hwif->INB = scc_ide_inb; 792 hwif->INB = scc_ide_inb;
636 hwif->INW = scc_ide_inw;
637 hwif->INSW = scc_ide_insw;
638 hwif->INSL = scc_ide_insl;
639 hwif->OUTB = scc_ide_outb; 793 hwif->OUTB = scc_ide_outb;
640 hwif->OUTBSYNC = scc_ide_outbsync; 794 hwif->OUTBSYNC = scc_ide_outbsync;
641 hwif->OUTW = scc_ide_outw;
642 hwif->OUTSW = scc_ide_outsw;
643 hwif->OUTSL = scc_ide_outsl;
644 795
645 hwif->dma_base = dma_base; 796 hwif->dma_base = dma_base;
646 hwif->config_data = ports->ctl; 797 hwif->config_data = ports->ctl;
@@ -687,7 +838,6 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif)
687 838
688 hwif->dma_command = hwif->dma_base; 839 hwif->dma_command = hwif->dma_base;
689 hwif->dma_status = hwif->dma_base + 0x04; 840 hwif->dma_status = hwif->dma_base + 0x04;
690 hwif->dma_prdtable = hwif->dma_base + 0x08;
691 841
692 /* PTERADD */ 842 /* PTERADD */
693 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma); 843 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
@@ -706,10 +856,10 @@ static const struct ide_port_ops scc_port_ops = {
706}; 856};
707 857
708static const struct ide_dma_ops scc_dma_ops = { 858static const struct ide_dma_ops scc_dma_ops = {
709 .dma_host_set = ide_dma_host_set, 859 .dma_host_set = scc_dma_host_set,
710 .dma_setup = scc_dma_setup, 860 .dma_setup = scc_dma_setup,
711 .dma_exec_cmd = ide_dma_exec_cmd, 861 .dma_exec_cmd = ide_dma_exec_cmd,
712 .dma_start = ide_dma_start, 862 .dma_start = scc_dma_start,
713 .dma_end = scc_dma_end, 863 .dma_end = scc_dma_end,
714 .dma_test_irq = scc_dma_test_irq, 864 .dma_test_irq = scc_dma_test_irq,
715 .dma_lost_irq = ide_dma_lost_irq, 865 .dma_lost_irq = ide_dma_lost_irq,
@@ -763,9 +913,8 @@ static void __devexit scc_remove(struct pci_dev *dev)
763 hwif->dmatable_cpu = NULL; 913 hwif->dmatable_cpu = NULL;
764 } 914 }
765 915
766 ide_unregister(hwif->index); 916 ide_unregister(hwif);
767 917
768 hwif->chipset = ide_unknown;
769 iounmap((void*)ports->dma); 918 iounmap((void*)ports->dma);
770 iounmap((void*)ports->ctl); 919 iounmap((void*)ports->ctl);
771 pci_release_selected_regions(dev, (1 << 2) - 1); 920 pci_release_selected_regions(dev, (1 << 2) - 1);
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
index 321a4e28ac19..16a0bce17d69 100644
--- a/drivers/ide/pci/sgiioc4.c
+++ b/drivers/ide/pci/sgiioc4.c
@@ -98,28 +98,28 @@ sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
98 int i; 98 int i;
99 99
100 /* Registers are word (32 bit) aligned */ 100 /* Registers are word (32 bit) aligned */
101 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) 101 for (i = 0; i <= 7; i++)
102 hw->io_ports[i] = reg + i * 4; 102 hw->io_ports_array[i] = reg + i * 4;
103 103
104 if (ctrl_port) 104 if (ctrl_port)
105 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; 105 hw->io_ports.ctl_addr = ctrl_port;
106 106
107 if (irq_port) 107 if (irq_port)
108 hw->io_ports[IDE_IRQ_OFFSET] = irq_port; 108 hw->io_ports.irq_addr = irq_port;
109} 109}
110 110
111static void 111static void
112sgiioc4_maskproc(ide_drive_t * drive, int mask) 112sgiioc4_maskproc(ide_drive_t * drive, int mask)
113{ 113{
114 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 114 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
115 (void __iomem *)drive->hwif->io_ports[IDE_CONTROL_OFFSET]); 115 (void __iomem *)drive->hwif->io_ports.ctl_addr);
116} 116}
117 117
118static int 118static int
119sgiioc4_checkirq(ide_hwif_t * hwif) 119sgiioc4_checkirq(ide_hwif_t * hwif)
120{ 120{
121 unsigned long intr_addr = 121 unsigned long intr_addr =
122 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4; 122 hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
123 123
124 if ((u8)readl((void __iomem *)intr_addr) & 0x03) 124 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
125 return 1; 125 return 1;
@@ -134,8 +134,8 @@ sgiioc4_clearirq(ide_drive_t * drive)
134{ 134{
135 u32 intr_reg; 135 u32 intr_reg;
136 ide_hwif_t *hwif = HWIF(drive); 136 ide_hwif_t *hwif = HWIF(drive);
137 unsigned long other_ir = 137 struct ide_io_ports *io_ports = &hwif->io_ports;
138 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2); 138 unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
139 139
140 /* Code to check for PCI error conditions */ 140 /* Code to check for PCI error conditions */
141 intr_reg = readl((void __iomem *)other_ir); 141 intr_reg = readl((void __iomem *)other_ir);
@@ -147,12 +147,12 @@ sgiioc4_clearirq(ide_drive_t * drive)
147 * a "clear" status if it got cleared. If not, then spin 147 * a "clear" status if it got cleared. If not, then spin
148 * for a bit trying to clear it. 148 * for a bit trying to clear it.
149 */ 149 */
150 u8 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]); 150 u8 stat = sgiioc4_INB(io_ports->status_addr);
151 int count = 0; 151 int count = 0;
152 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]); 152 stat = sgiioc4_INB(io_ports->status_addr);
153 while ((stat & 0x80) && (count++ < 100)) { 153 while ((stat & 0x80) && (count++ < 100)) {
154 udelay(1); 154 udelay(1);
155 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]); 155 stat = sgiioc4_INB(io_ports->status_addr);
156 } 156 }
157 157
158 if (intr_reg & 0x02) { 158 if (intr_reg & 0x02) {
@@ -162,9 +162,9 @@ sgiioc4_clearirq(ide_drive_t * drive)
162 pci_stat_cmd_reg; 162 pci_stat_cmd_reg;
163 163
164 pci_err_addr_low = 164 pci_err_addr_low =
165 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]); 165 readl((void __iomem *)io_ports->irq_addr);
166 pci_err_addr_high = 166 pci_err_addr_high =
167 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4)); 167 readl((void __iomem *)(io_ports->irq_addr + 4));
168 pci_read_config_dword(dev, PCI_COMMAND, 168 pci_read_config_dword(dev, PCI_COMMAND,
169 &pci_stat_cmd_reg); 169 &pci_stat_cmd_reg);
170 printk(KERN_ERR 170 printk(KERN_ERR
@@ -573,7 +573,7 @@ static const struct ide_port_info sgiioc4_port_info __devinitdata = {
573 .init_dma = ide_dma_sgiioc4, 573 .init_dma = ide_dma_sgiioc4,
574 .port_ops = &sgiioc4_port_ops, 574 .port_ops = &sgiioc4_port_ops,
575 .dma_ops = &sgiioc4_dma_ops, 575 .dma_ops = &sgiioc4_dma_ops,
576 .host_flags = IDE_HFLAG_NO_AUTOTUNE, 576 .host_flags = IDE_HFLAG_MMIO,
577 .mwdma_mask = ATA_MWDMA2_ONLY, 577 .mwdma_mask = ATA_MWDMA2_ONLY,
578}; 578};
579 579
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
index 1fffea3211bd..4cf8fc54aa2a 100644
--- a/drivers/ide/pci/siimage.c
+++ b/drivers/ide/pci/siimage.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com> 3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007 MontaVista Software, Inc. 4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
6 * 6 *
7 * May be copied or modified under the terms of the GNU General Public License 7 * May be copied or modified under the terms of the GNU General Public License
8 * 8 *
@@ -17,10 +17,10 @@
17 * 17 *
18 * FAQ Items: 18 * FAQ Items:
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives 19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5 not UDMA6. 20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
21 * 21 *
22 * If you are using WD drives with SATA bridges you must set the 22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang 23 * drive to "Single". "Master" will hang.
24 * 24 *
25 * If you have strange problems with nVidia chipset systems please 25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS 26 * see the SI support documentation and update your system BIOS
@@ -42,25 +42,24 @@
42#include <linux/hdreg.h> 42#include <linux/hdreg.h>
43#include <linux/ide.h> 43#include <linux/ide.h>
44#include <linux/init.h> 44#include <linux/init.h>
45 45#include <linux/io.h>
46#include <asm/io.h>
47 46
48/** 47/**
49 * pdev_is_sata - check if device is SATA 48 * pdev_is_sata - check if device is SATA
50 * @pdev: PCI device to check 49 * @pdev: PCI device to check
51 * 50 *
52 * Returns true if this is a SATA controller 51 * Returns true if this is a SATA controller
53 */ 52 */
54 53
55static int pdev_is_sata(struct pci_dev *pdev) 54static int pdev_is_sata(struct pci_dev *pdev)
56{ 55{
57#ifdef CONFIG_BLK_DEV_IDE_SATA 56#ifdef CONFIG_BLK_DEV_IDE_SATA
58 switch(pdev->device) { 57 switch (pdev->device) {
59 case PCI_DEVICE_ID_SII_3112: 58 case PCI_DEVICE_ID_SII_3112:
60 case PCI_DEVICE_ID_SII_1210SA: 59 case PCI_DEVICE_ID_SII_1210SA:
61 return 1; 60 return 1;
62 case PCI_DEVICE_ID_SII_680: 61 case PCI_DEVICE_ID_SII_680:
63 return 0; 62 return 0;
64 } 63 }
65 BUG(); 64 BUG();
66#endif 65#endif
@@ -70,10 +69,10 @@ static int pdev_is_sata(struct pci_dev *pdev)
70/** 69/**
71 * is_sata - check if hwif is SATA 70 * is_sata - check if hwif is SATA
72 * @hwif: interface to check 71 * @hwif: interface to check
73 * 72 *
74 * Returns true if this is a SATA controller 73 * Returns true if this is a SATA controller
75 */ 74 */
76 75
77static inline int is_sata(ide_hwif_t *hwif) 76static inline int is_sata(ide_hwif_t *hwif)
78{ 77{
79 return pdev_is_sata(to_pci_dev(hwif->dev)); 78 return pdev_is_sata(to_pci_dev(hwif->dev));
@@ -86,21 +85,22 @@ static inline int is_sata(ide_hwif_t *hwif)
86 * 85 *
87 * Turn a config register offset into the right address in either 86 * Turn a config register offset into the right address in either
88 * PCI space or MMIO space to access the control register in question 87 * PCI space or MMIO space to access the control register in question
89 * Thankfully this is a configuration operation so isnt performance 88 * Thankfully this is a configuration operation, so isn't performance
90 * criticial. 89 * critical.
91 */ 90 */
92 91
93static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) 92static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
94{ 93{
95 unsigned long base = (unsigned long)hwif->hwif_data; 94 unsigned long base = (unsigned long)hwif->hwif_data;
95
96 base += 0xA0 + r; 96 base += 0xA0 + r;
97 if(hwif->mmio) 97 if (hwif->mmio)
98 base += (hwif->channel << 6); 98 base += hwif->channel << 6;
99 else 99 else
100 base += (hwif->channel << 4); 100 base += hwif->channel << 4;
101 return base; 101 return base;
102} 102}
103 103
104/** 104/**
105 * siimage_seldev - return register base 105 * siimage_seldev - return register base
106 * @hwif: interface 106 * @hwif: interface
@@ -110,20 +110,69 @@ static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
110 * PCI space or MMIO space to access the control register in question 110 * PCI space or MMIO space to access the control register in question
111 * including accounting for the unit shift. 111 * including accounting for the unit shift.
112 */ 112 */
113 113
114static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) 114static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
115{ 115{
116 ide_hwif_t *hwif = HWIF(drive); 116 ide_hwif_t *hwif = HWIF(drive);
117 unsigned long base = (unsigned long)hwif->hwif_data; 117 unsigned long base = (unsigned long)hwif->hwif_data;
118
118 base += 0xA0 + r; 119 base += 0xA0 + r;
119 if(hwif->mmio) 120 if (hwif->mmio)
120 base += (hwif->channel << 6); 121 base += hwif->channel << 6;
121 else 122 else
122 base += (hwif->channel << 4); 123 base += hwif->channel << 4;
123 base |= drive->select.b.unit << drive->select.b.unit; 124 base |= drive->select.b.unit << drive->select.b.unit;
124 return base; 125 return base;
125} 126}
126 127
128static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
129{
130 u8 tmp = 0;
131
132 if (pci_get_drvdata(dev))
133 tmp = readb((void __iomem *)addr);
134 else
135 pci_read_config_byte(dev, addr, &tmp);
136
137 return tmp;
138}
139
140static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
141{
142 u16 tmp = 0;
143
144 if (pci_get_drvdata(dev))
145 tmp = readw((void __iomem *)addr);
146 else
147 pci_read_config_word(dev, addr, &tmp);
148
149 return tmp;
150}
151
152static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
153{
154 if (pci_get_drvdata(dev))
155 writeb(val, (void __iomem *)addr);
156 else
157 pci_write_config_byte(dev, addr, val);
158}
159
160static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
161{
162 if (pci_get_drvdata(dev))
163 writew(val, (void __iomem *)addr);
164 else
165 pci_write_config_word(dev, addr, val);
166}
167
168static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
169{
170 if (pci_get_drvdata(dev))
171 writel(val, (void __iomem *)addr);
172 else
173 pci_write_config_dword(dev, addr, val);
174}
175
127/** 176/**
128 * sil_udma_filter - compute UDMA mask 177 * sil_udma_filter - compute UDMA mask
129 * @drive: IDE device 178 * @drive: IDE device
@@ -136,24 +185,26 @@ static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
136 185
137static u8 sil_pata_udma_filter(ide_drive_t *drive) 186static u8 sil_pata_udma_filter(ide_drive_t *drive)
138{ 187{
139 ide_hwif_t *hwif = drive->hwif; 188 ide_hwif_t *hwif = drive->hwif;
140 struct pci_dev *dev = to_pci_dev(hwif->dev); 189 struct pci_dev *dev = to_pci_dev(hwif->dev);
141 unsigned long base = (unsigned long) hwif->hwif_data; 190 unsigned long base = (unsigned long)hwif->hwif_data;
142 u8 mask = 0, scsc = 0; 191 u8 scsc, mask = 0;
143 192
144 if (hwif->mmio) 193 scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
145 scsc = hwif->INB(base + 0x4A);
146 else
147 pci_read_config_byte(dev, 0x8A, &scsc);
148 194
149 if ((scsc & 0x30) == 0x10) /* 133 */ 195 switch (scsc & 0x30) {
196 case 0x10: /* 133 */
150 mask = ATA_UDMA6; 197 mask = ATA_UDMA6;
151 else if ((scsc & 0x30) == 0x20) /* 2xPCI */ 198 break;
199 case 0x20: /* 2xPCI */
152 mask = ATA_UDMA6; 200 mask = ATA_UDMA6;
153 else if ((scsc & 0x30) == 0x00) /* 100 */ 201 break;
202 case 0x00: /* 100 */
154 mask = ATA_UDMA5; 203 mask = ATA_UDMA5;
155 else /* Disabled ? */ 204 break;
205 default: /* Disabled ? */
156 BUG(); 206 BUG();
207 }
157 208
158 return mask; 209 return mask;
159} 210}
@@ -175,15 +226,16 @@ static u8 sil_sata_udma_filter(ide_drive_t *drive)
175 226
176static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) 227static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
177{ 228{
178 const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; 229 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
179 const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 230 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
180 231
181 ide_hwif_t *hwif = HWIF(drive); 232 ide_hwif_t *hwif = HWIF(drive);
233 struct pci_dev *dev = to_pci_dev(hwif->dev);
182 ide_drive_t *pair = ide_get_paired_drive(drive); 234 ide_drive_t *pair = ide_get_paired_drive(drive);
183 u32 speedt = 0; 235 u32 speedt = 0;
184 u16 speedp = 0; 236 u16 speedp = 0;
185 unsigned long addr = siimage_seldev(drive, 0x04); 237 unsigned long addr = siimage_seldev(drive, 0x04);
186 unsigned long tfaddr = siimage_selreg(hwif, 0x02); 238 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
187 unsigned long base = (unsigned long)hwif->hwif_data; 239 unsigned long base = (unsigned long)hwif->hwif_data;
188 u8 tf_pio = pio; 240 u8 tf_pio = pio;
189 u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84) 241 u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84)
@@ -203,36 +255,20 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
203 speedp = data_speed[pio]; 255 speedp = data_speed[pio];
204 speedt = tf_speed[tf_pio]; 256 speedt = tf_speed[tf_pio];
205 257
206 if (hwif->mmio) { 258 sil_iowrite16(dev, speedp, addr);
207 hwif->OUTW(speedp, addr); 259 sil_iowrite16(dev, speedt, tfaddr);
208 hwif->OUTW(speedt, tfaddr); 260
209 /* Now set up IORDY */ 261 /* now set up IORDY */
210 if (pio > 2) 262 speedp = sil_ioread16(dev, tfaddr - 2);
211 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); 263 speedp &= ~0x200;
212 else 264 if (pio > 2)
213 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); 265 speedp |= 0x200;
214 266 sil_iowrite16(dev, speedp, tfaddr - 2);
215 mode = hwif->INB(base + addr_mask); 267
216 mode &= ~(unit ? 0x30 : 0x03); 268 mode = sil_ioread8(dev, base + addr_mask);
217 mode |= (unit ? 0x10 : 0x01); 269 mode &= ~(unit ? 0x30 : 0x03);
218 hwif->OUTB(mode, base + addr_mask); 270 mode |= unit ? 0x10 : 0x01;
219 } else { 271 sil_iowrite8(dev, mode, base + addr_mask);
220 struct pci_dev *dev = to_pci_dev(hwif->dev);
221
222 pci_write_config_word(dev, addr, speedp);
223 pci_write_config_word(dev, tfaddr, speedt);
224 pci_read_config_word(dev, tfaddr - 2, &speedp);
225 speedp &= ~0x200;
226 /* Set IORDY for mode 3 or 4 */
227 if (pio > 2)
228 speedp |= 0x200;
229 pci_write_config_word(dev, tfaddr - 2, speedp);
230
231 pci_read_config_byte(dev, addr_mask, &mode);
232 mode &= ~(unit ? 0x30 : 0x03);
233 mode |= (unit ? 0x10 : 0x01);
234 pci_write_config_byte(dev, addr_mask, mode);
235 }
236} 272}
237 273
238/** 274/**
@@ -245,59 +281,45 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
245 281
246static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) 282static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
247{ 283{
248 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; 284 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
249 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; 285 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
250 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; 286 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
251 287
252 ide_hwif_t *hwif = HWIF(drive); 288 ide_hwif_t *hwif = HWIF(drive);
253 struct pci_dev *dev = to_pci_dev(hwif->dev); 289 struct pci_dev *dev = to_pci_dev(hwif->dev);
254 u16 ultra = 0, multi = 0; 290 u16 ultra = 0, multi = 0;
255 u8 mode = 0, unit = drive->select.b.unit; 291 u8 mode = 0, unit = drive->select.b.unit;
256 unsigned long base = (unsigned long)hwif->hwif_data; 292 unsigned long base = (unsigned long)hwif->hwif_data;
257 u8 scsc = 0, addr_mask = ((hwif->channel) ? 293 u8 scsc = 0, addr_mask = hwif->channel ?
258 ((hwif->mmio) ? 0xF4 : 0x84) : 294 (hwif->mmio ? 0xF4 : 0x84) :
259 ((hwif->mmio) ? 0xB4 : 0x80)); 295 (hwif->mmio ? 0xB4 : 0x80);
260
261 unsigned long ma = siimage_seldev(drive, 0x08); 296 unsigned long ma = siimage_seldev(drive, 0x08);
262 unsigned long ua = siimage_seldev(drive, 0x0C); 297 unsigned long ua = siimage_seldev(drive, 0x0C);
263 298
264 if (hwif->mmio) { 299 scsc = sil_ioread8 (dev, base + (hwif->mmio ? 0x4A : 0x8A));
265 scsc = hwif->INB(base + 0x4A); 300 mode = sil_ioread8 (dev, base + addr_mask);
266 mode = hwif->INB(base + addr_mask); 301 multi = sil_ioread16(dev, ma);
267 multi = hwif->INW(ma); 302 ultra = sil_ioread16(dev, ua);
268 ultra = hwif->INW(ua);
269 } else {
270 pci_read_config_byte(dev, 0x8A, &scsc);
271 pci_read_config_byte(dev, addr_mask, &mode);
272 pci_read_config_word(dev, ma, &multi);
273 pci_read_config_word(dev, ua, &ultra);
274 }
275 303
276 mode &= ~((unit) ? 0x30 : 0x03); 304 mode &= ~(unit ? 0x30 : 0x03);
277 ultra &= ~0x3F; 305 ultra &= ~0x3F;
278 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; 306 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
279 307
280 scsc = is_sata(hwif) ? 1 : scsc; 308 scsc = is_sata(hwif) ? 1 : scsc;
281 309
282 if (speed >= XFER_UDMA_0) { 310 if (speed >= XFER_UDMA_0) {
283 multi = dma[2]; 311 multi = dma[2];
284 ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] : 312 ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
285 ultra5[speed - XFER_UDMA_0]); 313 ultra5[speed - XFER_UDMA_0];
286 mode |= (unit ? 0x30 : 0x03); 314 mode |= unit ? 0x30 : 0x03;
287 } else { 315 } else {
288 multi = dma[speed - XFER_MW_DMA_0]; 316 multi = dma[speed - XFER_MW_DMA_0];
289 mode |= (unit ? 0x20 : 0x02); 317 mode |= unit ? 0x20 : 0x02;
290 } 318 }
291 319
292 if (hwif->mmio) { 320 sil_iowrite8 (dev, mode, base + addr_mask);
293 hwif->OUTB(mode, base + addr_mask); 321 sil_iowrite16(dev, multi, ma);
294 hwif->OUTW(multi, ma); 322 sil_iowrite16(dev, ultra, ua);
295 hwif->OUTW(ultra, ua);
296 } else {
297 pci_write_config_byte(dev, addr_mask, mode);
298 pci_write_config_word(dev, ma, multi);
299 pci_write_config_word(dev, ua, ultra);
300 }
301} 323}
302 324
303/* returns 1 if dma irq issued, 0 otherwise */ 325/* returns 1 if dma irq issued, 0 otherwise */
@@ -309,13 +331,14 @@ static int siimage_io_dma_test_irq(ide_drive_t *drive)
309 unsigned long addr = siimage_selreg(hwif, 1); 331 unsigned long addr = siimage_selreg(hwif, 1);
310 332
311 /* return 1 if INTR asserted */ 333 /* return 1 if INTR asserted */
312 if ((hwif->INB(hwif->dma_status) & 4) == 4) 334 if (hwif->INB(hwif->dma_status) & 4)
313 return 1; 335 return 1;
314 336
315 /* return 1 if Device INTR asserted */ 337 /* return 1 if Device INTR asserted */
316 pci_read_config_byte(dev, addr, &dma_altstat); 338 pci_read_config_byte(dev, addr, &dma_altstat);
317 if (dma_altstat & 8) 339 if (dma_altstat & 8)
318 return 0; //return 1; 340 return 0; /* return 1; */
341
319 return 0; 342 return 0;
320} 343}
321 344
@@ -335,9 +358,9 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
335 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; 358 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
336 359
337 if (sata_error_addr) { 360 if (sata_error_addr) {
338 unsigned long base = (unsigned long)hwif->hwif_data; 361 unsigned long base = (unsigned long)hwif->hwif_data;
339 u32 ext_stat = readl((void __iomem *)(base + 0x10)); 362 u32 ext_stat = readl((void __iomem *)(base + 0x10));
340 u8 watchdog = 0; 363 u8 watchdog = 0;
341 364
342 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { 365 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
343 u32 sata_error = readl(sata_error_addr); 366 u32 sata_error = readl(sata_error_addr);
@@ -346,25 +369,22 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
346 watchdog = (sata_error & 0x00680000) ? 1 : 0; 369 watchdog = (sata_error & 0x00680000) ? 1 : 0;
347 printk(KERN_WARNING "%s: sata_error = 0x%08x, " 370 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
348 "watchdog = %d, %s\n", 371 "watchdog = %d, %s\n",
349 drive->name, sata_error, watchdog, 372 drive->name, sata_error, watchdog, __func__);
350 __func__); 373 } else
351
352 } else {
353 watchdog = (ext_stat & 0x8000) ? 1 : 0; 374 watchdog = (ext_stat & 0x8000) ? 1 : 0;
354 }
355 ext_stat >>= 16;
356 375
376 ext_stat >>= 16;
357 if (!(ext_stat & 0x0404) && !watchdog) 377 if (!(ext_stat & 0x0404) && !watchdog)
358 return 0; 378 return 0;
359 } 379 }
360 380
361 /* return 1 if INTR asserted */ 381 /* return 1 if INTR asserted */
362 if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) 382 if (readb((void __iomem *)hwif->dma_status) & 0x04)
363 return 1; 383 return 1;
364 384
365 /* return 1 if Device INTR asserted */ 385 /* return 1 if Device INTR asserted */
366 if ((readb((void __iomem *)addr) & 8) == 8) 386 if (readb((void __iomem *)addr) & 8)
367 return 0; //return 1; 387 return 0; /* return 1; */
368 388
369 return 0; 389 return 0;
370} 390}
@@ -423,63 +443,33 @@ static void sil_sata_pre_reset(ide_drive_t *drive)
423} 443}
424 444
425/** 445/**
426 * proc_reports_siimage - add siimage controller to proc 446 * setup_mmio_siimage - switch controller into MMIO mode
427 * @dev: PCI device
428 * @clocking: SCSC value
429 * @name: controller name
430 *
431 * Report the clocking mode of the controller and add it to
432 * the /proc interface layer
433 */
434
435static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
436{
437 if (!pdev_is_sata(dev)) {
438 printk(KERN_INFO "%s: BASE CLOCK ", name);
439 clocking &= 0x03;
440 switch (clocking) {
441 case 0x03: printk("DISABLED!\n"); break;
442 case 0x02: printk("== 2X PCI\n"); break;
443 case 0x01: printk("== 133\n"); break;
444 case 0x00: printk("== 100\n"); break;
445 }
446 }
447}
448
449/**
450 * setup_mmio_siimage - switch an SI controller into MMIO
451 * @dev: PCI device we are configuring 447 * @dev: PCI device we are configuring
452 * @name: device name 448 * @name: device name
453 * 449 *
454 * Attempt to put the device into mmio mode. There are some slight 450 * Attempt to put the device into MMIO mode. There are some slight
455 * complications here with certain systems where the mmio bar isnt 451 * complications here with certain systems where the MMIO BAR isn't
456 * mapped so we have to be sure we can fall back to I/O. 452 * mapped, so we have to be sure that we can fall back to I/O.
457 */ 453 */
458 454
459static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) 455static unsigned int setup_mmio_siimage(struct pci_dev *dev, const char *name)
460{ 456{
461 resource_size_t bar5 = pci_resource_start(dev, 5); 457 resource_size_t bar5 = pci_resource_start(dev, 5);
462 unsigned long barsize = pci_resource_len(dev, 5); 458 unsigned long barsize = pci_resource_len(dev, 5);
463 u8 tmpbyte = 0;
464 void __iomem *ioaddr; 459 void __iomem *ioaddr;
465 u32 tmp, irq_mask;
466 460
467 /* 461 /*
468 * Drop back to PIO if we can't map the mmio. Some 462 * Drop back to PIO if we can't map the MMIO. Some systems
469 * systems seem to get terminally confused in the PCI 463 * seem to get terminally confused in the PCI spaces.
470 * spaces.
471 */ 464 */
472 465 if (!request_mem_region(bar5, barsize, name)) {
473 if(!request_mem_region(bar5, barsize, name)) 466 printk(KERN_WARNING "siimage: IDE controller MMIO ports not "
474 { 467 "available.\n");
475 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
476 return 0; 468 return 0;
477 } 469 }
478
479 ioaddr = ioremap(bar5, barsize);
480 470
481 if (ioaddr == NULL) 471 ioaddr = ioremap(bar5, barsize);
482 { 472 if (ioaddr == NULL) {
483 release_mem_region(bar5, barsize); 473 release_mem_region(bar5, barsize);
484 return 0; 474 return 0;
485 } 475 }
@@ -487,62 +477,6 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
487 pci_set_master(dev); 477 pci_set_master(dev);
488 pci_set_drvdata(dev, (void *) ioaddr); 478 pci_set_drvdata(dev, (void *) ioaddr);
489 479
490 if (pdev_is_sata(dev)) {
491 /* make sure IDE0/1 interrupts are not masked */
492 irq_mask = (1 << 22) | (1 << 23);
493 tmp = readl(ioaddr + 0x48);
494 if (tmp & irq_mask) {
495 tmp &= ~irq_mask;
496 writel(tmp, ioaddr + 0x48);
497 readl(ioaddr + 0x48); /* flush */
498 }
499 writel(0, ioaddr + 0x148);
500 writel(0, ioaddr + 0x1C8);
501 }
502
503 writeb(0, ioaddr + 0xB4);
504 writeb(0, ioaddr + 0xF4);
505 tmpbyte = readb(ioaddr + 0x4A);
506
507 switch(tmpbyte & 0x30) {
508 case 0x00:
509 /* In 100 MHz clocking, try and switch to 133 */
510 writeb(tmpbyte|0x10, ioaddr + 0x4A);
511 break;
512 case 0x10:
513 /* On 133Mhz clocking */
514 break;
515 case 0x20:
516 /* On PCIx2 clocking */
517 break;
518 case 0x30:
519 /* Clocking is disabled */
520 /* 133 clock attempt to force it on */
521 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
522 break;
523 }
524
525 writeb( 0x72, ioaddr + 0xA1);
526 writew( 0x328A, ioaddr + 0xA2);
527 writel(0x62DD62DD, ioaddr + 0xA4);
528 writel(0x43924392, ioaddr + 0xA8);
529 writel(0x40094009, ioaddr + 0xAC);
530 writeb( 0x72, ioaddr + 0xE1);
531 writew( 0x328A, ioaddr + 0xE2);
532 writel(0x62DD62DD, ioaddr + 0xE4);
533 writel(0x43924392, ioaddr + 0xE8);
534 writel(0x40094009, ioaddr + 0xEC);
535
536 if (pdev_is_sata(dev)) {
537 writel(0xFFFF0000, ioaddr + 0x108);
538 writel(0xFFFF0000, ioaddr + 0x188);
539 writel(0x00680000, ioaddr + 0x148);
540 writel(0x00680000, ioaddr + 0x1C8);
541 }
542
543 tmpbyte = readb(ioaddr + 0x4A);
544
545 proc_reports_siimage(dev, (tmpbyte>>4), name);
546 return 1; 480 return 1;
547} 481}
548 482
@@ -552,55 +486,92 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
552 * @name: device name 486 * @name: device name
553 * 487 *
554 * Perform the initial PCI set up for this device. Attempt to switch 488 * Perform the initial PCI set up for this device. Attempt to switch
555 * to 133MHz clocking if the system isn't already set up to do it. 489 * to 133 MHz clocking if the system isn't already set up to do it.
556 */ 490 */
557 491
558static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) 492static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev,
493 const char *name)
559{ 494{
560 u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0; 495 unsigned long base, scsc_addr;
496 void __iomem *ioaddr = NULL;
497 u8 rev = dev->revision, tmp, BA5_EN;
561 498
562 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); 499 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
563 500
564 pci_read_config_byte(dev, 0x8A, &BA5_EN); 501 pci_read_config_byte(dev, 0x8A, &BA5_EN);
565 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { 502
566 if (setup_mmio_siimage(dev, name)) { 503 if ((BA5_EN & 0x01) || pci_resource_start(dev, 5))
567 return 0; 504 if (setup_mmio_siimage(dev, name))
505 ioaddr = pci_get_drvdata(dev);
506
507 base = (unsigned long)ioaddr;
508
509 if (ioaddr && pdev_is_sata(dev)) {
510 u32 tmp32, irq_mask;
511
512 /* make sure IDE0/1 interrupts are not masked */
513 irq_mask = (1 << 22) | (1 << 23);
514 tmp32 = readl(ioaddr + 0x48);
515 if (tmp32 & irq_mask) {
516 tmp32 &= ~irq_mask;
517 writel(tmp32, ioaddr + 0x48);
518 readl(ioaddr + 0x48); /* flush */
568 } 519 }
520 writel(0, ioaddr + 0x148);
521 writel(0, ioaddr + 0x1C8);
522 }
523
524 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
525 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
526
527 scsc_addr = base ? (base + 0x4A) : 0x8A;
528 tmp = sil_ioread8(dev, scsc_addr);
529
530 switch (tmp & 0x30) {
531 case 0x00:
532 /* On 100 MHz clocking, try and switch to 133 MHz */
533 sil_iowrite8(dev, tmp | 0x10, scsc_addr);
534 break;
535 case 0x30:
536 /* Clocking is disabled, attempt to force 133MHz clocking. */
537 sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
538 case 0x10:
539 /* On 133Mhz clocking. */
540 break;
541 case 0x20:
542 /* On PCIx2 clocking. */
543 break;
569 } 544 }
570 545
571 pci_write_config_byte(dev, 0x80, 0x00); 546 tmp = sil_ioread8(dev, scsc_addr);
572 pci_write_config_byte(dev, 0x84, 0x00); 547
573 pci_read_config_byte(dev, 0x8A, &tmpbyte); 548 sil_iowrite8 (dev, 0x72, base + 0xA1);
574 switch(tmpbyte & 0x30) { 549 sil_iowrite16(dev, 0x328A, base + 0xA2);
575 case 0x00: 550 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
576 /* 133 clock attempt to force it on */ 551 sil_iowrite32(dev, 0x43924392, base + 0xA8);
577 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); 552 sil_iowrite32(dev, 0x40094009, base + 0xAC);
578 case 0x30: 553 sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
579 /* if clocking is disabled */ 554 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
580 /* 133 clock attempt to force it on */ 555 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
581 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); 556 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
582 case 0x10: 557 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
583 /* 133 already */ 558
584 break; 559 if (base && pdev_is_sata(dev)) {
585 case 0x20: 560 writel(0xFFFF0000, ioaddr + 0x108);
586 /* BIOS set PCI x2 clocking */ 561 writel(0xFFFF0000, ioaddr + 0x188);
587 break; 562 writel(0x00680000, ioaddr + 0x148);
563 writel(0x00680000, ioaddr + 0x1C8);
588 } 564 }
589 565
590 pci_read_config_byte(dev, 0x8A, &tmpbyte); 566 /* report the clocking mode of the controller */
567 if (!pdev_is_sata(dev)) {
568 static const char *clk_str[] =
569 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
591 570
592 pci_write_config_byte(dev, 0xA1, 0x72); 571 tmp >>= 4;
593 pci_write_config_word(dev, 0xA2, 0x328A); 572 printk(KERN_INFO "%s: BASE CLOCK %s\n", name, clk_str[tmp & 3]);
594 pci_write_config_dword(dev, 0xA4, 0x62DD62DD); 573 }
595 pci_write_config_dword(dev, 0xA8, 0x43924392);
596 pci_write_config_dword(dev, 0xAC, 0x40094009);
597 pci_write_config_byte(dev, 0xB1, 0x72);
598 pci_write_config_word(dev, 0xB2, 0x328A);
599 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
600 pci_write_config_dword(dev, 0xB8, 0x43924392);
601 pci_write_config_dword(dev, 0xBC, 0x40094009);
602 574
603 proc_reports_siimage(dev, (tmpbyte>>4), name);
604 return 0; 575 return 0;
605} 576}
606 577
@@ -610,8 +581,7 @@ static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const ch
610 * 581 *
611 * The basic setup here is fairly simple, we can use standard MMIO 582 * The basic setup here is fairly simple, we can use standard MMIO
612 * operations. However we do have to set the taskfile register offsets 583 * operations. However we do have to set the taskfile register offsets
613 * by hand as there isnt a standard defined layout for them this 584 * by hand as there isn't a standard defined layout for them this time.
614 * time.
615 * 585 *
616 * The hardware supports buffered taskfiles and also some rather nice 586 * The hardware supports buffered taskfiles and also some rather nice
617 * extended PRD tables. For better SI3112 support use the libata driver 587 * extended PRD tables. For better SI3112 support use the libata driver
@@ -622,23 +592,21 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
622 struct pci_dev *dev = to_pci_dev(hwif->dev); 592 struct pci_dev *dev = to_pci_dev(hwif->dev);
623 void *addr = pci_get_drvdata(dev); 593 void *addr = pci_get_drvdata(dev);
624 u8 ch = hwif->channel; 594 u8 ch = hwif->channel;
625 hw_regs_t hw; 595 struct ide_io_ports *io_ports = &hwif->io_ports;
626 unsigned long base; 596 unsigned long base;
627 597
628 /* 598 /*
629 * Fill in the basic HWIF bits 599 * Fill in the basic hwif bits
630 */ 600 */
631 601 hwif->host_flags |= IDE_HFLAG_MMIO;
632 default_hwif_mmiops(hwif); 602 default_hwif_mmiops(hwif);
633 hwif->hwif_data = addr; 603 hwif->hwif_data = addr;
634 604
635 /* 605 /*
636 * Now set up the hw. We have to do this ourselves as 606 * Now set up the hw. We have to do this ourselves as the
637 * the MMIO layout isnt the same as the standard port 607 * MMIO layout isn't the same as the standard port based I/O.
638 * based I/O
639 */ 608 */
640 609 memset(io_ports, 0, sizeof(*io_ports));
641 memset(&hw, 0, sizeof(hw_regs_t));
642 610
643 base = (unsigned long)addr; 611 base = (unsigned long)addr;
644 if (ch) 612 if (ch)
@@ -647,21 +615,18 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
647 base += 0x80; 615 base += 0x80;
648 616
649 /* 617 /*
650 * The buffered task file doesn't have status/control 618 * The buffered task file doesn't have status/control, so we
651 * so we can't currently use it sanely since we want to 619 * can't currently use it sanely since we want to use LBA48 mode.
652 * use LBA48 mode. 620 */
653 */ 621 io_ports->data_addr = base;
654 hw.io_ports[IDE_DATA_OFFSET] = base; 622 io_ports->error_addr = base + 1;
655 hw.io_ports[IDE_ERROR_OFFSET] = base + 1; 623 io_ports->nsect_addr = base + 2;
656 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; 624 io_ports->lbal_addr = base + 3;
657 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; 625 io_ports->lbam_addr = base + 4;
658 hw.io_ports[IDE_LCYL_OFFSET] = base + 4; 626 io_ports->lbah_addr = base + 5;
659 hw.io_ports[IDE_HCYL_OFFSET] = base + 5; 627 io_ports->device_addr = base + 6;
660 hw.io_ports[IDE_SELECT_OFFSET] = base + 6; 628 io_ports->status_addr = base + 7;
661 hw.io_ports[IDE_STATUS_OFFSET] = base + 7; 629 io_ports->ctl_addr = base + 10;
662 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
663
664 hw.io_ports[IDE_IRQ_OFFSET] = 0;
665 630
666 if (pdev_is_sata(dev)) { 631 if (pdev_is_sata(dev)) {
667 base = (unsigned long)addr; 632 base = (unsigned long)addr;
@@ -672,8 +637,6 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
672 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; 637 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
673 } 638 }
674 639
675 memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
676
677 hwif->irq = dev->irq; 640 hwif->irq = dev->irq;
678 641
679 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); 642 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
@@ -683,19 +646,17 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
683 646
684static int is_dev_seagate_sata(ide_drive_t *drive) 647static int is_dev_seagate_sata(ide_drive_t *drive)
685{ 648{
686 const char *s = &drive->id->model[0]; 649 const char *s = &drive->id->model[0];
687 unsigned len; 650 unsigned len = strnlen(s, sizeof(drive->id->model));
688
689 len = strnlen(s, sizeof(drive->id->model));
690 651
691 if ((len > 4) && (!memcmp(s, "ST", 2))) { 652 if ((len > 4) && (!memcmp(s, "ST", 2)))
692 if ((!memcmp(s + len - 2, "AS", 2)) || 653 if ((!memcmp(s + len - 2, "AS", 2)) ||
693 (!memcmp(s + len - 3, "ASL", 3))) { 654 (!memcmp(s + len - 3, "ASL", 3))) {
694 printk(KERN_INFO "%s: applying pessimistic Seagate " 655 printk(KERN_INFO "%s: applying pessimistic Seagate "
695 "errata fix\n", drive->name); 656 "errata fix\n", drive->name);
696 return 1; 657 return 1;
697 } 658 }
698 } 659
699 return 0; 660 return 0;
700} 661}
701 662
@@ -712,7 +673,7 @@ static void __devinit sil_quirkproc(ide_drive_t *drive)
712{ 673{
713 ide_hwif_t *hwif = drive->hwif; 674 ide_hwif_t *hwif = drive->hwif;
714 675
715 /* Try and raise the rqsize */ 676 /* Try and rise the rqsize */
716 if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) 677 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
717 hwif->rqsize = 128; 678 hwif->rqsize = 128;
718} 679}
@@ -746,20 +707,14 @@ static void __devinit init_iops_siimage(ide_hwif_t *hwif)
746 * sil_cable_detect - cable detection 707 * sil_cable_detect - cable detection
747 * @hwif: interface to check 708 * @hwif: interface to check
748 * 709 *
749 * Check for the presence of an ATA66 capable cable on the 710 * Check for the presence of an ATA66 capable cable on the interface.
750 * interface.
751 */ 711 */
752 712
753static u8 __devinit sil_cable_detect(ide_hwif_t *hwif) 713static u8 __devinit sil_cable_detect(ide_hwif_t *hwif)
754{ 714{
755 struct pci_dev *dev = to_pci_dev(hwif->dev); 715 struct pci_dev *dev = to_pci_dev(hwif->dev);
756 unsigned long addr = siimage_selreg(hwif, 0); 716 unsigned long addr = siimage_selreg(hwif, 0);
757 u8 ata66 = 0; 717 u8 ata66 = sil_ioread8(dev, addr);
758
759 if (pci_get_drvdata(dev) == NULL)
760 pci_read_config_byte(dev, addr, &ata66);
761 else
762 ata66 = hwif->INB(addr);
763 718
764 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; 719 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
765} 720}
@@ -805,15 +760,16 @@ static const struct ide_port_info siimage_chipsets[] __devinitdata = {
805}; 760};
806 761
807/** 762/**
808 * siimage_init_one - pci layer discovery entry 763 * siimage_init_one - PCI layer discovery entry
809 * @dev: PCI device 764 * @dev: PCI device
810 * @id: ident table entry 765 * @id: ident table entry
811 * 766 *
812 * Called by the PCI code when it finds an SI680 or SI3112 controller. 767 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
813 * We then use the IDE PCI generic helper to do most of the work. 768 * We then use the IDE PCI generic helper to do most of the work.
814 */ 769 */
815 770
816static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) 771static int __devinit siimage_init_one(struct pci_dev *dev,
772 const struct pci_device_id *id)
817{ 773{
818 struct ide_port_info d; 774 struct ide_port_info d;
819 u8 idx = id->driver_data; 775 u8 idx = id->driver_data;
diff --git a/drivers/ide/pci/trm290.c b/drivers/ide/pci/trm290.c
index 15ee38f7ad3f..a8a3138682ef 100644
--- a/drivers/ide/pci/trm290.c
+++ b/drivers/ide/pci/trm290.c
@@ -298,7 +298,7 @@ static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
298 if (old != compat && old_mask == 0xff) { 298 if (old != compat && old_mask == 0xff) {
299 /* leave lower 10 bits untouched */ 299 /* leave lower 10 bits untouched */
300 compat += (next_offset += 0x400); 300 compat += (next_offset += 0x400);
301 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2; 301 hwif->io_ports.ctl_addr = compat + 2;
302 outw(compat | 1, hwif->config_data); 302 outw(compat | 1, hwif->config_data);
303 new = inw(hwif->config_data); 303 new = inw(hwif->config_data);
304 printk(KERN_INFO "%s: control basereg workaround: " 304 printk(KERN_INFO "%s: control basereg workaround: "
diff --git a/drivers/ide/pci/via82cxxx.c b/drivers/ide/pci/via82cxxx.c
index bbd17bec6ffe..566e0ecb8db1 100644
--- a/drivers/ide/pci/via82cxxx.c
+++ b/drivers/ide/pci/via82cxxx.c
@@ -340,7 +340,7 @@ static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const
340 * Determine system bus clock. 340 * Determine system bus clock.
341 */ 341 */
342 342
343 via_clock = system_bus_clock() * 1000; 343 via_clock = (ide_pci_clk ? ide_pci_clk : system_bus_clock()) * 1000;
344 344
345 switch (via_clock) { 345 switch (via_clock) {
346 case 33000: via_clock = 33333; break; 346 case 33000: via_clock = 33333; break;
diff --git a/drivers/ide/ppc/mpc8xx.c b/drivers/ide/ppc/mpc8xx.c
index a82f6efb660b..f0e638dcc3ab 100644
--- a/drivers/ide/ppc/mpc8xx.c
+++ b/drivers/ide/ppc/mpc8xx.c
@@ -131,7 +131,7 @@ static int pcmcia_schlvl = PCMCIA_SCHLVL;
131#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) 131#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
132static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port) 132static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
133{ 133{
134 unsigned long *p = hw->io_ports; 134 unsigned long *p = hw->io_ports_array;
135 int i; 135 int i;
136 136
137 typedef struct { 137 typedef struct {
@@ -314,7 +314,7 @@ static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
314#if defined(CONFIG_IDE_EXT_DIRECT) 314#if defined(CONFIG_IDE_EXT_DIRECT)
315static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port) 315static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
316{ 316{
317 unsigned long *p = hw->io_ports; 317 unsigned long *p = hw->io_ports_array;
318 int i; 318 int i;
319 319
320 u32 ide_phy_base; 320 u32 ide_phy_base;
@@ -811,24 +811,28 @@ static int __init mpc8xx_ide_probe(void)
811#ifdef IDE0_BASE_OFFSET 811#ifdef IDE0_BASE_OFFSET
812 memset(&hw, 0, sizeof(hw)); 812 memset(&hw, 0, sizeof(hw));
813 if (!m8xx_ide_init_ports(&hw, 0)) { 813 if (!m8xx_ide_init_ports(&hw, 0)) {
814 ide_hwif_t *hwif = &ide_hwifs[0]; 814 ide_hwif_t *hwif = ide_find_port();
815 815
816 ide_init_port_hw(hwif, &hw); 816 if (hwif) {
817 hwif->pio_mask = ATA_PIO4; 817 ide_init_port_hw(hwif, &hw);
818 hwif->port_ops = &m8xx_port_ops; 818 hwif->pio_mask = ATA_PIO4;
819 hwif->port_ops = &m8xx_port_ops;
819 820
820 idx[0] = 0; 821 idx[0] = hwif->index;
822 }
821 } 823 }
822#ifdef IDE1_BASE_OFFSET 824#ifdef IDE1_BASE_OFFSET
823 memset(&hw, 0, sizeof(hw)); 825 memset(&hw, 0, sizeof(hw));
824 if (!m8xx_ide_init_ports(&hw, 1)) { 826 if (!m8xx_ide_init_ports(&hw, 1)) {
825 ide_hwif_t *mate = &ide_hwifs[1]; 827 ide_hwif_t *mate = ide_find_port();
826 828
827 ide_init_port_hw(mate, &hw); 829 if (mate) {
828 mate->pio_mask = ATA_PIO4; 830 ide_init_port_hw(mate, &hw);
829 mate->port_ops = &m8xx_port_ops; 831 mate->pio_mask = ATA_PIO4;
832 mate->port_ops = &m8xx_port_ops;
830 833
831 idx[1] = 1; 834 idx[1] = mate->index;
835 }
832 } 836 }
833#endif 837#endif
834#endif 838#endif
diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c
index 185faa0dce94..48aa019127bc 100644
--- a/drivers/ide/ppc/pmac.c
+++ b/drivers/ide/ppc/pmac.c
@@ -417,7 +417,7 @@ static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
417#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */ 417#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
418 418
419#define PMAC_IDE_REG(x) \ 419#define PMAC_IDE_REG(x) \
420 ((void __iomem *)((drive)->hwif->io_ports[IDE_DATA_OFFSET] + (x))) 420 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
421 421
422/* 422/*
423 * Apply the timings of the proper unit (master/slave) to the shared 423 * Apply the timings of the proper unit (master/slave) to the shared
@@ -941,6 +941,7 @@ static const struct ide_port_info pmac_port_info = {
941 .port_ops = &pmac_ide_port_ops, 941 .port_ops = &pmac_ide_port_ops,
942 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA | 942 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
943 IDE_HFLAG_POST_SET_MODE | 943 IDE_HFLAG_POST_SET_MODE |
944 IDE_HFLAG_MMIO |
944 IDE_HFLAG_UNMASK_IRQS, 945 IDE_HFLAG_UNMASK_IRQS,
945 .pio_mask = ATA_PIO4, 946 .pio_mask = ATA_PIO4,
946 .mwdma_mask = ATA_MWDMA2, 947 .mwdma_mask = ATA_MWDMA2,
@@ -1086,8 +1087,9 @@ static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base)
1086 int i; 1087 int i;
1087 1088
1088 for (i = 0; i < 8; ++i) 1089 for (i = 0; i < 8; ++i)
1089 hw->io_ports[i] = base + i * 0x10; 1090 hw->io_ports_array[i] = base + i * 0x10;
1090 hw->io_ports[8] = base + 0x160; 1091
1092 hw->io_ports.ctl_addr = base + 0x160;
1091} 1093}
1092 1094
1093/* 1095/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 01:17:33 -0500