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diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c
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1/*
2 * Support for IDE interfaces on PowerMacs.
3 *
4 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
6 *
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
8 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25#include <linux/types.h>
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36
37#include <asm/prom.h>
38#include <asm/io.h>
39#include <asm/dbdma.h>
40#include <asm/ide.h>
41#include <asm/pci-bridge.h>
42#include <asm/machdep.h>
43#include <asm/pmac_feature.h>
44#include <asm/sections.h>
45#include <asm/irq.h>
46
47#ifndef CONFIG_PPC64
48#include <asm/mediabay.h>
49#endif
50
51#define DRV_NAME "ide-pmac"
52
53#undef IDE_PMAC_DEBUG
54
55#define DMA_WAIT_TIMEOUT 50
56
57typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned mediabay : 1;
63 unsigned broken_dma : 1;
64 unsigned broken_dma_warn : 1;
65 struct device_node* node;
66 struct macio_dev *mdev;
67 u32 timings[4];
68 volatile u32 __iomem * *kauai_fcr;
69#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
70 /* Those fields are duplicating what is in hwif. We currently
71 * can't use the hwif ones because of some assumptions that are
72 * beeing done by the generic code about the kind of dma controller
73 * and format of the dma table. This will have to be fixed though.
74 */
75 volatile struct dbdma_regs __iomem * dma_regs;
76 struct dbdma_cmd* dma_table_cpu;
77#endif
78
79} pmac_ide_hwif_t;
80
81enum {
82 controller_ohare, /* OHare based */
83 controller_heathrow, /* Heathrow/Paddington */
84 controller_kl_ata3, /* KeyLargo ATA-3 */
85 controller_kl_ata4, /* KeyLargo ATA-4 */
86 controller_un_ata6, /* UniNorth2 ATA-6 */
87 controller_k2_ata6, /* K2 ATA-6 */
88 controller_sh_ata6, /* Shasta ATA-6 */
89};
90
91static const char* model_name[] = {
92 "OHare ATA", /* OHare based */
93 "Heathrow ATA", /* Heathrow/Paddington */
94 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
95 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
96 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
97 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
98 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
99};
100
101/*
102 * Extra registers, both 32-bit little-endian
103 */
104#define IDE_TIMING_CONFIG 0x200
105#define IDE_INTERRUPT 0x300
106
107/* Kauai (U2) ATA has different register setup */
108#define IDE_KAUAI_PIO_CONFIG 0x200
109#define IDE_KAUAI_ULTRA_CONFIG 0x210
110#define IDE_KAUAI_POLL_CONFIG 0x220
111
112/*
113 * Timing configuration register definitions
114 */
115
116/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
117#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
118#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
119#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
120#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
121
122/* 133Mhz cell, found in shasta.
123 * See comments about 100 Mhz Uninorth 2...
124 * Note that PIO_MASK and MDMA_MASK seem to overlap
125 */
126#define TR_133_PIOREG_PIO_MASK 0xff000fff
127#define TR_133_PIOREG_MDMA_MASK 0x00fff800
128#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
129#define TR_133_UDMAREG_UDMA_EN 0x00000001
130
131/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
132 * this one yet, it appears as a pci device (106b/0033) on uninorth
133 * internal PCI bus and it's clock is controlled like gem or fw. It
134 * appears to be an evolution of keylargo ATA4 with a timing register
135 * extended to 2 32bits registers and a similar DBDMA channel. Other
136 * registers seem to exist but I can't tell much about them.
137 *
138 * So far, I'm using pre-calculated tables for this extracted from
139 * the values used by the MacOS X driver.
140 *
141 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
142 * register controls the UDMA timings. At least, it seems bit 0
143 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
144 * cycle time in units of 10ns. Bits 8..15 are used by I don't
145 * know their meaning yet
146 */
147#define TR_100_PIOREG_PIO_MASK 0xff000fff
148#define TR_100_PIOREG_MDMA_MASK 0x00fff000
149#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
150#define TR_100_UDMAREG_UDMA_EN 0x00000001
151
152
153/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
154 * 40 connector cable and to 4 on 80 connector one.
155 * Clock unit is 15ns (66Mhz)
156 *
157 * 3 Values can be programmed:
158 * - Write data setup, which appears to match the cycle time. They
159 * also call it DIOW setup.
160 * - Ready to pause time (from spec)
161 * - Address setup. That one is weird. I don't see where exactly
162 * it fits in UDMA cycles, I got it's name from an obscure piece
163 * of commented out code in Darwin. They leave it to 0, we do as
164 * well, despite a comment that would lead to think it has a
165 * min value of 45ns.
166 * Apple also add 60ns to the write data setup (or cycle time ?) on
167 * reads.
168 */
169#define TR_66_UDMA_MASK 0xfff00000
170#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
171#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
172#define TR_66_UDMA_ADDRSETUP_SHIFT 29
173#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
174#define TR_66_UDMA_RDY2PAUS_SHIFT 25
175#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
176#define TR_66_UDMA_WRDATASETUP_SHIFT 21
177#define TR_66_MDMA_MASK 0x000ffc00
178#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
179#define TR_66_MDMA_RECOVERY_SHIFT 15
180#define TR_66_MDMA_ACCESS_MASK 0x00007c00
181#define TR_66_MDMA_ACCESS_SHIFT 10
182#define TR_66_PIO_MASK 0x000003ff
183#define TR_66_PIO_RECOVERY_MASK 0x000003e0
184#define TR_66_PIO_RECOVERY_SHIFT 5
185#define TR_66_PIO_ACCESS_MASK 0x0000001f
186#define TR_66_PIO_ACCESS_SHIFT 0
187
188/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
189 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
190 *
191 * The access time and recovery time can be programmed. Some older
192 * Darwin code base limit OHare to 150ns cycle time. I decided to do
193 * the same here fore safety against broken old hardware ;)
194 * The HalfTick bit, when set, adds half a clock (15ns) to the access
195 * time and removes one from recovery. It's not supported on KeyLargo
196 * implementation afaik. The E bit appears to be set for PIO mode 0 and
197 * is used to reach long timings used in this mode.
198 */
199#define TR_33_MDMA_MASK 0x003ff800
200#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
201#define TR_33_MDMA_RECOVERY_SHIFT 16
202#define TR_33_MDMA_ACCESS_MASK 0x0000f800
203#define TR_33_MDMA_ACCESS_SHIFT 11
204#define TR_33_MDMA_HALFTICK 0x00200000
205#define TR_33_PIO_MASK 0x000007ff
206#define TR_33_PIO_E 0x00000400
207#define TR_33_PIO_RECOVERY_MASK 0x000003e0
208#define TR_33_PIO_RECOVERY_SHIFT 5
209#define TR_33_PIO_ACCESS_MASK 0x0000001f
210#define TR_33_PIO_ACCESS_SHIFT 0
211
212/*
213 * Interrupt register definitions
214 */
215#define IDE_INTR_DMA 0x80000000
216#define IDE_INTR_DEVICE 0x40000000
217
218/*
219 * FCR Register on Kauai. Not sure what bit 0x4 is ...
220 */
221#define KAUAI_FCR_UATA_MAGIC 0x00000004
222#define KAUAI_FCR_UATA_RESET_N 0x00000002
223#define KAUAI_FCR_UATA_ENABLE 0x00000001
224
225#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
226
227/* Rounded Multiword DMA timings
228 *
229 * I gave up finding a generic formula for all controller
230 * types and instead, built tables based on timing values
231 * used by Apple in Darwin's implementation.
232 */
233struct mdma_timings_t {
234 int accessTime;
235 int recoveryTime;
236 int cycleTime;
237};
238
239struct mdma_timings_t mdma_timings_33[] =
240{
241 { 240, 240, 480 },
242 { 180, 180, 360 },
243 { 135, 135, 270 },
244 { 120, 120, 240 },
245 { 105, 105, 210 },
246 { 90, 90, 180 },
247 { 75, 75, 150 },
248 { 75, 45, 120 },
249 { 0, 0, 0 }
250};
251
252struct mdma_timings_t mdma_timings_33k[] =
253{
254 { 240, 240, 480 },
255 { 180, 180, 360 },
256 { 150, 150, 300 },
257 { 120, 120, 240 },
258 { 90, 120, 210 },
259 { 90, 90, 180 },
260 { 90, 60, 150 },
261 { 90, 30, 120 },
262 { 0, 0, 0 }
263};
264
265struct mdma_timings_t mdma_timings_66[] =
266{
267 { 240, 240, 480 },
268 { 180, 180, 360 },
269 { 135, 135, 270 },
270 { 120, 120, 240 },
271 { 105, 105, 210 },
272 { 90, 90, 180 },
273 { 90, 75, 165 },
274 { 75, 45, 120 },
275 { 0, 0, 0 }
276};
277
278/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
279struct {
280 int addrSetup; /* ??? */
281 int rdy2pause;
282 int wrDataSetup;
283} kl66_udma_timings[] =
284{
285 { 0, 180, 120 }, /* Mode 0 */
286 { 0, 150, 90 }, /* 1 */
287 { 0, 120, 60 }, /* 2 */
288 { 0, 90, 45 }, /* 3 */
289 { 0, 90, 30 } /* 4 */
290};
291
292/* UniNorth 2 ATA/100 timings */
293struct kauai_timing {
294 int cycle_time;
295 u32 timing_reg;
296};
297
298static struct kauai_timing kauai_pio_timings[] =
299{
300 { 930 , 0x08000fff },
301 { 600 , 0x08000a92 },
302 { 383 , 0x0800060f },
303 { 360 , 0x08000492 },
304 { 330 , 0x0800048f },
305 { 300 , 0x080003cf },
306 { 270 , 0x080003cc },
307 { 240 , 0x0800038b },
308 { 239 , 0x0800030c },
309 { 180 , 0x05000249 },
310 { 120 , 0x04000148 },
311 { 0 , 0 },
312};
313
314static struct kauai_timing kauai_mdma_timings[] =
315{
316 { 1260 , 0x00fff000 },
317 { 480 , 0x00618000 },
318 { 360 , 0x00492000 },
319 { 270 , 0x0038e000 },
320 { 240 , 0x0030c000 },
321 { 210 , 0x002cb000 },
322 { 180 , 0x00249000 },
323 { 150 , 0x00209000 },
324 { 120 , 0x00148000 },
325 { 0 , 0 },
326};
327
328static struct kauai_timing kauai_udma_timings[] =
329{
330 { 120 , 0x000070c0 },
331 { 90 , 0x00005d80 },
332 { 60 , 0x00004a60 },
333 { 45 , 0x00003a50 },
334 { 30 , 0x00002a30 },
335 { 20 , 0x00002921 },
336 { 0 , 0 },
337};
338
339static struct kauai_timing shasta_pio_timings[] =
340{
341 { 930 , 0x08000fff },
342 { 600 , 0x0A000c97 },
343 { 383 , 0x07000712 },
344 { 360 , 0x040003cd },
345 { 330 , 0x040003cd },
346 { 300 , 0x040003cd },
347 { 270 , 0x040003cd },
348 { 240 , 0x040003cd },
349 { 239 , 0x040003cd },
350 { 180 , 0x0400028b },
351 { 120 , 0x0400010a },
352 { 0 , 0 },
353};
354
355static struct kauai_timing shasta_mdma_timings[] =
356{
357 { 1260 , 0x00fff000 },
358 { 480 , 0x00820800 },
359 { 360 , 0x00820800 },
360 { 270 , 0x00820800 },
361 { 240 , 0x00820800 },
362 { 210 , 0x00820800 },
363 { 180 , 0x00820800 },
364 { 150 , 0x0028b000 },
365 { 120 , 0x001ca000 },
366 { 0 , 0 },
367};
368
369static struct kauai_timing shasta_udma133_timings[] =
370{
371 { 120 , 0x00035901, },
372 { 90 , 0x000348b1, },
373 { 60 , 0x00033881, },
374 { 45 , 0x00033861, },
375 { 30 , 0x00033841, },
376 { 20 , 0x00033031, },
377 { 15 , 0x00033021, },
378 { 0 , 0 },
379};
380
381
382static inline u32
383kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
384{
385 int i;
386
387 for (i=0; table[i].cycle_time; i++)
388 if (cycle_time > table[i+1].cycle_time)
389 return table[i].timing_reg;
390 BUG();
391 return 0;
392}
393
394/* allow up to 256 DBDMA commands per xfer */
395#define MAX_DCMDS 256
396
397/*
398 * Wait 1s for disk to answer on IDE bus after a hard reset
399 * of the device (via GPIO/FCR).
400 *
401 * Some devices seem to "pollute" the bus even after dropping
402 * the BSY bit (typically some combo drives slave on the UDMA
403 * bus) after a hard reset. Since we hard reset all drives on
404 * KeyLargo ATA66, we have to keep that delay around. I may end
405 * up not hard resetting anymore on these and keep the delay only
406 * for older interfaces instead (we have to reset when coming
407 * from MacOS...) --BenH.
408 */
409#define IDE_WAKEUP_DELAY (1*HZ)
410
411static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
412static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
413static void pmac_ide_selectproc(ide_drive_t *drive);
414static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
415
416#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
417
418#define PMAC_IDE_REG(x) \
419 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
420
421/*
422 * Apply the timings of the proper unit (master/slave) to the shared
423 * timing register when selecting that unit. This version is for
424 * ASICs with a single timing register
425 */
426static void
427pmac_ide_selectproc(ide_drive_t *drive)
428{
429 ide_hwif_t *hwif = drive->hwif;
430 pmac_ide_hwif_t *pmif =
431 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
432
433 if (drive->dn & 1)
434 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
435 else
436 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
437 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
438}
439
440/*
441 * Apply the timings of the proper unit (master/slave) to the shared
442 * timing register when selecting that unit. This version is for
443 * ASICs with a dual timing register (Kauai)
444 */
445static void
446pmac_ide_kauai_selectproc(ide_drive_t *drive)
447{
448 ide_hwif_t *hwif = drive->hwif;
449 pmac_ide_hwif_t *pmif =
450 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
451
452 if (drive->dn & 1) {
453 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
454 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
455 } else {
456 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
457 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
458 }
459 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
460}
461
462/*
463 * Force an update of controller timing values for a given drive
464 */
465static void
466pmac_ide_do_update_timings(ide_drive_t *drive)
467{
468 ide_hwif_t *hwif = drive->hwif;
469 pmac_ide_hwif_t *pmif =
470 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
471
472 if (pmif->kind == controller_sh_ata6 ||
473 pmif->kind == controller_un_ata6 ||
474 pmif->kind == controller_k2_ata6)
475 pmac_ide_kauai_selectproc(drive);
476 else
477 pmac_ide_selectproc(drive);
478}
479
480static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
481{
482 writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
483 (void)readl((void __iomem *)(hwif->io_ports.data_addr
484 + IDE_TIMING_CONFIG));
485}
486
487static void pmac_set_irq(ide_hwif_t *hwif, int on)
488{
489 u8 ctl = ATA_DEVCTL_OBS;
490
491 if (on == 4) { /* hack for SRST */
492 ctl |= 4;
493 on &= ~4;
494 }
495
496 ctl |= on ? 0 : 2;
497
498 writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);
499 (void)readl((void __iomem *)(hwif->io_ports.data_addr
500 + IDE_TIMING_CONFIG));
501}
502
503/*
504 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
505 */
506static void
507pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
508{
509 ide_hwif_t *hwif = drive->hwif;
510 pmac_ide_hwif_t *pmif =
511 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
512 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
513 u32 *timings, t;
514 unsigned accessTicks, recTicks;
515 unsigned accessTime, recTime;
516 unsigned int cycle_time;
517
518 /* which drive is it ? */
519 timings = &pmif->timings[drive->dn & 1];
520 t = *timings;
521
522 cycle_time = ide_pio_cycle_time(drive, pio);
523
524 switch (pmif->kind) {
525 case controller_sh_ata6: {
526 /* 133Mhz cell */
527 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
528 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
529 break;
530 }
531 case controller_un_ata6:
532 case controller_k2_ata6: {
533 /* 100Mhz cell */
534 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
535 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
536 break;
537 }
538 case controller_kl_ata4:
539 /* 66Mhz cell */
540 recTime = cycle_time - tim->active - tim->setup;
541 recTime = max(recTime, 150U);
542 accessTime = tim->active;
543 accessTime = max(accessTime, 150U);
544 accessTicks = SYSCLK_TICKS_66(accessTime);
545 accessTicks = min(accessTicks, 0x1fU);
546 recTicks = SYSCLK_TICKS_66(recTime);
547 recTicks = min(recTicks, 0x1fU);
548 t = (t & ~TR_66_PIO_MASK) |
549 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
550 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
551 break;
552 default: {
553 /* 33Mhz cell */
554 int ebit = 0;
555 recTime = cycle_time - tim->active - tim->setup;
556 recTime = max(recTime, 150U);
557 accessTime = tim->active;
558 accessTime = max(accessTime, 150U);
559 accessTicks = SYSCLK_TICKS(accessTime);
560 accessTicks = min(accessTicks, 0x1fU);
561 accessTicks = max(accessTicks, 4U);
562 recTicks = SYSCLK_TICKS(recTime);
563 recTicks = min(recTicks, 0x1fU);
564 recTicks = max(recTicks, 5U) - 4;
565 if (recTicks > 9) {
566 recTicks--; /* guess, but it's only for PIO0, so... */
567 ebit = 1;
568 }
569 t = (t & ~TR_33_PIO_MASK) |
570 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
571 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
572 if (ebit)
573 t |= TR_33_PIO_E;
574 break;
575 }
576 }
577
578#ifdef IDE_PMAC_DEBUG
579 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
580 drive->name, pio, *timings);
581#endif
582
583 *timings = t;
584 pmac_ide_do_update_timings(drive);
585}
586
587#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
588
589/*
590 * Calculate KeyLargo ATA/66 UDMA timings
591 */
592static int
593set_timings_udma_ata4(u32 *timings, u8 speed)
594{
595 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
596
597 if (speed > XFER_UDMA_4)
598 return 1;
599
600 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
601 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
602 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
603
604 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
605 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
606 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
607 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
608 TR_66_UDMA_EN;
609#ifdef IDE_PMAC_DEBUG
610 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
611 speed & 0xf, *timings);
612#endif
613
614 return 0;
615}
616
617/*
618 * Calculate Kauai ATA/100 UDMA timings
619 */
620static int
621set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
622{
623 struct ide_timing *t = ide_timing_find_mode(speed);
624 u32 tr;
625
626 if (speed > XFER_UDMA_5 || t == NULL)
627 return 1;
628 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
629 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
630 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
631
632 return 0;
633}
634
635/*
636 * Calculate Shasta ATA/133 UDMA timings
637 */
638static int
639set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
640{
641 struct ide_timing *t = ide_timing_find_mode(speed);
642 u32 tr;
643
644 if (speed > XFER_UDMA_6 || t == NULL)
645 return 1;
646 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
647 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
648 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
649
650 return 0;
651}
652
653/*
654 * Calculate MDMA timings for all cells
655 */
656static void
657set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
658 u8 speed)
659{
660 u16 *id = drive->id;
661 int cycleTime, accessTime = 0, recTime = 0;
662 unsigned accessTicks, recTicks;
663 struct mdma_timings_t* tm = NULL;
664 int i;
665
666 /* Get default cycle time for mode */
667 switch(speed & 0xf) {
668 case 0: cycleTime = 480; break;
669 case 1: cycleTime = 150; break;
670 case 2: cycleTime = 120; break;
671 default:
672 BUG();
673 break;
674 }
675
676 /* Check if drive provides explicit DMA cycle time */
677 if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME])
678 cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime);
679
680 /* OHare limits according to some old Apple sources */
681 if ((intf_type == controller_ohare) && (cycleTime < 150))
682 cycleTime = 150;
683 /* Get the proper timing array for this controller */
684 switch(intf_type) {
685 case controller_sh_ata6:
686 case controller_un_ata6:
687 case controller_k2_ata6:
688 break;
689 case controller_kl_ata4:
690 tm = mdma_timings_66;
691 break;
692 case controller_kl_ata3:
693 tm = mdma_timings_33k;
694 break;
695 default:
696 tm = mdma_timings_33;
697 break;
698 }
699 if (tm != NULL) {
700 /* Lookup matching access & recovery times */
701 i = -1;
702 for (;;) {
703 if (tm[i+1].cycleTime < cycleTime)
704 break;
705 i++;
706 }
707 cycleTime = tm[i].cycleTime;
708 accessTime = tm[i].accessTime;
709 recTime = tm[i].recoveryTime;
710
711#ifdef IDE_PMAC_DEBUG
712 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
713 drive->name, cycleTime, accessTime, recTime);
714#endif
715 }
716 switch(intf_type) {
717 case controller_sh_ata6: {
718 /* 133Mhz cell */
719 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
720 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
721 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
722 }
723 case controller_un_ata6:
724 case controller_k2_ata6: {
725 /* 100Mhz cell */
726 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
727 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
728 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
729 }
730 break;
731 case controller_kl_ata4:
732 /* 66Mhz cell */
733 accessTicks = SYSCLK_TICKS_66(accessTime);
734 accessTicks = min(accessTicks, 0x1fU);
735 accessTicks = max(accessTicks, 0x1U);
736 recTicks = SYSCLK_TICKS_66(recTime);
737 recTicks = min(recTicks, 0x1fU);
738 recTicks = max(recTicks, 0x3U);
739 /* Clear out mdma bits and disable udma */
740 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
741 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
742 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
743 break;
744 case controller_kl_ata3:
745 /* 33Mhz cell on KeyLargo */
746 accessTicks = SYSCLK_TICKS(accessTime);
747 accessTicks = max(accessTicks, 1U);
748 accessTicks = min(accessTicks, 0x1fU);
749 accessTime = accessTicks * IDE_SYSCLK_NS;
750 recTicks = SYSCLK_TICKS(recTime);
751 recTicks = max(recTicks, 1U);
752 recTicks = min(recTicks, 0x1fU);
753 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
754 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
755 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
756 break;
757 default: {
758 /* 33Mhz cell on others */
759 int halfTick = 0;
760 int origAccessTime = accessTime;
761 int origRecTime = recTime;
762
763 accessTicks = SYSCLK_TICKS(accessTime);
764 accessTicks = max(accessTicks, 1U);
765 accessTicks = min(accessTicks, 0x1fU);
766 accessTime = accessTicks * IDE_SYSCLK_NS;
767 recTicks = SYSCLK_TICKS(recTime);
768 recTicks = max(recTicks, 2U) - 1;
769 recTicks = min(recTicks, 0x1fU);
770 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
771 if ((accessTicks > 1) &&
772 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
773 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
774 halfTick = 1;
775 accessTicks--;
776 }
777 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
778 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
779 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
780 if (halfTick)
781 *timings |= TR_33_MDMA_HALFTICK;
782 }
783 }
784#ifdef IDE_PMAC_DEBUG
785 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
786 drive->name, speed & 0xf, *timings);
787#endif
788}
789#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
790
791static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
792{
793 ide_hwif_t *hwif = drive->hwif;
794 pmac_ide_hwif_t *pmif =
795 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
796 int ret = 0;
797 u32 *timings, *timings2, tl[2];
798 u8 unit = drive->dn & 1;
799
800 timings = &pmif->timings[unit];
801 timings2 = &pmif->timings[unit+2];
802
803 /* Copy timings to local image */
804 tl[0] = *timings;
805 tl[1] = *timings2;
806
807#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
808 if (speed >= XFER_UDMA_0) {
809 if (pmif->kind == controller_kl_ata4)
810 ret = set_timings_udma_ata4(&tl[0], speed);
811 else if (pmif->kind == controller_un_ata6
812 || pmif->kind == controller_k2_ata6)
813 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
814 else if (pmif->kind == controller_sh_ata6)
815 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
816 else
817 ret = -1;
818 } else
819 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
820#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
821 if (ret)
822 return;
823
824 /* Apply timings to controller */
825 *timings = tl[0];
826 *timings2 = tl[1];
827
828 pmac_ide_do_update_timings(drive);
829}
830
831/*
832 * Blast some well known "safe" values to the timing registers at init or
833 * wakeup from sleep time, before we do real calculation
834 */
835static void
836sanitize_timings(pmac_ide_hwif_t *pmif)
837{
838 unsigned int value, value2 = 0;
839
840 switch(pmif->kind) {
841 case controller_sh_ata6:
842 value = 0x0a820c97;
843 value2 = 0x00033031;
844 break;
845 case controller_un_ata6:
846 case controller_k2_ata6:
847 value = 0x08618a92;
848 value2 = 0x00002921;
849 break;
850 case controller_kl_ata4:
851 value = 0x0008438c;
852 break;
853 case controller_kl_ata3:
854 value = 0x00084526;
855 break;
856 case controller_heathrow:
857 case controller_ohare:
858 default:
859 value = 0x00074526;
860 break;
861 }
862 pmif->timings[0] = pmif->timings[1] = value;
863 pmif->timings[2] = pmif->timings[3] = value2;
864}
865
866/* Suspend call back, should be called after the child devices
867 * have actually been suspended
868 */
869static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
870{
871 /* We clear the timings */
872 pmif->timings[0] = 0;
873 pmif->timings[1] = 0;
874
875 disable_irq(pmif->irq);
876
877 /* The media bay will handle itself just fine */
878 if (pmif->mediabay)
879 return 0;
880
881 /* Kauai has bus control FCRs directly here */
882 if (pmif->kauai_fcr) {
883 u32 fcr = readl(pmif->kauai_fcr);
884 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
885 writel(fcr, pmif->kauai_fcr);
886 }
887
888 /* Disable the bus on older machines and the cell on kauai */
889 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
890 0);
891
892 return 0;
893}
894
895/* Resume call back, should be called before the child devices
896 * are resumed
897 */
898static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
899{
900 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
901 if (!pmif->mediabay) {
902 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
903 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
904 msleep(10);
905 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
906
907 /* Kauai has it different */
908 if (pmif->kauai_fcr) {
909 u32 fcr = readl(pmif->kauai_fcr);
910 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
911 writel(fcr, pmif->kauai_fcr);
912 }
913
914 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
915 }
916
917 /* Sanitize drive timings */
918 sanitize_timings(pmif);
919
920 enable_irq(pmif->irq);
921
922 return 0;
923}
924
925static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
926{
927 pmac_ide_hwif_t *pmif =
928 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
929 struct device_node *np = pmif->node;
930 const char *cable = of_get_property(np, "cable-type", NULL);
931
932 /* Get cable type from device-tree. */
933 if (cable && !strncmp(cable, "80-", 3))
934 return ATA_CBL_PATA80;
935
936 /*
937 * G5's seem to have incorrect cable type in device-tree.
938 * Let's assume they have a 80 conductor cable, this seem
939 * to be always the case unless the user mucked around.
940 */
941 if (of_device_is_compatible(np, "K2-UATA") ||
942 of_device_is_compatible(np, "shasta-ata"))
943 return ATA_CBL_PATA80;
944
945 return ATA_CBL_PATA40;
946}
947
948static void pmac_ide_init_dev(ide_drive_t *drive)
949{
950 ide_hwif_t *hwif = drive->hwif;
951 pmac_ide_hwif_t *pmif =
952 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
953
954 if (pmif->mediabay) {
955#ifdef CONFIG_PMAC_MEDIABAY
956 if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) {
957 drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
958 return;
959 }
960#endif
961 drive->dev_flags |= IDE_DFLAG_NOPROBE;
962 }
963}
964
965static const struct ide_tp_ops pmac_tp_ops = {
966 .exec_command = pmac_exec_command,
967 .read_status = ide_read_status,
968 .read_altstatus = ide_read_altstatus,
969 .read_sff_dma_status = ide_read_sff_dma_status,
970
971 .set_irq = pmac_set_irq,
972
973 .tf_load = ide_tf_load,
974 .tf_read = ide_tf_read,
975
976 .input_data = ide_input_data,
977 .output_data = ide_output_data,
978};
979
980static const struct ide_port_ops pmac_ide_ata6_port_ops = {
981 .init_dev = pmac_ide_init_dev,
982 .set_pio_mode = pmac_ide_set_pio_mode,
983 .set_dma_mode = pmac_ide_set_dma_mode,
984 .selectproc = pmac_ide_kauai_selectproc,
985 .cable_detect = pmac_ide_cable_detect,
986};
987
988static const struct ide_port_ops pmac_ide_ata4_port_ops = {
989 .init_dev = pmac_ide_init_dev,
990 .set_pio_mode = pmac_ide_set_pio_mode,
991 .set_dma_mode = pmac_ide_set_dma_mode,
992 .selectproc = pmac_ide_selectproc,
993 .cable_detect = pmac_ide_cable_detect,
994};
995
996static const struct ide_port_ops pmac_ide_port_ops = {
997 .init_dev = pmac_ide_init_dev,
998 .set_pio_mode = pmac_ide_set_pio_mode,
999 .set_dma_mode = pmac_ide_set_dma_mode,
1000 .selectproc = pmac_ide_selectproc,
1001};
1002
1003static const struct ide_dma_ops pmac_dma_ops;
1004
1005static const struct ide_port_info pmac_port_info = {
1006 .name = DRV_NAME,
1007 .init_dma = pmac_ide_init_dma,
1008 .chipset = ide_pmac,
1009 .tp_ops = &pmac_tp_ops,
1010 .port_ops = &pmac_ide_port_ops,
1011#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1012 .dma_ops = &pmac_dma_ops,
1013#endif
1014 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
1015 IDE_HFLAG_POST_SET_MODE |
1016 IDE_HFLAG_MMIO |
1017 IDE_HFLAG_UNMASK_IRQS,
1018 .pio_mask = ATA_PIO4,
1019 .mwdma_mask = ATA_MWDMA2,
1020};
1021
1022/*
1023 * Setup, register & probe an IDE channel driven by this driver, this is
1024 * called by one of the 2 probe functions (macio or PCI).
1025 */
1026static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif, hw_regs_t *hw)
1027{
1028 struct device_node *np = pmif->node;
1029 const int *bidp;
1030 struct ide_host *host;
1031 ide_hwif_t *hwif;
1032 hw_regs_t *hws[] = { hw, NULL, NULL, NULL };
1033 struct ide_port_info d = pmac_port_info;
1034 int rc;
1035
1036 pmif->broken_dma = pmif->broken_dma_warn = 0;
1037 if (of_device_is_compatible(np, "shasta-ata")) {
1038 pmif->kind = controller_sh_ata6;
1039 d.port_ops = &pmac_ide_ata6_port_ops;
1040 d.udma_mask = ATA_UDMA6;
1041 } else if (of_device_is_compatible(np, "kauai-ata")) {
1042 pmif->kind = controller_un_ata6;
1043 d.port_ops = &pmac_ide_ata6_port_ops;
1044 d.udma_mask = ATA_UDMA5;
1045 } else if (of_device_is_compatible(np, "K2-UATA")) {
1046 pmif->kind = controller_k2_ata6;
1047 d.port_ops = &pmac_ide_ata6_port_ops;
1048 d.udma_mask = ATA_UDMA5;
1049 } else if (of_device_is_compatible(np, "keylargo-ata")) {
1050 if (strcmp(np->name, "ata-4") == 0) {
1051 pmif->kind = controller_kl_ata4;
1052 d.port_ops = &pmac_ide_ata4_port_ops;
1053 d.udma_mask = ATA_UDMA4;
1054 } else
1055 pmif->kind = controller_kl_ata3;
1056 } else if (of_device_is_compatible(np, "heathrow-ata")) {
1057 pmif->kind = controller_heathrow;
1058 } else {
1059 pmif->kind = controller_ohare;
1060 pmif->broken_dma = 1;
1061 }
1062
1063 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1064 pmif->aapl_bus_id = bidp ? *bidp : 0;
1065
1066 /* On Kauai-type controllers, we make sure the FCR is correct */
1067 if (pmif->kauai_fcr)
1068 writel(KAUAI_FCR_UATA_MAGIC |
1069 KAUAI_FCR_UATA_RESET_N |
1070 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1071
1072 pmif->mediabay = 0;
1073
1074 /* Make sure we have sane timings */
1075 sanitize_timings(pmif);
1076
1077 host = ide_host_alloc(&d, hws);
1078 if (host == NULL)
1079 return -ENOMEM;
1080 hwif = host->ports[0];
1081
1082#ifndef CONFIG_PPC64
1083 /* XXX FIXME: Media bay stuff need re-organizing */
1084 if (np->parent && np->parent->name
1085 && strcasecmp(np->parent->name, "media-bay") == 0) {
1086#ifdef CONFIG_PMAC_MEDIABAY
1087 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
1088 hwif);
1089#endif /* CONFIG_PMAC_MEDIABAY */
1090 pmif->mediabay = 1;
1091 if (!bidp)
1092 pmif->aapl_bus_id = 1;
1093 } else if (pmif->kind == controller_ohare) {
1094 /* The code below is having trouble on some ohare machines
1095 * (timing related ?). Until I can put my hand on one of these
1096 * units, I keep the old way
1097 */
1098 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1099 } else
1100#endif
1101 {
1102 /* This is necessary to enable IDE when net-booting */
1103 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1104 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1105 msleep(10);
1106 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1107 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1108 }
1109
1110 printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
1111 "bus ID %d%s, irq %d\n", model_name[pmif->kind],
1112 pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
1113 pmif->mediabay ? " (mediabay)" : "", hw->irq);
1114
1115 rc = ide_host_register(host, &d, hws);
1116 if (rc) {
1117 ide_host_free(host);
1118 return rc;
1119 }
1120
1121 return 0;
1122}
1123
1124static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base)
1125{
1126 int i;
1127
1128 for (i = 0; i < 8; ++i)
1129 hw->io_ports_array[i] = base + i * 0x10;
1130
1131 hw->io_ports.ctl_addr = base + 0x160;
1132}
1133
1134/*
1135 * Attach to a macio probed interface
1136 */
1137static int __devinit
1138pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1139{
1140 void __iomem *base;
1141 unsigned long regbase;
1142 pmac_ide_hwif_t *pmif;
1143 int irq, rc;
1144 hw_regs_t hw;
1145
1146 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1147 if (pmif == NULL)
1148 return -ENOMEM;
1149
1150 if (macio_resource_count(mdev) == 0) {
1151 printk(KERN_WARNING "ide-pmac: no address for %s\n",
1152 mdev->ofdev.node->full_name);
1153 rc = -ENXIO;
1154 goto out_free_pmif;
1155 }
1156
1157 /* Request memory resource for IO ports */
1158 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1159 printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1160 "%s!\n", mdev->ofdev.node->full_name);
1161 rc = -EBUSY;
1162 goto out_free_pmif;
1163 }
1164
1165 /* XXX This is bogus. Should be fixed in the registry by checking
1166 * the kind of host interrupt controller, a bit like gatwick
1167 * fixes in irq.c. That works well enough for the single case
1168 * where that happens though...
1169 */
1170 if (macio_irq_count(mdev) == 0) {
1171 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1172 "13\n", mdev->ofdev.node->full_name);
1173 irq = irq_create_mapping(NULL, 13);
1174 } else
1175 irq = macio_irq(mdev, 0);
1176
1177 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1178 regbase = (unsigned long) base;
1179
1180 pmif->mdev = mdev;
1181 pmif->node = mdev->ofdev.node;
1182 pmif->regbase = regbase;
1183 pmif->irq = irq;
1184 pmif->kauai_fcr = NULL;
1185#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1186 if (macio_resource_count(mdev) >= 2) {
1187 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1188 printk(KERN_WARNING "ide-pmac: can't request DMA "
1189 "resource for %s!\n",
1190 mdev->ofdev.node->full_name);
1191 else
1192 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1193 } else
1194 pmif->dma_regs = NULL;
1195#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1196 dev_set_drvdata(&mdev->ofdev.dev, pmif);
1197
1198 memset(&hw, 0, sizeof(hw));
1199 pmac_ide_init_ports(&hw, pmif->regbase);
1200 hw.irq = irq;
1201 hw.dev = &mdev->bus->pdev->dev;
1202 hw.parent = &mdev->ofdev.dev;
1203
1204 rc = pmac_ide_setup_device(pmif, &hw);
1205 if (rc != 0) {
1206 /* The inteface is released to the common IDE layer */
1207 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1208 iounmap(base);
1209 if (pmif->dma_regs) {
1210 iounmap(pmif->dma_regs);
1211 macio_release_resource(mdev, 1);
1212 }
1213 macio_release_resource(mdev, 0);
1214 kfree(pmif);
1215 }
1216
1217 return rc;
1218
1219out_free_pmif:
1220 kfree(pmif);
1221 return rc;
1222}
1223
1224static int
1225pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1226{
1227 pmac_ide_hwif_t *pmif =
1228 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1229 int rc = 0;
1230
1231 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1232 && (mesg.event & PM_EVENT_SLEEP)) {
1233 rc = pmac_ide_do_suspend(pmif);
1234 if (rc == 0)
1235 mdev->ofdev.dev.power.power_state = mesg;
1236 }
1237
1238 return rc;
1239}
1240
1241static int
1242pmac_ide_macio_resume(struct macio_dev *mdev)
1243{
1244 pmac_ide_hwif_t *pmif =
1245 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1246 int rc = 0;
1247
1248 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1249 rc = pmac_ide_do_resume(pmif);
1250 if (rc == 0)
1251 mdev->ofdev.dev.power.power_state = PMSG_ON;
1252 }
1253
1254 return rc;
1255}
1256
1257/*
1258 * Attach to a PCI probed interface
1259 */
1260static int __devinit
1261pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1262{
1263 struct device_node *np;
1264 pmac_ide_hwif_t *pmif;
1265 void __iomem *base;
1266 unsigned long rbase, rlen;
1267 int rc;
1268 hw_regs_t hw;
1269
1270 np = pci_device_to_OF_node(pdev);
1271 if (np == NULL) {
1272 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1273 return -ENODEV;
1274 }
1275
1276 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1277 if (pmif == NULL)
1278 return -ENOMEM;
1279
1280 if (pci_enable_device(pdev)) {
1281 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1282 "%s\n", np->full_name);
1283 rc = -ENXIO;
1284 goto out_free_pmif;
1285 }
1286 pci_set_master(pdev);
1287
1288 if (pci_request_regions(pdev, "Kauai ATA")) {
1289 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1290 "%s\n", np->full_name);
1291 rc = -ENXIO;
1292 goto out_free_pmif;
1293 }
1294
1295 pmif->mdev = NULL;
1296 pmif->node = np;
1297
1298 rbase = pci_resource_start(pdev, 0);
1299 rlen = pci_resource_len(pdev, 0);
1300
1301 base = ioremap(rbase, rlen);
1302 pmif->regbase = (unsigned long) base + 0x2000;
1303#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1304 pmif->dma_regs = base + 0x1000;
1305#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1306 pmif->kauai_fcr = base;
1307 pmif->irq = pdev->irq;
1308
1309 pci_set_drvdata(pdev, pmif);
1310
1311 memset(&hw, 0, sizeof(hw));
1312 pmac_ide_init_ports(&hw, pmif->regbase);
1313 hw.irq = pdev->irq;
1314 hw.dev = &pdev->dev;
1315
1316 rc = pmac_ide_setup_device(pmif, &hw);
1317 if (rc != 0) {
1318 /* The inteface is released to the common IDE layer */
1319 pci_set_drvdata(pdev, NULL);
1320 iounmap(base);
1321 pci_release_regions(pdev);
1322 kfree(pmif);
1323 }
1324
1325 return rc;
1326
1327out_free_pmif:
1328 kfree(pmif);
1329 return rc;
1330}
1331
1332static int
1333pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1334{
1335 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev);
1336 int rc = 0;
1337
1338 if (mesg.event != pdev->dev.power.power_state.event
1339 && (mesg.event & PM_EVENT_SLEEP)) {
1340 rc = pmac_ide_do_suspend(pmif);
1341 if (rc == 0)
1342 pdev->dev.power.power_state = mesg;
1343 }
1344
1345 return rc;
1346}
1347
1348static int
1349pmac_ide_pci_resume(struct pci_dev *pdev)
1350{
1351 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)pci_get_drvdata(pdev);
1352 int rc = 0;
1353
1354 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1355 rc = pmac_ide_do_resume(pmif);
1356 if (rc == 0)
1357 pdev->dev.power.power_state = PMSG_ON;
1358 }
1359
1360 return rc;
1361}
1362
1363static struct of_device_id pmac_ide_macio_match[] =
1364{
1365 {
1366 .name = "IDE",
1367 },
1368 {
1369 .name = "ATA",
1370 },
1371 {
1372 .type = "ide",
1373 },
1374 {
1375 .type = "ata",
1376 },
1377 {},
1378};
1379
1380static struct macio_driver pmac_ide_macio_driver =
1381{
1382 .name = "ide-pmac",
1383 .match_table = pmac_ide_macio_match,
1384 .probe = pmac_ide_macio_attach,
1385 .suspend = pmac_ide_macio_suspend,
1386 .resume = pmac_ide_macio_resume,
1387};
1388
1389static const struct pci_device_id pmac_ide_pci_match[] = {
1390 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1391 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1392 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1393 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1394 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
1395 {},
1396};
1397
1398static struct pci_driver pmac_ide_pci_driver = {
1399 .name = "ide-pmac",
1400 .id_table = pmac_ide_pci_match,
1401 .probe = pmac_ide_pci_attach,
1402 .suspend = pmac_ide_pci_suspend,
1403 .resume = pmac_ide_pci_resume,
1404};
1405MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1406
1407int __init pmac_ide_probe(void)
1408{
1409 int error;
1410
1411 if (!machine_is(powermac))
1412 return -ENODEV;
1413
1414#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1415 error = pci_register_driver(&pmac_ide_pci_driver);
1416 if (error)
1417 goto out;
1418 error = macio_register_driver(&pmac_ide_macio_driver);
1419 if (error) {
1420 pci_unregister_driver(&pmac_ide_pci_driver);
1421 goto out;
1422 }
1423#else
1424 error = macio_register_driver(&pmac_ide_macio_driver);
1425 if (error)
1426 goto out;
1427 error = pci_register_driver(&pmac_ide_pci_driver);
1428 if (error) {
1429 macio_unregister_driver(&pmac_ide_macio_driver);
1430 goto out;
1431 }
1432#endif
1433out:
1434 return error;
1435}
1436
1437#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1438
1439/*
1440 * pmac_ide_build_dmatable builds the DBDMA command list
1441 * for a transfer and sets the DBDMA channel to point to it.
1442 */
1443static int
1444pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1445{
1446 ide_hwif_t *hwif = drive->hwif;
1447 pmac_ide_hwif_t *pmif =
1448 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1449 struct dbdma_cmd *table;
1450 int i, count = 0;
1451 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1452 struct scatterlist *sg;
1453 int wr = (rq_data_dir(rq) == WRITE);
1454
1455 /* DMA table is already aligned */
1456 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1457
1458 /* Make sure DMA controller is stopped (necessary ?) */
1459 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1460 while (readl(&dma->status) & RUN)
1461 udelay(1);
1462
1463 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1464
1465 if (!i)
1466 return 0;
1467
1468 /* Build DBDMA commands list */
1469 sg = hwif->sg_table;
1470 while (i && sg_dma_len(sg)) {
1471 u32 cur_addr;
1472 u32 cur_len;
1473
1474 cur_addr = sg_dma_address(sg);
1475 cur_len = sg_dma_len(sg);
1476
1477 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1478 if (pmif->broken_dma_warn == 0) {
1479 printk(KERN_WARNING "%s: DMA on non aligned address, "
1480 "switching to PIO on Ohare chipset\n", drive->name);
1481 pmif->broken_dma_warn = 1;
1482 }
1483 goto use_pio_instead;
1484 }
1485 while (cur_len) {
1486 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1487
1488 if (count++ >= MAX_DCMDS) {
1489 printk(KERN_WARNING "%s: DMA table too small\n",
1490 drive->name);
1491 goto use_pio_instead;
1492 }
1493 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1494 st_le16(&table->req_count, tc);
1495 st_le32(&table->phy_addr, cur_addr);
1496 table->cmd_dep = 0;
1497 table->xfer_status = 0;
1498 table->res_count = 0;
1499 cur_addr += tc;
1500 cur_len -= tc;
1501 ++table;
1502 }
1503 sg = sg_next(sg);
1504 i--;
1505 }
1506
1507 /* convert the last command to an input/output last command */
1508 if (count) {
1509 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1510 /* add the stop command to the end of the list */
1511 memset(table, 0, sizeof(struct dbdma_cmd));
1512 st_le16(&table->command, DBDMA_STOP);
1513 mb();
1514 writel(hwif->dmatable_dma, &dma->cmdptr);
1515 return 1;
1516 }
1517
1518 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1519
1520use_pio_instead:
1521 ide_destroy_dmatable(drive);
1522
1523 return 0; /* revert to PIO for this request */
1524}
1525
1526/*
1527 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1528 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1529 */
1530static int
1531pmac_ide_dma_setup(ide_drive_t *drive)
1532{
1533 ide_hwif_t *hwif = HWIF(drive);
1534 pmac_ide_hwif_t *pmif =
1535 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1536 struct request *rq = HWGROUP(drive)->rq;
1537 u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
1538
1539 if (!pmac_ide_build_dmatable(drive, rq)) {
1540 ide_map_sg(drive, rq);
1541 return 1;
1542 }
1543
1544 /* Apple adds 60ns to wrDataSetup on reads */
1545 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1546 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1547 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1548 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1549 }
1550
1551 drive->waiting_for_dma = 1;
1552
1553 return 0;
1554}
1555
1556static void
1557pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1558{
1559 /* issue cmd to drive */
1560 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1561}
1562
1563/*
1564 * Kick the DMA controller into life after the DMA command has been issued
1565 * to the drive.
1566 */
1567static void
1568pmac_ide_dma_start(ide_drive_t *drive)
1569{
1570 ide_hwif_t *hwif = drive->hwif;
1571 pmac_ide_hwif_t *pmif =
1572 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1573 volatile struct dbdma_regs __iomem *dma;
1574
1575 dma = pmif->dma_regs;
1576
1577 writel((RUN << 16) | RUN, &dma->control);
1578 /* Make sure it gets to the controller right now */
1579 (void)readl(&dma->control);
1580}
1581
1582/*
1583 * After a DMA transfer, make sure the controller is stopped
1584 */
1585static int
1586pmac_ide_dma_end (ide_drive_t *drive)
1587{
1588 ide_hwif_t *hwif = drive->hwif;
1589 pmac_ide_hwif_t *pmif =
1590 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1591 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1592 u32 dstat;
1593
1594 drive->waiting_for_dma = 0;
1595 dstat = readl(&dma->status);
1596 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1597
1598 ide_destroy_dmatable(drive);
1599
1600 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1601 * in theory, but with ATAPI decices doing buffer underruns, that would
1602 * cause us to disable DMA, which isn't what we want
1603 */
1604 return (dstat & (RUN|DEAD)) != RUN;
1605}
1606
1607/*
1608 * Check out that the interrupt we got was for us. We can't always know this
1609 * for sure with those Apple interfaces (well, we could on the recent ones but
1610 * that's not implemented yet), on the other hand, we don't have shared interrupts
1611 * so it's not really a problem
1612 */
1613static int
1614pmac_ide_dma_test_irq (ide_drive_t *drive)
1615{
1616 ide_hwif_t *hwif = drive->hwif;
1617 pmac_ide_hwif_t *pmif =
1618 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1619 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1620 unsigned long status, timeout;
1621
1622 /* We have to things to deal with here:
1623 *
1624 * - The dbdma won't stop if the command was started
1625 * but completed with an error without transferring all
1626 * datas. This happens when bad blocks are met during
1627 * a multi-block transfer.
1628 *
1629 * - The dbdma fifo hasn't yet finished flushing to
1630 * to system memory when the disk interrupt occurs.
1631 *
1632 */
1633
1634 /* If ACTIVE is cleared, the STOP command have passed and
1635 * transfer is complete.
1636 */
1637 status = readl(&dma->status);
1638 if (!(status & ACTIVE))
1639 return 1;
1640
1641 /* If dbdma didn't execute the STOP command yet, the
1642 * active bit is still set. We consider that we aren't
1643 * sharing interrupts (which is hopefully the case with
1644 * those controllers) and so we just try to flush the
1645 * channel for pending data in the fifo
1646 */
1647 udelay(1);
1648 writel((FLUSH << 16) | FLUSH, &dma->control);
1649 timeout = 0;
1650 for (;;) {
1651 udelay(1);
1652 status = readl(&dma->status);
1653 if ((status & FLUSH) == 0)
1654 break;
1655 if (++timeout > 100) {
1656 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1657 timeout flushing channel\n", HWIF(drive)->index);
1658 break;
1659 }
1660 }
1661 return 1;
1662}
1663
1664static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
1665{
1666}
1667
1668static void
1669pmac_ide_dma_lost_irq (ide_drive_t *drive)
1670{
1671 ide_hwif_t *hwif = drive->hwif;
1672 pmac_ide_hwif_t *pmif =
1673 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1674 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1675 unsigned long status = readl(&dma->status);
1676
1677 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1678}
1679
1680static const struct ide_dma_ops pmac_dma_ops = {
1681 .dma_host_set = pmac_ide_dma_host_set,
1682 .dma_setup = pmac_ide_dma_setup,
1683 .dma_exec_cmd = pmac_ide_dma_exec_cmd,
1684 .dma_start = pmac_ide_dma_start,
1685 .dma_end = pmac_ide_dma_end,
1686 .dma_test_irq = pmac_ide_dma_test_irq,
1687 .dma_timeout = ide_dma_timeout,
1688 .dma_lost_irq = pmac_ide_dma_lost_irq,
1689};
1690
1691/*
1692 * Allocate the data structures needed for using DMA with an interface
1693 * and fill the proper list of functions pointers
1694 */
1695static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1696 const struct ide_port_info *d)
1697{
1698 pmac_ide_hwif_t *pmif =
1699 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1700 struct pci_dev *dev = to_pci_dev(hwif->dev);
1701
1702 /* We won't need pci_dev if we switch to generic consistent
1703 * DMA routines ...
1704 */
1705 if (dev == NULL || pmif->dma_regs == 0)
1706 return -ENODEV;
1707 /*
1708 * Allocate space for the DBDMA commands.
1709 * The +2 is +1 for the stop command and +1 to allow for
1710 * aligning the start address to a multiple of 16 bytes.
1711 */
1712 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
1713 dev,
1714 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1715 &hwif->dmatable_dma);
1716 if (pmif->dma_table_cpu == NULL) {
1717 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1718 hwif->name);
1719 return -ENOMEM;
1720 }
1721
1722 hwif->sg_max_nents = MAX_DCMDS;
1723
1724 return 0;
1725}
1726#else
1727static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1728 const struct ide_port_info *d)
1729{
1730 return -EOPNOTSUPP;
1731}
1732#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1733
1734module_init(pmac_ide_probe);
1735
1736MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 13:55:12 -0500