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path: root/drivers/ide/pdc202xx_old.c
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Diffstat (limited to 'drivers/ide/pdc202xx_old.c')
-rw-r--r--drivers/ide/pdc202xx_old.c92
1 files changed, 3 insertions, 89 deletions
diff --git a/drivers/ide/pdc202xx_old.c b/drivers/ide/pdc202xx_old.c
index e24ecc87a9b1..b6abf7e52cac 100644
--- a/drivers/ide/pdc202xx_old.c
+++ b/drivers/ide/pdc202xx_old.c
@@ -23,18 +23,6 @@
23 23
24#define PDC202XX_DEBUG_DRIVE_INFO 0 24#define PDC202XX_DEBUG_DRIVE_INFO 0
25 25
26static const char *pdc_quirk_drives[] = {
27 "QUANTUM FIREBALLlct08 08",
28 "QUANTUM FIREBALLP KA6.4",
29 "QUANTUM FIREBALLP KA9.1",
30 "QUANTUM FIREBALLP LM20.4",
31 "QUANTUM FIREBALLP KX13.6",
32 "QUANTUM FIREBALLP KX20.5",
33 "QUANTUM FIREBALLP KX27.3",
34 "QUANTUM FIREBALLP LM20.5",
35 NULL
36};
37
38static void pdc_old_disable_66MHz_clock(ide_hwif_t *); 26static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
39 27
40static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed) 28static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
@@ -151,19 +139,6 @@ static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
151 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); 139 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
152} 140}
153 141
154static void pdc202xx_quirkproc(ide_drive_t *drive)
155{
156 const char **list, *m = (char *)&drive->id[ATA_ID_PROD];
157
158 for (list = pdc_quirk_drives; *list != NULL; list++)
159 if (strstr(m, *list) != NULL) {
160 drive->quirk_list = 2;
161 return;
162 }
163
164 drive->quirk_list = 0;
165}
166
167static void pdc202xx_dma_start(ide_drive_t *drive) 142static void pdc202xx_dma_start(ide_drive_t *drive)
168{ 143{
169 if (drive->current_speed > XFER_UDMA_2) 144 if (drive->current_speed > XFER_UDMA_2)
@@ -203,52 +178,6 @@ static int pdc202xx_dma_end(ide_drive_t *drive)
203 return ide_dma_end(drive); 178 return ide_dma_end(drive);
204} 179}
205 180
206static int pdc202xx_dma_test_irq(ide_drive_t *drive)
207{
208 ide_hwif_t *hwif = drive->hwif;
209 unsigned long high_16 = hwif->extra_base - 16;
210 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
211 u8 sc1d = inb(high_16 + 0x001d);
212
213 if (hwif->channel) {
214 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
215 if ((sc1d & 0x50) == 0x50)
216 goto somebody_else;
217 else if ((sc1d & 0x40) == 0x40)
218 return (dma_stat & 4) == 4;
219 } else {
220 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
221 if ((sc1d & 0x05) == 0x05)
222 goto somebody_else;
223 else if ((sc1d & 0x04) == 0x04)
224 return (dma_stat & 4) == 4;
225 }
226somebody_else:
227 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
228}
229
230static void pdc202xx_reset(ide_drive_t *drive)
231{
232 ide_hwif_t *hwif = drive->hwif;
233 unsigned long high_16 = hwif->extra_base - 16;
234 u8 udma_speed_flag = inb(high_16 | 0x001f);
235
236 printk(KERN_WARNING "PDC202xx: software reset...\n");
237
238 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
239 mdelay(100);
240 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
241 mdelay(2000); /* 2 seconds ?! */
242
243 ide_set_max_pio(drive);
244}
245
246static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
247{
248 pdc202xx_reset(drive);
249 ide_dma_lost_irq(drive);
250}
251
252static int init_chipset_pdc202xx(struct pci_dev *dev) 181static int init_chipset_pdc202xx(struct pci_dev *dev)
253{ 182{
254 unsigned long dmabase = pci_resource_start(dev, 4); 183 unsigned long dmabase = pci_resource_start(dev, 4);
@@ -302,37 +231,22 @@ static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
302static const struct ide_port_ops pdc20246_port_ops = { 231static const struct ide_port_ops pdc20246_port_ops = {
303 .set_pio_mode = pdc202xx_set_pio_mode, 232 .set_pio_mode = pdc202xx_set_pio_mode,
304 .set_dma_mode = pdc202xx_set_mode, 233 .set_dma_mode = pdc202xx_set_mode,
305 .quirkproc = pdc202xx_quirkproc,
306}; 234};
307 235
308static const struct ide_port_ops pdc2026x_port_ops = { 236static const struct ide_port_ops pdc2026x_port_ops = {
309 .set_pio_mode = pdc202xx_set_pio_mode, 237 .set_pio_mode = pdc202xx_set_pio_mode,
310 .set_dma_mode = pdc202xx_set_mode, 238 .set_dma_mode = pdc202xx_set_mode,
311 .quirkproc = pdc202xx_quirkproc,
312 .resetproc = pdc202xx_reset,
313 .cable_detect = pdc2026x_cable_detect, 239 .cable_detect = pdc2026x_cable_detect,
314}; 240};
315 241
316static const struct ide_dma_ops pdc20246_dma_ops = {
317 .dma_host_set = ide_dma_host_set,
318 .dma_setup = ide_dma_setup,
319 .dma_start = ide_dma_start,
320 .dma_end = ide_dma_end,
321 .dma_test_irq = pdc202xx_dma_test_irq,
322 .dma_lost_irq = ide_dma_lost_irq,
323 .dma_timer_expiry = ide_dma_sff_timer_expiry,
324 .dma_sff_read_status = ide_dma_sff_read_status,
325};
326
327static const struct ide_dma_ops pdc2026x_dma_ops = { 242static const struct ide_dma_ops pdc2026x_dma_ops = {
328 .dma_host_set = ide_dma_host_set, 243 .dma_host_set = ide_dma_host_set,
329 .dma_setup = ide_dma_setup, 244 .dma_setup = ide_dma_setup,
330 .dma_start = pdc202xx_dma_start, 245 .dma_start = pdc202xx_dma_start,
331 .dma_end = pdc202xx_dma_end, 246 .dma_end = pdc202xx_dma_end,
332 .dma_test_irq = pdc202xx_dma_test_irq, 247 .dma_test_irq = ide_dma_test_irq,
333 .dma_lost_irq = pdc202xx_dma_lost_irq, 248 .dma_lost_irq = ide_dma_lost_irq,
334 .dma_timer_expiry = ide_dma_sff_timer_expiry, 249 .dma_timer_expiry = ide_dma_sff_timer_expiry,
335 .dma_clear = pdc202xx_reset,
336 .dma_sff_read_status = ide_dma_sff_read_status, 250 .dma_sff_read_status = ide_dma_sff_read_status,
337}; 251};
338 252
@@ -354,7 +268,7 @@ static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
354 .name = DRV_NAME, 268 .name = DRV_NAME,
355 .init_chipset = init_chipset_pdc202xx, 269 .init_chipset = init_chipset_pdc202xx,
356 .port_ops = &pdc20246_port_ops, 270 .port_ops = &pdc20246_port_ops,
357 .dma_ops = &pdc20246_dma_ops, 271 .dma_ops = &sff_dma_ops,
358 .host_flags = IDE_HFLAGS_PDC202XX, 272 .host_flags = IDE_HFLAGS_PDC202XX,
359 .pio_mask = ATA_PIO4, 273 .pio_mask = ATA_PIO4,
360 .mwdma_mask = ATA_MWDMA2, 274 .mwdma_mask = ATA_MWDMA2,