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-rw-r--r--drivers/ide/pci/aec62xx.c13
-rw-r--r--drivers/ide/pci/alim15x3.c3
-rw-r--r--drivers/ide/pci/amd74xx.c1
-rw-r--r--drivers/ide/pci/atiixp.c3
-rw-r--r--drivers/ide/pci/cmd64x.c10
-rw-r--r--drivers/ide/pci/cs5520.c1
-rw-r--r--drivers/ide/pci/cs5530.c2
-rw-r--r--drivers/ide/pci/cs5535.c2
-rw-r--r--drivers/ide/pci/hpt34x.c12
-rw-r--r--drivers/ide/pci/hpt366.c194
-rw-r--r--drivers/ide/pci/it8213.c21
-rw-r--r--drivers/ide/pci/pdc202xx_new.c64
-rw-r--r--drivers/ide/pci/pdc202xx_old.c24
-rw-r--r--drivers/ide/pci/piix.c17
-rw-r--r--drivers/ide/pci/sc1200.c172
-rw-r--r--drivers/ide/pci/scc_pata.c14
-rw-r--r--drivers/ide/pci/serverworks.c17
-rw-r--r--drivers/ide/pci/sgiioc4.c1
-rw-r--r--drivers/ide/pci/siimage.c29
-rw-r--r--drivers/ide/pci/sis5513.c99
-rw-r--r--drivers/ide/pci/sl82c105.c40
-rw-r--r--drivers/ide/pci/slc90e66.c14
-rw-r--r--drivers/ide/pci/tc86c001.c3
-rw-r--r--drivers/ide/pci/triflex.c2
-rw-r--r--drivers/ide/pci/via82cxxx.c1
25 files changed, 293 insertions, 466 deletions
diff --git a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c
index 44268504ae43..7f4d1857d555 100644
--- a/drivers/ide/pci/aec62xx.c
+++ b/drivers/ide/pci/aec62xx.c
@@ -202,6 +202,7 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
202 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 202 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
203 .host_flags = IDE_HFLAG_SERIALIZE | 203 .host_flags = IDE_HFLAG_SERIALIZE |
204 IDE_HFLAG_NO_ATAPI_DMA | 204 IDE_HFLAG_NO_ATAPI_DMA |
205 IDE_HFLAG_ABUSE_SET_DMA_MODE |
205 IDE_HFLAG_OFF_BOARD, 206 IDE_HFLAG_OFF_BOARD,
206 .pio_mask = ATA_PIO4, 207 .pio_mask = ATA_PIO4,
207 .mwdma_mask = ATA_MWDMA2, 208 .mwdma_mask = ATA_MWDMA2,
@@ -211,6 +212,7 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
211 .init_chipset = init_chipset_aec62xx, 212 .init_chipset = init_chipset_aec62xx,
212 .init_hwif = init_hwif_aec62xx, 213 .init_hwif = init_hwif_aec62xx,
213 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA | 214 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
215 IDE_HFLAG_ABUSE_SET_DMA_MODE |
214 IDE_HFLAG_OFF_BOARD, 216 IDE_HFLAG_OFF_BOARD,
215 .pio_mask = ATA_PIO4, 217 .pio_mask = ATA_PIO4,
216 .mwdma_mask = ATA_MWDMA2, 218 .mwdma_mask = ATA_MWDMA2,
@@ -220,7 +222,8 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
220 .init_chipset = init_chipset_aec62xx, 222 .init_chipset = init_chipset_aec62xx,
221 .init_hwif = init_hwif_aec62xx, 223 .init_hwif = init_hwif_aec62xx,
222 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 224 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
223 .host_flags = IDE_HFLAG_NO_ATAPI_DMA, 225 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
226 IDE_HFLAG_ABUSE_SET_DMA_MODE,
224 .pio_mask = ATA_PIO4, 227 .pio_mask = ATA_PIO4,
225 .mwdma_mask = ATA_MWDMA2, 228 .mwdma_mask = ATA_MWDMA2,
226 .udma_mask = ATA_UDMA4, 229 .udma_mask = ATA_UDMA4,
@@ -228,7 +231,9 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
228 .name = "AEC6280", 231 .name = "AEC6280",
229 .init_chipset = init_chipset_aec62xx, 232 .init_chipset = init_chipset_aec62xx,
230 .init_hwif = init_hwif_aec62xx, 233 .init_hwif = init_hwif_aec62xx,
231 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, 234 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
235 IDE_HFLAG_ABUSE_SET_DMA_MODE |
236 IDE_HFLAG_OFF_BOARD,
232 .pio_mask = ATA_PIO4, 237 .pio_mask = ATA_PIO4,
233 .mwdma_mask = ATA_MWDMA2, 238 .mwdma_mask = ATA_MWDMA2,
234 .udma_mask = ATA_UDMA5, 239 .udma_mask = ATA_UDMA5,
@@ -237,7 +242,9 @@ static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
237 .init_chipset = init_chipset_aec62xx, 242 .init_chipset = init_chipset_aec62xx,
238 .init_hwif = init_hwif_aec62xx, 243 .init_hwif = init_hwif_aec62xx,
239 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 244 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
240 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, 245 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
246 IDE_HFLAG_ABUSE_SET_DMA_MODE |
247 IDE_HFLAG_OFF_BOARD,
241 .pio_mask = ATA_PIO4, 248 .pio_mask = ATA_PIO4,
242 .mwdma_mask = ATA_MWDMA2, 249 .mwdma_mask = ATA_MWDMA2,
243 .udma_mask = ATA_UDMA5, 250 .udma_mask = ATA_UDMA5,
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c
index ce293936af4b..49aa82e412b6 100644
--- a/drivers/ide/pci/alim15x3.c
+++ b/drivers/ide/pci/alim15x3.c
@@ -402,9 +402,6 @@ static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
402 u8 tmpbyte = 0x00; 402 u8 tmpbyte = 0x00;
403 int m5229_udma = (hwif->channel) ? 0x57 : 0x56; 403 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
404 404
405 if (speed < XFER_PIO_0)
406 return;
407
408 if (speed == XFER_UDMA_6) 405 if (speed == XFER_UDMA_6)
409 speed1 = 0x47; 406 speed1 = 0x47;
410 407
diff --git a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c
index 8d4125ec252c..cee51fdafcf6 100644
--- a/drivers/ide/pci/amd74xx.c
+++ b/drivers/ide/pci/amd74xx.c
@@ -266,6 +266,7 @@ static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
266#define IDE_HFLAGS_AMD \ 266#define IDE_HFLAGS_AMD \
267 (IDE_HFLAG_PIO_NO_BLACKLIST | \ 267 (IDE_HFLAG_PIO_NO_BLACKLIST | \
268 IDE_HFLAG_PIO_NO_DOWNGRADE | \ 268 IDE_HFLAG_PIO_NO_DOWNGRADE | \
269 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
269 IDE_HFLAG_POST_SET_MODE | \ 270 IDE_HFLAG_POST_SET_MODE | \
270 IDE_HFLAG_IO_32BIT | \ 271 IDE_HFLAG_IO_32BIT | \
271 IDE_HFLAG_UNMASK_IRQS | \ 272 IDE_HFLAG_UNMASK_IRQS | \
diff --git a/drivers/ide/pci/atiixp.c b/drivers/ide/pci/atiixp.c
index ef8e0164ef7a..5ae26564fb72 100644
--- a/drivers/ide/pci/atiixp.c
+++ b/drivers/ide/pci/atiixp.c
@@ -133,9 +133,6 @@ static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
133 u32 tmp32; 133 u32 tmp32;
134 u16 tmp16; 134 u16 tmp16;
135 135
136 if (speed < XFER_MW_DMA_0)
137 return;
138
139 spin_lock_irqsave(&atiixp_lock, flags); 136 spin_lock_irqsave(&atiixp_lock, flags);
140 137
141 save_mdma_mode[drive->dn] = 0; 138 save_mdma_mode[drive->dn] = 0;
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
index bc553337b1be..0b1e9479f019 100644
--- a/drivers/ide/pci/cmd64x.c
+++ b/drivers/ide/pci/cmd64x.c
@@ -322,8 +322,6 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
322 case XFER_MW_DMA_0: 322 case XFER_MW_DMA_0:
323 program_cycle_times(drive, 480, 215); 323 program_cycle_times(drive, 480, 215);
324 break; 324 break;
325 default:
326 return;
327 } 325 }
328 326
329 if (speed >= XFER_SW_DMA_0) 327 if (speed >= XFER_SW_DMA_0)
@@ -333,14 +331,15 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
333static int cmd648_ide_dma_end (ide_drive_t *drive) 331static int cmd648_ide_dma_end (ide_drive_t *drive)
334{ 332{
335 ide_hwif_t *hwif = HWIF(drive); 333 ide_hwif_t *hwif = HWIF(drive);
334 unsigned long base = hwif->dma_base - (hwif->channel * 8);
336 int err = __ide_dma_end(drive); 335 int err = __ide_dma_end(drive);
337 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : 336 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
338 MRDMODE_INTR_CH0; 337 MRDMODE_INTR_CH0;
339 u8 mrdmode = inb(hwif->dma_master + 0x01); 338 u8 mrdmode = inb(base + 1);
340 339
341 /* clear the interrupt bit */ 340 /* clear the interrupt bit */
342 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask, 341 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
343 hwif->dma_master + 0x01); 342 base + 1);
344 343
345 return err; 344 return err;
346} 345}
@@ -365,10 +364,11 @@ static int cmd64x_ide_dma_end (ide_drive_t *drive)
365static int cmd648_ide_dma_test_irq (ide_drive_t *drive) 364static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
366{ 365{
367 ide_hwif_t *hwif = HWIF(drive); 366 ide_hwif_t *hwif = HWIF(drive);
367 unsigned long base = hwif->dma_base - (hwif->channel * 8);
368 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : 368 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
369 MRDMODE_INTR_CH0; 369 MRDMODE_INTR_CH0;
370 u8 dma_stat = inb(hwif->dma_status); 370 u8 dma_stat = inb(hwif->dma_status);
371 u8 mrdmode = inb(hwif->dma_master + 0x01); 371 u8 mrdmode = inb(base + 1);
372 372
373#ifdef DEBUG 373#ifdef DEBUG
374 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n", 374 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
diff --git a/drivers/ide/pci/cs5520.c b/drivers/ide/pci/cs5520.c
index 0466462fd21b..d1a91bcb5b29 100644
--- a/drivers/ide/pci/cs5520.c
+++ b/drivers/ide/pci/cs5520.c
@@ -137,6 +137,7 @@ static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
137 IDE_HFLAG_CS5520 | \ 137 IDE_HFLAG_CS5520 | \
138 IDE_HFLAG_VDMA | \ 138 IDE_HFLAG_VDMA | \
139 IDE_HFLAG_NO_ATAPI_DMA | \ 139 IDE_HFLAG_NO_ATAPI_DMA | \
140 IDE_HFLAG_ABUSE_SET_DMA_MODE |\
140 IDE_HFLAG_BOOTABLE, \ 141 IDE_HFLAG_BOOTABLE, \
141 .pio_mask = ATA_PIO4, \ 142 .pio_mask = ATA_PIO4, \
142 } 143 }
diff --git a/drivers/ide/pci/cs5530.c b/drivers/ide/pci/cs5530.c
index 547690395eee..df5966b33460 100644
--- a/drivers/ide/pci/cs5530.c
+++ b/drivers/ide/pci/cs5530.c
@@ -116,8 +116,6 @@ static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
116 case XFER_MW_DMA_0: timings = 0x00077771; break; 116 case XFER_MW_DMA_0: timings = 0x00077771; break;
117 case XFER_MW_DMA_1: timings = 0x00012121; break; 117 case XFER_MW_DMA_1: timings = 0x00012121; break;
118 case XFER_MW_DMA_2: timings = 0x00002020; break; 118 case XFER_MW_DMA_2: timings = 0x00002020; break;
119 default:
120 return;
121 } 119 }
122 basereg = CS5530_BASEREG(drive->hwif); 120 basereg = CS5530_BASEREG(drive->hwif);
123 reg = inl(basereg + 4); /* get drive0 config register */ 121 reg = inl(basereg + 4); /* get drive0 config register */
diff --git a/drivers/ide/pci/cs5535.c b/drivers/ide/pci/cs5535.c
index ddcbeba671e1..50b3d7791f55 100644
--- a/drivers/ide/pci/cs5535.c
+++ b/drivers/ide/pci/cs5535.c
@@ -190,7 +190,7 @@ static const struct ide_port_info cs5535_chipset __devinitdata = {
190 .name = "CS5535", 190 .name = "CS5535",
191 .init_hwif = init_hwif_cs5535, 191 .init_hwif = init_hwif_cs5535,
192 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE | 192 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE |
193 IDE_HFLAG_BOOTABLE, 193 IDE_HFLAG_ABUSE_SET_DMA_MODE | IDE_HFLAG_BOOTABLE,
194 .pio_mask = ATA_PIO4, 194 .pio_mask = ATA_PIO4,
195 .mwdma_mask = ATA_MWDMA2, 195 .mwdma_mask = ATA_MWDMA2,
196 .udma_mask = ATA_UDMA4, 196 .udma_mask = ATA_UDMA4,
diff --git a/drivers/ide/pci/hpt34x.c b/drivers/ide/pci/hpt34x.c
index ae6307fae4f9..dfba0d13fcd3 100644
--- a/drivers/ide/pci/hpt34x.c
+++ b/drivers/ide/pci/hpt34x.c
@@ -129,14 +129,18 @@ static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
129 hwif->set_dma_mode = &hpt34x_set_mode; 129 hwif->set_dma_mode = &hpt34x_set_mode;
130} 130}
131 131
132#define IDE_HFLAGS_HPT34X \
133 (IDE_HFLAG_NO_ATAPI_DMA | \
134 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
135 IDE_HFLAG_NO_AUTODMA)
136
132static const struct ide_port_info hpt34x_chipsets[] __devinitdata = { 137static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
133 { /* 0 */ 138 { /* 0 */
134 .name = "HPT343", 139 .name = "HPT343",
135 .init_chipset = init_chipset_hpt34x, 140 .init_chipset = init_chipset_hpt34x,
136 .init_hwif = init_hwif_hpt34x, 141 .init_hwif = init_hwif_hpt34x,
137 .extra = 16, 142 .extra = 16,
138 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | 143 .host_flags = IDE_HFLAGS_HPT34X,
139 IDE_HFLAG_NO_AUTODMA,
140 .pio_mask = ATA_PIO5, 144 .pio_mask = ATA_PIO5,
141 }, 145 },
142 { /* 1 */ 146 { /* 1 */
@@ -144,9 +148,7 @@ static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
144 .init_chipset = init_chipset_hpt34x, 148 .init_chipset = init_chipset_hpt34x,
145 .init_hwif = init_hwif_hpt34x, 149 .init_hwif = init_hwif_hpt34x,
146 .extra = 16, 150 .extra = 16,
147 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | 151 .host_flags = IDE_HFLAGS_HPT34X | IDE_HFLAG_OFF_BOARD,
148 IDE_HFLAG_NO_AUTODMA |
149 IDE_HFLAG_OFF_BOARD,
150 .pio_mask = ATA_PIO5, 152 .pio_mask = ATA_PIO5,
151#ifdef CONFIG_HPT34X_AUTODMA 153#ifdef CONFIG_HPT34X_AUTODMA
152 .swdma_mask = ATA_SWDMA2, 154 .swdma_mask = ATA_SWDMA2,
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index 9fce25bdec8a..3777fb8c8043 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/hpt366.c Version 1.22 Dec 4, 2007 2 * linux/drivers/ide/pci/hpt366.c Version 1.30 Dec 12, 2007
3 * 3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
@@ -88,7 +88,7 @@
88 * - rename all the register related variables consistently 88 * - rename all the register related variables consistently
89 * - move all the interrupt twiddling code from the speedproc handlers into 89 * - move all the interrupt twiddling code from the speedproc handlers into
90 * init_hwif_hpt366(), also grouping all the DMA related code together there 90 * init_hwif_hpt366(), also grouping all the DMA related code together there
91 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and 91 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
92 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings 92 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
93 * when setting an UltraDMA mode 93 * when setting an UltraDMA mode
94 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select 94 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
@@ -458,6 +458,13 @@ enum ata_clock {
458 NUM_ATA_CLOCKS 458 NUM_ATA_CLOCKS
459}; 459};
460 460
461struct hpt_timings {
462 u32 pio_mask;
463 u32 dma_mask;
464 u32 ultra_mask;
465 u32 *clock_table[NUM_ATA_CLOCKS];
466};
467
461/* 468/*
462 * Hold all the HighPoint chip information in one place. 469 * Hold all the HighPoint chip information in one place.
463 */ 470 */
@@ -468,7 +475,8 @@ struct hpt_info {
468 u8 udma_mask; /* Allowed UltraDMA modes mask. */ 475 u8 udma_mask; /* Allowed UltraDMA modes mask. */
469 u8 dpll_clk; /* DPLL clock in MHz */ 476 u8 dpll_clk; /* DPLL clock in MHz */
470 u8 pci_clk; /* PCI clock in MHz */ 477 u8 pci_clk; /* PCI clock in MHz */
471 u32 **settings; /* Chipset settings table */ 478 struct hpt_timings *timings; /* Chipset timing data */
479 u8 clock; /* ATA clock selected */
472}; 480};
473 481
474/* Supported HighPoint chips */ 482/* Supported HighPoint chips */
@@ -486,20 +494,30 @@ enum {
486 HPT371N 494 HPT371N
487}; 495};
488 496
489static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = { 497static struct hpt_timings hpt36x_timings = {
490 twenty_five_base_hpt36x, 498 .pio_mask = 0xc1f8ffff,
491 thirty_three_base_hpt36x, 499 .dma_mask = 0x303800ff,
492 forty_base_hpt36x, 500 .ultra_mask = 0x30070000,
493 NULL, 501 .clock_table = {
494 NULL 502 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
503 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
504 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
505 [ATA_CLOCK_50MHZ] = NULL,
506 [ATA_CLOCK_66MHZ] = NULL
507 }
495}; 508};
496 509
497static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = { 510static struct hpt_timings hpt37x_timings = {
498 NULL, 511 .pio_mask = 0xcfc3ffff,
499 thirty_three_base_hpt37x, 512 .dma_mask = 0x31c001ff,
500 NULL, 513 .ultra_mask = 0x303c0000,
501 fifty_base_hpt37x, 514 .clock_table = {
502 sixty_six_base_hpt37x 515 [ATA_CLOCK_25MHZ] = NULL,
516 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
517 [ATA_CLOCK_40MHZ] = NULL,
518 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
519 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
520 }
503}; 521};
504 522
505static const struct hpt_info hpt36x __devinitdata = { 523static const struct hpt_info hpt36x __devinitdata = {
@@ -507,7 +525,7 @@ static const struct hpt_info hpt36x __devinitdata = {
507 .chip_type = HPT36x, 525 .chip_type = HPT36x,
508 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2, 526 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
509 .dpll_clk = 0, /* no DPLL */ 527 .dpll_clk = 0, /* no DPLL */
510 .settings = hpt36x_settings 528 .timings = &hpt36x_timings
511}; 529};
512 530
513static const struct hpt_info hpt370 __devinitdata = { 531static const struct hpt_info hpt370 __devinitdata = {
@@ -515,7 +533,7 @@ static const struct hpt_info hpt370 __devinitdata = {
515 .chip_type = HPT370, 533 .chip_type = HPT370,
516 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 534 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
517 .dpll_clk = 48, 535 .dpll_clk = 48,
518 .settings = hpt37x_settings 536 .timings = &hpt37x_timings
519}; 537};
520 538
521static const struct hpt_info hpt370a __devinitdata = { 539static const struct hpt_info hpt370a __devinitdata = {
@@ -523,7 +541,7 @@ static const struct hpt_info hpt370a __devinitdata = {
523 .chip_type = HPT370A, 541 .chip_type = HPT370A,
524 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, 542 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
525 .dpll_clk = 48, 543 .dpll_clk = 48,
526 .settings = hpt37x_settings 544 .timings = &hpt37x_timings
527}; 545};
528 546
529static const struct hpt_info hpt374 __devinitdata = { 547static const struct hpt_info hpt374 __devinitdata = {
@@ -531,7 +549,7 @@ static const struct hpt_info hpt374 __devinitdata = {
531 .chip_type = HPT374, 549 .chip_type = HPT374,
532 .udma_mask = ATA_UDMA5, 550 .udma_mask = ATA_UDMA5,
533 .dpll_clk = 48, 551 .dpll_clk = 48,
534 .settings = hpt37x_settings 552 .timings = &hpt37x_timings
535}; 553};
536 554
537static const struct hpt_info hpt372 __devinitdata = { 555static const struct hpt_info hpt372 __devinitdata = {
@@ -539,7 +557,7 @@ static const struct hpt_info hpt372 __devinitdata = {
539 .chip_type = HPT372, 557 .chip_type = HPT372,
540 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 558 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
541 .dpll_clk = 55, 559 .dpll_clk = 55,
542 .settings = hpt37x_settings 560 .timings = &hpt37x_timings
543}; 561};
544 562
545static const struct hpt_info hpt372a __devinitdata = { 563static const struct hpt_info hpt372a __devinitdata = {
@@ -547,7 +565,7 @@ static const struct hpt_info hpt372a __devinitdata = {
547 .chip_type = HPT372A, 565 .chip_type = HPT372A,
548 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 566 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
549 .dpll_clk = 66, 567 .dpll_clk = 66,
550 .settings = hpt37x_settings 568 .timings = &hpt37x_timings
551}; 569};
552 570
553static const struct hpt_info hpt302 __devinitdata = { 571static const struct hpt_info hpt302 __devinitdata = {
@@ -555,7 +573,7 @@ static const struct hpt_info hpt302 __devinitdata = {
555 .chip_type = HPT302, 573 .chip_type = HPT302,
556 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 574 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
557 .dpll_clk = 66, 575 .dpll_clk = 66,
558 .settings = hpt37x_settings 576 .timings = &hpt37x_timings
559}; 577};
560 578
561static const struct hpt_info hpt371 __devinitdata = { 579static const struct hpt_info hpt371 __devinitdata = {
@@ -563,7 +581,7 @@ static const struct hpt_info hpt371 __devinitdata = {
563 .chip_type = HPT371, 581 .chip_type = HPT371,
564 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 582 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
565 .dpll_clk = 66, 583 .dpll_clk = 66,
566 .settings = hpt37x_settings 584 .timings = &hpt37x_timings
567}; 585};
568 586
569static const struct hpt_info hpt372n __devinitdata = { 587static const struct hpt_info hpt372n __devinitdata = {
@@ -571,7 +589,7 @@ static const struct hpt_info hpt372n __devinitdata = {
571 .chip_type = HPT372N, 589 .chip_type = HPT372N,
572 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 590 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
573 .dpll_clk = 77, 591 .dpll_clk = 77,
574 .settings = hpt37x_settings 592 .timings = &hpt37x_timings
575}; 593};
576 594
577static const struct hpt_info hpt302n __devinitdata = { 595static const struct hpt_info hpt302n __devinitdata = {
@@ -579,7 +597,7 @@ static const struct hpt_info hpt302n __devinitdata = {
579 .chip_type = HPT302N, 597 .chip_type = HPT302N,
580 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 598 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
581 .dpll_clk = 77, 599 .dpll_clk = 77,
582 .settings = hpt37x_settings 600 .timings = &hpt37x_timings
583}; 601};
584 602
585static const struct hpt_info hpt371n __devinitdata = { 603static const struct hpt_info hpt371n __devinitdata = {
@@ -587,7 +605,7 @@ static const struct hpt_info hpt371n __devinitdata = {
587 .chip_type = HPT371N, 605 .chip_type = HPT371N,
588 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, 606 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
589 .dpll_clk = 77, 607 .dpll_clk = 77,
590 .settings = hpt37x_settings 608 .timings = &hpt37x_timings
591}; 609};
592 610
593static int check_in_drive_list(ide_drive_t *drive, const char **list) 611static int check_in_drive_list(ide_drive_t *drive, const char **list)
@@ -675,71 +693,33 @@ static u32 get_speed_setting(u8 speed, struct hpt_info *info)
675 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) 693 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
676 if (xfer_speeds[i] == speed) 694 if (xfer_speeds[i] == speed)
677 break; 695 break;
678 /* 696
679 * NOTE: info->settings only points to the pointer 697 return info->timings->clock_table[info->clock][i];
680 * to the list of the actual register values
681 */
682 return (*info->settings)[i];
683} 698}
684 699
685static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed) 700static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
686{ 701{
687 ide_hwif_t *hwif = HWIF(drive); 702 struct pci_dev *dev = HWIF(drive)->pci_dev;
688 struct pci_dev *dev = hwif->pci_dev;
689 struct hpt_info *info = pci_get_drvdata(dev); 703 struct hpt_info *info = pci_get_drvdata(dev);
690 u8 itr_addr = drive->dn ? 0x44 : 0x40; 704 struct hpt_timings *t = info->timings;
705 u8 itr_addr = 0x40 + (drive->dn * 4);
691 u32 old_itr = 0; 706 u32 old_itr = 0;
692 u32 itr_mask, new_itr; 707 u32 new_itr = get_speed_setting(speed, info);
693 708 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
694 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 : 709 (speed < XFER_UDMA_0 ? t->dma_mask :
695 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff); 710 t->ultra_mask);
696
697 new_itr = get_speed_setting(speed, info);
698 711
712 pci_read_config_dword(dev, itr_addr, &old_itr);
713 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
699 /* 714 /*
700 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) 715 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
701 * to avoid problems handling I/O errors later 716 * to avoid problems handling I/O errors later
702 */ 717 */
703 pci_read_config_dword(dev, itr_addr, &old_itr);
704 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
705 new_itr &= ~0xc0000000; 718 new_itr &= ~0xc0000000;
706 719
707 pci_write_config_dword(dev, itr_addr, new_itr); 720 pci_write_config_dword(dev, itr_addr, new_itr);
708} 721}
709 722
710static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed)
711{
712 ide_hwif_t *hwif = HWIF(drive);
713 struct pci_dev *dev = hwif->pci_dev;
714 struct hpt_info *info = pci_get_drvdata(dev);
715 u8 itr_addr = 0x40 + (drive->dn * 4);
716 u32 old_itr = 0;
717 u32 itr_mask, new_itr;
718
719 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
720 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
721
722 new_itr = get_speed_setting(speed, info);
723
724 pci_read_config_dword(dev, itr_addr, &old_itr);
725 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
726
727 if (speed < XFER_MW_DMA_0)
728 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
729 pci_write_config_dword(dev, itr_addr, new_itr);
730}
731
732static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
733{
734 ide_hwif_t *hwif = HWIF(drive);
735 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
736
737 if (info->chip_type >= HPT370)
738 hpt37x_set_mode(drive, speed);
739 else /* hpt368: hpt_minimum_revision(dev, 2) */
740 hpt36x_set_mode(drive, speed);
741}
742
743static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) 723static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
744{ 724{
745 hpt3xx_set_mode(drive, XFER_PIO_0 + pio); 725 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
@@ -756,15 +736,6 @@ static int hpt3xx_quirkproc(ide_drive_t *drive)
756 return 0; 736 return 0;
757} 737}
758 738
759static void hpt3xx_intrproc(ide_drive_t *drive)
760{
761 if (drive->quirk_list)
762 return;
763
764 /* drives in the quirk_list may not like intr setups/cleanups */
765 outb(drive->ctl | 2, IDE_CONTROL_REG);
766}
767
768static void hpt3xx_maskproc(ide_drive_t *drive, int mask) 739static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
769{ 740{
770 ide_hwif_t *hwif = HWIF(drive); 741 ide_hwif_t *hwif = HWIF(drive);
@@ -914,32 +885,33 @@ static int hpt374_ide_dma_end(ide_drive_t *drive)
914 885
915static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) 886static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
916{ 887{
917 u8 scr2 = inb(hwif->dma_master + 0x7b); 888 unsigned long base = hwif->extra_base;
889 u8 scr2 = inb(base + 0x6b);
918 890
919 if ((scr2 & 0x7f) == mode) 891 if ((scr2 & 0x7f) == mode)
920 return; 892 return;
921 893
922 /* Tristate the bus */ 894 /* Tristate the bus */
923 outb(0x80, hwif->dma_master + 0x73); 895 outb(0x80, base + 0x63);
924 outb(0x80, hwif->dma_master + 0x77); 896 outb(0x80, base + 0x67);
925 897
926 /* Switch clock and reset channels */ 898 /* Switch clock and reset channels */
927 outb(mode, hwif->dma_master + 0x7b); 899 outb(mode, base + 0x6b);
928 outb(0xc0, hwif->dma_master + 0x79); 900 outb(0xc0, base + 0x69);
929 901
930 /* 902 /*
931 * Reset the state machines. 903 * Reset the state machines.
932 * NOTE: avoid accidentally enabling the disabled channels. 904 * NOTE: avoid accidentally enabling the disabled channels.
933 */ 905 */
934 outb(inb(hwif->dma_master + 0x70) | 0x32, hwif->dma_master + 0x70); 906 outb(inb(base + 0x60) | 0x32, base + 0x60);
935 outb(inb(hwif->dma_master + 0x74) | 0x32, hwif->dma_master + 0x74); 907 outb(inb(base + 0x64) | 0x32, base + 0x64);
936 908
937 /* Complete reset */ 909 /* Complete reset */
938 outb(0x00, hwif->dma_master + 0x79); 910 outb(0x00, base + 0x69);
939 911
940 /* Reconnect channels to bus */ 912 /* Reconnect channels to bus */
941 outb(0x00, hwif->dma_master + 0x73); 913 outb(0x00, base + 0x63);
942 outb(0x00, hwif->dma_master + 0x77); 914 outb(0x00, base + 0x67);
943} 915}
944 916
945/** 917/**
@@ -1210,7 +1182,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
1210 * We also don't like using the DPLL because this causes glitches 1182 * We also don't like using the DPLL because this causes glitches
1211 * on PRST-/SRST- when the state engine gets reset... 1183 * on PRST-/SRST- when the state engine gets reset...
1212 */ 1184 */
1213 if (chip_type >= HPT374 || info->settings[clock] == NULL) { 1185 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1214 u16 f_low, delta = pci_clk < 50 ? 2 : 4; 1186 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1215 int adjust; 1187 int adjust;
1216 1188
@@ -1226,7 +1198,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
1226 clock = ATA_CLOCK_50MHZ; 1198 clock = ATA_CLOCK_50MHZ;
1227 } 1199 }
1228 1200
1229 if (info->settings[clock] == NULL) { 1201 if (info->timings->clock_table[clock] == NULL) {
1230 printk(KERN_ERR "%s: unknown bus timing!\n", name); 1202 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1231 kfree(info); 1203 kfree(info);
1232 return -EIO; 1204 return -EIO;
@@ -1267,15 +1239,10 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
1267 printk("%s: using %d MHz PCI clock\n", name, pci_clk); 1239 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1268 } 1240 }
1269 1241
1270 /*
1271 * Advance the table pointer to a slot which points to the list
1272 * of the register values settings matching the clock being used.
1273 */
1274 info->settings += clock;
1275
1276 /* Store the clock frequencies. */ 1242 /* Store the clock frequencies. */
1277 info->dpll_clk = dpll_clk; 1243 info->dpll_clk = dpll_clk;
1278 info->pci_clk = pci_clk; 1244 info->pci_clk = pci_clk;
1245 info->clock = clock;
1279 1246
1280 /* Point to this chip's own instance of the hpt_info structure. */ 1247 /* Point to this chip's own instance of the hpt_info structure. */
1281 pci_set_drvdata(dev, info); 1248 pci_set_drvdata(dev, info);
@@ -1320,8 +1287,8 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1320 1287
1321 hwif->set_pio_mode = &hpt3xx_set_pio_mode; 1288 hwif->set_pio_mode = &hpt3xx_set_pio_mode;
1322 hwif->set_dma_mode = &hpt3xx_set_mode; 1289 hwif->set_dma_mode = &hpt3xx_set_mode;
1290
1323 hwif->quirkproc = &hpt3xx_quirkproc; 1291 hwif->quirkproc = &hpt3xx_quirkproc;
1324 hwif->intrproc = &hpt3xx_intrproc;
1325 hwif->maskproc = &hpt3xx_maskproc; 1292 hwif->maskproc = &hpt3xx_maskproc;
1326 hwif->busproc = &hpt3xx_busproc; 1293 hwif->busproc = &hpt3xx_busproc;
1327 1294
@@ -1494,6 +1461,11 @@ static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1494 return 0; 1461 return 0;
1495} 1462}
1496 1463
1464#define IDE_HFLAGS_HPT3XX \
1465 (IDE_HFLAG_NO_ATAPI_DMA | \
1466 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
1467 IDE_HFLAG_OFF_BOARD)
1468
1497static const struct ide_port_info hpt366_chipsets[] __devinitdata = { 1469static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1498 { /* 0 */ 1470 { /* 0 */
1499 .name = "HPT36x", 1471 .name = "HPT36x",
@@ -1508,9 +1480,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1508 */ 1480 */
1509 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, 1481 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1510 .extra = 240, 1482 .extra = 240,
1511 .host_flags = IDE_HFLAG_SINGLE | 1483 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1512 IDE_HFLAG_NO_ATAPI_DMA |
1513 IDE_HFLAG_OFF_BOARD,
1514 .pio_mask = ATA_PIO4, 1484 .pio_mask = ATA_PIO4,
1515 .mwdma_mask = ATA_MWDMA2, 1485 .mwdma_mask = ATA_MWDMA2,
1516 },{ /* 1 */ 1486 },{ /* 1 */
@@ -1520,7 +1490,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1520 .init_dma = init_dma_hpt366, 1490 .init_dma = init_dma_hpt366,
1521 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1491 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1522 .extra = 240, 1492 .extra = 240,
1523 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, 1493 .host_flags = IDE_HFLAGS_HPT3XX,
1524 .pio_mask = ATA_PIO4, 1494 .pio_mask = ATA_PIO4,
1525 .mwdma_mask = ATA_MWDMA2, 1495 .mwdma_mask = ATA_MWDMA2,
1526 },{ /* 2 */ 1496 },{ /* 2 */
@@ -1530,7 +1500,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1530 .init_dma = init_dma_hpt366, 1500 .init_dma = init_dma_hpt366,
1531 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1501 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1532 .extra = 240, 1502 .extra = 240,
1533 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, 1503 .host_flags = IDE_HFLAGS_HPT3XX,
1534 .pio_mask = ATA_PIO4, 1504 .pio_mask = ATA_PIO4,
1535 .mwdma_mask = ATA_MWDMA2, 1505 .mwdma_mask = ATA_MWDMA2,
1536 },{ /* 3 */ 1506 },{ /* 3 */
@@ -1540,7 +1510,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1540 .init_dma = init_dma_hpt366, 1510 .init_dma = init_dma_hpt366,
1541 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1511 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1542 .extra = 240, 1512 .extra = 240,
1543 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, 1513 .host_flags = IDE_HFLAGS_HPT3XX,
1544 .pio_mask = ATA_PIO4, 1514 .pio_mask = ATA_PIO4,
1545 .mwdma_mask = ATA_MWDMA2, 1515 .mwdma_mask = ATA_MWDMA2,
1546 },{ /* 4 */ 1516 },{ /* 4 */
@@ -1551,7 +1521,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1551 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1521 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1552 .udma_mask = ATA_UDMA5, 1522 .udma_mask = ATA_UDMA5,
1553 .extra = 240, 1523 .extra = 240,
1554 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, 1524 .host_flags = IDE_HFLAGS_HPT3XX,
1555 .pio_mask = ATA_PIO4, 1525 .pio_mask = ATA_PIO4,
1556 .mwdma_mask = ATA_MWDMA2, 1526 .mwdma_mask = ATA_MWDMA2,
1557 },{ /* 5 */ 1527 },{ /* 5 */
@@ -1561,7 +1531,7 @@ static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1561 .init_dma = init_dma_hpt366, 1531 .init_dma = init_dma_hpt366,
1562 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1532 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1563 .extra = 240, 1533 .extra = 240,
1564 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD, 1534 .host_flags = IDE_HFLAGS_HPT3XX,
1565 .pio_mask = ATA_PIO4, 1535 .pio_mask = ATA_PIO4,
1566 .mwdma_mask = ATA_MWDMA2, 1536 .mwdma_mask = ATA_MWDMA2,
1567 } 1537 }
diff --git a/drivers/ide/pci/it8213.c b/drivers/ide/pci/it8213.c
index 90b52ed37bfc..2a0f45c4f4c4 100644
--- a/drivers/ide/pci/it8213.c
+++ b/drivers/ide/pci/it8213.c
@@ -101,24 +101,11 @@ static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
101 pci_read_config_byte(dev, 0x54, &reg54); 101 pci_read_config_byte(dev, 0x54, &reg54);
102 pci_read_config_byte(dev, 0x55, &reg55); 102 pci_read_config_byte(dev, 0x55, &reg55);
103 103
104 switch(speed) {
105 case XFER_UDMA_6:
106 case XFER_UDMA_4:
107 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
108 case XFER_UDMA_5:
109 case XFER_UDMA_3:
110 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
111 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
112 break;
113 case XFER_MW_DMA_2:
114 case XFER_MW_DMA_1:
115 case XFER_SW_DMA_2:
116 break;
117 default:
118 return;
119 }
120
121 if (speed >= XFER_UDMA_0) { 104 if (speed >= XFER_UDMA_0) {
105 u8 udma = speed - XFER_UDMA_0;
106
107 u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
108
122 if (!(reg48 & u_flag)) 109 if (!(reg48 & u_flag))
123 pci_write_config_byte(dev, 0x48, reg48 | u_flag); 110 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
124 if (speed >= XFER_UDMA_5) { 111 if (speed >= XFER_UDMA_5) {
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index 2b4f44e45a1a..ef4a99b99d1f 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -146,7 +146,7 @@ static struct udma_timing {
146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ 146 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
147}; 147};
148 148
149static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed) 149static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
150{ 150{
151 ide_hwif_t *hwif = HWIF(drive); 151 ide_hwif_t *hwif = HWIF(drive);
152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00; 152 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
@@ -162,45 +162,18 @@ static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed)
162 if (max_dma_rate(hwif->pci_dev) == 4) { 162 if (max_dma_rate(hwif->pci_dev) == 4) {
163 u8 mode = speed & 0x07; 163 u8 mode = speed & 0x07;
164 164
165 switch (speed) { 165 if (speed >= XFER_UDMA_0) {
166 case XFER_UDMA_6: 166 set_indexed_reg(hwif, 0x10 + adj,
167 case XFER_UDMA_5: 167 udma_timings[mode].reg10);
168 case XFER_UDMA_4: 168 set_indexed_reg(hwif, 0x11 + adj,
169 case XFER_UDMA_3: 169 udma_timings[mode].reg11);
170 case XFER_UDMA_2: 170 set_indexed_reg(hwif, 0x12 + adj,
171 case XFER_UDMA_1: 171 udma_timings[mode].reg12);
172 case XFER_UDMA_0: 172 } else {
173 set_indexed_reg(hwif, 0x10 + adj, 173 set_indexed_reg(hwif, 0x0e + adj,
174 udma_timings[mode].reg10); 174 mwdma_timings[mode].reg0e);
175 set_indexed_reg(hwif, 0x11 + adj, 175 set_indexed_reg(hwif, 0x0f + adj,
176 udma_timings[mode].reg11); 176 mwdma_timings[mode].reg0f);
177 set_indexed_reg(hwif, 0x12 + adj,
178 udma_timings[mode].reg12);
179 break;
180
181 case XFER_MW_DMA_2:
182 case XFER_MW_DMA_1:
183 case XFER_MW_DMA_0:
184 set_indexed_reg(hwif, 0x0e + adj,
185 mwdma_timings[mode].reg0e);
186 set_indexed_reg(hwif, 0x0f + adj,
187 mwdma_timings[mode].reg0f);
188 break;
189 case XFER_PIO_4:
190 case XFER_PIO_3:
191 case XFER_PIO_2:
192 case XFER_PIO_1:
193 case XFER_PIO_0:
194 set_indexed_reg(hwif, 0x0c + adj,
195 pio_timings[mode].reg0c);
196 set_indexed_reg(hwif, 0x0d + adj,
197 pio_timings[mode].reg0d);
198 set_indexed_reg(hwif, 0x13 + adj,
199 pio_timings[mode].reg13);
200 break;
201 default:
202 printk(KERN_ERR "pdc202xx_new: "
203 "Unknown speed %d ignored\n", speed);
204 } 177 }
205 } else if (speed == XFER_UDMA_2) { 178 } else if (speed == XFER_UDMA_2) {
206 /* Set tHOLD bit to 0 if using UDMA mode 2 */ 179 /* Set tHOLD bit to 0 if using UDMA mode 2 */
@@ -212,7 +185,14 @@ static void pdcnew_set_mode(ide_drive_t *drive, const u8 speed)
212 185
213static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio) 186static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
214{ 187{
215 pdcnew_set_mode(drive, XFER_PIO_0 + pio); 188 ide_hwif_t *hwif = drive->hwif;
189 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
190
191 if (max_dma_rate(hwif->pci_dev) == 4) {
192 set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
193 set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
194 set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
195 }
216} 196}
217 197
218static u8 pdcnew_cable_detect(ide_hwif_t *hwif) 198static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
@@ -466,7 +446,7 @@ static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const cha
466static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif) 446static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
467{ 447{
468 hwif->set_pio_mode = &pdcnew_set_pio_mode; 448 hwif->set_pio_mode = &pdcnew_set_pio_mode;
469 hwif->set_dma_mode = &pdcnew_set_mode; 449 hwif->set_dma_mode = &pdcnew_set_dma_mode;
470 450
471 hwif->quirkproc = &pdcnew_quirkproc; 451 hwif->quirkproc = &pdcnew_quirkproc;
472 hwif->resetproc = &pdcnew_reset; 452 hwif->resetproc = &pdcnew_reset;
diff --git a/drivers/ide/pci/pdc202xx_old.c b/drivers/ide/pci/pdc202xx_old.c
index e09742e2ba59..67b2781e2213 100644
--- a/drivers/ide/pci/pdc202xx_old.c
+++ b/drivers/ide/pci/pdc202xx_old.c
@@ -162,7 +162,7 @@ static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
162 */ 162 */
163static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) 163static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
164{ 164{
165 unsigned long clock_reg = hwif->dma_master + 0x11; 165 unsigned long clock_reg = hwif->extra_base + 0x01;
166 u8 clock = inb(clock_reg); 166 u8 clock = inb(clock_reg);
167 167
168 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); 168 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
@@ -170,7 +170,7 @@ static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
170 170
171static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) 171static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
172{ 172{
173 unsigned long clock_reg = hwif->dma_master + 0x11; 173 unsigned long clock_reg = hwif->extra_base + 0x01;
174 u8 clock = inb(clock_reg); 174 u8 clock = inb(clock_reg);
175 175
176 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); 176 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
@@ -193,7 +193,7 @@ static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
193 if (drive->media != ide_disk || drive->addressing == 1) { 193 if (drive->media != ide_disk || drive->addressing == 1) {
194 struct request *rq = HWGROUP(drive)->rq; 194 struct request *rq = HWGROUP(drive)->rq;
195 ide_hwif_t *hwif = HWIF(drive); 195 ide_hwif_t *hwif = HWIF(drive);
196 unsigned long high_16 = hwif->dma_master; 196 unsigned long high_16 = hwif->extra_base - 16;
197 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 197 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
198 u32 word_count = 0; 198 u32 word_count = 0;
199 u8 clock = inb(high_16 + 0x11); 199 u8 clock = inb(high_16 + 0x11);
@@ -212,7 +212,7 @@ static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
212{ 212{
213 if (drive->media != ide_disk || drive->addressing == 1) { 213 if (drive->media != ide_disk || drive->addressing == 1) {
214 ide_hwif_t *hwif = HWIF(drive); 214 ide_hwif_t *hwif = HWIF(drive);
215 unsigned long high_16 = hwif->dma_master; 215 unsigned long high_16 = hwif->extra_base - 16;
216 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); 216 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
217 u8 clock = 0; 217 u8 clock = 0;
218 218
@@ -228,7 +228,7 @@ static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
228static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive) 228static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
229{ 229{
230 ide_hwif_t *hwif = HWIF(drive); 230 ide_hwif_t *hwif = HWIF(drive);
231 unsigned long high_16 = hwif->dma_master; 231 unsigned long high_16 = hwif->extra_base - 16;
232 u8 dma_stat = inb(hwif->dma_status); 232 u8 dma_stat = inb(hwif->dma_status);
233 u8 sc1d = inb(high_16 + 0x001d); 233 u8 sc1d = inb(high_16 + 0x001d);
234 234
@@ -271,7 +271,7 @@ static void pdc202xx_dma_timeout(ide_drive_t *drive)
271 271
272static void pdc202xx_reset_host (ide_hwif_t *hwif) 272static void pdc202xx_reset_host (ide_hwif_t *hwif)
273{ 273{
274 unsigned long high_16 = hwif->dma_master; 274 unsigned long high_16 = hwif->extra_base - 16;
275 u8 udma_speed_flag = inb(high_16 | 0x001f); 275 u8 udma_speed_flag = inb(high_16 | 0x001f);
276 276
277 outb(udma_speed_flag | 0x10, high_16 | 0x001f); 277 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
@@ -375,6 +375,11 @@ static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
375 } 375 }
376} 376}
377 377
378#define IDE_HFLAGS_PDC202XX \
379 (IDE_HFLAG_ERROR_STOPS_FIFO | \
380 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
381 IDE_HFLAG_OFF_BOARD)
382
378#define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \ 383#define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
379 { \ 384 { \
380 .name = name_str, \ 385 .name = name_str, \
@@ -382,9 +387,7 @@ static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
382 .init_hwif = init_hwif_pdc202xx, \ 387 .init_hwif = init_hwif_pdc202xx, \
383 .init_dma = init_dma_pdc202xx, \ 388 .init_dma = init_dma_pdc202xx, \
384 .extra = 48, \ 389 .extra = 48, \
385 .host_flags = IDE_HFLAG_ERROR_STOPS_FIFO | \ 390 .host_flags = IDE_HFLAGS_PDC202XX | extra_flags, \
386 extra_flags | \
387 IDE_HFLAG_OFF_BOARD, \
388 .pio_mask = ATA_PIO4, \ 391 .pio_mask = ATA_PIO4, \
389 .mwdma_mask = ATA_MWDMA2, \ 392 .mwdma_mask = ATA_MWDMA2, \
390 .udma_mask = udma, \ 393 .udma_mask = udma, \
@@ -397,8 +400,7 @@ static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
397 .init_hwif = init_hwif_pdc202xx, 400 .init_hwif = init_hwif_pdc202xx,
398 .init_dma = init_dma_pdc202xx, 401 .init_dma = init_dma_pdc202xx,
399 .extra = 16, 402 .extra = 16,
400 .host_flags = IDE_HFLAG_ERROR_STOPS_FIFO | 403 .host_flags = IDE_HFLAGS_PDC202XX,
401 IDE_HFLAG_OFF_BOARD,
402 .pio_mask = ATA_PIO4, 404 .pio_mask = ATA_PIO4,
403 .mwdma_mask = ATA_MWDMA2, 405 .mwdma_mask = ATA_MWDMA2,
404 .udma_mask = ATA_UDMA2, 406 .udma_mask = ATA_UDMA2,
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
index 27781d294cea..bd6d3f77d30c 100644
--- a/drivers/ide/pci/piix.c
+++ b/drivers/ide/pci/piix.c
@@ -203,20 +203,11 @@ static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
203 pci_read_config_byte(dev, 0x54, &reg54); 203 pci_read_config_byte(dev, 0x54, &reg54);
204 pci_read_config_byte(dev, 0x55, &reg55); 204 pci_read_config_byte(dev, 0x55, &reg55);
205 205
206 switch(speed) {
207 case XFER_UDMA_4:
208 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
209 case XFER_UDMA_5:
210 case XFER_UDMA_3:
211 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
212 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
213 case XFER_MW_DMA_2:
214 case XFER_MW_DMA_1:
215 case XFER_SW_DMA_2: break;
216 default: return;
217 }
218
219 if (speed >= XFER_UDMA_0) { 206 if (speed >= XFER_UDMA_0) {
207 u8 udma = speed - XFER_UDMA_0;
208
209 u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
210
220 if (!(reg48 & u_flag)) 211 if (!(reg48 & u_flag))
221 pci_write_config_byte(dev, 0x48, reg48 | u_flag); 212 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
222 if (speed == XFER_UDMA_5) { 213 if (speed == XFER_UDMA_5) {
diff --git a/drivers/ide/pci/sc1200.c b/drivers/ide/pci/sc1200.c
index 707d5ff66b03..fef20bd4aa78 100644
--- a/drivers/ide/pci/sc1200.c
+++ b/drivers/ide/pci/sc1200.c
@@ -135,59 +135,29 @@ static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
135 unsigned short pci_clock; 135 unsigned short pci_clock;
136 unsigned int basereg = hwif->channel ? 0x50 : 0x40; 136 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
137 137
138 static const u32 udma_timing[3][3] = {
139 { 0x00921250, 0x00911140, 0x00911030 },
140 { 0x00932470, 0x00922260, 0x00922140 },
141 { 0x009436a1, 0x00933481, 0x00923261 },
142 };
143
144 static const u32 mwdma_timing[3][3] = {
145 { 0x00077771, 0x00012121, 0x00002020 },
146 { 0x000bbbb2, 0x00024241, 0x00013131 },
147 { 0x000ffff3, 0x00035352, 0x00015151 },
148 };
149
138 pci_clock = sc1200_get_pci_clock(); 150 pci_clock = sc1200_get_pci_clock();
139 151
140 /* 152 /*
141 * Note that each DMA mode has several timings associated with it. 153 * Note that each DMA mode has several timings associated with it.
142 * The correct timing depends on the fast PCI clock freq. 154 * The correct timing depends on the fast PCI clock freq.
143 */ 155 */
144 timings = 0; 156
145 switch (mode) { 157 if (mode >= XFER_UDMA_0)
146 case XFER_UDMA_0: 158 timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
147 switch (pci_clock) { 159 else
148 case PCI_CLK_33: timings = 0x00921250; break; 160 timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
149 case PCI_CLK_48: timings = 0x00932470; break;
150 case PCI_CLK_66: timings = 0x009436a1; break;
151 }
152 break;
153 case XFER_UDMA_1:
154 switch (pci_clock) {
155 case PCI_CLK_33: timings = 0x00911140; break;
156 case PCI_CLK_48: timings = 0x00922260; break;
157 case PCI_CLK_66: timings = 0x00933481; break;
158 }
159 break;
160 case XFER_UDMA_2:
161 switch (pci_clock) {
162 case PCI_CLK_33: timings = 0x00911030; break;
163 case PCI_CLK_48: timings = 0x00922140; break;
164 case PCI_CLK_66: timings = 0x00923261; break;
165 }
166 break;
167 case XFER_MW_DMA_0:
168 switch (pci_clock) {
169 case PCI_CLK_33: timings = 0x00077771; break;
170 case PCI_CLK_48: timings = 0x000bbbb2; break;
171 case PCI_CLK_66: timings = 0x000ffff3; break;
172 }
173 break;
174 case XFER_MW_DMA_1:
175 switch (pci_clock) {
176 case PCI_CLK_33: timings = 0x00012121; break;
177 case PCI_CLK_48: timings = 0x00024241; break;
178 case PCI_CLK_66: timings = 0x00035352; break;
179 }
180 break;
181 case XFER_MW_DMA_2:
182 switch (pci_clock) {
183 case PCI_CLK_33: timings = 0x00002020; break;
184 case PCI_CLK_48: timings = 0x00013131; break;
185 case PCI_CLK_66: timings = 0x00015151; break;
186 }
187 break;
188 default:
189 return;
190 }
191 161
192 if (unit == 0) { /* are we configuring drive0? */ 162 if (unit == 0) { /* are we configuring drive0? */
193 pci_read_config_dword(hwif->pci_dev, basereg+4, &reg); 163 pci_read_config_dword(hwif->pci_dev, basereg+4, &reg);
@@ -260,66 +230,39 @@ static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
260} 230}
261 231
262#ifdef CONFIG_PM 232#ifdef CONFIG_PM
263static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev) 233struct sc1200_saved_state {
264{ 234 u32 regs[8];
265 int h; 235};
266
267 for (h = 0; h < MAX_HWIFS; h++) {
268 ide_hwif_t *hwif = &ide_hwifs[h];
269 if (prev) {
270 if (hwif == prev)
271 prev = NULL; // found previous, now look for next match
272 } else {
273 if (hwif && hwif->pci_dev == dev)
274 return hwif; // found next match
275 }
276 }
277 return NULL; // not found
278}
279
280typedef struct sc1200_saved_state_s {
281 __u32 regs[4];
282} sc1200_saved_state_t;
283
284 236
285static int sc1200_suspend (struct pci_dev *dev, pm_message_t state) 237static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
286{ 238{
287 ide_hwif_t *hwif = NULL;
288
289 printk("SC1200: suspend(%u)\n", state.event); 239 printk("SC1200: suspend(%u)\n", state.event);
290 240
241 /*
242 * we only save state when going from full power to less
243 */
291 if (state.event == PM_EVENT_ON) { 244 if (state.event == PM_EVENT_ON) {
292 // we only save state when going from full power to less 245 struct sc1200_saved_state *ss;
293 246 unsigned int r;
294 // 247
295 // Loop over all interfaces that are part of this PCI device: 248 /*
296 // 249 * allocate a permanent save area, if not already allocated
297 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { 250 */
298 sc1200_saved_state_t *ss; 251 ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
299 unsigned int basereg, r; 252 if (ss == NULL) {
300 // 253 ss = kmalloc(sizeof(*ss), GFP_KERNEL);
301 // allocate a permanent save area, if not already allocated 254 if (ss == NULL)
302 // 255 return -ENOMEM;
303 ss = (sc1200_saved_state_t *)hwif->config_data; 256 pci_set_drvdata(dev, ss);
304 if (ss == NULL) {
305 ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
306 if (ss == NULL)
307 return -ENOMEM;
308 hwif->config_data = (unsigned long)ss;
309 }
310 ss = (sc1200_saved_state_t *)hwif->config_data;
311 //
312 // Save timing registers: this may be unnecessary if
313 // BIOS also does it
314 //
315 basereg = hwif->channel ? 0x50 : 0x40;
316 for (r = 0; r < 4; ++r) {
317 pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
318 }
319 } 257 }
320 }
321 258
322 /* You don't need to iterate over disks -- sysfs should have done that for you already */ 259 /*
260 * save timing registers
261 * (this may be unnecessary if BIOS also does it)
262 */
263 for (r = 0; r < 8; r++)
264 pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
265 }
323 266
324 pci_disable_device(dev); 267 pci_disable_device(dev);
325 pci_set_power_state(dev, pci_choose_state(dev, state)); 268 pci_set_power_state(dev, pci_choose_state(dev, state));
@@ -328,30 +271,25 @@ static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
328 271
329static int sc1200_resume (struct pci_dev *dev) 272static int sc1200_resume (struct pci_dev *dev)
330{ 273{
331 ide_hwif_t *hwif = NULL; 274 struct sc1200_saved_state *ss;
332 int i; 275 unsigned int r;
276 int i;
333 277
334 i = pci_enable_device(dev); 278 i = pci_enable_device(dev);
335 if (i) 279 if (i)
336 return i; 280 return i;
337 281
338 // 282 ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
339 // loop over all interfaces that are part of this pci device: 283
340 // 284 /*
341 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { 285 * restore timing registers
342 unsigned int basereg, r; 286 * (this may be unnecessary if BIOS also does it)
343 sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data; 287 */
344 288 if (ss) {
345 // 289 for (r = 0; r < 8; r++)
346 // Restore timing registers: this may be unnecessary if BIOS also does it 290 pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
347 //
348 basereg = hwif->channel ? 0x50 : 0x40;
349 if (ss != NULL) {
350 for (r = 0; r < 4; ++r) {
351 pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
352 }
353 }
354 } 291 }
292
355 return 0; 293 return 0;
356} 294}
357#endif 295#endif
diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c
index ebb7132b9b84..24a85bbcd2a6 100644
--- a/drivers/ide/pci/scc_pata.c
+++ b/drivers/ide/pci/scc_pata.c
@@ -254,19 +254,7 @@ static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
254 offset = 0; /* 100MHz */ 254 offset = 0; /* 100MHz */
255 } 255 }
256 256
257 switch (speed) { 257 idx = speed - XFER_UDMA_0;
258 case XFER_UDMA_6:
259 case XFER_UDMA_5:
260 case XFER_UDMA_4:
261 case XFER_UDMA_3:
262 case XFER_UDMA_2:
263 case XFER_UDMA_1:
264 case XFER_UDMA_0:
265 idx = speed - XFER_UDMA_0;
266 break;
267 default:
268 return;
269 }
270 258
271 jcactsel = JCACTSELtbl[offset][idx]; 259 jcactsel = JCACTSELtbl[offset][idx];
272 if (is_slave) { 260 if (is_slave) {
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c
index a7280311357b..e9bd269547bb 100644
--- a/drivers/ide/pci/serverworks.c
+++ b/drivers/ide/pci/serverworks.c
@@ -366,12 +366,17 @@ static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
366 } 366 }
367} 367}
368 368
369#define IDE_HFLAGS_SVWKS \
370 (IDE_HFLAG_LEGACY_IRQS | \
371 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
372 IDE_HFLAG_BOOTABLE)
373
369static const struct ide_port_info serverworks_chipsets[] __devinitdata = { 374static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
370 { /* 0 */ 375 { /* 0 */
371 .name = "SvrWks OSB4", 376 .name = "SvrWks OSB4",
372 .init_chipset = init_chipset_svwks, 377 .init_chipset = init_chipset_svwks,
373 .init_hwif = init_hwif_svwks, 378 .init_hwif = init_hwif_svwks,
374 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE, 379 .host_flags = IDE_HFLAGS_SVWKS,
375 .pio_mask = ATA_PIO4, 380 .pio_mask = ATA_PIO4,
376 .mwdma_mask = ATA_MWDMA2, 381 .mwdma_mask = ATA_MWDMA2,
377 .udma_mask = 0x00, /* UDMA is problematic on OSB4 */ 382 .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
@@ -379,7 +384,7 @@ static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
379 .name = "SvrWks CSB5", 384 .name = "SvrWks CSB5",
380 .init_chipset = init_chipset_svwks, 385 .init_chipset = init_chipset_svwks,
381 .init_hwif = init_hwif_svwks, 386 .init_hwif = init_hwif_svwks,
382 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE, 387 .host_flags = IDE_HFLAGS_SVWKS,
383 .pio_mask = ATA_PIO4, 388 .pio_mask = ATA_PIO4,
384 .mwdma_mask = ATA_MWDMA2, 389 .mwdma_mask = ATA_MWDMA2,
385 .udma_mask = ATA_UDMA5, 390 .udma_mask = ATA_UDMA5,
@@ -387,7 +392,7 @@ static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
387 .name = "SvrWks CSB6", 392 .name = "SvrWks CSB6",
388 .init_chipset = init_chipset_svwks, 393 .init_chipset = init_chipset_svwks,
389 .init_hwif = init_hwif_svwks, 394 .init_hwif = init_hwif_svwks,
390 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE, 395 .host_flags = IDE_HFLAGS_SVWKS,
391 .pio_mask = ATA_PIO4, 396 .pio_mask = ATA_PIO4,
392 .mwdma_mask = ATA_MWDMA2, 397 .mwdma_mask = ATA_MWDMA2,
393 .udma_mask = ATA_UDMA5, 398 .udma_mask = ATA_UDMA5,
@@ -395,8 +400,7 @@ static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
395 .name = "SvrWks CSB6", 400 .name = "SvrWks CSB6",
396 .init_chipset = init_chipset_svwks, 401 .init_chipset = init_chipset_svwks,
397 .init_hwif = init_hwif_svwks, 402 .init_hwif = init_hwif_svwks,
398 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE | 403 .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
399 IDE_HFLAG_BOOTABLE,
400 .pio_mask = ATA_PIO4, 404 .pio_mask = ATA_PIO4,
401 .mwdma_mask = ATA_MWDMA2, 405 .mwdma_mask = ATA_MWDMA2,
402 .udma_mask = ATA_UDMA5, 406 .udma_mask = ATA_UDMA5,
@@ -404,8 +408,7 @@ static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
404 .name = "SvrWks HT1000", 408 .name = "SvrWks HT1000",
405 .init_chipset = init_chipset_svwks, 409 .init_chipset = init_chipset_svwks,
406 .init_hwif = init_hwif_svwks, 410 .init_hwif = init_hwif_svwks,
407 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_SINGLE | 411 .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
408 IDE_HFLAG_BOOTABLE,
409 .pio_mask = ATA_PIO4, 412 .pio_mask = ATA_PIO4,
410 .mwdma_mask = ATA_MWDMA2, 413 .mwdma_mask = ATA_MWDMA2,
411 .udma_mask = ATA_UDMA5, 414 .udma_mask = ATA_UDMA5,
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
index de820aa58cd0..7e9dade5648d 100644
--- a/drivers/ide/pci/sgiioc4.c
+++ b/drivers/ide/pci/sgiioc4.c
@@ -582,7 +582,6 @@ ide_init_sgiioc4(ide_hwif_t * hwif)
582 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */ 582 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
583 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine, 583 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
584 clear interrupts */ 584 clear interrupts */
585 hwif->intrproc = NULL; /* Enable or Disable interrupt from drive */
586 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */ 585 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
587 hwif->quirkproc = NULL; 586 hwif->quirkproc = NULL;
588 hwif->busproc = NULL; 587 hwif->busproc = NULL;
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
index 5709c252543b..7b45eaf5afd9 100644
--- a/drivers/ide/pci/siimage.c
+++ b/drivers/ide/pci/siimage.c
@@ -278,27 +278,14 @@ static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
278 278
279 scsc = is_sata(hwif) ? 1 : scsc; 279 scsc = is_sata(hwif) ? 1 : scsc;
280 280
281 switch(speed) { 281 if (speed >= XFER_UDMA_0) {
282 case XFER_MW_DMA_2: 282 multi = dma[2];
283 case XFER_MW_DMA_1: 283 ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] :
284 case XFER_MW_DMA_0: 284 ultra5[speed - XFER_UDMA_0]);
285 multi = dma[speed - XFER_MW_DMA_0]; 285 mode |= (unit ? 0x30 : 0x03);
286 mode |= ((unit) ? 0x20 : 0x02); 286 } else {
287 break; 287 multi = dma[speed - XFER_MW_DMA_0];
288 case XFER_UDMA_6: 288 mode |= (unit ? 0x20 : 0x02);
289 case XFER_UDMA_5:
290 case XFER_UDMA_4:
291 case XFER_UDMA_3:
292 case XFER_UDMA_2:
293 case XFER_UDMA_1:
294 case XFER_UDMA_0:
295 multi = dma[2];
296 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
297 (ultra5[speed - XFER_UDMA_0]));
298 mode |= ((unit) ? 0x30 : 0x03);
299 break;
300 default:
301 return;
302 } 289 }
303 290
304 if (hwif->mmio) { 291 if (hwif->mmio) {
diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c
index d90b42917775..85d36996e6af 100644
--- a/drivers/ide/pci/sis5513.c
+++ b/drivers/ide/pci/sis5513.c
@@ -305,59 +305,56 @@ static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
305 sis_program_timings(drive, XFER_PIO_0 + pio); 305 sis_program_timings(drive, XFER_PIO_0 + pio);
306} 306}
307 307
308static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) 308static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
309{ 309{
310 ide_hwif_t *hwif = HWIF(drive); 310 struct pci_dev *dev = drive->hwif->pci_dev;
311 struct pci_dev *dev = hwif->pci_dev; 311 u32 regdw = 0;
312 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
312 313
313 /* Config chip for mode */ 314 pci_read_config_dword(dev, drive_pci, &regdw);
314 switch(speed) { 315
315 case XFER_UDMA_6: 316 regdw |= 0x04;
316 case XFER_UDMA_5: 317 regdw &= 0xfffff00f;
317 case XFER_UDMA_4: 318 /* check if ATA133 enable */
318 case XFER_UDMA_3: 319 clk = (regdw & 0x08) ? ATA_133 : ATA_100;
319 case XFER_UDMA_2: 320 idx = mode - XFER_UDMA_0;
320 case XFER_UDMA_1: 321 regdw |= cycle_time_value[clk][idx] << 4;
321 case XFER_UDMA_0: 322 regdw |= cvs_time_value[clk][idx] << 8;
322 if (chipset_family >= ATA_133) { 323
323 u32 regdw = 0; 324 pci_write_config_dword(dev, drive_pci, regdw);
324 u8 drive_pci = sis_ata133_get_base(drive); 325}
325 326
326 pci_read_config_dword(dev, drive_pci, &regdw); 327static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
327 regdw |= 0x04; 328{
328 regdw &= 0xfffff00f; 329 struct pci_dev *dev = drive->hwif->pci_dev;
329 /* check if ATA133 enable */ 330 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
330 if (regdw & 0x08) { 331
331 regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4; 332 pci_read_config_byte(dev, drive_pci + 1, &reg);
332 regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8; 333
333 } else { 334 /* force the UDMA bit on if we want to use UDMA */
334 regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4; 335 reg |= 0x80;
335 regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8; 336 /* clean reg cycle time bits */
336 } 337 reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
337 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw); 338 /* set reg cycle time bits */
338 } else { 339 reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
339 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0; 340
340 341 pci_write_config_byte(dev, drive_pci + 1, reg);
341 pci_read_config_byte(dev, drive_pci+1, &reg); 342}
342 /* Force the UDMA bit on if we want to use UDMA */ 343
343 reg |= 0x80; 344static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
344 /* clean reg cycle time bits */ 345{
345 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family])) 346 if (chipset_family >= ATA_133) /* ATA_133 */
346 << cycle_time_offset[chipset_family]); 347 sis_ata133_program_udma_timings(drive, mode);
347 /* set reg cycle time bits */ 348 else /* ATA_33/66/100a/100/133a */
348 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0] 349 sis_ata33_program_udma_timings(drive, mode);
349 << cycle_time_offset[chipset_family]; 350}
350 pci_write_config_byte(dev, drive_pci+1, reg); 351
351 } 352static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
352 break; 353{
353 case XFER_MW_DMA_2: 354 if (speed >= XFER_UDMA_0)
354 case XFER_MW_DMA_1: 355 sis_program_udma_timings(drive, speed);
355 case XFER_MW_DMA_0: 356 else
356 sis_program_timings(drive, speed); 357 sis_program_timings(drive, speed);
357 break;
358 default:
359 break;
360 }
361} 358}
362 359
363static u8 sis5513_ata133_udma_filter(ide_drive_t *drive) 360static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c
index 147d783f7529..069f104fdcea 100644
--- a/drivers/ide/pci/sl82c105.c
+++ b/drivers/ide/pci/sl82c105.c
@@ -115,32 +115,24 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
115 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", 115 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
116 drive->name, ide_xfer_verbose(speed))); 116 drive->name, ide_xfer_verbose(speed)));
117 117
118 switch (speed) { 118 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
119 case XFER_MW_DMA_2:
120 case XFER_MW_DMA_1:
121 case XFER_MW_DMA_0:
122 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
123 119
124 /* 120 /*
125 * Store the DMA timings so that we can actually program 121 * Store the DMA timings so that we can actually program
126 * them when DMA will be turned on... 122 * them when DMA will be turned on...
127 */ 123 */
128 drive->drive_data &= 0x0000ffff; 124 drive->drive_data &= 0x0000ffff;
129 drive->drive_data |= (unsigned long)drv_ctrl << 16; 125 drive->drive_data |= (unsigned long)drv_ctrl << 16;
130 126
131 /* 127 /*
132 * If we are already using DMA, we just reprogram 128 * If we are already using DMA, we just reprogram
133 * the drive control register. 129 * the drive control register.
134 */ 130 */
135 if (drive->using_dma) { 131 if (drive->using_dma) {
136 struct pci_dev *dev = HWIF(drive)->pci_dev; 132 struct pci_dev *dev = HWIF(drive)->pci_dev;
137 int reg = 0x44 + drive->dn * 4; 133 int reg = 0x44 + drive->dn * 4;
138 134
139 pci_write_config_word(dev, reg, drv_ctrl); 135 pci_write_config_word(dev, reg, drv_ctrl);
140 }
141 break;
142 default:
143 return;
144 } 136 }
145} 137}
146 138
diff --git a/drivers/ide/pci/slc90e66.c b/drivers/ide/pci/slc90e66.c
index eb4445b229ed..dbbb46819a2d 100644
--- a/drivers/ide/pci/slc90e66.c
+++ b/drivers/ide/pci/slc90e66.c
@@ -91,19 +91,9 @@ static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
91 pci_read_config_word(dev, 0x48, &reg48); 91 pci_read_config_word(dev, 0x48, &reg48);
92 pci_read_config_word(dev, 0x4a, &reg4a); 92 pci_read_config_word(dev, 0x4a, &reg4a);
93 93
94 switch(speed) {
95 case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
96 case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
97 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
98 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
99 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
100 case XFER_MW_DMA_2:
101 case XFER_MW_DMA_1:
102 case XFER_SW_DMA_2: break;
103 default: return;
104 }
105
106 if (speed >= XFER_UDMA_0) { 94 if (speed >= XFER_UDMA_0) {
95 u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
96
107 if (!(reg48 & u_flag)) 97 if (!(reg48 & u_flag))
108 pci_write_config_word(dev, 0x48, reg48|u_flag); 98 pci_write_config_word(dev, 0x48, reg48|u_flag);
109 /* FIXME: (reg4a & a_speed) ? */ 99 /* FIXME: (reg4a & a_speed) ? */
diff --git a/drivers/ide/pci/tc86c001.c b/drivers/ide/pci/tc86c001.c
index a66ebd14664e..e1faf6c2fe16 100644
--- a/drivers/ide/pci/tc86c001.c
+++ b/drivers/ide/pci/tc86c001.c
@@ -222,7 +222,8 @@ static const struct ide_port_info tc86c001_chipset __devinitdata = {
222 .name = "TC86C001", 222 .name = "TC86C001",
223 .init_chipset = init_chipset_tc86c001, 223 .init_chipset = init_chipset_tc86c001,
224 .init_hwif = init_hwif_tc86c001, 224 .init_hwif = init_hwif_tc86c001,
225 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD, 225 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD |
226 IDE_HFLAG_ABUSE_SET_DMA_MODE,
226 .pio_mask = ATA_PIO4, 227 .pio_mask = ATA_PIO4,
227 .mwdma_mask = ATA_MWDMA2, 228 .mwdma_mask = ATA_MWDMA2,
228 .udma_mask = ATA_UDMA4, 229 .udma_mask = ATA_UDMA4,
diff --git a/drivers/ide/pci/triflex.c b/drivers/ide/pci/triflex.c
index a227c41d23a3..ae52a96a1cf9 100644
--- a/drivers/ide/pci/triflex.c
+++ b/drivers/ide/pci/triflex.c
@@ -81,8 +81,6 @@ static void triflex_set_mode(ide_drive_t *drive, const u8 speed)
81 case XFER_PIO_0: 81 case XFER_PIO_0:
82 timing = 0x0808; 82 timing = 0x0808;
83 break; 83 break;
84 default:
85 return;
86 } 84 }
87 85
88 triflex_timings &= ~(0xFFFF << (16 * unit)); 86 triflex_timings &= ~(0xFFFF << (16 * unit));
diff --git a/drivers/ide/pci/via82cxxx.c b/drivers/ide/pci/via82cxxx.c
index a0d3c16b68ec..4b32c90f4896 100644
--- a/drivers/ide/pci/via82cxxx.c
+++ b/drivers/ide/pci/via82cxxx.c
@@ -439,6 +439,7 @@ static const struct ide_port_info via82cxxx_chipset __devinitdata = {
439 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, 439 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
440 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | 440 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
441 IDE_HFLAG_PIO_NO_DOWNGRADE | 441 IDE_HFLAG_PIO_NO_DOWNGRADE |
442 IDE_HFLAG_ABUSE_SET_DMA_MODE |
442 IDE_HFLAG_POST_SET_MODE | 443 IDE_HFLAG_POST_SET_MODE |
443 IDE_HFLAG_IO_32BIT | 444 IDE_HFLAG_IO_32BIT |
444 IDE_HFLAG_BOOTABLE, 445 IDE_HFLAG_BOOTABLE,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 19:50:00 -0500